ADS5296A_技术文档

ADS5296A

www.ti.com.cn

ZHCSBT3 –OCTOBER 2013

10 位，200 每秒百万次采样 (MSPS) 和 12 位，80MSPS， 8 通道

模数转换器

查询样片: ADS5296A

1

特性

描述

2

•

可配置的运转模式：

ADS5296A 是一款低功耗，12 位，8 通道，模数转换

器 (ADC)，其采样速率高达 80MSPS。然而，此器件

也可被配置成运行为一个 4 通道 ADC，通过交错两个

ADC 通道的数据运行在 2 倍采样速率上。在交错模式

下，此器件接受一个双倍频率输入时钟。每对中的

ADC 在 2 倍输入时钟的交替上升边沿上转换一个常见

模拟输入信号。此器件能够被配置为一个采样速率高

达 200MSPS 的 10 位，4 通道 ADC，或者一个采样

速率高达 160MSPS 的 12 位，4 通道 ADC。

–

10 位， 200MSPS，4 通道模数转换器 (ADC)

12 位， 160MSPS，4 通道 ADC

10 位， 100MSPS，8 通道 ADC

12 位， 80MSPS，8 通道 ADC

•

针对低功耗而设计：

–

80MSPS 时，每通道为 65mW

（12 位，8 通道）

–

200MSPS 时，每通道为 150mW

（10 位，4 通道）

交错对内的每个 ADC 的数据在一条最大数据速率高达

1Gbps（100MSPS 上 10 位）的 LVDS 对上以串行格

式输出。当交错被禁用时，ADS5296A 可运行为一个

采样速率高达 100MSPS 的 8 通道，10 位器件。

•

12 位，80MSPS：

信噪比 (SNR)：70.3dBFS

10 位，200MSPS：

–

信噪比 (SNR)：61.3dBFS

系统中常用的几种数字功能也包含在器件中。这些功

能包括一个低频噪声抑制 (LFNS) 模式，数字滤波选项

和 LVDS 输出引脚与模拟输入通道的可编程映射。

交错杂散信号：90MHz 时大于 60dB

•

串行低压差分信令 (LVDS) 单线制接口：

–

每导线高达 1000Mbps 数据速率的 10 倍串行

化

对于低输入频率应用，LFNS 模式可实现低频状态下的

噪声抑制并将直流附近 1MHz 波段内的信噪比 (SNR)

提升大约 3dB。数字滤波选项包括低通、高通和带通

数字滤波器，以及直流偏移消除滤波器。

–

每导线高达 960Mbps 数据速率的 12 倍串行化

数字处理块：

–

可编程有限脉冲响应 (FIR) 抽取滤波器和过采样

以大大减少谐波干扰

低功耗和小型封装内集成的多通道使得此器件成为高通

道数量数据采集系统的理想选择。此器件采用紧凑型

9mm x 9mm QFN-64 封装。 ADS5296A 额定运行温

度范围为 -40°C 至 +85°C。

可编程无限脉冲响应 (IIR) 高通滤波器以最大限

度地减少直流偏移

可编程数字增益：0dB 至 12dB

•

低频噪声抑制模式

ADC 输入通道与 LVDS 输出引脚间的可编程映射

通道均衡模式

多种 LVDS 测试模式以验证

现场可编程栅极阵列 (FPGA) 或接收器的数据捕捉

•

封装：9mm x 9mm 四方扁平无引线 (QFN)-64 封

装

应用范围

•

超声波成像

通信应用

多通道数据采集

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

English Data Sheet: SBAS631

ADS5296A

ZHCSBT3 –OCTOBER 2013

www.ti.com.cn

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION⁽¹⁾

PRODUCT

PACKAGE-LEAD

PACKAGE DESIGNATOR

SPECIFIED TEMPERATURE RANGE

ADS5296A

QFN-64

RGC

–40°C to +85°C

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the

device product folder at www.ti.com.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Over operating free-air temperature range, unless otherwise noted.

PARAMETER

AVDD

VALUE

–0.3 to 2.2

UNIT

V

Supply voltage range

Voltage between:

LVDD

–0.3 to 2.2

V

AGND and LGND

–0.3 to 0.3

V

AVDD to LVDD (when AVDD leads LVDD)

LVDD to AVDD (when LVDD leads AVDD)

IN_p, IN_n

0 to 2.2

V

0 to 2.2

V

–0.3 to min (2.2, AVDD + 0.3)

–0.3 to 3.6

V

RESET, SCLK, SDATA, CS, PD, SYNC

CLKP, CLKN⁽²⁾

V

Voltage applied to:

–0.3 to min (2.2, AVDD + 0.3)

–0.3 to min (2.2, LVDD + 0.3)

–40 to +85

V

Digital outputs

V

Operating free-air, T_A

°C

V

Temperature range

Operating junction, T_J

+105

Storage, T_stg

–55 to +150

Electrostatic discharge (ESD) rating

Human body model (HBM)

2000

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) When AVDD is turned off, TI recommends switching off the input clock (or ensuring the voltage on CLKP and CLKN is less than |0.3 V|.

This setting prevents the ESD protection diodes at the clock input pins from turning on.

THERMAL INFORMATION

ADS5296

THERMAL METRIC⁽¹⁾

QFN (RGC)

64 PINS

22.8

UNITS

θ_JA

Junction-to-ambient thermal resistance

θ_JCtop

θ_JB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

6.9

2.4

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.1

ψ_JB

2.4

θ_JCbot

0.2

(1) 有关传统和全新热度量的更多信息，请参阅 IC 封装热度量应用报告（文献号：ZHCA543）。

2

ADS5296A

www.ti.com.cn

ZHCSBT3 –OCTOBER 2013

RECOMMENDED OPERATING CONDITIONS

MIN

NOM

MAX

UNIT

SUPPLIES

AVDD

Analog supply voltage

Digital supply voltage

1.7

1.8

1.9

V

LVDD

ANALOG INPUTS

V_ID

Differential input voltage range

Input common-mode voltage

External reference mode, top

External reference mode, bottom

Common-mode voltage output

2

VCM ± 0.05

1.45

V_PP

V

REFT

V

REFB

0.45

V

VCM

0.95

V

CLOCK INPUT

4-channel, 10-bit ADC with interleaving

4-channel, 12-bit ADC with interleaving

8-channel, 10-bit ADC without interleaving

8-channel,12-bit ADC without interleaving

Sine-wave, ac-coupled

20

200

160

100

80

MSPS

V_PP

Input clock frequency (1 / t_C)

10

0.2

1.5

1.6

Input clock amplitude differential

(VCLKP – VCLKN)

LVPECL, ac-coupled

V_PP

LVDS, ac-coupled

0.7

V_PP

V_ILwith < 0.1-mA current sink

V_IH

< 0.3

> 1.5

50

V

Input clock CMOS single-ended

(VCLKP)

V

Input clock duty cycle

35

65

%

DIGITAL OUTPUTS

1x

ADCLKP and ADCLKN outputs (LVDS)

LCLKP and LCLKN outputs (LVDS)

MHz

(sample rate in MSPS)

6x or 5x

(sample rate in MSPS)

12x serialization

10x serialization

960

Mbps

Output data rate

1000

3

ADS5296A

ZHCSBT3 –OCTOBER 2013

www.ti.com.cn

ELECTRICAL CHARACTERISTICS: General

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS differential analog input,

unless otherwise noted.

Minimum and maximum values are across the full temperature range of T_MIN= –40°C to T_MAX= +85°C, AVDD = 1.8 V, and

LVDD = 1.8 V.

8-CHANNEL, 12-BIT

(Non-Interleaving)

4-CHANNEL, 10-BIT

(Interleaving)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

MIN

TYP MAX

UNIT

RESOLUTION

Resolution

ANALOG INPUTS

12

10

Bits

Differential input voltage range

(0-dB gain)

2.0

V_PP

Differential input resistance

Differential input capacitance

Analog input bandwidth

At dc

> 1

2.2

> 1

2.2

kΩ

pF

> 500

MHz

Analog input common-mode current

(per input pin)

1

µA/MSPS

VCM

Common-mode output voltage

VCM output current capability

0.95

5

0.95

5

V

mA

DYNAMIC ACCURACY

E_O

Offset error

–20

20

–20

20

mV

Resulting from internal

reference inaccuracy alone

E_GREF

E_GCHAN

–1.5

1.5

–1.5

1.5

%FS

Gain error

Of channel itself

0.5

%FS

E_GCHANtemperature coefficient

POWER SUPPLY

< 0.01

Δ%FS/°C

80 MSPS, non-interleaving

200 MSPS, interleaving

176

111

mA

IAVDD

ILVDD

AVDD

LVDD

Analog supply current

207

125

227

148

80 MSPS with 100-Ω external

termination

mA

Output buffer supply current

Analog power

200 MSPS with 100-Ω external

termination

80 MSPS, non-interleaving

200 MSPS, interleaving

317

199

mW

372 408.6

225 266.4

80 MSPS with 100-Ω external

termination

mW

Digital power

200 MSPS with 100-Ω external

termination

80 MSPS with 100-Ω external

termination

516

Total power

200 MSPS with 100-Ω external

termination

597

190

675

40

Global power-down

Standby power

40

mW

175

4

ADS5296A

www.ti.com.cn

ZHCSBT3 –OCTOBER 2013

ELECTRICAL CHARACTERISTICS: Dynamic Performance

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, maximum rated input clock frequency, 50% clock duty cycle,

and –1-dBFS differential analog input, unless otherwise noted.

Minimum and maximum values are across the full temperature range of T_MIN= –40°C to T_MAX= +85°C, AVDD = 1.8 V, and

LVDD = 1.8 V.

8-CHANNEL, 12-BIT

(Non-Interleaving)

4-CHANNEL, 10-BIT

(Interleaving)

PARAMETER

TEST CONDITIONS

MIN

TYP

70.3

70.1

68.7

70.1

69.7

67.9

11.3

83

MAX

MIN

TYP

61.3

61

MAX UNIT

dBFS

LSBs

dBc

f_IN= 5 MHz

f_IN= 30 MHz

f_IN= 90 MHz

f_IN= 5 MHz

f_IN= 30 MHz

f_IN= 90 MHz

f_IN= 5 MHz

f_IN= 30 MHz

f_IN= 90 MHz

f_IN= 5 MHz

f_IN= 30 MHz

f_IN= 90 MHz

f_IN= 5 MHz

f_IN= 30 MHz

f_IN= 90 MHz

f_IN= 5 MHz

f_IN= 30 MHz

f_IN= 90 MHz

f_IN= 5 MHz

f_IN= 30 MHz

f_IN= 90 MHz

66

59.9

SNR

Signal-to-noise ratio⁽¹⁾

60.3

61.3

60.8

59.8

9.8

83

Signal-to-noise and distortion

ratio

SINAD

ENOB Effective number of bits

73

71

73

75

70.5

67.5

70.5

Spurious-free dynamic

SFDR

80

79

dBc

range⁽¹⁾

76

72.5

81

dBc

81

dBc

THD

HD2

HD3

Total harmonic distortion

Second-harmonic distortion

Third-harmonic distortion

78

77.5

70

dBc

74

dBc

90

86

dBc

88

84

dBc

85

83

dBc

83

dBc

80

79

dBc

76

72.5

79

dBc

93

65

60

dBc

Worst spur

(other than second and third

92

74

dBc

(2)

harmonics)

90

71

dBc

Two-tone intermodulation

distortion

IMD

f₁= 8 MHz, f₂= 10 MHz, each tone at –7 dBFS

83

dBc

With a full-scale, 10-MHz

aggressor signal applied and

no input on victim channel

Adjacent channel

Far channel

86

95

dBc

Crosstalk

110

Recovery to < 1% of full-scale after a 6-dB input

overload

Clock

cycle

Overload recovery

1

AC power-supply rejection

ratio

For a 50-mV_PPsignal on AVDD supply, up to 10

MHz, no signal applied to analog inputs

PSRR

> 50

dB

DNL

INL

Differential nonlinearity

Integrated nonlinearity

f_IN= 5 MHz

–0.8

±0.3

±0.2

+0.95

±1.1

LSBs

(1) In the 4-channel interleaving mode, this parameter does not include interleaving spur. Spur is specified separately as part of the worst

spur parameter.

(2) In the 4-channel interleaving mode, worst spur includes interleaving spur. Also see Figure 44, which shows interleaving spur across

input frequency.

5

ADS5296A

ZHCSBT3 –OCTOBER 2013

www.ti.com.cn

DIGITAL CHARACTERISTICS

The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic

level '0' or '1'. AVDD = 1.8 V and DRVDD = 1.8 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUTS (RESET, SCLK, SDATA, CS, SYNC, PDN, INTERLEAVE_MUX)

All pins support 1.8-V and 3.3-V CMOS logic

levels

V_IH

V_IL

High-level input voltage

Low-level input voltage

1.3

V

All pins support 1.8-V and 3.3-V CMOS logic

levels

0.4

I_IH

I_IL

High-level input current

Low-level input current

CS, SDATA, SCLK⁽¹⁾

V_HIGH= 1.8 V

V_LOW= 0 V

6

µA

0.1

DIGITAL OUTPUTS (CMOS INTERFACE: SDOUT)

V_OH

V_OL

High-level output voltage

Low-level output voltage

AVDD – 0.1

V

0.1

DIGITAL OUTPUTS (LVDS INTERFACE: OUT1_p, OUT1_n to OUT8_p, OUT8_n, ADCLKp, ADCLKn, LCLKp, LCLKn)

V_ODH

V_ODL

V_OCM

High-level output differential voltage⁽²⁾

Low-level output differential voltage⁽²⁾

Output common-mode voltage

340

–560

0.93

560

–340

1.2

mV

(1) CS, SDATA, and SCLK have an internal 220-kΩ pull-down resistor.

(2) With an external 100-Ω termination.

6

ADS5296A

www.ti.com.cn

ZHCSBT3 –OCTOBER 2013

TIMING REQUIREMENTS⁽¹⁾

Typical values are at +25°C, AVDD = 1.8 V, LVDD = 1.8 V, input clock frequency = 200 MSPS, sine-wave input clock, C_LOAD

= 5 pF, and R_LOAD= 100 Ω, unless otherwise noted.

Minimum and maximum values are across the full temperature range of T_MIN= –40°C to T_MAX= +85°C, AVDD = 1.8 V, and

LVDD = 1.7 V to 1.9 V, with decimation filters DISABLED.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t_A

Aperture delay

4

ns

Aperture delay matching

Variation of aperture delay

Aperture jitter

Between any two channels of the same device

±200

ps

Between two devices at the same temperature and

AVDD supply

±1

ns

t_J

Sample uncertainty

300

6

fs rms

µs

Time to valid data after coming out of standby

Wake-up time

ADC latency⁽²⁾

Time to valid data after coming out of global power-

down mode

100

12

µs

Input clock

cycles

Interleaving disabled

Interleaving enabled

Input clock

cycles

24

10x SERIALIZATION

t_SUData setup time

t_H

Data valid to LCLKP zero-crossing

0.200

0.160

ns

Data hold time

LCLKP zero-crossing to data becoming invalid

Input clock rising edge crossover to output clock

rising edge crossover

t_PDI= (4 / 5)

× t_S+ t_DELAY

t_PDI

Clock propagation delay

Delay time

ns

t_DELAY

7.8

11.8

Between two devices at the same temperature and

LVDD supply

Variation of t_DELAY

±0.8

50

Duty cycle of differential clock

(LCLKP – LCLKN)

LVDS bit clock duty cycle

%

ACROSS ALL SERIALIZATION MODES

Rise time measured from –100 mV to +100 mV,

10 MSPS ≤ sampling frequency ≤ 100 MSPS

t_FALL

Data fall time

0.13

ns

Rise time measured from –100 mV to +100 mV,

10 MSPS ≤ sampling frequency ≤ 100 MSPS

t_RISE

Data rise time

Rise time measured from –100 mV to +100 mV,

10 MSPS ≤ sampling frequency ≤ 100 MSPS

t_CLKRISE

t_CLKFALL

Output clock rise time

Output clock fall time

Rise time measured from –100 mV to +100 mV,

10 MSPS ≤ sampling frequency ≤ 100 MSPS

(1) Timing parameters are ensured by design and characterization, but are not tested in production.

(2) At higher frequencies, t_PDIis greater than one clock period. Overall latency = ADC latency + 1.

7

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ZHCSBT3 –OCTOBER 2013

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Table 1. 12x Serialization with Decimation Filters Disabled⁽¹⁾⁽²⁾

t_PDI= (9 / 12) × t_S

+

t_DELAY

(Where t_DELAYis

specified as below,

ns)

INPUT CLOCK FREQUENCY (MHz)

NON-

SETUP TIME (ns)⁽³⁾

HOLD TIME (ns)⁽³⁾

INTERLEAVED

MODE

INTERLEAVED

OUTPUT DATA

RATE (Mbps)

MODE⁽⁴⁾

MIN

3.80

1.60

0.80

0.38

0.22

TYP

MAX

MIN

3.80

1.80

0.69

0.19

0.14

TYP

MAX

MIN

8

TYP

MAX

13

10

20

40

65

80

20

40

120

240

480

780

960

8

13

80

8

13

130

160

8

13

8

13

(1) Minimum and maximum values are across the full temperature range of T_MIN= –40°C to T_MAX= +85°C, AVDD = 1.8 V, and LVDD =

1.7 V to 1.9 V.

(2) All timing specifications are taken with default output clock and data delay settings (0 ps). Refer to the Programmable LVDS Output

Clock and Data Edges section in the Application Information for additional output clock and data delay options.

(3) When decimation filters are enabled, the minimum setup and minimum hold time further reduce by 100 ps compared to their values with

the filters disabled (at the same output data rate).

Example: At an 80-MHz input clock frequency, with decimation by 2 enabled, output data rate = 480 Mbps. At 480 Mbps, as per Table 1,

the setup time with the decimation disabled is 0.80 ns. Therefore, the set-up time with filter enabled is 100 ps lower (0.8 – 0.1 = 0.7).

Similarly, the hold time with filter enabled is 0.59 ns.

(4) Refer to the Interleaving Mode section in the Application Information for details on interleaving mode.

Table 2. 10x Serialization with Decimation Filters Disabled⁽¹⁾⁽²⁾

t_PDI= (8 / 10) × t_S+ t_DELAY

(Where t_DELAYis specified as

INPUT CLOCK FREQUENCY (MHz)

NON-

SETUP TIME (ns)⁽³⁾

HOLD TIME (ns)⁽³⁾

below, ns)

OUTPUT

DATA RATE

(Mbps)

INTERLEAVED

MODE

INTERLEAVED

MODE⁽⁴⁾

MIN

0.85

0.52

0.33

0.2

TYP MAX

MIN

1

TYP MAX

MIN

7.8

TYP

MAX

11.8

40

65

80

400

650

130

160

200

0.35

0.19

0.16

80

800

100

1000

(1) Minimum and maximum values are across the full temperature range of T_MIN= –40°C to T_MAX= +85°C, AVDD = 1.8 V, and LVDD =

1.7 V to 1.9 V.

(2) All timing specifications are taken with default output clock and data delay settings (0 ps). Refer to the Programmable LVDS Output

Clock and Data Edges section in the Application Information for additional output clock and data delay options.

(3) When decimation filters are enabled, the minimum setup and minimum hold time further reduce by 100 ps compared to their values with

the filters disabled (at the same output data rate).

Example: At an 80-MHz input clock frequency, with decimation by 2 enabled, output data rate = 400 Mbps. At 400 Mbps, as per Table 2,

the setup time with the decimation disabled is 0.85 ns. Therefore, the set-up time with filter enabled is 100 ps lower (0.85 – 0.10 = 0.75).

Similarly ,the hold time with filter enabled is 0.90 ns.

(4) Refer to the Interleaving Mode section in the Application Information for details on interleaving mode.

8

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ZHCSBT3 –OCTOBER 2013

Table 3. 14x Serialization with Decimation by two filter enabled (Data Rate = 0.5x)^(1)(2)(3)

OUTPUT

DATA

SETUP TIME (ns)

HOLD TIME (ns)

SAMPLING FREQUENCY

(MSPS)

RATE

(Mbps)

MAX

MIN

TYP

MAX

MIN

TYP

65

80

455

560

700

0.73

0.54

0.32

0.75

0.50

0.25

100

(1) Minimum and maximum values are across the full temperature range of T_MIN= –40°C to T_MAX= +85°C, AVDD = 1.8 V, and LVDD =

1.7 V to 1.9 V.

(2) All timing specifications are taken with default output clock and data delay settings (0 ps).

(3) Refer to the Programmable LVDS Output Clock and Data Edges section in the Application Information for additional output clock and

data delay options.

Table 4. 14x Serialization with Decimation by four filter enabled (Data Rate = 0.25x)^(1)(2)(3)

OUTPUT

DATA

SETUP TIME (ns)

HOLD TIME (ns)

SAMPLING FREQUENCY

(MSPS)

RATE

(Mbps)

MAX

MIN

TYP

MAX

MIN

TYP

65

80

227.5

280

1.7

1.3

0.9

1.9

1.45

1.1

100

350

(1) Minimum and maximum values are across the full temperature range of T_MIN= –40°C to T_MAX= +85°C, AVDD = 1.8 V, and LVDD =

1.7 V to 1.9 V.

(2) All timing specifications are taken with default output clock and data delay settings (0 ps).

(3) Refer to the Programmable LVDS Output Clock and Data Edges section in the Application Information for additional output clock and

data delay options.

(1)(2)(3)

Table 5. 14x Serialization with Decimation by eight filter enabled (Data Rate = 0.125x)

OUTPUT

DATA

SETUP TIME (ns)

HOLD TIME (ns)

SAMPLING FREQUENCY

(MSPS)

RATE

(Mbps)

MAX

MIN

TYP

MAX

MIN

TYP

65

80

113.75

140

3.8

3

3.8

3

100

175

2.2

(1) Minimum and maximum values are across the full temperature range of T_MIN= –40°C to T_MAX= +85°C, AVDD = 1.8 V, and LVDD =

1.7 V to 1.9 V.

(2) All timing specifications are taken with default output clock and data delay settings (0 ps).

(3) Refer to the Programmable LVDS Output Clock and Data Edges section in the Application Information for additional output clock and

data delay options.

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PARAMETRIC MEASUREMENT INFORMATION

Figure 1 shows a timing diagram of the LVDS output voltage levels.

OUTP

Logic 0

V_ODL= -350 mV⁽¹⁾

Logic 1

V_ODH= +350 mV⁽¹⁾

OUTN

V_OCM

GND

(1) With an external 100-Ω termination.

Figure 1. LVDS Output Voltage Levels

Figure 2 shows the latency timing diagram.

Sample

N + 11

Sample

N + 12

Sample

N + 13

Sample

N

Input Signal

t_A

CLKN

CLKP

Input Clock

Frequency = f_S

Latency = 12 Clocks

t_PDI

LCLKP

LCLKN

Bit Clock

Frequency = 6x f_S

OUTP

OUTN

Output Data

Rate = 12x f_S

D11 D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0 D11 D10

D9

D8

D7

D6

D5

D4

D1

D0

D3

D2

D11 D10 D9 D8

Sample N-1

Sample N

ADCLKN

ADCLKP

Frame Clock

Frequency = 1x f_S

Figure 2. Latency Timing Diagram

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ZHCSBT3 –OCTOBER 2013

PARAMETRIC MEASUREMENT INFORMATION (continued)

LVDS OUTPUT TIMING

Figure 3 shows the output timing described in the Timing Requirements table.

CLKN

Input

Clock

CLKP

t_PDI

ADCLKN

Frame

Clock

ADCLKP

t_SU

t_H

LCLKP

Bit

Clock

LCLKN

t_SU

t_H

t_SU

t_H

OUT1, OUT2,

OUT3, OUT4,

OUT5, OUT6,

OUT7, OUT8

Output

Data

Dn⁽¹⁾

Dn+1⁽¹⁾

(1) n = 0 to 11.

Figure 3. LVDS Output Timing

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ZHCSBT3 –OCTOBER 2013

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PIN DESCRIPTION

RGC PACKAGE

QFN-64

(Top View)

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

IN1_p

1

2

3

4

5

6

7

8

9

48 IN8_n

47 IN8_p

46 AGND

45 IN7_n

44 IN7_p

43 AGND

42 IN6_n

41 IN6_p

40 AGND

39 IN5_n

38 IN5_p

37 AGND

36 LGND

35 LVDD

34 OUT8_n

33 OUT8_p

IN1_n

AGND

IN2_p

IN2_n

AGND

IN3_p

IN3_n

AGND

Thermal Pad

IN4_p 10

IN4_n 11

LGND 12

PDN 13

LGND 14

OUT1_p 15

OUT1_n 16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

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ZHCSBT3 –OCTOBER 2013

PIN DESCRIPTIONS

NAME

ADCLKN

ADCLKP

AGND

AVDD

CLKN

NO.

FUNCTION⁽¹⁾

DESCRIPTION

24

DO

G

Differential LVDS frame clock, negative

Differential LVDS frame clock, positive

Analog ground pin

23

3, 6, 9, 37, 40, 43, 46

50, 57, 60

S

Analog supply pin, 1.8 V

59

58

61

AI

Differential clock input, negative

Differential clock input, positive

CLKP

AI

CS

DI

Serial enable chip select; active low digital input

Control input to select conversion of odd channels (1, 3, 5, and 7) or

even channels (2, 4, 6, and 8).

INTERLEAVE_MUX

56

DI

IN1_n

IN1_p

2

1

AI

Differential analog input for channel 1, negative

Differential analog input for channel 1, positive

Differential analog input for channel 2, negative

Differential analog input for channel 2, positive

Differential analog input for channel 3, negative

Differential analog input for channel 3, positive

Differential analog input for channel 4, negative

Differential analog input for channel 4, positive

Differential analog input for channel 5, negative

Differential analog input for channel 5, positive

Differential analog input for channel 6, negative

Differential analog input for channel 6, positive

Differential analog input for channel 7, negative

Differential analog input for channel 7, positive

Differential analog input for channel 8, negative

Differential analog input for channel 8, positive

LVDS differential bit clock output pins (6x), negative

LVDS differential bit clock output pins (6x), positive

Digital ground pin

IN2_n

5

AI

IN2_p

4

AI

IN3_n

8

AI

IN3_p

7

AI

IN4_n

11

10

39

38

42

41

45

44

48

47

26

25

12, 14, 36

35

51

16

15

18

17

20

19

22

21

28

27

30

29

32

31

34

33

13

AI

IN4_p

AI

IN5_n

AI

IN5_p

AI

IN6_n

AI

IN6_p

AI

IN7_n

AI

IN7_p

AI

IN8_n

AI

IN8_p

AI

LCLKN

LCLKP

LGND

DO

G

LVDD

S

Digital and I/O power supply, 1.8 V

NC

—

Do not connect

OUT1_n

OUT1_p

OUT2_n

OUT2_p

OUT3_n

OUT3_p

OUT4_n

OUT4_p

OUT5_n

OUT5_p

OUT6_n

OUT6_p

OUT7_n

OUT7_p

OUT8_n

OUT8_p

PDN

DO

DI

Channel 1 differential LVDS negative data output

Channel 1 differential LVDS positive data output

Channel 2 differential LVDS negative data output

Channel 2 differential LVDS positive data output

Channel 3 differential LVDS negative data output

Channel 3 differential LVDS positive data output

Channel 4 differential LVDS negative data output

Channel 4 differential LVDS positive data output

Channel 5 differential LVDS negative data output

Channel 5 differential LVDS positive data output

Channel 6 differential LVDS negative data output

Channel 6 differential LVDS positive data output

Channel 7 differential LVDS negative data output

Channel 7 differential LVDS positive data output

Channel 8 differential LVDS negative data output

Channel 8 differential LVDS positive data output

Power-down control input pin

(1) Pin functionality: AI = analog input; DI = digital input; DO = digital output; G = ground; and S = supply.

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PIN DESCRIPTIONS (continued)

NAME

NO.

FUNCTION⁽¹⁾

DESCRIPTION

Negative reference input and output.

Internal reference mode: Reference bottom voltage (0.45 V) is

output on this pin. A decoupling capacitor is not required on this pin.

External reference mode: Reference bottom voltage (0.45 V) must

be externally applied to this pin.

REFB

54

AI

Positive reference input and output.

Internal reference mode: Reference top voltage (1.45 V) is output

on this pin. A decoupling capacitor is not required on this pin.

External reference mode: Reference top voltage (1.45 V) must be

externally applied to this pin.

REFT

55

AI

RESET

SCLK

64

63

62

52

DI

Active high RESET input

Serial clock input

SDATA

SDOUT

DI

Serial data input

DO

Serial data output

Control input pin to synchronize test patterns and decimation filters

across devices

SYNC

VCM

49

53

DI

AI

Common-mode voltage output pin, 0.95 V.

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ZHCSBT3 –OCTOBER 2013

FUNCTIONAL BLOCK DIAGRAMS

IN1_p

IN1_n

12 BIT

12-Bit ADC

ADAC

Digital Processing

Block

Sampling

Circuit

OUT1_p

Serializer

OUT1_n

IN2_p

IN2_n

12 BIT

12-Bit ADC

ADAC

Digital Processing

Block

Sampling

Circuit

OUT2_p

OUT2_n

IN3_p

IN3_n

OUT3_p

OUT3_n

12 BIT

12-Bit ADC

ADAC

Digital Processing

Block

Sampling

Circuit

IN4_p

IN4_n

OUT4_p

OUT4_n

12 BIT

12-Bit ADC

ADAC

Digital Processing

Block

Sampling

Circuit

LCLKP

LCLKN

CLKP

CLKN

CLOCKGEN

PLL

ADCLKP

ADCLKN

SYNC

IN5_p

IN5_n

OUT5_p

OUT5_n

12 BIT

12-Bit ADC

ADAC

Digital Processing

Block

Sampling

Circuit

Serializer

IN6_p

IN6_n

12 BIT

12-Bit ADC

ADAC

Digital Processing

Block

Sampling

Circuit

OUT6_p

OUT6_n

IN7_p

IN7_n

OUT7_p

OUT7_n

12 BIT

12-Bit ADC

ADAC

Digital Processing

Block

Sampling

Circuit

IN8_p

IN8_n

OUT8_p

OUT8_n

12 BIT

12-Bit ADC

ADAC

Digital Processing

Block

Sampling

Circuit

Reference

Control Interface

Device

Figure 4. 10- and 12-Bit, 8-Channel ADC, Non-Interleaving Mode

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ZHCSBT3 –OCTOBER 2013

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OUT1_p

OUT1_n

10 BIT

12-Bit ADC

ADAC

Sampling

Circuit

Digital Processing Block

Serializer

IN1_p

IN1_n

IN2_p

IN2_n

OUT2_p

OUT2_n

10 BIT

12-Bit ADC

ADAC

Sampling

Circuit

OUT3_p

OUT3_n

10 BIT

12-Bit ADC

ADAC

Sampling

Circuit

IN3_p

IN3_n

IN4_p

IN4_n

OUT4_p

OUT4_n

10 BIT

Sampling

Circuit

12-Bit ADC

Digital Processing Block

ADAC

0

180

LCLKP

LCLKN

CLKP

CLKN

Divide-

by-2

CLOCKGEN

PLL

ADCLKP

ADCLKN

180

0

SYNC

OUT5_p

OUT5_n

10 BIT

12-Bit ADC

ADAC

Sampling

Circuit

Digital Processing Block

Serializer

IN5_p

IN5_n

IN6_p

IN6_n

10 BIT

12-Bit ADC

ADAC

Sampling

Circuit

OUT6_p

OUT6_n

10 BIT

12-Bit ADC

ADAC

OUT7_p

OUT7_n

Sampling

Circuit

IN7_p

IN7_n

IN8_p

IN8_n

10 BIT

12-Bit ADC

ADAC

OUT8_p

OUT8_n

Sampling

Circuit

Digital Processing Block

Reference

Control Interface

Device

Figure 5. 10- and 12-Bit, 4-Channel ADC, Interleaving Mode

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ZHCSBT3 –OCTOBER 2013

TYPICAL CHARACTERISTICS: General (8-Channel, 12-Bit, Non-Interleaving Mode)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, input clock frequency = 80 MSPS, 50% clock duty cycle, and

–1-dBFS differential analog input, unless otherwise noted.

0

−10

0

−10

SNR = 70.4 dBFS

SINAD = 70.2 dBFS

SFDR = 82.8 dBc

THD = 82.5 dBc

SNR = 70.3 dBFS

SINAD = 70.1 dBFS

SFDR = 82.1 dBc

THD = 81.7 dBc

−20

−30

−40

−50

−60

−70

−80

−90

−100

−110

−120

−130

−140

−100

−110

−120

−130

−140

0

10

20

30

40

0

10

20

30

40

Frequency (MHz)

G001

G002

Figure 6. FFT FOR 5-MHz INPUT SIGNAL

(Sample Rate = 80 MSPS)

Figure 7. FFT FOR 15-MHz INPUT SIGNAL

(Sample Rate = 80 MSPS)

0

−10

0

−10

SNR = 69.4 dBFS

SINAD = 68.8 dBFS

SFDR = 77.1 dBc

THD = 76.3 dBc

SNR = 70.7 dBFS

SINAD = 70.4 dBFS

SFDR = 82.6 dBc

THD = 82.4 dBc

−20

−30

−40

−50

−60

−70

−80

−90

−100

−110

−120

−130

−140

−100

−110

−120

−130

−140

0

10

20

30

40

0

5

10

15

20

Frequency (MHz)

G003

G004

Figure 8. FFT FOR 70-MHz INPUT SIGNAL

(Sample Rate = 80 MSPS)

Figure 9. FFT FOR 5-MHz INPUT SIGNAL

(Sample Rate = 40 MSPS)

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ZHCSBT3 –OCTOBER 2013

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TYPICAL CHARACTERISTICS: General (8-Channel, 12-Bit, Non-Interleaving Mode) (continued)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, input clock frequency = 80 MSPS, 50% clock duty cycle, and

–1-dBFS differential analog input, unless otherwise noted.

0

SNR = 70.7 dBFS

SINAD = 70.5 dBFS

SFDR = 83.6 dBc

THD = 83.4 dBc

SNR = 69.7 dBFS

SINAD = 68.7 dBFS

SFDR = 75 dBc

−10

−20

THD = 74.5 dBc

−30

−40

−50

−60

−70

−80

−90

−100

−110

−120

−130

−140

−100

−110

−120

−130

−140

0

5

10

15

20

0

5

10

15

20

Frequency (MHz)

G005

G006

Figure 10. FFT FOR 15-MHz INPUT SIGNAL

(Sample Rate = 40 MSPS)

Figure 11. FFT FOR 70-MHz INPUT SIGNAL

(Sample Rate = 40 MSPS)

0

−10

71

70.5

70

f_IN1= 8 MHz

f_IN2= 10 MHz

Each Tone at −7−dBFS Amplitude

Two−Tone IMD = −90 dBFS

−20

−30

−40

−50

−60

−70

69.5

69

−80

−90

−100

−110

−120

−130

−140

68.5

68

0

10

20

30

40

0

10

20

30

40

50

60

70

80

90 100

Frequency (MHz)

Input Signal Frequency (MHz)

G007

G008

Figure 12. FFT WITH TWO-TONE SIGNAL

Figure 13. SIGNAL-TO-NOISE RATIO vs

INPUT SIGNAL FREQUENCY

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ADS5296A

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ZHCSBT3 –OCTOBER 2013

TYPICAL CHARACTERISTICS: General (8-Channel, 12-Bit, Non-Interleaving Mode) (continued)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, input clock frequency = 80 MSPS, 50% clock duty cycle, and

–1-dBFS differential analog input, unless otherwise noted.

86

84

82

80

78

76

74

72

74

70

66

62

58

Input Frequency = 10 MHz

Input Frequency = 70 MHz

0

10

20

30

40

50

60

70

80

90 100

0

1

2

3

4

5

6

7

8

9

10 11 12

Input Signal Frequency (MHz)

Digital Gain (dB)

G009

G010

Figure 14. SPURIOUS-FREE DYNAMIC RANGE vs

INPUT SIGNAL FREQUENCY

Figure 15. SIGNAL-TO-NOISE RATIO vs

DIGITAL GAIN

120

110

100

90

73

90

86

82

78

74

70

SNR

SFDR (dBc)

SFDR (dBFS)

Input Frequency = 5 MHz

Input Frequency = 10 MHz

Input Frequency = 70 MHz

72.5

72

71.5

71

80

70

70.5

70

60

50

69.5

69

40

30

68.5

68

20

−50 −45 −40 −35 −30 −25 −20 −15 −10 −5

Input amplitude (dBFS)

0

1

2

3

4

5

6

7

8

9

10 11 12

G012

Digital Gain (dB)

G011

Figure 16. SPURIOUS-FREE DYNAMIC RANGE vs

DIGITAL GAIN

Figure 17. PERFORMANCE vs INPUT AMPLITUDE

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ZHCSBT3 –OCTOBER 2013

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TYPICAL CHARACTERISTICS: General (8-Channel, 12-Bit, Non-Interleaving Mode) (continued)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, input clock frequency = 80 MSPS, 50% clock duty cycle, and

–1-dBFS differential analog input, unless otherwise noted.

83

82.5

82

73

83

82.5

82

73

Input Frequency = 5 MHz

SFDR

SNR

Input Frequency = 5 MHz

THD

SNR

72.5

72

72.5

72

81.5

81

71.5

71

81.5

81

71.5

71

80.5

80

70.5

70

80.5

80

70.5

70

79.5

69.5

79.5

79

69.5

69

79

69

2.2

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

35

40

45

50

55

60

65

Input Clock Duty Cycle (%)

Input Clock Amplitude, differential (V_P−P

)

G013

G014

Figure 18. PERFORMANCE vs INPUT CLOCK AMPLITUDE

Figure 19. PERFORMANCE vs INPUT CLOCK DUTY CYCLE

86

84

82

80

78

76

74

72

Input Frequency = 5 MHz

SFDR

SNR

Input Frequency = 5 MHz

AVDD = 1.7 V

AVDD = 1.8 V

AVDD = 1.9 V

71.5

71

71.5

71

70.5

70

70.5

70

69.5

69

69.5

69

68.5

0.8

0.85

0.9

0.95

1

1.05

1.1

68

Analog Input Common−Mode Voltage (V)

−40 −27.5 −15 −2.5 10 22.5 35 47.5 60 72.5 85

Temperature (°C)

G015

G016

Figure 20. PERFORMANCE vs

INPUT COMMON-MODE VOLTAGE

Figure 21. SIGNAL-TO-NOISE RATIO vs

AVDD AND TEMPERATURE

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ADS5296A

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ZHCSBT3 –OCTOBER 2013

TYPICAL CHARACTERISTICS: General (8-Channel, 12-Bit, Non-Interleaving Mode) (continued)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, input clock frequency = 80 MSPS, 50% clock duty cycle, and

–1-dBFS differential analog input, unless otherwise noted.

84

83.5

83

120

115

110

105

100

95

Input Frequency = 5 MHz

AVDD = 1.7 V

AVDD = 1.8 V

AVDD = 1.9 V

Adjacent Channel

Near Channel

Far Channel

82.5

82

90

85

80

75

81.5

81

70

65

−40 −27.5 −15 −2.5 10 22.5 35 47.5 60 72.5 85

Temperature (°C)

10

20

30

40

50

60

70

Frequency of Aggressor Channel (MHz)

G017

G018

(1)

Figure 22. SPURIOUS-FREE DYNAMIC RANGE vs

AVDD AND TEMPERATURE

Figure 23. CROSSTALK vs FREQUENCY

0.2

0.1

0.4

0.3

0.2

0.1

0

−0.1

−0.2

−0.3

−0.1

−0.2

−0.3

−0.4

0

500 1000 1500 2000 2500 3000 3500 4000

0

500 1000 1500 2000 2500 3000 3500 4000

Output Codes (LSB)

G020

G021

Figure 24. INTEGRAL NONLINEARITY

Figure 25. DIFFERENTIAL NONLINEARITY

(1) Adjacent channel: Neighboring channels on the immediate left and right of the channel of interest.

Near channel: Channels on the same side of the package, except the immediate neighbors.

Far channel: Channels on the opposite side of the package.

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ZHCSBT3 –OCTOBER 2013

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TYPICAL CHARACTERISTICS:

Digital Processing (8-Channel, 12-Bit, Non-Interleaving Mode)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, input clock frequency = 80 MSPS, 50% clock duty cycle, and

–1-dBFS differential analog input, unless otherwise noted.

20

10

40

30

Low−Pass

High−Pass

Low−Pass

Band−Pass 1

Band−Pass 2

High−Pass

20

0

10

−10

−20

−30

−40

−50

−60

−70

−80

0

−10

−20

−30

−40

−50

−60

−70

−80

0

0.1

0.2

0.3

0.4

0.5

0

0.1

0.2

0.3

0.4

0.5

Normalized Frequency (f_INf_S)

G021

G022

Figure 26. DIGITAL FILTER RESPONSE

(Decimate-by-2)

Figure 27. DIGITAL FILTER RESPONSE

(Decimate-by-4)

0

−10

0

−10

SNR = 75.4 dBFS

SINAD = 75 dBFS

SFDR = 85.7 dBc

THD = 85.5 dBc

SNR = 74.9 dBFS

SINAD = 74.2 dBFS

SFDR = 84.3 dBc

THD = 81.5 dBc

−20

−30

Decimate−by−2 Filter Enabled

2 Channels Averaged

−40

−50

−60

−70

−80

−90

−100

−110

−120

−130

−140

−100

−110

−120

−130

−140

0

5

10

15

20

0

10

20

30

40

Frequency (MHz)

G023

G024

Figure 28. FFT FOR 5-MHz INPUT SIGNAL

(Sample Rate = 80 MSPS, Decimation Filter = 2)

Figure 29. FFT FOR 5-MHz INPUT SIGNAL

(1)

(Sample Rate = 80 MSPS by Averaging Two Channels)⁽¹⁾

(1) 14x serialization is used to capture data.

22

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ZHCSBT3 –OCTOBER 2013

TYPICAL CHARACTERISTICS:

Digital Processing (8-Channel, 12-Bit, Non-Interleaving Mode) (continued)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, input clock frequency = 80 MSPS, 50% clock duty cycle, and

–1-dBFS differential analog input, unless otherwise noted.

0

SNR = 76.7 dBFS

SINAD = 76.6 dBFS

SFDR = 93.9 dBc

THD = 98.6 dBc

Decimate−by−4 Filter

Enabled

SNR = 75.8 dBFS

SINAD = 73.8 dBFS

SFDR = 77.5 dBc

THD = 76.9 dBc

−10

−20

−30

4 Channels Averaged

−40

−50

−60

−70

−80

−90

−100

−110

−120

−130

−140

−100

−110

−120

−130

−140

0

5

10

0

10

20

30

40

Frequency (MHz)

G025

G026

Figure 30. FFT FOR 5-MHz INPUT SIGNAL

(Sample Rate = 80 MSPS, Decimation Filter = 4)

Figure 31. FFT FOR 5-MHz INPUT SIGNAL

(2)

(Sample Rate = 80 MSPS by Averaging Four Channels)⁽²⁾

3

0

HPF_DISABLED

HPF_ENABLED (K = 2)

0

−3

−10

−20

−30

−6

−9

−40

−12

−15

−18

−21

−24

−27

−30

−33

−36

−39

−42

−45

−50

−60

−70

−80

K = 2

K = 3

K= 4

K = 5

K = 6

K = 7

K = 8

K = 9

−90

−100

−110

−120

−130

−140

K = 10

0.02

0.1

1

10 15

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Frequency (MHz)

G027

G032

Figure 32. DIGITAL HIGH-PASS FILTER RESPONSE

Figure 33. FFT WITH HPF ENABLED AND DISABLED

(No Signal)

(2) 14x serialization is used to capture data.

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ZHCSBT3 –OCTOBER 2013

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TYPICAL CHARACTERISTICS:

Power Consumption (8-Channel, 12-Bit, Non-Interleaving Mode)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS differential analog input,

unless otherwise noted.

330

300

270

240

210

180

150

120

275

250

225

200

175

150

125

100

One−Wire

One−Wire, Decimate−By−2

One−Wire, Decimate−By−4

One−Wire

One−Wire, Decimate−By−2

One−Wire, Decimate−By−4

10

20

30

40

50

60

70

80

10

20

30

40

50

60

70

80

Sampling Frequency (MHz)

G032

G033

Figure 34. ANALOG SUPPLY POWER

Figure 35. DIGITAL SUPPLY POWER

180

160

140

120

100

80

150

130

110

90

One−Wire

One−Wire, Decimate−By−2

One−Wire, Decimate−By−4

One−Wire

One−Wire, Decimate−By−2

One−Wire, Decimate−By−4

70

50

10

20

30

40

50

60

70

80

10

20

30

40

50

60

70

80

Sampling Frequency (MHz)

G034

G035

Figure 36. ANALOG SUPPLY CURRENT

Figure 37. DIGITAL SUPPLY CURRENT

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TYPICAL CHARACTERISTICS:

Power Consumption (8-Channel, 12-Bit, Non-Interleaving Mode) (continued)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS differential analog input,

unless otherwise noted.

65

60

55

50

45

40

35

30

10

20

30

40

50

60

70

80

Sampling Frequency (MHz)

G036

Figure 38. TOTAL POWER PER CHANNEL

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TYPICAL CHARACTERISTICS: Contour (8-Channel, 12-Bit, Non-Interleaving Mode)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS differential analog input,

unless otherwise noted.

80

70

60

50

40

30

20

70.3

70.4

69.7

70

69.4

69.1

70.5

70.3

70.4

70

69.7

69.4

68.8

69.1

70.6

70.5

70.3

70.4

69.1

69.4

69.7

70

68.5

68.2

10

20

30

40

50

60

70

80

90

Input Frequency, MHz

68

68.5

69

69.5

70

70.5

Figure 39. SIGNAL-TO-NOISE RATIO vs INPUT AND SAMPLING FREQUENCIES

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TYPICAL CHARACTERISTICS: Contour (8-Channel, 12-Bit, Non-Interleaving Mode) (continued)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS differential analog input,

unless otherwise noted.

80

78

80

82

70

78

60

80

78

50

76

82

74

40

30

20

80

78

82

76

84

74

80

78

10

20

30

40

50

60

70

80

90

Input Frequency, MHz

74

76

78

80

82

84

Figure 40. SPURIOUS-FREE DYNAMIC RANGE vs INPUT AND SAMPLING FREQUENCIES

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TYPICAL CHARACTERISTICS: General (4-Channel, 10-Bit, Interleaving Mode)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, input clock frequency = 200 MSPS, 50% clock duty cycle,

and –1-dBFS differential analog input, unless otherwise noted.

0

−10

0

−10

SNR = 61.5 dBFS

SINAD = 61.5 dBFS

SFDR = 86.6 dBc

THD = 85.4 dBc

SNR = 61.4 dBFS

SINAD = 61.3 dBFS

SFDR = 75.6 dBc

THD = 84.9 dBc

−20

−30

−40

−50

−60

−70

−80

−90

−100

−110

−120

−130

−140

−100

−110

−120

−130

−140

0

10

20

30

40

50

60

70

80

90 100

0

10

20

30

40

50

60

70

80

90 100

Frequency (MHz)

G037

G038

Figure 41. FFT FOR 5-MHz INPUT SIGNAL

Figure 42. FFT FOR 15-MHz INPUT SIGNAL

0

−10

62

61.75

61.5

61.25

61

SNR = 61.1 dBFS

SINAD = 61.03 dBFS

SFDR = 74.1 dBc

THD = 77.2 dBc

−20

−30

−40

−50

−60

−70

−80

60.75

60.5

60.25

60

−90

−100

−110

−120

−130

−140

0

10

20

30

40

50

60

70

80

90 100

0

10

20

30

40

50

60

70

80

90 100

Frequency (MHz)

Input Signal Frequency (MHz)

G039

G040

Figure 43. FFT FOR 70-MHz INPUT SIGNAL

Figure 44. SIGNAL-TO-NOISE RATIO vs

INPUT SIGNAL FREQUENCY

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TYPICAL CHARACTERISTICS: General (4-Channel, 10-Bit, Interleaving Mode) (continued)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, input clock frequency = 200 MSPS, 50% clock duty cycle,

and –1-dBFS differential analog input, unless otherwise noted.

88

85

82

79

76

73

70

80

78

76

74

72

70

68

Normal Mode

Mux Mode

0

10

20

30

40

50

60

70

80

90 100

0

10

20

30

40

50

60

70

80

90 100

Input Signal Frequency (MHz)

G041

G042

Figure 45. SPURIOUS-FREE DYNAMIC RANGE vs

INPUT SIGNAL FREQUENCY

Figure 46. INTERLEAVING SPUR (f_S/ 2 – f_IN

)

vs INPUT SIGNAL FREQUENCY

63

62

61

60

59

58

57

56

94

90

86

82

78

74

Input Frequency = 10 MHz

Input Frequency = 70 MHz

Input Frequency = 10 MHz

Input Frequency = 70 MHz

0

1

2

3

4

5

6

7

8

9

10 11 12

0

1

2

3

4

5

6

7

8

9

10 11 12

Digital Gain (dB)

G043

G044

Figure 47. SIGNAL-TO-NOISE RATIO vs

DIGITAL GAIN

Figure 48. SPURIOUS-FREE DYNAMIC RANGE vs

DIGITAL GAIN

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TYPICAL CHARACTERISTICS: General (4-Channel, 10-Bit, Interleaving Mode) (continued)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, input clock frequency = 200 MSPS, 50% clock duty cycle,

and –1-dBFS differential analog input, unless otherwise noted.

100

90

80

70

60

50

40

30

20

68

66

64

62

60

58

56

54

52

85

82.5

80

SNR

SFDR (dBc)

SFDR (dBFS)

Input Frequency = 5 MHz

Normal Mode − Input Frequency = 10 MHz

Normal mode − Input Frequency = 70 MHz

Mux mode − Input Frequency = 10 MHz

Mux mode − Input Frequency = 70 MHz

77.5

75

72.5

70

67.5

65

−50 −45 −40 −35 −30 −25 −20 −15 −10 −5

Input amplitude (dBFS)

0

1

2

3

4

5

6

7

8

9

10 11 12

G046

Digital Gain (dB)

G045

Figure 49. INTERLEAVING SPUR (f_S/ 2 – f_IN

)

Figure 50. PERFORMANCE vs INPUT AMPLITUDE

vs DIGITAL GAIN

62

61.9

61.8

61.7

61.6

61.5

61.4

61.3

61.2

61.1

61

84

83

82

81

80

79

78

77

76

75

Input Frequency = 5 MHz

AVDD = 1.7 V

AVDD = 1.8 V

AVDD = 1.9 V

Input Frequency = 5 MHz

AVDD = 1.7 V

AVDD = 1.8 V

AVDD = 1.9 V

−40 −27.5 −15 −2.5 10 22.5 35 47.5 60 72.5 85

Temperature (°C)

−40 −27.5 −15 −2.5 10 22.5 35 47.5 60 72.5 85

Temperature (°C)

G047

G048

Figure 51. SIGNAL-TO-NOISE RATIO vs

AVDD AND TEMPERATURE

Figure 52. SPURIOUS-FREE DYNAMIC RANGE vs

AVDD AND TEMPERATURE

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TYPICAL CHARACTERISTICS: General (4-Channel, 10-Bit, Interleaving Mode) (continued)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, input clock frequency = 200 MSPS, 50% clock duty cycle,

and –1-dBFS differential analog input, unless otherwise noted.

82

Normal Mode − AVDD = 1.7 V

Normal mode − AVDD = 1.8 V

Normal Mode − AVDD = 1.9 V

Mux Mode − AVDD = 1.7V

Mux Mode − AVDD = 1.8V

Mux Mode − AVDD = 1.9V

81

80

79

78

77

76

75

Input Frequency = 5 MHz

−40 −27.5 −15 −2.5 10 22.5 35 47.5 60 72.5 85

Temperature (°C)

G049

Figure 53. INTERLEAVING SPUR (f_S/ 2 – f_IN) vs

AVDD AND TEMPERATURE

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TYPICAL CHARACTERISTICS:

Power Consumption (4-Channel, 10-Bit, Interleaving Mode)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS differential analog input,

unless otherwise noted.

390

360

330

300

270

240

210

180

150

120

240

220

200

180

160

140

120

100

20

40

60

80

100 120 140 160 180 200

20

40

60

80

100 120 140 160 180 200

Sampling Frequency (MHz)

G050

G051

Figure 54. ANALOG SUPPLY POWER

Figure 55. DIGITAL SUPPLY POWER

220

200

180

160

140

120

100

80

125

110

95

80

65

50

20

40

60

80

100 120 140 160 180 200

20

40

60

80

100 120 140 160 180 200

Sampling Frequency (MHz)

G052

G053

Figure 56. ANALOG SUPPLY CURRENT

Figure 57. DIGITAL SUPPLY CURRENT

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TYPICAL CHARACTERISTICS:

Power Consumption (4-Channel, 10-Bit, Interleaving Mode) (continued)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS differential analog input,

unless otherwise noted.

150

140

130

120

110

100

90

80

70

60

20

40

60

80

100 120 140 160 180 200

Sampling Frequency (MHz)

G054

Figure 58. TOTAL POWER PER CHANNEL

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TYPICAL CHARACTERISTICS: Contour (4-Channel, 10-Bit, Interleaving Mode)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS differential analog input,

unless otherwise noted.

200

61

61.1

60.9

61.4

61.3

61.2

180

160

140

120

100

61.1

61.4

61.3

61.2

61.1

61.4

61.3

61.2

10

20

30

40

50

60

70

80

90

Input Frequency, MHz

60.9

61

61.1

61.2

61.3

61.4

Figure 59. SIGNAL-TO-NOISE RATIO vs INPUT AND SAMPLING FREQUENCIES

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TYPICAL CHARACTERISTICS: Contour (4-Channel, 10-Bit, Interleaving Mode) (continued)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS differential analog input,

unless otherwise noted.

200

76

80

82

78

74

180

76

80

72

78

160

140

120

100

82

80

78

74

76

78

76

74

80

10

20

30

40

50

60

70

80

90

82

Input Frequency, MHz

72

74

76

78

80

Figure 60. SPURIOUS-FREE DYNAMIC RANGE vs INPUT AND SAMPLING FREQUENCIES

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TYPICAL CHARACTERISTICS: General (8-Channel, 12-Bit, Interleaving Mode)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, input clock frequency = 160 MSPS, 50% clock duty cycle,

and –1-dBFS differential analog input, unless otherwise noted.

70

69.5

69

94

90

86

82

78

74

70

68.5

68

67.5

67

0

10

20

30

40

50

60

70

80

90 100

0

10

20

30

40

50

60

70

80

90 100

Input Signal Frequency (MHz)

G058

G059

Figure 61. SIGNAL-TO-NOISE RATIO vs

INPUT SIGNAL FREQUENCY

Figure 62. SPURIOUS-FREE DYNAMIC RANGE vs

INPUT SIGNAL FREQUENCY

82

80

78

76

74

72

0.2

0.1

Normal Mode

Mux Mode

0

−0.1

−0.2

−0.3

0

10

20

30

40

50

60

70

80

90 100

0

500 1000 1500 2000 2500 3000 3500 4000

Input Signal Frequency (MHz)

Output Codes (LSB)

G060

G061

Figure 63. INTERLEAVING SPUR (f_S/ 2 – f_IN

)

Figure 64. INTEGRAL NONLINEARITY

vs INPUT SIGNAL FREQUENCY

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TYPICAL CHARACTERISTICS: General (8-Channel, 12-Bit, Interleaving Mode) (continued)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, input clock frequency = 160 MSPS, 50% clock duty cycle,

and –1-dBFS differential analog input, unless otherwise noted.

0.4

0.3

0.2

0.1

0

−0.1

−0.2

−0.3

−0.4

0

500 1000 1500 2000 2500 3000 3500 4000

Output Codes (LSB)

G062

Figure 65. DEFERENTIAL NONLINEARITY

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TYPICAL CHARACTERISTICS:

Power Consumption (8-Channel, 12-Bit, Interleaving Mode)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS differential analog input,

unless otherwise noted.

330

300

270

240

210

180

150

120

220

200

180

160

140

120

100

20

40

60

80

100

120

140

160

20

40

60

80

100

120

140

160

Sampling Frequency (MHz)

G063

G064

Figure 66. ANALOG SUPPLY POWER

Figure 67. DIGITAL SUPPLY POWER

180

160

140

120

100

80

120

110

100

90

80

70

60

20

40

60

80

100

120

140

160

20

40

60

80

100

120

140

160

Sampling Frequency (MHz)

G065

G066

Figure 68. ANALOG SUPPLY CURRENT

Figure 69. DIGITAL SUPPLY CURRENT

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TYPICAL CHARACTERISTICS:

Power Consumption (8-Channel, 12-Bit, Interleaving Mode) (continued)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS differential analog input,

unless otherwise noted.

140

130

120

110

100

90

80

70

60

20

40

60

80

100

120

140

160

Sampling Frequency (MHz)

G067

Figure 70. TOTAL POWER PER CHANNEL

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TYPICAL CHARACTERISTICS: Contour (8-Channel, 12-Bit, Interleaving Mode)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS differential analog input,

unless otherwise noted.

160

68.4

68.2

68.6

68.8

69

69.1

150

140

130

120

110

100

68

69.1

68.4

68.2

68.6

68.8

69

69.2

69.1

68.6

68.4

68.2

68.8

69

10

20

30

40

50

60

70

80

90

Input Frequency, MHz

68

68.2

68.4

68.6

68.8

69

69.2

Figure 71. SIGNAL-TO-NOISE RATIO vs INPUT AND SAMPLING FREQUENCIES

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TYPICAL CHARACTERISTICS: Contour (8-Channel, 12-Bit, Interleaving Mode) (continued)

Typical values are at T_A= +25°C, AVDD = 1.8 V, LVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS differential analog input,

unless otherwise noted.

160

79

80

78

75

74

150

140

130

120

110

100

73

76

78

77

79

75

74

77

78

76

77

76

74

75

78

10

20

30

40

50

60

70

80

90

80

Input Frequency, MHz

73

74

75

76

77

78

79

Figure 72. SPURIOUS-FREE DYNAMIC RANGE vs INPUT AND SAMPLING FREQUENCIES

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DEVICE CONFIGURATION

SERIAL INTERFACE

The device has a set of internal registers that can be accessed by the serial interface formed by the CS (serial

interface enable), SCLK (serial interface clock), and SDATA (serial interface data) pins.

Register Initialization

After power-up, the internal registers must be initialized to default values. This initialization can be accomplished

in one of two ways:

1. Either through a hardware reset by applying a low pulse on the RESET pin (of widths greater than 50 ns),

see Figure 74; or

2. By applying a software reset. When using the serial interface, set the RST bit (register 00h, bit D0) high. This

setting initializes the internal registers to default values and then self-resets the RST bit low. In this case, the

RESET pin is kept high (inactive).

Reset Timing

Figure 73 shows a timing diagram for the reset function.

Power Supply

AVDD, LVDD

t₁

RESET

t₂

t₃

SEN

Figure 73. Reset Timing Diagram

Table 6. Timing Characteristics for Figure 73⁽¹⁾⁽²⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Delay from AVDD and LVDD power-up to active

RESET pulse

t₁

Power-on delay

1

ms

t₂

t₃

Reset pulse width

Pulse width of active RESET signal

50

ns

Register write delay

Delay from RESET disable to CS active

100

(1) Typical values are at T_A= +25°C, minimum and maximum values are across the full temperature range of T_MIN= –40°C to

T_MAX= +85°C, unless otherwise noted.

(2) A low pulse on the RESET pin is required when initialization is done via a hardware reset.

Serial Interface Write Operation

Serial shifting of bits into the device is enabled when CS is low. Serial data (on the SDATA pin) are latched at

every SCLK rising edge when CS is active (low). Serial data are loaded into the register at every 24th SCLK

rising edge when CS is low. When the word length exceeds a multiple of 24 bits, the excess bits are ignored (the

excess bits being the last bits clocked). Data can be loaded in multiples of 24-bit words within a single active CS

pulse. The first eight bits form the register address and the remaining 16 bits are the register data.

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CS

t_{CS_SU}

Data Latched On

Rising Edge of SCLK

t_{SCLK_L}

t_SCLK

t_{CS_HO}

SCLK

t_{SCLK_H}

t_DSU

t_DH

A7

A6

A5

A4

A3

A2

A1

A0 D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SDATA

RESET

Figure 74. Serial Interface Write Timing Diagram

Table 7. Timing Characteristics for Figure 74 and Figure 76⁽¹⁾

PARAMETER

MIN

> dc

50

TYP

MAX

UNIT

f_SCLK

SCLK frequency (equal to 1 / t_SCLK

)

20

MHz

ns

t_SCLK

SCLK period

t_{SCLK_H}

t_{SCLK_L}

t_DSU

SCLK high time

20

ns

SCLK low time

20

ns

SDATA setup time

SDATA hold time

25

ns

t_DHO

25

ns

t_{CS_SU}

t_{CS_HO}

CS fall to SCLK rise

25

ns

Time between last SCLK rising edge to CS rising edge

Delay from SCLK falling edge to SDOUT valid

25

ns

(2)

t_{OUT_DV}

15

19

23

ns

(1) Typical values are at T_A= +25°C, minimum and maximum values are across the full temperature range of T_MIN= –40°C to T_MAX

=

+85°C, unless otherwise noted.

(2) See Figure 76.

Serial Interface Read Operation

The device includes a mode where the contents of the internal registers can be read back on the SDOUT pin.

This readback mode may be useful as a diagnostic check to verify the serial interface communication between

the external controller and the ADC.

By default, the SDOUT pin is in 3-state after a device power-up or reset. When the readout mode is enabled

using the EN_READOUT register bit, SDOUT serially outputs the contents of the selected register. The following

steps describe how to achieve this functionality:

1. Set the EN_READOUT register bit to '1'; see Figure 75(a). This setting puts the device in serial readout

mode. This mode prevents any further writes to the internal registers, except for at register 01h. Note that the

EN_READOUT bit is also located in register 01h. The device can exit readout mode by setting the

EN_READOUT bit to '0'. Note that only the contents of register 01h are unable to be read in register readout

mode.

2. Initiate a serial interface cycle specifying the address of the register (A[7:0]) whose content must be read.

3. The device serially outputs the contents (D[15:0]) of the selected register on the SDOUT pin; see

Figure 75(b).

4. The external controller can latch the contents at the SCLK rising edge.

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To exit serial readout mode, reset the EN_READOUT register bit to '0', which enables writes to all device

registers. At this point, the SDOUT pin is in 3-state. A detailed timing diagram for the serial readout mode is

shown in Figure 76.

Register Address (A[7:0]) = 01h

Register Data (D[15:0]) = 0001

SDATA

SCLK

0

1

0

1

The SDOUT pin becomes active and is forced low.

CS

SDOUT

The SDOUT Pin is in 3-State

a) Enable Serial Readout (READOUT = 1)

Register Address (A[7:0]) = 0Fh

Register Data (D[15:0]) = XXXX (don’t care)

SDATA

SCLK

A7

A6

A5

A4

A3

A2

A1

A0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

CS

0

1

SDOUT

SDOUT outputs the contents of register 0Fh in the same cycle, MSB first.

b) Read contents of register 0Fh. This register is initialized with 0200 (the device was previously put in global power-down).

Figure 75. Serial Readout Functional Diagram

CS

SCLK

t_{OUT_DV}

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SDOUT

A7

A6

A5

A4

A3

A2

A1

A0

X

SDATA

Figure 76. Serial Interface Read Timing Diagram

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DESCRIPTION OF SERIAL INTERFACE REGISTERS

Table 9. Register 00h

D15

0

D14

0

D13

0

D12

0

D11

0

D10

0

D9

0

D8

0

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

RST

All bits default to '0' after reset.

Bits D[15:1]

Bit D0

Must write '0'

RST

0 = Normal operation (default)

1 = Self-clearing software RESET; after reset, this bit is set to '0'

Table 10. Register 01h

D15

0

D14

0

D13

0

D12

0

D11

0

D10

0

D9

0

D8

0

D7

0

D6

0

D5

0

D4

D3

0

D2

0

D1

0

D0

EN_HIGH_

ADDRS

EN_READOUT

All bits default to '0' after reset.

Bits D[15:5]

Bit D4

Must write '0'

EN_HIGH_ADDRS

0 = Access to register F0h disabled (default)

1 = Access to register F0h enabled

Bits D[3:1]

Bit D0

Must write '0'

EN_READOUT

0 = Normal operation (default)

1 = READOUT of registers mode using the SDOUT pin enabled

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Table 11. Register 07h

D15

0

D14

0

D13

0

D12

0

D11

0

D10

0

D9

D8

0

D1

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D0

EN_

INTERLEAVE

EN_MUX_REG

All bits default to '0' after reset.

Bits D[15:2]

Bit D1

Must write '0'

EN_MUX_REG

Enables mux mode interleaving using register bit.

0 = Enables mux mode interleaving using the ODD_EVEN_SEL register bits (default)

1 = Enables mux mode interleaving using the INTERLEAVE_MUX pin.

For more details on this bit, see the Interleaving Mode section.

Bit D0

EN_INTERLEAVE

Enables interleaving of adjacent channel pairs.

0 = Interleaving disabled (default)

1 = Interleaving enabled

For more details on this bit, see the Interleaving Mode section.

Table 12. Register 0Ah

D15

D7

D14

D6

D13

D5

D12

RAMP_PAT_RESET_VAL

D4 D3

RAMP_PAT_RESET_VAL

D11

D10

D2

D9

D1

D8

D0

All bits default to '0' after reset.

Bits D[15:0] RAMP_PAT_RESET_VAL

The starting value of the digital ramp test pattern can be programmed using these register

bits. By default, the starting value is 0000h after reset.

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Table 13. Register 0Fh

D15

0

D14

D13

0

D12

D11

D10

D9

D8

PDN_

COMPLETE

0

PDN_PIN_CFG

PDN_PARTIAL

D7

D6

D5

D4

D3

D2

D1

D0

PDN_CH[8:1]

All bits default to '0' after reset.

Bits D[15:11]

Bit D10

Must write '0'

PDN_PIN_CFG

0 = PD pin configured for complete power-down mode

1 = PD pin configured for partial power-down mode

Bit D9

PDN_COMPLETE

0 = Normal operation

1 = Register mode for complete power-down; slow recovery from power-down

Bit D8

PDN_PARTIAL

0 = Normal operation

1 = Partial power-down mode; fast recovery from power-down

Bits D[7:0]

PDN_CH[8:1]

0 = Normal operation

1 = Individual channel ADC power-down mode

Table 14. Register 14h

D15

0

D14

0

D13

0

D12

0

D11

0

D10

0

D9

0

D8

0

D7

D6

D5

D4

D3

D2

D1

D0

LFNS_CH[8:1]

All bits default to '0' after reset.

Bits D[15:8]

Bits D[7:0]

Must write '0'

LFNS_CH[8:1]

0 = Low-frequency noise suppression (LFNS) mode disabled (default)

1 = LFNS mode enabled for individual channels

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Table 15. Register 1Ch

D15

0

D14

D13

0

D12

D11

D10

ADCLKOUT[11:0]

D2 D1

D9

D8

D0

EN_FRAME_

PAT

0

D7

D6

D5

D4

D3

ADCLKOUT[11:0]

All bits default to '0' after reset.

Bit D15

Bit D14

Must write '0'

EN_FRAME_PAT

0 = Normal operation on frame clock (default)

1 = Enables output frame clock to be programmed through a pattern specified by the

ADCCLKOUT register bits

Bits D[13:12]

Bits D[11:0]

Must write '0'

ADCLKOUT[11:0]

These bits create the 12-bit pattern for the frame clock on the ADCLKP, ADCLKN pins.

Table 16. Register 23h

D15

D7

D14

D6

D13

D5

D12

D11

D10

D2

D9

D1

D8

D0

PRBS_SEED[15:0]

D4

D3

PRBS_SEED[15:0]

All bits default to '0' after reset.

Bits D[15:0]

PRBS_SEED[15:0]

These bits are the lower 16 bits of the PRBS pattern starting seed value.

The starting seed value of the PRBS test pattern can be specified using these register bits.

Table 17. Register 24h

D15

D7

D14

D6

D13

D5

D12

D11

D10

D2

D9

D1

D8

0

PRBS_SEED[22:16]

D4

D3

D0

INVERT_CH[8:1]

All bits default to '0' after reset.

Bits D[15:9]

PRBS_SEED[22:16]

These bits are the seven upper bits of the PRBS seed starting value.

Bit D8

Must write '0'

Bits D[7:0]

INVERT_CH[8:1]

0 = Normal configuration

Normally, the IN_p pin represents the positive analog input pin and IN_n represents the

complementary negative input.

1 = The polarity of the analog input pins is electrically swapped

Setting the INVERT_CH[8:1] bits causes the inputs to be swapped. IN_n now represents the

positive input and IN_p represents the negative input.

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Table 18. Register 25h

D15

D14

D13

D12

D11

D10

0

D9

0

D8

TP_HARD_

SYNC

PRBS_SEED_

FROM_REG

PRBS_

MODE_2

TP_SOFT_

SYNC

PRBS_TP_EN

0

D7

0

D6

D5

D4

D3

D2

D1

D0

TEST_PATT[2:0]

BITS_CUSTOM2[11:10]

BITS_CUSTOM1[11:10]

All bits default to '0' after reset.

Bit D15

TP_HARD_SYNC

0 = Inactive

1 = The external SYNC feature is enabled for syncing test patterns

Bit D14

PRBS_SEED_FROM_REG

0 = Disabled

1 = The PRBS seed can be chosen from registers 23h and 24h

Bit D13

Bit D12

PRBS_MODE_2

The PRBS 9-bit LFSR (23-bit LFSR) is the default mode.

PRBS_TP_EN

0 = PRBS test pattern disabled

1 = PRBS test pattern enabled

Bits D[11:9]

Bit D8

Must write '0'

TP_SOFT_SYNC

0 = No sync

1 = Software sync bit for the test patterns on all eight channels

Bit D7

Bit D6

Must write '0'

TEST_PATT2

0 = Normal operation

1 = A repeating full-scale ramp pattern is enabled on the outputs; ensure that bits D4 and

D5 are '0'

Bit D5

Bit D4

TEST_PATT1

0 = Normal operation

1 = Enables a mode where the output toggles between two defined codes; ensure that bits

D4 and D6 are '0'

TEST_PATT0

0 = Normal operation

1 = Enables a mode where the output is a constant specified code; ensure that bits D5 and

D6 are '0'

Bits D[3:2]

Bits D[1:0]

BITS_CUSTOM2[11:10]

These bits are the two MSBs for the second code of the dual custom patterns.

BITS_CUSTOM1[11:10]

These bits are the two MSBs for the single custom pattern (and for the first code of the dual

custom patterns).

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Table 19. Register 26h

D15

D7

D14

D6

D13

D12

D11

D10

D9

D8

BITS_CUSTOM1[9:0]

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

BITS_CUSTOM1[9:0]

All bits default to '0' after reset.

Bits D[15:6]

BITS_CUSTOM1[9:0]

These bits are the 10 lower bits for the single custom pattern (and for the first code of the

dual custom pattern).

Bits D[5:0]

Must write '0'

Table 20. Register 27h

D15

D7

D14

D6

D13

D12

D11

D10

D9

D8

BITS_CUSTOM2[9:0]

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

BITS_CUSTOM2[9:0]

All bits default to '0' after reset.

Bits D[15:6]

Bits D[5:0]

BITS_CUSTOM2[9:0]

These bits are the 10 lower bits for the second code of the dual custom pattern.

Must write '0'

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Table 21. Register 29h

D15

0

D14

D13

0

D12

0

D11

0

D10

0

D9

0

D8

0

D6

0

D7

0

D5

0

D4

0

D3

0

D2

0

D1

D0

GLOBAL_EN

FILTER

EN_CHANNEL

_AVG

All bits default to '0' after reset.

Bits D[15:2]

Bit D1

Must write '0'

GLOBAL_EN_FILTER

0 = Global control digital filter disabled(default)

1 = Global control digital filter enabled

Bit D0

EN_CHANNEL_AVG

0 = Channel averaging disabled (default)

1 = Channel averaging enabled and specified by the AVG_OUTn register bits

Table 22. Register 2Ah

D15

D7

D14

D13

D5

D12

D11

D10

D9

D1

D8

D0

GAIN_CH4[3:0]

GAIN_CH3[3:0]

D6

D4

D3

D2

GAIN_CH1[3:0]

GAIN_CH2[3:0]

All bits default to '0' after reset.

Bits D[15:12]

Bits D[11:8]

Bits D[7:4]

Bits D[3:0]

GAIN_CH4[3:0]

These bits set the programmable gain for channel 4.

GAIN_CH3[3:0]

These bits set the programmable gain for channel 3.

GAIN_CH2[3:0]

These bits set the programmable gain for channel 2.

GAIN_CH1[3:0]

These bits set the programmable gain for channel 1.

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Table 23. Register 2Bh

D15

D7

D14

D13

D5

D12

D11

D10

GAIN_CH6[3:0]

D2 D1

GAIN_CH8[3:0]

D9

D8

D0

GAIN_CH5[3:0]

D6

D4

D3

GAIN_CH7[3:0]

All bits default to '0' after reset.

Bits D[15:12]

Bits D[11:8]

Bits D[7:4]

Bits D[3:0]

GAIN_CH5[3:0]

These bits set the programmable gain for channel 4.

GAIN_CH6[3:0]

These bits set the programmable gain for channel 5.

GAIN_CH7[3:0]

These bits set the programmable gain for channel 6.

GAIN_CH8[3:0]

These bits set the programmable gain for channel 7.

Table 24. Register 2Ch

D15

0

D14

0

D13

0

D12

0

D11

0

D10

D9

D8

0

AVG_OUT4[1:0]

D7

D6

D5

0

D4

D3

D2

0

D1

D0

AVG_OUT3[1:0]

AVG_OUT2[1:0]

AVG_OUT1[1:0]

All bits default to '0' after reset.

Bits D[15:11]

Bits D[10:9]

Must write '0'

AVG_OUT4[1:0]

These bits set the averaging control for data transmitted on the LVDS output OUT4.

Bit D8

Must write '0'

Bits D[7:6]

AVG_OUT3[1:0]

These bits set the averaging control for data transmitted on the LVDS output OUT3.

Bit D5

Must write '0'

Bits D[4:3]

AVG_OUT2[1:0]

These bits set the averaging control for data transmitted on the LVDS output OUT2.

Bit D2

Must write '0'

Bits D[1:0]

AVG_OUT1[1:0]

These bits set the averaging control for data transmitted on the LVDS output OUT1.

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Table 25. Register 2Dh

D15

0

D14

D13

0

D12

0

D11

0

D10

D9

D1

D8

0

AVG_OUT8[1:0]

D7

D6

D5

0

D4

D3

D2

0

D0

AVG_OUT7[1:0]

AVG_OUT6[1:0]

AVG_OUT5[1:0]

All bits default to '0' after reset.

Bits D[15:11]

Bits D[10:9]

Must write '0'

AVG_OUT8[1:0]

These bits set the averaging control for data transmitted on the LVDS output OUT8.

Bit D8

Must write '0'

Bits D[7:6]

AVG_OUT7[1:0]

These bits set the averaging control for data transmitted on the LVDS output OUT7.

Bit D5

Must write '0'

Bits D[4:3]

AVG_OUT6[1:0]

These bits set the averaging control for data transmitted on the LVDS output OUT6.

Bit D2

Must write '0'

Bits D[1:0]

AVG_OUT5[1:0]

These bits set the averaging control for data transmitted on the LVDS output OUT5.

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Table 26. Register 2Eh

D15

0

D14

D13

D12

D11

D10

D2

D9

D8

HPF_EN_CH1

HPF_CORNER _CH1[3:0]

FILTER_TYPE_CH1[2:0]

D7

D6

D5

D4

D3

0

D1

0

D0

FILTER_TYPE

_CH1[2:0]

SEL_ODD_

TAP_CH1

USE_FILTER_

CH1

DEC_RATE_CH1[2:0]

All bits default to '0' after reset.

Bit D15

Bit D14

Must write '0'

HPF_EN_CH1

This bit enables the HPF filter for channel 1.

HPF_CORNER _CH1[3:0]

Bits D[13:10]

Bits D[9:7]

Bits D[6:4]

These bits program the HPF corner for channel 1.

FILTER_TYPE_CH1[2:0]

These bits select the type of filter on channel 1.

DEC_RATE_CH1[2:0]

These bits set the decimation factor for the filter on channel 1.

Must write '0'

Bit D3

Bit D2

SEL_ODD_TAP_CH1

This bit enables the odd tap filter for channel 1.

Must write '0'

Bit D1

Bit D0

USE_FILTER_CH1

This bit enables the filter for channel 1.

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Table 27. Register 2Fh

D15

0

D14

D13

D12

D11

D10

D2

D9

D8

HPF_EN_CH2

D6

HPF_CORNER _CH2[3:0]

FILTER_TYPE_CH2[2:0]

D7

D5

D4

D3

0

D1

0

D0

FILTER_TYPE

_CH2[2:0]

SEL_ODD_

TAP_CH2

USE_FILTER_

CH2

DEC_RATE_CH2[2:0]

All bits default to '0' after reset.

Bit D15

Bit D14

Must write '0'

HPF_EN_CH2

This bit enables the HPF filter for channel 2.

HPF_CORNER _CH2[3:0]

Bits D[13:10]

Bits D[9:7]

Bits D[6:4]

These bits program the HPF corner for channel 2.

FILTER_TYPE_CH2[2:0]

These bits select the type of filter on channel 2.

DEC_RATE_CH2[2:0]

These bits set the decimation factor for the filter on channel 2.

Must write '0'

Bit D3

Bit D2

SEL_ODD_TAP_CH2

This bit enables the odd tap filter for channel 2.

Must write '0'

Bit D1

Bit D0

USE_FILTER_CH2

This bit enables the filter for channel 2.

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Table 28. Register 30h

D15

0

D14

D13

D12

D11

D10

D2

D9

D8

HPF_EN_CH3

HPF_CORNER _CH3[3:0]

FILTER_TYPE_CH3[2:0]

D7

D6

D5

D4

D3

0

D1

0

D0

FILTER_TYPE

_CH3[2:0]

SEL_ODD_

TAP_CH3

USE_FILTER_

CH3

DEC_RATE_CH3[2:0]

All bits default to '0' after reset.

Bit D15

Bit D14

Must write '0'

HPF_EN_CH3

This bit enables the HPF filter for channel 3.

HPF_CORNER _CH3[3:0]

Bits D[13:10]

Bits D[9:7]

Bits D[6:4]

These bits program the HPF corner for channel 3.

FILTER_TYPE_CH3[2:0]

These bits select the type of filter on channel 3.

DEC_RATE_CH3[2:0]

These bits set the decimation factor for the filter on channel 3.

Must write '0'

Bit D3

Bit D2

SEL_ODD_TAP_CH3

This bit enables the odd tap filter for channel 3.

Must write '0'

Bit D1

Bit D0

USE_FILTER_CH3

This bit enables the filter for channel 3.

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Table 29. Register 31h

D15

0

D14

D13

D12

D11

D10

D2

D9

D8

HPF_EN_CH4

D6

HPF_CORNER _CH4[3:0]

FILTER_TYPE_CH4[2:0]

D7

D5

D4

D3

0

D1

0

D0

FILTER_TYPE

_CH4[2:0]

SEL_ODD_

TAP_CH4

USE_FILTER_

CH4

DEC_RATE_CH4[2:0]

All bits default to '0' after reset.

Bit D15

Bit D14

Must write '0'

HPF_EN_CH4

This bit enables the HPF filter for channel 4.

HPF_CORNER _CH4[3:0]

Bits D[13:10]

Bits D[9:7]

Bits D[6:4]

These bits program the HPF corner for channel 4.

FILTER_TYPE_CH4[2:0]

These bits select the type of filter on channel 4.

DEC_RATE_CH4[2:0]

These bits set the decimation factor for the filter on channel 4.

Must write '0'

Bit D3

Bit D2

SEL_ODD_TAP_CH4

This bit enables the odd tap filter for channel 4.

Must write '0'

Bit D1

Bit D0

USE_FILTER_CH4

This bit enables the filter for channel 4.

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Table 30. Register 32h

D15

0

D14

D13

D12

D11

D10

D2

D9

D8

HPF_EN_CH5

HPF_CORNER _CH5[3:0]

FILTER_TYPE_CH5[2:0]

D7

D6

D5

D4

D3

0

D1

0

D0

FILTER_TYPE

_CH5[2:0]

SEL_ODD_

TAP_CH5

USE_FILTER_

CH5

DEC_RATE_CH5[2:0]

All bits default to '0' after reset.

Bit D15

Bit D14

Must write '0'

HPF_EN_CH5

This bit enables the HPF filter for channel 5.

HPF_CORNER _CH5[3:0]

Bits D[13:10]

Bits D[9:7]

Bits D[6:4]

These bits program the HPF corner for channel 5.

FILTER_TYPE_CH5[2:0]

These bits select the type of filter on channel 5.

DEC_RATE_CH5[2:0]

These bits set the decimation factor for the filter on channel 5.

Must write '0'

Bit D3

Bit D2

SEL_ODD_TAP_CH5

This bit enables the odd tap filter for channel 5.

Must write '0'

Bit D1

Bit D0

USE_FILTER_CH5

This bit enables the filter for channel 5.

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Table 31. Register 33h

D15

0

D14

D13

D12

D11

D10

D2

D9

D8

HPF_EN_CH6

D6

HPF_CORNER _CH6[3:0]

FILTER_TYPE_CH6[2:0]

D7

D5

D4

D3

0

D1

0

D0

FILTER_TYPE

_CH6[2:0]

SEL_ODD_

TAP_CH6

USE_FILTER_

CH6

DEC_RATE_CH6[2:0]

All bits default to '0' after reset.

Bit D15

Bit D14

Must write '0'

HPF_EN_CH6

This bit enables the HPF filter for channel 6.

HPF_CORNER _CH6[3:0]

Bits D[13:10]

Bits D[9:7]

Bits D[6:4]

These bits program the HPF corner for channel 6.

FILTER_TYPE_CH6[2:0]

These bits select the type of filter on channel 6.

DEC_RATE_CH6[2:0]

These bits set the decimation factor for the filter on channel 6.

Must write '0'

Bit D3

Bit D2

SEL_ODD_TAP_CH6

This bit enables the odd tap filter for channel 6.

Must write '0'

Bit D1

Bit D0

USE_FILTER_CH6

This bit enables the filter for channel 6.

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Table 32. Register 34h

D15

0

D14

D13

D12

D11

D10

D2

D9

D8

HPF_EN_CH7

HPF_CORNER _CH7[3:0]

FILTER_TYPE_CH7[2:0]

D7

D6

D5

D4

D3

0

D1

0

D0

FILTER_TYPE

_CH7[2:0]

SEL_ODD_

TAP_CH7

USE_FILTER_

CH7

DEC_RATE_CH7[2:0]

All bits default to '0' after reset.

Bit D15

Bit D14

Must write '0'

HPF_EN_CH7

This bit enables the HPF filter for channel 7.

HPF_CORNER _CH7[3:0]

Bits D[13:10]

Bits D[9:7]

Bits D[6:4]

These bits program the HPF corner for channel 7.

FILTER_TYPE_CH7[2:0]

These bits select the type of filter on channel 7.

DEC_RATE_CH7[2:0]

These bits set the decimation factor for the filter on channel 7.

Must write '0'

Bit D3

Bit D2

SEL_ODD_TAP_CH7

This bit enables the odd tap filter for channel 7.

Must write '0'

Bit D1

Bit D0

USE_FILTER_CH7

This bit enables the filter for channel 7.

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Table 33. Register 35h

D15

0

D14

D13

D12

D11

D10

D2

D9

D8

HPF_EN_CH8

D6

HPF_CORNER _CH8[3:0]

FILTER_TYPE_CH8[2:0]

D7

D5

D4

D3

0

D1

0

D0

FILTER_TYPE

_CH8[2:0]

SEL_ODD_

TAP_CH8

USE_FILTER_

CH8

DEC_RATE_CH8[2:0]

All bits default to '0' after reset.

Bit D15

Bit D14

Must write '0'

HPF_EN_CH8

This bit enables the HPF filter for channel 8.

HPF_CORNER _CH8[3:0]

Bits D[13:10]

Bits D[9:7]

Bits D[6:4]

These bits program the HPF corner for channel 8.

FILTER_TYPE_CH8[2:0]

These bits select the type of filter on channel 8.

DEC_RATE_CH8[2:0]

These bits set the decimation factor for the filter on channel 8.

Must write '0'

Bit D3

Bit D2

SEL_ODD_TAP_CH8

This bit enables the odd tap filter for channel 8.

Must write '0'

Bit D1

Bit D0

USE_FILTER_CH8

This bit enables the filter for channel 8.

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Table 34. Register 38h

D15

0

D14

0

D13

0

D12

0

D11

0

D10

0

D9

D8

0

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

D0

DATA_RATE[1:0]

All bits default to '0' after reset.

Bits D[15:2]

Bits D[1:0]

Must write '0'

DATA_RATE[1:0]

Bits D1 and D0 select the output data rate depending on the type of filter.

Table 35. Register 40h

D15

D14

0

D13

0

D12

0

D11

0

D10

0

D9

0

D8

0

ENABLE 40

D7

D6

D5

D4

D3

D2

D1

D0

ODD_EVEN_SEL

All bits default to '0' after reset.

Bits D15

Enable 40

0 = Disable bits D[7:0] of register 40h

1 = Enable bits D[7:0] of register 40h

Bits D[14:8]

Bits D[:0]

Must write '0'

ODD_EVEN_SEL[7:0]

8000 = Input pins IN1, IN3, IN5, and IN7 are interleaved

80FF = Input pins IN2, IN4, IN6, and IN8 are interleaved

For more details on this bit, see the Interleaving Mode section.

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Table 36. Register 42h

D15

D14

D13

0

D12

D11

D10

0

D9

0

D8

0

EN_PHASE_

DDR

0

D7

0

D6

D5

D4

0

D3

0

D2

0

D1

0

D0

0

PHASE_DDR1 PHASE_DDR0

All bits default to '0' after reset.

Bit D15

EN_PHASE_DDR

This bit enables LCLK phase programmability.

0 = Disable bits D[6:5] of register 42h

1 = Enable bits D[6:5] of register 42h

Bits D[14:7]

Bits D[6:5]

Must write '0'

PHASE_DDR[1:0]

These bits control the LCLK output phase relative to data.

Refer to the Programmable LCLK Phase section.

Bits D[4:0]

Must write '0'

Table 37. Register 45h

D15

0

D14

0

D13

0

D12

0

D11

0

D10

0

D9

0

D8

0

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

D0

PAT_DESKEW_SYNC[1:0]

All bits default to '0' after reset.

Bits D[15:2]

Bit D1

Must write '0'

PAT_DESKEW_SYNC1

0 = Inactive

1 = Sync pattern mode enabled; ensure that D0 is '0'

Bit D0

PAT_DESKEW_SYNC0

0 = Inactive

1 = Deskew pattern mode enabled; ensure that D1 is '0'

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Table 38. Register 46h

D15

D14

0

D13

D12

0

D11

D10

D2

D9

D8

ENABLE 46

FALL_SDR

EN_BIT_SER

D7

0

D6

0

D5

0

D4

D3

D1

0

D0

0

EN_MSB_

FIRST

EN_SDR

BTC_MODE

All bits default to '0' after reset. Note that bit D15 must be set to '1' to enable bits D[13:0].

Bit D15

ENABLE 46

0 = Disable bits D13, D[11:8] and D[4:2] of register 46h

1 = Enable bits D13, D[11:8] and D[4:2] of register 46h

Bit D14

Bit D13

Must write '0'

FALL_SDR

0 = The LCLK rising or falling edge comes at the edge of the data window when operating in

SDR output mode

1 = The LCLK rising or falling edge comes in the middle of the data window when operating

in SDR output mode

Bit D12

Must write '0'

EN_BIT_SER

Bits D[11:8]

0001 = 10-bit serialization mode enabled

0010 = 12-bit serialization mode enabled

0100 = 14-bit serialization mode enabled

Do not use any other bit combinations.

Bits D[7:5]

Bit D4

Must write '0'

EN_SDR

0 = DDR bit clock

1 = SDR bit clock

Bit D3

EN_MSB_FIRST

0 = LSB first

1 = MSB first

Bit D2

BTC_MODE

0 = Binary offset (ADC data output format)

1 = Twos complement (ADC data output format)

Bit D[1:0]

Must write '0'

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Programmable LVDS Mapping Mode Registers

Table 39. Register 50h

D15

D14

0

D13

0

D12

0

D11

D10

MAP_Ch1234_to_OUT2

D2 D1

MAP_Ch1234_to_OUT1

D9

D8

D0

ENABLE 50

D7

0

D6

0

D5

0

D4

0

D3

All bits default to '0' after reset.

Bit D15

ENABLE 50

0 = Disable bits D[11:8] and D[3:0] of register 50h.

1 = Enable bits D[11:8] and D[3:0] of register 50h.

Bits D[14:12], D[7:4]

Bits D[11:8]

Must write '0'

MAP_Ch1234_to_OUT2

These bits set the OUT2 pin pair to the channel data mapping selection.

MAP_Ch1234_to_OUT1

Bits D[3:0]

These bits set the OUT1 pin pair to the channel data mapping selection.

Table 40. Register 51h

D15

D14

0

D13

0

D12

0

D11

0

D10

0

D9

0

D8

0

ENABLE 51

D7

D6

D5

D4

D3

0

D2

0

D1

0

D0

0

MAP_Ch1234_to_OUT3

All bits default to '0' after reset.

Bit D15

ENABLE 51

0 = Disable bits D[7:4] of register 51h

1 = Enable bits D[7:4] of register 51h.

Bits D[14:8], D[3:0]

Bits D[7:4]

Must write '0'

MAP_Ch1234_to_OUT3

These bits set the OUT3 pin pair to the channel data mapping selection.

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Table 41. Register 52h

D15

D14

0

D13

0

D12

0

D11

0

D10

0

D9

D8

0

ENABLE 52

0

D7

0

D6

0

D5

0

D4

0

D3

D2

D1

D0

MAP_Ch1234_to_OUT4

All bits default to '0' after reset.

Bit D15

ENABLE 52

0 = Disable bits D[3:0] of register 52h

1 = Enable bits D[3:0] of register 52h

Bits D[14:4]

Bits D[3:0]

Must write '0'

MAP_Ch1234_to_OUT4

These bits set the OUT4 pin pair to the channel data mapping selection.

Table 42. Register 53h

D15

D14

0

D13

0

D12

0

D11

0

D10

0

D9

0

D8

0

ENABLE 53

D7

D6

D5

D4

D3

0

D2

0

D1

0

D0

0

MAP_Ch5678_to_OUT5

All bits default to '0' after reset.

Bit D15

ENABLE 53

0 = Disable bits D[7:4] of register 53h.

1 = Enable bits D[7:4] of register 53h.

Bits D[14:8], D[3:0]

Bits D[7:4]

Must write '0'

MAP_Ch5678_to_OUT5

These bits set the OUT5 pin pair to the channel data mapping selection.

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Table 43. Register 54h

D15

D14

D13

0

D12

0

D11

D10

MAP_Ch5678_to_OUT7

D2 D1

MAP_Ch5678_to_OUT6

D9

D8

D0

ENABLE 54

0

D7

0

D6

0

D5

0

D4

0

D3

All bits default to '0' after reset.

Bit D15

ENABLE 54

0 = Disable bits D[11:8] and D[3:0] of register 54h.

1 = Enable bits D[11:8] and D[3:0] of register 54h.

Bits D[14:12], D[7:4]

Bits D[11:8]

Must write '0'

MAP_Ch5678_to_OUT7

These bits set the OUT7 pin pair to the channel data mapping selection.

MAP_Ch5678_to_OUT6

Bits D[3:0]

These bits set the OUT6 pin pair to the channel data mapping selection.

Table 44. Register 55h

D15

D14

0

D13

0

D12

0

D11

0

D10

0

D9

0

D8

0

ENABLE 55

D7

D6

D5

D4

D3

0

D2

0

D1

0

D0

0

MAP_Ch5678_to_OUT8

All bits default to '0' after reset.

Bit D15

ENABLE 55

0 = Disable bits D[7:4] of register 55h.

1 = Enable bits D[7:4] of register 55h.

Bits D[14:8], D[3:0]

Bits D[7:4]

Must write '0'

MAP_Ch5678_to_OUT8

These bits set the OUT8 pin pair to the channel data mapping selection.

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Custom Coefficient Registers

Table 45. Registers 5Ah to 65h⁽¹⁾

D15

D14

0

D13

0

D12

D11

D10

D9

D8

D0

EN_CUSTOM_

FILT_CH1

0

COEFFn_SET_CH1[11:0]

D7

D6

D5

D4

D3

D2

D1

COEFFn_SET_CH1[11:0]

(1) n = 0 to 11.

All bits default to '0' after reset.

These registers are the custom coefficient registers for channel 1.

Bit D15

EN_CUSTOM_FILT_CH1

0 = Built-in coefficients are used

1 = Enables custom coefficients to be used

Bits D[14:12]

Bits D[11:0]

Must write '0'

COEFFn_SET_CH1[11:0]

These bits set the custom coefficient n for the channel 1 digital filter.

Table 46. Registers 66h to 71h⁽¹⁾

D15

D14

0

D13

0

D12

D11

D10

COEFFn_SET_CH2[11:0]

D2 D1

D9

D8

D0

EN_CUSTOM_

FILT_CH2

0

D7

D6

D5

D4

D3

COEFFn_SET_CH2[11:0]

(1) n = 0 to 11.

All bits default to '0' after reset.

These registers are the custom coefficient registers for channel 2.

Bit D15

EN_CUSTOM_FILT_CH2

0 = Built-in coefficients are used

1 = Enables custom coefficients to be used

Bits D[14:12]

Bits D[11:0]

Must write '0'

COEFFn_SET_CH2[11:0]

These bits set the custom coefficient n for the channel 2 digital filter.

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Table 47. Registers 72h to 7Dh⁽¹⁾

D15

D14

D13

0

D12

D11

D10

COEFFn_SET_CH3[11:0]

D2 D1

D9

D8

D0

EN_CUSTOM_

FILT_CH3

0

D7

D6

D5

D4

D3

COEFFn_SET_CH3[11:0]

(1) n = 0 to 11.

All bits default to '0' after reset.

These registers are the custom coefficient registers for channel 3.

Bit D15

EN_CUSTOM_FILT_CH3

0 = Built-in coefficients are used

1 = Enables custom coefficients to be used

Bits D[14:12]

Bits D[11:0]

Must write '0'

COEFFn_SET_CH3[11:0]

These bits set the custom coefficient n for the channel 3 digital filter.

Table 48. Registers 7Eh to 89h⁽¹⁾

D15

D14

0

D13

0

D12

D11

D10

COEFFn_SET_CH4[11:0]

D2 D1

D9

D8

D0

EN_CUSTOM_

FILT_CH4

0

D7

D6

D5

D4

D3

COEFFn_SET_CH4[11:0]

(1) n = 0 to 11.

All bits default to '0' after reset.

These registers are the custom coefficient registers for channel 4.

Bit D15

EN_CUSTOM_FILT_CH4

0 = Built-in coefficients are used

1 = Enables custom coefficients to be used

Bits D[14:12]

Bits D[11:0]

Must write '0'

COEFFn_SET_CH4[11:0]

These bits set the custom coefficient n for the channel 4 digital filter.

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Table 49. Registers 8Ah to 95h⁽¹⁾

D15

D14

0

D13

0

D12

D11

D10

D9

D8

D0

EN_CUSTOM_

FILT_CH5

0

COEFFn_SET_CH5[11:0]

D7

D6

D5

D4

D3

D2

D1

COEFFn_SET_CH5[11:0]

(1) n = 0 to 11.

All bits default to '0' after reset.

These registers are the custom coefficient registers for channel 5.

Bit D15

EN_CUSTOM_FILT_CH5

0 = Built-in coefficients are used

1 = Enables custom coefficients to be used

Bits D[14:12]

Bits D[11:0]

Must write '0'

COEFFn_SET_CH5[11:0]

These bits set the custom coefficient n for the channel 5 digital filter.

Table 50. Registers 96h to A1h⁽¹⁾

D15

D14

0

D13

0

D12

D11

D10

COEFFn_SET_CH6[11:0]

D2 D1

D9

D8

D0

EN_CUSTOM_

FILT_CH6

0

D7

D6

D5

D4

D3

COEFFn_SET_CH6[11:0]

(1) n = 0 to 11.

All bits default to '0' after reset.

These registers are the custom coefficient registers for channel 6.

Bit D15

EN_CUSTOM_FILT_CH6

0 = Built-in coefficients are used

1 = Enables custom coefficients to be used

Bits D[14:12]

Bits D[11:0]

Must write '0'

COEFFn_SET_CH6[11:0]

These bits set the custom coefficient n for the channel 6 digital filter.

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Table 51. Registers A2h to ADh⁽¹⁾

D15

D14

D13

0

D12

D11

D10

COEFFn_SET_CH7[11:0]

D2 D1

D9

D8

D0

EN_CUSTOM_

FILT_CH7

0

D7

D6

D5

D4

D3

COEFFn_SET_CH7[11:0]

(1) n = 0 to 11.

All bits default to '0' after reset.

These registers are the custom coefficient registers for channel 7.

Bit D15

EN_CUSTOM_FILT_CH7

0 = Built-in coefficients are used

1 = Enables custom coefficients to be used

Bits D[14:12]

Bits D[11:0]

Must write '0'

COEFFn_SET_CH7[11:0]

These bits set the custom coefficient n for the channel 7 digital filter.

Table 52. Registers AEh to B9h⁽¹⁾

D15

D14

0

D13

0

D12

D11

D10

COEFFn_SET_CH8[11:0]

D2 D1

D9

D8

D0

EN_CUSTOM_

FILT_CH8

0

D7

D6

D5

D4

D3

COEFFn_SET_CH8[11:0]

(1) n = 0 to 11.

All bits default to '0' after reset.

These registers are the custom coefficient registers for channel 8.

Bit D15

EN_CUSTOM_FILT_CH8

0 = Built-in coefficients are used

1 = Enables custom coefficients to be used

Bits D[14:12]

Bits D[11:0]

Must write '0'

COEFFn_SET_CH8[11:0]

These bits set the custom coefficient n for the channel 8 digital filter.

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Table 53. Register BEh

D15

D14

0

D13

0

D12

D11

D10

0

D9

D8

EN_LVDS_

PROG

0

DELAY_DATA_R[1:0]

D7

D6

D5

D4

D3

D2

D1

D0

DELAY_LCLK_R[2:0]

DELAY_DATA_F[1:0]

DELAY_LCLK_F[2:0]

All bits default to '0' after reset.

Bit D15

This bit enables LVDS edge delay programmability.

Must write '0'

Bits D[14:10]

Bits D[9:8]

Bits D[7:5]

Bits D[4:3]

Bits D[2:0]

Refer to Table 68 for settings.

Refer to Table 69 for settings.

Refer to Table 68 for settings.

Refer to Table 69 for settings.

Table 54. Register F0h

D15

D14

0

D13

0

D12

0

D11

0

D10

0

D9

0

D8

0

EN_EXT_REF

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

All bits default to '0' after reset.

The EN_HIGH_ADDRS register bit (register 01h, bit D4) must be set to '1' to allow access to this register.

Bit D15

EN_EXT_REF

0 = Internal reference mode (default)

1 = External reference mode enabled; apply the reference voltages on the REFT and REFB

pins

Bits D[14:0]

Must write '0'

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APPLICATION INFORMATION

THEORY OF OPERATION

The ADS5296A is a low-power, multichannel, analog-to-digital converter (ADC) that can be operated at sample

rates up to 200 MSPS from a single 1.8-V supply. At the core, the device consists of eight 12-bit ADCs with

sample rates up to 80 MSPS. By interleaving every pair of 12-bit ADCs, the effective sample rate can be doubled

to 160 MSPS. A mode exists to operate the device as a 10-bit ADC, in which the effective sample rate can be

increased to 200 MSPS with interleaving. In both the interleaving modes (12-bit and 10-bit), the device operates

as a 4-channel ADC.

When interleaving is disabled, the device can also be operated as an 8-channel 10-bit ADC up to 100 MSPS for

systems where the SNR of the 10-bit ADC is sufficient. To summarize, the device can be configured as:

•

An 8-channel, 12-bit ADC without interleaving, with sample rates up to 80 MSPS

An 8-channel, 10-bit ADC without interleaving, with sample rates up to 100 MSPS

A 4-channel, 12-bit ADC with interleaving, with sample rates up to 160 MSPS

A 4-channel, 10-bit ADC with interleaving, with sample rates up to 200 MSPS

ANALOG INPUT

The analog input consists of a switched-capacitor-based, differential sample-and-hold architecture, as shown in

Figure 77. This differential topology results in very good ac performance even for high input frequencies at high

sampling rates. The INP and INM pins must be externally biased around a common-mode voltage of 0.95 V,

available on the VCM pin. For a full-scale differential input, each input pin (IN_p, IN_n) must swing symmetrically

between VCM + 0.5 V and VCM – 0.5 V, resulting in a 2-V_PPdifferential input swing. The input sampling circuit

has a high 3-dB bandwidth that extends up to 500 MHz (measured from the input pins to the sampled voltage).

S

SZ

R_ON

25 W

R_ON

C_PAR3

100 W

0.3 pF

Sampling

Switch

L_PKG

2 nH

S

Sampling

Capacitor

15 W

INP

R_ON

10 W

C_BOND

0.5 pF

C_PAR2

1 pF

C_SAMP

2.6 pF

1 kW

R_ESR

200 W

C_PAR1

1.5 pF

R_ON

40 W

VCM

L_PKG

2 nH

1 kW

C_SAMP

2.6 pF

R_ON

10 W

15 W

INN

C_BOND

0.5 pF

C_PAR2

1 pF

Sampling

Capacitor

S

R_ESR

Sampling

Switch

200 W

R_ON

25 W

100 W

C_PAR3

0.3 pF

S

SZ

Figure 77. Analog Input Equivalent Circuit

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Drive Circuit Requirements

For optimum performance, the analog inputs must be driven differentially. This architecture improves the

common-mode noise immunity and even-order harmonic rejection. A small resistor (10 Ω to 20 Ω) in series with

each input pin is recommended to damp out ringing caused by package parasitics. The drive circuits in Figure 78

and Figure 79 show an R-C filter across the analog input pins. The purpose of the filter is to absorb the glitches

caused by the opening and closing of the sampling capacitors. Figure 78 is recommended for driving the analog

inputs in interleaving mode and Figure 79 can be used for non-interleaving mode .

The analog input pins of the ADC have an internal 1k-Ω termination resistance connected to VCM voltage (see

Figure 77 ) which allows external signals to be ac-coupled to the ADC input pins. During the sampling process, a

common-mode current is drawn from VCM through the 1-kΩ termination. This current scales with sampling

frequency (approximately 1 µA per MSPS) and results in a drop in the common-mode voltage of the input pins.

The recommended range of input common-mode voltage is VCM ± 50 mV. Therefore, at higher sample rates, TI

recommends connecting an external 25-Ω to 100-Ω termination resistor to VCM. Figure 80 and Figure 81 show

the differential input resistance and capacitance across frequency.

20 ꢀ

0.1 PF

10 ꢀ

5 ꢀ

INP

100 ꢀ

25 ꢀ

VCM

25 ꢀ

6.8 pF

Device

3.3 pF

Device

100 ꢀ

0.1 PF

INN

20 ꢀ

10 ꢀ

5 ꢀ

Figure 78. DC-Coupled Drive Circuit with RCR

Figure 79. AC-Coupled Drive Circuit

2

4

3.5

3

1.5

1

2.5

2

0.5

1.5

1

0

100 200 300 400 500 600 700 800 900 1000

0

100 200 300 400 500 600 700 800 900 1000

Frequency (MHz)

G043

G044

Figure 80. ADC Differential Input Resistance (R_IN)

vs Frequency

Figure 81. ADC Differential Input Capacitance (C_IN)

vs Frequency

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Large- and Small-Signal Input Bandwidth

The small-signal bandwidth of the analog input circuit is high, approximately 500 MHz. When using an amplifier

to drive the ADS5296A, the total amplifier noise up to the small-signal bandwidth must be considered. The large-

signal bandwidth of the device depends on the amplitude of the input signal. The ADS5296A supports a 2-V_PP

amplitude for input signal frequencies up to 90 MHz. For higher frequencies, the amplitude of the input signal

must be decreased proportionally. For example, at 180 MHz, the device supports a maximum 1-V_PPsignal.

INTERLEAVING MODE

The interleaving mode in the device can be used to sample analog inputs at frequencies greater than 100 MSPS.

A pair of ADCs are used in interleaving mode, both of which sample the same analog input signal. The sampling

instants of the two ADCs are interleaved in such a way that while one ADC samples the input at every odd edge

of the device input clock, the second ADC samples the input at every even edge of the input clock, as shown in

Figure 82.

Sample

N + 15

Sample

N + 16

Sample

N + 17

Sample

N + 14

Sample

N + 18

Sample

N + 13

Sample

N + 4

Sample

N + 3

Sample

N + 12

Sample

N + 2

Sample

N + 1

Sample

N

INP

CLKP

Sampling Clock

ADCn

Internal

Signals

Sampling Clock

ADCn+1

N

N + 2

N + 4

…………

………… ……

…………

OUTn

D9

D0

D9

D0

D9

D0

D9

D0

D9

D0

D1

…………

OUTn+1

N + 1

N + 3

N + 5

NOTE: n = 1, 3, 5, or 7.

Figure 82. Interleaving Mode Latency Timing Diagram

Note that in this mode, device input clock frequency is actually 2x times the sampling rate of each ADC. For

example, when a 200-MHz clock input is applied, each ADC in the pair samples at 100 MHz, but the sampling

instants of both ADCs are staggered (or offset) by one 200-MHz clock cycle. Each ADC converts the sampled

values and outputs the data over separate LVDS pairs. The receiver used to capture the data from the device

[either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA)] must combine

the data from the two LVDS pairs and reconstruct the data stream at 200 MSPS (see Figure 83). In this mode,

the device operates as a 4-channel ADC because the interleaving operation requires two ADCs per channel.

After applying a reset and enabling interleaving mode (EN_INTERLEAVE = 1), the four interleaved ADC

channels sample the analog inputs at the odd pins (IN1, IN3, IN5, and IN7). A mode exists where the analog

inputs at the even pins can be sampled by using the ODD_EVEN_SEL register bits. Instead of using the register

bits, the INTERLEAVE_MUX pin can be used to select between the odd and even input pins (see Table 55).

As Figure 82 shows, in the interleaving mode, the device input clock is divided by two to generate two sampling

clocks which are 180° out of phase with each other. The odd ADC (ADC1, ADC3, ADC5, ADC7) in each

interleaving pair uses one sampling clock while the even ADC (ADC2, ADC4, ADC6, ADC8) in the pair uses the

other sampling clock. When using multiple ADS5296A devices, ensure that the sampling clock for the odd (and

even) ADCs in every chip are synchronized. This can be achieved by using the SYNC input signal; see the

Synchronization Using the SYNC Pin section for a description of the SYNC functionality.

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Table 55. Interleaving Mode

PIN⁽¹⁾

REGISTER BITS

EN_MUX_REG ODD_EVEN_SEL

MODE

EN_

INTERLEAVE

INTERLEAVE_MUX

No interleaving

•

8-channel ADC mode

IN1 ↔ OUT1, IN2 ↔ OUT2

Don't care

Low

0

1

0

1

0

1

0

1

8000h

Don't care

80FFh

•

IN3 ↔ OUT3, IN4 ↔ OUT4

IN5 ↔ OUT5, IN6 ↔ OUT6

IN7 ↔ OUT7, IN8 ↔ OUT8

0

1

No interleaving

•

8-channel ADC mode

IN1 ↔ OUT2, IN2 ↔ OUT1

Don't care

High

•

IN3 ↔ OUT4, IN4 ↔ OUT3

IN5 ↔ OUT6, IN6 ↔ OUT5

IN7 ↔ OUT8, IN8 ↔ OUT7

Don't care

8000h

Interleaving enabled

•

4-channel ADC mode

IN1 ↔ OUT1, OUT2

Don't care

Low

•

IN3 ↔ OUT3, OUT4

IN5 ↔ OUT5, OUT6

IN7 ↔ OUT7, OUT8

Don't care

80FFh

Interleaving enabled

•

4-channel ADC mode

IN2 ↔ OUT1, OUT2

Don't care

High

•

IN4 ↔ OUT3, OUT4

IN6 ↔ OUT5, OUT6

IN8 ↔ OUT7, OUT8

Don't care

(1) INTERLEAVE_MUX has an internal pull-up resistor to supply.

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The block diagrams for interleaving even input pins and interleaving odd input pins are shown in Figure 83 and

Figure 84.

EN_INTERLEAVE Register Bits = 1, EN_MUX_REG = 0, and ODD_EVEN_SEL = 8000h,

or

EN_INTERLEAVE Register Bits = 1, EN_MUX_REG = 1, and INTERLEAVE_MUX Pin Low

OUT1

IN1

Sample N

IN1

Sample N+2

10 BIT

ADAC

ADC 1

IN1_p, IN1_n

IN2_p, IN2_n

OUT2

10 BIT

ADAC

ADC 2

IN1

Sample N+1

IN1

Sample N+3

OUT3

OUT4

IN3

Sample N

IN3

Sample N+2

IN3_p, IN3_n

IN4_p, IN4_n

IN3

Sample N+1

Sample N+3

OUT5

OUT6

IN5

Sample N

IN5

Sample N+2

IN5_p, IN5_n

IN6_p, IN6_n

IN5

Sample N+1

Sample N+3

OUT7

OUT8

IN7

Sample N

IN7

Sample N+2

IN7_p, IN7_n

IN8_p, IN8_n

IN7

Sample N+1

Sample N+3

Figure 83. Odd Input Pins, Interleaved

EN_INTERLEAVE Register Bits = 1, EN_MUX_REG = 0, and ODD_EVEN_SEL = 80FFh,

or

EN_INTERLEAVE Register Bits = 1, EN_MUX_REG = 1, and INTERLEAVE_MUX Pin High

OUT1

OUT2

IN2

Sample N

IN2

Sample N+2

10 BIT

ADC 1

ADAC

IN1_p, IN1_n

IN2_p, IN2_n

10 BIT

ADC 2

ADAC

IN2

Sample N+1

IN2

Sample N+3

OUT3

OUT4

IN4

Sample N

IN4

Sample N+2

IN3_p, IN3_n

IN4_p, IN4_n

IN4

Sample N+1

Sample N+3

OUT5

OUT6

IN6

Sample N

IN6

Sample N+2

IN5_p, IN5_n

IN6_p, IN6_n

IN6

Sample N+1

Sample N+3

OUT7

OUT8

IN8

Sample N

IN8

Sample N+2

IN7_p, IN7_n

IN8_p, IN8_n

IN8

Sample N+1

Sample N+3

Figure 84. Even Input Pins, Interleaved

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CLOCK INPUT

The device can operate with both single-ended (CMOS) and differential input clocks (such as sine wave,

LVPECL, and LVDS). Operating with a low-jitter differential clock is recommended for good SNR performance,

especially at input frequencies greater than 30 MHz. In differential mode, the clock inputs are internally biased to

a 0.95-V common-mode voltage. While driving with an external LVPECL or LVDS driver, TI recommends ac-

coupling the clock signals so that the clock pins are correctly biased to the common-mode voltage (0.95 V). To

operate using a single-ended clock, connect a CMOS clock source to CLKP and tie CLKN to GND. The device

automatically detects the presence of a single-ended clock without requiring any configuration and disables

internal biasing. Typical clock termination schemes are shown in Figure 85, Figure 86, Figure 87, and Figure 88.

Figure 89 and Figure 90 show the equivalent circuit of the clock pins in both single-ended and differential modes.

0.1 mF

CLKP

R_TERM

Differential

LVPECL

Clock Input

Differential

Sine-Wave

Clock Input

0.1 mF

CLKN

R_TERM

Figure 85. Differential Sine-Wave Clock

Driving Circuit

Figure 86. Differential LVPECL Clock

Driving Circuit

0.1 mF

CMOS

Clock Input

CLKP

Differential

LVDS

Clock Input

R_TERM

0.1 mF

CLKN

Figure 87. Differential LVDS Clock Driving Circuit

Figure 88. Single-Ended Clock Driving Circuit

Sampling clock

CLKP

Internal single ended

clock buffer

4kQ

VCM_Internal

4kQ

22kQ

Sampling clock

VCM_Internal

Internal differential

clock buffer

22kQ

CLKN

Device

Figure 89. Input Clock Equivalent Circuit:

Single-Ended Mode

Figure 90. Input Clock Equivalent Circuit:

Differential Mode

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EXTERNAL REFERENCE MODE OF OPERATION

For normal operation, the device requires two reference voltages (REFT and REFB) that are generated internally

by default, as shown in Figure 91. The value of the reference voltage determines the actual ADC full-scale input

voltage, as shown in Equation 1:

Full-Scale Input Voltage = 2 ´ (V_REFT- V_REFB

)

(1)

Device

EN_EXT_REF

Internal

Reference

REFT

REFB

REF Amp

ADC

Figure 91. Reference Equivalent Circuit

Any error in the reference results in a deviation of the full-scale input range from its ideal value of 2.0 V_PP, as

shown in Equation 2:

Error in Full-Scale Voltage = 2x [Error in (V_REFT– V_REFB)]

(2)

The reference inaccuracy results in a gain error, which is defined as Equation 3:

100

Gain Error (%) = Error in Full-Scale Voltage ´

Ideal Full-Scale Voltage

100

= 2x [Error in (V_REFT- V_REFB)] ´

2.0

(3)

To minimize gain error, the internal reference voltages are trimmed to an accuracy of ±1.5%. To obtain even

lower gain error, the device supports an external reference mode of operation. In this mode, the internal

reference amplifiers are powered down and an external amplifier must force the reference voltages on the REFT

and REFB pins. For example, this mode can be used to ensure that multiple ADS5296A devices in the system

have nearly the same full-scale voltage.

To enable external reference mode, set the register bits as shown in Table 56. These settings power-down the

internal reference amplifier and the two reference voltages can be forced directly on the REFT and REFB pins as

V_REFT= 1.45 V and V_REFB= 0.45 V, respectively.

Table 56. External Reference Function

FUNCTION

EN_HIGH_ADDRS

EN_EXT_REF

External reference using the REFT, REFB pins

1

Because the internal reference amplifiers are powered down, the accuracy of the full-scale voltage is determined

by the accuracy of (V_REFT– V_REFB), where V_REFTis the voltage forced on REFT and V_REFBis the voltage forced

on REFB. Note that although the nominal value of (V_REFT– V_REFB) = 1.0 V, ensure that Equation 4 is met:

[(V_REFT+ V_REFB) / 2 = 0.950 V ± 50 mV]

(4)

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Figure 92 shows an example of driving the reference pins. The 1-µF bypass capacitor helps provide the

switching current drawn by the REFT and REFB pins. The external amplifier must provide an average current of

5 mA or less at the maximum sample rate. Performance in the external reference mode depends on sampling

speed. At low sampling speeds (for instance, 20 MSPS), performance is the same as that of an internal

reference. At higher speeds, performance degrades because of the effect of parasitic bond-wire inductance of

the REF pins. Figure 93 highlights the difference in SNR between the external and internal reference modes.

R_S

+

REFT

V_T

V_B

-

1 mF

Precision

Reference

Device

+

R_S

REFB

-

1 mF

Figure 92. Driving Reference Inputs in External Reference Mode

73

SNR in External Reference

SNR in Internal Reference

72

71

70

69

68

67

66

65

20

30

40

50

60

70

80

Sampling Frequency (MSPS)

G045

Figure 93. SNR in Internal and External Reference Mode

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LOW-FREQUENCY NOISE SUPPRESSION

The low-frequency noise suppression (LFNS) mode is particularly useful in applications where good noise

performance is desired in the low-frequency band of dc to 1 MHz. By setting this mode, the low-frequency noise

spectrum band around dc is shifted to a similar band around f_S/ 2 (or the Nyquist frequency). As a result, the

noise spectrum from dc to approximately 1 MHz improves significantly, as shown in Figure 94, Figure 95, and

Figure 96.

This function can be selectively enabled in each channel using the LFNS_CH register bits. Figure 94, Figure 95,

and Figure 96 show the effect of this mode on the spectrum.

0

−10

0

−10

SNR = 70.3 dBFS

SINAD = 70.1 dBFS

SFDR = 82.7 dBc

THD = 82.2 dBc

LF Noise Suppression Enabled

LF Noise Suppression Disabled

−20

−30

−40

−50

−60

−70

−80

−70

−90

−80

−100

−110

−120

−130

−140

−90

−100

−110

−120

0

10

20

30

40

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Frequency (MHz)

1

Frequency (MHz)

G029

G030

Figure 94. Full-Band FFT, 5-MHz Input

(80-MHz FS with LFNS Enabled)

Figure 95. 0-MHz to 1-MHz FFT, 5-MHz Input

(80-MHz FS with LFNS Enabled)

0

−10

LF Noise Suppression Enabled

LF Noise Suppression Disabled

−20

−30

−40

−50

−60

−70

−80

−90

−100

−110

−120

−130

−140

39 39.1 39.2 39.3 39.4 39.5 39.6 39.7 39.8 39.9 40

Frequency (MHz)

G031

Figure 96. 39-MHz to 40-MHz FFT, 5-MHz Input

(80-MHz FS with LFNS Enabled)

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DIGITAL PROCESSING BLOCKS

The device integrates a set of commonly-used digital functions that can be used to ease system design. These

functions are shown in Figure 97 and are described in the following sections.

LVDS Outputs

Test

Patterns,

Ramp

Channel 1 ADC Data

12-Bit

ADC

Channel 1

Serializer

Wire 1

OUT1

Average of

2 Channels

Built-In Coefficients

Decimate

By 2 or 4

24-Tap Filter

(Even Tap)

ADC Data:

Channel 2

Channel 3

Channel 4

Channel 2

23-Tap Tilter

(Odd Tap)

Serializer

Wire 1

Average of

4 Channels

OUT2

OUT3

OUT4

Mapper

Custom Coefficients

Decimate

By 2, 4,

or 8

24-Tap Filter

(Even Tap)

4:4

Multiplexer

Channel 3

Gain

(0 dB to 12 dB,

in 1-dB steps)

Serializer

Wire 1

23-Tap Filter

(Odd Tap)

12-Tap Filter

Channel 4

Serializer

Wire 1

Digital Processing Block for Channel 1

Digital Processing Block for Channel 2

12-Bit

ADC

Channel 2 ADC Data

Channel 3 ADC Data

12-Bit

ADC

Digital Processing Block for Channel 3

Digital Processing Block for Channel 4

12-Bit

ADC

Channel 4 ADC Data

1/2 of Device

Figure 97. Digital Processing Block Diagram

Digital Gain

The device includes programmable digital gain settings from 0 dB to 12 dB, in 1-dB steps. The benefit of digital

gain is obtaining improved SFDR performance. However, SFDR improvement is achieved at the expense of

SNR; for each gain setting, SNR degrades by approximately 1 dB. Therefore, gain can be used to trade-off

between SFDR and SNR.

For each gain setting, the supported analog input full-scale range scales proportionally, as shown in Table 57.

After reset, the device comes up in 0-dB gain mode. To use other gain settings, program the GAIN_CHn[3:0]

register bits.

Table 57. Analog Full-Scale Range Across Gains

GAIN_CHn[3:0]

DIGITAL GAIN (dB)

ANALOG FULL-SCALE INPUT (V_PP)

0000

0001

0

2

1

1.78

1.59

1.42

1.26

1.12

1

0010

2

0011

3

0100

4

0101

5

0110

6

0111

7

0.89

0.8

1000

8

1001

9

0.71

0.63

0.56

0.5

1010

10

11

1011

1100

12

Other combinations

Do not use

—

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Digital Filter

The digital processing block includes the option to filter and decimate the ADC data outputs digitally. Various

filters and decimation rates are supported: decimation rates of 2, 4, and 8, and low-pass, high-pass, and band-

pass filters are available.

The filters are internally implemented as 24-tap symmetric finite impulse response (FIR) filters (even-tap) using

the predefined coefficients of Equation 5:

y(n) =

1

2¹¹

´ [h0.x(n) + h1.x(n-1) + h2.x(n-2) + ... + h11.x(n-11) + h12.x(n-12) + ... + h1.x (n-22) + h0.x(n-23)]

(5)

Alternatively, some filters can be configured as 23-tap symmetric FIR filters (odd-tap), as described in

Equation 6:

y(n) =

1

2¹¹

´ [h0.x(n) + h1.x(n-1) + h2.x(n-2) + ... + h10.x(n-10) + h11.x(n-11) + h10.x(n-12) + ... + h1.x (n-21) + h0.x(n-22)]

(6)

In Equation 5 and Equation 6, h0 through h11 are 12-bit, signed, twos complement representations of the

coefficients (–2048 to +2047). x(n) is the filter input data sequence and y(n) is the filter output sequence.

Details of the registers used for configuring the digital filters are described in the digital filter registers (registers

29h, 2Eh, 2Fh, 30h, 31h, and 38h) and Table 58. Table 58 gives a summary of the register bits to be used for

each filter type.

Table 58. Digital Filters

USE_

FILTER_

CHn

EN_

CUSTOM_

FILT_CHn

DATA_ DEC_RATE

RATE

FILTER_

TYPE_CHn

ODD_

TAP_CHn

EN_DIG_

FILTER

DECIMATION

TYPE OF FILTER

_CHn⁽¹⁾

Built-in, low-pass, odd-tap filter

(pass band = 0 to f_S/ 4)

01

000

001

010

011

1

0

1

0

1

Decimate-by-2

Built-in, high-pass, odd-tap filter

(pass band = 0 to f_S/ 4)

01

10

000

001

Built-in, low-pass, even-tap filter

(pass band = 0 to f_S/ 8)

Built-in, first band-pass, even-tap filter

(pass band = f_S/ 8 to f_S/ 4)

Decimate-by-4

Built-in, second band-pass,

even-tap filter

10

001

100

0

1

0

1

(pass band = f_S/ 4 to 3 f_S/ 8)

Built-in, high-pass, odd-tap filter

(pass band = 3 f_S/ 8 to f_S/ 2)

10

01

10

11

00

001

000

001

100

011

101

000

1

0

1

Custom filter

(user-programmable coefficients)

Decimate-by-2

Decimate-by-4

Decimate-by-8

0 or 1

0

Custom filter

(user-programmable coefficients)

Custom filter

(user-programmable coefficients)

12-tap filter, no Custom filter

decimation (user-programmable coefficients)

(1) The DEC_RATE_CHn value must be the same for all channels.

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Predefined Coefficients

The built-in filter types (low pass, high pass, and band pass) use predefined coefficients. The frequency

response of the built-in filters is shown in Figure 98 and Figure 99.

The predefined coefficients for the decimate-by-2 and decimate-by-4 filters are listed in Table 59 and Table 60,

respectively.

20

10

40

30

Low-Pass

High-Pass

Low-Pass

Band-Pass 1

Band-Pass 2

High-Pass

20

0

10

−10

−20

−30

−40

−50

−60

−70

−80

0

−10

−20

−30

−40

−50

−60

−70

−80

0

0.1

0.2

0.3

0.4

0.5

0

0.1

0.2

0.3

0.4

0.5

Normalized Frequency (f_IN/f_S)

G024

G025

Figure 98. Filter Response (Decimate-by-2)

Figure 99. Filter Response (Decimate-by-4)

Table 59. Predefined Coefficients for Decimate-by-2 Filters

DECIMATE-BY-2 FILTERS

COEFFICIENTS

LOW-PASS

HIGH-PASS

–22

h0

h1

3

0

–65

h2

5

–52

h3

1

30

h4

–27

–2

66

h5

–35

h6

73

–107

38

h7

3

h8

–178

–4

202

h9

–41

h10

h11

636

1024

–644

1061

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Table 60. Predefined Coefficients for Decimate-by-4 Filters

DECIMATE-BY-4 FILTERS

COEFFICIENTS

LOW-PASS

–17

–50

71

1st BAND-PASS

2nd BAND-PASS

HIGH-PASS

h0

h1

–7

19

–34

–101

43

40

–15

–95

22

h2

–47

127

73

h3

46

h4

24

58

–8

h5

–42

–100

–97

8

0

–28

–5

–81

106

–62

–97

310

–501

575

h6

86

h7

117

–190

–464

–113

526

–179

294

86

h8

h9

202

414

554

h10

h11

–563

352

Custom Filter Coefficients

In addition to the built-in filters described in the Predefined Coefficients section, customers also have the option

of using their own custom, 12-bit, signed coefficients. Because of the symmetric FIR implementation of the filters,

only 12 coefficients can be specified with the configurations in Equation 5 or Equation 6. These coefficients (h0

to h11) must be configured in the custom coefficient registers, as shown in Equation 7:

Register Content = 12-Bit Signed Representation of (Real Coefficient Value × 2¹¹)

(7)

The 12 custom coefficients must be loaded into 12 separate registers for each channel (refer to the custom

coefficient registers, 5Ah to B9h). The MSB bit of each coefficient register determines whether built-in filters or

custom filters are used. If the EN_CUSTOM_FILT MSB bit is reset to '0', then built-in filter coefficients are used.

Otherwise, custom coefficients are used.

Custom Filter without Decimation

Another mode is available that enables the use of the digital filter without decimation. In this mode, the filter

behaves similar to a 12-tap symmetric FIR filter, as shown in Equation 8:

y(n) =

1

2¹¹

´ [h6.x(n) + h7.x(n-1) + h8.x(n-2) + h9.x(n-3) + h10.x(n-4) + h11.x(n-5) +

+ h11.x(n-6) + h10.x(n-7) + h9.x(n-8) + h8.x(n-9) + h7.x(n-10) + h6.x (n-11)]

(8)

In Equation 8, h6 through h11 are 12-bit, signed, twos complement representations of the coefficients (–2048 to

+2047). x(n) is the filter input data sequence and y(n) is the filter output sequence.

In this mode, because the filter is implemented as a 12-tap symmetric FIR, only six custom coefficients must be

specified and loaded in registers h6 to h11 (refer to the custom coefficient registers, 5Ah to B9h). To enable this

mode, use the register setting specified in bit 15 of registers AEh to B9h.

Digital High-Pass Filter

In addition to the 12 tap filters described previously, the digital processing block also includes a separate high-

pass filter for each channel. The high-pass corner frequency can be programmed using bits D[14:10] in register

2Eh.

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Digital Averaging

The device includes an averaging function where the ADC digital data from two (or four) channels can be

averaged. The averaged data are output on specific LVDS channels. Table 61 shows the combinations of the

input channels that can be averaged and the LVDS channels on which the averaged data are available.

Table 61. Using Channel Averaging

OUTPUT WHERE

AVERAGED CHANNELS AVERAGED DATA ARE

AVAILABLE AT

REGISTER SETTINGS

1, 2

OUT1

OUT3

OUT4

OUT2

OUT1

OUT4

OUT5

OUT7

OUT8

OUT6

OUT5

OUT8

Set AVG_OUT1 = 10 and EN_CHANNEL_AVG = 1

Set AVG_OUT3 = 11 and EN_CHANNEL_AVG = 1

Set AVG_OUT4 = 10 and EN_CHANNEL_AVG = 1

Set AVG_OUT2 = 11 and EN_CHANNEL_AVG = 1

Set AVG_OUT1 = 11 and EN_CHANNEL_AVG = 1

Set AVG_OUT4 = 11 and EN_CHANNEL_AVG = 1

Set AVG_OUT5 = 10 and EN_CHANNEL_AVG = 1

Set AVG_OUT7 = 11 and EN_CHANNEL_AVG = 1

Set AVG_OUT8 = 10 and EN_CHANNEL_AVG = 1

Set AVG_OUT6 = 11 and EN_CHANNEL_AVG = 1

Set AVG_OUT5 = 11 and EN_CHANNEL_AVG = 1

Set AVG_OUT8 = 11 and EN_CHANNEL_AVG = 1

3, 4

1, 2, 3, 4

5, 6

7, 8

5, 6, 7, 8

Performance with Digital Processing Blocks

In applications where higher SNR performance is desired, digital processing blocks (such as averaging and

decimation filters) can be used advantageously to achieve higher performance. Table 62 shows the improvement

in SNR that can be achieved compared to the default value, using these modes.

Table 62. SNR Improvement Using Digital Processing

TYPICAL IMPROVEMENT IN

MODE

TYPICAL SNR (dB)⁽¹⁾

SNR (dB)

Default

70.4

75.4

76.7

75

NA

5

With decimate-by-2 filter enabled

With decimate-by-4 filter enabled

With two channels averaged

With four channels averaged

6.3

4.6

5.4

75.8

(1) In all modes (except default), 14x serialization is used to capture data.

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PROGRAMMABLE MAPPING BETWEEN INPUT CHANNELS AND OUTPUT PINS

The device has eight pairs of LVDS channel outputs. The mapping of ADC channels to LVDS output channels is

programmable to allow for flexibility in board layout. Control register mapping is shown in Table 63. The eight

LVDS channel outputs are split into two groups of four LVDS pairs. Within each group, four ADC input channels

can be multiplexed to the four LVDS pairs.

Table 63. Mapping Control Registers

ADDRESS

(Hex)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

NAME

1

X

MAP_Ch1234_to_OUT1

MAP_Ch1234_to_OUT2

MAP_Ch1234_to_OUT3

MAP_Ch1234_to_OUT4

MAP_Ch5678_to_OUT5

MAP_Ch5678_to_OUT6

MAP_Ch5678_to_OUT7

MAP_Ch5678_to_OUT8

50

X

51

52

53

X

54

55

X

Input channels 1 to 4 can be mapped to any LVDS output (OUT1 to OUT4) using the MAP_CH1234_TO_OUTn

bits, as shown in Table 64.

Table 64. Mapping Analog Inputs IN1-IN4 to LVDS Outputs OUT1-4

MAP_CH1234_TO_OUTN[3:0]⁽¹⁾

MAPPING

ADC input channel IN1 to OUTn

0000

0010

0100

0110

1xxx

ADC input channel IN2 to OUTn

ADC input channel IN3 to OUTn

ADC input channel IN4 to OUTn

LVDS output buffer OUTn powered down

(1) n = 1, 2, 3, or 4.

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Similarly, input channels 5 to 8 can be mapped to any LVDS output (OUT5 to OUT8) using the

MAP_CH5678_TO_OUTn bits, as shown in Table 65. Both multiplexing options are controlled by registers 50h to

55h. The channel mapping block diagram is illustrated in Figure 100.

Table 65. Mapping analog inputs IN8-IN8 to LVDS outputs OUT5-8

MAP_CH5678_TO_OUTN[3:0]⁽¹⁾

MAPPING

ADC input channel IN8 to OUTn

0000

0010

0100

0110

1xxx

ADC input channel IN7 to OUTn

ADC input channel IN6 to OUTn

ADC input channel IN5 to OUTn

LVDS output buffer OUTn powered down

(1) n = 5, 6, 7, or 8.

Channel 8 Data

MAP_CH5678_to_OUTn[3:0] = 0000

Channel 7 Data

MAP_CH5678_to_OUTn[3:0] = 0010

(1)

OUTn

Channel 6 Data

MAP_CH5678_to_OUTn[3:0] = 0100

MAP_CH5678_to_OUTn[3:0] = 1xxx,

the unused OUTn LVDS buffer is powered down.

Channel 5 Data

MAP_CH5678_to_OUTn[3:0] = 0110

Channel 4 Data

MAP_CH1234_to_OUTn[3:0] = 0110

Channel 3 Data

MAP_CH1234_to_OUTn[3:0] = 0100

(1)

OUTn

Channel 2 Data

MAP_CH1234_to_OUTn[3:0] = 0010

MAP_CH1234_to_OUTn[3:0] = 1xxx,

the unused OUTn LVDS buffer is powered down.

Channel 1 Data

MAP_CH1234_to_OUTn[3:0] = 0000

(1) For channels 1 to 4, n = 1, 2, 3, 4. For channels 5 to 8, n = 5, 6, 7, 8.

Figure 100. Channel Mapping

The default mapping is shown in Table 66.

Table 66. Default Mapping After Reset

ANALOG INPUT CHANNEL

Channel IN1

LVDS OUTPUT

OUT1

Channel IN2

OUT2

Channel IN3

OUT3

Channel IN4

OUT4

Channel IN5

OUT5

Channel IN6

OUT6

Channel IN7

OUT7

Channel IN8

OUT8

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SYNCHRONIZATION USING THE SYNC PIN

The SYNC pin can be used to synchronize:

•

The data output across channels within the same device or

The data from channels across multiple devices when decimation filters are used

The odd and even ADC sampling instants across multiple devices in interleaving mode

When decimation filters are used (if the decimate-by-2 filter is enabled, for example), then effectively the device

outputs one digital code for every two analog input samples. If the SYNC pulse is not used, then the filters are

not synchronized (even within a device). When the filters are not synchronized, one channel may be transmitting

codes corresponding to input samples N, N+1, and so on, while another channel may be transmitting codes

corresponding to N+1, N+2, and so on.

To achieve synchronization across multiple devices, the SYNC pulse must arrive at all ADS5296A devices at the

same time (as shown in Figure 101). The ADS5296A generates an internal synchronization signal that resets the

internal clock dividers used by the decimation filter and in the interleaving mode. Using the SYNC signal in this

manner ensures that all channels output digital codes corresponding to the same set of input samples.

Synchronizing the filters using the SYNC pin is enabled by default. No register bits are required to be written.

The TP_HARD_SYNC register bit must be reset to '0' for this mode to function properly. As shown in Figure 101,

the SYNC rising edge can be positioned anywhere within the window. SYNC width must be at least one clock

cycle.

In addition, SYNC can also be used to synchronize the RAMP test patterns across channels. In order to

synchronize the test patterns, TP_HARD_SYNC must be set to '1'. Setting TP_HARD_SYNC to '1' actually

disables the sync of the filters.

0 ns

t_CLK/ 2

ADC Input

Clock

-1 ns

t_CLK/ 2

t_D= -1 ns < t_D< t_CLK/ 2

SYNC

t_WIDTH³ 1 Clock Cycle

Figure 101. SYNC Timing Diagram

Synchronizing ADC Sampling Instants (Non-Interleaving mode)

Note that in the non-interleaved mode, the SYNC cannot be used to synchronize the ADC sampling instants

across devices. All channels within a single device sample the analog inputs simultaneously. To ensure that

channels across two devices sample the analog inputs simultaneously, the input clock must be routed to both

devices with an identical length. This layout ensures that the input clocks arrive at both devices at the same time.

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DIGITAL OUTPUT INTERFACE

SERIAL LVDS INTERFACE

The ADS5296A offers several flexible output options, making the device easy to interface to an application-

specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). Each option can be easily

programmed using the serial interface. A summary of all available options is listed in Table 67 along with the

default values after power-up and reset. Following Table 67, each option is described in detail.

Table 67. Summary of Output Interface Options

DEFAULT AFTER POWER-

FEATURE

OPTIONS

12x

UP AND RESET

BRIEF DESCRIPTION

12x

10x

Serialization factor

To be used with digital processing functions, such as

averaging and decimation filers.

14x

DDR bit clock frequency

Frame clock frequency

6x, 5x, 7x

6x

1x

For 12x, 10x, and 14x serialization factors respectively.

1x sample rate

12x Serialization with DDR Bit Clock and 1x Frame Clock

The 12-bit ADC data are serialized and output over one LVDS pair per channel along with a 6x bit clock and a 1x

frame clock, as shown in Figure 102. The output data rate is a 12x sample rate, and maximum data rates up to

960 Mbps are supported.

Input Clock

(CLK Frequency = f_S)

Frame Clock

(ADCLK Frequency = 1x f_S)

Bit Clock

(LCLK Frequency = 6x f_S)

Output Data⁽¹⁾

(OUTA Data rate = 12x f_S)

D11

(D0)

D10

(D1)

D9

(D2)

D8

(D3)

D7

(D4)

D6

(D5)

D5

(D6)

D4

(D7)

D3

(D8)

D2

(D9)

D1

(D10)

D0

(D11)

D11

(D0)

D10

(D1)

Sample N

Sample N+1

(1) The upper data bit is the MSB-first mode data bit and the lower data bit is the LSB-first mode data bit.

Figure 102. LVDS Output Interface Timing Diagram (12x Serialization)

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10x Serialization with DDR Bit Clock and 1x Frame Clock

The 10 upper bits of the 12-bit ADC data are serialized and output over one LVDS pair per channel along with a

5x bit clock and a 1x frame clock, as shown in Figure 103. The output data rate is a 10x sample rate, and

maximum data rate ups to 1 Gbps are supported.

Input Clock

(CLK Frequency = f_S)

Frame Clock

(ADCLK Frequency = 1x f_S)

Bit Clock

(LCLK Frequency = 5x f_S)

Output Data⁽¹⁾

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

D9

D8

D7

(OUTA Data rate = 10x f_S)

(D0)

(D1)

(D2)

(D3)

(D4)

(D5)

(D6)

(D7)

(D8)

(D9)

(D0)

(D1)

(D2)

Sample N

Sample N+1

(1) The upper data bit is the MSB-first mode data bit and the lower data bit is the LSB-first mode data bit.

Figure 103. LVDS Output Interface Timing Diagram (10x Serialization)

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PROGRAMMABLE LCLK PHASE

The device enables the edge of the output bit clock (LCLK) to be programmed with the PHASE_DDR register

bits. The default value of PHASE_DDR after reset is '10'. The default phase is shown in Figure 104.

The phase can also be changed by changing the value of the PHASE_DDR[1:0] bits, as shown in Figure 105.

ADCLKP

LCLKP

DATA

OUT

PHASE_DDR[1:0] = 10

Figure 104. Default LCLK Phase

ADCLKP

LCLKP

ADCLKP

LCLKP

DATA

OUT

DATA

OUT

PHASE_DDR[1:0] = 10

PHASE_DDR[1:0] = 00

ADCLKP

LCLKP

ADCLKP

LCLKP

DATA

OUT

DATA

OUT

PHASE_DDR[1:0] = 11

PHASE_DDR[1:0] = 01

Figure 105. Programmable LCLK Phases

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PROGRAMMABLE LVDS OUTPUT CLOCK AND DATA DELAYS

The device enables the edges of the output data and output bit clock to be delayed with the DELAY_DATA and

DELAY_LCLK register bits.

Figure 106 details the timing of the output data and clock edge movements. Table 68 and Table 69 show the

register settings and corresponding delay values for the data and clock edge movements.

t_DF

DATA

t_DR

LCLKN

LCLKP

t_CR

t_CF

Figure 106. LVDS Interface Output Data and Clock Edge Movement

Table 68. LVDS Interface Output Data Delay Settings⁽¹⁾

DATA DELAY,

RISING CLOCK EDGE⁽²⁾

(t_DR, typical, ps)

DATA DELAY,

FALLING CLOCK EDGE⁽²⁾

(t_DF, typical, ps)

DELAY_DATA_R[1:0]

DELAY_DATA_F[1:0]

0

1

0

1

0

1

0

1

0

1

0

1

0

33

72

120

(1) Delay settings are the same for both 10x and 12x serialization modes.

(2) Positive value indicates that the data edge is delayed with respect to the clock, resulting in lower setup time and higher hold time

Table 69. LVDS Interface Output Clock Delay Settings⁽¹⁾

CLOCK RISING EDGE DELAY⁽²⁾

(t_CR, typical, ps)

CLOCK FALLING EDGE DELAY⁽²⁾

(t_CF, typical, ps)

DELAY_LCLK_R[2:0]

DELAY_LCLK_F[2:0]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

-106

-73

-34

14

0

1

0

1

0

1

0

1

0

1

0

1

0

1

-120

-87

-48

0

-14

39

53

96

82

138

124

(1) Delay settings are the same for both 10x and 12x serialization modes.

(2) Negative value indicates that the clock edge is advanced with respect to the data edge, resulting in lower setup time and higher hold

time. Positive value indicates that the clock edge is delayed with respect to the data edge, resulting in higher setup time and lower hold

time

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LVDS OUTPUT DATA AND CLOCK BUFFERS

The equivalent circuit of each LVDS output buffer is shown in Figure 107. After reset, the buffer presents an

output impedance of 100 Ω to match with the external 100-Ω termination.

The V_DIFFvoltage is nominally 400 mV, resulting in an output swing of ±400 mV with a 100-Ω external

termination. The buffer output impedance behaves in the same way as a source-side series termination. By

absorbing reflections from the receiver end, this impedance helps improve signal integrity.

V_DIFF

High

Low

OUTP

OUTM

External

100-W Load

V_OCM

(1)

R_OUT

V_DIFF

High

Low

(1) R_OUT= 100 Ω.

Figure 107. LVDS Buffer Equivalent Circuit

OUTPUT DATA FORMAT

Two output data formats are supported: twos complement and offset binary. These formats can be selected by

the BTC_MODE serial interface register bit. In the event of an input voltage overdrive, the digital outputs go to

the appropriate full-scale level. For a positive overload, the 12-bit output data (D[11:0]) is FFFh in offset binary

output format and 7FFh in twos complement output format. For a negative input overload, the output data is 000h

in offset binary output format and 800h in twos complement output format.

BOARD DESIGN CONSIDERATIONS

Grounding

A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of

the board are cleanly partitioned. Refer to the EVM User Guide, ADS5295, 8-Channel ADC Evaluation Module,

(SLAU442) for details on layout and grounding.

Supply Decoupling

Minimal external decoupling can be used without loss in performance because the device already includes

internal decoupling. Note that decoupling capacitors can help filter external power-supply noise; thus, the

optimum number of capacitors depends on the actual application. The decoupling capacitors should be placed as

close as possible to the converter supply pins.

Exposed Pad

In addition to providing a path for heat dissipation, the pad is also electrically connected to the digital ground

internally. Therefore, the exposed pad must be soldered to the ground plane for best thermal and electrical

performance.

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DEFINITION OF SPECIFICATIONS

Analog Bandwidth: The analog input frequency at which the power of the fundamental is reduced by 3 dB with

respect to the low-frequency value.

Aperture Delay: The delay in time between the rising edge of the input sampling clock and the actual time at

which the sampling occurs. This delay is different across channels. The maximum variation is specified as

aperture delay variation (channel-to-channel).

Aperture Uncertainty (jitter): The sample-to-sample variation in aperture delay.

Clock Pulse Width (duty cycle): The duty cycle of a clock signal is the ratio of the time that the clock signal

remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a

percentage. A perfect differential sine-wave clock results in a 50% duty cycle.

Maximum Conversion Rate: The maximum sampling rate at which specified operation is given. All parametric

testing is performed at this sampling rate, unless otherwise noted.

Minimum Conversion Rate: The minimum sampling rate at which the ADC functions.

Differential Nonlinearity (DNL): An ideal ADC exhibits code transitions at analog input values spaced exactly

1 LSB apart. DNL is the deviation of any single step from this ideal value, measured in units of LSBs.

Integral Nonlinearity (INL): INL is the deviation of the ADC transfer function from a best-fit line determined by a

least-squares curve fit of that transfer function, measured in units of LSBs.

Gain Error: Gain error is the deviation of the actual ADC input full-scale range from its ideal value. The gain

error is given as a percentage of the ideal input full-scale range. Gain error has two components: error as a

result of reference inaccuracy and error as a result of the channel. Both errors are specified independently as

E_GREFand E_GCHAN, respectively. To a first-order approximation, the total gain error is (E_TOTAL~ E_GREF+ E_GCHAN).

For example, if E_TOTAL= ±0.5%, then the full-scale input varies from [(1 – 0.5 / 100) × FS_IDEAL] to [(1 + 0.5 / 100)

× FS_IDEAL].

Offset Error: Offset error is the difference, given in number of LSBs, between the actual average ADC idle

channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts.

Temperature Drift: The temperature drift coefficient (with respect to gain error and offset error) specifies the

change per degree Celsius of the parameter from T_MINto T_MAX. Drift is calculated by dividing the maximum

deviation of the parameter across the T_MINto T_MAXrange by the difference of T_MAX– T_MIN

.

Signal-to-Noise Ratio (SNR): SNR is the ratio of the power of the fundamental (P_S) to the noise floor power

(P_N), excluding the power at dc and the first nine harmonics. SNR is either given in units of dBc (dB to carrier)

when the absolute power of the fundamental is used as the reference, or dBFS (dB to full-scale) when the power

of the fundamental is extrapolated to the converter full-scale range.

P_S

SNR = 10 Log¹⁰

P_N

(9)

Signal-to-Noise and Distortion (SINAD): SINAD is the ratio of the power of the fundamental (P_S) to the power

of all the other spectral components, including noise (P_N) and distortion (P_D), but excluding dc. SINAD is either

given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or

dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range.

P_S

SINAD = 10 Log¹⁰

P_N+ P_D

(10)

Effective Number of Bits (ENOB): ENOB is a measure of the converter performance as compared to the

theoretical limit based on quantization noise.

SINAD - 1.76

ENOB =

6.02

(11)

Total Harmonic Distortion (THD): THD is the ratio of the power of the fundamental (P_S) to the power of the first

nine harmonics (P_D). THD is typically given in units of dBc (dB to carrier).

P_S

THD = 10 Log¹⁰

P_N

(12)

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Spurious-Free Dynamic Range (SFDR): SFDR is the ratio of power of the fundamental to the highest other

spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).

Two-Tone Intermodulation Distortion (IMD3): IMD3 is the ratio of the power of the fundamental (at frequencies

f₁and f₂) to the power of the worst spectral component at either frequency 2 f₁– f₂or 2 f₂– f₁. IMD3 is either

given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or

dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range.

AC Power-Supply Rejection Ratio (AC PSRR): AC PSRR is the measure of rejection of variations in the supply

voltage by the ADC. If ΔV_SUPis the change in supply voltage and ΔV_OUTis the resultant change of the ADC

output code (referred to the input), then:

DV_OUT

PSRR = 20 Log¹⁰

(Expressed in dBc)

DV_SUP

(13)

Voltage Overload Recovery: The number of clock cycles taken to recover to less than 1% error after an

overload on the analog inputs. This recovery is tested by separately applying a sine-wave signal with 6-dB

positive and negative overload. The deviation of the first few samples after the overload (from the expected

values) is noted.

Common-Mode Rejection Ratio (CMRR): CMRR is the measure of rejection of variation in the analog input

common-mode by the ADC. If ΔV_{CM_IN}is the change in the common-mode voltage of the input pins and ΔV_OUTis

the resulting change of the ADC output code (referred to the input), then:

DV_OUT

CMRR = 20 Log¹⁰

(Expressed in dBc)

DV_CM

(14)

CROSSTALK: (only for multichannel ADCs) Crosstalk is a measure of the internal coupling of a signal from an

adjacent channel into the channel of interest. Crosstalk is specified separately for coupling from the immediate

neighboring channel (near-channel) and for coupling from a channel across the package (far-channel). Crosstalk

is usually measured by applying a full-scale signal in the adjacent channel. Crosstalk is the ratio of the power of

the coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the

adjacent channel input. Crosstalk is typically expressed in dBc.

99

GENERIC PACKAGE VIEW

RGC 64

9 x 9, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224597/A

www.ti.com

PACKAGE OUTLINE

VQFN - 1 mm max height

RGC0064A

PLASTIC QUADFLAT PACK- NO LEAD

9.15

8.85

A

B

9.15

8.85

PIN 1 INDEX AREA

(0.2)TYP

(0.1)TYP

DETAIL 'A'

OPTION1

OPTION2

1 MAX

C

SEATING PLANE

0.08 C

0.05

0.00

2X

7.5

EXPOSED

7.25±0.1

THERMAL PAD

32

17

16

33

SEE DETAIL 'A'

60X

0.5

SYMM

65

2X

7.5

0.3

0.18

64X

0.1

C A B

C

48

1

0.05

PIN1 ID

64

49

(OPTIONAL)

SYMM

0.5

0.3

64X

4219009/A 10/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

VQFN - 1 mm max height

RGC0064A

PLASTIC QUADFLAT PACK- NO LEAD

2X(8.8)

2X(7.5)

SEE SOLDER MASK

DETAIL

64X(0.6)

(

7.25)

64

49

1

48

64X(0.24)

60X(0.5)

65

SYMM

2X

2X(7.5)

(8.8)

4X

(1.14)

2X

(1.1)

(0.05)

(TYP)

33

16

45X (Ø0.2)

(TYP) VIA

4X

(1.14)

SYMM

32

17

2X

(1.1)

LAND PATTERN EXAMPLE

SCALE: 10X

SOLDER MASK

OPENING

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

EXPOSED METAL

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4219009/A 10/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

VQFN - 1 mm max height

RGC0064A

PLASTIC QUADFLAT PACK- NO LEAD

2X (8.8)

2X(7.5)

SYMM

36X

(0.94)

64x(0.6)

64

49

1

48

65

64X(0.24)

60X(0.5)

2X(0.57)

2X(8.8)

SYMM

2X(7.5)

4X(1.14)

(R0.05)

TYP

33

16

EXPOSED METAL

17

32

4X(1.14)

2X(0.57)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

60% PRINTED COVERAGE BY AREA

SCALE: 12X

4219009/A 10/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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型号：	ADS5296A
厂家：	TEXAS INSTRUMENTS
描述：	10 位、200MSPS、4 或 8 通道/12 位、80MSPS、8 通道 ADC
文件：	总106页 (文件大小：3152K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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