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ADS52J90

ZHCSDS3C –MAY 2015–REVISED APRIL 2018

具有 LVDS、JESD 输出的 ADS52J90 10 位、12 位、14 位多通道低功耗

高速 ADC

1 特性

3 说明

1

•

16 通道 ADC，可配置为转换

8、16 或 32 路输入

ADS52J90 是一款低功耗、高性能、16 通道的模数转

换器 (ADC)。每个 ADC 在 10 位模式下的转换速率最

高可达 100MSPS。ADC 分辨率越高，最高转换速率

越低。

•

10 位、12 位和 14 位三种分辨率模式

最大 ADC 转换速率：

–

10 位模式下为 100MSPS

12 位模式下为 80MSPS

14 位模式下为 65MSPS

该器件可配置为接受 8、16 或 32 个输入。在 32 位模

式下，每个 ADC 以值为 ADC 转换速率一半的有效采

样率对两个不同输入交替进行采样并转换。在 8 位输

入模式下，两个 ADC 以交错方式对同一输入进行转

换，这种情况下的有效采样率为 ADC 转换速率的 2

倍。ADC 设计为根据转换速率调整其功耗。

•

16 个 ADC 经配置可进行下列转换：

–

8 个输入，采样率为

ADC 转换速率的 2 倍

16 个输入，采样率与

ADC 转换速率相同

器件信息

32 个输入，采样率为

ADC 转换速率的一半

器件型号

ADS52J90

封装

封装尺寸（标称值）

NFBGA (198)

9.00mm × 15.00mm

•

支持 10/12/14/16 倍串行化的低压差分信令 (LVDS)

输出

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

5Gbps JESD 接口：

简化原理图

–

在 16 输入和 32 输入模式下受支持

JESD204B 子类 0、1 和 2

AVDD_1P8

DVDD_1P2

DVDD_1P8

每条 JESD 信道包含 2、4 或 8 条通道

Reference

VCM

(1)

Generator

ADC 1

•

可选的数字 I-Q 解调器

电源：1.2V、1.8V

DOUTP1

DOUTM1

INP1

INM1

DOUTP2

DOUTM2

2 V_PP差分输入，0.8V 共模

差分或单端输入时钟

信噪比 (SNR)：

INP2

INM2

DOUTP16

DOUTM16

–

10 位模式下为 61dBFS

12 位模式下为 70dBFS

14 位模式下为 73.5dBFS

INP31

INM31

FCLKP

FCLKM

ADC 16

DCLKP

DCLKM

INP32

INM32

•

100MSPS 转换速率下的功耗：41mW/通道

封装：NFBGA-198 (9mm x 15mm)

无铅（符合 RoHS 标准）绿色

CML1_OUTP

CML1_OUTM

CML8_OUTP

CML8_OUTM

2 应用

•

超声波成像

Clock

Generator

CLKP

CLKM

Serial

Interface

便携式仪表

SYNC

Generator

SDOUT

声纳和雷达

高速多通道数据采集

(1) 本文档中未详细介绍。如需详细信息，请联系工厂。

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SBAS690

ADS52J90

ZHCSDS3C –MAY 2015–REVISED APRIL 2018

www.ti.com.cn

8.4 Device Functional Modes........................................ 73

8.5 Programming........................................................... 76

Application and Implementation ........................ 77

9.1 Application Information............................................ 77

9.2 Typical Application .................................................. 78

9.3 Do's and Don'ts....................................................... 90

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

说明（续）.............................................................. 4

Pin Configuration and Functions......................... 5

Specifications......................................................... 9

7.1 Absolute Maximum Ratings ...................................... 9

7.2 ESD Ratings.............................................................. 9

7.3 Recommended Operating Conditions..................... 10

7.4 Thermal Information................................................ 10

7.5 Electrical Characteristics......................................... 11

7.6 Digital Characteristics ............................................. 13

7.7 Timing Requirements: Signal Chain ....................... 14

7.8 Timing Requirements: JESD Interface.................... 15

7.9 Timing Requirements: Serial Interface.................... 15

7.10 Typical Characteristics.......................................... 17

7.11 Typical Characteristics: JESD Interface................ 24

7.12 Typical Characteristics: Contour Plots.................. 26

Detailed Description ............................................ 28

8.1 Overview ................................................................. 28

8.2 Functional Block Diagrams ..................................... 28

8.3 Feature Description................................................. 29

9

10 Power Supply Recommendations ..................... 90

10.1 Power Sequencing and Initialization..................... 90

11 Layout................................................................... 92

11.1 Power Supply, Grounding, and Bypassing ........... 92

11.2 Layout Guidelines ................................................. 92

11.3 Layout Example .................................................... 93

12 Register Map........................................................ 94

12.1 ADC Registers ...................................................... 94

12.2 JESD Serial Interface Registers ......................... 134

13 器件和文档支持 ................................................... 149

13.1 文档支持.............................................................. 149

13.2 社区资源.............................................................. 149

13.3 商标..................................................................... 149

13.4 静电放电警告....................................................... 149

13.5 术语表 ................................................................. 149

14 机械、封装和可订购信息..................................... 150

8

4 修订历史记录

Changes from Revision B (August 2015) to Revision C

Page

•

已更改 HPF_ROUND_ENABLE register bit (register 15, bit 5) to HPF_ROUND_EN_CH1-8 and

HPF_ROUND_EN_CH9-16 bits in last paragraph of Digital HPF section ........................................................................... 40

•

已更改 Masking of the Various Reset Operations Resulting from SYNC~ or SYSREF table ............................................. 59

已添加 Interfacing SYNC~ and SYSREF Between the FPGA and ADCs section ............................................................... 65

已更改 Mapping of Analog Inputs to LVDS Outputs (8-Input Mode, 1X Data Rate) table ................................................... 84

已更改 Mapping of Analog Inputs to LVDS Outputs (8-Input Mode, 2X Data Rate) table ................................................... 85

已更改 description for the value 001 in Pattern Mode Bit Description table......................................................................... 99

已更改 bit 5 from HPF_ROUND_EN to HPF_ROUND_EN_CH1-8 in Register 15 ........................................................... 109

已更改 bit 5 from 0 to HPF_ROUND_EN_CH9-16 in Register 2Dh .................................................................................. 123

已更改 description for JESD_RESET1 in Register 70........................................................................................................ 135

已更改 description of JESD_RESET2 and JESD_RESET3 in Register 74 ....................................................................... 137

Changes from Revision A (June 2015) to Revision B

Page

•

已更改文档标题以包含 LVDS 和 JESD 输出 .......................................................................................................................... 1

已添加 JESD 接口可选解调器和特性要点 ........................................................................................................................... 1

更改简化原理图....................................................................................................................................................................... 1

已添加 JESD 接口信息至说明部分中添加了“概述”部分......................................................................................................... 4

Added footnote 1 to Pin Functions table ................................................................................................................................ 6

Changed description of SPI_DIG_EN pin in Pin Functions table........................................................................................... 8

Changed title of Current Consumption with LVDS Interface Enabled section of Electrical Characteristics table................ 12

Changed Current Consumption with JESD Interface Enabled section of Electrical Characteristics table........................... 12

2

ADS52J90

www.ti.com.cn

ZHCSDS3C –MAY 2015–REVISED APRIL 2018

•

Added SPI_DIG_EN to Digital Inputs section title of Digital Characteristics table ............................................................... 13

Changed V_OC-CMLparameter name in JESD Interface Timing Requirements table.............................................................. 15

Added 图 47.......................................................................................................................................................................... 25

Added LVDS, JESD discussion to second paragraph of Overview section......................................................................... 51

添加了社区资源部分 ........................................................................................................................................................... 149

Changes from Original (May 2015) to Revision A

Page

•

已投入量产.............................................................................................................................................................................. 1

已更改 Circuit to Level-Shift the Common-Mode Voltage From 1.2 V at the Driver Output to 0.7 V at the ADC Input

figure..................................................................................................................................................................................... 65

•

已更改 AC-Coupling Scheme for SYSREF figure ................................................................................................................ 66

3

ADS52J90

ZHCSDS3C –MAY 2015–REVISED APRIL 2018

www.ti.com.cn

5 说明（续）

ADC 输出会进行串行化，并与帧时钟和高速位时钟一起通过低压差分信令 (LVDS) 接口输出。

该器件还具有一个可选的 JESD204B 接口，同时可在 16 输入和 32 输入模式下工作。该接口的运行速率最高可达

5Gbps。

ADS52J90 采用间距为 0.8mm 的 9mm × 15mm NFBGA-198 封装，额定工作温度范围为 –40°C 至 +85°C。

4

ADS52J90

www.ti.com.cn

ZHCSDS3C –MAY 2015–REVISED APRIL 2018

6 Pin Configuration and Functions

ZZE Package

NFBGA-198 (15 mm × 9 mm)

Top View

1

2

3

4

5

6

7

8

9

10

11

A

B

C

D

E

F

INM2

INP2

INP1

AVDD_1P8

SDIN

RESET

DVDD_1P2

DVSS

CML1_OUTP

CML1_OUTM

CML2_OUTP

INM3

INM5

INP3

INP5

INM1

INP4

AVSS

INP8

SEN

SDOUT

NC

SPI_DIG_EN

PDN_FAST

TX_TRIG

AVDD_1P8

AVSS

SCLK

PDN_GBL

DVSS

DVDD_1P2

DVDD_1P8

DVSS

DOUTP1

DOUTP2

DOUTP3

DOUTP4

DOUTP5

DOUTP6

DOUTP7

FCLKP

DOUTM1

DOUTM2

DOUTM3

DOUTM4

DOUTM5

DOUTM6

DOUTM7

DVDD_1P8

DVSS

CML2_OUTM

CML3_OUTP

CML3_OUTM

CML4_OUTP

CML4_OUTM

DOUTM8

INM6

INP6

INM4

INM7

INP7

INM8

NC

DVSS

INM9

INP9

INM10

INM12

INM14

INM16

INM18

INM20

INM22

INM24

INM26

INM28

INP28

INM32

INP32

INP10

INP12

INP14

INP16

INP18

INP20

INP22

INP24

INP26

AVSS

AVDD_1P8

VCM

DVDD_1P2

DVSS

G

H

J

INM11

INM13

INM15

INM17

INM19

INM21

INM23

INM25

INM27

INM29

INM30

INM31

INP11

INP13

INP15

INP17

INP19

INP21

INP23

INP25

INP27

INP29

INP30

INP31

AVDD_1P8

AVSS

AVDD_1P8

NC

DOUTP8

AVSS

DVSS

DCLKP

K

L

AVSS

DVSS

FCLKM

DCLKM

AVSS

DVSS

DOUTP10

DOUTP11

DOUTP12

DOUTP13

DOUTP14

DOUTP15

DOUTP16

CML5_OUTP

DOUTM10

DOUTM11

DOUTM12

DOUTM13

DOUTM14

DOUTM15

DOUTM16

CML5_OUTM

DOUTP9

M

N

P

R

T

AVDD_1P8

DVSS

DVDD_1P2

DVDD_1P8

DVDD_1P2

DVSS

DOUTM9

CML8_OUTM

CML8_OUTP

CML7_OUTM

CML7_OUTP

CML6_OUTM

CML6_OUTP

SYNCM_

SERDES

NC

SYNCP_

SERDES

AVSS

CLKM

CLKP

SYSREFM_

SERDES

DVDD_1P2

AVSS

SYSREFP_

SERDES

U

V

AVSS

DVDD_1P2

5

ADS52J90

ZHCSDS3C –MAY 2015–REVISED APRIL 2018

www.ti.com.cn

Pin Functions⁽¹⁾

I/O

DESCRIPTION

NAME

AVDD_1P8

NO.

A4, E6, F6, G5, G6, M5,

M6, N6, P6, V4

P

1.8-V analog supply voltage

Analog ground

B4, C4, D4, H5, H6, J5,

J6, K5, K6, L5, L6, R4, R5,

T4, T5, U4, U6, V6

AVSS

G

CLKM

U5

V5

Differential clock input pins. A single-ended clock is also supported.

See the Clock Input section for further details.

I

CLKP

CML1_OUTM

CML1_OUTP

CML2_OUTM

CML2_OUTP

CML3_OUTM

CML3_OUTP

CML4_OUTM

CML4_OUTP

CML5_OUTM

CML5_OUTP

CML6_OUTM

CML6_OUTP

CML7_OUTM

CML7_OUTP

CML8_OUTM

CML8_OUTP

DCLKM

A10

A9

O

JESD output lane 1

JESD output lane 2

JESD output lane 3

JESD output lane 4

JESD output lane 5

JESD output lane 6

JESD output lane 7

JESD output lane 8

LVDS bit clock output

LVDS data lane 1

LVDS data lane 2

LVDS data lane 3

LVDS data lane 4

LVDS data lane 5

LVDS data lane 6

LVDS data lane 7

LVDS data lane 8

LVDS data lane 9

LVDS data lane 10

LVDS data lane 11

LVDS data lane 12

B11

A11

D11

C11

F11

E11

V10

V9

U11

V11

R11

T11

N11

P11

K11

J11

B10

B9

DCLKP

DOUTM1

DOUTP1

DOUTM2

C10

C9

DOUTP2

DOUTM3

D10

D9

DOUTP3

DOUTM4

E10

E9

DOUTP4

DOUTM5

F10

F9

DOUTP5

DOUTM6

G10

G9

DOUTP6

DOUTM7

H10

H9

DOUTP7

DOUTM8

G11

H11

M11

L11

L10

L9

DOUTP8

DOUTM9

DOUTP9

DOUTM10

DOUTP10

DOUTM11

DOUTP11

DOUTM12

DOUTP12

M10

M9

N10

N9

(1) If the JESD interface is not used, then do not connect the CMLx, SYNCx, and SYSREFx pins. If the LVDS interface is not used, then do

not connect DOUTx, DCLKx, and FCLKx.

6

ADS52J90

www.ti.com.cn

ZHCSDS3C –MAY 2015–REVISED APRIL 2018

Pin Functions⁽¹⁾(continued)

I/O

DESCRIPTION

NAME

DOUTM13

DOUTP13

DOUTM14

DOUTP14

DOUTM15

DOUTP15

DOUTM16

DOUTP16

NO.

P10

P9

O

LVDS data lane 13

LVDS data lane 14

LVDS data lane 15

LVDS data lane 16

R10

R9

O

T10

T9

O

U10

U9

O

A7, B8, C8, D8, F7, G7,

M7, N7, R8, T6, T8, U8,

V7

DVDD_1P2

DVDD_1P8

DVSS

P

G

1.2-V digital supply voltage

1.8-V digital supply voltage

Digital ground

E8, F8, G8, J10, M8, N8,

P8

A8, D7, E7, H7, H8, J7,

J8, K7, K8, K10, L7, L8,

R6, V8

FCLKM

FCLKP

INM1

INP1

K9

J9

O

I

LVDS frame clock output

B3

A3

A1

A2

B1

B2

D3

C3

C1

C2

D1

D2

E1

E2

E3

E4

F1

F2

F3

F4

G1

G2

G3

G4

H1

H2

H3

H4

J1

Differential analog input 1 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

INM2

INP2

Differential analog input 2 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

INM3

INP3

Differential analog input 3 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

INM4

INP4

Differential analog input 4 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

INM5

INP5

Differential analog input 5 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

INM6

INP6

Differential analog input 6 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

INM7

INP7

Differential analog input 7 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

INM8

INP8

Differential analog input 8 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

INM9

INP9

Differential analog input 9 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

INM10

INP10

INM11

INP11

INM12

INP12

INM13

INP13

INM14

INP14

INM15

INP15

INM16

INP16

INM17

INP17

Differential analog input 10 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

Differential analog input 11 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

Differential analog input 12 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

Differential analog input 13 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

Differential analog input 14 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

Differential analog input 15 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

J2

J3

Differential analog input 16 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

J4

K1

K2

Differential analog input 17 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

7

ADS52J90

ZHCSDS3C –MAY 2015–REVISED APRIL 2018

www.ti.com.cn

Pin Functions⁽¹⁾(continued)

I/O

DESCRIPTION

NAME

NO.

INM18

INP18

INM19

INP19

INM20

INP20

INM21

INP21

INM22

INP22

INM23

INP23

INM24

INP24

INM25

INP25

INM26

INP26

INM27

INP27

INM28

INP28

INM29

INP29

INM30

INP30

INM31

INP31

INM32

INP32

NC

K3

Differential analog input 18 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

I

K4

L1

Differential analog input 19 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

L2

L3

Differential analog input 20 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

L4

M1

Differential analog input 21 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

M2

M3

Differential analog input 22 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

M4

N1

Differential analog input 23 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

N2

N3

Differential analog input 24 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

N4

P1

Differential analog input 25 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

P2

P3

Differential analog input 26 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

P4

R1

Differential analog input 27 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

R2

R3

Differential analog input 28 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

T3

T1

Differential analog input 29 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

T2

U1

Differential analog input 30 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

U2

V1

Differential analog input 31 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

V2

U3

V3

Differential analog input 32 pins; see 表 1 for mapping to external inputs in 8-, 16-, and

32-input modes

D5, E5, N5, P5

—

I

Do not connect; leave floating.

Fast power-down control pin (active high) with an internal pulldown resistor of 20 kΩ.

For active high, a 1.8-V logic level is recommended.

PDN_FAST

PDN_GBL

SPI_DIG_EN

RESET

C6

C7

B6

A6

B7

A5

C5

B5

Global power-down control input (active high) with an internal pulldown resistor of 20

kΩ. For active high, a 1.8-V logic level is recommended.

I

Reserved for digital functionality. This pin can be left floating or be connected to the

1.8-V supply. This pin has an internal pullup resistor of 20 kΩ.

Hardware reset pin (active high) with an internal pulldown resistor of 20 kΩ. For active

high, a 1.8-V logic level is recommended.

I

Serial interface clock input with an internal pulldown resistor of 20 kΩ. For active high,

a 1.8-V logic level is recommended.

SCLK

I

Serial interface data input with an internal pulldown resistor of 20 kΩ. For active high, a

1.8-V logic level is recommended.

SDIN

I

Serial interface data readout. High impedance when readout is disabled. 1.8-V logic

level is recommended.

SDOUT

SEN

O

I

Serial interface enable with an internal pullup resistor of 20 kΩ. 1.8-V logic level is

recommended.

1.8-V logic; a pulse on TX_TRIG must be applied after power-up to ensure that all

internal clock dividers are synchronized⁽²⁾.Has an internal pull-down resistor of 20 kΩ

to ground.

TX_TRIG

D6

I

SYNCM_SERDES

SYNCP_SERDES

P7

R7

Frame synchronization input as per JESD204B standard

(2) See the Device Synchronization Using TX_TRIG section for more details on synchronization using TX_TRIG.

8

ADS52J90

www.ti.com.cn

ZHCSDS3C –MAY 2015–REVISED APRIL 2018

Pin Functions⁽¹⁾(continued)

I/O

DESCRIPTION

NAME

NO.

T7

SYSREFM_SERDES

SYSREFP_SERDES

Frame clock and local multiframe clock (LMFC) synchronization input as per

JESD204B, subclass 1 standard

I

U7

Common-mode output pin for biasing analog input signals. Connect a 10-µF capacitor

to ground.

VCM

F5

O

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

UNIT

AVDD_1P8

2.2

Voltage

DVDD_1P2

DVDD_1P8

1.35

V

2.2

Analog input pins (INM_i, INP_i)

CLKP, CLKM

Minimum [2.2, (AVDD_1P8 + 0.3)]

V

PDN_GBL, PDN_FAST, RESET, SCLK, SDIN,

SEN, TX_TRIG, SPI_DIG_EN,

SYNCM_SERDES, SYNCP_SERDES,

SYSREFM_SERDES, SYSREFP_SERDES

Digital control pins

–0.3

Minimum [2.2, (DVDD_1P8 + 0.3)]

V

Maximum operating junction temperature, T_JMax

Storage temperature, T_stg

105

150

°C

–55

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

±1000

±250

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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7.3 Recommended Operating Conditions

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

TEMPERATURE

T_A

Ambient

–40

85

°C

SUPPLIES

V_{(AVDD_1P8)}

V_{(DVDD_1P8)}

V_{(DVDD_1P2)}

ANALOG INPUT

V_(INx)

1.8-V analog supply voltage

1.8-V digital supply voltage

1.2-V digital supply voltage

1.7

1.8

1.2

1.9

V

1.15

1.25

Voltage range at analog input pins

VCM – 0.5

0.7

VCM + 0.5

0.9

V

Input common-mode range at

analog input pins

V_IN(CM)

0.8

2

V_IN(FS)

Input differential full-scale voltage

Analog input frequency range⁽¹⁾

V_PP

F_IN

0

70

MHz

ANALOG OUTPUT

I_(VCM)

External loading on VCM pin

±50-mV change in VCM

100

µA

CLOCK INPUT

16-input mode, 10-bit ADC resolution

16-input mode, 12-bit ADC resolution

16-input mode, 14-bit ADC resolution

32-input mode, 10-bit ADC resolution

32-input mode, 12-bit ADC resolution

32-input mode, 14-bit ADC resolution

8-input mode, 10-bit ADC resolution

Sine-wave, ac-coupled

5

100

80

5

65

f_S

System clock frequency

5

100

80

MSPS

5

65

10

0.7

200

V_CLKP– V_CLKM

Differential clock amplitude

LVPECL, ac-coupled

1.6

0.7

V_PP

LVDS, ac-coupled

0.35

40%

V_CLKP

Single-ended clock amplitude

Input clock duty cycle

LVCMOS on CLKP with CLKM grounded

1.8

50%

60%

DIGITAL INPUTS

0.75 ×

DVDD_1P8

V_IH

Digital input minimum, high level

Digital input maximum, low level

1.8

0

V

0.25 ×

DVDD_1P8

V_IL

DIGITAL OUTPUT (LVDS)

R_LOAD

Differential load resistance

Between DOUTP and DOUTM

100

50

Ω

DIGITAL OUTPUT (CML)

R_CML

Load resistance from each CML output to a common mode

(1) Performance degradation may be seen at high input frequencies.

7.4 Thermal Information

ADS52J90

ZZE (NFBGA)

198 PINS

33.7

THERMAL METRIC⁽¹⁾

UNITS

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

4.9

14.1

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.1

ψ_JB

14.1

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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7.5 Electrical Characteristics

Typical values are across ADC resolution and input modes, unless otherwise specified. Typical values are at 25°C,

AVDD_1P8 = DVDD_1P8 = 1.8 V, DVDD_1P2 = 1.2 V. External 100-Ω differential load between LVDS outputs, 4-pF load

capacitor from each LVDS output to ground, and 1X data rate mode.

All ADCs are powered up and the input signal is a –1-dBFS tone at 5 MHz applied on one channel at a time.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ADC

32-channel input, 16-channel input

8-channel input

10

14

N_adc

ADC resolution

Bits

10

16

Number of ADCs

ADCs

CLOCK DOMAINS

10-bit ADC resolution

12-bit ADC resolution

14-bit ADC resolution

16-input mode

100

80

Conversion rate of each ADC

(conversion clock frequency)

f_C

MSPS

65

f_C

System clock frequency in

terms of f_C

f_S

32-input mode

8-input mode

2 × f_C

f_C

16-input mode

Effective sampling rate of each

input channel in terms of f_C

f_SAMP

32-input mode

0.5 × f_C

2 × f_C

8-input mode

PERFORMANCE

Same device, across channels

Same channel, across devices

±0.1

G_MATCH

Gain matching

dB

Gain drift with temperature over

full temperature range

G_DRIFT

V_OFF

0.1

dB

Offset error

–7 to 7

–0.5 to 0.5

–0.9 to 0.9

–1 to 2

–0.5 to 0.5

–1 to 1

–3 to 3

61.3

mV

10-bit resolution

12-bit resolution

14-bit resolution

10-bit resolution

Differential nonlinearity of the

ADC

DNL

INL

LSB

Integral nonlinearity of the ADC 12-bit resolution

14-bit resolution

10-bit, 16-channel input mode, f_SAMP= 100 MSPS

10-bit, 32-channel input mode, f_SAMP= 50 MSPS

10-bit mode, 8-channel input, f_SAMP= 200 MSPS

10-bit mode, 8-channel input, f_SAMP= 130 MSPS

12-bit mode, 16- channel input, f_SAMP= 80 MSPS

12-bit mode, 32-channel input, f_SAMP= 40 MSPS

12-bit mode, 32-channel input, f_SAMP= 20 MSPS

14-bit mode, 16- channel input, f_SAMP= 65 MSPS

14-bit mode, 16- channel input, f_SAMP= 50 MSPS

14-bit mode, 32-channel input, f_SAMP= 32.5 MSPS

61.3

56

60

58.2

61

Signal-to-noise ratio:

69.5

excludes first 9 harmonics as

well as spurs at (f_S/ 2 ± f_IN),

(f_S/ 4 ± f_IN), f_S/ 2, and f_S/ 4

SNR

dBFS

65

67.5

65.9

67.9

69.5

70.2

72.5

73.5

73

Second-order harmonic

distortion

HD2

All input modes and resolutions

–80

dBc

HD3

THD

Third-order harmonic distortion All input modes and resolutions

–80

–76

–73

–62

dBc

Total harmonic distortion

All input modes and resolutions

16-input mode; 10-,12-,14-bit resolutions

8-input mode, 10-bit resolution

Magnitude of spur at

dBc

(f_S/ 2 ± f_IN

)

Magnitude of spur at

8-input mode, 10-bit resolution

–65

–80

dBc

(f_S/ 4 ± f_IN

)

Input spur on neighboring channel with one channel

excited at 5 MHz, –1 dBFS

Crosstalk

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Electrical Characteristics (continued)

Typical values are across ADC resolution and input modes, unless otherwise specified. Typical values are at 25°C,

AVDD_1P8 = DVDD_1P8 = 1.8 V, DVDD_1P2 = 1.2 V. External 100-Ω differential load between LVDS outputs, 4-pF load

capacitor from each LVDS output to ground, and 1X data rate mode.

All ADCs are powered up and the input signal is a –1-dBFS tone at 5 MHz applied on one channel at a time.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PERFORMANCE (continued)

AC power-supply rejection ratio:

PSRR_100kHz

tone at output relative to tone

on supply

100-mV_PP, 100-kHz tone on supply

–70

dBc

AC power-supply modulation

ratio: intermodulation tone at

output resulting from tones at

supply and input measured

relative to input tone

100-mV_PP, 100-kHz tone on supply and –1-dBFS,

5-MHz tone on input

PSMR_100kHz

–80

–40

dBc

AC common-mode rejection

ratio: tone at output relative to

the common-mode tone applied frequency of 5 MHz

at the analog input pins

50-mV_PPcommon-mode tone at input pins with a

CMRR

TRANSIENT BEHAVIOR

N_OVERLOADInput overload recovery

t_{PDN_GBL}

Conversion

clock

5-MHz overload input, 6-dBFS overload

PDN_GBL from high to low

1

Recovery time from global

power-down mode

ms

Recovery time from fast power-

down mode (standby mode)

Conversion

clocks

t_{PDN_FAST}

PDN_FAST from high to low

15

CURRENT CONSUMPTION WITH LVDS INTERFACE ENABLED

AVDD_1P8 current

3

Current consumption in global

power-down mode

(PDN_GBL = 1)

DVDD_1P8 current

DVDD_1P2 current

AVDD_1P8 current

DVDD_1P8 current

DVDD_1P2 current

AVDD_1P8 current

DVDD_1P8 current

DVDD_1P2 current

16-channel input mode

32-channel input mode

8-channel input mode

mA

25

80

Current consumption in standby

mode (PDN_FAST = 1) at

f_C= 100 MSPS

35

70

190

100

110

41

Current consumption in active

mode at f_C= 100 MSPS⁽¹⁾

mA

Power dissipation in active

mode per input channel at

f_C= 100 MSPS

P_CH

20.5

82

mW/channel

CURRENT CONSUMPTION WITH JESD INTERFACE ENABLED

AVDD_1P8 current⁽¹⁾

170

260

40

Supply currents: JESD204B

interface enabled, LVDS

interface disabled at 12-bit, 80-

MSPS, 4 ADCs per lane mode

I_JESD

DVDD_1P2 current⁽¹⁾

DVDD_1P8 current⁽¹⁾

16-channel input mode

mA

Power dissipation in active

mode per input channel: f_C= 80

MSPS, 12-bit mode, LVDS

interface disabled, JESD

interface enabled (4 ADCs per

lane mode)

43.1

P_{JESD_CH}

mW/channel

32-channel input mode

21.6

(1) See the Power Supply Recommendations section for guidelines on designing the supplies.

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7.6 Digital Characteristics

The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic

level 0 or 1. Typical values are at 25°C, AVDD_1P8 = DVDD_1P8 = 1.8 V, DVDD_1P2 = 1.2 V, and external differential load

resistance between the LVDS output pair (R_LOAD= 100 Ω), unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUTS (PDN_FAST, PDN_GBL, RESET, SCLK, SDIN, SEN, TX_TRIG, SPI_DIG_EN)

V_IH

V_IL

I_IH

I_IL

High-level input voltage

Low-level input voltage

High-level input current

Low-level input current

Input capacitance

1.35

V

0.45

150

4

µA

pF

C_i

DIGITAL OUTPUTS (SDOUT)

V_OH

V_OL

z_o

High-level output voltage

Low-level output voltage

Output impedance

1.6

1.8

0

V

Ω

0.2

50

LVDS DIGITAL OUTPUTS (DOUTPI, DOUTMI)⁽¹⁾

100-Ω external load connected differentially

across DOUTP_Iand DOUTM_I

|V_OD

|

Output differential voltage

320

0.9

400

480

mV

V

Output offset voltage

(common-mode voltage of

DOUTP_Iand DOUTM_I)

100-Ω external load connected differentially

across DOUTP_Iand DOUTM_I

V_OS

1.03

1.15

(1) All digital specifications are characterized across operating temperature range but are not tested at production.

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7.7 Timing Requirements: Signal Chain

Typical values are at 25°C. AVDD_1P8 = DVDD_1P8 = 1.8 V, DVDD_1P2 = 1.2 V, and external differential load resistance

between the LVDS output pair (R_LOAD= 100 Ω), unless otherwise noted. A capacitive load of 4 pF is on the LVDS outputs.

MIN

TYP

MAX

UNIT

GENERAL

t_AP

Aperture delay

1.6

±0.5

0.5

ns

ps

Aperture delay variation from device to device

(at same temperature and supply)

δt_AP

t_APJ

Aperture jitter with LVPECL clock as input clock

ADC TIMING

Default after reset

ADC latency

8.5

4.5

Conversion

clocks

N_LAT

Low-latency mode

LVDS TIMING

16-input and 8-input modes

Frame clock frequency

f_C

f_C/ 2

50%

f_F

MHz

32-input mode

D_FRAME

N_SER

Frame clock duty cycle

Number of bits serialization of each ADC word

10

16

Bits

Mbps

MHz

Output rate of serialized data for 1X output data rate

mode, 16-, 8-. and 32-input modes

N_SER× f_C

1000

f_D

Output rate of serialized data for 2X output data rate

mode, 16-input and 8-input modes

2 × N_SER× f_C

1000

500

f_B

Bit clock frequency

Bit clock duty cycle

Data bit duration

f_D/ 2

50%

D_BIT

t_D

1

1000 / f_D

6 × t_D+ 5

ns

t_PROP

Clock propagation delay⁽¹⁾

Clock propagation delay variation from device to device

(at same temperature and supply)

δt_PROP

±2

ns

DOUT, DCLK, FCLK rise and fall time, transition time

between –100 mV and +100 mV

t_ORF

0.2

t_OSU

t_OH

t_DV

Minimum serial data, serial clock setup time⁽²⁾

Minimum serial data, serial clock hold time⁽²⁾

Minimum data valid window⁽³⁾⁽²⁾

t_D/ 2 – 0.4

t_D– 0.65

ns

TX_TRIG TIMING

t_{TX_TRIG_DEL}

Delay between TX_TRIG and TX_TRIGD⁽⁴⁾

(5)

0.5

0.4 × t_S

ns

Setup time related to latching TX_TRIG relative to the

rising edge of the system clock

t_{SU_TX_TRIGD}

0.6

0.4

Hold time related to latching TX_TRIG relative to the

rising edge of the system clock

t_{H_TX_TRIGD}

ns

(1) See 图 64 to 图 68 for the definition of t_PROPin various operating modes.

(2) See 图 1.

(3) The specification for the minimum data valid window is larger than the sum of the minimum setup and hold times because there can be

a skew between the ideal transitions of the serial output data with respect to the transition of the bit clock. This skew can vary across

channels and across devices. A mechanism to correct this skew can therefore improve the setup and hold timing margins. For example,

the LVDS_DCLK_DELAY_PROG control can be used to shift the relative timing of the bit clock with respect to the data.

(4) TX_TRIGD is the internally delayed version of TX_TRIG that gets latched on the rising edge of the system clock.

(5) t_Sis the system clock period in ns.

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7.8 Timing Requirements: JESD Interface

Typical values are at T_A= 25°C, AVDD_1P8 = 1.8 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, differential ADC clock, R_LOAD

=

50 Ω from each CML pin to DVDD_1P2, 12-bit ADC resolution, sample rate, and f_C= 80 MSPS, unless otherwise noted.

Minimum and maximum values are across the full temperature range of T_MIN= –40°C to T_MAX= 85°C. The JESD204B

interface operates in default mode after setting the JESD_EN bit to 1 (12-bit ADC resolution, 12-bit serialization, 4 ADCs per

lane, and scrambling disabled).

MIN

TYP

MAX

UNIT

TIMING CHARACTERISTICS

Serial output data rate in terms of F (number of octets per frame)

and f_C(ADC clock frequency in MHz)

f_JESD

0.01 × F × f_C

Gbps

UI

Tj

Unit interval

200 1000 / f_JESD

0.27

2000

ps

Total jitter: f_JESD= 5 Gbps, PRE_EMP = 7, INC_JESD_VDD = 1

p-p UI

Rise and fall time: 20% to 80%, each pin loaded by C_LOAD= 1.2 pF

to DVDD_1P2

t_R, t_F

85

ps

SAMPLING TIMING

t_{SU_S}Setup time for SYSREF with respect to the device clock rising edge

t_{H_S}

t_{SU_T}

t_{H_T}

JESD LATENCY

Latency from SYNC~ assertion (falling) edge to start of CGS phase

3

2

3

2

ns

Hold time for SYSREF with respect to the device clock rising edge

Setup time for SYNC~ with respect to the device clock rising edge

Hold time for SYNC~ with respect to the device clock rising edge

Device

clock cycles

N_{A_SYNC~}

17

11

(K28.5) in subclass 0, 1, and 2

Latency from the first LMFC boundary after SYNC~ deassertion

(rising) edge to start of ILA phase (K28.0) in subclass 1

Device

clock cycles

N_{D_SYNC~}

Latency from the device clock falling edge sampling the analog input

of ADC1 to the appearance of the corresponding octets on the JESD

outputs

Device

clock cycles

N_{LAT_JESD}

14.5

JESD DIGITAL OUTPUTS

High-level output voltage of the CML output (CMLx_OUTP,

CMLx_OUTM)

V_OH-CML

V_OL-CML

DVDD_1P2

V

Low-level output voltage of the CML output (CMLx_OUTP,

CMLx_OUTM)

DVDD_1P2 – 0.4

|V_OD-CML

V_OC-CML

z_OS

|

Differential output voltage of CMLx_OUT

0.4

DVDD_1P2 – 0.2

50 ± 25%

V

Common-mode output voltage of CMLx_OUTP, CMLx_OUTM

Single-ended output impedance

Ω

C_CML

Output capacitance inside device from either CML output to ground

1

pF

Transmitter short-circuit current: transmitter terminals shorted to any

voltage between –0.25 V and 1.45 V

±100

mA

7.9 Timing Requirements: Serial Interface⁽¹⁾⁽²⁾

MIN

50

20

5

TYP

MAX

UNIT

ns

t_SCLK

SCLK period

t_{SCLK_H}

t_{SCLK_L}

t_DSU

SCLK high time

ns

SCLK low time

ns

Data setup time

ns

t_DHO

Data hold time

5

ns

t_{SEN_SU}

t_{SEN_HO}

t_{OUT_DV}

SEN falling edge to SCLK rising edge

Time between last SCLK rising edge to SEN rising edge

SDOUT delay

8

ns

8

ns

12

20

28

ns

(1) Characterized in lab over operating temperature range, not tested at production testing.

(2) See 图 92 and 图 93.

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SERIAL_IN1 (D[11:0])

Frame Clock (FCLK)

D0

D2

D4

D6

D8

DOUT1

D1

D3

D5

D7

D9

D10 D11

Bit Clock (DCLK)

t_D

t_OH

t_OSU

DOUT1

t_B

Bit Clock (DCLK)

t_DV

图 1. LVDS Output Signals Timing Diagram in

16-Input Mode with 12-Bit Serialization, LSB-First, 1X Data Rate Mode

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7.10 Typical Characteristics

At 25°C, AVDD_IP8 = DVDD_1P8 = 1.8 V, and DVDD_1P2 = 1.2 V, unless otherwise noted. All LVDS outputs are active with

100-Ω differential terminations and a 4-pF load capacitor from each LVDS output pin to ground. A –1-dBFS input signal at

5 MHz is applied to the input channel under test. SNR is computed by ignoring the power contained in the first nine harmonic

bins, the f_S/ 2 and f_S/ 4 frequency bins as well as the bins corresponding to the intermodulation frequencies between the

input and the clock. A LVPECL clock is used as the clock source.

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-100

-110

-120

-130

-140

0

5

10

15

20

25

0

5

10

15

20

25

30

35

40

45

50

Frequency (MHz)

f_IN= 5 MHz, f_C= 100 MSPS, SNR = 61.5 dBFS,

f_IN= 5 MHz, f_C= 100 MSPS, SNR = 61.6 dBFS,

SFDR = 81.9 dBc, HD2 = –86.5 dBc, HD3 = –93.9 dBc

SFDR = 78.7 dBc, HD2 = –97.6 dBc, HD3 = –92.2 dBc

图 2. FFT of 10-Bit, 32-Input Mode

图 3. FFT of 10-Bit, 16-Input Mode

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-100

-110

-120

-130

0

10

20

30

40

50

60

70

80

90 100

0

5

10

15

20

Frequency (MHz)

f_IN= 5 MHz, f_C= 100 MSPS, SNR = 61.3 dBFS,

SFDR = 70.8 dBc, HD2 = –94.2 dBc, HD3 = –80.1 dBc

f_IN= 5 MHz, f_C= 80 MSPS, SNR = 69.9 dBFS, SFDR = 82.6 dBc,

HD2 = –82.6 dBc, HD3 = –88.9 dBc

图 5. FFT of 12-Bit, 32-Input Mode

图 4. FFT of 10-Bit, 8-Input Mode

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

-100

-110

-120

-130

-140

-150

0

5

10

15

20

25

30

35

40

0

5

10

15

Frequency (MHz)

f_IN= 5 MHz, f_C= 80 MSPS, SNR = 70.2 dBFS, SFDR = 75.4 dBc,

HD2 = –109.8 dBc, HD3 = –86.1 dBc

f_IN= 5 MHz, f_C= 65 MSPS, SNR = 73.7 dBFS, SFDR = 91.8 dBc,

HD2 = –96.6 dBc, HD3 = –97.2 dBc

图 6. FFT of 12-Bit, 16-Input Mode

图 7. FFT of 14-Bit, 32-Input Mode

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Typical Characteristics (接下页)

At 25°C, AVDD_IP8 = DVDD_1P8 = 1.8 V, and DVDD_1P2 = 1.2 V, unless otherwise noted. All LVDS outputs are active with

100-Ω differential terminations and a 4-pF load capacitor from each LVDS output pin to ground. A –1-dBFS input signal at

5 MHz is applied to the input channel under test. SNR is computed by ignoring the power contained in the first nine harmonic

bins, the f_S/ 2 and f_S/ 4 frequency bins as well as the bins corresponding to the intermodulation frequencies between the

input and the clock. A LVPECL clock is used as the clock source.

61.62

61.58

61.54

61.5

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

61.46

61.42

5

10 15 20 25 30 35 40 45 50 55 60 65 70

Input Frequency, f_IN(MHz)

0

5

10

15

20

25

30 32.5

Frequency (MHz)

f_SAMP= 50 MSPS

f_IN= 5 MHz, f_C= 65 MSPS, SNR = 73.4 dBFS, SFDR = 80.2 dBc,

HD2 = –88.7 dBc, HD3 = –93.9 dBc

图 9. Signal-to-Noise Ratio vs f_INin

图 8. FFT of 14-Bit, 16-Input Mode

10-Bit, 32-Input Mode

61.58

61.4

61.35

61.3

61.54

61.5

61.25

61.2

61.46

61.42

61.15

5

10 15 20 25 30 35 40 45 50 55 60 65 70

Input Frequency, f_IN(MHz)

5

10 15 20 25 30 35 40 45 50 55 60 65 70

Input Frequency, f_IN(MHz)

f_SAMP= 100 MSPS

f_SAMP= 200 MSPS

图 10. Signal-to-Noise Ratio vs f_INin

图 11. Signal-to-Noise Ratio vs f_INin

10-Bit, 16-Input Mode

10-Bit, 8-Input Mode

70.28

70.08

69.88

69.68

69.48

69.28

69.08

70.2

70

69.8

69.6

69.4

69.2

69

5

10 15 20 25 30 35 40 45 50 55 60 65 70

Input Frequency, f_IN(MHz)

5

10 15 20 25 30 35 40 45 50 55 60 65 70

Input Frequency, f_IN(MHz)

f_SAMP= 40 MSPS

f_SAMP= 80 MSPS

图 12. Signal-to-Noise Ratio vs f_INin

图 13. Signal-to-Noise Ratio vs f_INin

12-Bit, 32-Input Mode

12-Bit, 16-Input Mode

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Typical Characteristics (接下页)

At 25°C, AVDD_IP8 = DVDD_1P8 = 1.8 V, and DVDD_1P2 = 1.2 V, unless otherwise noted. All LVDS outputs are active with

100-Ω differential terminations and a 4-pF load capacitor from each LVDS output pin to ground. A –1-dBFS input signal at

5 MHz is applied to the input channel under test. SNR is computed by ignoring the power contained in the first nine harmonic

bins, the f_S/ 2 and f_S/ 4 frequency bins as well as the bins corresponding to the intermodulation frequencies between the

input and the clock. A LVPECL clock is used as the clock source.

74

73.5

73

73.7

73.3

72.9

72.5

72.1

71.7

71.3

72.5

72

71.5

71

5

10 15 20 25 30 35 40 45 50 55 60 65 70

Input Frequency, f_IN(MHz)

5

10 15 20 25 30 35 40 45 50 55 60 65 70

Input Frequency, f_IN(MHz)

f_SAMP= 32.5 MSPS

f_SAMP= 65 MSPS

图 14. Signal-to-Noise Ratio vs f_INin

图 15. Signal-to-Noise Ratio vs f_INin

14-Bit, 32-Input Mode

14-Bit, 16-Input Mode

-77

-80

-83

-86

-89

-92

-95

-82

-83

-84

-85

-86

-87

-88

5

10 15 20 25 30 35 40 45 50 55 60 65 70

Input Frequency, f_IN(MHz)

5

10 15 20 25 30 35 40 45 50 55 60 65 70

Input Frequency, f_IN(MHz)

100-MSPS conversion clock

图 16. Third-Order Harmonic Distortion vs f_IN

图 17. Second-Order Harmonic Distortion vs f_IN

-74

-46

-75

-76

-77

-78

-79

-80

-50

-54

-58

-62

-66

-70

5

10 15 20 25 30 35 40 45 50 55 60 65 70

Input Frequency, f_IN(MHz)

5

10 15 20 25 30 35 40 45 50 55 60 65 70

Input Frequency, f_IN(MHz)

100-MSPS conversion clock

f_SAMP= 200 MSPS

图 18. Total Harmonic Distortion vs f_IN

图 19. Input-Clock Intermodulation Spur at (f_S/ 2 ± f_IN) vs f_IN

in 8-Input Mode

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Typical Characteristics (接下页)

At 25°C, AVDD_IP8 = DVDD_1P8 = 1.8 V, and DVDD_1P2 = 1.2 V, unless otherwise noted. All LVDS outputs are active with

100-Ω differential terminations and a 4-pF load capacitor from each LVDS output pin to ground. A –1-dBFS input signal at

5 MHz is applied to the input channel under test. SNR is computed by ignoring the power contained in the first nine harmonic

bins, the f_S/ 2 and f_S/ 4 frequency bins as well as the bins corresponding to the intermodulation frequencies between the

input and the clock. A LVPECL clock is used as the clock source.

-65

-69

-73

-77

-81

-85

-68

-70

-72

-74

-76

-78

-80

5

10 15 20 25 30 35 40 45 50 55 60 65 70

Input Frequency, f_IN(MHz)

5

10 15 20 25 30 35 40 45 50 55 60 65 70

Input Frequency, f_IN(MHz)

f_SAMP= 100 MSPS

f_SAMP= 200 MSPS

图 20. Input-Clock Intermodulation Spur at (f_S/ 2 ± f_IN) vs f_IN

图 21. Input-Clock Intermodulation Spur at (f_S/ 4 ± f_IN) vs f_IN

in 16-Input Mode

in 8-Input Mode

75.7

110

100

90

104

100

96

SFDR (dBc)

SFDR (dBFS)

75.3

74.9

74.5

74.1

73.7

73.3

80

92

70

88

60

84

50

80

-40

-35

-30

-25

-20

-15

-10

-5

-1

-40

-35

-30

-25

-20

-15

-10

-5

-1

Input Amplitude, A_IN(dBFS)

16-input mode, 14-bit resolution, f_SAMP= 65 MSPS

32-input mode, 14-bit resolution, f_SAMP= 32.5 MSPS

图 22. Signal-to-Noise Ratio vs A_IN

图 23. Spurious-Free Dynamic Range vs A_IN

74

73.9

73.8

73.7

73.6

73.5

73.4

73.3

73.2

73.1

73

78

Input signal frequency = 5 MHz

Input signal frequency = 50 MHz

75

72

69

66

63

60

0.6

0.65

0.7

0.75

0.8

0.85

0.9

0.95

1

0.1

0.4

0.7

1

1.3

1.6

1.9

2.2

Input Common-Mode Voltage, INPCM (V)

Differential Input Clock Amplitude (V_PP

)

16-input mode, 14-bit resolution, f_SAMP= 65 MSPS

图 24. Signal-to-Noise Ratio vs

图 25. Signal-to-Noise Ratio vs Amplitude of

Input Common-Mode Voltage (INPCM)

Differential Sine-Wave Input Clock

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Typical Characteristics (接下页)

At 25°C, AVDD_IP8 = DVDD_1P8 = 1.8 V, and DVDD_1P2 = 1.2 V, unless otherwise noted. All LVDS outputs are active with

100-Ω differential terminations and a 4-pF load capacitor from each LVDS output pin to ground. A –1-dBFS input signal at

5 MHz is applied to the input channel under test. SNR is computed by ignoring the power contained in the first nine harmonic

bins, the f_S/ 2 and f_S/ 4 frequency bins as well as the bins corresponding to the intermodulation frequencies between the

input and the clock. A LVPECL clock is used as the clock source.

-57

-62

-67

-72

-77

-82

-87

74.2

74

73.8

73.6

73.4

73.2

73

5

10 15 20 25 30 35 40 45 50 55 60 65 70

Input Frequency, f_IN(MHz)

30

35

40

45

50

55

60

65

70

Differential Input Clock Duty Cycle (%)

32-input mode, 14-bit resolution, f_SAMP= 32.5 MSPS, –1-dBFS

tone applied on one channel and spur on neighboring channel

measured as crosstalk

16-input mode, 14-bit resolution, f_SAMP= 65 MSPS

space

图 27. Crosstalk vs f_IN

图 26. Signal-to-Noise Ratio vs Differential Input

Clock Duty Cycle

2.8

2.5

2

1.8

0.8

1.5

1

-0.2

-1.2

-2.2

-3.2

0.5

0

-0.5

-1

-1.5

0

3000

6000

9000

Code

12000

15000

0

3000

6000

9000

Code

12000

15000

32-input mode, 14-bit resolution, f_SAMP= 32.5 MSPS

图 28. Integral Nonlinearity

图 29. Differential Nonlinearity

-58

-36

-60

-62

-64

-66

-68

-70

-40

-44

-48

-52

-56

-60

0.1

0.2 0.3

0.5 0.7

1

2

3

4

5

6 7 8 10

0.1

0.2 0.3

0.5 0.7

1

2

3

4 5 6 7 8 10

Frequency of Signal on Supply (MHz)

32-input mode, 14-bit resolution, f_SAMP= 32.5 MSPS, 100-mV_PP

tone on supply

32-input mode; 14-bit resolution; f_SAMP= 32.5 MSPS; 100-mV_PP

tone on supply; 5-MHz, –1-dBFS tone on input; PSMR is

intermodulation tone referred to input tone amplitude

图 31. Power-Supply Modulation Ratio vs

图 30. Power-Supply Rejection Ratio vs

Frequency of Signal on Supply

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Typical Characteristics (接下页)

At 25°C, AVDD_IP8 = DVDD_1P8 = 1.8 V, and DVDD_1P2 = 1.2 V, unless otherwise noted. All LVDS outputs are active with

100-Ω differential terminations and a 4-pF load capacitor from each LVDS output pin to ground. A –1-dBFS input signal at

5 MHz is applied to the input channel under test. SNR is computed by ignoring the power contained in the first nine harmonic

bins, the f_S/ 2 and f_S/ 4 frequency bins as well as the bins corresponding to the intermodulation frequencies between the

input and the clock. A LVPECL clock is used as the clock source.

180

170

160

150

140

130

120

110

100

-30

-35

-40

-45

-50

-55

-60

10

20

30

40

50

60

70

80

90

100

Conversion Clock Frequency, f_C(MHz)

0.1

0.2 0.3 0.50.7

1

2

3

4 5 67 10

20 30 50 70

Frequency of Common-Mode Input Signal (MHz)

32-input mode, 10-bit resolution

32-input mode, 14-bit resolution, f_SAMP= 32.5 MSPS, 50-mV_PP

common-mode tone applied at the inputs, output tone referred to

the input tone

图 33. AVDD_1P8 Current vs

Conversion Clock Frequency

图 32. Common-Mode Rejection Ratio vs

Frequency of Common-Mode Input Signal

101

99

97

95

93

91

89

87

85

83

120

110

100

90

80

70

60

50

40

30

10

20

30

40

50

60

70

80

90

100

10

20

30

40

50

60

70

80

90

100

Conversion Clock Frequency, f_C(MHz)

32-input mode, 10-bit resolution

图 34. DVDD_1P8 Current vs

图 35. DVDD_1P2 Current vs

Conversion Clock Frequency

655

10

0

620

585

550

515

480

445

410

375

-10

-20

-30

-40

-50

-60

HPF_CORNER_ADC* = 2

HPF_CORNER_ADC* = 3

HPF_CORNER_ADC* = 4

HPF_CORNER_ADC* = 5

HPF_CORNER_ADC* = 6

HPF_CORNER_ADC* = 7

HPF_CORNER_ADC* = 8

HPF_CORNER_ADC* = 9

HPF_CORNER_ADC* = 10

10

20

30

40

50

60

70

80

90

100

0.01

0.05

0.2 0.5

1

2 3 45 710 20 50 100 200

Conversion Clock Frequency, f_C(MHz)

Frequency (MHz)

32-input mode, 10-bit resolution

图 36. Total Power vs Conversion Clock Frequency

图 37. Digital High-Pass Filter Response

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Typical Characteristics (接下页)

At 25°C, AVDD_IP8 = DVDD_1P8 = 1.8 V, and DVDD_1P2 = 1.2 V, unless otherwise noted. All LVDS outputs are active with

100-Ω differential terminations and a 4-pF load capacitor from each LVDS output pin to ground. A –1-dBFS input signal at

5 MHz is applied to the input channel under test. SNR is computed by ignoring the power contained in the first nine harmonic

bins, the f_S/ 2 and f_S/ 4 frequency bins as well as the bins corresponding to the intermodulation frequencies between the

input and the clock. A LVPECL clock is used as the clock source.

77

76

75

74

73

72

71

70

69

400

350

300

250

200

150

100

50

Min

Typ

Max

Chopper Disabled

Chopper Enabled

0

1E-5

0.0001

0.001

Frequency (MHz)

0.01

0.10.2 0.5 1 2

1

5

9

13

17

21

25

29

32

Channel Number

16-input mode, 12-bit resolution

Statistical values taken over 100 devices in 14-bit, 32-input mode

at f_SAMP= 32.5 MSPS

图 38. Signal-to-Noise Ratio Histogram

图 39. Low-Frequency Noise With and Without

Chopper Enabled

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7.11 Typical Characteristics: JESD Interface

Typical values are at T_A= 25°C, AVDD_1P8 = 1.8 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, differential ADC clock, R_LOAD

50 Ω from each CML pin to DVDD_1P2, 12-bit ADC resolution, sample rate, and f_CLKIN= 80 MSPS, unless otherwise noted.

Minimum and maximum values are across the full temperature range of T_MIN= –40°C to T_MAX= 85°C. The JESD204B

interface operates in default mode after setting the JESD_EN bit to 1 (12-bit ADC resolution, 12-bit serialization, 4 ADCs per

lane, and scrambling disabled).

=

0.55

0.5

0.55

0.5

0.45

0.4

0.45

0.4

0.35

0.3

0.35

0.3

5 Gbps

6 Gbps

6.4 Gbps

PRE_EMP = 0

PRE_EMP = 7

PRE_EMP = 15

0.25

0.2

0.25

1

3

5

7

9

11

13

1

3

5

7

9

11

13

Trace Length (inch)

D001

D002

PRE_EMP = 15 , across JESD speeds

图 40. Total Jitter vs Trace Length

JESD speed = 5 Gbps, across PRE_EMP settings

图 41. Total Jitter vs Trace Length

0.65

0.6

0.65

PRE_EMP = 0

PRE_EMP = 7

PRE_EMP = 15

0.6

0.55

0.5

0.55

0.5

0.45

0.4

0.45

0.4

PRE_EMP = 0

PRE_EMP = 7

PRE_EMP = 15

0.35

0.3

0.35

1

3

5

7

9

11

13

1

3

5

7

9

11

13

Trace Length (inch)

D003

D004

JESD speed = 6 Gbps, across PRE_EMP settings

JESD speed = 6.4 Gbps, across PRE_EMP settings

图 42. Total Jitter vs Trace Length

图 43. Total Jitter vs Trace Length

175

320

ADC Resolution 12 bit

ADC Resolution 14 bit

2 ADCs per lane

4 ADCs per lane

8 ADCs per lane

170

165

160

155

150

145

140

135

130

125

120

115

110

300

280

260

240

220

200

180

160

140

120

100

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

ADC Sample Rate (MHz)

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

ADC Sample Rate (MHz)

Across ADC resolutions

ADC resolution = 12 bits, across lane modes

图 44. AVDD_1P8 Current vs ADC Sample Rate

图 45. DVDD_1P2 Current vs ADC Sample Rate

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Typical Characteristics: JESD Interface (接下页)

Typical values are at T_A= 25°C, AVDD_1P8 = 1.8 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, differential ADC clock, R_LOAD

=

50 Ω from each CML pin to DVDD_1P2, 12-bit ADC resolution, sample rate, and f_CLKIN= 80 MSPS, unless otherwise noted.

Minimum and maximum values are across the full temperature range of T_MIN= –40°C to T_MAX= 85°C. The JESD204B

interface operates in default mode after setting the JESD_EN bit to 1 (12-bit ADC resolution, 12-bit serialization, 4 ADCs per

lane, and scrambling disabled).

300

280

260

240

220

200

180

160

140

120

100

45

40

35

30

25

20

15

10

2 ADCs per lane

4 ADCs per lane

8 ADCs per lane

10 15 20 25 30 35 40 45 50 55 60 65

ADC Sample Rate (MHz)

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

ADC Sample Rate (MHz)

ADC resolution = 14 bits, across lane modes

ADC resolution = 12, 14 bits; across lane modes

图 46. DVDD_1P2 Current vs ADC Sample Rate

图 47. DVDD_1P8 Current vs ADC Sample Rate

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7.12 Typical Characteristics: Contour Plots

At 25°C, AVDD_IP8 = DVDD_1P8 = 1.8 V, and DVDD_1P2 = 1.2 V, unless otherwise noted. All LVDS outputs are active with

100-Ω differential terminations and a 4-pF load capacitor from each LVDS output pin to ground. A –1-dBFS input signal at 5

MHz is applied to the input channel under test. SNR is computed by ignoring the power contained in the first nine harmonic

bins, the f_S/ 2 and f_S/ 4 frequency bins as well as the bins corresponding to the intermodulation frequencies between the

input and the clock. An LVPECL clock is used as the clock source.

图 49. Signal-to-Noise Ratio in 10-Bit, 16-Input Mode

图 48. Signal-to-Noise Ratio in 10-Bit, 32-Input Mode

图 50. Signal-to-Noise Ratio in 10-Bit, 8-Input Mode

图 51. Signal-to-Noise Ratio in 12-Bit, 32-Input Mode

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Typical Characteristics: Contour Plots (接下页)

At 25°C, AVDD_IP8 = DVDD_1P8 = 1.8 V, and DVDD_1P2 = 1.2 V, unless otherwise noted. All LVDS outputs are active with

100-Ω differential terminations and a 4-pF load capacitor from each LVDS output pin to ground. A –1-dBFS input signal at 5

MHz is applied to the input channel under test. SNR is computed by ignoring the power contained in the first nine harmonic

bins, the f_S/ 2 and f_S/ 4 frequency bins as well as the bins corresponding to the intermodulation frequencies between the

input and the clock. An LVPECL clock is used as the clock source.

图 53. Signal-to-Noise Ratio in 14-Bit, 32-Input Mode

图 52. Signal-to-Noise Ratio in 12-Bit, 16-Input Mode

图 54. Signal-to-Noise Ratio in 14-Bit, 16-Input Mode

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8 Detailed Description

8.1 Overview

A block diagram of the device is shown in 图 55. 图 56 illustrates the signal flow for the device while operating

with the LVDS output interface. The device consists of 16 ADCs configurable to convert 8-, 16-, or 32-inputs. All

ADCs run off the external clocks (provided on the CLKP, CLKM pins). The references needed for the ADCs are

internally generated. The reference voltage that can be used to set the common mode voltage of the analog

input comes out on the VCM pin. The output data from the 16 ADCs are serialized and output on the LVDS

interface. The device also has an optional JESD204B interface. The device is controlled using an SPI interface.

8.2 Functional Block Diagrams

Reference Voltage

VCM

and

Current Generator

INP1

INM1

LVDS

DOUTP1

DOUTM1

ADC 1

INP2

INM2

DOUTP2

DOUTM2

INP3

INM3

ADC 2

LVDS Outputs

INP4

INM4

Analog Inputs

DOUTP16

DOUTM16

FCLKP

FCLKM

INP31

INM31

DCLKP

DCLKM

ADC 16

INP32

INM32

CML

f_SAMP

f_C

CML1_OUTP

CML1_OUTM

CML Outputs

CML8_OUTP

CML8_OUTM

Clock

Generator

CLKP

CLKM

System Clock

SYNC

Generator

Serial Interface

SDOUT

f_S

图 55. Block Diagram

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Functional Block Diagrams (接下页)

16-, 32-, and

8-Input Mode

ADC Resolution:

10, 12, 14, 16

Serialization Factor:

10, 12, 14, 16

Test Pattern

Setting

MSB_FIRST 1X, 2X Mode

1X, 2X Mode

Analog

Inputs

LVDS

Outputs

IN1

IN2

AIN1

ADCIN1

ADCIN2

ADCOUT1

10/12/14

SERIAL_IN1

SERIAL_OUT1

SERIAL_OUT2

DOUT1

DOUT2

DIGOUT1

16

DIGRES1

ADC1

ADC2

AIN2

10, 12, 14, 16

SERIAL_IN2

10, 12, 14,

16

ADCOUT2

DIGOUT2

DIGRES2

Digital

Processing

Input

Multiplexer

and Sampler

Teset Pattern

Insertion

Output

Multiplexer

Serializer

Truncation

(Bypassable)

DOUT16

FCLK

ADCIN16

ADCOUT16

DIGOUT16

DIGRES16

SERIAL_IN16

SERIAL_OUT16

ADC16

IN32

DCLK

AIN32

A/D Conversion and Digital Processing

Data Formatting

Frame Clock, f_F

Sampling Clock, f_SAMP

(Split as Odd and Even

Conversion Clock, f_C

Sampling Phase for Each ADC)

Internal Clock Generation

and Clock Tree

System Clock, f_S

图 56. Signal Flow Diagram

8.3 Feature Description

The device has 16 synchronously operating ADCs (ADC1 to ADC16) and can be configured to accept and

convert 8, 16, or 32 active differential external analog inputs (AIN1 to AIN32). The converted digital outputs can

be made to come out on either 16 pairs of low-voltage differential signaling (LVDS) outputs or compressed into

eight pairs. The device operates from a single clock input. This input is referred to as the system clock and its

frequency is denoted by f_S. The recommended mode of driving the clock is with a differential low-voltage

positive-referenced emitter coupled logic (LVPECL) clock. The system clock can be also driven by a differential

sine-wave or LVDS, or can be driven with a single-ended low voltage complementary metal oxide semiconductor

(LVCMOS) clock. The various aspects of the signal chain are discussed in the following sections.

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Feature Description (接下页)

8.3.1 Connection of the External Inputs to the Input Pins

The effective conversion rate per input changes depending on the input mode. The methodology of connecting

the external inputs (AINx) to the input pins (INx) is shown in 表 1 for the 16-, 32- and 8-channel input modes. In

表 1, AIN1 refers to the differential input signal (AINP1, AINM1) and IN1 refers to the input pair (INP1, INM1).

The voltage that gets sampled and converted by the device is (AINP1-AINM1).

表 1. Scheme of Driving the Input Pins (16-, 32-, 8-Channel Input Modes)

CONNECTION TO THE EXTERNAL ANALOG INPUT SIGNAL

INPUT PAIR

16-CHANNEL INPUT MODE⁽¹⁾⁽²⁾

32-CHANNEL INPUT MODE

AIN1

8-CHANNEL INPUT MODE⁽¹⁾

IN1

IN2

AIN1

—

AIN1

—

AIN2

IN3

AIN2

—

AIN3

AIN1

—

IN4

AIN4

IN5

AIN3

—

AIN5

AIN2

—

IN6

AIN6

IN7

AIN4

—

AIN7

AIN2

—

IN8

AIN8

IN9

AIN5

—

AIN9

AIN3

—

IN10

IN11

IN12

IN13

IN14

IN15

IN16

IN17

IN18

IN19

IN20

IN21

IN22

IN23

IN24

IN25

IN26

IN27

IN28

IN29

IN30

IN31

IN32

AIN10

AIN11

AIN12

AIN13

AIN14

AIN15

AIN16

AIN17

AIN18

AIN19

AIN20

AIN21

AIN22

AIN23

AIN24

AIN25

AIN26

AIN27

AIN28

AIN29

AIN30

AIN31

AIN32

AIN6

—

AIN3

—

AIN7

—

AIN4

—

AIN8

—

AIN4

—

AIN9

—

AIN5

—

AIN10

—

AIN5

—

AIN11

—

AIN6

—

AIN12

—

AIN6

—

AIN13

—

AIN7

—

AIN14

—

AIN7

—

AIN15

—

AIN8

—

AIN16

—

AIN8

—

(1) — = do not connect.

(2) To switch ADCx to convert the even numbered inputs, use register control IN_16CH_ADCx.

8.3.2 Input Multiplexer and Sampler

The input multiplexer determines the mapping of the input pins (IN1 to IN32) to the inputs that are sampled and

converted by the ADCs (ADC1 to ADC16). Each ADC has two sets of sampling circuits (termed odd and even)

and alternately converts the inputs presented to them.

30

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The sampling windows for the odd and even sampling circuits of each ADC are derived from the system clock. A

pair of ADCs are used in 图 57, 图 58, and 图 59 to illustrate how the odd and even sampling phases are derived

for each ADC in each input mode. AIN1 (t₁) refers to the AIN1 input sampled at the t₁instant. ADC1o refers to

the odd sample converted by ADC1 and ADC1e refers to the even sample converted by ADC1. The input

sampling and conversion schemes for the 32-, 16-, and 8-input modes are illustrated in 图 57, 图 58, and 图 59,

respectively.

32-Channel Input Mode

t₁

t₂

t₃

t₄

Sampling Instants

Analog input, AIN1

Analog input, AIN2

Analog input, AIN3

Analog input, AIN4

System Clock, f_S

(External Clock)

Sampling Clock for Input 1, f_SAMP

(Internal Signal)

Input to Odd

Sampling Circuit

AIN1

ADCIN1

Input to Even

Sampling Circuit

AIN2

ADC1o

AIN1(t₁)

ADC1e

AIN2(t₂)

ADC1o

AIN1(t₃)

ADC1e

AIN2(t₄)

ADC1 Conversion

Input to Odd

Sampling Circuit

AIN3

ADCIN2

Input to Even

Sampling Circuit

AIN4

ADC2o

AIN3(t₁)

ADC2e

AIN4(t₂)

ADC2o

AIN3(t₃)

ADC2e

AIN4(t₄)

ADC2 Conversion

ADC Conversion Clock, f_C

(Internal Signal)

图 57. Input Sampling and Conversion Scheme (32-Input Mode)

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16-Channel Input Mode

Sampling Instants

Analog input, AIN1

t₂

t₃

t₁

t₄

Analog input, AIN2

System Clock, f_S

(External Clock)

Sampling Clock for Input 1, f_SAMP

(Internal Signal)

Input to Odd

Sampling Circuit

AIN1

ADCIN1

Input to Even

AIN1

Sampling Circuit

ADC1o

ADC1e

ADC1o

ADC1e

AIN1(t₃)

AIN1(t₄)

AIN1(t₁)

AIN1(t₂)

ADC1 Conversion

Input to Odd

Sampling Circuit

AIN2

ADCIN2

Input to Even

Sampling Circuit

AIN2

ADC2o

ADC2e

ADC2o

ADC2e

AIN2(t₃)

AIN2(t₄)

AIN2(t₁)

AIN2(t₂)

ADC2 Conversion

ADC Conversion Clock, f_C

(Internal Signal)

图 58. Input Sampling and Conversion Scheme (16-Input Mode)

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8-Channel Input Mode

Sampling Instants

t₅

t₇

t₈

t₆

t₁

t₃

t₄

t₂

Analog input, AIN1

System Clock, f_S

(External Clock)

Sampling Clock for Input 1, f_SAMP

(Internal Signal)

Input to Odd

Sampling Circuit

AIN1

ADCIN1

Input to Even

Sampling Circuit

AIN1

ADC1o

ADC1e

ADC1o

ADC1e

AIN1(t₅)

AIN1(t₇)

AIN1(t₁)

AIN1(t₃)

ADC1 Conversion

Input to Odd

Sampling Circuit

AIN1

ADCIN2

Input to Even

Sampling Circuit

AIN1

ADC2o

ADC2e

ADC2o

ADC2e

ADC2 Conversion

AIN1(t₂)

AIN1(t₄)

AIN1(t₆)

AIN1(t₈)

ADC Conversion Clock, f_C

(Internal Signal)

图 59. Input Sampling and Conversion Scheme (8-Input Mode)

Mapping the inputs of the odd and even sampling circuits of subsequent-numbered ADCs to subsequent-

numbered sets of input pairs repeats in a similar manner.

The sampling rate (f_SAMP) can be defined as the rate at which the device converts each analog input presented to

it. The relationship between the sampling rate and the system clock frequency is listed in 表 2 for the three input

modes.

表 2. Sampling Rate and Input Clock Frequency

ANALOG INPUT MODE (Number of Input Channels)

SAMPLING RATE (f_SAMP)

16

32

8

f_S

0.5 × f_S

f_S

In 16-input mode, each ADC converts one input at a sampling rate equal to the system clock. In 32-input mode,

one ADC alternately converts two sets of inputs, each at a sampling rate that is half the system clock. In the 8-

input mode, two ADCs convert the same input in interleaved manner.

In 16-input mode, a ping-pong operation exists between two sampling circuits of one ADC that are sampling the

same input. The mismatch between the two sampling circuit bandwidths can result in an interleaving spur at

(f_S/ 2 ± f_IN), where f_Sis the frequency of the system clock and f_INis the frequency of the input signal.

In 8-input mode, additional interleaving across two adjacent ADCs is present in addition to the ping-pong

operation between the two sampling circuits of the same ADC. This increased mismatch can result in significant

interleaving spurs at (f_S/ 2 ± f_IN) and (f_S/ 4 ± f_IN). The offset mismatch between the four sets of sampling circuits

can result in a spur at f_S/ 4.

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For the 32-input mode, the sampling instants of the even-numbered input signals are offset from the sampling

instants of the odd-numbered input signals by one system clock period. The magnitude of the interleaving spurs

increases when the input frequency is increased because the sampling bandwidth mismatch across the different

sampling circuits results in larger phase error mismatches when the input frequency is increased.

8.3.3 Analog-to-Digital Converter (ADC)

The device has 16 synchronous ADCs that provide a digital representation of the input in twos complement

format. Each ADC converts at a rate of f_Cusing a conversion clock that is internally generated from the system

clock. Every cycle of a conversion clock corresponds to a new ADC conversion.

The mapping of the ADC conversions to the analog input is described in 表 3. See 图 57, 图 58, and 图 59 for the

naming conventions.

表 3. Mapping of the ADC Conversions to the Analog Inputs and Sampling Instants

INPUT CONVERTED BY THE ADC

ADC SAMPLE

16-INPUT MODE

AIN1 (t₁)

32-INPUT MODE

AIN1 (t₁)

8-INPUT MODE

AIN1 (t₁)

ADC1o

ADC2o

ADC1e

ADC2e

AIN2 (t₁)

AIN3 (t₁)

AIN1 (t₂)

AIN2 (t₂)

AIN1 (t₃)

AIN2 (t₂)

AIN4 (t₂)

AIN1 (t₄)

The ADC resolution (the number of bits in the signals marked as ADCOUT1 to ADCOUT16) can be programmed

as 10, 12, or 14 bits using the ADC_RES bits. The maximum conversion clock of the ADC depends on the ADC

resolution setting, as shown in 表 4.

表 4. Maximum Conversion Rate of the ADC for Different ADC Resolutions

ADC RESOLUTION (Bits)

MAXIMUM CONVERSION CLOCK (f_C(max), MSPS)

10

12

14

100

80

65

The relationship between the system clock and sampling clock rates to the ADC conversion clock is shown in 表

5. Note that the maximum conversion rate of the ADC is fixed for the three resolution modes. In 表 5, sampling

rate refers to the effective rate of sampling each active analog input.

表 5. System Clock and Sampling Clock Relationship to the ADC Conversion Clock

ANALOG INPUT MODE

(1)

(Number of Input

Channels)

SYSTEM CLOCK RATE (f_S)

SAMPLING RATE (f_SAMP

)

ADC RESOLUTIONS SUPPORTED

16

32

8

f_C

10, 12, 14

10

0.5 × f_C

2 × f_C

(1) Sampling rate is also the effective conversion rate of each input channel.

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8.3.4 Device Synchronization Using TX_TRIG

The device has multiple PLLs and clock dividers that are used to generate the programmable ADC resolutions

and LVDS synchronization factors as well as to synchronize LVDS test patterns.

The TX_TRIG input is used to synchronize clock dividers inside the device. The synchronization achieved using

TX_TRIG also enables multiple parallel devices to operate synchronously.

For the 32-input mode, the same ADC alternates between converting two inputs. The TX_TRIG signal provides

the mechanism to determine the sampling instants of the odd and even input signals with respect to the system

clock, as shown in 图 60.

t_{TX_TRIG_DEL}

TX_TRIG

t_{SU_TX_TRIGD}

t_{H_TX_TRIGD}

TX_TRIGD

(Internal signal latched by

System clock rising edge)

t₂

t₁

System Clock

ADC1o

ADC1e

AIN2(t₂)

ADC1 Conversion

AIN1(t₁)

ADC2o

AIN3(t₁)

ADC2e

AIN4(t₂)

ADC2 Conversion

Conversion Clock

图 60. Odd- and Even-Channel Sampling Instant Definition Mechanism in

32-Input Mode with the TX_TRIG Signal

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For the 8-input mode, the conversion clock is obtained by dividing the system clock by 2. The phase of the

division is again determined by the TX_TRIG signal, as shown in 图 61.

t_{TX_TRIG_DEL}

TX_TRIG

t_{SU_TX_TRIGD}

t_{H_TX_TRIGD}

TX_TRIGD

(Internal signal latched by

System clock rising edge)

t₁

t₂

t₃

t₄

System Clock

ADC1o

AIN1(t₁)

ADC1e

AIN1(t₃)

ADC1 Conversion

ADC2o

AIN1(t₂)

ADC2e

AIN1(t₄)

ADC2 Conversion

Conversion Clock

图 61. Conversion Clock Deriving Mechanism from Division of the Sampling Clock in 8-Input Mode

Applying a pulse on TX_TRIG is a mandatory part of the power-up and initialization sequence; see the Power

Sequencing and Initialization section.

In case a TX_TRIG is not applied, the device can possibly behave in an unexpected manner. The identified

cases are shown in 表 6.

表 6. Device Behavior Cases: TX_TRIG is Not Applied

INPUT MODE WHERE ISSUE OCCURS

(8-, 16-, 32-Channel Input Modes)

SCENARIO

ISSUE

Frame clock across devices is not

synchronized

8- and 32-channel input modes

Multiple devices operating in parallel

LVDS patterns across devices are not

synchronized

8-, 16-, and 32-channel input modes

8- and 32-channel input modes

Serialization factor different from ADC

resolution

Framing of data words within a frame clock is

not defined

The TX_TRIG pulse resets the phase of the test pattern generator, the odd and even sampling phase selection,

and the phase of the frame clock. As a result of this phase reset operation, the ADC data can be corrupted for

four to six clocks immediately after applying TX_TRIG. The phase reset from TX_TRIG can be disabled using

MASK_TX_TRIG.

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8.3.5 Digital Processing

The ADC outputs go to a digital processing block that can be used to enhance ADC performance. Some of the

operations done in the digital processing block can enhance the effective signal to noise ratio at its output. For

this reason, the number of bits at the DIGOUT1 to DIGOUT16 signals are considered to be 16. However, some

of the LSBs of this 16-bit word may be zero. For example, when the digital processing block is bypassed, the

number of non-zero bits in DIGOUT is the same as the ADC resolution—the extra LSBs of the 16-bit word are

zero.

The digital processing block results in additional latency that can be avoided by using the low latency mode

(programmed using the LOW_LATENCY_EN bit) that bypasses the entire digital processing block without

introducing extra latency. The various features available in the digital processing block are shown in 图 62 and

are explained in the subsequent sections.

ADC 2

Output

Digital Test Patterns

ADCOUT

10b, 12b, 14b

MUX

DIGOUT

16b

ADC1

Output

Digital Average

Default = No

Digital Gain

Default = 0 dB

Digital HPF

Default = No

Digital Offset

Default = No

图 62. ADC Digital Block Diagram

8.3.5.1 Digital Offset

Digital functionality provides for channel offset correction. Setting the DIG_OFFSET_EN bit to 1 enables the

subtraction of the offset value from the ADC output. There are two offset correction modes, as shown in 图 63.

DIG_OFFSET_EN

0

Data Output,

Bits 13-0

MUX

(0s appended as LSBs when in 10-/12-bit resolutions)

Analog

Input(s)

ADCx

+

1

-

AUTO_OFFSET_REMOVAL_

ACC_CYCLES

OFFSET_REMOVAL_SELF

(Register 4, Bit 15)

(Register 4, Bits 12:9)

OFFSET_REMOVAL_START_SEL

(Register 4, Bit 14)

Bits

29-0

OFFSET_REMOVAL_

Truncation and

Rounding Data

Bits

Bits 13-0

1

START_MANUAL

(Register 4, Bit 13)

0

Accumulator

Start

MUX

1

TX_TRIG Pin

Bits 9-0

0

OFFSET_ADC_xo,

OFFSET_ADC_xe

Extending Sign

Bit to 14 Bits

Bits 13-0

图 63. Digital Offset Correction Block Diagram

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8.3.5.1.1 Manual Offset Correction

If the channel offset is known or estimated, it can be written into a 10-bit register and can be subtracted from the

ADC output. There are 32 sets of manual offset controls. To enable per-channel offset correction in the 32-input

mode, the offset values for the odd and even data streams of each of the 16 ADCs can be independently

controlled. The registers OFFSET_ADCxo and OFFSET_ADCxe correspond to the offsets subtracted from the

odd and even data streams of ADCx. Write the offset values in twos complement format.

8.3.5.1.2 Auto Offset Correction Mode (Offset Correction using a Built-In Offset Calculation Function)

The auto offset calculation module can be used to calculate the channel offset that is then subtracted from the

ADC output. To enable the auto offset correction mode, set the OFFSET_REMOVAL_SELF bit and

DIG_OFFSET_EN bit to 1.

In auto offset correction mode the dc component of the ADC output (assumed to be the channel offset) is

estimated using a digital accumulator. The ADC output sample set used by the accumulator is determined by a

start time or first sample and number of samples to be used. A high pulse on the TX_TRIG pin or setting the

OFFSET_REMOVAL_START_MANUAL register can be used to determine the first sample to the accumulator.

To set the number of samples, the AUTO_OFFSET_REMOVAL_ACC_CYCLES register must be programmed

according to 表 7.

If a pulse on the TX_TRIG pin is used to set the first sample, additional flexibility in setting the first sample is

provided. A programmable delay between the TX_TRIG pulse and the first sample can be set by writing to the

OFFSET_CORR_DELAY_FROM_TX_TRIG register.

The determined offset value can be read out for each channel. Set the channel number in the

AUTO_OFFSET_REMOVAL_VAL_RD_CH_SEL register and read the offset value for the corresponding channel

in the AUTO_OFFSET_REMOVAL_VAL_RD register. Note that the offset estimation is done separately for the

odd and even data streams of each of the 16 ADCs and results in 32 sets of offset estimates that can be read

out.

表 7. Auto Offset Removal Accumulator Cycles

NUMBER OF SAMPLES USED FOR OFFSET VALUE

AUTO_OFFSET_REMOVAL_ACC_CYCLES (Bits 3-0)

EVALUATION

0

2047

127

1

2

255

3

511

4

1023

2045

4095

8191

16383

32767

65535

5

6

7

8

9

10 to 15

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8.3.5.1.3 Digital Averaging

The data from two adjacent ADCs (ADC1 and ADC2, ADC3 and ADC4, and so forth) can be averaged by

enabling the AVG_EN bit. A scenario where this feature can be useful is where the same analog input is fed to

two channels and their outputs are averaged to achieve approximately a 3-dB improvement in SNR. The

mapping of DIGOUT to the ADC data is shown in 表 8.

表 8. Mapping of the DIGOUT Words to the ADC Outputs when Using Digital Averaging

LVDS PAIR THE DATA COME OUT ON

DIGOUT

RELATIONSHIP TO ADC DATA

1X DATA RATE MODE

2X DATA RATE MODE

DIGOUT1

DIGOUT2

DIGOUT3

DIGOUT4

DIGOUT5

DIGOUT6

DIGOUT7

DIGOUT8

DIGOUT9

DIGOUT10

DIGOUT11

DIGOUT12

DIGOUT13

DIGOUT14

DIGOUT15

DIGOUT16

Average of ADC1 and ADC2

DOUT1

DOUT2

DOUT3

DOUT4

—

DOUT1

Average of ADC3 and ADC4

Average of ADC5 and ADC6

DOUT2

Average of ADC7 and ADC8

Ignore

—

Ignore

—

Ignore

—

Ignore

Average of ADC9 and ADC10

Average of ADC11 and ADC12

Average of ADC13 and ADC14

Average of ADC15 and ADC16

Ignore

—

DOUT9

DOUT10

DOUT11

DOUT12

—

DOUT9

DOUT10

—

Ignore

—

Ignore

—

Ignore

—

8.3.5.1.4 Digital Gain

The digital gain block can be enabled using the DIG_GAIN_EN bit. When enabled, a digital gain programmable

from 0 dB to 6 dB in steps of 0.2 dB can be applied. To enable individual digital gain control for each input in 32-

input mode, a separate digital gain control is provided for the odd and even sample of each ADC. Therefore,

there are 32 gain controls. When using 16-input mode, set the odd and even gain controls of the same ADC to

the same value. When using 8-input mode, four sets of gain controls are to be set to the same value (the odd

and even gains of adjacent ADCs; for instance, ADC1 and ADC2).

8.3.5.1.5 Digital HPF

A digital high-pass filter (HPF) can be enabled in the path of each ADC word. The enable control is shared

between sets of four consecutive-numbered ADCs (ADC1-ADC4, ADC5-ADC8, ADC9-ADC12, and ADC13-

ADC16). For example, DIG_HPF_EN_ADC1-4 enables the HPF in the paths of ADCOUT1, ADCOUT2,

ADCOUT3, and ADCOUT4. The digital high-pass transfer function is determined by 公式 1:

2^k

Y(n) =

[x(n) - x(n - 1) + y(n - 1)]

2

^k

+ 1

(1)

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When DIG_HPF_EN_ADC1-4 is set, the value of K in 公式 1 is set by the HPF_CORNER_ADC1-4 bits. The

value of K can be programmed from 2 to 10. 表 9 shows the cutoff frequency as a function of K.

表 9. Digital HPF, –1-dB Corner Frequency versus K and f_S

CORNER FREQUENCY (k)

(HPF_CORNER_ADCx

Register)

CORNER FREQUENCY (kHz)

f_S= 40 MSPS

f_S= 50 MSPS

f_S= 65 MSPS

2

3

2780

1490

738

369

185

111

49

3480

1860

230

461

230

138

61

4520

2420

1200

600

300

180

80

4

5

6

7

8

9

25

30

40

10

12.

15

20

By default the HPF output is truncated to 14 bits. To enable the rounding operation to map the HPF output to the

ADC resolution, set the HPF_ROUND_EN_CH1-8 and HPF_ROUND_EN_CH9-16 bits to 1.

8.3.6 Data Formatting

The data formatting block does two functions: truncation and test pattern insertion. The serialization block

following the data formatting block performs a parallel-to-serial conversion of the input word. The serialization

factor is programmable to 10, 12, 14, or 16. The truncation block truncates the DIGOUT signal to the number of

bits specified by the serialization factor. The number of bits in DIGRES1 to DIGRES16 is therefore determined by

the serialization factor. Again, some of the bits in DIGRES may always be zero, depending on the combination of

ADC resolution, what digital features are enabled or disabled, and the serialization factor that is programmed. To

aid the FPGA in capturing and deserializing the serial output, the device includes provisions to replace the ADC

data with test patterns. The SERIAL_IN1 to SERIAL_IN16 signals are the same as the DIGRES1 to DIGRES16

signals during normal operation. When a test pattern is programmed, the DIGRES signals are replaced with the

appropriate test pattern. The manner in which a given test pattern actually comes out of the LVDS lines can be

altered based on the serializer operating mode because the serializer itself has multiple modes (LSB-, MSB-first

modes and 1X, 2X data rate modes).

8.3.7 Serializer and LVDS Interface

By default, each serializer takes in one SERIAL_IN word and performs a parallel-to-serial conversion. This mode

is referred to as the 1X data rate mode. In the 1X data rate mode, all 16 LVDS pairs are active and each pair

corresponds to the data coming out of one ADC. In the 2X data rate mode (set using the LVDS_RATE_2X bit),

the data from a pair of ADCs (two SERIAL_IN words) is packed into the same serial stream. In 2X mode, half the

LVDS pairs are idle and can be powered down. The 2X data rate mode causes the LVDS interface to run at

twice the rate but results in power saving. See the Timing Requirements: Signal Chain table for speed

restrictions when using the 1X and 2X data rate modes.

The LVDS interface is a clock-data-frame (CDF) format, and has a frame clock and a high-speed bit clock in

addition to the serial data lines.

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The frequency of the bit clock with respect to the conversion clock frequency depends on the serialization factor

(set using the SER_DATA_RATE bits), as shown in 表 10. Note that the serialized data are meant to be captured

on both the rising and falling edges of the bit clock. Thus, the serialized data rate is twice the bit clock frequency.

表 10. Bit Clock Rate Relationship to the Conversion Clock and System Clock Rates

BIT CLOCK RATE (f_Bin Terms of f_S)

SERIALIZATION

FACTOR

BIT CLOCK RATE

(f_Bin Terms of f_C)

DATA RATE MODE

16-INPUT MODE

32-INPUT MODE

5 × f_S

8-INPUT MODE

1X

2X

1X

2X

1X

2X

1X

2X

5 × f_C

10 × f_C

6 × f_C

5 × f_S

10 × f_S

6 × f_S

2.5 × f_S

5 × f_S

3 × f_S

6 × f_S

3.5 × f_S

7 × f_S

4 × f_S

8 × f_S

10

12

14

16

10 × f_S

6 × f_S

12 × f_C

7 × f_C

12 × f_S

7 × f_S

12 × f_S

7 × f_S

14 × f_C

8 × f_C

14 × f_S

8 × f_S

14 × f_S

8 × f_S

16 × f_C

16 × f_S

The relationship of the frame clock frequency to the conversion clock frequency for the three input modes is as

shown in 表 11. The relationship of the frame clock frequency to the system clock (and conversion clock)

frequencies is the same between the 1X and 2X data rate modes.

表 11. Relation of Frame Clock Rate to the Conversion Clock and System Clock Rates

ANALOG INPUT MODE

(Number of Channels)

FRAME CLOCK RATE

(f_Fin Terms of f_C)

FRAME CLOCK RATE

(f_Fin Terms of f_S)

DATA RATE MODES

SUPPORTED

16

32

8

f_C

0.5 × f_C

f_C

f_S

1X, 2X

1X

0.5 × f_S

1X, 2X

The serialization schemes for the various modes are illustrated in 图 64 to 图 68. Note that although the signals

marked ADCx Conversion in 图 64 to 图 68 represent a multi-bit digital word, the SERIAL_OUTx signals are

actually serialized representations of the correspondingly colored signals. For example, the blue-colored section

in the SERIAL_OUT1 signal in 图 64 contains the serial stream of data that originated from the word

corresponding to ADC1o.

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AIN1

t₂

AIN2

t₁

t_AP

System Clock, f_S

Conversion Clock, f_C

N_LAT

Frame Clock Output, f_F

t_PROP

ADC1e

ADC1o

ADC1 Conversion

SERIAL_OUT1

Serialized output of ...

Corresponding to ...

SERIAL_IN1

AIN1(t₁)

AIN1(t₂)

ADC2o

ADC2e

ADC2 Conversion

SERIAL_OUT2

Serialized output of ...

Corresponding to ...

SERIAL_IN2

AIN2(t₁)

AIN2(t₂)

图 64. ADC to Output Mapping in 16-Input, 1X Mode in LVDS Interface Mode

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t₄

t₃

t₁

t₂

AIN1

t_AP

System Clock, f_S

Conversion Clock, f_C

N_LAT

Frame Clock Output, f_F

t_PROP

ADC1o

ADC1e

ADC1 Conversion

SERIAL_OUT1

Serialized output of ...

Corresponding to ...

SERIAL_IN1

AIN1(t₁)

SERIAL_IN1

AIN1(t₃)

ADC2 Conversion

SERIAL_OUT2

ADC2o

ADC2e

Serialized output of ...

Corresponding to ...

SERIAL_IN2

AIN1(t₂)

SERIAL_IN2

AIN1(t₄)

图 65. ADC to Output Mapping in 8-Input, 1X Mode in LVDS Interface Mode

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AIN1

t₂

AIN2

t₁

t_AP

System Clock, f_S

Conversion Clock, f_C

N_LAT

Frame Clock Output, f_F

ADC1o

ADC1e

t_PROP

ADC1 Conversion

ADC2 Conversion

ADC2o

ADC2e

SERIAL_OUT1

(SERIAL_OUT2 is Idle)

SERIAL_IN2

ADC2o

SERIAL_IN1

ADC1e

SERIAL_IN2

ADC2e

Serialized output of ...

Corresponding to ...

SERIAL_IN1

ADC1o

AIN1(t₁)

AIN2(t₁)

AIN1(t₂)

AIN2(t₂)

图 66. ADC to Output Mapping in 16-Input, 2X Mode in LVDS Interface Mode

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t₄

t₃

t₁

t₂

AIN1

t_AP

System Clock, f_S

Conversion Clock, f_C

N_LAT

Frame Clock Output, f_F

ADC1 Conversion

t_PROP

ADC1o

ADC1e

ADC2o

ADC2e

ADC2 Conversion

SERIAL_OUT1

(SERIAL_OUT2 is Idle)

SERIAL_IN2

ADC2o

SERIAL_IN1

ADC1e

SERIAL_IN2

ADC2e

Serialized output of ...

Corresponding to ...

SERIAL_IN1

ADC1o

AIN1(t₁)

AIN1(t₂)

AIN1(t₃)

AIN1(t₄)

图 67. ADC to Output Mapping in 8-Input, 2X Mode in LVDS Interface Mode

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AIN1

t₁

t₂

t_AP

AIN2

t_AP

System Clock, f_S

Conversion Clock, f_C

N_LAT

Frame Clock Output, f_F

t_PROP

ADC1o

ADC1e

ADC1 Conversion

SERIAL_OUT1

Serialized output of ...

Corresponding to ...

SERIAL_IN1

AIN1(t₁)

SERIAL_IN1

AIN2(t₂)

ADC2o

ADC2e

ADC2 Conversion

SERIAL_OUT2

Serialized output of ...

Corresponding to ...

SERIAL_IN2

AIN3(t₁)

SERIAL_IN2

AIN4(t₂)

图 68. ADC to Output Mapping in 32-Input, 1X Mode in LVDS Interface Mode

The mapping of the subsequent-numbered ADC signals to subsequent-numbered SERIAL_OUT signals follows

the same pattern as indicated previously.

The serialized stream in SERIAL_OUT is a serialized representation of SERIAL_IN, which is the input word

coming into the serializer. By default, serialization is done LSB-first. By setting the MSB_FIRST bit, serialization

can be set to MSB-first.

The alignment of the frame clock, bit clock, and the serialized output data is illustrated in 图 1 for 16-input mode

where the serialization factor is set to 12 bit, serialization is LSB-first, and the data rate is set to 1X mode.

Another case is shown in 图 69 for 16-input mode. Here, the serialization factor is set to 14 bit, serialization is

MSB-first, and the data rate is set to 2X mode.

SERIAL_IN1 (D[13:0])

SERIAL_IN2 (D[13:0])

D13 D12

D11 D10 D9

D7

D5

D3

D1

D13 D12

D8

D6

D4

D2

D0

D11 D10 D9

D7

D5

D3

D1

D8

D6

D4

D2

Data (DOUT)

D0

Bit Clock (DCLK)

Frame Clock (FCLK)

图 69. LVDS Output Signals Timing Diagram in 16-Input Mode with

14-Bit Serialization, MSB-First, 2X Data Rate Mode

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The serialized signals come out on the DOUT pins as indicated in 表 12. The buffers marked Idle can be

powered down using the appropriate register bits to save power.

表 12. Mapping of the Serialized Outputs to the DOUT Pins

OUTPUT SIGNAL

LVDS OUTPUT PIN (DOUT)

1X DATA RATE MODE

SERIAL_OUT1

SERIAL_OUT2

SERIAL_OUT3

SERIAL_OUT4

SERIAL_OUT5

SERIAL_OUT6

SERIAL_OUT7

SERIAL_OUT8

SERIAL_OUT9

SERIAL_OUT10

SERIAL_OUT11

SERIAL_OUT12

SERIAL_OUT13

SERIAL_OUT14

SERIAL_OUT15

SERIAL_OUT16

2X DATA RATE MODE

SERIAL_OUT1

SERIAL_OUT3

SERIAL_OUT5

SERIAL_OUT7

Idle

DOUT1

DOUT2

DOUT3

DOUT4

DOUT5

DOUT6

DOUT7

DOUT8

DOUT9

DOUT10

DOUT11

DOUT12

DOUT13

DOUT14

DOUT15

DOUT16

Idle

SERIAL_OUT9

SERIAL_OUT11

SERIAL_OUT13

SERIAL_OUT15

Idle

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8.3.8 LVDS Buffers

A graphical representation of the 18 LVDS output buffers is shown in 图 70.

LVDS Buffer

DOUTP1

DOUTM1

DOUTP2

DOUTM2

Digital Output

DOUTP16

DOUTM16

DCLKP

DCLKM

Serial Clock

Frame Clock

FCLKP

FCLKM

图 70. LVDS Output

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The equivalent circuit of each LVDS output buffer is shown in 图 71. The buffer is designed for a differential

output impedance of 100 Ω (R_OUT). The differential outputs can be terminated at the receiver end by a 100-Ω

termination. The buffer output impedance functions like a source-side series termination. By absorbing reflections

from the receiver end, the buffer output impedance helps improve signal integrity.

Device

OUTP

+0.4 V

External

100-ꢀ Load

OUTM

R_OUT

1.03 V

-0.4 V

Switch impedance is

nominally 50 ꢀ (ê10%).

NOTE: When either the high or low switches are closed, differential R_OUT= 100 Ω.

图 71. LVDS Output Circuit

8.3.9 JESD204B Interface

8.3.9.1 Overview

When operating in 16-input and 32-input modes, the device supports a multi-lane output interface based on the

JEDEC standard: JESD204B (serial interface for data converters). This interface runs up to 5 Gbps and provides

a compact way of routing the data from multiple ADCs in the device to the FPGA. Subclasses 0, 1, and 2 of the

JESD204B interface are supported. The block diagram in 图 72 illustrates the connections of the JESD interface

to the rest of the device. After the test pattern insertion block, the parallel data streams SERIAL_IN1 to

SERIAL_IN16 can be routed to either the LVDS interface or to the JESD interface (or both). The ADC data can

be sent out using the EN_JESD and DIS_LVDS controls. The LVDS_INx and CML_INx words are the same as

the SERIAL_INx words.

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The JESD interface can be enabled by setting the EN_JESD bit to 1. When in JESD mode, the LVDS interface

can be disabled by setting the DIS_LVDS bit to 1. Both the LVDS and JESD interfaces can be simultaneously

kept active by setting the DIS_LVDS bit to 0 and the EN_JESD bit to 1.

表 13 shows the clock rates corresponding to the various clocks mentioned in the JESD204B document. This

mapping is independent of whether the device operates in 8-, 16-, or 32-input mode.

表 13. Mapping of JESD204B Clock Notation to the Clock Rates

CLOCK NOTATION IN JESD204B DOCUMENT

CORRESPONDING CLOCK RATE

Device clock

Frame clock

f_S

f_C

Conversion clock

Sample clock

All mandatory features of the JESD204B interface are supported by the device, and are:

•

Breaking up of data from the ADCs into octets.

Optional scrambling of octets to avoid spectral tones.

Conversion of (scrambled) octets to 10-bit words using 8b, 10b encoding.

Parallel-to-serial conversion of octets.

A code group synchronization (CGS) phase to enable the receiver to synchronize to the frame boundaries.

An initial lane alignment (ILA) sequence phase to help the receiver align the data from all lanes and also for

the receiver to read and verify the link configuration parameters.

•

Character replacement at frame and multi-frame boundaries during normal data transmission to enable the

receiver to monitor frame alignment.

Mechanism to achieve deterministic latency across the link using the SYSREF signal in subclass 1 and the

SYNC~ signal in subclass 2.

The Link Configuration section details only the device-specific implementation aspects of the JESD204B

interface. For additional details related to the standard, see the JEDEC standard 204B (July 2011).

8.3.9.2 Link Configuration

The JESD204B link in the device can be configured to operate in different modes using the register controls in 表

14.

表 14. Register Controls Determining Link Configuration Parameters

REGISTER CONTROL

DESCRIPTION

ALLOWED SETTINGS

NUM_ADC_PER_LANE

Number of ADC words packed into one lane

2, 4, 8

Number of bits resolution in the ADC word input to the JESD

transmitter block

ADC_RES

10, 12, 14, 16

SER_DATA_RATE

Serialization factor control

In addition to the register controls mentioned in 表 14, the SING_CONV_PER_OCT register bit controls the

packaging efficiency of the ADC data into octets.

The link configuration parameters are determined by 表 15.

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8.3.9.3 JESD Version and Subclass

The interface can be configured to operate either as a JESD204A version or as a JESD204B version.

Furthermore, when operating as a JESD204B version, the subclass can be configured as subclass 0, 1, or 2.

The register controls for programming the version and subclass are shown in 表 16.

表 16. JESD Version and Subclass Control

FIELD VALUE

ENABLE_JESD_

VER_CONTROL JESD_VERSION

JESD_

SUBCLASS

VERSION

JESD VERSION

JESD204B-subclass1

JESD204A

JESD VERSION

0

1

X⁽¹⁾

000

001

X

001

000

001

000

001

010

000

001

010

JESD204B-subclass 0

JESD204B-subclass 1

JESD204B-subclass 2

(1) X = don't care.

8.3.9.4 Transport Layer

In the JESD204B transport layer, the incoming stream of ADC samples are mapped to one or more parallel lanes

and grouped into a frame of F octets for transmission on each lane. Additional tail bits can be appended to the

ADC samples.

8.3.9.4.1 User Data Format

The interface can be configured to operate in 2, 4, or 8 lane modes (L = 2, 4, or 8). Depending on the number of

lanes used, the data from the 16 ADCs comes out in the different lanes as shown in 表 17.

表 17. Lane Mapping to CML Pins⁽¹⁾

DEFAULT

LANE ID

2 ADCS PER LANE

(8-Lane Mode)⁽²⁾

4 ADCS PER LANE

(4-Lane Mode)⁽²⁾

8 ADCS PER LANE

(2-Lane Mode)⁽²⁾

MAPPING TO THE PINS

1

2

3

4

5

6

7

8

CML1_OUTP-CML1_OUTM

CML2_OUTP-CML2_OUTM

CML3_OUTP-CML3_OUTM

CML4_OUTP-CML4_OUTM

CML5_OUTP-CML5_OUTM

CML6_OUTP-CML6_OUTM

CML7_OUTP-CML7_OUTM

CML8_OUTP-CML8_OUTM

ADC1, ADC2

ADC3, ADC4

ADC5, ADC6

ADC7, ADC8

ADC9, ADC10

ADC11, ADC12

ADC13, ADC14

ADC15, ADC16

ADC1…ADC4

ADC1…ADC8

—

ADC5…ADC8

—

ADC9…ADC12

ADC9…ADC16

—

ADC13…ADC16

—

(1) More accurately, ADC1…ADC16 corresponds to CML_IN1…CML_IN16 as illustrated in 图 72.

(2) Determined by the NUM_ADC_PER_LANE register control.

The unused lanes are automatically powered down.

The device supports several combinations of ADC resolutions and number of lanes. There are no control bits or

control words (CF = 0). The device has two modes of data packing: normal packing mode and single converter

per octet mode. The packing mode can be chosen using the SING_CONV_PER_OCT register control. The

number of ADCs per lane can be programmed to 8, 4, or 2 using the NUM_ADC_PER_LANE register control.

The number of ADCs per lane automatically determines the value of L (the number of lanes). The values of N’

and F for the different modes are described in 表 18.

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表 18. Different JESD204B Interface Modes of Operation

N⁽³⁾

SINGLE CONVERTER PER

OCTET MODE⁽¹⁾

NORMAL PACKING MODE⁽¹⁾

(Resolution of

ADC Word

Input to the

JESD204B

Transmitter)

NUMBER OF

ADCS PER

LANE, N_AL

SER_DATA_

RATE,

ADC_RES,

N_RES

(Bits)

L⁽³⁾

(Lanes)

(1)

N'⁽³⁾

F⁽³⁾

N'⁽³⁾

F⁽³⁾

(1)

N_SER⁽¹⁾⁽²⁾(Bits)

(Total Number

of Bits)

(Octets per

Frame)

(Total Number

of Bits)

(Octets per

Frame)

SER_DATA_

RATE

SER_DATA_

RATE

8

4

10, 12, 14, 16

2

4

ADC_RES

16

16⁽⁵⁾

8⁽⁵⁾

(4)

SER_DATA_

RATE⁽⁴⁾

SER_DATA_

RATE/2

10

12

14

16

10

ADC_RES

12

16

3⁽⁶⁾

16

4⁽⁵⁾

10, 12

3

2

8

10, 12, 14

10, 12, 14, 16

4⁽⁶⁾

4

(1) Value or mode is set by programming the appropriate registers.

(2) SER_DATA_RATE must be greater than or equal to ADC_RES.

(3) Automatically calculated and set by the device.

(4) When SER_DATA_RATE > ADC_RES, then each ADC word is additionally padded with the (SER_DATA_RATE – ADC_RES) number

of zeros on the LSB side to create the‘JESD ADC word. Each JESD ADC word is broken up into nibbles. Incomplete nibbles (if any) are

stuffed with the starting bits of the subsequent JESD ADC word for maximum data packing.

(5) Each ADC sample is broken into two octets; the incomplete octet is completed using zeros as tail bits.

(6) Each ADC sample is broken into nibbles; incomplete nibbles are completed using zeros as tail bits.

The data packing modes are described in 表 19 to 表 24 for different modes of operation. Lane 1 is used for

illustration purposes in these tables.

(1)

表 19. Data Packing in Normal Packing Mode for N_AL= 8 and N_RES= N_SER

N_RES= 10, N_SER= 10

N_RES= 12, N_SER= 12

N_RES= 14, N_SER= 14

N_RES= 16, N_SER= 16

OCTET

NIBBLE 1

NIBBLE 2

NIBBLE 1

NIBBLE 2

NIBBLE 1

NIBBLE 2

NIBBLE 1

NIBBLE 2

1

2

3

4

5

6

ADC1[9:6]

ADC1[5:2]

ADC1[11:8]

ADC1[7:4]

ADC1[13:10]

ADC1[9:6]

ADC1[15:12]

ADC1[11:8]

ADC1[1:0],

ADC2[9:8]

ADC1[1:0],

ADC2[13:12]

ADC2[7:4]

ADC3[9:6]

ADC1[3:0]

ADC2[7:4]

ADC3[11:8]

ADC3[3:0]

ADC4[7:4]

ADC2[11:8]

ADC2[3:0]

ADC3[7:4]

ADC4[11:8]

ADC4[3:0]

ADC1[5:2]

ADC2[11:8]

ADC2[3:0]

ADC3[9:6]

ADC1[7:4]

ADC2[15:12]

ADC2[7:4]

ADC1[3:0]

ADC2[11:8]

ADC2[3:0]

ADC3[11:8]

ADC3[3:0]

ADC2[3:0]

ADC3[5:2]

ADC4[7:4]

ADC5[9:6]

ADC2[7:4]

ADC3[13:10]

ADC3[5:2]

ADC3[1:0],

ADC4[9:8]

ADC4[3:0]

ADC3[15:12]

ADC3[7:4]

ADC3[1:0],

ADC4[13:12]

ADC5[5:2]

ADC4[11:8]

ADC5[1:0],

ADC6[9:8]

7

8

9

ADC6[7:4]

ADC7[9:6]

ADC5[11:8]

ADC5[3:0]

ADC6[7:4]

ADC5[7:4]

ADC6[11:8]

ADC6[3:0]

ADC4[7:4]

ADC5[13:10]

ADC5[5:2]

ADC4[3:0]

ADC5[9:6]

ADC4[15:12]

ADC4[7:4]

ADC4[11:8]

ADC4[3:0]

ADC5[11:8]

ADC6[3:0]

ADC7[1:0],

ADC8[9:8]

ADC5[1:0],

ADC6[13:12]

ADC7[5:2]

ADC5[15:12]

ADC5[7:4]

10

11

12

ADC7[7:4]

ADC8[3:0]

ADC7[11:8]

ADC7[3:0]

ADC8[7:4]

ADC7[7:4]

ADC8[11:8]

ADC8[3:0]

ADC6[11:8]

ADC6[3:0]

ADC7[9:6]

ADC6[7:4]

ADC5[3:0]

ADC6[11:8]

ADC6[3:0]

—

ADC7[13:10] ADC6[15:12]

ADC7[5:2]

ADC6[7:4]

ADC7[1:0],

ADC8[13:12]

13

—

ADC8[11:8]

ADC7[15:12]

ADC7[11:8]

14

15

16

—

ADC8[7:4]

ADC8[3:0]

ADC7[7:4]

ADC8[15:12]

ADC8[7:4]

ADC7[3:0]

ADC8[11:8]

ADC8[3:0]

—

(1) A similar data packing scheme is used for other lanes with the mapping of ADCs per lane as indicated in 表 17.

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(1)

表 20. Data Packing in Normal Packing Mode for N_AL= 8 and N_SER> N_RES

N_RES= 10, N_SER= 12

NIBBLE 1

N_RES= 12, N_SER= 14

NIBBLE 1

N_RES= 14, N_SER= 16

NIBBLE 2

ADC1[5:2]

ADC2[9:6]

ADC2[1:0], 00

ADC3[5:2]

ADC4[9:6]

ADC4[1:0], 00

ADC5[5:2]

ADC6[9:6]

ADC6[1:0], 00

ADC7[5:2]

ADC8[9:6]

ADC8[1:0], 00

—

NIBBLE 2

ADC1[7:4]

00,ADC2[11:10]

ADC2[5:2]

ADC3[11:8]

ADC3[3:0]

ADC4[9:6]

ADC4[1:0],00

ADC5[7:4]

00,ADC6[11:10]

ADC6[5:2]

ADC7[11:8]

ADC7[3:0]

ADC8[9:6]

ADC8[1:0],00

—

NIBBLE 1

NIBBLE 2

ADC1[9:6]

1

2

ADC1[9:6]

ADC1[1:0], 00

ADC2[5:2]

ADC3[9:6]

ADC3[1:0], 00

ADC4[5:2]

ADC5[9:6]

ADC5[1:0], 00

ADC6[5:2]

ADC7[9:6]

ADC7[1:0], 00

ADC8[5:2]

—

ADC1[11:8]

ADC1[3:0]

ADC2[9:6]

ADC2[1:0],00

ADC3[7:4]

00,ADC4[11:10]

ADC4[5:2]

ADC5[11:8]

ADC5[3:0]

ADC6[9:6]

ADC6[1:0],00

ADC7[7:4]

00,ADC8[11:10]

ADC8[5:2]

—

ADC1[13:10]

ADC1[5:2]

ADC1[1:0], 00

ADC2[9:6]

3

ADC2[13:10]

ADC2[5:2]

4

ADC2[1:0], 00

ADC3[9:6]

5

ADC3[13:10]

ADC3[5:2]

6

ADC3[1:0], 00

ADC4[9:6]

7

ADC4[13:10]

ADC4[5:2]

8

ADC4[1:0], 00

ADC5[9:6]

9

ADC5[13:10]

ADC5[5:2]

10

11

12

13

14

15

16

ADC5[1:0], 00

ADC6[9:6]

ADC6[13:10]

ADC6[5:2]

ADC6[1:0], 00

ADC7[9:6]

ADC7[13:10]

ADC7[5:2]

—

ADC7[1:0], 00

ADC8[9:6]

—

ADC8[13:10]

ADC8[5:2]

—

ADC8[1:0], 00

(1) A similar data packing scheme is used for other lanes with the mapping of ADCs per lane as indicated in 表 17.

(1)

表 21. Data Packing in Normal Packing Mode for N_AL= 4 and N_RES= N_SER

N_RES= 10, NSER = 10

N_RES= 12, N_SER= 12

N_RES= 14, N_SER= 14

N_RES= 16, N_SER= 16

OCTET

NIBBLE 1

NIBBLE 2

NIBBLE 1

NIBBLE 2

NIBBLE 1

NIBBLE 2

NIBBLE 1

NIBBLE 2

1

2

3

4

5

6

ADC1[9:6]

ADC1[5:2]

ADC1[11:8]

ADC1[7:4]

ADC1[13:10]

ADC1[9:6]

ADC1[15:12]

ADC1[11:8]

ADC1[1:0],

ADC2[9:8]

ADC1[1:0],

ADC2[13:12]

ADC2[7:4]

ADC3[9:6]

ADC1[3:0]

ADC2[7:4]

ADC3[11:8]

ADC3[3:0]

ADC4[7:4]

ADC2[11:8]

ADC2[3:0]

ADC3[7:4]

ADC4[11:8]

ADC4[3:0]

ADC1[5:2]

ADC2[11:8]

ADC2[3:0]

ADC3[9:6]

ADC1[7:4]

ADC2[15:12]

ADC2[7:4]

ADC1[3:0]

ADC2[11:8]

ADC2[3:0]

ADC3[11:8]

ADC3[3:0]

ADC2[3:0]

ADC3[5:2]

ADC4[7:4]

—

ADC2[7:4]

ADC3[13:10]

ADC3[5:2]

ADC3[1:0],

AD4[9:8]

ADC4[3:0]

ADC3[15:12]

ADC3[7:4]

ADC3[1:0],

ADC4[13:12]

—

ADC4[11:8]

7

8

—

ADC4[7:4]

—

ADC4[3:0]

—

ADC4[15:12]

ADC4[7:4]

ADC4[11:8]

ADC4[3:0]

(1) A similar data packing scheme is used for other lanes with the mapping of ADCs per lane as indicated in 表 17.

(1)

表 22. Data Packing in Normal Packing Mode for N_AL= 4 and N_SER> N_RES

N_RES= 10, NSER = 12

NIBBLE 1

N_RES= 12, N_SER= 14

NIBBLE 1

N_RES= 14, N_SER= 16

OCTET

NIBBLE 2

ADC1[5:2]

ADC2[9:6]

ADC2[1:0], 00

ADC3[5:2]

ADC4[9:6]

ADC4[1:0], 00

—

NIBBLE 2

ADC1[7:4]

00,ADC2[11:10]

ADC2[5:2]

ADC3[11:8]

ADC3[3:0]

ADC4[9:6]

ADC4[1:0],00

—

NIBBLE 1

NIBBLE 2

ADC1[9:6]

1

2

3

4

5

6

7

8

ADC1[9:6]

ADC1[1:0], 00

ADC2[5:2]

ADC3[9:6]

ADC3[1:0], 00

ADC4[5:2]

—

ADC1[11:8]

ADC1[3:0]

ADC2[9:6]

ADC2[1:0],00

ADC3[7:4]

00,ADC4[11:10]

ADC4[5:2]

—

ADC1[13:10]

ADC1[5:2]

ADC1[1:0], 00

ADC2[9:6]

ADC2[13:10]

ADC2[5:2]

ADC2[1:0], 00

ADC3[9:6]

ADC3[13:10]

ADC3[5:2]

ADC3[1:0], 00

ADC4[9:6]

ADC4[13:10]

ADC4[5:2]

—

ADC4[1:0], 00

(1) A similar data packing scheme is used for other lanes with the mapping of ADCs per lane as indicated in 表 17.

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表 23. Data Packing in Normal Packing Mode for N_AL= 2⁽¹⁾

N_RES= 10, NSER = 10 or 12

N_RES= 12, N_SER= 12

N_RES= 14, N_SER= 14 or 16

N_RES= 16, N_SER= 16

OCTET

NIBBLE 1

ADC1[9:6]

ADC1[1:0], 00

ADC2[5:2]

—

NIBBLE 2

ADC1[5:2]

ADC2[9:6]

ADC3[1:0], 00

—

NIBBLE 1

ADC1[11:8]

ADC1[3:0]

ADC2[7:4]

—

NIBBLE 2

ADC1[7:4]

ADC2[11:8]

ADC2[3:0]

—

NIBBLE 1

ADC1[13:10]

ADC1[5:2]

NIBBLE 2

ADC1[9:6]

NIBBLE 1

ADC1[15:12]

ADC1[7:4]

NIBBLE 2

ADC1[11:8]

ADC1[3:0]

ADC2[11:8]

ADC2[3:0]

1

2

3

4

ADC1[1:0], 00

ADC2[9:6]

ADC2[13:10]

ADC2[5:2]

ADC2[15:12]

ADC2[7:4]

ADC2[1:0], 00

(1) A similar data packing scheme is used for other lanes with the mapping of ADCs per lane as indicated in 表 17.

(1)(2)

表 24. Data Packing in Single Converter per Octet Packing Mode for N_AL= 8 (Independent of N_SER

)

N_RES= 10

N_RES= 12

N_RES= 14

N_RES= 16, N_SER= 16

OCTET

NIBBLE 1

NIBBLE 2

ADC1[5:2]

0000

NIBBLE 1

NIBBLE 2

ADC1[7:4]

0000

NIBBLE 1

NIBBLE 2

ADC1[9:6]

NIBBLE 1

ADC1[15:12]

ADC1[7:4]

NIBBLE 2

ADC1[11:8]

ADC1[3:0]

ADC2[11:8]

ADC2[3:0]

ADC3[11:8]

ADC3[3:0]

ADC4[11:8]

ADC4[3:0]

ADC5[11:8]

ADC5[3:0]

ADC6[11:8]

ADC6[3:0]

ADC7[11:8]

ADC7[3:0]

ADC8[11:8]

ADC8[3:0]

1

2

ADC1[9:6]

ADC1[1:0], 00

ADC2[9:6]

ADC1[11:8]

ADC1[3:0]

ADC2[11:8]

ADC2[3:0]

ADC3[11:8]

ADC3[3:0]

ADC4[11:8]

ADC4[3:0]

ADC5[11:8]

ADC5[3:0]

ADC6[11:8]

ADC6[3:0]

ADC7[11:8]

ADC7[3:0]

ADC8[11:8]

ADC8[3:0]

ADC1[13:10]

ADC1[5:2]

ADC1[1:0], 00

ADC2[9:6]

3

ADC2[5:2]

0000

ADC2[7:4]

0000

ADC2[13:10]

ADC2[5:2]

ADC2[15:12]

ADC2[7:4]

4

ADC2[1:0], 00

ADC3[9:6]

ADC2[1:0], 00

ADC3[9:6]

5

ADC3[5:2]

0000

ADC3[7:4]

0000

ADC3[13:10]

ADC3[5:2]

ADC3[15:12]

ADC3[7:4]

6

ADC3[1:0], 00

ADC4[9:6]

ADC3[1:0], 00

ADC4[9:6]

7

ADC4[5:2]

0000

ADC4[7:4]

0000

ADC4[13:10]

ADC4[5:2]

ADC4[15:12]

ADC4[7:4]

8

ADC4[1:0], 00

ADC5[9:6]

ADC4[1:0], 00

ADC5[9:6]

9

ADC5[5:2]

0000

ADC5[7:4]

0000

ADC5[13:10]

ADC5[5:2]

ADC5[15:12]

ADC5[7:4]

10

11

12

13

14

15

16

ADC5[1:0], 00

ADC6[9:6]

ADC5[1:0], 00

ADC6[9:6]

ADC6[5:2]

0000

ADC6[7:4]

0000

ADC6[13:10]

ADC6[5:2]

ADC6[15:12]

ADC6[7:4]

ADC6[1:0], 00

ADC7[9:6]

ADC6[1:0], 00

ADC7[9:6]

ADC7[5:2]

0000

ADC7[7:4]

0000

ADC7[13:10]

ADC7[5:2]

ADC7[15:12]

ADC7[7:4]

ADC7[1:0], 00

ADC8[9:6]

ADC7[1:0], 00

ADC8[9:6]

ADC8[5:2]

0000

ADC8[7:4]

0000

ADC8[13:10]

ADC8[5:2]

ADC8[15:12]

ADC8[7:4]

ADC8[1:0], 00

(1) For N_AL= 4, use the first eight octets. For N_AL= 2, use the first four octets.

(2) A similar data packing scheme is used for other lanes with the mapping of ADCs per lane as indicated in 表 17.

Tail bits (in modes where applicable) are set to 0. There is no option for a pseudo-random generator for

generating the tail bits. When a converter is powered down, the corresponding sample is replaced by a dummy

sample that corresponds to all zeros. There is no option for a pseudo-random generator for generating the

dummy samples. The value S (number of samples per ADC per frame minus 1) is always 0 and HD mode is not

supported.

8.3.9.4.2 Transport Layer Test Patterns

All test patterns described in the LVDS Test Pattern Mode section can be set, even with the JESD204B interface.

These test patterns serve as transport layer test modes for the JESD interface. These test patterns can replace

the normal ADC data going into the JESD204B link layer.

8.3.9.5 Scrambler

An optional scrambler is implemented in the device using the polynomial as defined in the JESD204B standard.

The scrambler can be enabled using the SCR_EN register control. The scrambler is bypassed during the code

group synchronization and transmission of the initial lane alignment sequence. There is no alternate scrambler to

keep processing the user data during these states.

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8.3.9.6 Data Link Layer

The data link layer of the JESD204B block handles various functions (such as the 8b, 10b encoding of the input

octets, code group synchronization (CGS), transmission of an initial lane alignment (ILA) sequence, frame

alignment character replacement, and transmission of link layer test patterns). As specified by the standard, the

device uses 8b, 10b coding to encode the data before being transmitted. The frame contents are processed from

MSB to LSB.

8.3.9.6.1 Code Group Synchronization (CGS)

In the CGS state, the device transmits a set of /K28.5/ characters that are used by the receiver to recover the

clock and data from the serial stream using a clock and data recovery (CDR) circuit, and also to align to the

symbol boundaries. The device enters the CGS state when it receives an active (low going) SYNC pulse that is

at least four device clocks wide. In addition, when the device is in the CGS state as defined by the JESD204B

standard, the device can also be made to transmit a stream of /K28.5/ symbols by programming the

TX_SYNC_REQ register control.

8.3.9.6.2 Initial Lane Alignment (ILA)

By default, the CGS phase is followed by the transmission of an ILA sequence. The ILA transmission can be

disabled using the LINK_CONFIG_DIS register control. Transitioning from a CGS state to an ILA sequence state

occurs on the local multiframe clock (LMFC) boundary. By default, the transition occurs at the first LMFC

boundary after SYNC~ is deasserted. However, the transition point can be delayed to the second, third, or fourth

LMFC edge by programming the RELEASE_ILA register control to 1, 2, or 3, respectively. This mode can be

used to provide sufficient time to the receiver to achieve synchronization.

8.3.9.6.3 Lane and Frame Alignment Monitoring

The lane and frame alignment monitoring and character replacement are as per the JESD204B standard. The

insertion of frame and lane alignment characters can be enabled by setting the LANE_ALIGN and

FRAME_ALIGN register controls. These controls, in conjunction with the SCR_EN control, determine the

mechanism of the lane and frame alignment character replacement, as shown in 表 25.

表 25. Character Replacement for Lane and Frame Alignment

SCR_EN

FRAME_ALIGN LANE_ALIGN

EFFECT ON LINK DATA

0

ADC data are sent without any character replacement.

If the last octet of the multiframe is the same as the last octet of the previous

multiframe, then the last octet is replaced with /K28.3/.

0

1

If the last octet of the frame is the same as the last octet of the previous frame, then

the last octet is replaced with /K28.7/. If an alignment character has already been

sent in the previous frame, then no characters are replaced.

0

1

0

1

0

1

0

Frame and lane alignment character replacements are enabled.

ADC data are scrambled and sent without any character replacement.

If the last scrambled octet of the multiframe is D28.3, then that octet is replaced with

/K28.3/.

1

0

1

If the last scrambled octet of the frame is D28.7, then that octet is replaced with

/K28.7/.

1

0

1

Frame and lane alignment character replacements are enabled with scrambling.

8.3.9.6.4 Link Layer Test Modes

The JESD link can be tested by transmitting predetermined 8b, 10b characters in all frames and on all lanes.

Test modes can be enabled with the LINK_LAYER_TESTMODES register control. These test patterns are never

scrambled. A pseudo-random pattern of 120 bits corresponds to the random pattern (RPAT). An additional PRBS

pattern can be output by setting the transport layer test mode to a constant pattern and enabling the scrambler. A

scrambled jitter pattern (JSPAT) is not supported.

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8.3.9.7 Deterministic Latency

Deterministic latency is achieved in the subclass 1 and subclass 2 of the JESD204B standard through a local

multiframe clock (LMFC) that is synchronized between the transmitter and receiver. The phase of the LMFC is

dictated by the sampled SYSREF input in subclass 1 and by the SYNC~ rising edge in subclass 2.

8.3.9.7.1 Synchronization Using SYNC~ and SYSREF

In order to achieve deterministic latency across the entire link, the device supports system-level link

synchronization using the SYNC~ (in subclass 2) and SYSREF (in subclass 1) signals, as mentioned in the

JESD204B standards document. The mapping of these signals to the pin voltages is shown in 表 26.

表 26. Mapping of the JESD204B Signals to Device Pins

SIGNAL NOTATION IN JESD204B DOCUMENT

RELATION TO DEVICE PINS

ADC_CLKP – ADC_CLKM

Device clock

SYNC~

SYSREF⁽¹⁾

SYNCP_SERDES – SYNCM_SERDES

SYSREFP_SERDES – SYSREFM_SERDES

(1) Must be inactive (low) except when operating in JESD204B subclass 1.

JESD subclasses 1 and 2 use an internal clock called the local multiframe clock (LMFC) to achieve deterministic

latency in the link. The phase of the LMFC clock is set based on the device clock rising edge that the SYSREF

(in subclass 1) or SYNC~(in subclass 2) signals are sampled on. The device clock is the highest speed input

clock for the device and there is no provision for a higher speed adjustment clock to achieve phase adjustments

finer than what is achievable using the device clock. By default, the LMFC count is reset to 0 during a SYNC~ or

SYSREF event. This reset count can be forced to a different value by using the FORCE_LMFC_COUNT and

LMFC_COUNTER_INIT_VALUE register controls. The LMFC does not exist in JESD subclass 0.

SYSREF can be a periodic, one-shot, or gapped periodic active-high signal that is sampled on the rising edge of

the device clock. There is no option to sample the SYSREF signal on the falling edge of the device clock. If

SYSREF is a periodic or gapped periodic signal, then its periodicity must be a multiple of the LMFC period in

order to avoid unwanted sudden shifts in the phase of the LMFC. Note that a continuous periodic SYSREF can

cause spurious degradation in the ADC performance because of energy coupling into the device at a rate that is

a sub-harmonic of the device clock rate.

In addition to resetting the phase of the LMFC, SYSREF (or SYNC~) also resets some of the other internal clock

dividers not related to the JESD block and affects the reset of the phase of the test pattern generator (see the

LVDS Test Pattern Mode section). SYSREF (or SYNC~) also affects the reset of the frame clock phases and the

odd or even sampling selection in 32-channel mode.

The default mode is to reset all internal dividers as well as the phase of the LMFC during every SYSREF (or

SYNC~) event based on the JESD subclass.

The reset operations based on SYNC~ and SYSREF for the different subclasses occurs as shown in 表 27.

表 27. Reset Operations from SYNC~ or SYSREF in the Various JESD204B Subclasses

What gets reset

EVENT CONTROLLING THE

SUBCLASS

JESD BLOCK (Phase of the LMFC

Clock)

RESET

REST OF DEVICE

JESD204B-subclass 0

JESD204B-subclass 1

JESD204B-subclass 2

JESD204A

SYNC~ rising edge

SYSREF⁽¹⁾

Not applicable

Yes

SYNC~ rising edge

Yes

Not applicable

(1) To avoid unexpected reset behavior, SYSREF must be active only when operating in JESD204B subclass 1.

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表 28 lists the register controls to selectively mask the reset operations of the various blocks.

表 28. Masking of the Various Reset Operations Resulting from SYNC~ or SYSREF

MASKS RESET OPERATION IN

REGISTER BIT

JESD BLOCK (Phase of the

LMFC Clock)

CLOCK DIVIDERS

OTHER SYNCHRONIZATION⁽¹⁾

JESD_RESET1

JESD_RESET2

No

Yes

No

Yes

(1) Demodulators and test pattern generation.

The JESD_RESET1 and JESD_RESET2 bits mask the reset operations as indicated in 表 28 for all subsequent

SYNC~ and SYSREF events after the bits are set. The JESD_RESET3 register bit is functionally similar to

JESD_RESET2 (in terms of masking the reset function to the blocks). However, when JESD_RESET3 is set, this

bit allows the first SYNC~ or SYSREF event to reset all clock dividers, takes affect, and masks the reset of the

LMFC clock divider only after the first SYNC~ or SYSREF event occurs. The JESD_RESET1, JESD_RESET2,

and JESD_RESET3 bits can be used appropriately to avoid unwanted reset operations resulting from SYNC~

and SYSREF events.

When SYSREF resets the rest of the device, the ADC data can be corrupted for four to six clocks. If SYSREF is

periodic, then periodic corruption of ADC data can result. Thus, when using a periodic or a gapped periodic

SYSREF, one JESD_RESET (JESD_RESET1, JESD_RESET2, or JESD_RESET3) must be set to 1.

8.3.9.7.2 Latency

图 73 to 图 76 illustrate the relevant latencies for the JESD interface with the default mode of operation (four

ADCs per lane mode, N_ADC= 12, N_SER= 12, and K = 3) used for illustration purposes.

N+3

N+4

N+2

N+1

Sample

N

Analog Input

to ADC1

t_AP

ADC_CLKP

ADC_CLKM

(3)

t_{D_JESD}

N_{LAT_JESD}

CML_OUT⁽¹⁾

Output⁽²⁾

N

Output

N+1

Output

N+2

(1) CML_OUT is shown broken in terms of octets.

(2) The ADC word corresponding to ADC1 is contained in the first two octets of output N.

(3) t_{D_JESD}is a small additional variable delay which is a fraction of the device clock period.

图 73. ADC Latency in JESD Mode

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SYNC~ is latched by the device.

ADC_CLKP

ADC_CLKM

t_{SU_T}

t_{H_T}

SYNC~

N_{A_SYNC~}

CGS Phase

CML_OUT⁽¹⁾

= K28.5

= Data

(1) CML_OUT is broken in terms of octets.

图 74. Latency from SYNC~ Assertion to Start of CGS Phase

SYSREF is latched

by the device.

SYNC~ is latched

by the device.

ADC_CLKP

ADC_CLKM

Input Clock

SYSREF

LMFC

(Internal Signal)

1st LMFC boundary after SYNC~.

SYNC~

N_{D_SYNC~}

ILA Sequence

CML_OUT

CGS Phase

= K28.5

= K28.0

图 75. Latency from SYNC~ Deassertion to Start of ILA Phase in Subclass 1

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SYNC~ is latched

by the device.

ADC_CLKP

Input Clock

ADC_CLKM

LMFC

(Internal Signal)

1st LMFC boundary after SYNC~.

SYNC~

N_{D_SYNC~}

ILA Sequence

CML_OUT

CGS Phase

= K28.5

= K28.0

图 76. Latency from SYNC~ Deassertion to Start of ILA Phase in Subclass 2

8.3.9.7.3 Multiframe Size

The size of the multiframe (as well as the periodicity of the LMFC clock) is denoted as K. Multiframe size is

calculated as shown in 公式 2:

Ceil (17 / Number of Octets per Frame) ≤ Multiframe Size (In Terms of Number of Frames)

(2)

表 29 lists the multiframe size for different modes of operation.

表 29. Multiframe Size in Different Modes⁽¹⁾

2 ADCS PER LANE⁽²⁾

MULTIFRAME SIZE

FRAMES OCTETS

18

4 ADCS PER LANE⁽²⁾

8 ADCS PER LANE⁽²⁾

MULTIFRAME SIZE

ADC

RESOLUTION FRAME SIZE

MULTIFRAME SIZE

FRAME SIZE

(Octets)

(Bits)

(Octets)

FRAMES

OCTETS

FRAMES

OCTETS

12

3

4

6

7

8

3

18

21

24

12

2

24

28

32

14

5

20

14

16

(1) The decimal equivalent of K[4:0] in the link configuration parameter is equal to the multiframe size (in frames) minus 1.

(2) Determined by the register control NUM_ADC_PER_LANE.

8.3.9.8 JESD Physical Layer

The JESD transmitter uses a PLL that runs off an internal low-dropout (LDO) regulator that provides noise

rejection on the external 1.2-V supply. At higher speeds (beyond 4 Gbps), the LDO voltage drops because of

increased switching currents. To improve the jitter at higher speeds, restore the LDO voltage with the

INC_JESD_VDD register control.

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8.3.9.8.1 CML Buffer

The device JESD204B transmitter uses differential CML output drivers with a typical current drive of 16 mA. The

output driver includes an internal 50-Ω termination to the DVDD_1P2 supply. Additionally, external 50-Ω

termination resistors connected to DVDD_1P2 must be placed close to the receiver pins. DC compliance to the

standard is not ensured and ac coupling can be used to avoid the common-mode mismatch between the

transmitter and receiver, as shown in 图 77.

DVDD_1P2

CM

CML Buffer (TX)

50 Ω

50 W (Typ)

CML1_

OUTP

Z_O= 50 W

0.1 mF

LO

HI

CML

Receiver

16 mA

(Typ)

CML1_

OUTM

Z_O= 50 W

50 Ω

50 W (Typ)

CM

DVDD_1P2

图 77. CML Output Connections

The CML buffer also has a pre-emphasis control for improving the timing margins. Pre-emphasis is achieved by

increasing the CML buffer current if the current transmitter bit is different from the previous one. The current of

the CML buffer for a transitioning bit can be increased from the CML buffer current setting to one of 16 settings in

steps of 0.25 mA using the PRE_EMP register control. Pre-emphasis is recommended to be used at higher

speeds in order to improve the timing margins.

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8.3.9.8.2 Jitter Considerations

图 78 shows the data eye measurement of the device JESD204B transmitter against the JESD204B transmitter

eye mask at 3.125 Gbps.

图 78. Eye Diagram at the CML Output at a Data Rate of 3.125 Gbps

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图 79 shows the data eye measurement of the device JESD204B transmitter against the JESD204B transmitter

eye mask at 5 Gbps. This measurement is taken with PRE_EMP set to 7.

图 79. Eye Diagram at the CML Output at a Data Rate of 5 Gbps

The total jitter as a fraction of the UI changes with interface speed, pre-emphasis setting, and the length of the

trace from the transmitter pins to the external termination resistor. The total jitter at the transmitter pins can

exceed the transmitter eye mask specification for speeds beyond 5 Gbps. However, the interface can be made to

work (and meet the eye mask specification at the receiver inputs) at speeds higher than 5 Gbps for short trace

lengths. 图 40 illustrates the total jitter as a function of the trace length (between the transmitter pins and the

termination resistor) for 5-Gbps, 6-Gbps, and 6.4-Gbps speeds. 图 41 to 图 43 illustrate the total jitter as a

function of the trace length for different pre-emphasis settings at 5 Gbps, 6 Gbps, and 6.4 Gbps, respectively.

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8.3.10 Interfacing SYNC~ and SYSREF Between the FPGA and ADCs

The SYNC~ and SYSREF signals must be connected to the FPGA and the multiple ADCs in the system. When

driving SYNC~ and SYSREF using differential signals, additional interface circuits may be required to decouple

the common-mode levels between the FPGA and the ADC. 图 80 shows an overview of such a scheme for

driving the SYNC~ signal from the FPGA to multiple ADCs.

SYNC~ (eg. LVDS level)

FPGA

Interface circuit(s)

ADC1

ADC2

ADCn

图 80. Connection of SYNC~ From the FPGA to the ADCs

The ADC has internal 5-kΩ resistors from the SYNCP and SYNCM pins to an internal reference voltage of 0.7 V.

When driven by a differential driver, an interface circuit may be required to match the common-mode voltages

between the driver and the ADC. An example circuit is shown in 图 81 to level-shift from a 1.2-V common-mode

voltage at the driver output to the 0.7 V at the ADC input. The 100 Ω at the driver output depicts the differential

termination and could be realized inside the FPGA.

3.57 KΩ

FPGA

ADC

33 nF

SYNCP_FPGA

SYNCP_ADC

5 KΩ

VOCM = 1.2 V

100 Ω

0.7 V

33 nF

SYNCM_ADC

SYNCM_FPGA

5 KΩ

3.57 KΩ

图 81. Circuit to Level-Shift the Common-Mode Voltage From 1.2 V at the Driver Output to 0.7 V at the

ADC Input

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For a different driver output common-mode than the one shown in 图 81, the interface circuit must be modified.

A similar circuit as shown in 图 81 can also be used to interface the SYSREF signals to the ADC. As shown in 图

82, the SYSREF signal can also be driven using an ac-coupling scheme. The external components are chosen

for a case where the SYSREF source drives only one ADC. The values of these components must be changed if

the signal is interfaced to multiple ADCs (contact the factory for details).

1.8 V

50 KΩ

ADC

1 uF

SYSREFM_SRC

SYSREFM_ADC

5 KΩ

100 Ω

0.7 V

SYSREF Source

5 KΩ

SYSREFP_ADC

SYSREFP_SRC

1 uF

30 KΩ

图 82. AC-Coupling Scheme for SYSREF (do not use for SYNC~)

SYSREFM_SRC

SYSREFP_SRC

SYSREFM_ADC

SYSREFP_ADC

c

SYSREF high pulse should be less wide than this point

图 83. Transient of SYSREF With AC-Coupling

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The 50-kΩ and 30-kΩ external resistors along with the two 5-kΩ resistors internal to the ADC form a voltage

divider circuit to generate a negative differential offset at the ADC SYSREF input when SYSREF is low. A high-

going pulse on the SYSREF_SRC signal passes through the ac-coupling capacitor. The ac-coupling capacitor

and the resistors form a high-pass filter and cause the SYSREF_ADC signal to droop towards their quiescent

values over time (denoted by the dotted lines in 图 83). However, if the high width of SYSREF is much lower

than the time constant of the filter, the circuit is able to pass the pulse properly.

The SYNC~ and SYSREF signals also can be driven using single-ended LVCMOS levels, which can be done by

driving the P side with the LVCMOS level and connecting the M side to ground as shown in 图 84. When driven

in this manner, the internal 5-kΩ resistor (connecting the P and M pins to the 0.7-V node) is disconnected from

the pins.

LVCMOS

Clock Input

LVCMOS

Clock Input

SYNCP_SERDES

SYSREFP_SERDES

SYNCM_SERDES

SYSREFM_SERDES

图 84. Single-Ended Driving Circuit for SYNC~ and SYSREF

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8.3.11 Clock Input

The input clock to the device (referred to as the system clock) goes to an input buffer that automatically

configures itself either to accept a single-ended clock or a differential clock. The equivalent load on the clock pins

in the case of a differential clock input is shown in 图 85. For the case of a single-ended clock input, the 5-kΩ

resistor is disconnected from the input.

AVDD_1P8

0.7 V

VCM

100 pF

5 kQ

CLKP

6 pF

CLKM

图 85. Internal Clock Buffer for Differential Clock Mode

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If the preferred clocking scheme for the device is single-ended, connect the CLKM pin to ground (in other words,

short CLKM directly to AVSS, as shown in 图 86). In this case, the auto-detect feature shuts down the internal

differential clock buffer and the device automatically goes into a single-ended clock input. Connect the single-

ended clock source directly (without decoupling) to the CLKP pin. When using a single-ended clock input, TI

recommends using low-jitter, square signals (LVCMOS levels, 1.8-V amplitude) to drive the ADC (refer to

technical brief, Clocking High-Speed Data Converters, SLYT075 for further details).

CMOS Clock Input

CLKP

CLKM

图 86. Single-Ended Clock Driving Circuit

For differential clocks (such as differential sine-wave, LVPECL, LVDS, and so forth), enable the clock amplifier

with the connection scheme shown in 图 87. This same scheme applies when the clock is single-ended but the

clock amplitude is either small or its edges are not sharp. In this case, connect the input clock signal with a

capacitor to CLKP (as in 图 87) and connect CLKM to ground through a capacitor (that is, ac-coupled to AVSS).

If a transformer is used with the secondary coil floating (for instance, to convert from single-ended to differential),

the outputs of the transformer can be connected directly to the clock inputs without requiring the 10-nF series

capacitors.

10 nF

CLKP

Differential Sine Wave

or PECL or LVDS Clock Signal

CLKM

10 nF

图 87. Differential Clock Driving Circuit

To ensure that the aperture delay and jitter are the same for all channels, the device uses a clock tree network to

generate individual sampling clocks for each channel. For all channels, the clock is closley matched from the

source point to the sampling circuit of each of the eight internal devices.

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The jitter cleaners CDCM7005, CDCE72010, or LMK048X series are suitable to generate the system clock and

enable high performance. 图 88 shows a clock distribution network.

FPGA Clock,

Noisy Clock

n × (5 MHz to 100 MHz)

TI Jitter Cleaner

LMK048X

CDCE72010

CDCM7005

5-MHz to 100-MHz

ADC CLK

CDCLVP1208

The CDCE72010 has 10

LMK0030X

outputs

LMK01000

8 Synchronized

DUT System CLKs

图 88. System Clock Distribution Network

8.3.12 Analog Input and Driving Circuit

8.3.12.1 Signal Input

The analog input to the device can be either ac- or dc-coupled. In ac-coupling, the input common-mode required

for device functionality can be forced with the common-mode voltage, generated internally by the device (that

comes at the VCM pin) through a resistor, as shown in 图 89. The resistor and capacitor values used for coupling

determines the high-pass filter corner of the input circuit; thus, these values are chosen with the frequency of

interest in mind.

Device

INPx

10 nF

25 Q

50 Q

6.8 pF

Input 2-V_PP

Differential

VCM

1 mF

25 Q

50 Q

Internal

Reference

INMx

CM Buffer

VCM

10 nF

图 89. AC Coupling

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When dc-coupling the analog input, the output common-mode voltage of the driver can be set using the VCM

output pin as a reference, as shown in 图 90.

Device

50 Q

INPx

INMx

OUTP

OUTM

6.8 pF

2-V_PPDifferential VCM = 0.8 V

CM

Internal

Reference

CM Buffer

VCM

图 90. DC Coupling

Each input interfaces to two sets of identical sampling circuits. The electrical model of the load that each of the

sampling networks present is illustrated in 图 91. For the sake of simplification, the MOS switches can be

considered as ideal switches.

As illustrated in 图 57, 图 58, and 图 59, the scheme of connecting each input sampling circuit to the input pins

differs across the three input modes. The time-dependent loading of the input pins therefore is different across

the three input modes, and can be determined by referring to 图 57, 图 58, 图 59, and 图 91.

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SZ

S

R_ON

170 Ω

R_ON

100 Ω

C_PAR3

2 pF

Sampling

Switch

S

L_PKG

3.5 nH

Sampling

Capacitor

21 Ω

INP

R_ON

14 Ω

C_BOND

0.5 pF

C_PAR3

1 pF

C_SAMP

4.6 pF

R_ESR

200 Ω

14 Ω

S

R_ON

40 Ω

CPAR1

1.5 pF

14 Ω

L_PKG

3.5 nH

C_SAMP

4.6 pF

R_ON

14 Ω

21 Ω

INM

C_BOND

0.5 pF

C_PAR3

1 pF

Sampling

Capacitor

S

Sampling

Switch

R_ESR

200 Ω

R_ON

170 Ω

R_ON

100 Ω

C_PAR3

2 pF

S

SZ

图 91. Analog Input Sampling Network

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8.4 Device Functional Modes

8.4.1 Input Modes

The device supports three input modes: a 16-input, a 32-input, and an 8-input mode using the SEL_CH[2:0]

register controls. See 表 49 for a listing of register bits that select the 8-, 16-, and 32-input modes. Using the

same set of 16 ADCs, the three modes can be used to convert 16, 32, or 8 input channels, respectively. The

performance of the ADC itself depends on the conversion clock frequency, which has a different relationship to

the system clock and sampling rates in each of the three modes. Although the ADCs are common to all three

modes, the manner in which the ADCs are used determines unique performance characteristics in each mode.

For example, the 8-input mode can have significant interleaving spurs. Additionally, in the 8-input mode, the

conversion phases of two adjacent ADCs are offset by one system clock period. The switching operation in one

ADC can affect the performance of the adjacent ADC especially at higher input frequencies. For this reason, only

10-bit ADC resolution is supported in the 8-input mode. The restrictions when operating in the different input

modes are listed in 表 30.

表 30. Modes Supported in 8-, 16-, and 32-Input Modes

ANALOG INPUT MODE

ADC RESOLUTIONS SUPPORTED (Bits)

LVDS DATA RATE MODES SUPPORTED

16

32

8

10, 12, 14

10

1X, 2X

1X

1X, 2X

8.4.2 ADC Resolution Modes

The ADC resolution can be programmed between 10, 12,and 14 with the ADC_RES register control. The

maximum conversion rate of each ADC is determined by the programmed ADC resolution. The restrictions when

operating with the different ADC resolutions are listed in 表 31.

表 31. Modes Supported in the 10-, 12-, and 14-Bit ADC Resolution Modes

ADC RESOLUTION (Bits)

ANALOG INPUT MODES SUPPORTED

MAXIMUM CONVERSION CLOCK (f_C, MHz)

10

12

14

16, 8, 32

16, 32

100

80

16, 32

65

8.4.3 LVDS and JESD Interface Modes

By default, the LVDS interface is enabled. To disable the LVDS interface, set DIS_LVDS to 1.

To enable the JESD204B interface, set EN_JESD to 1. The JESD204B interface is supported only in 16-input

and 32-input modes.

8.4.4 LVDS Serialization and Output Data Rate Modes

The serialization factor of the LVDS interface can be set to 10, 12, 14, or 16 using the SER_DATA_RATE

register. Additionally, the density of output data payload can be set to 1X or 2X mode by using the

LVDS_RATE_2X register bits. The maximum data rate (in bits per sec) of the LVDS interface is limited.

Depending on the input mode, serialization factor, and output data rate mode, the LVDS interface speed

restriction may impose additional constraints on the maximum sampling rate achievable.

8.4.5 Power Modes

The ADS52J90 can be configured via SPI or pin settings to a global power-down mode and via pin settings to a

fast power-down (standby mode). During these two modes (global and standby power-down), different internal

functions stay powered up, resulting in different power consumption and wake-up times.

In standby mode, all LVDS data lanes are powered down. The bit clock and frame clock lanes remain enabled to

save time to sync again on the receiver side. However, in global power-down mode all lanes are powered down

and thus this mode requires more time to wake-up because the bit clock and frame clock lanes must sync again

with the receiver device.

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The device consists of the following key blocks:

•

Band-gap circuit,

Serial interface,

Reference voltage and current generator,

ADC analog block that performs a sampling and conversion,

ADC digital block that includes all the digital post processing blocks (such as the offset, gain, digital HPF, and

so forth),

•

LVDS data serializer and buffer that converts the ADC parallel data to a serial stream,

LVDS frame and clock serializer and buffer, and

PLL (phase-locked loop) that generates a high-frequency clock for both the ADC and serializer.

Of all these blocks, only the band-gap and serial interface block are not powered down using the power-down

pins or bits. 表 32 lists which blocks in the ADC are powered down using different pins and bits.

表 32. Power-Down Modes Description for the ADC

LVDS FRAME

LVDS DATA

SERIALIZER,

BUFFER

REFERENCE

+ ADC CLOCK

BUFFER

TYPE (Pin or

Register)

ADC

ANALOG

ADC

DIGITAL

AND CLOCK

SERIALIZER,

BUFFER

NAME

PLL

CHANNEL

PDN_GBL

GLOBAL_PDN

PDN_FAST

Yes⁽¹⁾

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

All⁽²⁾

All

Register

All

DIS_LVDS

Register

Yes

No

All

PDN_ANA_ADCx

PDN_DIG_ADCx

PDN_LVDSx

Yes

No

Individual

Yes

No

Yes

No

(1) Yes = powered down. No = active.

(2) All = all channels are powered down. Individual = only a single channel is powered down, depending upon the corresponding bit.

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8.4.6 LVDS Test Pattern Mode

The ADC data coming out of the LVDS outputs can be replaced by different kinds of test patterns. Note that the

test patterns replace the data streaming out of the ADCs (more specifically, the DIGRES1 signal). Therefore, in

16-, 8-, and 32-channel input modes, the pattern that occurs on a per-channel basis can be different for some

test patterns. The different test patterns are described in 表 33.

表 33. Description of LVDS Test Patterns

PROGRAMMING THE MODE

TEST

THE PATTERN IS SELECTIVELY

PATTERN

MODE

THE SAME PATTERN MUST BE COMMON

TO ALL DATA LINES

REQUIRED ON ONE OR MORE DATA

LINE

TEST PATTERNS

REPLACE⁽¹⁾

Set PAT_SELECT_IND = 1. To output the

pattern on the DOUTx line, select

PAT_LVDSx[2:0]

Zeros in all bits

(00000000000000) of

DIGRESx

All 0s

Set the mode using PAT_MODES[2:0]

Set PAT_SELECT_IND = 1. To output the

pattern on the DOUTx line, select

PAT_LVDSx[2:0]

Ones in all bits

(11111111111111) of

DIGRESx

All 1s

Deskew

Sync

Set PAT_SELECT_IND = 1. To output the

pattern on the DOUTx line, select

PAT_LVDSx[2:0]

DIGRESx word is replaced

by alternate 0s and 1s

(01010101010101)

Set PAT_SELECT_IND = 1. To output the

pattern on the DOUTx line, select

PAT_LVDSx[2:0]

DIGRESx word is replaced

by half 1s and half 0s

(11111110000000)

The word written in the

CUSTOM_PATTERN control

(taken from the MSB side)

replaces DIGRESx.

Set the mode using PAT_MODES[2:0]. Set

the desired custom pattern using the

CUSTOM_PATTERN register control.

Set PAT_SELECT_IND = 1. To output the

pattern on the DOUTx line, select

PAT_LVDSx[2:0]

(For instance,

Custom

CUSTOM_PATTERN =

1100101101011100 and

DIGRESx =

11001011010111 when the

serialization factor is 14.)

The ADCOUTx word (not the

DIGRESx word) is replaced

by a word that increments by

1 LSB every conversion clock

starting at negative full-scale,

increments until positive full-

scale, and wraps back to

negative full-scale.

Set PAT_SELECT_IND = 1. To output the

pattern on the DOUTx line, select

PAT_LVDSx[2:0]

Ramp

Set the mode using PAT_MODES[2:0]

The DIGRESx word

alternates between two

words that are all 1s and all

0s. At each setting of the

toggle pattern, the start word

can either be all 0s or all 1s.

(Alternate between

Set PAT_SELECT_IND = 1. To output the

pattern on the DOUTx line, select

PAT_LVDSx[2:0]

Toggle

Set the mode using PAT_MODES[2:0]

11111111111111 and

00000000000000.)

Set PAT_SELECT_IND = 1. Select either

custom or ramp pattern with

PAT_LVDSx[2:0]. Enable PRBS mode on

Set SEL_PRBS_PAT_GBL = 1. Select either

custom or ramp pattern with

PAT_MODES[2:0]. Enable PRBS mode

using PRBS_EN. Select the desired PRBS

mode using PRBS_MODE. Reset the PRBS

generator with PRBS_SYNC.

A 16-bit pattern is generated

by a 23-bit (or 9-bit) PRBS

PRBS

DOUTx with the PAT_PRBS_LVDSx control. pattern generator (taken from

Select the desired PRBS mode using

PRBS_MODE. Reset the PRBS generator

with PRBS_SYNC.

the MSB side) and replaces

the DIGRESx word.

(1) Shown for a serialization factor of 14.

All patterns listed in 表 33 (except the PRBS pattern) can also be forced on the frame clock output line by using

PAT_MODES_FCLK[2:0]. To force a PRBS pattern on the frame clock, use the SEL_PRBS_PAT_FCLK,

PRBS_EN, and PAT_MODES_FCLK register controls.

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The ramp, toggle, and pseudo-random sequence (PRBS) test patterns can be reset or synchronized by providing

a synchronization pulse on the TX_TRIG pin or by setting and resetting a specific register bit.

These test patterns also function as transport layer test patterns for the JESD204B interface.

8.5 Programming

8.5.1 Serial Peripheral Interface (SPI) Operation

This section discusses the read and write operations of the SPI interface.

8.5.1.1 Serial Register Write Description

Several different modes can be programmed with the serial peripheral interface (SPI). This interface is formed by

the SEN (serial interface enable), SCLK (serial interface clock), SDIN (serial interface data), and RESET pins.

The SCLK, SDIN, and RESET pins have a 20-kΩ pulldown resistor to ground. SEN has a 20-kΩ pullup resistor to

supply. Serially shifting bits into the device is enabled when SEN is low. SDIN serial data are latched at every

SCLK rising edge when SEN is active (low). SDIN serial data are loaded into the register at every 24th SCLK

rising edge when SEN is low. If the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data

can be loaded in multiples of 24-bit words within a single active SEN pulse (an internal counter counts the

number of 24 clock groups after the SEN falling edge). Data is divided into two main portions: the register

address (8 bits) and data (16 bits). 图 92 shows the timing diagram for serial interface write operation.

SEN

t_{SEN_SU}

Data Latched On

SCLK Rising Edge

t_{SCLK_H}

t_{SEN_HO}

t_SCLK

SCLK

t_{SCLK_L}

t_DH

t_DSU

A7

A6

A5

A4

A3

A2

A1

A0 D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SDIN

RESET

图 92. Serial Interface Timing

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Programming (接下页)

8.5.1.2 Register Readout

The device includes an option where the contents of the internal registers can be read back. This readback can

be useful as a diagnostic test to verify the serial interface communication between the external controller and

AFE. First, the REG_READ_EN bit must be set to 1. Then, initiate a serial interface cycle specifying the address

of the register (A[7:0]) whose content must be read. The data bits are don’t care. The device outputs the contents

(D[15:0]) of the selected register on the SDOUT pin. For lower-speed SCLKs, SDOUT can be latched on the

SCLK rising edge. For higher-speed SCLKs, latching SDOUT at the next SCLK falling edge is preferable. The

read operation timing diagram is shown in 图 93. In readout mode, the REG_READ_EN bit can be accessed with

SDIN, SCLK, and SEN. To enable serial register writes, set the REG_READ_EN bit back to 0.

SEN

SCLK

t_{OUT_DV}

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SDOUT

SDIN

A7

A6

A5

A4

A3

A2

A1

A0

X

图 93. Serial Interface Register, Read Operation

The device SDOUT buffer is 3-stated and is only enabled when the REG_READ_EN bit is enabled. SDOUT pins

from multiple devices can therefore be tied together without any pullup resistors. The SN74AUP1T04 level shifter

can be used to convert 1.8-V logic to 2.5-V or 3.3-V logic, if necessary.

9 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The ADS52J90 supports multiple levels of channel integration (8, 16, and 32) with high sampling rates

achievable for each channel. The ADS52J90 also has options to synchronize the clocking and LVDS interface of

multiple devices. These features, combined with the excellent ADC performance and low power, make the

ADS52J90 an excellent choice for applications involving high channel counts. Such applications include

ultrasound imaging systems, sonar imaging equipment, and radar.

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9.2 Typical Application

An illustration of a system with a channel count of 64 is shown in 图 94. In 图 94, the output interface is selected

as the LVDS interface. Four ADS52J90 devices, each operating in 16-input mode, are connected to a single

FPGA that aggregates the data from all ADCs for further data processing and storage.

SPI

Control

INP1

Channel 1

INM1

TX_TRIG

INP3

Channel 2

INM3

LVDS

Lines

LVDS

Receiver

ADS52J90,

Device1

INP31

INM31

Channel 16

FPGA

Data

Processing

and

Storage

INP1

INM1

INP3

INM3

LVDS

Lines

ADS52J90,

Device4

LVDS

Receiver

INP31

INM31

Channel 64

Clock

Generator

CLKP,

CLKM

图 94. Application Schematic: 64-Channel Medical Ultrasound Receiver Using the ADS52J90

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Typical Application (接下页)

9.2.1 Design Requirements

Typical requirements of a medical ultrasound receiver system are listed in 表 34.

表 34. Requirements of a Typical Medical Ultrasound Receiver

DESIGN PARAMETER

EXAMPLE VALUES

5 MHz-15 MHz

2 MHz

Signal center frequency

Signal bandwidth

Maximum input signal amplitude

Transducer noise level

Total harmonic distortion

100 mV_PP

1 nV/√Hz

40 dBc

The ultrasound system typically has an LNA and a time-dependent gain block at the front-end before the ADC. In

an ultrasound receiver, the signal level keeps reducing as a function of time and the role of the front-end blocks

is to gain up the signal level without adding too much additional noise. The gain of the front-end can be adjusted

so that the input signal to the ADC always remains within its full-scale range.

A sampling rate of approximately 40 MHz to 50 MHz is usually sufficient for such an application. Thus the

ADS52J90 can be operated in 16-input mode. Furthermore, the resolution can be set to 14 bits to maximize the

SNR of the device. A higher sampling rate ADC results in a lower noise density in the signal band of interest. For

example, an ADC with a 2-V_PPinput operating at 50 MSPS with an SNR of 73 dBFS has a noise level of

approximately 35 nV/√Hz referred to the input of the ADC. If the front-end has a gain of 40 dB, the ADC noise

referred to the input of the front-end is then 0.35 nV/√Hz, which in this case is lower than the transducer noise

level.

9.2.2 Detailed Design Procedure

The design considerations when designing with the 16-, 32-, and 8-input modes are described in the following

sections.

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9.2.2.1 Designing with the 16-Input Mode

Mapping of the analog inputs to the LVDS outputs is shown in 表 35 for a case corresponding to a 16-input mode

and a 1X data rate.

表 35. Mapping of Analog Inputs to LVDS Outputs (16-Input Mode, 1X Data Rate)

CONNECTION TO

ANALOG INPUT

PINS

ANALOG INPUT

SIGNAL

SAMPLING

INSTANT

SERIAL_OUT

(Over Two Frames)

LVDS OUTPUTS ON

DOUT PINS

ADC WORD

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

ADCOUT1o

ADCOUT1e

ADCOUT2o

ADCOUT2e

ADCOUT3o

ADCOUT3e

ADCOUT4o

ADCOUT4e

ADCOUT5o

ADCOUT5e

ADCOUT6o

ADCOUT6e

ADCOUT7o

ADCOUT7e

ADCOUT8o

ADCOUT8e

ADCOUT9o

ADCOUT9e

ADCOUT10o

ADCOUT10e

ADCOUT11o

ADCOUT11e

ADCOUT12o

ADCOUT12e

ADCOUT13o

ADCOUT13e

ADCOUT14o

ADCOUT14e

ADCOUT15o

ADCOUT15e

ADCOUT16o

ADCOUT16e

Frame 1: ADCOUT1o

Frame 2: ADCOUT1e

AIN1

AIN2

IN1

IN3

DOUT1

DOUT2

DOUT3

DOUT4

DOUT5

DOUT6

DOUT7

DOUT8

DOUT9

DOUT10

DOUT11

DOUT12

DOUT13

DOUT14

DOUT15

DOUT16

Frame 1: ADCOUT2o

Frame 2: ADCOUT2e

Frame 1: ADCOUT3o

Frame 2: ADCOUT3e

AIN3

IN5

Frame 1: ADCOUT4o

Frame 2: ADCOUT4e

AIN4

IN7

Frame 1: ADCOUT5o

Frame 2: ADCOUT5e

AIN5

IN9

Frame 1: ADCOUT6o

Frame 2: ADCOUT6e

AIN6

IN11

IN13

IN15

IN17

IN19

IN21

IN23

IN25

IN27

IN29

IN31

Frame 1: ADCOUT7o

Frame 2: ADCOUT7e

AIN7

Frame 1: ADCOUT8o

Frame 2: ADCOUT8e

AIN8

Frame 1: ADCOUT9o

Frame 2: ADCOUT9e

AIN9

Frame 1: ADCOUT10o

Frame 2: ADCOUT10e

AIN10

AIN11

AIN12

AIN13

AIN14

AIN15

AIN16

Frame 1: ADCOUT11o

Frame 2: ADCOUT11e

Frame 1: ADCOUT12o

Frame 2: ADCOUT12e

Frame 1: ADCOUT13o

Frame 2: ADCOUT13e

Frame 1: ADCOUT14o

Frame 2: ADCOUT14e

Frame 1: ADCOUT15o

Frame 2: ADCOUT15e

Frame 1: ADCOUT16o

Frame 2: ADCOUT16e

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Mapping of the analog inputs to the LVDS outputs is shown in 表 36 for a case corresponding to a 16-input mode

and a 2X data rate.

表 36. Mapping of Analog Inputs to LVDS Outputs (16-Input Mode, 2X Data Rate)

CONNECTION TO

ANALOG INPUT

PINS

ANALOG INPUT

SIGNAL

SAMPLING

INSTANT

SERIAL_OUT

(Over Two Frames)

LVDS OUTPUTS ON

DOUT PINS

ADC WORD

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

ADCOUT1o

ADCOUT1e

ADCOUT2o

ADCOUT2e

ADCOUT3o

ADCOUT3e

ADCOUT4o

ADCOUT4e

ADCOUT5o

ADCOUT5e

ADCOUT6o

ADCOUT6e

ADCOUT7o

ADCOUT7e

ADCOUT8o

ADCOUT8e

ADCOUT9o

ADCOUT9e

ADCOUT10o

ADCOUT10e

ADCOUT11o

ADCOUT11e

ADCOUT12o

ADCOUT12e

ADCOUT13o

ADCOUT13e

ADCOUT14o

ADCOUT14e

ADCOUT15o

ADCOUT15e

ADCOUT16o

ADCOUT16e

Frame 1: ADCOUT1o,

ADCOUT2o

Frame 2: ADCOUT1e,

ADCOUT2e

AIN1

AIN2

IN1

IN3

DOUT1

DOUT2

DOUT3

DOUT4

DOUT9

DOUT10

DOUT11

DOUT12

Frame 1: ADCOUT3o,

ADCOUT4o

Frame 2: ADCOUT3e,

ADCOUT4e

AIN3

IN5

AIN4

IN7

Frame 1: ADCOUT5o,

ADCOUT6o

Frame 2: ADCOUT5e,

ADCOUT6e

AIN5

IN9

AIN6

IN11

IN13

IN15

IN17

IN19

IN21

IN23

IN25

IN27

IN29

IN31

Frame 1: ADCOUT7o,

ADCOUT8o

Frame 2: ADCOUT7e,

ADCOUT8e

AIN7

AIN8

Frame 1: ADCOUT9o,

ADCOUT10o

Frame 2: ADCOUT9e,

ADCOUT10e

AIN9

AIN10

AIN11

AIN12

AIN13

AIN14

AIN15

AIN16

Frame 1: ADCOUT11o,

ADCOUT12o

Frame 2: ADCOUT11e,

ADCOUT12e

Frame 1: ADCOUT13o,

ADCOUT14

Frame 2: ADCOUT13e,

ADCOUT14e

Frame 1: ADCOUT15o,

ADCOUT16o

Frame 2: ADCOUT15e,

ADCOUT16e

表 35 and 表 36 illustrate that the ADCs convert the odd numbered input when operating in the 16-input mode.

Each ADC can be set to convert the following even numbered input using the register control IN_CH_ADCx. The

performance of the ADC may slightly degrade when IN_CH_ADCx is set to 1.

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In 16-input mode, there is a one-to-one mapping between the inputs and the ADCs. The register map relative to

the ADCs can therefore be mapped to the 16 channels, as shown in 表 37.

表 37. Reinterpretation of the Register Map in 16-Input Mode

MAPPING TO

CHANNELS IN 16-INPUT

MODE

REGISTER MAP

NOTATION

EXAMPLE

GAIN_ADCxo,

GAIN_ADCxe

GAIN_CHANNEL1 = GAIN_ADC1o (same for GAIN_ADC1e)

(Set odd and even gains of the same ADC to the same setting)

GAIN_CHANNELx

OFFSET_ADCxo,

OFFSET_ADCxe

OFFSET_CHANNEL1 = OFFSET_ADC1o (same for OFFSET_ADC1e

(Set odd and even offsets of the same ADC to the same setting)

OFFSET_CHANNELx

PDN_DIG_CHANNELx

PDN_DIG_ADCx

PDN_ANA_ADCx

PDN_DIG_CHANNEL1 = PDN_DIG_ADC1

PDN_ANA_CHANNELx PDN_ANA_CHANNEL1 = PDN_ANA_ADC1

DIG_HPF_EN_CHANNEL1-4 = DIG_HPF_EN_ADC1-4

Mapped to 4 channels

DIG_HPF_EN_ADCx

HPF_CORNER_ADCx

Common setting for 4 ADCs maps to common setting for 4 channels

HPF_CORNER_CHANNEL1-4 = HPF_CORNER_ADC1-4

Mapped to 4 channels

Common setting for 4 ADCs maps to common setting for 4 channels

9.2.2.2 Designing with the 32-Input Mode

Mapping of the analog inputs to the LVDS outputs is shown in 表 38 for a case corresponding to a 32-input mode

and a 1X data rate.

表 38. Mapping of Analog Inputs to LVDS Outputs (32-Input Mode, 1X Data Rate)

CONNECTION TO

ANALOG INPUT

PINS

ANALOG INPUT

SIGNAL

SAMPLING

INSTANT

SERIAL_OUT

(Over One Frame)

LVDS OUTPUTS ON

DOUT PINS

ADC WORD

AIN1

AIN2

IN1

IN2

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

t₁

t₂

ADCOUT1o

ADCOUT1e

ADCOUT2o

ADCOUT2e

ADCOUT3o

ADCOUT3e

ADCOUT4o

ADCOUT4e

ADCOUT5o

ADCOUT5e

ADCOUT6o

ADCOUT6e

ADCOUT7o

ADCOUT7e

ADCOUT8o

ADCOUT8e

ADCOUT9o

ADCOUT9e

ADCOUT10o

ADCOUT10e

ADCOUT11o

ADCOUT11e

ADCOUT12o

ADCOUT12e

ADCOUT13o

ADCOUT13e

ADCOUT1o,

ADCOUT1e

DOUT1

DOUT2

DOUT3

DOUT4

DOUT5

DOUT6

DOUT7

DOUT8

DOUT9

DOUT10

DOUT11

DOUT12

DOUT13

AIN3

IN3

ADCOUT2o,

ADCOUT2e

AIN4

IN4

AIN5

IN5

ADCOUT3o,

ADCOUT3e

AIN6

IN6

AIN7

IN7

ADCOUT4o,

ADCOUT4e

AIN8

IN8

AIN9

IN9

ADCOUT5o,

ADCOUT5e

AIN10

AIN11

AIN12

AIN13

AIN14

AIN15

AIN16

AIN17

AIN18

AIN19

AIN20

AIN21

AIN22

AIN23

AIN24

AIN25

AIN26

IN10

IN11

IN12

IN13

IN14

IN15

IN16

IN17

IN18

IN19

IN20

IN21

IN22

IN23

IN24

IN25

IN26

ADCOUT6o,

ADCOUT6e

ADCOUT7o,

ADCOUT7e

ADCOUT8o,

ADCOUT8e

ADCOUT9o,

ADCOUT9e

ADCOUT10o,

ADCOUT10e

ADCOUT11o,

ADCOUT11e

ADCOUT12o,

ADCOUT12e

ADCOUT13o,

ADCOUT13e

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表 38. Mapping of Analog Inputs to LVDS Outputs (32-Input Mode, 1X Data Rate) (接下页)

CONNECTION TO

ANALOG INPUT

PINS

ANALOG INPUT

SIGNAL

SAMPLING

INSTANT

SERIAL_OUT

(Over One Frame)

LVDS OUTPUTS ON

DOUT PINS

ADC WORD

AIN27

AIN28

AIN29

AIN30

AIN31

AIN32

IN27

IN28

IN29

IN30

IN31

IN32

t₁

t₂

t₁

t₂

t₁

t₂

ADCOUT14o

ADCOUT14e

ADCOUT15o

ADCOUT15e

ADCOUT16o

ADCOUT16e

ADCOUT14o,

ADCOUT14e

DOUT14

DOUT15

DOUT16

ADCOUT15o,

ADCOUT15e

ADCOUT16o,

ADCOUT16e

Note that 2X data rate mode is not supported in 32-input mode. In 32-input mode, only one ADC is used to

convert two inputs.

The odd numbered inputs correspond to the odd sample from the ADC, and the even numbered inputs

correspond to the even sample from the ADC. The register map relative to the ADCs can therefore be mapped to

the 32 channels, as shown in 表 39.

表 39. Reinterpretation of Register Map in 32-Input Mode

MAPPING TO CHANNELS IN 16-INPUT

REGISTER MAP NOTATION

EXAMPLE

MODE

GAIN_ADCxo

GAIN_ADCxe

GAIN_CHANNEL (odd)

GAIN_CHANNEL (even)

OFFSET_CHANNEL (odd)

OFFSET_CHANNEL (even)

GAIN_CHANNEL1 = GAIN_ADC1o

GAIN_CHANNEL2 = GAIN_ADC1e

OFFSET_CHANNEL1 = OFFSET_ADC1o

OFFSET_CHANNEL2 = OFFSET_ADC1e

OFFSET_ADCXo

OFFSET_ADCxe

PDN_DIG_CHANNEL1 =

PDN_DIG_CHANNEL2 = PDN_DIG_ADC1

PDN_DIG_ADCx

PDN_ANA_ADCx

PDN_DIG_CHANNEL (odd and even)

PDN_ANA_CHANNEL (odd and even)

PDN_ANA_CHANNEL1 =

PDN_ANA_CHANNEL2 = PDN_ANA_ADC1

DIG_HPF_EN_CHANNEL1-8 =

DIG_HPF_EN_ADC1-4

Common setting for 4 ADCs mapped to

common setting for 8 channels

DIG_HPF_EN_ADCx

HPF_CORNER_ADCx

Mapped to 8 channels

HPF_CORNER_CHANNEL1-8 =

HPF_CORNER_ADC1-4

Common setting for 4 ADCs mapped to

common setting for 8 channels

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9.2.2.3 Designing with the 8-Input Mode

Mapping of the analog inputs to the LVDS outputs is shown in 表 40 for a case corresponding to an 8-input mode

and a 1X data rate.

表 40. Mapping of Analog Inputs to LVDS Outputs (8-Input Mode, 1X Data Rate)

CONNECTION TO

ANALOG INPUT

PINS

ANALOG INPUT

SIGNAL

SAMPLING

INSTANT

SERIAL_OUT

(Over Two Frames)

LVDS OUTPUTS ON

DOUT PINS

ADC WORD

t₁

t₂

t₃

t₄

t₁

t₂

t₃

t₄

t₁

t₂

t₃

t₄

t₁

t₂

t₃

t₄

t₁

t₂

t₃

t₄

t₁

t₂

t₃

t₄

t₁

t₂

t₃

t₄

t₁

t₂

t₃

t₄

ADCOUT1o

ADCOUT2o

ADCOUT1e

ADCOUT2e

ADCOUT3o

ADCOUT4o

ADCOUT3e

ADCOUT4e

ADCOUT5o

ADCOUT6o

ADCOUT5e

ADCOUT6e

ADCOUT7o

ADCOUT8o

ADCOUT7e

ADCOUT8e

ADCOUT9o

ADCOUT10o

ADCOUT9e

ADCOUT10e

ADCOUT11o

ADCOUT12o

ADCOUT11e

ADCOUT12e

ADCOUT13o

ADCOUT14o

ADCOUT13e

ADCOUT14e

ADCOUT15o

ADCOUT16o

ADCOUT15e

ADCOUT16e

Frame 1: ADCOUT1o

Frame 2: ADCOUT1e

DOUT1

DOUT2

DOUT3

DOUT4

DOUT5

DOUT6

DOUT7

DOUT8

DOUT9

DOUT10

DOUT11

DOUT12

DOUT13

DOUT14

DOUT15

DOUT16

IN1, IN3

(shorted externally)

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

Frame 1: ADCOUT2o

Frame 2: ADCOUT2e

Frame 1: ADCOUT3o

Frame 2: ADCOUT3e

IN5, IN7

(shorted externally)

Frame 1: ADCOUT4o

Frame 2: ADCOUT4e

Frame 1: ADCOUT5o

Frame 2: ADCOUT5e

IN9, IN11

(shorted externally)

Frame 1: ADCOUT6o

Frame 2: ADCOUT6e

Frame 1: ADCOUT7o

Frame 2: ADCOUT7e

IN13, IN15

(shorted externally)

Frame 1: ADCOUT8o

Frame 2: ADCOUT8e

Frame 1: ADCOUT9o

Frame 2: ADCOUT9e

IN17, IN19

(shorted externally)

Frame 1: ADCOUT10o

Frame 2: ADCOUT10e

Frame 1: ADCOUT11o

Frame 2: ADCOUT11e

IN21, IN23

(shorted externally)

Frame 1: ADCOUT12o

Frame 2: ADCOUT12e

Frame 1: ADCOUT13o

Frame 2: ADCOUT13e

IN25, IN27

(shorted externally)

Frame 1: ADCOUT14o

Frame 2: ADCOUT14e

Frame 1: ADCOUT15o

Frame 2: ADCOUT15e

IN29, IN31

(shorted externally)

Frame 1: ADCOUT16o

Frame 2: ADCOUT16e

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Mapping of the analog inputs to the LVDS outputs is shown in 表 41 for a case corresponding to an 8-input mode

and a 2X data rate.

表 41. Mapping of Analog Inputs to LVDS Outputs (8-Input Mode, 2X Data Rate)

CONNECTION TO

ANALOG INPUT

PINS

ANALOG INPUT

SIGNAL

SAMPLING

INSTANT

SERIAL_OUT

(Over Two Frames)

LVDS OUTPUTS ON

DOUT PINS

ADC WORD

t₁

t₂

t₃

t₄

t₁

t₂

t₃

t₄

t₁

t₂

t₃

t₄

t₁

t₂

t₃

t₄

t₁

t₂

t₃

t₄

t₁

t₂

t₃

t₄

t₁

t₂

t₃

t₄

t₁

t₂

t₃

t₄

ADCOUT1o

ADCOUT2o

ADCOUT1e

ADCOUT2e

ADCOUT3o

ADCOUT4o

ADCOUT3e

ADCOUT4e

ADCOUT5o

ADCOUT6o

ADCOUT5e

ADCOUT6e

ADCOUT7o

ADCOUT8o

ADCOUT7e

ADCOUT8e

ADCOUT9o

ADCOUT10o

ADCOUT9e

ADCOUT10e

ADCOUT11o

ADCOUT12o

ADCOUT11e

ADCOUT12e

ADCOUT13o

ADCOUT14o

ADCOUT13e

ADCOUT14e

ADCOUT15o

ADCOUT16o

ADCOUT15e

ADCOUT16e

Frame 1: ADCOUT1o,

ADCOUT2o

IN1, IN3

(shorted externally)

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

DOUT1

DOUT2

DOUT3

DOUT4

DOUT9

DOUT10

DOUT11

DOUT12

Frame 2: ADCOUT1e,

ADCOUT2e

Frame 1: ADCOUT3o,

ADCOUT4o

IN5, IN7

(shorted externally)

Frame 2: ADCOUT3e,

ADCOUT4e

Frame 1: ADCOUT5o,

ADCOUT6o

IN9, IN11

(shorted externally)

Frame 2: ADCOUT5e,

ADCOUT6e

Frame 1: ADCOUT7o,

ADCOUT8o

IN13, IN15

(shorted externally)

Frame 2: ADCOUT7e,

ADCOUT8e

Frame 1: ADCOUT9o,

ADCOUT10o

IN17, IN19

(shorted externally)

Frame 2: ADCOUT9e,

ADCOUT10e

Frame 1: ADCOUT11o,

ADCOUT12o

IN21, IN23

(shorted externally)

Frame 2: ADCOUT11e,

ADCOUT12e

Frame 1: ADCOUT13o,

ADCOUT14

IN25, IN27

(shorted externally)

Frame 2: ADCOUT13e,

ADCOUT14e

Frame 1: ADCOUT15o,

ADCOUT16o

IN29, IN31

(shorted externally)

Frame 2: ADCOUT15e,

ADCOUT16e

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In 8-input mode, two neighboring ADCs are used to convert a single input. The register map relative to the ADCs

can be mapped to the eight channels, as shown in 表 42.

表 42. Reinterpretation of Register Map in 8-input Mode

MAPPING TO

CHANNELS IN 16-INPUT

MODE

REGISTER MAP

NOTATION

EXAMPLE

GAIN_ADCxo,

GAIN_ADCxe of two

adjacent channels

GAIN_CHANNEL1 = GAIN_ADC1o (same for GAIN_ADC1e, GAIN_ADC2o, and

GAIN_ADC2e)

Set odd and even gains of two adjacent ADCs to the same setting.

GAIN_CHANNELx

OFFSET_CHANNEL1 = OFFSET_ADC1o (same for OFFSET_ADC1e,

OFFSET_ADC2o, and OFFSET_ADC2e)

Set odd and even offsets of two adjacent ADCs to the same setting.

OFFSET_ADCxo,

OFFSET_ADCxe

OFFSET_CHANNELx

PDN_DIG_ADCx of two

adjacent channels

PDN_DIG_CHANNEL1 = PDN_DIG_ADC1 (same for PDN_DIG_ADC2)

Set the power-down for two adjacent ADCs to the same setting.

PDN_DIG_CHANNELx

PDN_ANA_CHANNELx

Mapped to 2 channels

PDN_ANA_ADCx of two

adjacent channels

PDN_ANA_CHANNEL1 = PDN_ANA_ADC1 (same for PDN_ANA_ADC2)

Set the power-down for two adjacent ADCs to the same setting.

DIG_HPF_EN_CHANNEL1-2 = DIG_HPF_EN_ADC1-4

Common setting for 4 ADCs mapped to the common setting for 2 channels.

DIG_HPF_EN_ADCx

HPF_CORNER_ADCx

HPF_CORNER_CHANNEL1-2 = HPF_CORNER_ADC1-4

Common setting for 4 ADCs mapped to the common setting for 2 channels.

9.2.3 Application Curves

This section outlines the trends described in the Typical Characteristics section from an application perspective.

图 2 illustrates the FFT with a 5-MHz input signal for 32-input mode with the ADC resolution set to 10 bits. The

system clock provided is 100 MSPS and the input is sampled at an effective rate of 50 MSPS, which is the

maximum sampling rate for this mode of operation.

图 3 illustrates the FFT with a 5-MHz input signal for 16-input mode with the ADC resolution set to 10 bits. The

system clock provided is 100 MSPS and the input is sampled at an effective rate of 100 MSPS, which is the

maximum sampling rate for this mode of operation.

图 4 illustrates the FFT with a 5-MHz input signal for 8-input mode with the ADC resolution set to 10 bits. The

system clock provided is 200 MSPS and the input is sampled at an effective rate of 200 MSPS, which is the

maximum sampling rate for this mode of operation. The increase in sampling rate is achieved through two ADCs

converting the same input in an interleaved manner. The interleaving spurs are visible in the FFT. The

predominant spur is at the frequencies of (f_S/ 2 ± f_IN), which appear at 95 MHz. Additional spurs are at the

frequencies of (f_S/ 4 ± f_IN), which appear at 45 MHz and 55 MHz. The magnitude of the spurs is expected to rise

when the input frequency is increased. Also, the spur level is sensitive to the matching of the manner in which

the two sets of input pins are driven. A spur at f_S/4 is also seen. This arises from the offset mismatch between

the four sets of sampling circuits used to sample the same input.

图 5 illustrates the FFT with a 5-MHz input signal for 32-input mode with the ADC resolution set to 12 bits. The

system clock provided is 80 MSPS and the input is sampled at an effective rate of 40 MSPS, which is the

maximum sampling rate for this mode of operation.

图 6 illustrates the FFT with a 5-MHz input signal for 16-input mode with the ADC resolution set to 12 bits. The

system clock provided is 80 MSPS and the input is sampled at an effective rate of 80 MSPS, which is the

maximum sampling rate for this mode of operation.

图 7 illustrates the FFT with a 5-MHz input signal for 32-input mode with the ADC resolution set to 14 bits. The

system clock provided is 65 MSPS and the input is sampled at an effective rate of 32.5 MSPS, which is the

maximum sampling rate for this mode of operation.

图 8 illustrates the FFT with a 5-MHz input signal for 16-input mode with the ADC resolution set to 14 bits. The

system clock provided is 65 MSPS and the input is sampled at an effective rate of 65 MSPS, which is the

maximum sampling rate for this mode of operation. In addition to the harmonics, the spur at the frequency (f_S/ 2

± f_IN) also occurs at 27.5 MHz. This spur is caused by the interleaved sampling of the input signal by two

physically different sampling circuits of the same ADC.

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图 9 illustrates the signal-to-noise ratio (SNR) versus the frequency of the input signal for 32-input mode with the

ADC resolution set to 10 bits. SNR is expressed in the dBFS scale where the RMS noise at the ADC output is

referred to the full-scale differential voltage of 2 V. The system clock provided is 100 MSPS and the input is

sampled at an effective rate of 50 MSPS. SNR is computed by integrating the noise in all FFT bins after

excluding the first nine harmonics. SNR is dominated by the quantization noise of the 10-bit conversion.

图 10 illustrates SNR versus the frequency of the input signal for 16-input mode with the ADC resolution set to 10

bits. The system clock provided is 100 MSPS and the input is sampled at an effective rate of 100 MSPS. SNR is

computed by integrating the noise in all FFT bins after excluding the first nine harmonics and any interleaving

spurs. SNR is dominated by the quantization noise of the 10-bit conversion.

图 11 illustrates SNR versus the frequency of the input signal for 8-input mode with the ADC resolution set to 10

bits. The system clock provided is 200 MSPS and the input is sampled at an effective rate of 200 MSPS. SNR is

computed by integrating the noise in all FFT bins after excluding the first nine harmonics and any interleaving

spurs at (f_S/ 2 ± f_IN) and (f_S/ 4 ± f_IN) as well as additional spurs at f_S/ 2 and f_S/ 4. SNR is dominated by the

quantization noise of the 10-bit conversion.

图 12 illustrates SNR versus the frequency of the input signal for 32-input mode with the ADC resolution set to 12

bits. The system clock provided is 80 MSPS and the input is sampled at an effective rate of 40 MSPS.

图 13 illustrates SNR versus the frequency of the input signal for 16-input mode with the ADC resolution set to 12

bits. The system clock provided is 80 MSPS and the input is sampled at an effective rate of 80 MSPS.

图 14 illustrates SNR versus the frequency of the input signal for 32-input mode with the ADC resolution set to 14

bits. The system clock provided is 65 MSPS and the input is sampled at an effective rate of 32.5 MSPS. SNR at

high input frequencies degrades because of clock jitter.

图 15 illustrates SNR versus the frequency of the input signal for 16-input mode with the ADC resolution set to 14

bits. The system clock provided is 65 MSPS and the input is sampled at an effective rate of 65 MSPS.

图 16 illustrates the amplitude of the third-order harmonic distortion (HD3) of the input signal versus the

frequency of the input signal. The unit of dBc indicates that the HD3 amplitude is referred to the amplitude of the

input signal, which is set to –1 dBFS. 图 16 is taken for 32-input mode with the ADC resolution set to 10 bits. The

system clock provided is 100 MSPS and the input is sampled at an effective rate of 50 MSPS. The device follows

a similar trend across the other input modes and resolutions.

图 17 illustrates the amplitude of the second-order harmonic distortion (HD2) of the input signal versus the

frequency of the input signal. The unit of dBc indicates that the HD2 amplitude is referred to the amplitude of the

input signal, which is set to –1 dBFS. 图 17 is taken for 32-input mode with the ADC resolution set to 10 bits. The

system clock provided is 100 MSPS and the input is sampled at an effective rate of 50 MSPS. The device follows

a similar trend across the other input modes and resolutions.

图 18 illustrates the total harmonic distortion (THD) versus the frequency of the input signal. The THD parameter

includes the RMS amplitude of the first nine harmonics of the fundamental signal. The unit of dBc indicates that

THD is referred to the amplitude of the input signal, which is set to –1 dBFS. 图 18 is taken for 32-input mode

with the ADC resolution set to 10 bits. The system clock provided is 100 MSPS and the input is sampled at an

effective rate of 50 MSPS. The device follows a similar trend across the other input modes and resolutions.

图 19 illustrates the interleaving spur at (f_S/ 2 ± f_IN) versus the frequency of the input signal. 图 19 is taken for 8-

input mode with the ADC resolution set to 10 bits. The system clock is set to 200 MSPS and the input is sampled

at an effective rate of 200 MSPS. The interleaving spur at (f_S/ 2 ± f_IN) is referred to the fundamental amplitude,

which is at a level of –1 dBFS. The (f_S/ 2 ± f_IN) spur comes about because of the interleaved conversion of the

same input by two ADCs. As illustrated in 图 19, the interleaving spur gets much worse at higher input

frequencies. This degradation results from the fact that when the input frequency is increased, any mismatch in

the sampling bandwidths and sampling instants of the two interleaved ADCs leads to a larger phase error

between the interleaved conversions.

图 20 illustrates the interleaving spur at (f_S/ 2 ± f_IN) versus the frequency of the input signal. 图 20 is taken for

16-input mode with the ADC resolution set to 10 bits. The system clock is set to 100 MSPS and the input is

sampled at an effective rate of 100 MSPS. The (f_S/ 2 ± f_IN) spur comes about because of the interleaved

sampling of the input by the two sampling circuits of one ADC. Although not as bad as the (f_S/ 2 ± f_IN) spur for 8-

input mode, the interleaving spur could still be the dominant factor governing the SFDR at high input frequencies.

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图 21 illustrates the interleaving spur at (f_S/ 4 ± f_IN) versus the frequency of the input signal. 图 21 is taken for 8-

input mode with the ADC resolution set to 10 bits. The system clock is set to 200 MSPS and the input is sampled

at an effective rate of 200 MSPS. In 8-input mode, there are a total of four sampling circuits (two in each ADC)

that sample the same input in sequence. The (f_S/ 4 ± f_IN) spur comes about from mismatches between these

four sampling circuits.

图 22 illustrates SNR in dBFS as a function of the input amplitude, also expressed in dBFS. SNR excludes the

first nine harmonics and the interleaving spurs. 图 22 is taken for the 16-input mode with the ADC resolution set

to 14 bits. The system clock is set to 65 MSPS and the input is sampled at an effective rate of 65 MSPS. The

points in the left extreme of the curve provide an estimate of the idle channel SNR (SNR in the absence of an

input signal).

图 23 illustrates the spurious-free dynamic range (SFDR) as a function of the input amplitude. 图 23 is taken for

32-input mode with the ADC resolution set to 14 bits. In 32-input mode, there is no interleaved operation of any

sort and SFDR is a true measure of ADC conversion performance. As mentioned previously, SFDR may be

dominated by interleaving spurs (and significantly lower than 32-input mode) when operated in 16-input or 8-

input modes. SFDR is plotted in both dBc and dBFS: the former referring the amplitude of the worst-spur to the

fundamental amplitude and the latter to the full-scale voltage.

图 24 illustrates SNR as a function of the input common-mode voltage (average of INP and INM). 图 24 is taken

for 16-input mode with the ADC resolution set to 14 bits. The device is meant to be operated at an input

common-mode that is tightly controlled around the ideal value of 0.8 V. The driving circuit can generate its output

common-mode using the 0.8-V reference voltage provided at the VCM pin.

图 25 illustrates SNR as a function of the input clock amplitude (expressed in differential V_PP) when driven with a

differential sine-wave clock input. At small input amplitudes, the sine-wave clock has a low dV/dt slope at the

zero crossings. This low slope can cause increased jitter in the clocking and can lead to a reduction in the SNR

within the device. The effect is more pronounced when the input frequency is set to a higher value (as is

evidenced by the difference in behavior between the 5-MHz and 50-MHz inputs). The recommended manner to

drive the device is with an LVPECL clock.

图 26 illustrates SNR as a function of the duty cycle of a differential clock input. Ideally, the device is driven with

a 50% clock; see the Electrical Characteristics table for the acceptable variation around 50% duty cycle.

图 27 illustrates the channel-to-channel crosstalk as a function of the analog input frequency. An analog input of

a –1-dBFS amplitude is applied on one channel and the crosstalk spur (at the input frequency) is measured on

all channels. The worst of the crosstalk numbers (usually on the physically closest channel) is plotted.

图 28 illustrates the integral nonlinearity (INL) versus ADC code. The device is operated in 32-input mode at 14-

bit resolution with an effective sampling rate of 32.5 MSPS. 图 28 provides an accurate INL estimate of the ADC

inside the device because there is no interleaving of any kind in the 32-input mode operation.

图 29 illustrates the differential nonlinearity (DNL) versus ADC code. The device is operated in 32-input mode at

14-bit resolution with an effective sampling rate of 32.5 MSPS. The saturation of the DNL on the lower side to –1

indicates missing codes at the 14-bit level.

图 30 illustrates the power-supply rejection ratio (PSRR) as a function of the tone frequency applied on the

supply. A tone is applied on the supplies and the tone at the same frequency is measured at the device output.

The unit of dBc refers to the relation of the amplitude of the output tone to the amplitude of the supply tone that is

set to 100 mV_PPfor this measurement.

图 31 illustrates the power-supply modulation ratio (PSMR) as a function of the tone frequency applied on the

supply. A –1-dBFS input at 5 MHz is applied on the analog input. Simultaneously, a 100-mV_PPtone is applied on

the supply. The tone caused by the intermodulation between the supply tone and the input tone is measured at

the device output. PSMR refers to the intermodulation tone referred to in terms of dBc to the amplitude of the

input tone.

图 32 illustrates the common-mode rejection ratio (CMRR) as a function of the tone frequency applied as a

common-mode signal on the input pins. A 50-mV_PPcommon-mode signal is applied to INP and INM around the

ideal common-mode voltage of 0.8 V. The amplitude of the tone at the same frequency is measured at the

device output. CMRR refers to the amplitude of this output tone referred to in terms of dBc to the amplitude of

the common-mode input tone.

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图 33 illustrates the current of the AVDD_1P8 supply as a function of f_C, the conversion clock frequency. The

relation of the sampling rate to the conversion clock frequency is different between the 16-, 32-, and 8- input

modes and therefore the curve can be appropriately interpreted for each mode. The curve extends to a

conversion clock frequency of up to 100 MSPS, which is the maximum value for the 10-bit ADC resolution. For

the 12- and 14-bit ADC resolutions, sections of the same curve up to 80 MSPS and 65 MSPS (respectively) are

applicable.

图 34 illustrates the current of the DVDD_1P8 supply as a function of the conversion clock frequency. All 16

LVDS buffers are on during this measurement.

图 35 illustrates the current of the DVDD_1P2 supply as a function of the conversion clock frequency.

图 36 illustrates the total power consumption as a function of the conversion clock frequency. The power per

input channel can be calculated by dividing this total power by 8, 16, or 32 for the 8-, 16-, or 32-input modes.

图 37 illustrates the digital high-pass filter response for different settings of the HPF corner frequency.

图 38 illustrates the typical minimum and maximum SNR values taken across 100 devices operating in the 14-bit,

32-input mode at f_C= 65 MSPS (corresponding to f_SAMP= 32.5 MSPS). A trend can be observed across

channels and originates from the physical placement and routing of common signals (such as reference voltage

and power) to the channels. Depending on the way the channel data are combined, an averaging effect can

result when the system-level SNR is computed.

图 39 illustrates a plot of the low-frequency noise from the device with and without the chopper enabled. When

the chopper is enabled (using the CHOPPER_EN register control), the low-frequency noise generated inside the

device is shifted to approximately f_S/ 2. Chopper mode is useful when the signal frequency of interest is close to

dc.

图 48 illustrates a contour plot of SNR as a function of both the input frequency and sampling frequency for 32-

input mode operating with a 10-bit ADC resolution.

图 49 illustrates a contour plot of SNR as a function of both the input frequency and sampling frequency for 16-

input mode operating with a 10-bit ADC resolution.

图 50 illustrates a contour plot of SNR as a function of both the input frequency and sampling frequency for 8-

input mode operating with a 10-bit ADC resolution.

图 51 illustrates a contour plot of SNR as a function of both the input frequency and sampling frequency for 32-

input mode operating with a 12-bit ADC resolution.

图 52 illustrates a contour plot of SNR as a function of both the input frequency and sampling frequency for 16-

input mode operating with a 12-bit ADC resolution.

图 53 illustrates a contour plot of SNR as a function of both the input frequency and sampling frequency for 32-

input mode operating with a 14-bit ADC resolution.

图 54 illustrates a contour plot of SNR as a function of both the input frequency and sampling frequency for 16-

input mode operating with a 14-bit ADC resolution.

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9.3 Do's and Don'ts

Driving the inputs (analog or digital) beyond the power-supply rails. For device reliability, an input must not

go more than 300 mV below the ground pins or 300 mV above the supply pins. Exceeding these limits, even on

a transient basis, can cause faulty or erratic operation and can impair device reliability.

Driving the device signal input with an excessively high level signal. The device offers consistent and fast

overload recovery for an overload of upto 6 dBFS. For very large overload signals (> 6 dB of the linear input

signal range), TI recommends back-to-back Schottky clamping diodes at the input to limit the amplitude of the

input signal.

Using a clock source with excessive jitter, an excessively long input clock signal trace, or having other

signals coupled to the ADC clock signal trace. These situations cause the sampling instant vary, causing an

excessive output noise and a reduction in SNR performance. For a system with multiple devices, the clock tree

scheme must be used to apply an ADC clock. Excessive clock delay mismatch between devices can also lead to

latency mismatch and functional failure at the system level.

LVDS routing length mismatch. The routing length of all LVDS lines routing to the FPGA must be matched to

avoid any timing-related issues. For systems with multiple devices, the LVDS serialized data clock (DCLKP,

DCLKM) and the frame clock (FCLKP, FCLKM) of each individual device must be used to deserialize the

corresponding LDVS serialized data (DOUTP, DOUTM).

Failure to provide adequate heat removal. Use the appropriate thermal parameter listed in the Thermal

Information table and an ambient, board, or case temperature in order to calculate device junction temperature. A

suitable heat removal technique must be used to keep the device junction temperature below the maximum limit

of 105°C.

10 Power Supply Recommendations

The device requires three supplies in order to operate properly. These supplies are AVDD_1P8, DVDD_1P8, and

DVDD_1P2. All supplies must be driven with low-noise sources to be able to achieve the best performance from

the device. When determining the drive current needed to drive each of the supplies of the device, a margin of

50-100% over the typical current might be needed to account for the current consumption across different modes

of operation.

10.1 Power Sequencing and Initialization

图 95 shows the suggested power-up sequencing and reset timing for the device. Note that the DVDD_1P2

supply must rise before the AVDD_1P8 supply. If the AVDD_1P8 supply rises before the DVDD_1P2 supply, the

AVDD_1P8 supply current is several times higher than the normal operating current until the time the DVDD_1P2

supply reaches the 1.2-V level.

The device requires register described in 表 43 to be written as part of the initialization.

表 43. Initialization Register Details

INITIALIZATION REGISTER ADDRESS

16-BIT DATA WORD TO BE WRITTEN

0Ah

3000h

The initialization sequence is described below:

1. Power-up the supplies as indicated,

2. Apply a hardware reset pulse,

3. Write the initialization register listed in 表 43 through the SPI interface,

4. Write other device settings through the SPI interface, and

5. After a wait time, the device is ready for high accuracy operation.

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The power sequence and initialization is shown in 图 95.

t₁

DVDD_1P2

t₂

t₃

DVDD_1P8

AVDD_1P8

t₅

t₄

RESET

t₆

t₇

Device

Initialization

and Settings

SPI

Interface

CLK

t₈

TX_TRIG

Device

State

High-Accuracy Operation

图 95. Power Sequencing and Initialization

The timing parameters corresponding to 图 95 are shown in 表 44.

表 44. Timing for Power Sequencing and Initialization

MIN

10 µ

t₁

MAX

50 m

UNIT

t₁

t₂

t₃

Ramp-up time of DVDD_1P2

s

Ramp up time of AVDD_1P8 and DVDD_1P8

Time between DVDD_1P2 and AVDD_1P8 start of ramp up

Time between supplies stabilizing and application of a

hardware reset

t₄

t₅

t₆

10

100

ms

ns

Width of hardware reset

Time between hardware reset and SPI write for device

initialization and programming of device settings

Time between programming of device settings and

synchronization using TX_TRIG

t₇

t₈

100

10

ns

Time between TX_TRIG pulse and device ready for high-

accuracy operation

ADC clocks

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11 Layout

11.1 Power Supply, Grounding, and Bypassing

In a mixed-signal system design, the power-supply and grounding design plays a significant role. The device

distinguishes between two different grounds: AVSS (analog ground) and DVSS (digital ground). In most cases,

laying out the PCB to use a single ground plane is adequate. However, in high-frequency or high-performance

systems, care must be taken so that this ground plane is properly partitioned between various sections within the

system to minimize interactions between analog and digital circuitry. Alternatively, the digital supply set

consisting of the DVDD_1P8, DVDD_1P2, and DVSS pins can be placed on separate power and ground planes.

For this configuration, tie the AVSS and DVSS grounds together at the power connector in a star layout. In

addition, optical or digital isolators (such as the ISO7240) can completely separate the analog portion from the

digital portion. Consequently, such isolators prevent digital noise from contaminating the analog portion. 表 45

lists the related circuit blocks for each power supply.

表 45. Supply versus Circuit Blocks

POWER SUPPLY

GROUND

CIRCUIT BLOCKS

ADC analog, reference voltage and current generator, band-gap circuit,

and ADC clock buffer

AVDD_1P8

AVSS

DVDD_1P8

DVDD_1P2

DVSS

LVDS serializer and buffer, and PLL

ADC digital and serial interface

Reference all bypassing and power supplies for the device to their corresponding ground planes. Bypass all

supply pins with 0.1-μF ceramic chip capacitors (size 0603 or smaller). In order to minimize the lead and trace

inductance, the capacitors must be located as close to the supply pins as possible. Where double-sided

component mounting is allowed, these capacitors are best placed directly under the package. In addition, larger

bipolar decoupling capacitors (2.2 µF to 10 μF, effective at lower frequencies) can also be used on the main

supply pins. These components can be placed on the PCB in close proximity (< 0.5 inch or 12.7 mm) to the

device itself.

Bypass the VCM pin with at least a 1-μF capacitor; higher value capacitors can be used for better low-frequency

noise suppression. For best results, choose low-inductance ceramic chip capacitors (size 0402, > 1 μF) placed

as close as possible to the device pin.

11.2 Layout Guidelines

High-speed, mixed-signal devices are sensitive to various types of noise coupling. One primary source of noise is

the switching noise from the serializer and the output buffer and drivers. For the device, care must be taken to

ensure that the interaction between the analog and digital supplies within the device is kept to a minimal amount.

The extent of noise coupled and transmitted from the digital and analog sections depends on the effective

inductances of each of the supply and ground connections. Smaller effective inductances of the supply and

ground pins result in better noise suppression. For this reason, multiple pins are used to connect each supply

and ground sets. Low inductance properties must be maintained throughout the design of the PCB layout by use

of proper planes and layer thickness.

To avoid noise coupling through supply pins, TI recommends keeping sensitive input pins (such as the INM and

INP pins) away from the supply planes. For example, do not route the traces or vias connected to these pins

across the supply planes. That is, avoid the power planes under the INM and INP pins.

Some layout guidelines associated with the layout of the high speed interfaces are listed below:

•

The length of the positive and negative traces of a differential pair must be matched to within 2 mils of each

other.

•

Each differential pair length must be matched within 10 mils of other differential pairs.

When the ADC is used on the same printed circuit board (PCB) with a digital intensive component (such as

an FPGA or ASIC), separate digital and analog ground planes must be used. Do not overlap these separate

ground planes to minimize undesired coupling.

•

Connect decoupling capacitors directly to ground and place these capacitors close to the ADC power pins

and the power-supply pins to filter high-frequency current transients directly to the ground plane.

Ground and power planes must be wide enough to keep the impedance very low. In a multilayer PCB, one

layer must be dedicated to each ground and power plane.

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Layout Guidelines (接下页)

•

All high-speed traces must be routed straight with minimum bends. Where a bend is necessary, avoid making

very sharp right-angle bends in the trace.

•

In order to maintain proper LVDS timing, all LVDS traces must follow a controlled impedance design. In

addition, all LVDS trace lengths must be equal and symmetrical; TI recommends keeping trace length

variations less than 150 mil (0.150 inch or 3.81 mm).

•

When routing CML lines, the traces must be designed for a controlled impedance of 50 Ω. The routing of

different lines must be matched as much as possible to minimize the inter-lane skew. However, trace length

matching is less critical for the JESD interface as compared to the LVDS interface.

Additional details on the NFBGA PCB layout techniques can be found in the Texas Instruments application

report, MicroStar BGA Packaging Reference Guide (SSYZ015), available from www.ti.com.

11.3 Layout Example

图 96. Example Layout

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12.1.1 Description of Registers

12.1.1.1 Register 0h (address = 0h)

图 97. Register 0h

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

W-0h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

REG_READ_

EN

RESET

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

表 47. Register 0h Field Descriptions

Bit

15-2

1

Field

Type

W

Reset

0h

Description

0

Must write 0

REG_READ_EN

W

0h

Register readout enabled.

0 = Disabled

1 = Enabled; see the Serial Peripheral Interface (SPI) Operation

section for further details.

0

RESET

W

0h

0 = Disabled

1 = Enabled (this setting returns the device to a reset state; this

bit is self-clearing bit)

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12.1.1.2 Register 1h (address = 1h)

图 98. Register 1h

15

0

14

13

0

12

0

11

0

10

0

9

0

8

0

LVDS_RATE_

2X

R/W-0h

7

6

5

4

3

0

2

1

0

SEL_CH[2]

R/W-0h

EN_JESD

R/W-0h

DIS_LVDS

R/W-0h

SEL_CH[1]

R/W-0h

SEL_CH[0]

R/W-0h

GLOBAL_PDN

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 48. Register 1h Field Descriptions

Bit

15

14

Field

Type

R/W

Reset

0h

Description

0

Must write 0

LVDS_RATE_2X

0h

0 = 1X rate; normal operation (default)

1 = 2X rate. This setting combines the data of two LVDS pairs

into a single LVDS pair. This feature can be used when the ADC

clock rate is low.

13-8

7

0

R/W

0h

Must write 0

SEL_CH[2]

Input mode selection bit 3. 表 49 lists bit settings for the three

input modes.

6

5

4

EN_JESD

DIS_LVDS

SEL_CH[1]

R/W

0h

0 = JESD interface disabled

1 = JESD interface enabled; see 表 49

0 = LVDS interface is enabled (default)

1 = LVDS interface is disabled

Input mode selection bit 2. 表 49 lists bit settings for the three

input modes.

3

2

0

R/W

0h

Must write 0

SEL_CH[0]

Input mode selection bit 1. 表 49 lists bit settings for the three

input modes.

1

0

R/W

0h

Must write 0

GLOBAL_PDN

0 = The device operates in normal mode (default)

1 = ADC enters complete power-down mode

表 49. 8-, 16-, and 32-Input Mode Selection

INPUT MODE

8-channel input

16-channel input

32-channel input

SEL_CH[2]

SEL_CH[1]

SEL_CH[0]

1

0

1

0

1

0

表 50. Output Interface Supported in 8-, 16-, and 32-Input Mode

OUTPUT INTERFACE SUPPORTED?

INPUT MODE

LVDS

Yes

JESD204B

No

8-channel input

16-channel input

32-channel input

Yes

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12.1.1.3 Register 2h (address = 2h)

图 99. Register 2h

15

14

13

5

12

11

10

9

8

LOW_

LATENCY_EN

SEL_PRBS_

PAT_FCLK

PAT_MODES_FCLK[2:0]

R/W-0h

AVG_EN

PAT_MODES[2:0]

R/W-0h

4

R/W-0h

3

R/W-0h

2

7

6

1

0

PAT_

MODES[2:0]

SEL_PRBS_

PAT_GBL

OFFSET_CORR_DELAY_FROM_TX_TRIG[5:0]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 51. Register 2h Field Descriptions

Bit

Field

Type

Reset

Description

15-13

PAT_MODES_FCLK[2:0]

R/W

0h

These bits enable different test patterns on the frame clock line;

see 表 52 for bit descriptions and the LVDS Test Pattern Mode

section for further details.

12

11

LOW_LATENCY_EN

AVG_EN

R/W

0h

0 = Default latency with digital features supported

1 = Low-latency with digital features bypassed

0 = No digital averaging

1 = Enables digital averaging of two channels to improve signal-

to-noise ratio (SNR)

10

9-7

6

SEL_PRBS_PAT_FCLK

PAT_MODES[2:0]

R/W

0h

0 = Normal operation

1 = Enables the PRBS pattern to be generated on FCLK; see

the LVDS Test Pattern Mode section for further details.

These bits enable different test patterns on the LVDS data lines;

see 表 52 for bit descriptions and the LVDS Test Pattern Mode

section for further details.

SEL_PRBS_PAT_GBL

0 = Normal operation

1 = Enables the PRBS pattern to be generated on all the LVDS

data lines; see the LVDS Test Pattern Mode section for further

details.

5-0

OFFSET_CORR_DELAY_FROM_

TX_TRIG[5:0]

R/W

0h

This is a part of an 8-bit control that initiates offset correction

after the TX_TRIG input pulse (each step is equivalent to one

sample delay); the remaining two MSB bits are the

OFFSET_CORR_DELAY_FROM_TX_TRIG[7:6] bits (bits 10-9)

in register 3.

表 52. Pattern Mode Bit Description⁽¹⁾

PAT_MODES[2:0] or PAT_MODES_FCLK[2:0] or PAT_LVDSx[2:0]

DESCRIPTION

Normal operation

Sync (half frame 1, half frame 0)

Deskew

000

001

010

011

100

101

110

111

Custom⁽²⁾

All 1s

Toggle mode

All 0s

Ramp⁽²⁾

(1) For detailed description, see 表 33.

(2) Either the custom or ramp pattern setting is required for PRBS pattern selection.

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12.1.1.4 Register 3h (address = 3h)

图 100. Register 3h

15

14

13

5

12

11

0

10

9

8

OFFSET_CORR_DELAY_FROM

_TX_TRIG[7:6]

DIG_

OFFSET_EN

SER_DATA_RATE

DIG_GAIN_EN

R/W-0h

6

R/W-0h

4

R/W-0h

3

R/W-0h

0

7

0

2

0

1

0

JESD_WR_

SEL

0

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 53. Register 3h Field Descriptions

Bit

Field

Type

Reset

Description

15-13

SER_DATA_RATE

R/W

0h

These bits control the LVDS serialization rate.

000 = 12X

001 = 14X

100 = 16X

011 = 10X

101, 110, 111, 010 = Unused

12

DIG_GAIN_EN

0

R/W

0h

0 = Digital gain disabled

1 = Digital gain enabled

11

R/W

0h

Must write 0

10-9

OFFSET_CORR_DELAY_FROM_

TX_TRIG[7:6]

This is a part of an 8-bit control that initiates offset correction

after the TX_TRIG input pulse (each step is equivalent to one

sample delay); the remaining six LSB bits are the

OFFSET_CORR_DELAY_FROM_TX_TRIG[5:0] bits (bits 5-0) in

register 2.

8

DIG_OFFSET_EN

R/W

0h

0 = Digital offset subtraction disabled

1 = Digital offset subtraction enabled

7-6

5

0

R/W

0h

Must write 0

JESD_WR_SEL

0 = Setting when writing to all registers except for registers with

addresses in the decimal range of 115-119 and 134-138

1 = Setting when writing to registers with addresses in the

decimal range of 115-119 and 134-138

4-0

0

R/W

0h

Must write 0

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12.1.1.5 Register 4h (address = 4h)

图 101. Register 4h

15

14

13

12

11

10

9

1

8

OFFEST_

REMOVAL_

START_

OFFSET_

REMOVAL_

SELF

OFFSET_

REMOVAL_

START_ SEL

PAT_

SELECT_ IND

AUTO_OFFSET_REMOVAL_ACC_CYCLES[3:0]

R/W-0h

MANUAL

R/W-0h

7

R/W-0h

6

R/W-0h

5

R/W-0h

0

4

3

0

2

0

PRBS_

SYNC

PRBS_

MODE

PRBS_EN

R/W-0h

MSB_FIRST

R/W-0h

ADC_RES

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 54. Register 4h Field Descriptions

Bit

15

14

Field

Type

Reset

0h

Description

OFFSET_REMOVAL_SELF

R/W

Auto offset removal mode is enabled when this bit is set to 1

OFFSET_REMOVAL_START_SEL R/W

0h

0 = Auto offset correction initiated when the

OFFSET_REMOVAL_START_ MANUAL bit is set to 1.

1 = Auto offset correction initiated with a pulse on TX_TRIG pin.

13

12-9

8

OFFSET_REMOVAL_START_

MANUAL

R/W

0h

This bit initiates offset correction when

OFFSET_REMOVAL_START_SEL is set to 0.

AUTO_OFFSET_REMOVAL_ACC_ R/W

CYCLES

These bits define the number of samples required to generate

an offset in auto offset correction mode

PAT_SELECT_IND

R/W

0 = All LVDS output data lines have the same pattern, as

determined by the PAT_MODES[2:0] bits

1 = Different test patterns can be sent on different LVDS data

lines; see the LVDS Test Pattern Mode section for further details

7

6

5

PRBS_SYNC

PRBS_MODE

PRBS_EN

R/W

0h

0 = Normal operation

1 = PRBS generator is in a reset state

0 = 23-bit PRBS generator

1 = 9-bit PRBS generator

0 = PRBS sequence generation block disabled

1 = PRBS sequence generation block enabled; see the LVDS

Test Pattern Mode section for further details

4

MSB_FIRST

R/W

0h

0 = The LSB is transmitted first on serialized output data

1 = The MSB is transmitted first on serialized output data

3-2

1-0

0

R/W

0h

Must write 0

ADC_RES

These bits control the ADC resolution.

00 = 12-bit resolution

01 = 14-bit resolution

11 = 10-bit resolution

10 = Unused

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12.1.1.6 Register 5h (address = 5h)

图 102. Register 5h

15

7

14

6

13

5

12

11

10

2

9

1

8

0

CUSTOM_PATTERN

R/W-0h

4

3

CUSTOM_PATTERN

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 55. Register 5h Field Descriptions

Bit

Field

Type

Reset

Description

15-0

CUSTOM_PATTERN

R/W

0h

If the pattern mode is programmed to a custom pattern mode,

then the custom pattern value can be provided by programming

these bits; see the LVDS Test Pattern Mode section for further

details.

12.1.1.7 Register 7h (address = 7h)

图 103. Register 7h

15

14

13

12

11

10

0

9

0

8

0

AUTO_OFFSET_REMOVAL_VAL_RD_CH_SEL

R/W-0h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

CHOPPER_EN

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 56. Register 7h Field Descriptions

Bit

Field

Type

Reset

Description

15-11

AUTO_OFFSET_REMOVAL_VAL_ R/W

RD_CH_SEL

0h

Write the channel number to read the offset value in auto offset

correction mode for a corresponding channel number (read the

offset value in AUTO_OFFSET_REMOVAL_VAL_RD.⁽¹⁾

10-1

0

R/W

0h

Must write 0

CHOPPER_EN

The chopper can be used to move low-frequency, 1 / f noise to

f_S/ 2 frequency.

0 = Chopper disabled

1 = Chopper enabled

(1) In 32-channel input mode, the value written in this register corresponds to the channel number (minus 1). When operating in 8- and 16-

input modes, the value can be mapped to the odd or even data streams of the 16 ADCs. For example, a value of 0 corresponds to the

odd data stream of ADC1. Likewise, a value of 1 corresponds to the even data stream of ADC1, and so on respectively.

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12.1.1.8 Register 8h (address = 8h)

图 104. Register 8h

15

0

14

0

13

5

12

11

10

9

1

8

0

AUTO_OFFSET_REMOVAL_VAL_RD[13:0]

R/W-0h

7

6

4

3

2

AUTO_OFFSET_REMOVAL_VAL_RD[13:0]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 57. Register 8h Field Descriptions

Bit

Field

Type

Reset

0h

Description

15-14

13-0

0

R/W

Must write 0

AUTO_OFFSET_REMOVAL_VAL_ R/W

RD

0h

Read the offset value applied in auto offset correction mode for

a specific channel number as defined in

AUTO_OFFSET_REMOVAL_VAL_RD_CH_SEL

12.1.1.9 Register Ah (address = Ah)

图 105. Register Ah

15

0

14

0

13

12

11

0

10

0

9

0

8

0

INIT2

INIT1

R/W-0h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 58. Register Ah Field Descriptions

Bit

15-14

13

Field

0

Type

R/W

Reset

0h

Description

Must write 0

INIT2

INIT1

0

0h

Write 1 as part of the initialization after power-up⁽¹⁾

Must write 0

12

0h

11-0

0h

(1) See 表 43.

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12.1.1.10 Register Bh (address = Bh)

图 106. Register Bh

15

0

14

0

13

0

12

0

11

10

0

9

0

8

0

EN_DITHER

R/W-0h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 59. Register Bh Field Descriptions

Bit

15-12

11

Field

Type

R/W

Reset

0h

Description

0

Must write 0

EN_DITHER

0h

Dither can be used to reduce the power in higher-order

harmonics.

0 = Dither disabled

1 = Dither enabled

Note: Enabling the dither converts higher-order harmonics power

into noise. Thus, enabling this mode reduce the power in higher-

order harmonics but degrades SNR.

10-0

0

R/W

0h

Must write 0

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12.1.1.11 Register Dh (address = Dh)

图 107. Register Dh

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC1o

R/W-0h

OFFSET_ADC1o

R/W-0h

5

4

3

2

1

0

OFFSET_ADC1o

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 60. Register Dh Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC1o

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the odd sample of ADC1 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC1o

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the odd sample of ADC1 can

be obtained with this 10-bit register. The offset value is in twos

complement format and its LSB corresponds to a 14-bit LSB.

12.1.1.12 Register Eh (address = Eh)

图 108. Register Eh

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC1e

R/W-0h

OFFSET_ADC1e

R/W-0h

5

4

3

2

1

0

OFFSET_ADC1e

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 61. Register Eh Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC1e

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the even sample of ADC1 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC1e

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the even sample of ADC1 can

be obtained with this 10-bit register. The offset value is in twos

complement format and its LSB corresponds to a 14-bit LSB.

105

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12.1.1.13 Register Fh (address = Fh)

图 109. Register Fh

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC2o

R/W-0h

OFFSET_ADC2o

R/W-0h

5

4

3

2

1

0

OFFSET_ADC2o

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 62. Register Fh Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC2o

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the odd sample of ADC2 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC2o

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the odd sample of ADC2 can

be obtained with this 10-bit register. The offset value is in twos

complement format and its LSB corresponds to a 14-bit LSB.

12.1.1.14 Register 10h (address = 10h)

图 110. Register 10h

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC2e

R/W-0h

OFFSET_ADC2e

R/W-0h

5

4

3

2

1

0

OFFSET_ADC2e

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 63. Register 10h Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC2e

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the even sample of ADC2 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC2e

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the even sample of ADC2 can

be obtained with this 10-bit register. The offset value is in twos

complement format and its LSB corresponds to a 14-bit LSB.

106

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12.1.1.15 Register 11h (address = 11h)

图 111. Register 11h

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC3o

R/W-0h

OFFSET_ADC3o

R/W-0h

5

4

3

2

1

0

OFFSET_ADC3o

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 64. Register 11h Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC3o

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the odd sample of ADC3 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC3o

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the odd sample of ADC3 can

be obtained with this 10-bit register. The offset value is in twos

complement format and its LSB corresponds to a 14-bit LSB.

12.1.1.16 Register 12h (address = 12h)

图 112. Register 12h

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC3e

R/W-0h

OFFSET_ADC3e

R/W-0h

5

4

3

2

1

0

OFFSET_ADC3e

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 65. Register 12h Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC3e

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the even sample of ADC3 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC3e

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the even sample of ADC3 can

be obtained with this 10-bit register. The offset value is in twos

complement format and its LSB corresponds to a 14-bit LSB.

107

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12.1.1.17 Register 13h (address = 13h)

图 113. Register 13h

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC4o

R/W-0h

OFFSET_ADC4o

R/W-0h

5

4

3

2

1

0

OFFSET_ADC4o

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 66. Register 13h Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC4o

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the odd sample of ADC4 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC4o

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the odd sample of ADC4 can

be obtained with this 10-bit register. The offset value is in twos

complement format and its LSB corresponds to a 14-bit LSB.

12.1.1.18 Register 14h (address = 14h)

图 114. Register 14h

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC4e

R/W-0h

OFFSET_ADC4e

R/W-0h

5

4

3

2

1

0

OFFSET_ADC4e

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 67. Register 14h Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC4e

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the even sample of ADC4 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC4e

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the even sample of ADC4 can

be obtained with this 10-bit register. The offset value is in twos

complement format and its LSB corresponds to a 14-bit LSB.

108

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12.1.1.19 Register 15h (address = 15h)

图 115. Register 15h

15

14

13

12

11

10

9

1

8

PAT_PRBS_

LVDS1

PAT_PRBS_

LVDS2

PAT_PRBS_

LVDS3

PAT_PRBS_

LVDS4

PAT_

LVDS2

PAT_LVDS1

R/W-0h

7

R/W-0h

6

R/W-0h

5

R/W-0h

4

R/W-0h

2

R/W-0h

0

3

HPF_ROUND_

EN_CH1-8

DIG_HPF_EN_

ADC1-4

PAT_LVDS2

R/W-0h

HPF_CORNER_ADC1-4

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 68. Register 15h Field Descriptions

Bit

Field

Type

Reset

Description

15

PAT_PRBS_LVDS1

R/W

0h

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the PRBS pattern on LVDS output 1 can be enabled with this bit;

see the LVDS Test Pattern Mode section for further details.

14

13

PAT_PRBS_LVDS2

PAT_PRBS_LVDS3

PAT_PRBS_LVDS4

PAT_LVDS1

R/W

0h

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the PRBS pattern on LVDS output 2 can be enabled with this bit;

see the LVDS Test Pattern Mode section for further details.

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the PRBS pattern on LVDS output 3 can be enabled with this bit;

see the LVDS Test Pattern Mode section for further details.

12

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the PRBS pattern on LVDS output 4 can be enabled with this bit;

see the LVDS Test Pattern Mode section for further details.

11-9

8-6

5

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the pattern on LVDS output 1 can be programmed with these

bits; see 表 33 for bit descriptions.

PAT_LVDS2

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the pattern on LVDS output 2 can be programmed with these

bits; see 表 33 for bit descriptions.

HPF_ROUND_EN_CH1-8

0 = Rounding in the ADC HPF is disabled for channel 1 to 8.

HPF output is truncated to be mapped to the ADC resolution

bits.

1 = HPF output of channel 1 to 8 is mapped to the ADC

resolution bits by the round-off operation.

4-1

0

HPF_CORNER_ADC1-4

DIG_HPF_EN_ADC1-4

R/W

0h

When the DIG_HPF_EN_ADC1-4 bit is set to 1, the digital HPF

characteristic for the corresponding ADCs can be programmed

by setting the value of k with these bits.

The value of k can be from 2 to 10 (0010b to 1010b); see the

Digital HPF section for further details.

0 = Digital HPF disabled for ADCs 1 to 4 (default)

1 = Enables digital HPF for ADCs 1 to 4

109

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12.1.1.20 Register 17h (address = 17h)

图 116. Register 17h

15

0

14

0

13

0

12

0

11

10

9

8

IN_16CH_

ADC1

IN_16CH_

ADC2

IN_16CH_

ADC3

IN_16CH_

ADC4

R/W-0h

7

R/W-0h

5

R/W-0h

4

R/W-0h

2

R/W-0h

6

3

1

0

PAT_LVDS3

R/W-0h

PAT_LVDS4

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 69. Register 17h Field Descriptions

Bit

15-12

11

Field

Type

R/W

Reset

0h

Description

0

Must write 0

IN_16CH_ADC1

0h

Selects the input pair sampled by ADC1 in 16-input mode.

0 = ADC1 samples the signal on INP1, INM1

1 = ADC1 samples the signal on INP2, INM2

10

9

IN_16CH_ADC2

IN_16CH_ADC3

IN_16CH_ADC4

PAT_LVDS3

PAT_LVDS4

0

R/W

0h

Selects the input pair sampled by ADC2 in 16-input mode.

0 = ADC2 samples the signal on INP3, INM3

1 = ADC2 samples the signal on INP4, INM4

Selects the input pair sampled by ADC3 in 16-input mode.

0 = ADC3 samples the signal on INP5, INM5

1 = ADC3 samples the signal on INP6, INM6

8

Selects the input pair sampled by ADC4 in 16-input mode.

0 = ADC4 samples the signal on INP7, INM7

1 = ADC4 samples the signal on INP8, INM8

7-5

4-2

1-0

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the pattern on LVDS output 3 can be programmed with these

bits; see 表 33 for bit descriptions.

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the pattern on LVDS output 4 can be programmed with these

bits; see 表 33 for bit descriptions.

Must write 0

110

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12.1.1.21 Register 18h (address = 18h)

图 117. Register 18h

15

14

13

12

11

10

9

8

PDN_DIG_

ADC4

PDN_DIG_

ADC3

PDN_DIG_

ADC2

PDN_DIG_

ADC1

PDN_LVDS4

PDN_LVDS3

PDN_LVDS2

PDN_LVDS1

R/W-0h

7

R/W-0h

6

R/W-0h

5

R/W-0h

4

R/W-0h

3

R/W-0h

2

R/W-0h

1

R/W-0h

0

PDN_ANA_

ADC4

PDN_ANA_

ADC3

PDN_ANA_

ADC2

PDN_ANA_

ADC1

INVERT_

LVDS4

INVERT_

LVDS3

INVERT_

LVDS2

INVERT_

LVDS1

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 70. Register 18h Field Descriptions

Bit

Field

Type

Reset

Description

15

PDN_DIG_ADC4

R/W

0h

0 = Normal operation (default)

1 = Powers down the digital block for ADC4

14

13

12

11

10

9

PDN_DIG_ADC3

PDN_DIG_ADC2

PDN_DIG_ADC1

PDN_LVDS4

R/W

0h

0 = Normal operation (default)

1 = Powers down the digital block for ADC3

0 = Normal operation (default)

1 = Powers down the digital block for ADC2

0 = Normal operation (default)

1 = Powers down the digital block for ADC1

0 = Normal operation (default)

1 = Powers down LVDS output line 4

PDN_LVDS3

0 = Normal operation (default)

1 = Powers down LVDS output line 3

PDN_LVDS2

0 = Normal operation (default)

1 = Powers down LVDS output line 2

8

PDN_LVDS1

0 = Normal operation (default)

1 = Powers down LVDS output line 1

7

PDN_ANA_ADC4

PDN_ANA_ADC3

PDN_ANA_ADC2

PDN_ANA_ADC1

INVERT_LVDS4

0 = Normal operation (default)

1 = Powers down the analog block for ADC4

6

0 = Normal operation (default)

1 = Powers down the analog block for ADC3

5

0 = Normal operation (default)

1 = Powers down the analog block for ADC2

4

0 = Normal operation (default)

1 = Powers down the analog block for ADC1

3

0 = Normal operation (default)

1 = Inverts ADC data sent on LVDS output line 4. Has no effect

on Test patterns.

2

1

0

INVERT_LVDS3

INVERT_LVDS2

INVERT_LVDS1

R/W

0h

0 = Normal operation (default)

1 = Inverts ADC data sent on LVDS output line 3. Has no effect

on Test patterns.

0 = Normal operation (default)

1 = Inverts ADC data sent on LVDS output line 2. Has no effect

on Test patterns.

0 = Normal operation (default)

1 = Inverts ADC data sent on LVDS output line 1. Has no effect

on Test patterns.

111

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12.1.1.22 Register 19h (address = 19h)

图 118. Register 19h

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC5o

R/W-0h

OFFSET_ADC5o

R/W-0h

5

4

3

2

1

0

OFFSET_ADC5o

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 71. Register 19h Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC5o

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the odd sample of ADC5 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC5o

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the odd sample of ADC5 can

be obtained with this 10-bit register. The offset value is in twos

complement format and its LSB corresponds to a 14-bit LSB.

12.1.1.23 Register 1Ah (address = 1Ah)

图 119. Register 1Ah

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC5e

R/W-0h

OFFSET_ADC5e

R/W-0h

5

4

3

2

1

0

OFFSET_ADC5e

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 72. Register 1Ah Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC5e

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the even sample of ADC5 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC5e

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the even sample of ADC5 can

be obtained with this 10-bit register. The offset value is in twos

complement format and its LSB corresponds to a 14-bit LSB.

112

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12.1.1.24 Register 1Bh (address = 1Bh)

图 120. Register 1Bh

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC6o

R/W-0h

OFFSET_ADC6o

R/W-0h

5

4

3

2

1

0

OFFSET_ADC6o

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 73. Register 1Bh Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC6o

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the odd sample of ADC6 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC6o

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the odd sample of ADC6 can

be obtained with this 10-bit register. The offset value is in twos

complement format and its LSB corresponds to a 14-bit LSB.

12.1.1.25 Register 1Ch (address = 1Ch)

图 121. Register 1Ch

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC6e

R/W-0h

OFFSET_ADC6e

R/W-0h

5

4

3

2

1

0

OFFSET_ADC6e

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 74. Register 1Ch Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC6e

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the even sample of ADC6 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC6e

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the even sample of ADC6 can

be obtained with this 10-bit register. The offset value is in twos

complement format and its LSB corresponds to a 14-bit LSB.

113

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12.1.1.26 Register 1Dh (address = 1Dh)

图 122. Register 1Dh

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC7o

R/W-0h

OFFSET_ADC7o

R/W-0h

5

4

3

2

1

0

OFFSET_ADC7o

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 75. Register 1Dh Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC7o

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the odd sample of ADC7 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC7o

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the odd sample of ADC7 can

be obtained with this 10-bit register. The offset value is in twos

complement format and its LSB corresponds to a 14-bit LSB.

12.1.1.27 Register 1Eh (address = 1Eh)

图 123. Register 1Eh

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC7e

R/W-0h

OFFSET_ADC7e

R/W-0h

5

4

3

2

1

0

OFFSET_ADC7e

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 76. Register 1Eh Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC7e

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the even sample of ADC7 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC7e

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the even sample of ADC7 can

be obtained with this 10-bit register. The offset value is in twos

complement format and its LSB corresponds to a 14-bit LSB.

114

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12.1.1.28 Register 1Fh (address = 1Fh)

图 124. Register 1Fh

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC8o

R/W-0h

OFFSET_ADC8o

R/W-0h

5

4

3

2

1

0

OFFSET_ADC8o

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 77. Register 1Fh Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC8o

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the odd sample of ADC8 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC8o

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the odd sample of ADC8 can

be obtained with this 10-bit register. The offset value is in twos

complement format and its LSB corresponds to a 14-bit LSB.

12.1.1.29 Register 20h (address = 20h)

图 125. Register 20h

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC8e

R/W-0h

OFFSET_ADC8e

R/W-0h

5

4

3

2

1

0

OFFSET_ADC8e

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 78. Register 20h Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC8e

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the even sample of ADC8 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC8e

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the even sample of ADC8 can

be obtained with this 10-bit register. The offset value is in twos

complement format and its LSB corresponds to a 14-bit LSB.

115

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12.1.1.30 Register 21h (offset = 21h)

图 126. Register 21h

15

14

13

12

11

10

9

1

8

PAT_PRBS_

LVDS5

PAT_PRBS_

LVDS6

PAT_PRBS_

LVDS7

PAT_PRBS_

LVDS8

PAT_

LVDS6

PAT_LVDS5

R/W-0h

7

R/W-0h

6

R/W-0h

5

R/W-0h

4

R/W-0h

2

R/W-0h

0

3

DIG_HPF_EN_

ADC5-8

PAT_LVDS6

R/W-0h

0

HPF_CORNER_ADC5-8

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 79. Register 21h Field Descriptions

Bit

Field

Type

Reset

Description

15

PAT_PRBS_LVDS5

R/W

0h

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the PRBS pattern on LVDS output 5 can be enabled with this bit;

see the LVDS Test Pattern Mode section for further details.

14

13

PAT_PRBS_LVDS6

PAT_PRBS_LVDS7

PAT_PRBS_LVDS8

PAT_LVDS5

R/W

0h

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the PRBS pattern on LVDS output 6 can be enabled with this bit;

see the LVDS Test Pattern Mode section for further details.

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the PRBS pattern on LVDS output 7 can be enabled with this bit;

see the LVDS Test Pattern Mode section for further details.

12

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the PRBS pattern on LVDS output 8 can be enabled with this bit;

see the LVDS Test Pattern Mode section for further details.

11-9

8-6

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the pattern on LVDS output 5 can be programmed with these

bits; see 表 33 for bit descriptions.

PAT_LVDS6

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the pattern on LVDS output 6 can be programmed with these

bits; see 表 33 for bit descriptions.

5

0

R/W

0h

Must write 0

4-1

HPF_CORNER_ADC5-8

When the DIG_HPF_EN_ADC5-8 bit is set to 1, the digital HPF

characteristic for the corresponding ADCs can be programmed

by setting the value of k with these bits.

The value of k can be from 2 to 10 (0010b to 1010b); see the

Digital HPF section for further details.

0

DIG_HPF_EN_ADC5-8

R/W

0h

0 = Digital HPF disabled for ADCs 5 to 8 (default)

1 = Enables digital HPF for ADCs 5 to 8

116

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12.1.1.31 Register 23h (register = 23h)

图 127. Register 23h

15

0

14

0

13

0

12

0

11

10

9

8

IN_16CH_

ADC5

IN_16CH_

ADC6

IN_16CH_

ADC7

IN_16CH_

ADC8

R/W-0h

7

R/W-0h

5

R/W-0h

4

R/W-0h

2

R/W-0h

6

3

1

0

PAT_LVDS7

R/W-0h

PAT_LVDS8

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 80. Register 23h Field Descriptions

Bit

15-12

11

Field

Type

R/W

Reset

0h

Description

0

Must write 0

IN_16CH_ADC5

0h

Selects the input pair sampled by ADC5 in 16-input mode.

0 = ADC5 samples the signal on INP9, INM9

1 = ADC5 samples the signal on INP10, INM10

10

9

IN_16CH_ADC6

IN_16CH_ADC7

IN_16CH_ADC8

PAT_LVDS7

PAT_LVDS8

0

R/W

0h

Selects the input pair sampled by ADC6 in 16-input mode.

0 = ADC6 samples the signal on INP11, INM11

1 = ADC6 samples the signal on INP12, INM12

Selects the input pair sampled by ADC7 in 16-input mode.

0 = ADC7 samples the signal on INP13, INM13

1 = ADC7 samples the signal on INP14, INM14

8

Selects the input pair sampled by ADC8 in 16-input mode.

0 = ADC8 samples the signal on INP15, INM15

1 = ADC8 samples the signal on INP16, INM16

7-5

4-2

1-0

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the pattern on LVDS output 7 can be programmed with these

bits; see 表 33 for bit descriptions.

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the pattern on LVDS output 8 can be programmed with these

bits; see 表 33 for bit descriptions.

Must write 0

117

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12.1.1.32 Register 24h (address = 24h)

图 128. Register 24h

15

14

13

12

11

10

9

8

PDN_DIG_

ADC8

PDN_DIG_

ADC7

PDN_DIG_

ADC6

PDN_DIG_

ADC5

PDN_LVDS8

PDN_LVDS7

PDN_LVDS6

PDN_LVDS5

R/W-0h

7

R/W-0h

6

R/W-0h

5

R/W-0h

4

R/W-0h

3

R/W-0h

2

R/W-0h

1

R/W-0h

0

PDN_ANA_

ADC8

PDN_ANA_

ADC7

PDN_ANA_

ADC6

PDN_ANA_

ADC5

INVERT_

LVDS8

INVERT_

LVDS7

INVERT_

LVDS6

INVERT_

LVDS5

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 81. Register 24h Field Descriptions

Bit

Field

Type

Reset

Description

15

PDN_DIG_ADC8

R/W

0h

0 = Normal operation (default)

1 = Powers down the digital block for ADC8

14

13

12

11

10

9

PDN_DIG_ADC7

PDN_DIG_ADC6

PDN_DIG_ADC5

PDN_LVDS8

R/W

0h

0 = Normal operation (default)

1 = Powers down the digital block for ADC7

0 = Normal operation (default)

1 = Powers down the digital block for ADC6

0 = Normal operation (default)

1 = Powers down the digital block for ADC5

0 = Normal operation (default)

1 = Powers down LVDS output line 8

PDN_LVDS7

0 = Normal operation (default)

1 = Powers down LVDS output line 7

PDN_LVDS6

0 = Normal operation (default)

1 = Powers down LVDS output line 6

8

PDN_LVDS5

0 = Normal operation (default)

1 = Powers down LVDS output line 5

7

PDN_ANA_ADC8

PDN_ANA_ADC7

PDN_ANA_ADC6

PDN_ANA_ADC5

INVERT_LVDS8

0 = Normal operation (default)

1 = Powers down the analog block for ADC8

6

0 = Normal operation (default)

1 = Powers down the analog block for ADC7

5

0 = Normal operation (default)

1 = Powers down the analog block for ADC6

4

0 = Normal operation (default)

1 = Powers down the analog block for ADC5

3

0 = Normal operation (default)

1 = Inverts ADC data sent on LVDS output line 8. Has no effect

on Test patterns.

2

1

0

INVERT_LVDS7

INVERT_LVDS6

INVERT_LVDS5

R/W

0h

0 = Normal operation (default)

1 = Inverts ADC data sent on LVDS output line 7. Has no effect

on Test patterns.

0 = Normal operation (default)

1 = Inverts ADC data sent on LVDS output line 6. Has no effect

on Test patterns.

0 = Normal operation (default)

1 = Inverts ADC data sent on LVDS output line 5. Has no effect

on Test patterns.

118

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12.1.1.33 Register 25h (address = 25h)

图 129. Register 25h

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC9o

R/W-0h

OFFSET_ADC9o

R/W-0h

5

4

3

2

1

0

OFFSET_ADC9o

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 82. Register 25h Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC9o

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the odd sample of ADC9 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC9o

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the odd sample of ADC9 can

be obtained with this 10-bit register. The offset value is in twos

complement format and its LSB corresponds to a 14-bit LSB.

12.1.1.34 Register 26h (address = 26h)

图 130. Register 26h

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC9e

R/W-0h

OFFSET_ADC9e

R/W-0h

5

4

3

2

1

0

OFFSET_ADC9e

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 83. Register 26h Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC9e

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the even sample of ADC9 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC9e

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the even sample of ADC9 can

be obtained with this 10-bit register. The offset value is in twos

complement format and its LSB corresponds to a 14-bit LSB.

119

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12.1.1.35 Register 27h (address = 27h)

图 131. Register 27h

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC10o

R/W-0h

OFFSET_ADC10o

R/W-0h

5

4

3

2

1

0

OFFSET_ADC10o

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 84. Register 27h Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC10o

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the odd sample of ADC10 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC10o

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the odd sample of ADC10 can

be obtained with this 10-bit register. The offset value is in twos

complement format and its LSB corresponds to a 14-bit LSB.

12.1.1.36 Register 28h (address = 28h)

图 132. Register 28h

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC10e

R/W-0h

OFFSET_ADC10e

R/W-0h

5

4

3

2

1

0

OFFSET_ADC10e

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 85. Register 28h Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC10e

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the even sample of ADC10 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC10e

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the even sample of ADC10

can be obtained with this 10-bit register. The offset value is in

twos complement format and its LSB corresponds to a 14-bit

LSB.

120

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12.1.1.37 Register 29h (address = 29h)

图 133. Register 29h

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC11o

R/W-0h

OFFSET_ADC11o

R/W-0h

5

4

3

2

1

0

OFFSET_ADC11o

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 86. Register 29h Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC11o

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the odd sample of ADC11 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC11o

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the odd sample of ADC11 can

be obtained with this 10-bit register. The offset value is in twos

complement format and its LSB corresponds to a 14-bit LSB.

12.1.1.38 Register 2Ah (address = 2Ah)

图 134. Register 2Ah

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC11e

R/W-0h

OFFSET_ADC11e

R/W-0h

5

4

3

2

1

0

OFFSET_ADC11e

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 87. Register 2Ah Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC11e

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the even sample of ADC11 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC11e

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the even sample of ADC11

can be obtained with this 10-bit register. The offset value is in

twos complement format and its LSB corresponds to a 14-bit

LSB.

121

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12.1.1.39 Register 2Bh (address = 2Bh)

图 135. Register 2Bh

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC12o

R/W-0h

OFFSET_ADC12o

R/W-0h

5

4

3

2

1

0

OFFSET_ADC12o

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 88. Register 2Bh Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC12o

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the odd sample of ADC12 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC12o

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the odd sample of ADC12 can

be obtained with this 10-bit register. The offset value is in twos

complement format and its LSB corresponds to a 14-bit LSB.

12.1.1.40 Register 2Ch (address = 2Ch)

图 136. Register 2Ch

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC12e

R/W-0h

OFFSET_ADC12e

R/W-0h

5

4

3

2

1

0

OFFSET_ADC12e

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 89. Register 2Ch Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC12e

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the even sample of ADC12 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC12e

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the even sample of ADC12

can be obtained with this 10-bit register. The offset value is in

twos complement format and its LSB corresponds to a 14-bit

LSB.

122

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12.1.1.41 Register 2Dh (address = 2Dh)

图 137. Register 2Dh

15

14

13

12

11

10

9

1

8

PAT_PRBS_

LVDS9

PAT_PRBS_

LVDS10

PAT_PRBS_

LVDS11

PAT_PRBS_

LVDS12

PAT_

LVDS10

PAT_LVDS9

R/W-0h

7

R/W-0h

6

R/W-0h

5

R/W-0h

4

R/W-0h

2

R/W-0h

0

3

HPF_ROUND_

EN_CH9-16

DIG_HPF_EN_

ADC9-12

PAT_LVDS10

R/W-0h

HPF_CORNER_ADC9-12

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 90. Register 2Dh Field Descriptions

Bit

Field

Type

Reset

Description

15

PAT_PRBS_LVDS9

R/W

0h

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the PRBS pattern on LVDS output 9 can be enabled with this bit;

see the LVDS Test Pattern Mode section for further details.

14

13

PAT_PRBS_LVDS10

PAT_PRBS_LVDS11

PAT_PRBS_LVDS12

PAT_LVDS9

R/W

0h

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the PRBS pattern on LVDS output 10 can be enabled with this

bit; see the LVDS Test Pattern Mode section for further details.

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the PRBS pattern on LVDS output 11 can be enabled with this

bit; see the LVDS Test Pattern Mode section for further details.

12

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the PRBS pattern on LVDS output 12 can be enabled with this

bit; see the LVDS Test Pattern Mode section for further details.

11-9

8-6

5

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the pattern on LVDS output 9 can be programmed with these

bits; see表 33 for bit descriptions.

PAT_LVDS10

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the pattern on LVDS output 10 can be programmed with these

bits; see表 33 for bit descriptions.

HPF_ROUND_EN_CH9-16

0 = Rounding in the ADC HPF is disabled for channels 9-16.

The HPF output is truncated to be mapped to the ADC

resolution bits.

1 = HPF output of channels 9-16 is mapped to the ADC

resolution bits by the round-off operation.

4-1

0

HPF_CORNER_ADC9-12

DIG_HPF_EN_ADC9-12

R/W

0h

When the DIG_HPF_EN_CH9-12 bit is set to 1, the digital HPF

characteristic for the corresponding ADCs can be programmed

by setting the value of k with these bits.

The value of k can be from 2 to 10 (0010b to 1010b); see the

Digital HPF section for further details.

0 = Digital HPF disabled for ADCs 9 to 12 (default)

1 = Enables digital HPF for ADCs 9 to 12

123

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12.1.1.42 Register 2Fh (address = 2Fh)

图 138. Register 2Fh

15

0

14

0

13

0

12

0

11

10

9

8

IN_16CH_

ADC9

IN_16CH_

ADC10

IN_16CH_

ADC11

IN_16CH_

ADC12

R/W-0h

7

R/W-0h

5

R/W-0h

4

R/W-0h

2

R/W-0h

6

3

1

0

PAT_LVDS11

R/W-0h

PAT_LVDS12

R/W-0h

LEGEND: R/W = Read/Write;-n = value after reset

表 91. Register 2Fh Field Descriptions

Bit

15-12

11

Field

Type

R/W

Reset

0h

Description

0

Must write 0

IN_16CH_ADC9

0h

Selects the input pair sampled by ADC9 in 16-input mode.

0 = ADC9 samples the signal on INP17, INM17

1 = ADC9 samples the signal on INP18, INM18

10

9

IN_16CH_ADC10

IN_16CH_ADC11

IN_16CH_ADC12

PAT_LVDS11[2:0]

PAT_LVDS12[2:0]

0

R/W

0h

Selects the input pair sampled by ADC10 in 16-input mode.

0 = ADC10 samples the signal on INP19, INM19

1 = ADC10 samples the signal on INP20, INM20

Selects the input pair sampled by ADC11 in 16-input mode.

0 = ADC11 samples the signal on INP21, INM21

1 = ADC11 samples the signal on INP22, INM22

8

Selects the input pair sampled by ADC12 in 16-input mode.

0 = ADC12 samples the signal on INP23, INM23

1 = ADC12 samples the signal on INP24, INM24

7-5

4-2

1-0

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the pattern on LVDS output 11 can be programmed with these

bits; see表 33 for bit descriptions.

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the pattern on LVDS output 12 can be programmed with these

bits; see表 33 for bit descriptions.

Must write 0

124

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12.1.1.43 Register 30h (address = 30h)

图 139. Register 30h

15

14

13

12

11

10

9

8

PDN_DIG_

ADC12

PDN_DIG_

ADC11

PDN_DIG_

ADC10

PDN_DIG_

ADC9

PDN_

LVDS12

PDN_

LVDS11

PDN_

LVDS10

PDN_

LVDS9

R/W-0h

7

R/W-0h

6

R/W-0h

5

R/W-0h

4

R/W-0h

3

R/W-0h

2

R/W-0h

1

R/W-0h

0

PDN_ANA_

ADC12

PDN_ANA_

ADC11

PDN_ANA_

ADC10

PDN_ANA_

ADC9

INVERT_

LVDS12

INVERT_

LVDS11

INVERT_

LVDS10

INVERT_

LVDS9

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; = value after reset

表 92. Register 30h Field Descriptions

Bit

Field

Type

Reset

Description

15

PDN_DIG_ADC12

R/W

0h

0 = Normal operation (default)

1 = Powers down the digital block for ADC12

14

13

12

11

10

9

PDN_DIG_ADC11

PDN_DIG_ADC10

PDN_DIG_ADC9

PDN_LVDS12

R/W

0h

0 = Normal operation (default)

1 = Powers down the digital block for ADC11

0 = Normal operation (default)

1 = Powers down the digital block for ADC10

0 = Normal operation (default)

1 = Powers down the digital block for ADC9

0 = Normal operation (default)

1 = Powers down LVDS output line 12

PDN_LVDS11

0 = Normal operation (default)

1 = Powers down LVDS output line 11

PDN_LVDS10

0 = Normal operation (default)

1 = Powers down LVDS output line 10

8

PDN_LVDS9

0 = Normal operation (default)

1 = Powers down LVDS output line 9

7

PDN_ANA_ADC12

PDN_ANA_ADC11

PDN_ANA_ADC10

PDN_ANA_ADC9

INVERT_LVDS12

0 = Normal operation (default)

1 = Powers down the analog block for ADC12

6

0 = Normal operation (default)

1 = Powers down the analog block for ADC11

5

0 = Normal operation (default)

1 = Powers down the analog block for ADC10

4

0 = Normal operation (default)

1 = Powers down the analog block for ADC9

3

0 = Normal operation (default)

1 = Inverts ADC data sent on LVDS output line 12. Has no effect

on Test patterns.

2

1

0

INVERT_LVDS11

INVERT_LVDS10

INVERT_LVDS9

R/W

0h

0 = Normal operation (default)

1 = Inverts ADC data sent on LVDS output line 11. Has no effect

on Test patterns.

0 = Normal operation (default)

1 = Inverts ADC data sent on LVDS output line 10. Has no effect

on Test patterns.

0 = Normal operation (default)

1 = Inverts ADC data sent on LVDS output line 9. Has no effect

on Test patterns.

125

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12.1.1.44 Register 31h (address = 31h)

图 140. Register 31h

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC13o

R/W-0h

OFFSET_ADC13o

R/W-0h

5

4

3

2

1

0

OFFSET_ADC13o

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 93. Register 31h Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC13o

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the odd sample of ADC13 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC13o

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the odd sample of ADC13 can

be obtained with this 10-bit register. The offset value is in twos

complement format and its LSB corresponds to a 14-bit LSB.

12.1.1.45 Register 32h (address = 32h)

图 141. Register 32h

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC13e

R/W-0h

OFFSET_ADC13e

R/W-0h

5

4

3

2

1

0

OFFSET_ADC13e

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 94. Register 32h Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC13e

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the even sample of ADC13 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC13e

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the even sample of ADC13

can be obtained with this 10-bit register. The offset value is in

twos complement format and its LSB corresponds to a 14-bit

LSB.

126

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12.1.1.46 Register 33h (address = 33h)

图 142. Register 33h

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC14o

R/W-0h

OFFSET_ADC14o

R/W-0h

5

4

3

2

1

0

OFFSET_ADC14o

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 95. Register 33h Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC14o

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the odd sample of ADC14 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC14o

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the odd sample of ADC14 can

be obtained with this 10-bit register. The offset value is in twos

complement format and its LSB corresponds to a 14-bit LSB.

12.1.1.47 Register 34h (address = 34h)

图 143. Register 34h

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC14e

R/W-0h

OFFSET_ADC14e

R/W-0h

5

4

3

2

1

0

OFFSET_ADC14e

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 96. Register 34h Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC14e

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the even sample of ADC14 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC14e

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the even sample of ADC14

can be obtained with this 10-bit register. The offset value is in

twos complement format and its LSB corresponds to a 14-bit

LSB.

127

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12.1.1.48 Register 35h (address = 35h)

图 144. Register 35h

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC15o

R/W-0h

OFFSET_ADC15o

R/W-0h

5

4

3

2

1

0

OFFSET_ADC15o

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 97. Register 35h Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC15o

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the odd sample of ADC15 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC15o

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the odd sample of ADC15 can

be obtained with this 10-bit register. The offset value is in twos

complement format and its LSB corresponds to a 14-bit LSB.

12.1.1.49 Register 36h (address = 36h)

图 145. Register 36h

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC15e

R/W-0h

OFFSET_ADC15e

R/W-0h

5

4

3

2

1

0

OFFSET_ADC15e

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 98. Register 36h Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC15e

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the even sample of ADC15 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC15e

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the even sample of ADC15

can be obtained with this 10-bit register. The offset value is in

twos complement format and its LSB corresponds to a 14-bit

LSB.

128

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12.1.1.50 Register 37h (address = 37h)

图 146. Register 37h

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC16o

R/W-0h

OFFSET_ADC16o

R/W-0h

5

4

3

2

1

0

OFFSET_ADC16o

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 99. Register 37h Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC16o

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the odd sample of ADC16 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC16o

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the odd sample of ADC16 can

be obtained with this 10-bit register. The offset value is in twos

complement format and its LSB corresponds to a 14-bit LSB.

12.1.1.51 Register 38h (address = 38h)

图 147. Register 38h

15

7

14

6

13

12

11

10

0

9

8

GAIN_ADC16e

R/W-0h

OFFSET_ADC16e

R/W-0h

5

4

3

2

1

0

OFFSET_ADC16e

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 100. Register 38h Field Descriptions

Bit

Field

Type

Reset

Description

15-11

GAIN_ADC16e

R/W

0h

When the DIG_GAIN_EN bit (register 3, bit 12) is set to 1, the

digital gain value for the even sample of ADC16 can be obtained

with this register. For a value of N (decimal equivalent of binary)

written to these bits, the digital gain gets set to N × 0.2 dB.

10

0

R/W

0h

Must write 0

9-0

OFFSET_ADC16e

When the DIG_OFFSET_EN bit (register 3, bit 8) is set to 1, the

offset value to be subtracted from the even sample of ADC16

can be obtained with this 10-bit register. The offset value is in

twos complement format and its LSB corresponds to a 14-bit

LSB.

129

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12.1.1.52 Register 39h (address = 39h)

图 148. Register 39h

15

14

13

12

11

10

9

1

8

PAT_PRBS_

LVDS13

PAT_PRBS_

LVDS14

PAT_PRBS_

LVDS15

PAT_PRBS_

LVDS16

PAT_LVDS13

PAT_LVDS14

R/W-0h

7

R/W-0h

6

R/W-0h

5

R/W-0h

4

R/W-0h

2

R/W-0h

0

3

DIG_HPF_EN_

ADC13-16

PAT_LVDS14

R/W-0h

0

HPF_CORNER_ADC13-16

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 101. Register 39h Field Descriptions

Bit

Field

Type

Reset

Description

15

PAT_PRBS_LVDS13

R/W

0h

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the PRBS pattern on LVDS output 13 can be enabled with this

bit; see the LVDS Test Pattern Mode section for further details.

14

13

PAT_PRBS_LVDS14

PAT_PRBS_LVDS15

PAT_PRBS_LVDS16

PAT_LVDS13[2:0]

PAT_LVDS14[2:0]

R/W

0h

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the PRBS pattern on LVDS output 14 can be enabled with this

bit; see the LVDS Test Pattern Mode section for further details.

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the PRBS pattern on LVDS output 15 can be enabled with this

bit; see the LVDS Test Pattern Mode section for further details.

12

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the PRBS pattern on LVDS output 16 can be enabled with this

bit; see the LVDS Test Pattern Mode section for further details.

11-9

8-6

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the pattern on LVDS output 13 can be programmed with these

bits; see 表 33 for bit descriptions.

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the pattern on LVDS output 14 can be programmed with these

bits; see 表 33 for bit descriptions.

5

0

R/W

0h

Must write 0

4-1

HPF_CORNER_ADC13-16

When the DIG_HPF_EN_CH13-16 bit is set to 1, the digital HPF

characteristic for the corresponding ADCs can be programmed

by setting the value of k with these bits.

The value of k can be from 2 to 10 (0010b to 1010b); see the

Digital HPF section for further details.

0

DIG_HPF_EN_ADC13-16

R/W

0h

0 = Digital HPF disabled for ADCs 13 to 16 (default)

1 = Enables digital HPF for ADCs 13 to 16

130

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12.1.1.53 Register 3Bh (address = 3Bh)

图 149. Register 3Bh

15

0

14

0

13

0

12

0

11

10

9

8

IN_16CH_

ADC13

IN_16CH_

ADC14

IN_16CH_

ADC15

IN_16CH_

ADC16

R/W-0h

7

R/W-0h

5

R/W-0h

4

R/W-0h

2

R/W-0h

6

3

1

0

PAT_LVDS15

R/W-0h

PAT_LVDS16

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 102. Register 3Bh Field Descriptions

Bit

15-12

11

Field

Type

R/W

Reset

0h

Description

0

Must write 0

IN_16CH_ADC13

0h

Selects the input pair sampled by ADC13 in 16-input mode.

0 = ADC13 samples the signal on INP25, INM25

1 = ADC13 samples the signal on INP26, INM26

10

9

IN_16CH_ADC14

IN_16CH_ADC15

IN_16CH_ADC16

PAT_LVDS15[2:0]

PAT_LVDS16[2:0]

0

R/W

0h

Selects the input pair sampled by ADC14 in 16-input mode.

0 = ADC14 samples the signal on INP27, INM27

1 = ADC14 samples the signal on INP28, INM28

Selects the input pair sampled by ADC15 in 16-input mode.

0 = ADC15 samples the signal on INP29, INM29

1 = ADC15 samples the signal on INP30, INM30

8

Selects the input pair sampled by ADC16 in 16-input mode.

0 = ADC16 samples the signal on INP31, INM31

1 = ADC16 samples the signal on INP32, INM32

7-5

4-2

1-0

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the pattern on LVDS output 15 can be programmed with these

bits; see 表 33 for bit descriptions.

When the PAT_SELECT_IND bit (register 4, bit 8) is set to 1,

the pattern on LVDS output 16 can be programmed with these

bits; see 表 33 for bit descriptions.

Must write 0

131

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12.1.1.54 Register 3Ch (address = 3Ch)

图 150. Register 3Ch

15

14

13

12

11

10

9

8

PDN_DIG_

ADC16

PDN_DIG_

ADC15

PDN_DIG_

ADC14

PDN_DIG_

PDN_LVDS16 PDN_LVDS15 PDN_LVDS14 PDN_LVDS13

R/W-0h

7

R/W-0h

6

R/W-0h

5

R/W-0h

4

R/W-0h

3

R/W-0h

2

R/W-0h

1

R/W-0h

0

PDN_ANA_

ADC16

PDN_ANA_

ADC15

PDN_ANA_

ADC14

PDN_ANA_

ADC13

INVERT_

LVDS16

INVERT_

LVDS15

INVERT_

LVDS14

INVERT_

LVDS13

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 103. Register 3Ch Field Descriptions

Bit

Field

Type

Reset

Description

15

PDN_DIG_ADC16

R/W

0h

0 = Normal operation (default)

1 = Powers down the digital block for ADC16

14

13

12

11

10

9

PDN_DIG_ADC15

PDN_DIG_ADC14

PDN_DIG_ADC13

PDN_LVDS16

R/W

0h

0 = Normal operation (default)

1 = Powers down the digital block for ADC15

0 = Normal operation (default)

1 = Powers down the digital block for ADC14

0 = Normal operation (default)

1 = Powers down the digital block for ADC13

0 = Normal operation (default)

1 = Powers down LVDS output line 16

PDN_LVDS15

0 = Normal operation (default)

1 = Powers down LVDS output line 15

PDN_LVDS14

0 = Normal operation (default)

1 = Powers down LVDS output line 14

8

PDN_LVDS13

0 = Normal operation (default)

1 = Powers down LVDS output line 13

7

PDN_ANA_ADC16

PDN_ANA_ADC15

PDN_ANA_ADC14

PDN_ANA_ADC13

INVERT_LVDS16

0 = Normal operation (default)

1 = Powers down the analog block for ADC16

6

0 = Normal operation (default)

1 = Powers down the analog block for ADC15

5

0 = Normal operation (default)

1 = Powers down the analog block for ADC14

4

0 = Normal operation (default)

1 = Powers down the analog block for ADC13

3

0 = Normal operation (default)

1 = Inverts ADC data sent on LVDS output line 16. Has no effect

on Test patterns.

2

1

0

INVERT_LVDS15

INVERT_LVDS14

INVERT_LVDS13

R/W

0h

0 = Normal operation (default)

1 = Inverts ADC data sent on LVDS output line 15. Has no effect

on Test patterns.

0 = Normal operation (default)

1 = Inverts ADC data sent on LVDS output line 14. Has no effect

on Test patterns.

0 = Normal operation (default)

1 = Inverts ADC data sent on LVDS output line 13. Has no effect

on Test patterns.

132

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12.1.1.55 Register 43h (address = 43h)

图 151. Register 43h

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

R/W-0h

7

0

6

0

5

0

4

3

2

1

0

LVDS_DCLK_DELAY_PROG

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 104. Register 43h Field Descriptions

Bit

15-5

4-1

Field

Type

R/W

Reset

0h

Description

0

Must write 0

LVDS_DCLK_DELAY_PROG

0h

The LVDS DCLK output delay is programmable with 110-ps

steps. Delay values are in twos complement format. Increasing

the positive delay increases setup time and reduces hold time,

and vice-versa for the negative delay.

0000 = No delay

0001 = 110 ps

0010 = 220 ps

…

1110 = –220 ps

1111 = –110ps

…

0

R/W

0h

Must write 0

133

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12.2.1 Description of JESD Serial Interface Registers

12.2.1.1 Register 70 (address = 46h)

图 152. Register 70

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

R/W-0h

7

0

6

0

5

0

4

0

3

0

2

1

0

MASK_TX_

TRIG

JESD_RESET1

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 106. Register 70 Field Descriptions

Bit

15-3

2

Field

Type

R/W

Reset

0h

Description

0

Must write 0

MASK_TX_TRIG

0h

0 = TX_TRIG affects internal clock-phase resets

1 = TX_TRIG does not affect internal clock-phase resets

1

JESD_RESET1

R/W

0h

0 = SYNC~ and SYSREF events reset non-JESD blocks (such

as the clock dividers, demodulator, and test pattern generator)

1 = SYNC~ and SYSREF events do not reset non-JESD blocks

(such as the clock dividers, demodulator, and test pattern

generator)

0

R/W

0h

Must write 0

135

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12.2.1.2 Register 73 (address = 49h)

图 153. Register 73

15

14

0

13

0

12

11

10

9

0

8

0

LINK_CONFIG

_DIS

IDLE_MODE

R/W-0h

LANE_ALIGN FRAME_ALIGN

R/W-0h

7

0

6

0

5

0

4

0

3

0

2

1

0

FORCE_K

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 107. Register 73 Field Descriptions

Bit

Field

Type

Reset

Description

15

IDLE_MODE

R/W

0h

0 = Idle mode disabled (normal operation)

1 = Device sends a continuous pattern (BC50h) on all lanes

Must write 0

14-13

12

0

R/W

0h

LANE_ALIGN

0 = Character replacement disabled. Data are sent without

inserting a lane alignment control character.

1 = If the last octet of the multiframe is the same as the last

octet of the previous multiframe, then the last octet is replaced

with a /K28.3/ character that can be used by the receiver for

lane alignment monitoring and correction; see the JESD204B

document., section 5.3.3.4 for details.

11

10

FRAME_ALIGN

R/W

0h

0 = Character replacement is disabled. Data are sent without

inserting a frame alignment control character.

1 = If the last octet of the frame is the same as the last octet of

the previous frame, then the octet is replaced with /K28.7/.

Character replacement is not performed if a control character

was already sent in the previous frame; see the JESD204B

document., section 5.3.3.4 for details.

LINK_CONFIG_DIS

0 = ILA transmission enabled. The initial lane alignment data are

sent, as per section 5.3.3.5 and 8.3 of the JESD204B document.

1 = ILA transmission disabled. The device starts sending

payload data immediately after the code group synchronization.

9-3

2

0

R/W

0h

Must write 0

FORCE_K

0 = Value of K (number of frames per multiframe) minus 1 is

automatically calculated and set

1 = Value of K (number of frames per multiframe) minus 1 is set

by the K_VALUE_TO_FORCE register setting

1-0

0

R/W

0h

Must write 0

136

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12.2.1.3 Register 74 (address = 4Ah)

图 154. Register 74

15

14

13

12

11

10

9

0

8

TX_SYNC_

REQ

LINK_LAYER_TESTMODES

RELEASE_ILA

R/W-0h

JESD_RESET2

R/W-0h

6

R/W-0h

7

5

0

4

0

3

0

2

0

1

0

JESD_RESET3

R/W-0h

0

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 108. Register 74 Field Descriptions

Bit

Field

Type

Reset

Description

15-13

LINK_LAYER_TESTMODES

R/W

0h

000 = Normal operation

001 = D21.5 (1010101010) is transmitted on all lanes

010 = /K28.5/ is transmitted on all lanes

011 = ILA sequence is continuously transmitted on all lanes

100 = Pseudo-random pattern of 120 bits is transmitted on all

lanes

All other combinations are invalid.

12

TX_SYNC_REQ

RELEASE_ILA

R/W

0h

0 = Sync reinitialization request disabled (normal operation)

1 = A stream of /K28.5/ symbols are transmitted, requesting link

reinitialization. After transmission, the /K28.5/ characters enter

into a link initialization state; see section 5.3.3.7 of the

JESD204B document for further details.

11-10

000 = Default value

The value of this register determines the LMFC edge that the

transmitter enters in the ILA phase from the code group

synchronization. This setting is useful for adjusting the

deterministic latency value; see the Data Link Layer section.

9

8

0

R/W

0h

Must write 0

JESD_RESET2

0 = SYNC~ and SYSREF events reset the phase of JESD and

non-JESD blocks (demodulator, test pattern generator, and

clock dividers)

1 = SYNC~ and SYSREF events do not reset the phase of

JESD block and clock dividers but do reset the phase of the

demodulator and test pattern generator

7

JESD_RESET3

R/W

0h

0 = SYNC~ and SYSREF events reset the phase of JESD and

non-JESD blocks (demodulator, test pattern generator, and

clock dividers)

1 = Immediately after setting this bit to 1, the first SYNC~ and

SYSREF event resets the phase of the JESD and non-JESD

blocks. Subsequent SYNC~ and SYSREF events do not reset

the phase of the JESD block and clock dividers but do reset the

phase of the demodulator and test pattern generator.

6-0

0

Must write 0

137

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12.2.1.4 Register 75 (address = 4Bh)

图 155. Register 75

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

SING_CONV_

PER_OCT

R/W-0h

7

R/W-0h

5

R/W-0h

6

4

0

3

0

2

0

1

0

NUM_ADC_PER_LANE

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 109. Register 75 Field Descriptions

Bit

15-9

8

Field

Type

R/W

Reset

0h

Description

0

Must write 0

SING_CONV_PER_OCT

0h

0 = Data are packed efficiently and transmitted over the link

1 = Each ADC data are packed in two octets [that is, each ADC

data are transmitted as 16 bits (12-, 14-, and 16-bit mode) by

the appropriate zero padding]; see the User Data Format section

for further details.

7-5

NUM_ADC_PER_LANE

R/W

0h

000 = Four ADCs per lane mode: data from four ADCs are

packed into a lane. Four lanes are active and four lanes are

powered down.

001 = Eight ADCs per lane mode: data from eight ADCs are

packed into a lane. Two lanes are active and six lanes are

powered down.

100 = Two ADCs per lane mode: data from two ADCs are

packed into a lane. All eight lanes are active.

All other settings are invalid.

4-0

0

R/W

0h

Must write 0

138

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12.2.1.5 Register 77 (address = 4Dh)

图 156. Register 77

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

R/W-0h

7

6

5

4

3

0

2

0

1

0

PRE_EMP

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 110. Register 77 Field Descriptions

Bit

15-8

7-4

Field

Type

R/W

Reset

0h

Description

0

Must write 0

PRE_EMP

0h

The extra current during pre-emphasis is equal to the decimal

equivalent of the programmed value multiplied by 0.25 mA. A

value corresponding to 0 refers to no pre-emphasis.

3-0

0

R/W

0h

Must write 0

12.2.1.6 Register 80 (address = 50h)

图 157. Register 80

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

R/W-0h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

INC_JESD_

VDD

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 111. Register 80 Field Descriptions

Bit

15-2

1

Field

Type

R/W

Reset

0h

Description

0

Must write 0

INC_JESD_VDD

0h

0 = Default value for the internal LDO driving the JESD PLL

1 = Increased value for the internal LDO driving the JESD PLL

0

R/W

0h

Must write 0

139

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12.2.1.7 Register 81 (address = 51h)

图 158. Register 81

15

14

13

12

11

10

9

1

8

0

DEVICE_ID

R/W-0h

7

0

6

0

5

0

4

3

2

BANK_ID

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 112. Register 81 Field Descriptions

Bit

15-8

7-5

Field

Type

R/W

Reset

0h

Description

DEVICE_ID

0

These bits force the device ID value.

Must write 0

0h

4-0

BANK_ID

0h

These bits force the bank ID value.

12.2.1.8 Register 82 (address = 52h)

图 159. Register 82

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

R/W-0h

7

6

0

5

0

4

0

3

0

2

0

1

0

SCR_EN

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 113. Register 82 Field Descriptions

Bit

15-8

7

Field

0

Type

R/W

Reset

0h

Description

Must write 0

SCR_EN

0h

0 = Scrambler disabled

1 = Scrambler enabled; see the Scrambler section for further

details

6-0

0

R/W

0h

Must write 0

140

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12.2.1.9 Register 83 (address = 53h)

图 160. Register 83

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

R/W-0h

7

0

6

0

5

0

4

3

2

1

0

K_VALUE_TO_FORCE

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 114. Register 83 Field Descriptions

Bit

15-5

4-0

Field

Type

R/W

Reset

0h

Description

0

Must write 0

K_VALUE_TO_FORCE

0h

Specifies the value of K (number of frames per multiframe)

minus 1 to be forced when the FORCE_K bit is set to 1.

12.2.1.10 Register 85 (address = 55h)

图 161. Register 85

15

7

14

13

5

12

0

11

0

10

0

9

0

8

0

JESD_SUBCLASS

R/W-0h

6

4

0

3

0

2

0

1

0

JESD_VER

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 115. Register 85 Field Descriptions

Bit

Field

Type

Reset

Description

15-13

JESD_SUBCLASS

R/W

0h

000 = Subclass 0

001 = Subclass 1

010 = subclass 2

See the JESD Version and Subclass section for further details.

12-8

7-5

0

R/W

0h

Must write 0

JESD_VER

000 = JESD204A

001 = JESD204B

See the JESD Version and Subclass section for further details.

4-0

0

R/W

0h

Must write 0

141

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12.2.1.11 Register 115 (address = 73h)

图 162. Register 115

15

14

13

12

11

10

9

8

EN_

CHECKSUM_

LANE2

EN_

CHECKSUM_

LANE3

EN_

CHECKSUM_

LANE4

EN_LANE_ID1 EN_LANE_ID2 EN_LANE_ID3 EN_LANE_ID4 CHECKSUM_

LANE1

R/W-0h

7

R/W-0h

6

R/W-0h

5

R/W-0h

4

R/W-0h

3

R/W-0h

2

R/W-0h

1

R/W-0h

0

ENABLE_JESD

_VER_

0

CONTROL

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 116. Register 115 Field Descriptions

Bit

Field

Type

Reset

Description

15

EN_LANE_ID1

R/W

0h

0 = Lane 1 default ID (00001) is set

1 = Lane 1 default ID (00001) can be forced with register 118,

bits 12-8

14

13

12

11

10

9

EN_LANE_ID2

R/W

0h

0 = Lane 2 default ID (00010) is set

1 = Lane 2 default ID (00010) can be forced with register 118,

bits 4-0

EN_LANE_ID3

0 = Lane 3 default ID (00011) is set

1 = Lane 3 default ID (00011) can be forced with register 119,

bits 12-8

EN_LANE_ID4

0 = Lane 4 default ID (00100) is set

1 = Lane 4 default ID (00100) can be forced with register 119,

bits 4-0

EN_CHECKSUM_LANE1

EN_CHECKSUM_LANE2

EN_CHECKSUM_LANE3

EN_CHECKSUM_LANE4

0 = The default checksum value is calculated by the device

1 = Checksum value (FCHK field in 表 15) is forced from register

116, bits 15-8

0 = The default checksum value is calculated by the device

1 = Checksum value (FCHK field in 表 15) is forced from register

116, bits 7-0

0 = The default checksum value is calculated by the device

1 = Checksum value (FCHK field in 表 15) is forced from register

117, bits 15-8

8

0 = The default checksum value is calculated by the device

1 = Checksum value (FCHK field in 表 15) is forced from register

117, bits 7-0

7-5

4

0

R/W

0h

Must write 0

ENABLE_JESD_VER_CONTROL

0 = The device is in JESD204B, subclass 1 mode

1 = JESD version and subclass can be changed; see the 表 15

section for further details.

3-0

0

R/W

0h

Must write 0

142

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12.2.1.12 Register 116 (address = 74h)

图 163. Register 116

15

7

14

6

13

5

12

11

10

2

9

1

8

0

CHECK_SUM1

R/W-0h

4

3

CHECK_SUM2

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 117. Register 116 Field Descriptions

Bit

Field

Type

Reset

Description

15-8

CHECK_SUM1

R/W

0h

These bits determine the lane 1 checksum value; see register

135.

7-0

CHECK_SUM2

R/W

0h

These bits determine the lane 2 checksum value; see register

135.

12.2.1.13 Register 117 (address = 75h)

图 164. Register 117

15

7

14

6

13

5

12

11

10

2

9

1

8

0

CHECK_SUM3

R/W-0h

4

3

CHECK_SUM4

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 118. Register 117 Field Descriptions

Bit

Field

Type

Reset

Description

15-8

CHECK_SUM3

R/W

0h

These bits determine the lane 3 checksum value; see register

136.

7-0

CHECK_SUM4

R/W

0h

These bits determine the lane 4 checksum value; see register

136.

143

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12.2.1.14 Register 118 (address = 76h)

图 165. Register 118

15

0

14

0

13

0

12

11

10

9

1

8

0

LANE_ID1

R/W-0h

7

0

6

0

5

0

4

3

2

LANE_ID2

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 119. Register 118 Field Descriptions

Bit

15-13

12-8

7-5

Field

Type

R/W

Reset

0h

Description

0

Must write 0

LANE_ID1

0

0h

These bits determine the lane 1 ID value; see register 137.

Must write 0

0h

4-0

LANE_ID2

0h

These bits determine the lane 2 ID value; see register 137.

12.2.1.15 Register 119 (address = 77h)

图 166. Register 119

15

0

14

0

13

0

12

11

10

9

1

8

0

LANE_ID3

R/W-0h

7

0

6

0

5

0

4

3

2

LANE_ID4

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 120. Register 119 Field Descriptions

Bit

15-13

12-8

7-5

Field

Type

R/W

Reset

0h

Description

0

Must write 0

LANE_ID3

0

0h

These bits determine the lane 3 ID value; see register 138.

Must write 0

0h

4-0

LANE_ID4

0h

These bits determine the lane 4 ID value; see register 138.

144

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12.2.1.16 Register 120 (address = 78h)

图 167. Register 120

15

14

13

12

LMFC_COUNTER_INIT_VALUE

R/W-0h

11

10

9

0

8

0

FORCE_LMFC

_COUNT

R/W-0h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 121. Register 120 Field Descriptions

Bit

Field

Type

Reset

Description

15

FORCE_LMFC_COUNT

R/W

0h

0 = Default value

1 = The LMFC counter value is forced, as per register 120, bits

14-10.

14-10

9-0

LMFC_COUNTER_INIT_VALUE

R/W

0h

These bits specify the initial value of the LMFC counter. This

option is useful when the multiframe size must be different than

the default value; see the Synchronization Using SYNC~ and

SYSREF section.

0

Must write 0

145

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12.2.1.17 Register 134 (address = 86h)

图 168. Register 134

15

14

13

12

11

10

9

8

EN_

CHECKSUM_

LANE6

EN_

CHECKSUM_

LANE7

EN_

CHECKSUM_

LANE8

EN_LANE_ID5 EN_LANE_ID6 EN_LANE_ID7 EN_LANE_ID8 CHECKSUM_

LANE5

R/W-0h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

(1) This register is valid when JESD_WR_SEL (register 3, bit 5) is 1.

表 122. Register 134 Field Descriptions

Bit

Field

Type

R/W

Reset

0h

Description

15

EN_LANE_ID5

0 = Lane 5 default ID (00101) is set

1 = Lane 5 default ID (00101) can be forced with register 137, bits 12-8

14

13

12

11

10

9

EN_LANE_ID6

R/W

0h

0 = Lane 6 default ID (00110) is set

1 = Lane 6 default ID (00110) can be forced with register 137, bits 4-0

EN_LANE_ID7

0 = Lane 7 default ID (00111) is set

1 = Lane 7 default ID (00111) can be forced with register 138, bits 12-8

EN_LANE_ID8

0 = Lane 8 default ID (01000) is set

1 = Lane 8 default ID (01000) can be forced with register 138, bits 4-0

EN_CHECKSUM_LANE5

EN_CHECKSUM_LANE6

EN_CHECKSUM_LANE7

EN_CHECKSUM_LANE8

0

0 = Default checksum value calculated by device

1 = Checksum value (FCHK field in 表 15) from register 135, bits 15-8

0 = The default checksum value is calculated by the device

1 = Checksum value (FCHK field in 表 15) from register 135, bits 7-0

0 = The default checksum value is calculated by the device

1 = Checksum value (FCHK field in 表 15) from register 135, bits 15-8

8

0 = The default checksum value is calculated by the device

1 = Checksum value (FCHK field in 表 15) from register 135, bits 7-0

7-0

Must write 0

12.2.1.18 Register 135 (address = 87h)

图 169. Register 135

15

7

14

6

13

5

12

11

10

2

9

1

8

0

CHECK_SUM5

R/W-0h

4

3

CHECK_SUM6

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 123. Register 135 Field Descriptions

Bit

15-8

7-0

Field

Type

R/W

Reset

0h

Description

CHECK_SUM5

CHECK_SUM6

These bits determine the lane 5 checksum value.

These bits determine the lane 6 checksum value.

0h

146

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12.2.1.19 Register 136 (address = 88h)

图 170. Register 136

15

7

14

6

13

5

12

11

10

2

9

1

8

0

CHECK_SUM7

R/W-0h

4

3

CHECK_SUM8

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 124. Register 136 Field Descriptions

Bit

15-8

7-0

Field

Type

R/W

Reset

0h

Description

CHECK_SUM7

CHECK_SUM8

These bits determine the lane 7 checksum value.

These bits determine the lane 8 checksum value.

0h

12.2.1.20 Register 137 (address = 89h)

图 171. Register 137

15

0

14

0

13

0

12

11

10

9

1

8

0

LANE_ID5

R/W-0h

7

0

6

0

5

0

4

3

2

LANE_ID6

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 125. Register 137 Field Descriptions

Bit

15-13

12-8

7-5

Field

Type

R/W

Reset

0h

Description

0

Must write 0

LANE_ID5

0

0h

These bits determine the lane 5 ID value.

Must write 0

0h

4-0

LANE_ID6

0h

These bits determine the lane 6 ID value.

147

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12.2.1.21 Register 138 (address = 8Ah)

图 172. Register 138

15

0

14

0

13

0

12

11

10

9

1

8

0

LANE_ID7

R/W-0h

7

0

6

0

5

0

4

3

2

LANE_ID8

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

表 126. Register 138 Field Descriptions

Bit

15-13

12-8

7-5

Field

Type

R/W

Reset

0h

Description

0

Must write 0

LANE_ID7

0

0h

These bits determine the lane 7 ID value.

Must write 0

0h

4-0

LANE_ID8

0h

These bits determine the lane 8 ID value.

148

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13 器件和文档支持

13.1 文档支持

13.1.1 相关文档

《CDCE72010 数据表》，SCAS858

《CDCM7005 数据表》，SCAS793

《LMK048X 数据表》，SNAS605

《SN74AUP1T04 数据表》，SCES800

《高速时钟数据转换器》，SLYT075

13.2 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

13.3 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

13.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

13.5 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

149

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14 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请参阅左侧的导航栏。

150

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TRAY

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device

Package Package Pins SPQ Unit array

Max

matrix temperature

(°C)

L (mm)

W

K0

P1

CL

CW

Name

Type

(mm) (µm) (mm) (mm) (mm)

ADS52J90ZZE

ZZE

NFBGA

198

160

10 x 16

150

315 135.9 7620 19.2

13.5 10.35

Pack Materials-Page 1

重要声明和免责声明

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型号：	ADS52J90ZZE
厂家：	TEXAS INSTRUMENTS
描述：	14 位多通道低功耗高速模数转换器 (ADC) \| ZZE \| 198 \| -40 to 85 转换器模数转换器
文件：	总153页 (文件大小：4702K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS52J90ZZE [TI]

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