ADS5400IPZP [TI]
12-Bit, 1-GSPS Analog-to-Digital Converter; 12位， 1 GSPS模拟数字转换器
| 型号： | ADS5400IPZP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12-Bit, 1-GSPS Analog-to-Digital Converter |
| 文件： | 总48页 (文件大小：1314K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS5400
www.ti.com
SLAS611B –OCT 2009–REVISED MARCH 2010
12-Bit, 1-GSPS Analog-to-Digital Converter
Check for Samples: ADS5400
1
FEATURES
•
•
On-Chip Analog Buffer
23
•
1-GSPS Sample Rate
100-Pin TQFP PowerPAD™ Package
(16-mm × 16-mm Footprint With Leads)
•
12-Bit Resolution
•
Industrial Temperature Range = –40°C to 85°C
•
•
•
•
•
2.1 GHz Input Bandwidth
SFDR = 66 dBc at 1.2 GHz
SNR = 57.6 dBFS at 1.2 GHz
7 Clock Cycle Latency
APPLICATIONS
•
•
•
•
•
•
Test and Measurement Instrumentation
Ultra-Wide Band Software-Defined Radio
Data Acquisition
Power Amplifier Linearization
Signal Intelligence and Jamming
Radar
Interleave Friendly: Internal Adjustments for
Gain, Phase, and Offset
•
•
•
1.5V to 2V Selectable Full-Scale Range
LVDS-Compatible Outputs, 1 or 2 Bus Options
Total Power Dissipation: 2.15 W
DESCRIPTION
The ADS5400 is a 12-bit, 1-GSPS analog-to-digital converter (ADC) that operates from both a 5-V supply and
3.3-V supply, while providing LVDS-compatible digital outputs. The analog input buffer isolates the internal
switching of the track and hold from disturbing the signal source. The simple 3-stage pipeline provides extremely
low latency for time critical applications. Designed for the conversion of signals up to 2 GHz of input frequency at
1 GSPS, the ADS5400 has outstanding low noise performance and spurious-free dynamic range over a large
input frequency range.
The ADS5400 is available in a TQFP-100 PowerPAD™ package. The combination of the PowerPAD package
and moderate power consumption of the ADS5400 allows for operation without an external heatsink. The
ADS5400 is built on Texas Instrument's complementary bipolar process (BiCom3) and is specified over the full
industrial temperature range (–40°C to 85°C).
BLOCK DIAGRAM
ADS5400
RESETP (SYNCINP)
RESETN (SYNCINN)
CLKINP
CLKINN
CLOCK
DIVIDE
INP
INN
12
CLKOUTAP
CLKOUTAN
12-bit ADC
(3 stage pipeline)
BUFFER
12
OUTA[0-11]P
OUTA[0-11]N
BUS A
VCM
OVRAP (SYNCOUTAP)
OVRAN (SYNCOUTAN)
REFERENCE
VREF
OVER RANGE
DETECTOR,
SYNC and
DEMUX
SCLK
SDIO
GAIN ADJUST
PHASE ADJUST
OFFSET ADJUST
TEMP SENSOR
CLKOUTBP
CLKOUTBN
SDO
12
SDENB
OUTB[0-11]P
OUTB[0-11]N
CONTROL
BUS B
ENEXTREF
ENPWD
ENA1BUS
OVRBP (SYNCOUTBP)
OVRBN (SYNCOUTBN)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2010, Texas Instruments Incorporated
ADS5400
SLAS611B –OCT 2009–REVISED MARCH 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Table 1. PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
(1)
ADS5400IPZP
Tray, 90
HTQFP-100
PowerPAD
ADS5400
PZP
–40°C to 85°C
ADS5400I
ADS5400IPZPR
Tape and reel, 1000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE
UNIT
V
AVDD5 to GND
6
5
Supply voltage
AVDD3 to GND
V
DVDD3 to GND
AINP, AINN to GND(2)
5
V
voltage difference between pin and ground
0.5 to 4.5
–0.3 to (AVDD5 + 0.3)
1.25 to 3.75
1.75 to 3.25
0.5 to 4.5
1.1 to 3.9
V
short duration
V
voltage difference between
(2)
AINP to AINN
pins, common mode at
AVDD5/2
continuous AC signal
continuous DC signal
V
V
(2)
CLKINP, CLKINN to GND
voltage difference between pin and ground
V
voltage difference between
pins, common mode at
AVDD5/2
continuous AC signal
continuous DC signal
V
(2)
CLKINP to CLKINN
2 to 3
V
(2)
RESETP, RESETN to GND
voltage difference between pin and ground
–0.3 to (AVDD5 + 0.3)
1.1 to 3.9
V
V
V
continuous AC signal
continuous DC signal
voltage difference between
pins
(2)
RESETP to RESETN
2 to 3
(2)
Data/OVR Outputs to GND
–0.3 to (DVDD3 + 0.3)
–0.3 to (AVDD3 + 0.3)
SDENB, SDIO, SCLK to GND(2)
voltage difference between pin and ground
V
ENA1BUS, ENPWD, ENEXTREF
to GND(2)
–0.3 to (AVDD5 + 0.3)
Operating temperature range
Maximum junction temperature, TJ
Storage temperature range
–40 to 85
150
°C
°C
°C
kV
–65 to 150
2
ESD, human-body model (HBM)
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied. Kirkendall voidings and current density information for calculation of expected lifetime is available upon
request.
(2) Valid when supplies are within recommended operating range.
THERMAL CHARACTERISTICS(1)
PARAMETER
TEST CONDITIONS
TYP
28.4
16.6
13.5
0.16
UNIT
°C/W
°C/W
Soldered thermal pad, no airflow
(2)
RqJA
Soldered thermal pad, 150-LFM airflow
Soldered thermal pad, 250-LFM airflow
Bottom of package (thermal pad)
(3)
RqJP
(1) Using 25 thermal pad vias (5 × 5 array). See PowerPAD Package in the Application Information section.
(2)
(3)
R
qJA is the thermal resistance from the junction to ambient.
RqJP is the thermal resistance from the junction to the thermal pad.
2
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS5400
ADS5400
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SLAS611B –OCT 2009–REVISED MARCH 2010
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLIES
Analog supply voltage, AVDD5
Analog supply voltage, AVDD3
Digital supply voltage, DVDD3
ANALOG INPUT
4.75
3.135
3.135
5
3.3
3.3
5.25
3.465
3.465
V
V
V
Full-scale differential input range
1.52
2
5
Vpp
V
VCM
DIGITAL OUTPUT
Differential output load
CLOCK INPUT
CLK input sample rate (sine wave)
Input common mode
AVDD5/2
pF
100
0.6
1000
1.5
MSPS
Vpp
Clock amplitude, differential
Clock duty cycle
45%
–40
50%
55%
85
TA
Open free-air temperature
°C
ELECTRICAL CHARACTERISTICS
Typical values at TA = 25°C, minimum and maximum values over full temperature range TMIN = –40°C to TMAX = 85°C,
sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1-dBFS differential input,
and 1.5 VPP differential clock (unless otherwise noted)
PARAMETER
ANALOG INPUTS
TEST CONDITIONS/NOTES
MIN
1.52
85
TYP
MAX
UNIT
Full-scale differential input range
Common-mode input
Programmable
2
VPP
V
VCM
RIN
Self-biased to AVDD5 / 2
AVDD5/2
100
Input resistance, differential (dc)
115
Ω
Estimated to ground from each AIN pin,
excluding soldered package
CIN
Input capacitance
0.8
40
pF
dB
CMRR
Common-mode rejection ratio
Common mode signal = 125 MHz
INTERNAL REFERENCE VOLTAGE
VREF Reference voltage
2
V
DYNAMIC ACCURACY
Resolution
No missing codes
fIN = 125 MHz
12
-1
Bits
LSB
DNL
INL
Differential linearity error
±0.7
±2
2
4.5
2.5
Integral non- linearity error
Offset error
fIN = 125 MHz
-4
LSB
default is trimmed near 0mV
–2.5
0
mV
Offset temperature coefficient
Gain error
0.02
mV/°C
%FS
%FS/°C
–5
5
Gain temperature coefficient
0.03
Copyright © 2009–2010, Texas Instruments Incorporated
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SLAS611B –OCT 2009–REVISED MARCH 2010
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ELECTRICAL CHARACTERISTICS (continued)
Typical values at TA = 25°C, minimum and maximum values over full temperature range TMIN = –40°C to TMAX = 85°C,
sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1-dBFS differential input,
and 1.5 VPP differential clock (unless otherwise noted)
PARAMETER
POWER SUPPLY(1)
TEST CONDITIONS/NOTES
MIN
TYP
MAX
UNIT
5-V analog supply current (Bus A and
B active)
220
225
219
226
136
71
234
241
234
242
154
81
mA
mA
mA
mA
mA
I(AVDD5)
I(AVDD3)
I(DVDD3)
5-V analog supply current (Bus A
active)
3.3-V analog supply current (Bus A
and B active)
3.3-V analog supply current (Bus A
active)
fIN = 125 MHz,
fS = 1 GSPS
3.3-V digital supply current
(Bus A and B active)
3.3-V digital supply current
(Bus A active)
mA
W
Total power dissipation
(BUS A and B active)
2.28
2.15
2.45
Total power dissipation
(Bus A active)
2.25
50
W
Total power dissipation
Wake-up time from sleep
ENPWD = logic High (sleep enabled)
13
mW
ms
1.8
1MHz injected to each supply,
measured without external decoupling
PSRR
Power-supply rejection ratio
50
dB
DYNAMIC AC CHARACTERISTICS
fIN = 125 MHz
fIN = 600 MHz
fIN = 850 MHz
fIN = 1200 MHz
fIN = 1700 MHz
fIN = 125 MHz
fIN = 600 MHz
fIN = 850 MHz
fIN = 1200 MHz
fIN = 1700 MHz
fIN = 125 MHz
fIN = 600 MHz
fIN = 850 MHz
fIN = 1200 MHz
fIN = 1700 MHz
fIN = 125 MHz
fIN = 600 MHz
fIN = 850 MHz
fIN = 1200 MHz
fIN = 1700 MHz
57
56.5
56
58.5
58.2
57.8
57.6
55.7
75
SNR
SFDR
HD2
Signal-to-noise ratio
Spurious-free dynamic range
Second harmonic
dBFS
65
63
60
72
71
dBc
dBc
dBc
66
56
65
63
60
78
78
71
66
56
65
63
60
80
72
HD3
Third harmonic
72
70
65
(1) All power values assume LVDS output current is set to 3.5mA.
4
Copyright © 2009–2010, Texas Instruments Incorporated
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SLAS611B –OCT 2009–REVISED MARCH 2010
ELECTRICAL CHARACTERISTICS (continued)
Typical values at TA = 25°C, minimum and maximum values over full temperature range TMIN = –40°C to TMAX = 85°C,
sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1-dBFS differential input,
and 1.5 VPP differential clock (unless otherwise noted)
PARAMETER
TEST CONDITIONS/NOTES
fIN = 125 MHz
MIN
65
TYP
80
MAX
UNIT
fIN = 600 MHz
fIN = 850 MHz
fIN = 1200 MHz
fIN = 1700 MHz
fIN = 125 MHz
fIN = 600 MHz
fIN = 850 MHz
fIN = 1200 MHz
fIN = 1700 MHz
fIN = 125 MHz
fIN = 600 MHz
fIN = 850 MHz
fIN = 1200 MHz
fIN = 1700 MHz
63
72
Worst harmonic/spur (other than HD2
and HD3)
60
72
dBc
66
64
63
62
59
71.7
67
THD
Total Harmonic Distortion
66.5
65.1
55.7
58.5
58.2
57.8
57.5
54.2
dBc
56
55
54
SINAD
Signal-to-noise and distortion
dBFS
fIN1 = 247.5 MHz, fIN2 = 252.5 MHz,
each tone at –7 dBFS
74.6
80.4
70
fIN1 = 247.5 MHz, fIN2 = 252.5 MHz,
each tone at –11 dBFS
Two-tone SFDR
dBFS
Bits
fIN1 = 1197.5 MHz, fIN2 = 1202.5 MHz,
each tone at –7 dBFS
fIN1 = 1197.5 MHz, fIN2 = 1202.5 MHz,
each tone at –11 dBFS
78.3
fIN = 125 MHz
fIN = 600 MHz
fIN = 850 MHz
9
8.84
8.67
9.42
9.37
9.3
Effective number of bits (using
SINAD in dBFS)
ENOB
1.41
60.2
LSB rms
dBFS
RMS idle-channel noise
Inputs tied to common-mode
SWITCHING CHARACTERISTICS
Typical values at TA = 25°C, Min and Max values over full temperature range TMIN = –40°C to TMAX = 85°C, sampling rate = 1
GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 VPP differential clock (unless otherwise
noted)
PARAMETER
TEST CONDITIONS/NOTES
MIN
TYP
MAX
UNIT
LVDS DIGITAL OUTPUTS (DATA, OVR/SYNCOUT, CLKOUT)
VOD
VOC
Differential output voltage (±)
Common mode output voltage
247
350
454
mV
V
Terminated 100 Ω differential
1.125
1.25
1.375
LVDS DIGITAL INPUTS (RESET)
VID
VIC
RIN
CIN
Differential input voltage (±)
Common mode input voltage
Input resistance
175
0.1
85
350
1.25
100
0.6
mV
V
Each input pin
2.4
115
Ω
Input capacitance
Each pin to ground
pF
Copyright © 2009–2010, Texas Instruments Incorporated
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SWITCHING CHARACTERISTICS (continued)
Typical values at TA = 25°C, Min and Max values over full temperature range TMIN = –40°C to TMAX = 85°C, sampling rate = 1
GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 VPP differential clock (unless otherwise
noted)
PARAMETER
TEST CONDITIONS/NOTES
MIN
TYP
MAX
UNIT
DIGITAL INPUTS (SCLK, SDIO, SDENB)
VIH
VIL
IIH
High level input voltage
Low level input voltage
High level input current
Low level input current
Input capacitance
2
0
AVDD3 + 0.3
0.8
V
V
±1
±1
2
mA
mA
pF
IIL
CIN
DIGITAL INPUTS ( ENEXTREF, ENPWD, ENA1BUS)
VIH
VIL
IIH
High level input voltage
Low level input voltage
High level input current
Low level input current
Input capacitance
2
0
AVDD5 + 0.3
0.8
V
V
125
20
2
mA
mA
pF
~40kΩ internal pull-down
IIL
CIN
DIGITAL OUTPUTS (SDIO, SDO)
VOH
VOL
High level output voltage
Low level output voltage
IOH = 250 µA
IOL = 250 µA
2.8
V
V
0.4
CLOCK INPUTS
RIN
Differential input resistance
Input capacitance
CLKINP, CLKINN
130
160
0.8
190
Ω
Estimated to ground from each
CLKIN pin, excluding soldered
packaged
CIN
pF
TIMING CHARACTERISTICS(1)
Typical values at TA = 25°C, Min and Max values over full temperature range TMIN = –40°C to TMAX = 85°C, sampling rate = 1
GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 VPP differential clock (unless otherwise
noted)
PARAMETER
TEST CONDITIONS/NOTES
MIN
TYP
MAX UNIT
ta
Aperture delay
250
ps
Uncertainty of sample point due to internal jitter
sources
Aperture jitter, rms
Latency
125
fs
Bus A, using Single Bus Mode
7
Bus A, using Dual Bus Mode Aligned
Bus B, using Dual Bus Mode Aligned
Bus A and B, using Dual Bus Mode Staggered
7.5
8.5
7.5
Cycles
LVDS OUTPUT TIMING (DATA, CLKOUT, OVR/SYNCOUT)(2)
tCLK
Clock period
1
0.45
0.45
700
700
10
ns
ns
ns
ps
ps
tCLKH
Clock pulse duration, high
Clock pulse duration, low
Clock propagation delay
Clock propagation delay
Assuming worst case 45/55 duty cycle
tCLKL
Assuming worst case 55/45 duty cycle
tPD-CLKDIV2
tPD-CLKDIV4
CLKIN rising to CLKOUT rising in divide by 2 mode
CLKIN rising to CLKOUT rising in divide by 4 mode
1200
1200
1700
1700
Bus A data propagation
delay
tPD-ADATA
tPD-BDATA
700
700
1400
1400
2100
2100
ps
ps
CLKIN falling to Data Output transition
Bus B data propagation
delay
(1) Timing parameters are specified by design or characterization, but not production tested.
(2) LVDS output timing measured with a differential 100Ω load placed ~4 inches from the ADS5400. Measured differential load capacitance
is 3.5pF. Measurement probes and other parasitics add ~1pF. Total approximate capacitive load is 4.5pF differential. All timing
parameters are relative to the device pins, with the loading as stated.
6
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SLAS611B –OCT 2009–REVISED MARCH 2010
TIMING CHARACTERISTICS (1) (continued)
Typical values at TA = 25°C, Min and Max values over full temperature range TMIN = –40°C to TMAX = 85°C, sampling rate = 1
GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 VPP differential clock (unless otherwise
noted)
PARAMETER
TEST CONDITIONS/NOTES
MIN
TYP
MAX UNIT
(tCLK/2) -
185p
(3)
tSU-SBM
Setup time, single bus mode Data valid to CLKOUT edge, 50% CLKIN duty cycle
290p
s
CLKOUT edge to Data invalid, 50% CLKIN duty
(tCLK/2) -
65p
tH-SBM
tSU-DBM
tH-DBM
Hold time, single bus mode
cycle
410p
s
s
s
Setup time, dual bus mode
Data valid to CLKOUT edge, 50% CLKIN duty cycle
550p tCLK - 425p
CLKOUT edge to Data invalid, 50% CLKIN duty
cycle
Hold time, dual bus mode
1150p tCLK + 175p
tr
tf
LVDS rise time
400
400
ps
ps
Mmeasured 20% to 80%
LVDS output fall time
LVDS INPUT TIMING (RESETIN)
tRSU
tRH
RESET setup time
RESETP going HIGH to CLKINP going LOW
CLKINP going LOW to RESETP going LOW
Differential
300
300
1
ps
ps
pF
µA
RESET hold time
RESET input capacitance
RESET input current
±1
SERIAL INTERFACE TIMING
tS-SDENB
tH-SDENB
tS-SDIO
tH-SDIO
fSCLK
tSCLK
tSCLKH
tSCLKL
tr
Setup time, serial enable
SDENB falling to SCLK rising
SCLK falling to SENDB rising
SDIO valid to SCLK rising
20
25
10
10
ns
ns
ns
ns
Hold time, serial enable
Setup time, SDIO
Hold time, SDIO
Frequency
SCLK rising to SDIO transition
10
MHz
ns
SCLK period
100
40
40
10
10
Minimum SCLK high time
Minimum SCLK low time
Rise time
ns
ns
10pF
10pF
ns
tf
Fall time
ns
Data output (SDO/SDIO) delay after SCLK falling,
10pF load
tDDATA
Data output delay
75
ns
(3) In single bus mode at 1GSPS (1ns clock), the minimum output setup/hold times over process and temperature provide a minimum
700ps of data valid window, with 300ps of uncertainity.
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INTERLEAVING ADJUSTMENTS
Typical values at TA = 25°C, Min and Max values over full temperature range TMIN = –40°C to TMAX = 85°C, sampling rate = 1
GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 VPP differential clock (unless otherwise
noted)
PARAMETER
OFFSET ADJUSTMENTS
Resolution
TEST CONDITIONS
MIN
TYP
MAX
UNIT
9
Bits
µV
LSB magnitude
at full scale range of 2VPP
120
DNL
INL
Differential linearity error
-2.5
-3
2.5
3
LSB
LSB
mV
Integral Non-Linearity error
Recommended Min Offset
Setting
-8
8
from default offset value, to maintain AC
performance
Recommended Max Offset
Setting
mV
GAIN ADJUSTMENTS
Resolution
12
Bits
µV
LSB magnitude
120
-2, +1
-2, +4
1.52
2
DNL
INL
Differential linearity error
-4
-8
4
8
LSB
LSB
VPP
VPP
Integral Non-Linearity error
Min Gain Setting
Max Gain Setting
INPUT CLOCK FINE PHASE ADJUSTMENT
Resolution
6
Bits
fs
LSB magnitude
116
7.4
2.4
73
DNL
INL
Differential linearity error
Integral Non-Linearity error
Max Fine Clock Skew setting
-2
2.5
4
LSB
LBS
ps
-2.5
INPUT CLOCK COARSE PHASE ADJUSTMENT
Resolution
5
Bits
ps
LSB magnitude
DNL
INL
Differential linearity error
Integral Non-Linearity error
-1
-1
1
5
LSB
LSB
ps
Max Coarse Clock Skew
setting
8
Copyright © 2009–2010, Texas Instruments Incorporated
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Timing Diagrams
N
DIFFERENTIAL
ANALOG INPUT
(INP-INN)
Aperture
delay
ta
N+1
N+2
Sample N and RESET pulse
captured here
N
output
N+1
output
tCLKH
tCLKL
CLKINP
tRH
tRSU
CLKOUT is reset after 3.5 CLKIN cycles (+ tPD-CLKDIV2
tPD-CLKDIV2
)
RESETP
Phase 0: CLKOUT in desired
CLKOUTAP state after power up
Phase 1: misaligned by
1 clock after power up
tPD-ADATA
t
su
Latency of N and SYNCOUTA are matched to 7 CLKIN cycles
t
h
N-1
N
N+1 N+2
DATA BUS A
If SYNC mode is enabled,
the OVRA pins become SYNCOUTA pins
SYNCOUTA
(OVRA pins)
Sync
Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase
will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT
phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of
repetitive RESET pulses should not exceed CLKIN/2, and should be an even divisor of CLKIN, in order to keep the
CLKOUT phase the same with each RESET event. SYNCOUTA transitions with the same latency as the sample that
is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a
SYNCOUT pulse, which behaves as a data bit. Bus B is not active in single bus mode.
Figure 1. Single Bus Mode
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Timing Diagrams (continued)
N, N+1
output
Sample N and RESET
pulse captured here
N+1
CLKINP
tRH
tRSU
CLKOUT is reset after 3.5 CLKIN cycles (+ tPD-CLKDIV2
tPD-CLKDIV2
)
RESETP
Phase 0: CLKOUT in desired
state after power up
CLKOUTAP
CLKOUTBP
Phase 1: misaligned by 1
clock after power up
tPD-BDATA
t
su
Latency of N and SYNCOUTB are matched to 8.5 CLKIN cycles
t
h
DATA BUS B
The phase of data shown prior to reset matches CLKOUT in phase 0
N
N+2
N+3
If SYNC mode is enabled,
the OVRB pins become SYNCOUTB pins
SYNCOUTB
(OVRB pins)
Sync
N+1
The phase of data shown prior to reset matches CLKOUT in phase 0
Latency of N+1 is 7.5 CLKIN cycles
DATA BUS A
tPD-ADATA
Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase
will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT
phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of
repetitive RESET pulses should not exceed CLKIN/2, and should be an even divisor of CLKIN, in order to keep the
CLKOUT phase the same with each RESET event. SYNCOUTB transitions with the same latency as the sample that
is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a
SYNCOUT pulse, which behaves as a data bit.
Figure 2. Dual Bus Mode - Aligned, CLKOUT Divide By 2
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Timing Diagrams (continued)
N
output
N+1
output
Sample N and RESET
pulse captured here
N+1
CLKINP
tRH
tRSU
CLKOUT is reset after 3.5 CLKIN cycles (+ tPD-CLKDIV2
tPD-CLKDIV2
)
RESETP
Phase 0: CLKOUT in desired
state after power up
CLKOUTAP
Phase 1: misaligned by 1
clock after power up
Phase 0: CLKOUT in desired
state after power up
CLKOUTBP
Phase 1: misaligned by 1
clock after power up
tPD-BDATA
t
su
Latency of N and SYNCOUTB are matched to 7.5 CLKIN cycles
The phase of data shown prior to reset matches CLKOUT in phase 0
t
h
DATA BUS B
N
N+2
If SYNC mode is enabled,
the OVRB pins become SYNCOUTB pins
SYNCOUTB
(OVRB pins)
Sync
DATA BUS A
N+1
N+3
The phase of data shown prior to reset matches CLKOUT in phase 0
tPD-ADATA
Latency of N+1 is 7.5 CLKIN cycles
Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase
will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT
phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of
repetitive RESET pulses should not exceed CLKIN/2, and should be an even divisor of CLKIN, in order to keep the
CLKOUT phase the same with each RESET event. SYNCOUTB transitions with the same latency as the sample that
is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a
SYNCOUT pulse, which behaves as a data bit.
Figure 3. Dual Bus Mode - Staggered, CLKOUT Divide By 2
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Timing Diagrams (continued)
Sample N and RESET
pulse captured here
N, N+1
output
N+1
CLKINP
tRH
tRSU
tPD-CLKDIV4
RESETP
CLKOUT is reset after 7.5 CLKIN cycles (+ tPD-CLKDIV4
)
Phase 0: CLKOUT in desired
state after power up
Phase 1: misaligned by 1
clock after power up
CLKOUTAP
CLKOUTBP
Phase 2: misaligned by 2
clocks after power up
Phase 3: misaligned by 3
clocks after power up
tPD-BDATA
t
su
Latency of N and SYNCOUTB are matched to 8.5 CLKIN cycles
t
h
DATA BUS B
The phase of data shown prior to reset matches CLKOUT in phase 0
N
SYNCOUTB
(OVRB pins)
If SYNC mode is enabled,
the OVRB pins become SYNCOUTB pins
Sync
The phase of data shown prior to reset matches CLKOUT in phase 0
Latency of N+1 is 7.5 CLKIN cycles
DATA BUS A
N+1
tPD-ADATA
Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase
will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT
phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of
repetitive RESET pulses should not exceed CLKIN/4, and should be an even divisor of CLKIN, in order to keep the
CLKOUT phase the same with each RESET event. SYNCOUTB transitions with the same latency as the sample that
is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a
SYNCOUT pulse, which behaves as a data bit.
Figure 4. Dual Bus Mode - Aligned, CLKOUT Divide By 4
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Timing Diagrams (continued)
N
output
N+1
output
Sample N and RESET
pulse captured here
N+1
sampled
CLKINP
tRH
tRSU
CLKOUTA is reset after 7.5 CLKIN cycles (+ tPD-CLKDIV4
)
RESETP
tPD-CLKDIV4
Phase 0: CLKOUT in desired
state after power up
Phase 1: misaligned by 1
clock after power up
CLKOUTAP
Phase 2: misaligned by 2
clocks after power up
Phase 3: misaligned by 3
clocks after power up
tPD-CLKDIV4
CLKOUTB is reset after 6.5 CLKIN cycles (+ tPD-CLKDIV4
)
Phase 0: CLKOUT in desired
state after power up
Phase 1: misaligned by 1
clock after power up
CLKOUTBP
Phase 2: misaligned by 2
clocks after power up
Phase 3: misaligned by 3
clocks after power up
tPD-BDATA
t
su
Latency of N and SYNCOUTB are matched to 7.5 CLKIN cycles
The phase of data shown prior to reset matches CLKOUTB in phase 0
t
h
N+2
DATA BUS B
N
If SYNC mode is enabled,
the OVRB pins become SYNCOUTB pins
SYNCOUTB
(OVRB pins)
Sync
DATA BUS A
N+1
The phase of data shown prior to reset matches CLKOUTA in phase 0
Latency of N+1 is 7.5 CLKIN cycles
tPD-ADATA
Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase
will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT
phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of
repetitive RESET pulses should not exceed CLKIN/4, and should be an even divisor of CLKIN, in order to keep the
CLKOUT phase the same with each RESET event. SYNCOUTB transitions with the same latency as the sample that
is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a
SYNCOUT pulse, which behaves as a data bit.
Figure 5. Dual Bus Mode - Staggered, CLKOUT Divide By 4
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PIN CONFIGURATION
DA11P
DA11N
DA10P
DA10N
DA9P
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
AVDD5
2
AVDD3
3
AGND
4
CLKINP
5
CLKINN
DA9N
6
AGND
DA8P
7
AVDD3
DA8N
8
AGND
DA7P
9
AVDD3
DA7N
10
11
12
13
14
15
16
17
18
19
20
RESETN
RESETP
DB11N
DGND
DVDD3
DA6P
ADS5400
(TOP VIEW)
DB11P
DA6N
DB10N
DB10P
DB9N
DB9P
DB8N
DB8P
DB7N
CLKOUTAP
CLKOUTAN
DA5P
DA5N
DA4P
DA4N
DA3P
DB7P 21
DA3N
DB6N
DB6P
22
23
24
25
DA2P
Thermal Pad = AGND
DA2N
DVDD3
DGND
DGND
14
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Table 2. PIN FUNCTIONS
PIN
DESCRIPTION
NAME
NO.
AINP, AINN
94, 95
Analog differential input signal (positive, negative). Includes 100-Ω differential load on-chip.
1, 76, 86, 90, 92,
97, 99
AVDD5
Analog power supply (5 V)
AVDD3
DVDD3
2, 7, 9, 85
Analog power supply (3.3 V)
24, 38, 50, 64
Output driver power supply (3.3 V)
3, 6, 8, 84, 88, 91,
93, 96, 98, 100
AGND
DGND
Analog Ground
25, 39, 51, 65
Digital Ground
CLKINP,
CLKINN
4, 5
Differential input clock (positive, negative). Includes 160-Ω differential load on-chip.
Bus A, LVDS digital output pair, least-significant bit (LSB) (P = positive output, N = negative output)
Bus A, LVDS digital output pairs (bits 1- 10)
DA0N, DA0P
46, 47
DA1N–DA10N, 48-49, 52-59, 62-63,
DA1P-DA10P
66-73
DA11N,
DA11P
74, 75
Bus A, LVDS digital output pair, most-significant bit (MSB)
CLKOUTAN,
CLKOUTAP
60, 61
40, 41
Bus A, Clock Output (Data ready), LVDS output pair
DB0N, DB0P
Bus B, LVDS digital output pair, least-significant bit (LSB) (P = positive output, N = negative output)
Bus B, LVDS digital output pairs (bits 1- 10)
DB1N–DB10N,
DB1P-DB10P
14-23, 28-37
DB11N,
DB11P
12, 13
26, 27
44, 45
42, 43
Bus B, LVDS digital output pair, most-significant bit (MSB)
Bus B, Clock Output (Data ready), LVDS output pair
CLKOUTBN,
CLKOUTBP
OVRAN,
OVRAP
Bus A, Overrange indicator LVDS output. A logic high signals an analog input in excess of the
full-scale range. Becomes SYNCOUTA when SYNC mode is enabled in register 0x05.
OVRBN,
OVRBP
Bus B, Overrange indicator LVDS output. A logic high signals an analog input in excess of the
full-scale range. Becomes SYNCOUTB when SYNC mode is enabled in register 0x05.
Digital Reset Input, LVDS input pair. Inactive if logic low. When clocked in a high state, this is used
for resetting the polarity of CLKOUT signal pair(s). If SYNC mode is enabled in register 0x05, this
input also provides a SYNC time-stamp with the data sample present when RESET is clocked by
the ADC, as well as CLKOUT polarity reset. Includes 100-Ω differential load on-chip.
RESETN,
RESETP
10, 11
SCLK
SDIO
78
79
Serial interface clock.
Bi-directional serial interface data in 3-pin mode (default) for programming/reading internal registers.
In 4-pin interface mode (reg 0x01), the SDIO pin is an input only.
Uni-directional serial interface data in 4-pin mode (reg 0x01) provides internal register settings. The
SDO pin is in high-impedance state in 3-pin interface mode (default).
SDO
80
77
Active low serial data enable, always an input. Use to enable the serial interface. Internal 100kΩ
pull-up resistor.
SDENB
VREF
Reference voltage input (2V nominal). A 0.1mF capacitor to AGND is recommended, but not
required.
87
Enable single output bus mode (2-bus mode is default), active high. This pin is logic OR'd with addr
0x02h bit<0>.
ENA1BUS
ENPWD
ENEXTREF
VCM
81(1)
82(1)
83(1)
89
Enable Powerdown, active high. Places the converter into power-saving sleep mode when high. This
pin is logic OR'd with addr 0x05h bit<6>.
Enable External Reference Mode, active high. Device uses an external voltage reference when high.
This pin is logic OR'd with addr 0x05h bit<2>.
Analog input common mode voltage, Output (for DC-coupled applications, nominally 2.5V). A 0.1mF
capacitor to AGND is recommended, but not required.
(1) This pin contains an internal ~40kΩ pull-down resistor, to ground.
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SERIAL INTERFACE
The serial port of the ADS5400 is a flexible serial interface which communicates with industry standard
microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the
operating modes of ADS5400. It is compatible with most synchronous transfer formats and can be configured as
a 3 or 4 pin interface in register 0x01h. In both configurations, SCLK is the serial interface input clock and
SDENB is serial interface enable. For 3 pin configuration, SDIO is a bidirectional pin for both data in and data
out. For 4 pin configuration, SDIO is data in only and SDO is data out only.
Each read/write operation is framed by signal SDENB (Serial Data Enable Bar) asserted low for 2 to 5 bytes,
depending on the data length to be transferred (1–4 bytes). The first frame byte is the instruction cycle which
identifies the following data transfer cycle as read or write, how many bytes to transfer, and what address to
transfer the data. Table 3 indicates the function of each bit in the instruction cycle and is followed by a detailed
description of each bit. Frame bytes 2 to 5 comprise the data transfer cycle.
Table 3. Instruction Byte of the Serial Interface
MSB
7
LSB
0
Bit
6
5
4
3
2
1
Description
R/W
N1
N0
A4
A3
A2
A1
A0
R/W
Identifies the following data transfer cycle as a read or write operation. A high indicates a read
operation from ADS5400 and a low indicates a write operation to the ADS5400.
[N1:N0]
Identifies the number of data bytes to be transferred per Table 4 below. Data is transferred MSB
first.
Table 4. Number of Transferred Bytes Within One
Communication Frame
N1
0
N0
0
Description
Transfer 1 Byte
Transfer 2 Bytes
Transfer 3 Bytes
Transfer 4 Bytes
0
1
1
0
1
1
[A4:A0]
Identifies the address of the register to be accessed during the read or write operation. For
multi-byte transfers, this address is the starting address. Note that the address is written to the
ADS5400 MSB first and counts down for each byte.
Figure 6 shows the serial interface timing diagram for a ADS5400 write operation. SCLK is the serial interface
clock input to ADS5400. Serial data enable SDENB is an active low input to ADS5400. SDIO is serial data in.
Input data to ADS5400 is clocked on the rising edges of SCLK.
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Instruction Cycle
Data Transfer Cycle (s)
SDENB
SCLK
SDIO
r/w N1 N0 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
t
(SDENB)
t
S
SCLK
SDENB
SCLK
SDIO
t
SCLKL
t
(SDIO)
h
t
SCLKH
t
(SDIO)
S
Figure 6. Serial Interface Write Timing Diagram
Figure 7 shows the serial interface timing diagram for a ADS5400 read operation. SCLK is the serial interface
clock input to ADS5400. Serial data enable SDENB is an active low input to ADS5400. SDIO is serial data in
during the instruction cycle. In 3 pin configuration, SDIO is data out from ADS5400 during the data transfer
cycle(s), while SDO is in a high-impedance state. In 4 pin configuration, SDO is data out from ADS5400 during
the data transfer cycle(s). At the end of the data transfer, SDO will output low on the final falling edge of SCLK
until the rising edge of SDENB when it will 3-state.
Instruction Cycle
Data Transfer Cycle(s)
SDENB
SCLK
SDIO
SDO
r/w N1 N0
-
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
0
0
3 pin Configuration Output
4 pin Configuration Output
SDENB
SCLK
SDIO
SDO
Data n
Data n-1
t
(Data)
d
Figure 7. Serial Interface Read Timing Diagram
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Serial Register Map
Table 5 gives a summary of all the modes that can be programmed through the serial interface.
Table 5. Summary of Functions Supported by Serial Interface
REGISTER
ADDRESS
IN HEX
REGISTER FUNCTIONS
Address
BIT 7
BIT 6
BIT 5
BIT 4 BIT 3
BIT 2
BIT 1
BIT 0
00
Analog Gain Adjustment bits<11:4>
3 or 4-pin
01
02
continued...Analog Gain Adjustment bits<3:0>
Coarse Clock Phase Adjustment bits<4:0>
Fine Clock Phase Adjustment bits<5:0>
SPI Reset
0
0
0
SPI
Clock
Divider
Single or Dual
Bus
Analog Offset
bit<8>
03
04
05
0
continued...Analog Offset Control bits<7:0>
Data
Stagger
Output
Temp Sensor
Powerdown
1
Sync Mode
Reference
0
Format
06
07
Data output mode
LVDS termination
0000 0000
LVDS current
Force LVDS outputs
08
Die temperature bits<7:0>
000 0000
09
Memory error
0A
0B-16
17
0000 0000
addresses not implemented, writes have no effect, reads return 0x00
DIE ID<7:0>
DIE ID<15:8>
18
19
DIE ID<23:16>
1A
1B
1C
1D
1E
1F
DIE ID<31:24>
DIE ID<39:32>
DIE ID<47:40>
DIE ID<55:48>
DIE ID<63:56>
Die revision indicator<7:0>
18
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Description of Serial Registers
Each register function is explained in detail below.
Table 6. Serial Register 0x00 (Read or Write)
Address (hex)
0x00
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Analog Gain Adjustment bits<11:4>
Defaults
0
0
0
0
0
0
0
0
BIT <7:0>
Analog gain adjustment (most significant 8 bits of a 12 bit word)
All 12-bits in this adjustment in address 0x00 and 0x01 set to 0000
0000 0000 = fullscale analog input 2.0VPP
All 12-bits in this adjustment in address 0x00 and 0x01 set to 1111
1111 1111 = fullscale analog input 1.52VPP
Step adjustment resolution is 120µV.
Can be used for one-time setting or continual calibration of analog
signal path gain.
Table 7. Serial Register 0x01 (Read or Write)
Address (hex)
0x01
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
3 or 4-pin SPI
0
BIT 2
SPI Reset
0
BIT 1
BIT 0
Analog Gain Adjustment bits<3:0>
0
0
0
0
Defaults
0
0
0
0
BIT <0:1>
RESERVED
0
1
set to 0 if writing this register
do not set to 1
BIT <2>
SPI Register Reset
0
1
altered register settings are kept
resets all SPI registers to defaults (self clearing)
BIT <3>
Set SPI mode to 3- or 4-pin
0
1
3-pin SPI (read/write on SDIO, SDO not used)
4-pin SPI (SDIO is write, SDO is read)
BIT <7:4>
Analog gain adjustment continued (least significant 4 bits of a
12-bit word)
All 12-bits in this adjustment in address 0x00 and 0x01 set to 0000
0000 0000 = fullscale analog input 2VPP
All 12-bits in this adjustment in address 0x00 and 0x01 set to 1111
1111 1111 = fullscale analog input 1.52VPP
Step adjustment resolution is 120µV.
Can be used for one-time setting or continual calibration of analog
signal path gain.
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BIT 0
Table 8. Serial Register 0x02 (Read or Write)
Address (hex)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Clock Divider
0
Single or
Dual Bus
0x02
Coarse Clock Phase Adjustment bits<4:0>
0
0
Defaults
0
0
0
0
0
0
BIT <0>
Single or Dual Bus Output Selection
dual bus output (A and B)
0
1
single bus output (A)
BIT <1>
Output Clock Divider
0
1
CLKOUT equals CLKIN divide by 4 (not available in single bus mode)
CLKOUT equals CLKIN divide by 2
BIT <2>
RESERVED
0
1
set to 0 if writing this register
do not set to 1
BIT <7:3>
Input Clock Coarse Phase Adjustment
Use as a coarse adjustment of input clock phase. The 5-bit adjustment
provides a step size of ~2.4ps across a range from code 00000 = 0 ps
to code 11111 = 73ps.
Table 9. Serial Register 0x03 (Read or Write)
Address (hex)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Analog Offset
bit<8>
0x03
Fine Clock Phase Adjustment bits<5:0>
0
0
Defaults
0
0
0
0
0
0
factory set
BIT <0>
Analog Offset control (most significant bit of 9-bit word)
All 9-bits in this adjustment in address 0x03 and 0x04 set to 0 0000
0000 = -30mV (TBD)
All 9-bits in this adjustment in address 0x03 and 0x04 set to 1 1111
1111 = +30mV (TBD)
Step adjustment resolution is 120µV (or 1/4 LSB). Adjustments can be
used for calibration of analog signal path offset (for instance offset
error induced outside of the ADC) or to match multiple ADC offsets.
The default setting for this register is factory set to provide ~0mV of
ADC offset in the output codes and is unique for each device.
BIT <1>
RESERVED
0
1
set to 0 if writing this register
do not set to 1
BIT <7:2>
Fine Clock Phase Adjustment
Use as a fine adjustment of the input clock phase. The 6-bit
adjustment provides a step resolution of ~116fs across a range from
code 000000 = 0ps to code 111111 = 7.4ps. Can be used in conjuction
with Coarse Clock Phase Adjustment in address 0x02.
20
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Table 10. Serial Register 0x04 (Read or Write)
Address (hex)
0x04
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Analog Offset Control bits<7:0>
factory set
Defaults
BIT <7:0>
Analog Offset control continued (least significant bits of 9-bit
word)
All 9-bits in this adjustment in address 0x03 and 0x04 set to 0 0000
0000 = -30mV (TBD)
All 9-bits in this adjustment in address 0x03 and 0x04 set to 1 1111
1111 = +30mV (TBD)
Step adjustment resolution is 120uV (or 1/4 LSB). Adjustments can be
used for calibration of analog signal path offset (for instance offset
error induced outside of the ADC) or to match multiple ADC offsets.
The default setting for this register is factory set to provide ~0mV of
ADC offset in the output codes and is unique for each device.
Performance of the ADC is not specified across the entire offset
control range. Some performance degradation is expected as larger
offsets are programmed.
Table 11. Serial Register 0x05 (Read or Write)
Address (hex)
BIT 7
BIT 6
BIT 5
reserved
1
BIT 4
Sync Mode
0
BIT 3
Data Format
0
BIT 2
Reference
0
BIT 1
BIT 0
Stagger
Output
0x05
Temp Sensor Powerdown
0
0
Defaults
0
0
0
BIT <0>
RESERVED
0
1
set to 0 if writing this register
do not set to 1
BIT <1>
Stagger Output Bus
0
1
Output bus A and B aligned
Output bus A and B staggered (see timing diagrams)
BIT <2>
Enable External Reference
Enable internal reference
Enable external reference
0
1
BIT <3>
Set Data Output Format
Enable offset binary
0
1
Enable two's complement
BIT <4>
Set Sync Mode
0
1
Disable data synchronization mode
Enable data synchronization mode
When enabled, the OVR pin(s) are replaced with SYNC output
signal(s). The SYNC output signal is time-aligned with the output data
matching the corresponding input sample and RESET input pulse
BIT <5>
RESERVED
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0
1
set to 1 if writing this register
BIT <6>
Powerdown
0
1
device active
device in low power mode (sleep mode)
BIT <7>
Temperature Sensor
0
1
temperature sensor inactive
temperature sensor active, independent of powerdown bit in Bit<6>,
allows reading of temp sensor while the rest of the ADC is in sleep
mode
Table 12. Serial Register 0x06 (Read or Write)
Address (hex)
0x06
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Data output mode
LVDS termination
LVDS current
Force LVDS outputs
Defaults
0
0
0
0
0
1
0
0
BIT <0:1>
00 and 01
10
Force LVDS outputs
normal operating mode (LVDS is outputting sampled data bits)
forces the LVDS outputs to all logic zeros (data and clock out) - for
level check
11
forces the LVDS outputs to all logic ones (data and clock out) - for
level check
BIT <3:2>
Set LVDS output current
2.5mA
00
01
10
11
3.5mA (default)
4.5mA
5.5mA
BIT <5:4>
Set Internal LVDS termination differential resistor (for LVDS
outputs only)
00 and 01
no internal termination
10
11
internal 200Ω resistor selected
internal 100Ω resistor selected
BIT <7:6>
Control Data Output Mode
00
01
10
11
normal mode (LVDS is outputting sampled data bits)
scrambled output mode (D11:D1 is XOR'd with D0)
output data is replaced with PRBS test pattern (7-bit sequence)
output data is replaced with toggling test pattern (all 1s, then all 0s,
then all 1s, etc.....on all bits)
22
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Table 13. Serial Register 0x08 (Read only)
Address (hex)
0x08
BIT 7
BIT 6
BIT 5
BIT 4
Die temperature bits<7:0>
depends on reading from temperature sensor
BIT 3
BIT 2
BIT 1
BIT 0
Defaults
BIT <7:0>
Die temperature readout
if enabled in register 0x05. To obtain the die temperature in Celsius,
convert the 8-bit word to decimal and subtract 78.
<7:0> = 0x00 = 00000000, measured temperature is 0-78 = -78°C
<7:0> = 0x73 = 01110011, measured temperature is 115 - 78 = 37°C
<7:0> = 0xAF, measured temperature is 175 - 78 = 97°C
Table 14. Serial Register 0x09 (Read only)
Address (hex)
0x09
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Memory error
0
000 0000
000 0000
Defaults
BIT <7:1>
RESERVED
set to 0 if writing this register
do not set to 1
BIT <0>
Memory Error Indicator
Registers 0x00 through 0x07 have multiple redundancy. If any copy
disagrees with the others, an error is flagged in this bit. This is for
systems that require the highest level of assurance that the device
remains programmed in the proper state and indication of an error if
something changes unexpectedly.
Table 15. Serial Register 0x0A (Read only)
Address (hex)
0x0A
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
0000 0000
0000 0000
BIT 2
BIT 1
BIT 0
Defaults
BIT <7:0>
RESERVED
set to 0 if writing this register
do not set to 1
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BIT 0
Table 16. Serial Register 0x17 through 0x1E (Read only)
Address (hex)
0x17 - 0x1E
Defaults
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Die ID
factory set
BIT <7:0>
Die Identification Bits
Each of these eight registers contains 8-bits of a 64-bit unique die
identifier.
Table 17. Serial Register 0x1F (Read only)
Address (hex)
0x1F
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Die Revision Number
factory set
Defaults
BIT <7:0>
Die revision
Provides design revision information.
24
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TYPICAL CHARACTERISTICS
Typical plots at TA = 25°C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 1.5-VPP differential clock, (unless otherwise noted)
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
FFT FOR 250-MHz INPUT SIGNAL
FFT FOR 0.9-GHz INPUT SIGNAL
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
ENOB = 9.45 Bits
SFDR = 75.4 dBc
SINAD = 58.7 dBFS
SNR = 58.8 dBFS
THD = 72.5 dBc
ENOB = 9.31 Bits
SFDR = 71.5 dBc
SINAD = 57.8 dBFS
SNR = 58.04 dBFS
THD = 69.8 dBc
0
50 100 150 200 250 300 350 400 450 500
f − Frequency − MHz
0
50 100 150 200 250 300 350 400 450 500
f − Frequency − MHz
G001
G002
Figure 8.
Figure 9.
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
FFT FOR 1.3-GHz INPUT SIGNAL
FFT FOR 1.7-GHz INPUT SIGNAL
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
ENOB = 9.01 Bits
SFDR = 63.5 dBc
SINAD = 56 dBFS
SNR = 57.1 dBFS
THD = 61.7 dBc
ENOB = 8.6 Bits
SFDR = 56.3 dBc
SINAD = 53.6 dBFS
SNR = 56.4 dBFS
THD = 55.8 dBc
0
50 100 150 200 250 300 350 400 450 500
f − Frequency − MHz
0
50 100 150 200 250 300 350 400 450 500
f − Frequency − MHz
G003
G004
Figure 10.
Figure 11.
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 1.5-VPP differential clock, (unless otherwise noted)
DIFFERENTIAL NONLINEARITY
INTEGRAL NONLINEARITY
2.0
1.5
1.0
0.8
A
f
= −0.05 dBFS
= 100.33 MHz
= 1 GSPS
A
f
= −0.05 dBFS
= 100.33 MHz
= 1 GSPS
IN
IN
IN
IN
f
S
f
S
0.6
1.0
0.4
0.5
0.2
0.0
0.0
−0.2
−0.4
−0.6
−0.8
−1.0
−0.5
−1.0
−1.5
−2.0
0
512 1024 1536 2048 2560 3072 3584 4096
ADC Output Code
0
512 1024 1536 2048 2560 3072 3584 4096
ADC Output Code
G006
G005
Figure 12.
Figure 13.
AC PERFORMANCE
vs
AC PERFORMANCE
vs
INPUT AMPLITUDE
(801.13-MHz INPUT SIGNAL)
INPUT AMPLITUDE
(247.5-MHz AND 252.5-MHz TWO-TONE INPUT SIGNAL)
100
80
60
40
20
0
120
2F2−F1 (dBFS)
2F1−F2 (dBFS)
SFDR (dBFS)
100
SNR (dBFS)
SFDR (dBc)
80
Worst Spur (dBFS)
60
SNR (dBc)
Worst Spur (dBc)
40
20
0
f
f
= 801.13 MHz
= 1 GSPS
f
f
f
= 1 GSPS
IN
S
= 247.5 MHz
S
IN1
IN2
16k FFT
= 252.5 MHz
−20
−90 −80 −70 −60 −50 −40 −30 −20 −10
0
−87 −77 −67 −57 −47 −37 −27 −17
−7
Input Amplitude − dBFS
Input Amplitude − dBFS
G007
G019
Figure 14.
Figure 15.
26
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 1.5-VPP differential clock, (unless otherwise noted)
AC PERFORMANCE
AC PERFORMANCE
vs
vs
INPUT AMPLITUDE
INPUT AMPLITUDE
(747.5-MHz AND 752.5-MHz TWO-TONE INPUT SIGNAL)
(1197.5-MHz AND 1202.5-MHz TWO-TONE INPUT SIGNAL)
120
120
2F1−F2 (dBFS)
2F2−F1 (dBFS)
2F2−F1 (dBFS)
2F1−F2 (dBFS)
100
100
80
80
Worst Spur (dBFS)
Worst Spur (dBFS)
60
60
Worst Spur (dBc)
Worst Spur (dBc)
40
20
0
40
20
0
f
f
f
= 1 GSPS
f
f
f
= 1 GSPS
S
S
= 747.5 MHz
= 752.5 MHz
= 1197.5 MHz
= 1202.5 MHz
IN1
IN2
IN1
IN2
−87 −77 −67 −57 −47 −37 −27 −17
−7
−87 −77 −67 −57 −47 −37 −27 −17
−7
Input Amplitude − dBFS
Input Amplitude − dBFS
G020
G021
Figure 16.
Figure 17.
SFDR
SNR
vs
vs
AVDD5 ACROSS TEMPERATURE
AVDD5 ACROSS TEMPERATURE
60.0
80
78
76
74
72
70
T
= 0°C
A
T
A
= 0°C
T
= 25°C
A
T
A
= −40°C
T
A
= −20°C
T
= −20°C
A
59.5
59.0
58.5
58.0
57.5
57.0
T
A
= 25°C
T
A
= 55°C
T
A
= 85°C
T
= −40°C
A
T
= 55°C
A
T
A
= 85°C
T
A
= 100°C
T
A
= 100°C
f = 100.33 MHz
IN
f = 1 GSPS
S
f
f
= 100.33 MHz
= 1 GSPS
IN
S
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
AV − Supply Voltage − V
AV − Supply Voltage − V
DD
DD
G008
G009
Figure 18.
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 1.5-VPP differential clock, (unless otherwise noted)
SFDR
SNR
vs
vs
AVDD3 ACROSS TEMPERATURE
AVDD3 ACROSS TEMPERATURE
80
78
76
74
72
70
60
59
58
57
56
T
= 0°C
T
= −20°C
T
= 25°C
A
A
A
T
= −40°C
A
T
= 25°C
A
T
= 0°C
A
T
= 55°C
= 85°C
A
T
A
T
= −20°C
A
T
A
= 100°C
T
= 55°C
A
T
= 100°C
A
T
= 85°C
A
T
= −40°C
A
f
f
= 100.33 MHz
= 1 GSPS
f
IN
f
S
= 100.33 MHz
= 1 GSPS
IN
S
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
AV − Supply Voltage − V
AV − Supply Voltage − V
DD
DD
G010
G011
Figure 20.
Figure 21.
SFDR
vs
SNR
vs
DVDD3 ACROSS TEMPERATURE
DVDD3 ACROSS TEMPERATURE
60.0
59.5
59.0
58.5
58.0
57.5
57.0
80
78
76
74
72
70
T
= 0°C
T
= −40°C
A
T
= −20°C
A
A
T
A
= −20°C
T
= 25°C
A
T
= −40°C
T
= 0°C
A
A
T
= 25°C
A
T
A
= 55°C
T
A
= 85°C
T
= 55°C
A
T
A
= 100°C
T
A
= 85°C
T
= 100°C
A
f
f
= 100.33 MHz
= 1 GSPS
f
IN
f
S
= 100.33 MHz
= 1 GSPS
IN
S
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
DV − Supply Voltage − V
DV − Supply Voltage − V
DD
DD
G012
G013
Figure 22.
Figure 23.
28
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 1.5-VPP differential clock, (unless otherwise noted)
SNR vs INPUT FREQUENCY AND SAMPLING FREQUENCY
1000
59
58
56
900
800
700
600
500
400
300
200
57
56
59
58
57
59
58
57
55
56
10
200
400
600
800
1000
1200
1400
1600
1800
2000 2100
60
fIN – Input Frequency – MHz
56
52
53
54
55
57
58
59
SNR – dBFS
M0048-30
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 1.5-VPP differential clock, (unless otherwise noted)
SFDR vs INPUT FREQUENCY AND SAMPLING FREQUENCY
1000
60
65
70
55
900
800
700
600
500
400
300
200
75
70
60
55
75
65
75
55
65
60
70
10
200
400
600
800
1000
1200
1400
1600
1800
2000 2100
80
fIN – Input Frequency – MHz
65
50
55
60
70
75
SFDR – dBc
M0049-30
Figure 25.
NORMALIZED GAIN RESPONSE
vs
INPUT FREQUENCY
2
0
−2
−4
−6
−8
−10
f
S
= 1 GSPS
Measurement every 50 MHz
−12
10M
100M
1G
5G
f
IN
− Input Frequency − Hz
G018
Figure 26.
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APPLICATION INFORMATION
Theory of Operation
The ADS5400 is a 12-bit, 1-GSPS, monolithic pipeline ADC. Its bipolar transistor analog core operates from 5-V
and 3.3-V supplies, while the output uses a 3.3-V supply to provide LVDS-compatible digital outputs. The
conversion process is initiated by the falling edge of the external input clock. At the sampling instant, the
differential input signal is captured by the input track-and-hold (T&H), and the input sample is sequentially
converted by a series of lower resolution stages, with the outputs combined in a digital correction logic block.
Both the rising and the falling clock edges are used to propagate the sample through the pipeline every half clock
cycle. This process results in a data latency of 7 - 8.5 clock cycles (output mode dependent), after which the
output data is available as a 12-bit parallel word, coded in offset binary or two's complement format.
The user can select to accept the data at the full sample rate using one bus (bus A, latency 7 cycles), or
demultiplex the data into two buses (bus A and B, latency 7.5 or 8.5 cycles) at half rate. A serial peripheral
interface (SPI) is provided for adjusting operational modes, as well as for calibrations of analog gain, analog
offset and clock phase for inter-leaving multiple ADS5400. Die temperature readout using the SPI is provided.
SYNC and RESET modes exist for synchronizing output data across multiple ADS5400.
Input Configuration
The analog input for the ADS5400 consists of an analog pseudo-differential buffer followed by a bipolar transistor
track-and-hold (see Figure 27). The integrated analog buffer isolates the source driving the input of the ADC from
sampling glitches on the T&H and allows for the integration of a 100-Ω differential input resistor. The input
common mode is set internally through a 500-Ω resistor connected from half of the AVDD5 supply voltage to
each of the inputs. The parasitic package capacitance shown is with the package unsoldered. Once soldered,
depending on the board characteristics, one can expect another ~1pF at the analog input pins, which is board
dependent.
ADS5400
AVDD5
Bipolar
Transistor
Buffer
~5.25 nH Bond Wire
AINP
~0.3 pF
Package
~0.2 pF
Bondpad
0.3 pF
500 W
500 W
Sample and
Hold
Analog
Inputs
1st Stage
Of Pipeline
112 W
AGND
2.5 V
AVDD5
AGND
Bipolar
0.3 pF
~5.25 nH Bond Wire
AINN
~0.3 pF
Package
~0.2 pF
Bondpad
Transistor
Buffer
AGND
Figure 27. Analog Input Equivalent Circuit
For a full-scale differential input, each of the differential lines of the input signal swing symmetrically between 2.5
V + 0.5 V and 2.5 V – 0.5 V. This means that each input has a maximum signal swing of 1 VPP for a total
differential input signal swing of 2 VPP. The maximum fullscale range can be programmed from 1.5-2Vpp using
the SPI. The maximum swing is determined by the internal reference voltage generator and the fullscale range
set using the SPI, eliminating the need for any external circuitry for this purpose. The analog gain adjustment has
a resolution of 12-bits across the 1.5-2VPP range, providing for fine calibration of analog gain mismatches across
multiple ADS5400 signal chains, primarily for interleaving.
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The ADS5400 obtains optimum performance when the analog inputs are driven differentially. The circuit in
Figure 28 shows one possible configuration using an RF transformer. Datasheet performance, especially at
>1GHz input frequency, can only be obtained with a carefully designed differential drive path to the ADC.
Z
R
0
0
50 W
50 W
AIN
R
100 W
AC Signal
Source
ADS5400
AIN
1:1
Figure 28. Converting a Single-Ended Input to a Differential Signal Using an RF Transformer
Voltage Reference
The 2V voltage reference is provided internal to the ADS5400. A VCM (voltage common mode) pin is provided
as an output for use in dc-coupled applications, equal to the AVDD5 supply divided by 2. This provides the
analog input common mode voltage to a driving circuit so that the common mode is setup properly. Some
systems may prefer the use of an external voltage reference. This mode can be enabled by pulling the
ENEXTREF pin high. In this mode, an external reference can be driven onto the VREF pin, which is normally
expecting 2V.
Analog Input Over-Range Recovery Error
An over-range condition occurs if the analog input voltage exceeds the full-scale range of the converter (0dBFS).
To test recovery from an over-range, the ADC analog input is injected with a sinusoidal input frequency exactly at
CLKIN/4 (a four-point sinusoid at the digital outputs). The four sample points of each period occur at the top,
mid-scale, bottom and mid-scale of the sinusoid (clipped by the ADC when over-ranged to all 0s or all 1s). Once
the amplitude exceeds 0dBFS, the top and bottom of the sinusoidal input becomes out of range, while the
mid-scale point is always in-range and measureable with ADC output codes. The graph in Figure 29 indicates the
amount of error from the expected mid-scale value of 2048 that occurs after negative over-range (bottom of
sinusoid) and positive over-range (top of sinusoid). This equates to the amount of error in a valid sample 1 clock
cycle after an over-range occurs, as a function of input amplitude.
25
After Positive
Over-range
200MSPS (5ns)
After Positive
Over-range
1GSPS (1ns)
20
15
After Negative
Over-range
400MSPS (2.5ns)
10
5
0
−5
−10
−15
−20
−25
After Positive
Over-range
400MSPS (2.5ns)
After Negative
Over-range
200MSPS (5ns)
After Negative
Over-range
1GSPS (1ns)
−1
0
1
2
3
4
5
6
Analog Input Amplitude − dBFS
G023
Figure 29. Recovery Error 1 Clock Cycle After Over-Range vs Input Amplitude
32
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Clock Inputs
The ADS5400 clock input can be driven with either a differential clock signal or a single-ended clock input. The
equivalent clock input circuit can be seen in Figure 30. In low-input-frequency applications, where jitter may not
be a big concern, the use of a single-ended clock (as shown in Figure 31) could save cost and board space
without much performance tradeoff. When clocked with this configuration, it is best to connect CLK to ground
with a 0.01-mF capacitor, while CLK is ac-coupled with a 0.01-mF capacitor to the clock source, as shown in
Figure 31.
ADS5400
AVDD5
~5.25 nH Bond Wire
10 W
CLKINP
~0.2 pF
Bondpad
~0.35 pF
Package
400 W
200 W
0.25 pF
Internal
Clock
Buffer
AVDD5V/2
GND
AVDD5
0.25 pF
GND
~5.25 nH Bond Wire
400 W
CLKINN
10 W
~0.2 pF
Bondpad
~0.35 pF
Package
GND
Figure 30. Clock Input Circuit
Square Wave or
Sine Wave
CLK
0.01 mF
0.01 mF
ADS5400
CLK
Figure 31. Single-Ended Clock
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65
60
55
50
45
40
80
f
= 10.05 MHz
IN
f
= 10.05 MHz
f
= 100.33 MHz
IN
IN
75
70
65
60
55
50
45
40
f
= 601.13 MHz
IN
f
IN
= 1498.5 MHz
f
IN
= 801.13 MHz
f
IN
= 100.33 MHz
f
= 1498.5 MHz
f
IN
= 801.13 MHz
IN
f
= 601.13 MHz
IN
f
S
= 1 GSPS
f
S
= 1 GSPS
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Clock Amplitude − V
Clock Amplitude − V
P−P
P−P
G014
G015
Figure 32. ADS5400 SFDR vs Differential Clock
Level
Figure 33. ADS5400 SNR vs Differential Clock
Level
The characterization of the ADS5400 is typically performed with a 1.5 VPP differential clock, but the ADC
performs well with a differential clock amplitude down to ~400mVPP (200mV swing on both CLK and CLK), as
shown in Figure 32 and Figure 33. For jitter-sensitive applications, the use of a differential clock has some
advantages at the system level and is strongly recommended. The differential clock allows for common-mode
noise rejection at the printed circuit board (PCB) level. With a differential clock, the signal-to-noise ratio of the
ADC is better for jitter-sensitive, high-frequency applications because the board level clock jitter is superior.
Larger clock amplitude levels are recommended for high analog input frequencies or slow clock frequencies. At
high analog input frequencies, the sampling process is sensitive to jitter. At slow clock frequencies, a small
amplitude sinusoidal clock has a lower slew rate and can create jitter-related SNR degradation due to the
uncertainty in the sampling point associated with a slow slew rate. Figure 34 demonstrates a recommended
method for converting a single-ended clock source into a differential clock; it is similar to the configuration found
on the evaluation board and was used for much of the characterization. See also Clocking High Speed Data
Converters (SLYT075) for more details.
0.1 mF
Clock
CLK
Source
ADS5400
CLK
Figure 34. Differential Clock
The common-mode voltage of the clock inputs is set internally to 2.5 V using internal 400Ω resistors (see
Figure 30). It is recommended to use ac coupling in the clock path, but if this scheme is not possible, the
ADS5400 features good tolerance to clock common-mode variation, as shown in Figure 35 and Figure 36. The
internal ADC core uses both edges of the clock for the conversion process. Ideally, a 50% duty-cycle clock signal
should be provided.
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80
65
60
55
50
45
40
f
= 901.13 MHz
f
= 100.33 MHz
IN
IN
75
70
65
60
55
50
45
40
f
IN
= 601.13 MHz
f
IN
= 100.33 MHz
f
= 601.13 MHz
= 1498.5 MHz
IN
f
IN
= 1498.5 MHz
f
IN
f
IN
= 901.13 MHz
f
S
= 1 GSPS
0.5
f
= 1 GSPS
0.5
S
0.0
1.0
1.5
2.0
2.5
3.0
3.5
0.0
1.0
1.5
2.0
2.5
3.0
3.5
Clock Common Mode − V
Clock Common Mode − V
G016
G017
Figure 35. ADS5400 SFDR vs Clock Common Mode Figure 36. ADS5400 SNR vs Clock Common Mode
To understand how to determine the required clock jitter, an example is useful. The ADS5400 is capable of
achieving 58.7 dBFS SNR at 850 MHz of analog input frequency. To achieve SNR at 850 MHz, the external
clock source rms jitter must be at least 210fs when combined with the 125fs of internal aperture jitter in order for
the total rms jitter to be 244fs. A summary of maximum recommended rms clock jitter as a function of analog
input frequency is provided in Table 18 (using 125fs of internal aperture jitter). The equations used to create the
table are also presented.
Table 18. Recommended RMS Clock Jitter
INPUT FREQUENCY
(MHz)
MEASURED SNR
(dBc)
TOTAL JITTER
(fs rms)
MAXIMUM EXT CLOCK JITTER
(fs rms)
125
600
58.1
57.8
57.7
56.6
54.7
1585
318
244
196
172
1580
342
210
151
119
850
1200
1700
Equation 1 and Equation 2 are used to estimate the required clock source jitter.
SNR (dBc) = -20 x LOG10 (2 x p x fIN x jTOTAL
)
(1)
(2)
2
1/2
jTOTAL = (jADC2 + jCLOCK
)
where:
jTOTAL = the rms summation of the clock and ADC aperture jitter;
jADC = the ADC internal aperture jitter which is located in the data sheet;
jCLOCK = the rms jitter of the clock at the clock input pins to the ADC; and
fIN = the analog input frequency.
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Notice that the SNR is a strong function of the analog input frequency, not the clock frequency. The slope of the
clock source edges can have a mild impact on SNR as well and is not taken into account for these estimates.
For this reason, maximizing clock source amplitudes at the ADC clock inputs is recommended, though not
required (faster slope is desirable for jitter-related SNR). For more information on clocking high-speed ADCs, see
Application Note SLWA034, Implementing a CDC7005 Low Jitter Clock Solution For High-Speed, High-IF ADC
Devices. Recommended clock distribution chips (CDCs) are the TI CDC7005 and CDCM7005. Depending on the
jitter requirements, a band pass filter (BPF) is sometimes required between the CDC and the ADC. If the
insertion loss of the BPF causes the clock amplitude to be too low for the ADC, or the clock source amplitude is
too low to begin with, an inexpensive amplifier can be placed between the CDC and the BPF.
Figure 37 represents a scenario where an LVPECL output is used from a TI CDCM7005 with the clock signal
path optimized for maximum amplitude and minimum jitter. The jitter of this setup is difficult to estimate and
requires a careful phase noise analysis of the clock path. The BPF (and possibly a low-cost amplifier because of
insertion loss in the BPF) can improve the jitter between the CDC and ADC when the jitter provided by the CDC
is still not adequate. The total jitter at the CDCM7005 output depends heavily on the phase noise of the VCXO
selected. If it is determined that the jitter from the CDCM7005 with a VCXO is sufficient without further
conditioning, it is possible to clock the ADS5400 directly from the CDCM7005 using differential LVPECL outputs
(see the CDCM7005 data sheet for the exact schematic). A careful analysis of the required jitter and of the
components involved is recommended before determining the proper approach.
Low Jitter Clock Distribution
Board Master
AMP and /or BPF optional , depending on jitter requirements
Reference Clock
(High or Low Jitter)
10 MHz
REF
CLKIN
CLKIN
LVPECL
AMP
SAW
XFMR
1000 MHz
ADC
1000 MHz (To Transmit DAC)
125 MHz (To DSP )
TI ADS5400
LVPECL
or
Low Jitter Oscillator
1000 MHz
LVCMOS
250 MHz (To FPGA )
To Other
CDC
VCO
(Clock Distribution Chip)
Ex : TI CDCM7005
This is a general block diagram example: Consult the datasheet of the CDCM7005 for proper schematic
and for specifications regarding allowable input and output frequency and amplitude ranges.
Figure 37. Clock Source Diagram
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Digital Outputs
Output Bus and Clock Options
The ADS5400 has two buses, A and B. Using register 0x02, a single or dual bus output can be selected. In
single-bus mode, bus A is used at the full clock rate, while in two-bus mode, data is multiplexed at half the clock
rate on A and B. While in single bus mode, CLKOUTA will be at frequency CLKIN/2 and a DDR interface is
achieved. In two-bus mode, CLKOUTA/CLKOUTB can be either at frequency CLKIN/2 or CLKIN/4, providing
options for an SDR or DDR interface. The ADC provides 12 LVDS-compatible data outputs (D11 to D0; D11 is
the MSB and D0 is the LSB), a data-ready signal (CLKOUT), and an over-range indicator (OVR) on each bus. It
is recommended to use the CLKOUT signal to capture the output data of the ADS5400. Both two's complement
and offset binary are available output formats, in register 0x05.
The capacitive loading on the digital outputs should be minimized. Higher capacitance shortens the data-valid
timing window. The values given for timing were obtained with an estimated 3.5-pF of differential parasitic board
capacitance on each LVDS pair.
Reset and Synchronization
Referencing the timing diagrams starting in Figure 1, the polarity of CLKOUT with respect to the sample N data
output transition is undetermined because of the unknown startup logic level of the clock divider that generates
the CLKOUT signal, whether in frequency CLKIN/2 or CLKIN/4 mode. The polarity of CLKOUT could invert when
power is cycled off/on. If a defined CLKOUT polarity is required, the RESET input pins are used to reset the
clock divider to a known state after power on with a reset pulse. A RESET is not commonly required when using
only one ADS5400 because a one sample uncertainty at startup is not usually a problem.
NOTE: initial samples capture RESET = HIGH on the rising edge of CLKINP. This is being corrected for final
samples and will reflect the diagram as drawn, with RESET = HIGH captured on falling edge of CLKINP.
In addition to CLKOUT alignment using RESET, a synchronization mode is provided in register 0x05. In this
mode, the OVR output becomes the SYNCOUT. The SYNCOUT will indicate which sample was present when
the RESET input pulse was captured in a HIGH state. The OVR indicator is not available when sync mode is
enabled. In single bus mode, only SYNCOUTA is used. In dual bus mode, only SYNCOUTB is used.
LVDS
Differential source loads of 100Ω and 200Ω are provided internal to the ADS5400 and can be implemented using
register 0x06 (as well as no internal load). Normal LVDS operation expects 3.5mA of current, but alternate values
of 2.5, 4.5, and 5.5mA are provided to save power or improve the LVDS signal quality when the environment
provides excessive loading.
Over Range
The OVR output equals a logic high when the 12-bit output word attempts to exceed either all 0s or all 1s. This
flag is provided as an indicator that the analog input signal exceeded the full-scale input limit set in register 0x00
and 0x01 (± gain error). The OVR indicator is provided for systems that use gain control to keep the analog input
signal within acceptable limits. The OVR pins are not available when the sychronization mode is enabled, as they
become the SYNCOUT indicator.
Data Scramble
In normal operation, with this mode disabled, the MSBs have similar energy to the analog input fundamental
frequency and can in some instances cause board interference. A data scramble mode is available in register
0x06. In this mode, bits 11-1 are XOR'd with bit 0 (the LSB). Because of the random nature of the LSB, this has
the effect of randomizing the data pattern. To de-scramble, perform the opposite operation in the digital chip after
receiving the scrambled data.
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Test Patterns
Determining the closure of timing or validating the digital interface can be difficult in normal operation. Therefore,
test patterns are available in register 0x06. One pattern toggles the outputs between all 1s and all 0s. Another
pattern generates a 7-bit PRBS (pseudo-random bit sequence).
In dual bus mode, the toggle mode could be in the same phase on bus A and B (bus A and B outputting 1s or 0s
together), or could be out of phase (bus A outputting 1s while bus B outputs 0s). The start phase cannot be
controlled.
The PRBS output sequence is a standard 27-1 pseudo-random sequence generated by a feedback shift register
where the two last bits of the shift register are exclusive-OR’ed and fed back to the first bit of the shift register.
The standard notation for the polynomial is x7 + x6 + 1. The PRBS generator is not reset, so there is no initial
position in the sequence. The pattern may start at any position in the repeating 127-bit long pattern and the
pattern repeats as long as the PRBS mode is enabled. The data pattern from the PRBS generator is used for all
of the LVDS parallel outputs, so when the pattern is ‘1’ then all of the LVDS outputs are outputting ‘1’ and when
the pattern is ‘0’ then all of the LVDS drivers output ‘0’. To determine if the digital interface is operating properly
with the PRBS sequence, the user must generate the same sequence in the receiving device, and do a
shift-and-compare until a matching sequence is confirmed.
Die Identification and Revision
A unique 64-bit die indentifier code can be read from registers 0x17 through 0x1E. An 8-bit die revision code is
available in register 0x1F.
Die Temperature Sensor
In register 0x05, the die temperature sensor can be enabled. The sensor is power controlled independently of
global powerdown, so that it and the SPI can be used to monitor the die temperature even when the remainder
of the ADC is in sleep mode. Register 0x08 is used to read values which can be mapped to the die temperature.
The exact mapping is detailed in the register map. Care should be taken not to exceed a maximum die
temperature of 150°C for prolonged periods of time in order to maintain the life of the device.
Interleaving
Gain Adjustment
A signal gain adjustment is available in registers 0x00 and 0x01. The allowable fullscale range for the ADC is
1.52 - 2VPP and can be set with 12-bit adjustment resolution across this range. For equal up/down gain
adjustment of the system and ADC gain mismatches, a nominal starting point of 1.75VPP could be programmed,
in which case ±250mV of adjustment range would be provided.
Offset Adjustment
Analog offset adjustment is available in register 0x03 and 0x04. This provides ±30mV of adjustment range with
9-bit adjustment resolution of 120uV per step. At production test, the default code for this register setting is set to
a value that provides 0mV of ADC offset. For optimum spectral performance, it is not recommended to use more
than ±8mV adjustment from the default setting
Input Clock Coarse Phase Adjustment
Coarse adjustment is available in register 0x02. The typical range is approximately 73 ps with a resolution of
2.4ps.
Input Clock Fine Phase Adjustment
Fine adjustment is available in register 0x03. The typical range is approximately 7.4 ps with a resolution of 116fs.
38
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Power Supplies
The ADS5400 uses three power supplies. For the analog portion of the design, a 5-V and 3.3-V supply (AVDD5
and AVDD3) are used, while the digital portion uses a 3.3-V supply (DVDD3). The use of low-noise power
supplies with adequate decoupling is recommended. Linear supplies are preferred to switched supplies; switched
supplies generate more noise components that can be coupled to the ADS5400. The PSRR value and the plot
shown in Figure 38 were obtained without bulk supply decoupling capacitors. When bulk (0.1 mF) decoupling
capacitors are used, the board-level PSRR is much higher than the stated value for the ADC. The power
consumption of the ADS5400 does not change substantially over clock rate or input frequency as a result of the
architecture and process.
100
90
DVDD3
80
70
60
50
40
AVDD5
30
AVDD3
20
10
0
0.01
0.1
1
10
100
Frequency − MHz
G022
Figure 38. PSRR versus Supply Injected Frequency
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Layout Information
The evaluation board provides a guideline of how to lay out the board to obtain the maximum performance from
the ADS5400. General design rules, such as the use of multilayer boards, single ground plane for ADC ground
connections, and local decoupling ceramic chip capacitors, should be applied. The input traces should be
isolated from any external source of interference or noise, including the digital outputs as well as the clock
traces. The clock signal traces should also be isolated from other signals, especially in applications where low
jitter is required like high IF sampling. Besides performance-oriented rules, care must be taken when considering
the heat dissipation of the device. The thermal heat sink should be soldered to the board as described in the
PowerPad Package section. See ADS5400 EVM User Guide (SLAU293) on the TI Web site for the evaluation
board schematic.
PowerPAD™ Package
The PowerPAD package is a thermally enhanced standard-size IC package designed to eliminate the use of
bulky heatsinks and slugs traditionally used in thermal packages. This package can be mounted using standard
printed circuit board (PCB) assembly techniques, and can be removed or replaced using standard repair
procedures.
The PowerPAD package is designed so that the leadframe die pad (or thermal pad) is exposed on the bottom of
the IC. This provides an extremely low thermal resistance path between the die and the exterior of the package.
The thermal pad on the bottom of the IC can then be soldered directly to the printed circuit board (PCB), using
the PCB as a heatsink.
Assembly Process
1. Prepare the PCB top-side etch pattern including etch for the leads as well as the thermal pad as illustrated in
the Mechanical Data section.
2. It is recommended to place a 9 x 9 array of 13-mil-diameter (0.33mm) via holes under the package, with the
middle 5 x 5 array of thermal vias exposed.
3. Connect all holes (both those inside and outside the thermal pad area) to an internal copper plane (such as a
ground plane).
4. Do not use the typical web or spoke via-connection pattern when connecting the thermal vias to the ground
plane. The spoke pattern increases the thermal resistance to the ground plane.
5. The top-side solder mask should leave exposed the terminals of the package and the 5 x 5 via array thermal
pad area (6 mm x 6 mm).
6. Cover the entire bottom side of the PowerPAD vias to prevent solder wicking.
7. Apply solder paste to the exposed thermal pad area and all of the package terminals.
For more detailed information regarding the PowerPAD package and its thermal properties, see either the
PowerPAD Made Easy application brief (SLMA004) or the PowerPAD Thermally Enhanced Package application
report (SLMA002).
40
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DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the
low-frequency value
Aperture Delay
The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling
occurs
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay
Clock Pulse Duration/Duty Cycle
The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse
duration) to the period of the clock signal, expressed as a percentage.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. DNL is the deviation
of any single step from this ideal value, measured in units of LSB.
Common-Mode Rejection Ratio (CMRR)
CMRR measures the ability to reject signals that are presented to both analog inputs simultaneously. The
injected common-mode frequency level is translated into dBFS, the spur in the output FFT is measured in dBFS,
and the difference is the CMRR in dB.
Effective Number of Bits (ENOB)
ENOB is a measure in units of bits of a converter's performance as compared to the theoretical limit based on
quantization noise
ENOB = (SINAD – 1.76)/6.02
(3)
Gain Error
Gain error is the deviation of the ADC actual input full-scale range from its ideal value, given as a percentage of
the ideal input full-scale range.
Integral Nonlinearity (INL)
INL is the deviation of the ADC transfer function from a best-fit line determined by a least-squares curve fit of that
transfer function. The INL at each analog input value is the difference between the actual transfer function and
this best-fit line, measured in units of LSB.
Offset Error
Offset error is the deviation of output code from mid-code when both inputs are tied to common-mode.
Power-Supply Rejection Ratio (PSRR)
PSRR is a measure of the ability to reject frequencies present on the power supply. The injected frequency level
is translated into dBFS, the spur in the output FFT is measured in dBFS, and the difference is the PSRR in dB.
The measurement calibrates out the benefit of the board supply decoupling capacitors.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at dc
and in the first five harmonics.
P
10
P
S
SNR + 10log
N
(4)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s
full-scale range.
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Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components
including noise (PN) and distortion (PD), but excluding dc.
P
S
SINAD + 10log
10
P
) P
N
D
(5)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s
full-scale range.
Temperature Drift
Temperature drift (with respect to gain error and offset error) specifies the change from the value at the nominal
temperature to the value at TMIN or TMAX. It is computed as the maximum variation the parameters over the whole
temperature range divided by TMIN – TMAX
.
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS) to the power of the first five harmonics (PD).
P
10
P
S
THD + 10log
D
(6)
THD is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion (IMD3)
IMD3 is the ratio of the power of the fundamental (at frequencies f1, f2) to the power of the worst spectral
component at either frequency 2f1 – f2 or 2f2 – f1). IMD3 is given in units of either dBc (dB to carrier) when the
absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the
fundamental is extrapolated to the converter’s full-scale range.
SPACER
REVISION HISTORY
Changes from Original (October 2009) to Revision A
Page
•
•
•
Changed the FEATURES list ................................................................................................................................................ 1
Changed Abs Max, Recommended Op Conditions, and Electrical Specs values. ............................................................... 2
Changed the description of the ANALOG INPUT entry in the Rec Op Condition table From: Differential input range
To: Full-scale differential input range .................................................................................................................................... 3
•
•
Changed the Rec Op table, VCM - TYP value From: 2.5V To AVDD5/2 ............................................................................... 3
Changed the description of the ANALOG INPUT entry in the Elect Char table From: Differential input range To:
Full-scale differential input range .......................................................................................................................................... 3
•
•
•
•
•
•
•
•
•
Changed the Elect Char table, VCM - TYP value From: 2.5V To AVDD5/2 .......................................................................... 3
Changed the Timing Diagrams illustrations .......................................................................................................................... 9
Changed Figure 1 ................................................................................................................................................................. 9
Changed Figure 2 ............................................................................................................................................................... 10
Changed Figure 3 ............................................................................................................................................................... 11
Changed Figure 4 ............................................................................................................................................................... 12
Changed Figure 5 ............................................................................................................................................................... 13
Deleted text "Internal pull-down resistor" from the SCLK, SDIO, and SDO pins in the Pin Functions table ...................... 15
Changed the SDENB pin text From: "Internal pull-up resistor" To: "Internal 100kΩ pull-up resisto" in the Pin
Functions table .................................................................................................................................................................... 15
•
•
•
•
Added Note to the Pin Functions table - This pin contains an internal ~40kΩ pull-down resistor, to ground. ................... 15
Changed Table 8 BIT <7:3>, Title and description ............................................................................................................. 20
Changed Table 9 BIT <0>, Default setting description, and BIT <7:2> description ........................................................... 20
Changed Table 10 BIT <0>, Default setting description ..................................................................................................... 21
42
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•
•
Changed Serial Register 0x06 (Read or Write) (Table 12). Bits 4 and 5 From TBD To: 0 ................................................ 22
Deleted Table 12 description comment from BIT <7:6> 11: (this mode is not working properly on early samples - will
be fixed) .............................................................................................................................................................................. 22
•
Changed the TYPICAL CHARACTERISTICS, Conditions Note From: DVDD3 = 3.3 V, and 3.3-VPP differential clock
To: DVDD = 3.3V and 1.5 VPP differential clock ................................................................................................................. 25
•
•
•
•
•
•
Added subsection - Analog Input Over-Range Recovery Error .......................................................................................... 32
Changed the Clock Inputs subsection ................................................................................................................................ 33
Changed the Test Patterns subsection ............................................................................................................................... 38
Changed the Interleaving subsection ................................................................................................................................. 38
Changed the Power Supplies subsection ........................................................................................................................... 39
Added Figure 38 - Was TBD .............................................................................................................................................. 39
Changes from Revision A (November 2009) to Revision B
Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Changed Data sheet From: Product Preview To: Production ............................................................................................... 1
Changed INL - Integral non- linearity error Max value From: 4 To: 4.5 ................................................................................ 3
Changed Worst harmonic/spur (other than HD2 and HD3), fIN = 1200 MHz TYP value From: 70 To 66 ............................ 5
Changed Worst harmonic/spur (other than HD2 and HD3), fIN = 1700 MHz TYP value From: 66 To 64 ............................ 5
Changed Total Harmonic Distortion, fIN = 125 MHz TYP value From: 73.5 To 71.7 ............................................................ 5
Changed Total Harmonic Distortion, fIN = 600 MHz TYP value From: 68.5 To 67 ............................................................... 5
Changed Total Harmonic Distortion, fIN = 850 MHz TYP value From: 68.5 To 66.5 ............................................................ 5
Changed Total Harmonic Distortion, fIN = 1700 MHz TYP value From: 56.2 To 55.7 .......................................................... 5
Changed Signal-to-noise and distortion, fIN = 125 MHz TYP value From: 58 To 58.5 ......................................................... 5
Changed Signal-to-noise and distortion, fIN = 600 MHz TYP value From: 57.4 To 58.2 ...................................................... 5
Changed Signal-to-noise and distortion, fIN = 850 MHz TYP value From: 57.3 To 57.8 ...................................................... 5
Changed Signal-to-noise and distortion, fIN = 1200 MHz TYP value From: 57.2 To 57.5 .................................................... 5
Changed Signal-to-noise and distortion, fIN = 1700 MHz TYP value From: 54 To 54.2 ....................................................... 5
Changed Effective number of bits (using SINAD in dBFS), fIN = 125 MHz TYP value From: 9.34 To 9.42 ......................... 5
Changed Effective number of bits (using SINAD in dBFS), fIN = 600 MHz TYP value From: 9.24 To 9.37 ......................... 5
Changed Effective number of bits (using SINAD in dBFS), fIN = 850 MHz TYP value From: 9.23 To 9.3 ........................... 5
Changed INPUT CLOCK COARSE PHASE ADJUSTMENT, Integral Non-Linearity error Max value From: 4 To 5 ........... 8
Changed Table 7, BIT 4 From: 1 To: 0 ............................................................................................................................... 19
Deleted note: (was not available on early samples) from SPI Register Reset in Table 7 .................................................. 19
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PACKAGE OPTION ADDENDUM
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23-Apr-2010
PACKAGING INFORMATION
Orderable Device
ADS5400IPZP
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
HTQFP
PZP
100
90 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
ADS5400IPZPR
HTQFP
PZP
100
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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