ADS5423IPGP [TI]
14 位、80MSPS 模数转换器 (ADC) | PGP | 52 | -40 to 85;
| 型号： | ADS5423IPGP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 14 位、80MSPS 模数转换器 (ADC) | PGP | 52 | -40 to 85 转换器 模数转换器 |
| 文件： | 总24页 (文件大小：1362K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS5423
www.ti.com
SLWS160 − FEBRUARY 2005
14 Bit, 80 MSPS
Analog-to-Digital Converter
D
52 Pin HTQFP Package With Exposed
Heatsink
FEATURES
D
D
D
D
D
D
D
D
D
D
14 Bit Resolution
D
Pin Compatible to the AD6644/45
80 MSPS Maximum Sample Rate
SNR = 74 dBc at 80 MSPS and 50 MHz IF
SFDR = 94 dBc at 80 MSPS and 50 MHz IF
D
Industrial Temperature Range = −405C to 855C
APPLICATIONS
2.2 V Differential Input Range
pp
D
D
D
D
Single and Multichannel Digital Receivers
Base Station Infrastructure
Instrumentation
5 V Supply Operation
3.3 V CMOS Compatible Outputs
1.85 W Total Power Dissipation
2s Complement Output Format
Video and Imaging
RELATED DEVICES
On-Chip Input Analog Buffer, Track and Hold,
and Reference Circuit
D
Clocking: CDC7005
Amplifiers: OPA695, THS4509
D
DESCRIPTION
The ADS5423 is a 14 bit 80 MSPS analog-to-digital converter (ADC) that operates from a 5 V supply, while providing 3.3 V
CMOS compatible digital outputs. The ADS5423 input buffer isolates the internal switching of the on-chip Track and Hold
(T&H) from disturbing the signal source. An internal reference generator is also provided to further simplify the system
design. The ADS5423 has outstanding low noise and linearity, over input frequency. With only a 2.2 VPP input range,
simplifies the design of multicarrier applications, where the carriers are selected on the digital domain.
The ADS5423 is available in a 52 pin HTQFP with heatsink package and is pin compatible to the AD6645. The ADS5423
is built on state of the art Texas Instruments complementary bipolar process (BiCom3) and is specified over full industrial
temperature range (−40°C to 85°C).
FUNCTIONAL BLOCK DIAGRAM
AV
DRV
DD
DD
A
IN
A
IN
+
+
A3
A2
TH3
TH2
TH1
ADC3
Σ
Σ
A1
−
−
ADC1
DAC1
ADC2
DAC2
VREF
Reference
5
5
6
C1
C2
Digital Error Correction
CLK+
CLK−
Timing
DMID OVR DRY
D[13:0]
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPad is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2005, Texas Instruments Incorporated
www.ti.com
ADS5423
www.ti.com
SLWS160 − FEBRUARY 2005
PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE LEAD
(1)
ADS5423IPJY
Tray, 160
HTQFP-52
ADS5423
PJY
−40°C to +85°C
ADS5423I
PowerPAD
ADS5423IPJYR
Tape and Reel, 1000
(1)
Thermal pad size: Octagonal 2,5 mm side
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handledwith appropriate precautions. Failure to observe
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range unless otherwise noted
proper handling and installation procedures can cause damage.
ADS5423
UNIT
AV to GND
6
5
DD
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because small parametric changes could cause
the device not to meet its published specifications.
Supply voltage
V
V
DRV to GND
DD
−0.3 to
Analog input to GND
AV + 0.3
DD
−0.3 to
Clock input to GND
CLK to CLK
V
V
V
RECOMMENDED OPERATING CONDITIONS
AV + 0.3
DD
2.5
MIN
TYP
MAX
UNIT
PARAMETER
−0.3 to
Supplies
Digital data output to GND
DRV + 0.3
DD
Analog supply voltage, AV
4.75
3
5
5.25
3.6
V
V
DD
Operating temperature range
Maximum junction temperature
Storage temperature range
(1)
−40 to 85
150
°C
°C
°C
Output driver supply voltage,
3.3
DRV
DD
−65 to 150
Analog Input
Differential input range
2.2
2.4
V
PP
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
Input common-mode voltage,
V
V
CM
Digital Output
Maximum output load
Clock Input
10
pF
THERMAL CHARACTERISTICS(1)
ADCLK input sample rate (sine
TEST
CONDITIONS
30
80
85
MSPS
PARAMETER
TYP
22.5
15.8
33.3
25.9
UNIT
°C/W
°C/W
°C/W
°C/W
wave) 1/t
C
Clock amplitude, sine wave,
Soldered slug, no
airflow
3
V
PP
(1)
θ
JA
differential
(2)
Clock duty cycle
50%
Soldered slug,
200-LPFM airflow
θ
JA
θ
JA
θ
JA
Open free-air temperature range −40
°C
(1)
See Figure 17 and Figure 18 for more information.
See Figure 16 for more information.
Unsoldered slug,
no airflow
(2)
Unsoldered slug,
200-LPFM airflow
Bottom of
package
(heatslug)
θ
JC
2
°C/W
(1)
Using 25 thermal vias (5 x 5 array). See the Application Section.
2
ADS5423
www.ti.com
SLWS160 − FEBRUARY 2005
ELECTRICAL CHARACTERISTICS
Over full temperature range (T
= −40°C to T
= 85°C), sampling rate = 80 MSPS, 50% clock duty cycle, AV = 5 V, DRV = 3.3 V,
MAX DD DD
MIN
−1 dBFS differential input, and 3 V differential sinusoidal clock, unless otherwise noted
PP
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
14
Bits
Analog Inputs
Differential input range
Differential input resistance
Differential input capacitance
Analog input bandwidth
Internal Reference Voltages
2.2
1
V
PP
See Figure 30
See Figure 30
kΩ
pF
1.5
570
MHz
Reference voltage, V
Dynamic Accuracy
No missing codes
2.4
V
REF
Tested
0.5
1.5
0
Differential linearity error, DNL
Integral linearity error, INL
Offset error
f
f
= 5 MHz
= 5 MHz
−0.95
−5
1.5
5
LSB
LSB
IN
IN
mV
Offset temperature coefficient
Gain error
1.7
0.9
1
ppm/°C
%FS
−5
5
PSRR
mV/V
ppm/°C
Gain temperature coefficient
Power Supply
77
Analog supply current, I
V
= full scale, f = 70 MHz
355
35
410
42
mA
mA
AVDD
IN
IN
Output buffer supply current, I
V
= full scale, f = 70 MHz
DRVDD
IN IN
Total power with 10-pF load on each digital output
to ground, f = 70 MHz
Power dissipation
1.85
20
2.2
W
IN
Power-up time
100
ms
Dynamic AC Characteristics
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
= 10 MHz
= 30 MHz
= 50 MHz
= 70 MHz
= 100 MHz
= 170 MHz
= 230 MHz
= 10 MHz
= 30 MHz
= 50 MHz
= 70 MHz
= 100 MHz
= 170 MHz
= 230 MHz
74.6
74.3
74.2
74.1
73.5
72
73
73
Signal-to-noise ratio, SNR
dBc
dBc
71.5
94
85
93
94
Spurious-free dynamic range, SFDR
90
86
73
64
3
ADS5423
www.ti.com
SLWS160 − FEBRUARY 2005
ELECTRICAL CHARACTERISTICS
Over full temperature range (T
= −40°C to T
= 85°C), sampling rate = 80 MSPS, 50% clock duty cycle, AV = 5 V, DRV = 3.3 V,
MAX DD DD
MIN
−1 dBFS differential input, and 3 V differential sinusoidal clock, unless otherwise noted
PP
PARAMETER
TEST CONDITIONS
MIN
TYP
74.6
74.2
74.1
73.9
72.7
69.1
62.8
105
100
99
MAX
UNIT
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
= 10 MHz
= 30 MHz
= 50 MHz
= 70 MHz
= 100 MHz
= 170 MHz
= 230 MHz
= 10 MHz
= 30 MHz
= 50 MHz
= 70 MHz
= 100 MHz
= 170 MHz
= 230 MHz
= 10 MHz
= 30 MHz
= 50 MHz
= 70 MHz
= 100 MHz
= 170 MHz
= 230 MHz
= 10 MHz
= 30 MHz
= 50 MHz
= 70 MHz
= 100 MHz
= 170 MHz
= 230 MHz
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
72.8
Signal-to-noise + distortion, SINAD
dBc
92
Second harmonic, HD2
dBc
90
94
88
94
93
94
90
Third harmonic, HD3
dBc
86
73
64
94
95
95
Worst-harmonic / spur (other than HD2 and
HD3)
90
dBc
LSB
88
88
88
RMS idle channel noise
Input pins tied together
0.9
DIGITAL CHARACTERISTICS
Over full temperature range (T
= −40°C to T = 85°C), AV = 5 V, DRV = 3.3 V, unless otherwise noted
MAX DD DD
MIN
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Outputs
(1)
Low-level output voltage
High-level output voltage
Output capacitance
DMID
C
C
= 10 pF
= 10 pF
0.1
3.2
3
0.6
V
V
LOAD
(1)
2.6
LOAD
pF
V
DRV /2
DD
(1)
Equivalent capacitance to ground of (load + parasitics of transmission lines).
4
ADS5423
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SLWS160 − FEBRUARY 2005
TIMING CHARACTERISTICS(3)
Over full temperature range, AV = 5 V, DRV = 3.3 V, sampling rate = 80 MSPS
DD
DD
PARAMETER
Aperture Time
DESCRIPTION
MIN
TYP
MAX
UNIT
t
t
Aperture delay
500
150
50
ps
fs
A
J
Clock slope independent aperture uncertainity (jitter)
Clock slope dependent jitter factor
k
µV
J
Clock Input
t
t
t
Clock period
12.5
6.25
6.25
ns
ns
ns
CLK
(1)
Clock pulsewidth high
Clock pulsewidth low
CLKH
(1)
CLKL
Clock to DataReady (DRY)
t
t
t
Clock rising 50% to DRY falling 50%
2.8
9
3.9
4.7
11
ns
ns
ns
DR
t
t
+
DR
Clock rising 50% to DRY rising 50%
C_DR
CLKH
Clock rising 50% to DRY rising 50% with 50% duty cycle clock
10.1
C_DR_50%
(4)
Clock to DATA, OVR
t
r
t
f
Data V to data V (rise time)
2
2
ns
ns
OL
OH
Data V to data V (fall time)
OH
OL
L
Latency
3
Cycles
ns
(2)
t
t
Valid DATA to clock 50% with 50% duty cycle clock (setup time)
4.8
2.6
6.3
3.6
su(C)
H(C)
(2)
Clock 50% to invalid DATA (hold time)
ns
(4)
DataReady (DRY) to DATA, OVR
(2)
t
t
Valid DATA to DRY 50% with 50% duty cycle clock (setup time)
3.3
5.4
4
ns
ns
su(DR)_50%
(2)
DRY 50% to invalid DATA with 50% duty cycle clock (hold time)
5.9
h(DR)_50%
(1)
(2)
(3)
(4)
See Figure 1 for more information.
See V and V levels.
All values obtained from design and characterization.
OH
OL
Data is updated with clock rising edge or DRY falling edge.
t
A
N+3
N
AIN
N+1
N+2
N+4
t
t
CLKL
t
CLKH
CLK
CLK, CLK
N + 1
N + 2
N + 3
N + 4
N
t
h(C)
t
t
su(C)
C_DR
D[13:0], OVR
DRY
N−3
N−2
N−1
N
t
t
h(DR)
su(DR)
t
r
t
f
t
DR
Figure 1. Timing Diagram
5
ADS5423
www.ti.com
SLWS160 − FEBRUARY 2005
PIN CONFIGURATION
PJY PACKAGE
(TOP VIEW)
52 51 50 49 48 47 46 45 44 43 42 41 40
1
39
38
37
36
35
34
33
32
31
30
29
28
27
DRVDD
D3
D2
D1
2
GND
VREF
GND
CLK
3
4
D0 (LSB)
DMID
GND
DRVDD
OVR
DNC
AVDD
GND
AVDD
GND
5
6
CLK
7
GND
AVDD
AVDD
GND
AIN
GND
8
9
10
11
12
13
AIN
GND
14 15 16 17 18 19 20 21 22 23 24 25 26
PIN ASSIGNMENTS
TERMINAL
DESCRIPTION
NAME
DRV
NO.
1, 33, 43
3.3 V power supply, digital output stage only
DD
GND
2, 4, 7, 10, 13, 15, Ground
17, 19, 21, 23, 25,
27, 29, 34, 42
VREF
CLK
3
5
6
2.4 V reference. Bypass to ground with a 0.1-µF microwave chip capacitor.
Clock input. Conversion initiated on rising edge.
Complement of CLK, differential input
CLK
AV
8, 9, 14, 16, 18,
22, 26, 28, 30
5 V analog power supply
DD
AIN
11
Analog input
AIN
12
Complement of AIN, differential analog input
C1
20
Internal voltage reference. Bypass to ground with a 0.1-µF chip capacitor.
Internal voltage reference. Bypass to ground with a 0.1-µF chip capacitor.
Do not connect
C2
24
DNC
31
OVR
32
Overrange bit. A logic level high indicates the analog input exceeds full scale.
DMID
35
Output data voltage midpoint. Approximately equal to (DV )/2
CC
D0 (LSB)
D1−D5, D6−D12
D13 (MSB)
DRY
36
Digital output bit (least significant bit); two’s complement
Digital output bits in two’s complement
Digital output bit (most significant bit); two’s complement
Data ready output
37−41, 44−50
51
52
6
ADS5423
www.ti.com
SLWS160 − FEBRUARY 2005
DEFINITION OF SPECIFICATIONS
Temperature Drift
Analog Bandwidth
The analog input frequency at which the power of the
fundamental is reduced by 3 dB with respect to the low
frequency value.
The temperature drift coefficient (with respect to gain
error and offset error) specifies the change per degree
celcius of the paramter from T
or T . It is
MAX
MIN
computed as the maximum variation of that parameter
over the whole temperature range divided by T
Aperture Delay
−
MAX
The delay in time between the rising edge of the input
sampling clock and the actual time at which the
sampling occurs.
T
.
MIN
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (P )
to the noise floor power (P ), excluding the power at dc
S
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
N
and the first five harmonics.
Clock Pulse Width/Duty Cycle
PS
SNR + 10Log
10 PN
The duty cycle of a clock signal is the ratio of the time
the clock signal remains at a logic high (clock pulse
width) to the period of the clock signal. Duty cycle is
typically expressed as a percentage. A perfect
differential sine wave clock results in a 50% duty cycle.
SNR is either given in units of dBc (dB to carrier) when
the absolute power of the fundamental is used as the
reference or dBFS (dB to full scale) when the power of
the fundamental is extrapolated to the converter’s
full-scale range.
Maximum Conversion Rate
The maximum sampling rate at which certified
operation is given. All parametric testing is performed
at this sampling rate unless otherwise noted.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental (P )
S
to the power of all the other spectral components
Minimum Conversion Rate
The minimum sampling rate at which the ADC
functions.
including noise (P ) and distortion (P ), but excluding
N
D
dc.
PS
SINAD + 10Log
10 PN ) PD
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions at analog input
values spaced exactly 1 LSB apart. The DNL is the
deviation of any single step from this ideal value,
measured in units of LSB.
SINAD is either given in units of dBc (dB to carrier) when
the absolute power of the fundamental is used as the
reference or dBFS (dB to full scale) when the power of
the fundamental is extrapolated to the converter’s
full-scale range.
Integral Nonlinearity (INL)
The INL is the deviation of the ADC’s transfer function
from a best fit line determined by a least squares curve
fit of that transfer function, measured in units of LSB.
Total Harmonic Distortion (THD)
THD is the ratio of the fundamental power (P ) to the
power of the first five harmonics (P ).
S
D
Gain Error
PS
THD + 10Log
10 PD
The gain error is the deviation of the ADC’s actual input
full-scale range from its ideal value. The gain error is
given as a percentage of the ideal input full-scale range.
THD is typically given in units of dBc (dB to carrier).
Offset Error
Power Up Time
The offset error is the difference, given in number of
LSBs, between the ADC’s actual value average idle
channel output code and the ideal average idle channel
output code. This quantity is often mapped into mV.
The difference in time from the point where the supplies
are stable at 5% of the final value, to the time the ac
test is past.
PSRR
The maximum change in offset voltage divided by the
total change in supply voltage, in units of mV/V.
7
ADS5423
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SLWS160 − FEBRUARY 2005
Spurious-Free Dynamic Range (SFDR)
Two-Tone Intermodulation Distortion
The ratio of the power of the fundamental to the highest
other spectral component (either spur or harmonic). SFDR
is typically given in units of dBc (dB to carrier).
IMD3 is the ratio of the power of the fundamental (at
frequiencies f1, f2) to the power of the worst spectral
component at either frequency 2f1 − f2 or 2f2 − f1). IMD3 is
either given in units of dBc (dB to carrier) when the
absolute power of the fundamental is used as the
reference or dBFS (dB to full scale) when it is referred to
the full-scale range.
8
ADS5423
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SLWS160 − FEBRUARY 2005
TYPICAL CHARACTERISTICS
Typical values are at T = 25°C, AV = DRV = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 80 MSPS, 3.3 Vpp sinusoidal
A
DD
DD
clock, 50% duty cycle, 16k FFT points, unless otherwise noted
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
1
1
0
0
−20
f
f
= 80 MSPS
f = 80 MSPS
S
S
= 2 MHz
f
IN
= 30 MHz
IN
−20
−40
SNR = 74.5 dBc
SINAD = 74.4 dBc
SFDR = 94 dBc
THD = 93 dBc
SNR = 74.3 dBc
SINAD = 74.2 dBc
SFDR = 93 dBc
THD = 89 dBc
−40
−60
−60
−80
−80
3
5
2
5
X
X
2
−100
−120
−100
−120
6
3
4
6
4
0
5
5
5
10
15
20
25
30
35
40
0
0
0
5
5
5
10
15
20
25
30
35
40
f − Frequency − MHz
f − Frequency − MHz
Figure 2
Figure 3
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
1
1
0
−20
0
−20
f
f
= 80 MSPS
= 70 MHz
SNR = 74 dBc
SINAD = 73.9 dBc
SFDR = 91 dBc
THD = 88 dBc
f = 80 MSPS
S
= 100 MHz
SNR = 73.4 dBc
SINAD = 72.9 dBc
SFDR = 84 dBc
THD = 82 dBc
S
f
IN
IN
−40
−40
−60
−60
3
−80
−80
2
2
5
5
3
X
X
4
6
−100
−120
−100
−120
6
4
0
10
15
20
25
30
35
40
10
15
20
25
30
35
40
f − Frequency − MHz
f − Frequency − MHz
Figure 4
Figure 5
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
1
1
0
−20
0
−20
f
f
= 80 MSPS
= 150 MHz
SNR = 71.9 dBc
SINAD = 70.8 dBc
SFDR = 77 dBc
THD = 77 dBc
f = 80 MSPS
S
= 230 MHz
SNR = 70.3 dBc
SINAD = 62.8 dBc
SFDR = 63 dBc
THD = 63 dBc
S
f
IN
IN
−40
−40
3
−60
−60
3
5
2
−80
−80
5
X
X
4
2
6
9
8
4
7
−100
−120
−100
−120
6
0
10
15
20
25
30
35
40
10
15
20
25
30
35
40
f − Frequency − MHz
f − Frequency − MHz
Figure 6
Figure 7
9
ADS5423
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SLWS160 − FEBRUARY 2005
TYPICAL CHARACTERISTICS
Typical values are at T = 25°C, AV = DRV = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 80 MSPS, 3.3 Vpp sinusoidal
A
DD
DD
clock, 50% duty cycle, 16k FFT points, unless otherwise noted
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
0
0
−20
f
f
f
= 80 MSPS
1 = 69.2 MHz, −7 dBFS
2 = 70.7 MHz, −7 dBFS
f
f
f
= 80 MSPS
1 = 169.6 MHz, −7 dBFS
2 = 170.4 MHz, −7 dBFS
S
S
−20
−40
IN
IN
IN
IN
IMD3 = −93 dBFS
IMD3 = −81 dBFS
−40
−60
−60
−80
−80
−100
−120
−140
−100
−120
−140
0
5
10
15
20
25
30
35
40
40
0
0
5
10
15
20
25
30
35
40
40
0
f − Frequency − MHz
f − Frequency − MHz
Figure 8
Figure 9
WCDMA CARRIER
WCDMA CARRIER
0
−20
0
−20
f
= 76.8 MSPS
f
= 76.8 MSPS
S
S
f
IN
= 70 MHz
f
IN
= 170 MHz
PAR = 5 dB
ACPR Adj Top = 79.2 dB
PAR = 5 dB
ACPR Adj Top = 74.8 dB
ACPR Adj Low = 73.9 dB
−40
−40
−60
−60
−80
−80
−100
−120
−140
−100
−120
−140
0
5
10
15
20
25
30
35
0
5
10
15
20
25
30
35
f − Frequency − MHz
f − Frequency − MHz
Figure 10
Figure 11
AC PERFORMANCE
vs
INPUT AMPLITUDE
AC PERFORMANCE
vs
INPUT AMPLITUDE
120
100
80
120
100
80
SFDR (dBFS)
SFDR (dBFS)
SNR (dBFS)
SNR (dBFS)
60
60
SFDR (dBc)
SFDR (dBc)
40
40
20
20
SNR (dBc)
SNR (dBc)
f
= 80 MSPS
= 70 MHz
f
= 80 MSPS
= 170 MHz
0
0
S
S
f
IN
f
IN
−20
−20
−90 −80 −70 −60 −50 −40 −30 −20 −10
−90 −80 −70 −60 −50 −40 −30 −20 −10
A
IN
− Input Amplitude − dBFS
A
IN
− Input Amplitude − dBFS
Figure 12
Figure 13
10
ADS5423
www.ti.com
SLWS160 − FEBRUARY 2005
TYPICAL CHARACTERISTICS
Typical values are at T = 25°C, AV = DRV = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 80 MSPS, 3.3 Vpp sinusoidal
A
DD
DD
clock, 50% duty cycle, 16k FFT points, unless otherwise noted
TWO-TONE SPURIOUS-FREE DYNAMIC RANGE
vs
INPUT AMPLITUDE
NOISE HISTOGRAM WITH INPUTS SHORTED
120
50
45
40
35
30
25
20
15
10
5
100
SFDR (dBFS)
80
60
40
SFDR (dBc)
20
90 dBFS Line
f
f
f
= 69 MHz
= 71 MHz
= 80 MSPS
IN1
IN2
0
S
−20
0
8174
8175
8176
8177
8178
−110−100 −90 −80 −70 −60 −50 −40 −30 −20 −10
0
70
4
A
− Input Amplitude − dBFS
Code Number
IN
Figure 14
Figure 15
SPURIOUS-FREE DYNAMIC RANGE
AC PERFORMANCE
vs
CLOCK LEVEL
vs
DUTY CYCLE
100
95
90
85
80
75
100
95
90
85
80
75
70
65
60
55
50
SFDR (dBc)
f
= 2 MHz
IN
SNR (dBc)
f
= 40 MHz
IN
f
f
= 80 MSPS
= 70 MHz
S
IN
30
40
50
60
0
1
2
3
4
Duty Cycle − %
Figure 16
Clock Level − V
PP
Figure 17
AC PERFORMANCE
vs
CLOCK LEVEL
AC PERFORMANCE
vs
CLOCK COMMON MODE
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
f
f
= 80 MSPS
= 69.6 MHz
S
IN
SFDR
SNR
SFDR (dBc)
SNR (dBc)
f
f
= 80 MSPS
= 170 MHz
S
IN
0
1
2
3
0
1
2
3
4
5
Clock Level − V
Clock Common Mode − V
PP
Figure 18
Figure 19
11
ADS5423
www.ti.com
SLWS160 − FEBRUARY 2005
TYPICAL CHARACTERISTICS
Typical values are at T = 25°C, AV = DRV = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 80 MSPS, 3.3 Vpp sinusoidal
A
DD
DD
clock, 50% duty cycle, 16k FFT points, unless otherwise noted
SPURIOUS-FREE DYNAMIC RANGE
SIGNAL-TO−NOISE RATIO
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
96
74.8
74.6
74.4
74.2
74.0
73.8
73.6
73.4
73.2
73.0
85°C
60°C
−40°C
95
94
93
92
91
90
89
88
87
86
0°C
40°C
−40°C
85°C
−20°C
f
f
= 80 MSPS
f
f
= 80 MSPS
= 69.6 MHz
S
S
100°C
= 69.6 MHz
IN
0°C
IN
4.6
4.8
5.0
5.2
5.4
4.6
2.6
0
4.8
5.0
5.2
5.4
AV − Supply Voltage − V
AV − Supply Voltage − V
DD
DD
Figure 20
Figure 21
SPURIOUS-FREE DYNAMIC RANGE
SIGNAL-TO-NOISE RATIO
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
96
95
94
93
92
91
90
89
88
74.8
74.6
74.4
74.2
74.0
73.8
73.6
73.4
73.2
−40°C
0°C
f
f
= 80 MSPS
= 69.6 MHz
S
85°C
IN
40°C
20°C
40°C
60°C
−40°C
85°C
f
f
= 80 MSPS
= 69.6 MHz
S
0°C
IN
2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8
2.8
3.0
3.2
3.4
3.6
3.8
AV − Supply Voltage − V
IOV − Supply Voltage − V
DD
DD
Figure 22
Figure 23
DIFFERENTIAL NONLINEARITY
INTEGRAL NONLINEARITY
1.5
1.0
1.0
0.8
0.6
0.5
0.4
0.2
0.0
0.0
−0.5
−1.0
−1.5
−2.0
−0.2
−0.4
−0.6
−0.8
−1.0
5000
10000
Code
15000
0
5000
10000
15000
Code
Figure 25
Figure 24
12
ADS5423
www.ti.com
SLWS160 − FEBRUARY 2005
TYPICAL CHARACTERISTICS
Typical values are at T = 25°C, AV = DRV = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 80 MSPS, 3.3 Vpp sinusoidal
A
DD
DD
clock, 50% duty cycle, 16k FFT points, unless otherwise noted
TOTAL POWER
vs
INPUT BANDWIDTH
SAMPLING FREQUENCY
5
1.90
1.89
1.88
1.87
1.86
1.85
1.84
1.83
1.82
1.81
IF = 70 MHz
0
−5
−10
−15
f
A
= 80 MSPS
S
= −1dBFS
IN
−20
1
10
100
1k
0
20
40
60
80
100
120
140
f − Frequency − MHz
f
S
− Sampling Frequency − MSPS
Figure 26
Figure 27
13
ADS5423
www.ti.com
SLWS160 − FEBRUARY 2005
Typical values are at T = 25°C, AV = DRV = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 80 MSPS, 3.3 Vpp sinusoidal
A
DD
DD
clock, 50% duty cycle, 16k FFT points, unless otherwise noted
90
73
71
80
70
74
72
73
70
60
71
74
69
68
50
72
74
70
40
69
73
71
68
66
70
69
30
67
65
62
72
20
73
67
68
71
70
66
69
64
63
65
10
0
20
40
60
80
100
120
140
160
180
200
220
f
IN
− Input Frequency − MHz
62
64
66
68
70
72
74
SNR − dBc
Figure 28.
90
80
70
60
50
40
30
20
10
94
91
94
67
73
76
88
70
94
82
94
94
94
85
79
94
91
94
76
94
94
88
73
94
94
67
70
91
94
85
82
91
94
91
79
94
64
91
61
70
73
76
85
0
20
40
60
80
100
120
140
160
180
200
220
f
IN
− Input Frequency − MHz
60
65
70
75
80
85
90
SFDR − dBc
Figure 29.
14
ADS5423
www.ti.com
SLWS160 − FEBRUARY 2005
EQUIVALENT CIRCUITS
AV
DD
AIN
BUF
T/H
AV
DD
500 Ω
+
25 Ω
V
REF
BUF
V
REF
−
Bandgap
AV
DD
1.2 kΩ
1.2 kΩ
500 Ω
AIN
BUF
T/H
Figure 33. Reference
Figure 30. Analog Input
DRV
DD
AV
DD
−
I
I
P
OUT
DAC
M
OUT
+
Bandgap
C1, C2
Figure 31. Digital Output
Figure 34. Decoupling Pin
AV
DD
DRV
DD
10 kΩ
CLK
1 kΩ
1 kΩ
Clock Buffer
DMID
Bandgap
AV
DD
10 kΩ
CLK
Figure 35. DMID Generation
Figure 32. Clock Input
15
ADS5423
www.ti.com
SLWS160 − FEBRUARY 2005
APPLICATION INFORMATION
of 2.2 V . The maximum swing is determined by the
internal reference voltage generator eliminating any
external circuitry for this purpose.
THEORY OF OPERATION
PP
The ADS5423 is a 14 bit, 80 MSPS, monolithic pipeline
analog to digital converter. Its bipolar analog core
operates from a 5 V supply, while the output uses 3.3 V
supply for compatibility with the CMOS family. The
conversion process is initiated by the rising edge of the
external input clock. At that instant, the differential input
signal is captured by the input track and hold (T&H) and
the input sample is sequentially converted by a series
of small resolution stages, with the outputs combined in
a digital correction logic block. Both the rising and the
falling clock edges are used to propagate the sample
through the pipeline every half clock cycle. This process
results in a data latency of three clock cycles, after
which the output data is available as a 14 bit parallel
word, coded in binary two’s complement format.
The ADS5423 obtains optimum performance when the
analog inputs are driven differentially. The circuit in
Figure 36 shows one possible configuration using an
RF transformer with termination either on the primary or
on the secondary of the transformer. If voltage gain is
required a step up transformer can be used. For higher
gains that would require impractical higher turn ratios on
the transformer, a single-ended amplifier driving the
transformer can be used (see Figure 37). Another
circuit optimized for performance would be the one on
Figure 38, using the THS4304 or the OPA695. Texas
Instruments has shown excellent performance on this
configuration up to 10 dB gain with the THS4304 and at
14 dB gain with the OPA695. For the best performance,
they need to be configured differentially after the
transformer (as shown) or in inverting mode for the
OPA695 (see SBAA113); otherwise, HD2 from the op
amps limits the useful frequency.
INPUT CONFIGURATION
The analog input for the ADS5423 (see Figure 30)
consists of an analog differential buffer followed by a
bipolar track-and-hold. The analog buffer isolates the
source driving the input of the ADC from any internal
switching. The input common mode is set internally
through a 500 Ω resistor connected from 2.4 V to each
of the inputs. This results in a differential input
impedance of 1 kΩ.
R0
Z0
W
50
W
50
AIN
ADS5423
1:1
R
50
AC Signal
Source
W
For a full-scale differential input, each of the differential
lines of the input signal (pins 11 and 12) swings
symmetrically between 2.4 +0.55 V and 2.4 –0.55 V.
This means that each input is driven with a signal of up
to 2.4 0.55 V, so that each input has a maximum signal
AIN
ADT1−1WT
Figure 36. Converting a Single-Ended Input to a
Differential Signal Using RF Transformers
swing of 1.1 V for a total differential input signal swing
PP
5 V
−5 V
R
100 Ω
S
0.1 µF
+
V
IN
R
1:1
IN
AIN
OPA695
R
100 Ω
T
−
ADS5423
AIN
C
IN
R
IN
1000 µF
R
1
400 Ω
A = 8V/V
(18 dB)
R
V
2
57.5 Ω
Figure 37. Using the OPA695 With the ADS5423
16
ADS5423
www.ti.com
SLWS160 − FEBRUARY 2005
APPLICATION INFORMATION
R
G
R
F
CM
5 V
−
THS4304
+
1:1
V
IN
AIN
AIN
CM
49.9 Ω
ADS5423
5 V
V
REF
From
50 Ω
Source
+
THS4304
−
CM
R
G
R
F
CM
Figure 38. Using the THS4304 With the ADS5423
Besides these, Texas Instruments offers a wide
selection of single-ended operational amplifiers
(including the THS3201, THS3202, and OPA847) that
can be selected depending on the application. An RF
gain block amplifier, such as Texas Instrument’s
THS9001, can also be used with an RF transformer for
high input frequency applications. For applications
requiring dc-coupling with the signal source, instead of
using a topology with three single ended amplifiers, a
differential input/differential output amplifier like the
THS4509 (see Figure 39) can be used, which
minimizes board space and reduce number of
components.
On this configuration, the THS4509 amplifier circuit
provides 10 dB of gain, converts the single-ended input
to differential, and sets the proper input common-mode
voltage to the ADS5423.
The 225 Ω resistors and 2.7 pF capacitor between the
THS4509 outputs and ADS5423 inputs (along with the
input capacitance of the ADC) limit the bandwidth of the
signal to about 100 MHz (−3 dB).
For this test, an Agilent signal generator is used for the
signal source. The generator is an ac-coupled 50 Ω
source. A band-pass filter is inserted in series with the
input to reduce harmonics and noise from the signal
source.
Figure 41 shows their combined SNR and SFDR
performance versus frequency with −1 dBFS input
signal level and sampling at 80 MSPS.
17
ADS5423
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SLWS160 − FEBRUARY 2005
APPLICATION INFORMATION
Input termination is accomplished via the 69.8 Ω
resistor and 0.22 µF capacitor to ground in conjunction
with the input impedance of the amplifier circuit. A
0.22 µF capacitor and 49.9 Ω resistor is inserted to
ground across the 69.8 Ω resistor and 0.22 µF capacitor
on the alternate input to balance the circuit.
CLK
ADS5423
CLK
Square Wave or
Sine Wave
0.01 µF
0.01 µF
Gain is a function of the source impedance, termination,
and 348 Ω feedback resistor. See the THS4509 data
sheet for further component values to set proper 50 Ω
termination for other common gains.
Figure 41. Single-Ended Clock
Since
common-mode voltage is +2.4 V, the THS4509 is
operated from a single power supply input with V
the
ADS5423
recommended
input
CLOCK INPUTS
=
S+
The ADS5423 clock input can be driven with either a
differential clock signal or a single-ended clock input,
with little or no difference in performance between both
configurations. In low input frequency applications,
where jitter may not be a big concern, the use of single
ended clock (see Figure 41) could save some cost and
board space without any trade-off in performance.
When driven on this configuration, it is best to connect
CLKM (pin 11) to ground with a 0.01 µF capacitor, while
CLKP is ac-coupled with a 0.01 µF capacitor to the
clock source, as shown in Figure 38.
+5 V and V = 0 V (ground). This maintains maximum
S−
headroom on the internal transistors of the THS4509.
V
IN
From
50 Ω
Source
100 Ω
348 Ω
+5V
14-Bit
69.8 Ω
80 MSPS
225 Ω
225 Ω
0.22 µF
100 Ω
A
IN
2.7 pF
ADS5423
THS4509
CM
A
IN
V
REF
49.9 Ω
69.8 Ω
49.9 Ω
0.1 µF
0.1 µF
0.22 µF
0.22 µF
0.1 µF
1:4
Clock
348 Ω
CLK
Source
Figure 39. Using the THS4509 With the ADS5423
ADS5423
CLK
MA3X71600LCT−ND
PERFORMANCE
vs
INPUT FREQUENCY
Figure 42. Differential Clock
95
90
Nevertheless, for jitter sensitive applications, the use of
a differential clock will have some advantages (as with
any other ADCs) at the system level. The first
advantage is that it allows for common-mode noise
rejection at the PCB level. A further analysis (see
Clocking High Speed Data Converters, SLYT075)
reveals one more advantage. The following formula
describes the different contributions to clock jitter:
SFDR (dBc)
85
80
SNR (dBFS)
75
2
2
2
(Jittertotal) = (EXT_jitter) + (ADC_jitter) =
2
2
2
(EXT_jitter) + (ADC_int) + (K/clock_slope)
70
10
20
30
40
50
60
70
f
IN
− Input Frequency − MHz
Figure 40. Performance vs Input Frequency for
the THS4509 + ADS5423 Configuration
18
ADS5423
www.ti.com
SLWS160 − FEBRUARY 2005
APPLICATION INFORMATION
The first term would represent the external jitter, coming
from the clock source, plus noise added by the system
on the clock distribution, up to the ADC. The second
term is the ADC contribution, which can be divided in
two portions. The first does not depend directly on any
external factor. That is the best we can get out of our
ADC. The second contribution is a term inversely
proportional to the clock slope. The faster the slope, the
smaller this term will be. As an example, we could
compute the ADC jitter contribution from a sinusoidal
input clock of 3 Vpp amplitude and Fs = 80 MSPS:
Another possibility is the use of a logic based clock, as
PECL. In this case, the slew rate of the edges will most
likely be much higher than the one obtained for the
same clock amplitude based on a sinusoidal clock. This
solution would minimize the effect of the slope
dependent ADC jitter. Nevertheless, observe that for
the ADS5423, this term is small and has been
optimized. Using logic gates to square a sinusoidal
clock may not produce the best results as logic gates
may not have been optimized to act as comparators,
adding too much jitter while squaring the inputs.
2
−5
ADC_jitter = sqrt ((150fs) + (5 x 10 /(1.5 x 2 x PI x 80
x 10 )) ) = 164fs
The common-mode voltage of the clock inputs is set
internally to 2.4 V using internal 1 kΩ resistors. It is
recommended using an ac coupling, but if for any
reason, this scheme is not possible, due to, for
instance, asynchronous clocking, the ADS5423
presents a good tolerance to clock common-mode
variation (see Figure 19).
6
2
The use of differential clock allows for the use of bigger
clock amplitudes without exceeding the absolute
maximum ratings. This, on the case of sinusoidal clock,
results on higher slew rates which minimizes the impact
of the jitter factor inversely proportional to the clock
slope.
Additionally, the internal ADC core uses both edges of
the clock for the conversion process. This means that,
ideally, a 50% duty cycle should be provided. Figure 16
shows the performance variation of the ADC versus
clock duty cycle.
Figure 42 shows this approach. The back-to-back
Schottky can be added to limit the clock amplitude in
cases where this would exceed the absolute maximum
ratings, even when using a differential clock. Figure 17
and Figure 18 show the performance versus input clock
amplitude for a sinusoidal clock.
DIGITAL OUTPUTS
The ADC provides 14 data outputs (D13 to D0, with D13
being the MSB and D0 the LSB), a data-ready signal
(DRY, pin 52), and an out-of-range indicator (OVR, pin
32) that equals 1 when the output reaches the full-scale
limits.
100 nF
MC100EP16DT
Q
100 nF
100 nF
CLK
D
D
V
The output format is two’s complement. When the input
voltage is at negative full scale (around −1.1 V
differential), the output will be, from MSB to LSB, 10
0000 0000 0000. Then, as the input voltage is
increased, the output switches to 10 0000 0000 0001,
10 0000 0000 0010 and so on until 11 1111 1111 1111
right before mid-scale (when both inputs are tight
together if we neglect offset errors). Further increase on
input voltages, outputs the word 00 0000 0000 0000, to
be followed by 00 0000 0000 0001, 00 0000 0000 0010
and so on until reaching 01 1111 1111 1111 at full-scale
input (1.1 V differential).
Q
ADS5423
CLK
BB
100 nF
499 W
499 W
50 Ω
50 Ω
100 nF
113 Ω
Figure 43. Differential Clock Using PECL Logic
19
ADS5423
www.ti.com
SLWS160 − FEBRUARY 2005
APPLICATION INFORMATION
Although the output circuitry of the ADS5423 has been
designed to minimize the noise produced by the
transients of the data switching, care must be taken
when designing the circuitry reading the ADS5423
outputs. Output load capacitance should be minimized
by minimizing the load on the output traces, reducing
their length and the number of gates connected to them,
and by the use of a series resistor with each pin. Typical
numbers on the data sheet tables and graphs are
obtained with 100 Ω series resistor on each digital
output pin, followed by a 74AVC16244 digital buffer as
the one used in the evaluation board.
modules provided to customer for evaluation. In order
to obtain the best performance, the user should layout
the board to assure that the digital return currents do not
flow under the analog portion of the board. This can be
achieved without the need to split the board and just
with careful component placing and increasing the
number of vias and ground planes.
Finally, notice that the metallic heat sink under the
package is also connected to analog ground.
LAYOUT INFORMATION
The evaluation board represents a good guideline of
how to layout the board to obtain the maximum
performance out of the ADS5423. General design rules
as the use of multilayer boards, single ground plane for
both, analog and digital ADC ground connections and
local decoupling ceramic chip capacitors should be
applied. The input traces should be isolated from any
external source of interference or noise, including the
digital outputs as well as the clock traces. The clock
should also be isolated from other signals, especially on
applications where low jitter is required, as high IF
sampling.
POWER SUPPLIES
The use of low noise power supplies with adequate
decoupling is recommended, being the linear supplies
the first choice vs switched ones, which tend to
generate more noise components that can be coupled
to the ADS5423.
The ADS5423 uses two power supplies. For the analog
portion of the design, a 5 V AV is used, while for the
DD
digital outputs supply (DRV ), we recommend the use
DD
of 3.3 V. All the ground pins are marked as GND,
although AGND pins and DRGND pins are not tied
together inside the package. Customers willing to
experiment with different grounding schemes should
know that AGND pins are 4, 7, 10, 13, 15, 17, 19, 21,
23, 25, 27, and 29, while DRGND pins are 2, 34, and 42.
Nevertheless, we recommend that both grounds are
tied together externally, using a common ground plane.
That is the case on the production test boards and
Besides performance oriented rules, special care has
to be taken when considering the heat dissipation out
of the device. The thermal heat sink (octagonal, with
2,5 mm on each side) should be soldered to the board,
and provision for more than 16 ground vias should be
made. The thermal package information describes the
T
values obtained on the different configurations.
JA
20
ꢀꢁꢂꢃꢄꢅꢆ
www.ti.com
SLWS160 − FEBRUARY 2005
Center Power Pad Solder Stencil Opening
Stencil Thicknes s
0.1m m
X
7.0
6.5
Y
7.0
6.5
0.127m m
0.152m m
0.178m m
6.0
5.6
6.0
5.6
21
PACKAGE OPTION ADDENDUM
www.ti.com
26-Jul-2005
PACKAGING INFORMATION
Orderable Device
ADS5423IPJY
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
QFP
PJY
52
52
52
52
160 Green (RoHS &
no Sb/Br)
CU SN
CU SN
CU SN
CU SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
ADS5423IPJYG4
ADS5423IPJYR
ADS5423IPJYRG4
QFP
QFP
QFP
PJY
PJY
PJY
160 Green (RoHS &
no Sb/Br)
1000 Green (RoHS &
no Sb/Br)
1000 Green (RoHS &
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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