ADS5424-SP [TI]
CLASS V, 14-BIT, 105-MSPS ANALOG-TO-DIGITAL CONVERTER; V类，14位， 105 MSPS模拟数字转换器
| 型号： | ADS5424-SP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | CLASS V, 14-BIT, 105-MSPS ANALOG-TO-DIGITAL CONVERTER |
| 文件： | 总22页 (文件大小：400K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS5424-SP
www.ti.com
SLWS194B –MAY 2008–REVISED MARCH 2012
CLASS V, 14-BIT, 105-MSPS ANALOG-TO-DIGITAL CONVERTER
Check for Samples: ADS5424-SP
1
FEATURES
•
•
•
•
•
•
•
•
•
•
14-Bit Resolution
•
•
Military Temperature Range
( –55°C to 125°C Tcase
QML-V Qualified, SMD 5962-07206
)
105-MSPS Maximum Sample Rate
SNR = 70 dBc at 105 MSPS and 50 MHz IF
SFDR = 78 dBc at 105 MSPS and 50 MHz IF
2.2-VPP Differential Input Range
5-V Supply Operation
APPLICATIONS
•
•
•
•
Single and Multichannel Digital Receivers
Base Station Infrastructure
Instrumentation
3.3-V CMOS Compatible Outputs
2.3-W Total Power Dissipation
2s Complement Output Format
Video and Imaging
On-Chip Input Analog Buffer, Track and Hold,
and Reference Circuit
RELATED DEVICES
•
•
Clocking: CDC7005
•
52-Pin Ceramic Nonconductive Tie-Bar
Package (HFG)
Amplifiers: OPA695, THS4509
DESCRIPTION/ORDERING INFORMATION
The ADS5424 is a 14-bit, 105-MSPS analog-to-digital converter (ADC) that operates from a 5-V supply, while
providing 3.3-V CMOS compatible digital outputs. The ADS5424 input buffer isolates the internal switching of the
on-chip track and hold (T&H) from disturbing the signal source. An internal reference generator is also provided
to further simplify the system design. The ADS5424 has outstanding low noise and linearity, over input
frequency. With only a 2.2-VPP input range, ADS5424 simplifies the design of multicarrier applications, where the
carriers are selected on the digital domain.
The ADS5424 is available in a 52-pin ceramic nonconductive tie-bar package (HFG). The ADS5424 is built on
state of the art Texas Instruments complementary bipolar process (BiCom3) and is specified over full military
temperature range (–55°C to 125°C Tcase
)
Table 1. ORDERING INFORMATION(1)
TA
PACKAGE(2)
52/ HFG
ORDERING PART NUMBER
TOP-SIDE MARKING
5962-0720601VXC
ADS5424MHFG-V
–55°C to 125°C Tcase
5962-0720601VXC
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADS5424-SP
SLWS194B –MAY 2008–REVISED MARCH 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FUNCTIONAL BLOCK DIAGRAM
AV
DRV
DD
DD
A
A
+
+
IN
A3
A2
TH3
TH2
TH1
ADC3
Σ
Σ
A1
IN
−
−
ADC1
DAC1
ADC2
DAC2
VREF
Reference
5
5
6
C1
C2
Digital Error Correction
CLK+
CLK−
Timing
DMID OVR DRY
D[13:0]
GND
ABSOLUTE MAXIMUM RATINGS
over operating temperature range (unless otherwise noted)(1)
ADS5424
UNIT
AVDD to GND
Supply voltage
6
5
V
DRVDD to GND
Analog input to GND
Clock input to GND
CLK to CLK
–0.3 V to AVDD + 0.3
–0.3 V to AVDD + 0.3
±2.5
V
V
V
Digital data output to GND
–0.3 V to DRVDD + 0.3
–55°C to 125
150
V
TC
TJ
Characterized case operating temperature range
Maximum junction temperature
°C
°C
°C
Tstg
Storage temperature range
–65°C to 150
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only and functional operation of the device at these or any other conditions beyond
those specified is not implied.
2
Submit Documentation Feedback
Copyright © 2008–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS5424-SP
ADS5424-SP
www.ti.com
SLWS194B –MAY 2008–REVISED MARCH 2012
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
SUPPLIES
AVDD
Analog supply voltage
4.75
3
5
5.25
3.6
V
V
DRVDD
Output driver supply voltage
3.3
ANALOG INPUT
Differential input range
Input common mode voltage
DIGITAL OUTPUT
Maximum output load
CLOCK INPUT
ADCLK input sample rate (sine wave)
2.2
2.4
VPP
V
VCM
10
pF
30
105 MSPS
VPP
Clock amplitude, differential sine wave
Clock duty cycle
3
50%
TC
Open case temperature range
–55
125
°C
ELECTRICAL CHARACTERISTICS (Unchanged after 100 kRad)
Typical values at TC = 25°C, Over full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 105 MSPS,
50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1 dBFS differential input, and 3-VPP sinusoidal clock (unless otherwise
noted)
PARAMETER
Resolution
ANALOG INPUTS
Differential input range
TEST CONDITIONS
MIN
TYP
MAX UNIT
14
Bits
2.2
1
Vpp
kΩ
Differential input resistance
Differential input capacitance
See Figure 11
See Figure 11
1.5
570
pF
Analog input bandwidth
MHz
INTERNAL REFERENCE VOLTAGES
VREF
Reference voltage
2.38
2.4
2.41
V
DYNAMIC ACCURACY
No missing codes
Tested
±0.5
DNL
INL
Differential linearity error
fIN = 10 MHz
fIN = 10 MHz
fIN = 10 MHz
–0.98
–5.0
1.5
+5.0
+6.9
LSB
LSB
LSB
TC= 25°C and
TC,MAX
±3.0
Integral linearity error
TC= TC,MIN
–-6.9
–1.5
Offset error
0
0.0007
0.9
1.5 %FS
%FS/°C
Offset temperature coefficient
Gain error
–5
5
%FS
Gain temperature coefficient
0.006
%FS/°C
POWER SUPPLY
VIN = full scale, fIN = 70
MHz
IAVDD
Analog supply current
FS = 105 MSPS
FS = 105 MSPS
355
47
410
55
mA
mA
VIN = full scale, fIN = 70
MHz
IDRVDD Output buffer supply current
Total power with 10-pF
Power dissipation
Power-up time
load on each digital output FS = 105 MSPS
to ground, fIN = 70 MHz
1.9
20
2.3
W
FS = 105 MSPS
ms
Copyright © 2008–2012, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Link(s): ADS5424-SP
ADS5424-SP
SLWS194B –MAY 2008–REVISED MARCH 2012
www.ti.com
ELECTRICAL CHARACTERISTICS (Unchanged after 100 kRad) (continued)
Typical values at TC = 25°C, Over full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 105 MSPS,
50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1 dBFS differential input, and 3-VPP sinusoidal clock (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DYNAMIC AC CHARACTERISTICS
TC= 25°C
70.5
71.0
70.5
70.0
72.4
fIN = 10 MHz
TC = TC,MAX
TC= TC,MIN
fIN = 30 MHz
fIN = 50 MHz
Full Temp Range
71.5
70.9
70.1
SNR
Signal-to-noise ratio
TC= 25°C
68.2
67.0
68.0
dBc
fIN = 70 MHz
TC = TC,MAX
TC= TC,MIN
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
68.9
66.3
64.0
81.6
TC = 25°C
72.0
71.0
77.0
69.0
75.0
fIN = 10 MHz
Full Temp Range
TC= 25°C
80.6
fIN = 30 MHz
fIN = 50 MHz
fIN = 70 MHz
TC = TC,MAX
TC= TC,MIN
78.1
82.6
SFDR
Spurious free dynamic range
dBc
TC= 25°C
68.0
69.0
67.0
TC = TC,MAX
TC= TC,MIN
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
82.5
68.0
65.4
71.3
TC= 25°C
68.6
68.3
68.2
69.4
67.0
69.4
fIN = 10 MHz
TC = TC,MAX
TC= TC,MIN
TC= 25°C
70.2
fIN = 30 MHz
fIN = 50 MHz
fIN = 70 MHz
TC = TC,MAX
TC= TC,MIN
SINAD Signal-to-noise + distortion
69.9
69.7
dBc
TC= 25°C
65.8
64.6
65.0
TC = TC,MAX
TC= TC,MIN
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
68.6
64.0
61.1
4
Submit Documentation Feedback
Copyright © 2008–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS5424-SP
ADS5424-SP
www.ti.com
SLWS194B –MAY 2008–REVISED MARCH 2012
ELECTRICAL CHARACTERISTICS (Unchanged after 100 kRad) (continued)
Typical values at TC = 25°C, Over full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 105 MSPS,
50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1 dBFS differential input, and 3-VPP sinusoidal clock (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
TC = 25°C
MIN
72.0
71.0
77.0
69.0
75.0
TYP
MAX UNIT
81.8
fIN = 10 MHz
Full Temp Range
TC= 25°C
80.6
fIN = 30 MHz
fIN = 50 MHz
fIN = 70 MHz
TC = TC,MAX
TC= TC,MIN
86.5
85.0
HD2
Second harmonic
dBc
TC= 25°C
68.0
69.0
67.0
TC = TC,MAX
TC= TC,MIN
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
86.1
93.0
71.0
81.6
TC = 25°C
72.0
71.0
77.0
69.0
75.0
fIN = 10 MHz
Full Temp Range
TC= 25°C
81.3
fIN = 30 MHz
fIN = 50 MHz
fIN = 70 MHz
TC = TC,MAX
TC= TC,MIN
78.1
82.6
HD3
Third harmonic
dBc
TC= 25°C
68.0
69.0
67.0
TC = TC,MAX
TC= TC,MIN
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
83.3
68.0
65.4
85.5
83.8
Full Temp Range
TC= 25°C
75.0
80.0
74.0
80.0
fIN = 30 MHz
fIN = 50 MHz
fIN = 70 MHz
TC = TC,MAX
TC= TC,MIN
87.0
83.0
Worst other harmonic/spur (other than
HD2 and HD3)
TC= 25°C
74.0
72.0
74.0
dBc
TC = TC,MAX
TC= TC,MIN
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
82.5
79.8
78.0
Copyright © 2008–2012, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Link(s): ADS5424-SP
ADS5424-SP
SLWS194B –MAY 2008–REVISED MARCH 2012
www.ti.com
ELECTRICAL CHARACTERISTICS (Unchanged after 100 kRad) (continued)
Typical values at TC = 25°C, Over full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 105 MSPS,
50% clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1 dBFS differential input, and 3-VPP sinusoidal clock (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
TC = 25°C
MIN
71.0
70.0
75.0
68.0
73.8
TYP
MAX UNIT
77.8
fIN = 10 MHz
Full Temp Range
TC= 25°C
77.4
fIN = 30 MHz
fIN = 50 MHz
fIN = 70 MHz
TC = TC,MAX
TC= TC,MIN
76.7
79.6
THD
Total harmonic distortion
dBC
TC= 25°C
67.4
67.2
66.4
TC = TC,MAX
TC= TC,MIN
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
79.9
67.6
64.1
11.7
TC= 25°C
11.1
11.0
11.0
11.2
10.8
11.2
10.6
10.4
10.5
fIN = 10 MHz
fIN = 30 MHz
TC = TC,MAX
TC= TC,MIN
TC= 25°C
11.5
11.4
0.9
ENOB
Effective number of bits
RMS idle channel noise
TC = TC,MAX
TC= TC,MIN
TC= 25°C
Bits
fIN = 70 MHz
TC = TC,MAX
TC= TC,MIN
Input pins tied together
LSB
DIGITAL CHARACTERISTICS (Unchanged after 100 kRad)
Typical values at TC = 25 °C, Over full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, AVDD = 5 V, DRVDD = 3.3 V
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Digital Outputs
Low-level output voltage
High-level output voltage
Output capacitance
DMID
CLOAD = 10 pF(1)
CLOAD = 10 pF(1)
0.1
3.2
3
0.6
1.8
V
V
2.6
pF
V
1.65
(1) Equivalent capacitance to ground of (load + parasitics of transmission lines)
6
Submit Documentation Feedback
Copyright © 2008–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS5424-SP
ADS5424-SP
www.ti.com
SLWS194B –MAY 2008–REVISED MARCH 2012
TIMING CHARACTERISTICS(1)(Unchanged after 100 kRad)
Typical values at TC = 25°C, Over full temperature range, AVDD = 5 V, DRVDD = 3.3 V, sampling rate = 105 MSPS
PARAMETER
MI
N
TYP MAX UNIT
Aperture Time
tA
Aperture delay
500
150
50
ps
fs
tJ
Clock slope independent aperture uncertainty (jitter)
Clock slope dependent jitter factor
kJ
μV
Clock Input
tCLK
Clock period
9.5
4.75
4.75
ns
ns
ns
tCLKH
Clock pulse width high
Clock pulse width low
tCLKL
Clock to DataReady (DRY)
tDR
Clock rising 50% to DRY falling 50%
Clock rising 50% to DRY rising 50%
2.2
7.0
3.0
4.7 ns
ns
tDR
+
tC_DR
tCLKH
tC_DR_50%
Clock rising 50% to DRY rising 50% with 50% duty cycle
clock
7.8
9.5 ns
Clock to DATA, OVR(2)
tr
tf
Data VOL to data VOH (rise time)
Data VOH to data VOL (fall time)
0.6
0.6
ns
ns
Cycl
es
L
Latency
3
Valid DATA(3) to clock 50% with 50% duty cycle clock
(setup time)
Clock 50% to invalid DATA(3) (hold time)
tsu_c
1.8
2.6
3.6
4.1
ns
ns
th_c
DataReady (DRY)/DATA, OVR(2)
Valid DATA(3) to DRY 50% with 50% duty cycle clock
(setup time)
DRY 50% to invalid DATA(3) with 50% duty cycle clock
(hold time)
tsu(DR)_50%
th(DR)_50%
0.9
3.9
1.40
6.3
ns
ns
(1) All values obtained from design and characterization.
(2) Data is updated with clock rising edge or DRY falling edge.
(3) See VOH and VOL levels.
Copyright © 2008–2012, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Link(s): ADS5424-SP
ADS5424-SP
SLWS194B –MAY 2008–REVISED MARCH 2012
www.ti.com
t
A
N+3
N
AIN
N+1
N+2
N+4
t
t
CLKL
t
CLKH
CLK
CLK, CLK
N + 1
N + 2
N + 3
N + 4
N
t
h(C)
t
t
su(C)
C_DR
D[13:0], OVR
DRY
N−3
N−2
N−1
N
t
t
h(DR)
su(DR)
t
r
t
f
t
DR
Figure 1. Timing Diagram
8
Submit Documentation Feedback
Copyright © 2008–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS5424-SP
ADS5424-SP
www.ti.com
SLWS194B –MAY 2008–REVISED MARCH 2012
DEVICE INFORMATION
HFG PACKAGE
(TOP VIEW)
52 51 50 49 48 47 46 45 44 43 42 41 40
DRVDD
GND
1
39
D3
2
38
37
36
35
34
33
32
31
30
29
28
27
D2
3
VREF
GND
D1
D0 (LSB)
4
5
CLK
DMID
GND
6
CLK
GND
AVDD
AVDD
DRVDD
7
8
OVR
DNC
AVDD
9
10
11
12
13
GND
AIN
GND
AVDD
AIN
GND
GND
14 15 16 17 18 19 20 21 22 23 24 25 26
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
3.3 V power supply, digital output stage only
NAME
NO.
DRVDD
1, 33, 43
2, 4, 7, 10, 13, 15, 17,
GND
19, 21, 23, 25, 27, 29, Ground
34, 42
VREF
CLK
3
5
6
2.4 V reference. Bypass to ground with a 0.1 μF microwave chip capacitor.
Clock input. Conversion initiated on rising edge
Complement of CLK, differential input
CLK
8, 9, 14, 16, 18, 22, 26,
28, 30
AVDD
5 V analog power supply
AIN
11
Analog input
AIN
12
Complement of AIN, differential analog input
C1
20
Internal voltage reference. Bypass to ground with a 0.1 μF chip capacitor.
Internal voltage reference. Bypass to ground with a 0.1 μF chip capacitor.
Do not connect
C2
24
DNC
31
OVR
32
Overrange bit. A logic level high indicates the analog input exceeds full scale.
Output data voltage midpoint. Approximately equal to (DVCC)/2
Digital output bit (least significant bit); two's complement
Digital output bits in two's complement
DMID
35
D0 (LSB)
D1–D5, D6–D12
D13 (MSB)
DRY
36
37–41, 44–50
51
52
Digital output bit (most significant bit); two's complement
Data ready output
Copyright © 2008–2012, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Link(s): ADS5424-SP
ADS5424-SP
SLWS194B –MAY 2008–REVISED MARCH 2012
www.ti.com
THERMAL CHARACTERISTICS
PARAMETER
TEST CONDITIONS
TYP
21.81
0.849
UNIT
°C/W
°C/W
RθJA
RθJC
Junction-to-free-air thermal resistance
Junction-to-case thermal resistance
Board Mounted, Per JESD 51-5 methodology
MIL-STD-883 Test Method 1012
THERMAL NOTES
This CQFP package has built-in vias that electrically and thermally connect the bottom of the die to a pad on the
bottom of the package. To efficiently remove heat and provide a low-impedance ground path, a thermal land is
required on the surface of the PCB directly underneath the body of the package. During normal surface mount
flow solder operations, the heat pad on the underside of the package is soldered to this thermal land creating an
efficient thermal path. Normally, the PCB thermal land has a number of thermal vias within it that provide a
thermal path to internal copper areas (or to the opposite side of the PCB) that provide for more efficient heat
removal. TI typically recommends a 16-mm2 board-mount thermal pad. This allows maximum area for thermal
dissipation, while keeping leads away from the pad area to prevent solder bridging. A sufficient quantity of
thermal/electrical vias must be included to keep the device within recommended operating conditions. This pad
must be electrically at ground potential.
1000.00
100.00
Electromigration Fail Mode
10.00
1.00
80
90
100
110
120
130
140
150
160
170
180
Continuous Tj (°C)
Figure 2. ADS5424 Estimated Device Life at Elevated Temperatures Electromigration Fail Mode
10
Submit Documentation Feedback
Copyright © 2008–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS5424-SP
ADS5424-SP
www.ti.com
SLWS194B –MAY 2008–REVISED MARCH 2012
DEFINITION OF SPECIFICATIONS
Temperature Drift
Analog Bandwidth
The temperature drift coefficient (with respect to gain
error and offset error) specifies the change per
degree celsius of the parameter from TMIN or TMAX. It
is computed as the maximum variation of that
parameter over the whole temperature range divided
The analog input frequency at which the power of the
fundamental is reduced by 3 dB with respect to the
low-frequency value
Aperture Delay
by TMAX – TMIN
.
The delay in time between the rising edge of the input
sampling clock and the actual time at which the
sampling occurs
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS)
to the noise floor power (PN), excluding the power at
dc and in the first five harmonics.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay
PS
SNR + 10Log
10 PN
Clock Pulse Width/Duty Cycle
The duty cycle of a clock signal is the ratio of the time
the clock signal remains at a logic high (clock pulse
width) to the period of the clock signal. Duty cycle is
typically expressed as a percentage. A perfect
differential sine wave clock results in a 50% duty
cycle.
SNR is given either in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full scale) when the
power of the fundamental is extrapolated to the
converter’s full-scale range.
Maximum Conversion Rate
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental
(PS) to the power of all the other spectral components
including noise (PN) and distortion (PD), but excluding
dc.
PS
SINAD + 10Log
10 PN ) PD
The maximum sampling rate at which certified
operation is given. All parametric testing is performed
at this sampling rate unless otherwise noted.
Minimum Conversion Rate
The minimum sampling rate at which the ADC
functions
Differential Nonlinearity (DNL)
SINAD is given either in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to Full Scale) when the
power of the fundamental is extrapolated to the
converter’s full-scale range.
An ideal ADC exhibits code transitions at analog input
values spaced exactly 1 LSB apart. DNL is the
deviation of any single step from this ideal value,
measured in units of LSB.
Integral Nonlinearity (INL)
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS)
to the power of the first five harmonics (PD).
PS
THD + 10Log
10 PD
INL is the deviation of the ADC transfer function from
a best-fit line determined by a least-squares curve fit
of that transfer function, measured in units of LSB.
Gain Error
Gain error is the deviation of the ADC actual input
full-scale range from its ideal value. Gain error is
given as a percentage of the ideal input full-scale
range.
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR)
The ratio of the power of the fundamental to the
highest other spectral component (either spur or
harmonic). SFDR is typically given in units of dBc (dB
to carrier).
Offset Error
The offset error is the difference, given in number of
LSBs, between the ADC's actual value average idle
channel output code and the ideal average idle
channel output code. This quantity is often mapped
into mV.
Two-Tone Intermodulation Distortion
IMD3 is the ratio of the power of the fundamental (at
frequencies f1, f2) to the power of the worst spectral
component at either frequency 2f1 – f2 or 2f2 – f1).
IMD3 is given either in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full scale) when it is
referred to the full-scale range
Copyright © 2008–2012, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Link(s): ADS5424-SP
ADS5424-SP
SLWS194B –MAY 2008–REVISED MARCH 2012
www.ti.com
TYPICAL CHARACTERISTICS
Typical values are at TA = 25°C, AVDD = 5 V, DRVDD = 3.3 V, differential input amplitude = –1 dBFS,
sampling rate = 105 MSPS, 3 VPP sinusoidal clock, 50% duty cycle, 16k FFT points (unless otherwise noted)
AC PERFORMANCE
vs
AC PERFORMANCE
vs
INPUT AMPLITUDE (70 MHz)
INPUT AMPLITUDE (170 MHz)
fS = 92.16 MSPS
fIN = 70 MHz
fS = 92.16 MSPS
fIN = 170 MHz
AIN - Input Amplitude - dB
AIN - Input Amplitude - dB
Figure 3.
Figure 4.
AC PERFORMANCE
vs
AC PERFORMANCE
vs
CLOCK LEVEL (70 MHz)
CLOCK LEVEL (170 MHz)
Figure 5.
Figure 6.
12
Submit Documentation Feedback
Copyright © 2008–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS5424-SP
ADS5424-SP
www.ti.com
SLWS194B –MAY 2008–REVISED MARCH 2012
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, AVDD = 5 V, DRVDD = 3.3 V, differential input amplitude = –1 dBFS,
sampling rate = 105 MSPS, 3 VPP sinusoidal clock, 50% duty cycle, 16k FFT points (unless otherwise noted)
SPURIOUS-FREE DYNAMIC RANGE
SIGNAL-TO-NOISE RATIO
vs
vs
SUPPLY VOLTAGE AND AMBIENT TEMPERATURE
SUPPLY VOLTAGE AND AMBIENT TEMPERATURE
DRVDD - Supply Voltage - V
DRVDD - Supply Voltage - V
Figure 7.
Figure 8.
SNR
SFDR
vs
vs
INPUT FREQUENCY and SAMPLING FREQUENCY
INPUT FREQUENCY and SAMPLING FREQUENCY
Figure 9.
Figure 10.
Copyright © 2008–2012, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Link(s): ADS5424-SP
ADS5424-SP
SLWS194B –MAY 2008–REVISED MARCH 2012
www.ti.com
EQUIVALENT CIRCUITS
AV
DRV
DD
DD
AIN
BUF
T/H
500 Ω
V
REF
BUF
AV
DD
500 Ω
AIN
BUF
T/H
Figure 11. Analog Input
Figure 12. Digital Output
AV
AV
DD
DD
+
25 Ω
CLK
V
REF
−
Bandgap
1.2 kΩ
1 kΩ
Clock Buffer
1.2 kΩ
Bandgap
AV
DD
1 kΩ
CLK
Figure 13. Clock Input
Figure 14. Reference
14
Submit Documentation Feedback
Copyright © 2008–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS5424-SP
ADS5424-SP
www.ti.com
SLWS194B –MAY 2008–REVISED MARCH 2012
EQUIVALENT CIRCUITS (continued)
AV
DRV
DD
DD
10 kΩ
−
+
I
I
P
OUT
DMID
DAC
M
OUT
Bandgap
C1, C2
10 kΩ
Figure 15. Decoupling Pin
Figure 16. DMID Generation
Copyright © 2008–2012, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Link(s): ADS5424-SP
ADS5424-SP
SLWS194B –MAY 2008–REVISED MARCH 2012
www.ti.com
APPLICATION INFORMATION
THEORY OF OPERATION
The ADS5424 is a 14-bit, 105-MSPS, monolithic pipeline analog to digital converter. Its bipolar analog core
operates from a 5-V supply, while the output uses 3.3-V supply for compatibility with the CMOS family. The
conversion process is initiated by the rising edge of the external input clock. At that instant, the differential input
signal is captured by the input track and hold (T&H) and the input sample is sequentially converted by a series of
small resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the
falling clock edges are used to propagate the sample through the pipeline every half clock cycle. This process
results in a data latency of three clock cycles, after which the output data is available as a 14 bit parallel word,
coded in binary 2's complement format.
INPUT CONFIGURATION
The analog input for the ADS5424 (see Figure 11) consists of an analog differential buffer followed by a bipolar
track-and-hold. The analog buffer isolates the source driving the input of the ADC from any internal switching.
The input common mode is set internally through a 500-Ω resistor connected from 2.4 V to each of the inputs.
This results in a differential input impedance of 1 kΩ.
For a full-scale differential input, each of the differential lines of the input signal (pins 11 and 12) swings
symmetrically between 2.4 ±0.55 V and 2.4 –0.55 V. This means that each input is driven with a signal of up to
2.4 ±0.55 V, so that each input has a maximum signal swing of 1.1 VPP for a total differential input signal swing of
2.2 VPP. The maximum swing is determined by the internal reference voltage generator eliminating any external
circuitry for this purpose.
The ADS5424 obtains optimum performance when the analog inputs are driven differentially. The circuit in
Figure 17 shows one possible configuration using an RF transformer with termination either on the primary or on
the secondary of the transformer. If voltage gain is required, a step-up transformer can be used. For higher gains
that would require impractical higher turn ratios on the transformer, a single-ended amplifier driving the
transformer can be used (see Figure 18). Another circuit optimized for performance would be the one on
Figure 19, using the THS4304 or the OPA695. Texas Instruments has shown excellent performance on this
configuration up to 10-dB gain with the THS4304 and at 14-dB gain with the OPA695. For the best performance,
they need to be configured differentially after the transformer (as shown) or in inverting mode for the OPA695
(see SBAA113); otherwise, HD2 from the op amps limits the useful frequency.
R0
Z0
W
50
W
50
AIN
1:1
R
50
AC Signal
Source
ADS5424M
W
AIN
ADT1−1WT
Figure 17. Converting a Single-Ended Input to a Differential Signal Using RF Transformers
5 V
−5 V
R
100 Ω
S
0.1 µF
+
V
IN
R
R
1:1
IN
AIN
OPA695
−
R
100 Ω
T
ADS5424M
AIN
C
IN
IN
1000 µF
R
1
400 Ω
A
V
= 8V/V
R
2
(18 dB)
57.5 Ω
Figure 18. Using the OPA695 With the ADS5424
16
Submit Documentation Feedback
Copyright © 2008–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS5424-SP
ADS5424-SP
www.ti.com
SLWS194B –MAY 2008–REVISED MARCH 2012
R
G
R
F
CM
5 V
−
THS4304
+
1:1
V
IN
AIN
CM
49.9 Ω
ADS5424M
V
5 V
From
50 Ω
AIN
REF
+
Source
THS4304
−
CM
R
G
R
F
CM
Figure 19. Using the THS4304 With the ADS5424
Texas Instruments offers a wide selection of single-ended operational amplifiers (including the THS3201,
THS3202 and OPA847) that can be selected depending on the application. An RF gain block amplifier, such as
Texas Instrument's THS9001, also can be used with an RF transformer for high input frequency applications. For
applications requiring dc-coupling with the signal source, instead of using a topology with three single-ended
amplifiers, a differential input/differential output amplifier like the THS4509 (see Figure 20) can be used, which
minimizes board space and reduces the number of components.
V
IN
From
50 Ω
Source
100 Ω
348 Ω
+5V
14-Bit
69.8 Ω
105 MSPS
225 Ω
225 Ω
0.22 µF
100 Ω
A
IN
2.7 pF
ADS5424M
THS4509
CM
A
IN
V
REF
49.9 Ω
69.8 Ω
49.9 Ω
0.1 µF
0.22 µF
0.22 µF
0.1 µF
348 Ω
Figure 20. Using the THS4509 With the ADS5424
On this configuration, the THS4509 amplifier circuit provides 10-dB of gain, converts the single-ended input to
differential, and sets the proper input common-mode voltage to the ADS5424.
The 225-Ω resistors and 2.7-pF capacitor between the THS4509 outputs and ADS5424 inputs (along with the
input capacitance of the ADC) limit the bandwidth of the signal to about 100 MHz (–3 dB).
For this test, an Agilent signal generator is used for the signal source. The generator is an ac-coupled 50-Ω
source. A bandpass filter is inserted in series with the input to reduce harmonics and noise from the signal
source.
Input termination is accomplished via the 69.8-Ω resistor and 0.22-μF capacitor to ground in conjunction with the
input impedance of the amplifier circuit. A 0.22-μF capacitor and 49.9-Ω resistor is inserted to ground across the
69.8-Ω resistor and 0.22-μF capacitor on the alternate input to balance the circuit.
Gain is a function of the source impedance, termination, and 348-Ω feedback resistor. See the THS4509 data
sheet for further component values to set proper 50-Ω termination for other common gains.
Copyright © 2008–2012, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Link(s): ADS5424-SP
ADS5424-SP
SLWS194B –MAY 2008–REVISED MARCH 2012
www.ti.com
Because the ADS5424 recommended input common-mode voltage is 2.4 V, the THS4509 is operated from a
single power supply input with VS+ = 5 V and VS– = 0 V (ground). This maintains maximum headroom on the
internal transistors of the THS4509.
CLOCK INPUTS
The ADS5424 clock input can be driven with either a differential clock signal or a single-ended clock input, with
little or no difference in performance between both configurations. In low-input-frequency applications, where
jitter may not be a big concern, the use of single-ended clock (see Figure 21) could save cost and board space
without any trade-off in performance. When driven on this configuration, it is best to connect CLKM (pin 11) to
ground with a 0.01-μF capacitor, while CLKP is ac-coupled with a 0.01-μF capacitor to the clock source, as
shown in Figure 22.
CLK
Square Wave or
Sine Wave
0.01 µF
0.01 µF
ADS5424M
CLK
Figure 21. Single-Ended Clock
0.1 µF
1:4
Clock
CLK
Source
ADS5424
M
MA3X71600LCT−ND
CLK
Figure 22. Differential Clock
For jitter sensitive applications, the use of a differential clock has advantages (as with any other ADCs) at the
system level. The first advantage is that it allows for common-mode noise rejection at the PCB level. A further
analysis (see Clocking High Speed Data Converters, SLYT075) reveals one more advantage. The following
formula describes the different contributions to clock jitter:
(Jittertotal)2 = (EXT_jitter)2 + (ADC_jitter)2 = (EXT_jitter)2 + (ADC_int)2 + (K/clock_slope)2
The first term represents the external jitter, coming from the clock source, plus noise added by the system on the
clock distribution, up to the ADC. The second term is the ADC contribution, which can be divided in two portions.
The first does not depend directly on any external factor. The second contribution is a term inversely proportional
to the clock slope. The faster the slope, the smaller this term will be. As an example, the ADC jitter contribution
could be computed from a sinusoidal input clock of 3-Vpp amplitude and Fs = 80 MSPS:
ADC_jitter = sqrt ((150 fs)2 + (5 × 10–5/(1.5 × 2 × PI × 80 × 106))2) = 164 fs
The use of differential clock allows for the use of bigger clock amplitudes without exceeding the absolute
maximum ratings. This, on the case of sinusoidal clock, results on higher slew rates, which minimize the impact
of the jitter factor inversely proportional to the clock slope.
Figure 23 shows this approach. The back-to-back Schottky can be added to limit the clock amplitude in cases
where this would exceed the absolute maximum ratings, even when using a differential clock.
18
Submit Documentation Feedback
Copyright © 2008–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS5424-SP
ADS5424-SP
www.ti.com
SLWS194B –MAY 2008–REVISED MARCH 2012
100 nF
MC100EP16DT
Q
100 nF
100 nF
CLK
D
D
V
BB
Q
ADS5424M
CLK
100 nF
499 W
499 W
50 Ω
50 Ω
100 nF
113 Ω
Figure 23. Differential Clock Using PECL Logic
Another possibility is the use of a logic based clock, as PECL. In this case, the slew rate of the edges will most
likely be much higher than the one obtained for the same clock amplitude based on a sinusoidal clock. This
solution would minimize the effect of the slope dependent ADC jitter. Nevertheless, observe that for the
ADS5424, this term is small and has been optimized. Using logic gates to square a sinusoidal clock may not
produce the best results as logic gates, which may not have been optimized to act as comparators, adding too
much jitter while squaring the inputs.
The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1-kΩ resistors. It is
recommended to use an ac coupling, but if for any reason, this scheme is not possible, due to, for instance,
asynchronous clocking, the ADS5424 presents a good tolerance to clock common-mode variation.
Additionally, the internal ADC core uses both edges of the clock for the conversion process. This means that,
ideally, a 50% duty cycle should be provided.
DIGITAL OUTPUTS
The ADC provides 14 data outputs (D13 to D0, with D13 being the MSB and D0 the LSB), a data-ready signal
(DRY, pin 52), and an out-of-range indicator (OVR, pin 32) that equals 1 when the output reaches the full-scale
limits.
The output format is two's complement. When the input voltage is at negative full scale (around –1.1-V
differential), the output will be, from MSB to LSB, 10 0000 0000 0000. Then, as the input voltage is increased,
the output switches to 10 0000 0000 0001, 10 0000 0000 0010 and so on until 11 1111 1111 1111 right before
mid-scale (when both inputs are tight together if we neglect offset errors). Further increases on input voltage,
outputs the word 00 0000 0000 0000, to be followed by 00 0000 0000 0001, 00 0000 0000 0010 and so on until
reaching 01 1111 1111 1111 at full-scale input (1.1-V differential).
Although the output circuitry of the ADS5424 has been designed to minimize the noise produced by the
transients of the data switching, care must be taken when designing the circuitry reading the ADS5424 outputs.
Output load capacitance should be minimized by minimizing the load on the output traces, reducing their length
and the number of gates connected to them, and by the use of a series resistor with each pin. Typical numbers
on the data sheet tables and graphs are obtained with 100-Ω series resistor on each digital output pin, followed
by a 74AVC16244 digital buffer as the one used in the evaluation board.
POWER SUPPLIES
The use of low noise power supplies with adequate decoupling is recommended, being the linear supplies the
first choice versus switched ones, which tend to generate more noise components that can be coupled to the
ADS5424.
Copyright © 2008–2012, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Link(s): ADS5424-SP
ADS5424-SP
SLWS194B –MAY 2008–REVISED MARCH 2012
www.ti.com
The ADS5424 uses two power supplies. For the analog portion of the design, a 5-V AVDD is used, while for the
digital outputs supply (DRVDD), we recommend the use of 3.3 V. All the ground pins are marked as GND,
although AGND pins and DRGND pins are not tied together inside the package. Customers willing to experiment
with different grounding schemes should know that AGND pins are 4, 7, 10, 13, 15, 17, 19, 21, 23, 25, 27, and
29, while DRGND pins are 2, 34, and 42. We recommend that both grounds are tied together externally, using a
common ground plane. That is the case on the production test boards and modules provided to customer for
evaluation. To obtain the best performance, user should lay out the board to assure that the digital return
currents do not flow under the analog portion of the board. This can be achieved without splitting the board and
with careful component placement and increasing the number of vias and ground planes.
Finally, notice that the metallic heat sink under the package is also connected to analog ground.
LAYOUT INFORMATION
The evaluation board represents a good guideline of how to lay out the board to obtain the maximum
performance out of the ADS5424. General design rules for use of multilayer boards, single ground plane for both,
analog and digital ADC ground connections, and local decoupling ceramic chip capacitors should be applied. The
input traces should be isolated from any external source of interference or noise, including the digital outputs as
well as the clock traces. Clock also should be isolated from other signals, especially on applications where low
jitter is required, as high IF sampling.
Besides performance oriented rules, special care has to be taken when considering the heat dissipation out of
the device. The thermal package information describes the TJA values obtained on the different configurations.
20
Submit Documentation Feedback
Copyright © 2008–2012, Texas Instruments Incorporated
Product Folder Link(s): ADS5424-SP
PACKAGE OPTION ADDENDUM
www.ti.com
8-Mar-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
5962-0720601VXC
ACTIVE
CFP
HFG
52
1
TBD
Call TI
N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ADS5424-SP :
Catalog: ADS5424
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Audio
Applications
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
www.ti.com/security
Medical
Logic
Security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense www.ti.com/space-avionics-defense
microcontroller.ti.com
www.ti-rfid.com
Video and Imaging
www.ti.com/video
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community Home Page
e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明