ADS5444HFG/EM [TI]
QMLV、陶瓷、13 位、单通道、250MSPS ADC | HFG | 84 | 25 to 25;
| 型号： | ADS5444HFG/EM |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QMLV、陶瓷、13 位、单通道、250MSPS ADC | HFG | 84 | 25 to 25 转换器 模数转换器 |
| 文件： | 总23页 (文件大小：679K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS5444-SP
www.ti.com
SGLS391B –MARCH 2008–REVISED FEBRUARY 2012
CLASS V, 13 BIT, 250 MSPS ANALOG-TO-DIGITAL CONVERTER
Check for Samples: ADS5444-SP
1
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
13 Bit Resolution
APPLICATIONS
250 MSPS Sample Rate
•
•
•
•
•
Test and Measurement
SNR = 67.6 dBc at 230 MHz IF and 250 MSPS
SFDR = 74.0 dBc at 230 MHz IF and 250 MSPS
2.2 VPP Differential Input Voltage
Fully Buffered Analog Inputs
5 V Analog Supply Voltage
Software-Defined Radio
Multichannel Base Station Receivers
Base Station Tx Digital Predistortion
Communications Instrumentation
RELATED PRODUCTS
LVDS Compatible Outputs
•
•
•
ADS5424 - 14 Bit, 105 MSPS ADC
ADS5423 - 14 Bit, 80 MSPS ADC
ADS5440 - 13 Bit, 210 MSPS ADC
Total Power Dissipation: 2 W
Offset Binary Output Format
Pin Compatible With the ADS5440
Military Temperature Range
( –55°C to 125°C Tcase
)
DESCRIPTION/ORDERING INFORMATION
The ADS5444 is a 13 bit 250 MSPS analog-to-digital converter (ADC) that operates from a 5 V supply, while
providing LVDS-compatible digital outputs from a 3.3 V supply. The ADS5444 input buffer isolates the internal
switching of the onboard track and hold (T&H) from disturbing the signal source. An internal reference generator
is also provided to further simplify the system design. The ADS5444 has outstanding low noise and linearity over
input frequency.
AV
DD
DV
DD
AIN
AIN
+
+
Σ
Σ
A1
TH1
TH2
A2
TH3
A3
ADC3
−
−
ADC1
DAC1
ADC2
DAC2
VREF
Reference
5
5
5
Digital Error Correction
CLK
CLK
Timing
OVR
OVR
DRY
DRY
D[12:0]
GND
B0061-01
The ADS5444 is available in a 84 pin ceramic nonconductive tie-bar package (HFG). The ADS5444 is built on a
state-of-the-art Texas Instruments complementary bipolar process (BiCom3X) and is specified over the full
military temperature range (–55°C to 125°C Tcase).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADS5444-SP
SGLS391B –MARCH 2008–REVISED FEBRUARY 2012
www.ti.com
ORDERING INFORMATION
TEMPERATURE
PACKAGE(1) (2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
5962-0720701VXC
ADS5444MHFG-V
ADS5444HFG/EM(3)
EVAL ONLY
–55°C to 125°C Tcase
5962-0720701VXC
ADS5444HFGMPR
84/ HFG
25°C
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(3) These units are intended for engineering evaluation only. They are processed to a non-compliant flow (e.g. No Burn-In, etc.) and are
tested to a temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts
are not warranted for performance over the full MIL specified temperature range of -55°C to 125°C or operating life.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating temperature range (unless otherwise noted)(1)
VALUE/UNIT
AVDD to GND
6 V
5 V
Supply voltage
DRVDD to GND
Analog input to GND
Clock input to GND
CLK to CLK
–0.3 V to AVDD + 0.3 V
–0.3 V to AVDD + 0.3 V
±2.5 V
Digital data output to GND
–0.3 V to DRVDD + 0.3 V
–55°C to 125°C
150°C
TC
TJ
Characterized case operating temperature range
Maximum junction temperature
Storage temperature range
Tstg
–65°C to 150°C
2.5 kV
ESD Human Body Model (HBM)
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only and functional operation of the device at these or any other conditions beyond
those specified is not implied.
2
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ADS5444-SP
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SGLS391B –MARCH 2008–REVISED FEBRUARY 2012
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
SUPPLIES
AVDD
Analog supply voltage
4.75
3
5
5.25
3.6
V
V
DRVDD
Output driver supply voltage
3.3
ANALOG INPUT
Differential input range
Input common mode
CLOCK INPUT
ADCLK input sample rate (sine wave)
2.2
2.4
VPP
V
VCM
10
250 MSPS
VPP
Clock amplitude, differential sine wave
Clock duty cycle
3
50%
TC
Operating case temperature
–55
125
°C
ELECTRICAL CHARACTERISTICS
Typical values at TC = 25°C, full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 250 MSPS, 50%
clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1 dBFS differential input, and 3 VPP differential clock (unless otherwise noted)
PARAMETER
Resolution
ANALOG INPUTS
TEST CONDITIONS
MIN
TYP
MAX UNIT
13
Bits
Differential input range
Differential input resistance (DC)
Differential input capacitance
Analog input bandwidth
2.2
1
Vpp
kΩ
1.5
800
pF
MHz
INTERNAL REFERENCE VOLTAGE
VREF
DYNAMIC ACCURACY
No missing codes
Reference voltage
2.38
2.4
2.42
V
Assured
DNL
INL
Differential linearity error
fIN = 100 MHz
fIN = 100 MHz
Full temp range
–0.98
–2.8
–4.8
–0.6
±0.4
2
2.8
4.8
LSB
LSB
TC = 25°C and TC,MAX
TC = TC,MIN
Integral linearity error
Offset error
Full temp range
0.6 %FS
Offset temperature coefficient
Gain error
0.0005
%FS/°C
Full temp range
–5
5
%FS
Gain temperature coefficient
–0.02
%FS/°C
POWER SUPPLY
IAVDD
Analog supply current
340
80
2
410
100
mA
mA
W
IDRVDD
Output buffer supply current
Power dissipation
VIN = full scale, fIN = 170 MHz, FS = 250 MSPS
2.29
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SGLS391B –MARCH 2008–REVISED FEBRUARY 2012
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ELECTRICAL CHARACTERISTICS (continued)
Typical values at TC = 25°C, full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 250 MSPS, 50%
clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1 dBFS differential input, and 3 VPP differential clock (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DYNAMIC AC CHARACTERISTICS
fIN = 10 MHz
TC = 25°C
TC = TC,MAX
TC = TC,MIN
68.0
66.8
63.2
69.1
fIN = 70 MHz
fIN = 100 MHz
69.0
68.9
TC = 25°C
TC = TC,MAX
TC = TC,MIN
TC = 25°C
TC = TC,MAX
TC = TC,MIN
67.3
66.5
62.1
66.5
66.1
60.8
SNR
SFDR
HD2
Signal-to-noise ratio
dBc
fIN = 170 MHz
68.4
fIN = 230 MHz
fIN = 300 MHz
fIN = 400 MHz
67.6
66.5
65.5
84.0
TC = 25°C
TC = TC,MAX
TC = TC,MIN
75.0
74.0
75.0
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
71.8
67.4
TC = 25°C
TC = TC,MAX
TC = TC,MIN
TC = 25°C
TC = TC,MAX
TC = TC,MIN
62.0
74.5
63.0
63.0
65.0
59.0
Spurious free dynamic range
dBc
70.0
fIN = 230 MHz
fIN = 300 MHz
fIN = 400 MHz
fIN = 10 MHz
74.0
65.8
60.5
92.0
TC = 25°C
TC = TC,MAX
TC = TC,MIN
75.0
74.0
76.5
fIN = 70 MHz
fIN = 100 MHz
71.8
67.4
TC = 25°C
TC = TC,MAX
TC = TC,MIN
TC = 25°C
TC = TC,MAX
TC = TC,MIN
62.0
76.0
63.0
63.0
65.0
59.0
Second harmonic
dBc
fIN = 170 MHz
73.0
fIN = 230 MHz
fIN = 300 MHz
fIN = 400 MHz
74.0
65.8
60.6
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SGLS391B –MARCH 2008–REVISED FEBRUARY 2012
ELECTRICAL CHARACTERISTICS (continued)
Typical values at TC = 25°C, full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 250 MSPS, 50%
clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1 dBFS differential input, and 3 VPP differential clock (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
81.0
78.5
TYP
MAX UNIT
TC = 25°C
84.0
fIN = 10 MHz
Full temp range
fIN = 70 MHz
fIN = 100 MHz
72.8
78.4
TC = 25°C
TC = TC,MAX
TC = TC,MIN
TC = 25°C
TC = TC,MAX
TC = TC,MIN
72.0
74.5
65.0
65.0
69.0
63.0
HD3
Third harmonic
dBc
fIN = 170 MHz
70.1
fIN = 230 MHz
fIN = 300 MHz
fIN = 400 MHz
94.0
77.7
64.1
89.0
TC = 25°C
TC = TC,MAX
TC = TC,MIN
80.0
81.0
75.0
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
82.7
86.6
TC = 25°C
TC = TC,MAX
TC = TC,MIN
TC = 25°C
TC = TC,MAX
TC = TC,MIN
74.0
78.0
69.0
70.0
78.0
64.0
Worst other harmonic/spur (other
than HD2 and HD3)
dBc
fIN = 170 MHz
88.2
fIN = 230 MHz
fIN = 300 MHz
fIN = 400 MHz
81.8
83.6
82.0
83.0
TC = 25°C
TC = TC,MAX
TC = TC,MIN
74.5
73.0
74.0
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
68.9
67.0
TC = 25°C
TC = TC,MAX
TC = TC,MIN
TC = 25°C
TC = TC,MAX
TC = TC,MIN
61.5
73.0
60.0
62.0
63.5
58.0
THD
Total harmonic distortion
dBc
fIN = 170 MHz
68.2
fIN = 230 MHz
fIN = 300 MHz
fIN = 400 MHz
73.2
65.5
59.0
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ELECTRICAL CHARACTERISTICS (continued)
Typical values at TC = 25°C, full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 250 MSPS, 50%
clock duty cycle, AVDD = 5 V, DRVDD = 3.3 V, –1 dBFS differential input, and 3 VPP differential clock (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TC = 25°C
MIN
67.7
66.4
62.9
TYP
MAX UNIT
69.2
fIN = 10 MHz
TC = TC,MAX
TC = TC,MIN
fIN = 70 MHz
fIN = 100 MHz
69.2
68.9
TC = 25°C
TC = TC,MAX
TC = TC,MIN
TC = 25°C
TC = TC,MAX
TC = TC,MIN
62.2
66.2
59.4
61.7
62.9
57.6
SINAD
Signal-to-noise and distortion
dBc
fIN = 170 MHz
68.3
fIN = 230 MHz
fIN = 300 MHz
fIN = 400 MHz
67.5
66.6
65.4
11.3
TC = 25°C
TC = TC,MAX
TC = TC,MIN
TC = 25°C
TC = TC,MAX
TC = TC,MIN
TC = 25°C
TC = TC,MAX
TC = TC,MIN
10.9
10.7
10.1
10.0
10.7
9.5
Bits
fIN = 10 MHz
fIN = 100 MHz
fIN = 170 MHz
11.3
11.2
0.4
ENOB
Effective number of bits
RMS idle channel noise
9.9
10.1
9.2
Inputs tied to common-mode
LSB
DIGITAL CHARACTERISTICS – LVDS DIGITAL OUTPUTS
Differential output voltage
247
452
1.25 1.375
mV
V
Output offset voltage
1.125
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SGLS391B –MARCH 2008–REVISED FEBRUARY 2012
TIMING CHARACTERISTICS
t
A
N+3
N
AIN
N+1
N+2
N+4
t
t
t
CLKL
CLK
CLKH
CLK, CLK
N + 1
N + 2
N + 3
N + 4
N
t
t
t
h_c
C_DR
su_c
D[12:0],
OVR, OVR
N−3
N−2
N−1
t
N
t
f
t
t
r
h_DR
su_DR
DRY, DRY
t
DR
T0073-01
Figure 1. Timing Diagram
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TIMING CHARACTERISTICS
Typical values at TC = 25°C, 50% clock duty cycle, sampling rate = 250 MSPS, AVDD = 5 V, DRVDD = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
500
200
4
MAX UNIT
ps
tA
tJ
Aperture delay
Clock slope independent aperture uncertainty (jitter)
Latency
fs RMS
cycles
Clock Input
tCLK
Clock period
4
2
2
ns
ns
ns
tCLKH
Clock pulse width high
Clock pulse width low
tCLKL
Clock to DataReady (DRY)
tDR
Clock rising to DataReady falling
1.1
3.1
ns
(1)
tC_DR
Clock rising to DataReady rising
Clock duty cycle = 50%
2.7
3.5
ns
Clock to DATA, OVR(2)
tr
Data rise time (20% to 80%)
0.6
0.6
3.1
0.2
ns
ns
ns
ns
tf
Data fall time(80% to 20%)
tsu_c
th_c
Data valid to clock (setup time)
Clock to invalid data (hold time)
DataReady (DRY)/DATA, OVR(2)
tsu(DR)
th(DR)
Data valid to DRY
DRY to invalid data
1.5
0.9
2
ns
ns
1.3
(1) tC_DR = tDR + tCLKH for clock duty cycles other than 50%
(2) Data is updated with clock falling edge or DRY rising edge.
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SGLS391B –MARCH 2008–REVISED FEBRUARY 2012
DEVICE INFORMATION
HFG PACKAGE
(TOP VIEW)
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
63
GND
DVDD
GND
AVDD
NC
1
D4
2
62
61
60
59
58
57
56
55
54
53
52
D4
3
D3
4
D3
5
D2
NC
6
D2
VREF
GND
AVDD
GND
CLK
7
D1
8
D1
9
GND
DVDD
D0
10
11
12
13
14
15
16
17
18
19
20
21
ADS5444
CLK
D0
GND
AVDD
AVDD
GND
AIN
51 NC
50
49
48
47
46
45
44
43
NC
NC
NC
NC
AIN
NC
GND
AVDD
GND
OVR
OVR
GND
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
AVDD
DVDD
NO.
4, 9, 14, 15, 20, 23,
25, 27, 29, 33, 37, 39, Analog power supply
41
2, 54, 70
Output driver power supply
1, 3, 8, 10, 13, 16, 19,
21, 22, 24, 26, 28, 30,
32, 34, 36, 38, 40, 42,
43, 55, 64, 69
GND
Ground
VREF
CLK
CLK
AIN
7
Reference voltage
11
12
17
18
Differential input clock (positive). Conversion initiated on rising edge.
Differential input clock (negative)
Differential input signal (positive)
AIN
Differential input signal (negative)
Over range indicator LVDS output. A logic high signals an analog input in excess of the
full-scale range.
OVR, OVR
44, 45
D0, D0
52, 53
56–63
65–68
LVDS digital output pair, least-significant bit (LSB)
LVDS digital output pairs
D1–D4, D1–D4
D5–D6, D5–D6
LVDS digital output pairs
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TERMINAL FUNCTIONS (continued)
TERMINAL
DESCRIPTION
NAME
NO.
71–80
D7–D11, D7–D11
D12, D12
DRY, DRY
NC
LVDS digital output pairs
81, 82
LVDS digital output pair, most-significant bit (MSB)
Data ready LVDS output pair
No connect
83, 84
5, 6, 31, 35, 46–51
THERMAL CHARACTERISTICS
PARAMETER
TEST CONDITIONS
TYP
21.813
0.849
UNIT
°C/W
°C/W
RθJA
Junction-to-free-air thermal resistance
Junction-to-case thermal resistance
Board mounted, per JESD 51-5 methodology
MIL-STD-883 Test Method 1012
RθJC
THERMAL NOTES
This CQFP package has built in vias that electrically and thermally connect the bottom of the die to a pad on the
bottom of the package. To efficiently remove heat and provide a low-impedance ground path, a thermal land is
required on the surface of the PCB directly underneath the body of the package. During normal surface mount
flow solder operations, the heat pad on the underside of the package is soldered to this thermal land creating an
efficient thermal path. Normally, the PCB thermal land has a number of thermal vias within it that provide a
thermal path to internal copper areas (or to the opposite side of the PCB) that provide for more efficient heat
removal. TI typically recommends an 11,9-mm2 board-mount thermal pad. This allows maximum area for thermal
dissipation, while keeping leads away from the pad area to prevent solder bridging. A sufficient quantity of
thermal/electrical vias must be included to keep the device within recommended operating conditions. This pad
must be electrically at ground potential.
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SGLS391B –MARCH 2008–REVISED FEBRUARY 2012
1000.00
100.00
10.00
1.00
Electromigration Fail Mode
`
80
90
100
110
120
130
Continuous Tj (°C)
140
150
160
170
180
Figure 2. ADS5444 Estimated Device Life at Elevated Temperatures Electromigration Fail Mode
DEFINITION OF SPECIFICATIONS
Analog Bandwidth The analog input frequency at which the power of the fundamental is reduced by 3 dB with
respect to the low frequency value.
Aperture Delay The delay in time between the rising edge of the input sampling clock and the actual time at
which the sampling occurs.
Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle The duty cycle of a clock signal is the ratio of the time the clock signal remains
at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a
percentage. A perfect differential sine wave clock results in a 50% duty cycle.
Maximum Conversion Rate The maximum sampling rate at which certified operation is given. All parametric
testing is performed at this sampling rate unless otherwise noted.
Minimum Conversion Rate The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions at analog input values spaced exactly 1
LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSB.
Integral Nonlinearity (INL) The INL is the deviation of the ADCs transfer function from a best fit line determined
by a least squares curve fit of that transfer function. The INL at each analog input value is the difference
between the actual transfer function and this best fit line, measured in units of LSB.
Gain Error The gain error is the deviation of the ADCs actual input full-scale range from its ideal value. The gain
error is given as a percentage of the ideal input full-scale range.
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DEFINITION OF SPECIFICATIONS (continued)
Offset Error Offset error is the deviation of output code from mid-code when both inputs are tied to
common-mode.
Temperature Drift Temperature drift (with respect to gain error and offset error) specifies the change from the
value at the nominal temperature to the value at TMIN or TMAX. It is computed as the maximum variation
the parameters over the whole temperature range divided by TMIN – TMAX
.
Signal-to-Noise Ratio (SNR) SNR is the ratio of the power of the fundamental (PS) to the noise floor power
(PN), excluding the power at dc and the first five harmonics.
P
S
SNR + 10log
10
P
N
(1)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the
fundamental is used as the reference, or dBFS (dB to full scale) when the power of the
fundamental is extrapolated to the converter’s full-scale range.
Signal-to-Noise and Distortion (SINAD) SINAD is the ratio of the power of the fundamental (PS) to the power
of all the other spectral components including noise (PN) and distortion (PD), but excluding dc.
P
S
SINAD + 10log
10
P
) P
N
D
(2)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the
fundamental is used as the reference, or dBFS (dB to full scale) when the power of the
fundamental is extrapolated to the converter’s full-scale range.
Effective Resolution Bandwidth The highest input frequency where the SNR (dB) is dropped by 3 dB for a
full-scale input amplitude.
Total Harmonic Distortion (THD) THD is the ratio of the power of the fundamental (PS) to the power of the first
five harmonics (PD).
P
S
THD + 10log
10
P
D
(3)
THD is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion IMD3 is the ratio of the power of the fundamental (at frequencies f1, f2)
to the power of the worst spectral component at either frequency 2f1 – f2 or 2f2 – f1). IMD3 is either given
in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference or
dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s full-scale
range.
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TYPICAL CHARACTERISTICS
AC Performance
vs
AC Performance
vs
Input Amplitude (100 MHz)
Input Amplitude (230 MHz)
Input Amplitude - dBFS
Input Amplitude - dBFS
Figure 3.
Figure 4.
SFDR
vs
SNR
vs
Clock Level
Clock Level
fIN = 230 MHz
Clock Amplitude - VP-P
Clock Amplitude - VP-P
Figure 5.
Figure 6.
SFDR
SNR
vs
vs
AVDD Across Temperture
AVDD Across Temperture
AVDD - Supply Voltage - V
AVDD - Supply Voltage - V
Figure 7.
Figure 8.
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SGLS391B –MARCH 2008–REVISED FEBRUARY 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
SFDR
SNR
vs
vs
DRVDD Across Temperture
DRVDD Across Temperture
DRVDD - Supply Voltage - V
DRVDD - Supply Voltage - V
Figure 9.
Figure 10.
SNR
vs
SFDR
vs
Input Frequency and Sampling Frequency
Input Frequency and Sampling Frequency
Figure 11.
Figure 12.
14
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ADS5444-SP
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SGLS391B –MARCH 2008–REVISED FEBRUARY 2012
APPLICATION INFORMATION
Theory of Operation
The ADS5444 is a 13 bit, 250 MSPS, monolithic pipeline analog-to-digital converter (ADC). Its bipolar analog
core operates from a 5 V supply, while the output uses a 3.3 V supply to provide LVDS compatible outputs. The
conversion process is initiated by the rising edge of the external input clock. At that instant, the differential input
signal is captured by the input track and hold (T&H) and the input sample is sequentially converted by a series of
small resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the
falling clock edges are used to propagate the sample through the pipeline every half clock cycle. This process
results in a data latency of four clock cycles, after which the output data is available as a 13 bit parallel word,
coded in offset binary format.
Input Configuration
The analog input for the ADS5444 consists of an analog differential buffer followed by a bipolar T&H. The analog
buffer isolates the source driving the input of the ADC from any internal switching. The input common mode is
set internally through a 500 Ω resistor connected from 2.4 V to each of the inputs. This results in a differential
input impedance of 1 kΩ.
For a full-scale differential input, each of the differential lines of the input signal (pins 17 and 18) swings
symmetrically between 2.4 + 0.55 V and 2.4 – 0.55 V. This means that each input has a maximum signal swing
of 1.1 VPP for a total differential input signal swing of 2.2 VPP. The maximum swing is determined by the internal
reference voltage generator eliminating the need for any external circuitry for this purpose.
The ADS5444 obtains optimum performance when the analog inputs are driven differentially. The circuit in
Figure 13 shows one possible configuration using an RF transformer with termination either on the primary or on
the secondary of the transformer. If voltage gain is required, a step up transformer can be used. For voltage
gains that would require an impractical transformer turn ratio, a single-ended amplifier driving the transformer is
shown in Figure 14.
Z
50 W
R
50 W
0
0
AIN
1 : 1
R
50 W
ADS5444
AC Signal
Source
AIN
ADT1-1WT
Figure 13. Converting a Single-Ended Input to a Differential Signal Using RF Transformers
5 V
−5 V
R
100 Ω
S
0.1 µF
+
V
IN
R
R
1:1
IN
AIN
ADS5444
AIN
OPA695
−
R
100 Ω
T
C
IN
IN
1000 µF
R
1
400 Ω
A
V
= 8V/V
R
2
(18 dB)
57.5 Ω
Figure 14. Using the OPA695 with the ADS5444
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V
IN
From
50 Ω
Source
100 Ω
348 Ω
+5V
13 Bit
250 MSPS
78.9 Ω
49.9 Ω
49.9 Ω
0.22 µF
100 Ω
A
IN
18 pF
ADS5444
THS4509
CM
A
IN
V
REF
49.9 Ω
78.9 Ω
49.9 Ω
0.22 µF
0.22 µF
0.1 µF
0.1 µF
348 Ω
Figure 15. Using the THS4509 with the ADS5444
Besides the OPA695, TI offers a wide selection of single-ended operational amplifiers that can be selected
depending on the application. An RF gain block amplifier, such as the TI THS9001, can also be used with an RF
transformer for high input frequency applications. For applications requiring dc-coupling with the signal source, a
differential input/differential output amplifier like the THS4509 (see Figure 15) is a good solution, as it minimizes
board space and reduces the number of components.
In this configuration, the THS4509 amplifier circuit provides 10 dB of gain, converts the single-ended input to
differential, and sets the proper input common-mode voltage to the ADS5444.
The 50 Ω resistors and 18 pF capacitor between the THS4509 outputs and ADS5444 inputs (along with the input
capacitance of the ADC) limit the bandwidth of the signal to about 70 MHz (–3 dB).
Input termination is accomplished via the 78.9 Ω resistor and 0.22 μF capacitor to ground in conjunction with the
input impedance of the amplifier circuit. A 0.22 μF capacitor and 49.9 Ω resistor are inserted to ground across
the 78.9 Ω resistor and 0.22 μF capacitor on the alternate input to balance the circuit.
Gain is a function of the source impedance, termination, and 348 Ω feedback resistor. See the THS4509 data
sheet for further component values to set proper 50 Ω termination for other common gains.
Because the ADS5444 recommended input common-mode voltage is 2.4 V, the THS4509 is operated from a
single power supply input with VS+ = 5 V and VS– = 0 V (ground). This maintains maximum headroom on the
internal transistors of the THS4509.
Clock Inputs
The ADS5444 clock input can be driven with either a differential clock signal or a single-ended clock input, with
little or no difference in performance between both configurations. In low-input frequency applications, where jitter
may not be a big concern, the use of single-ended clock (see Figure 16) could save some cost and board space
without any trade-off in performance. When driven on this configuration, it is best to connect CLK to ground with
a 0.01 μF capacitor, while CLK is ac-coupled with a 0.01 μF capacitor to the clock source, as shown in
Figure 16.
CLK
Square Wave or
Sine Wave
0.01 µF
0.01 µF
ADS5444
CLK
Figure 16. Single-Ended Clock
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ADS5444-SP
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SGLS391B –MARCH 2008–REVISED FEBRUARY 2012
0.1 µF
1:4
Clock
CLK
Source
ADS5444
CLK
MA3X71600LCT−ND
Figure 17. Differential Clock
For jitter-sensitive applications, the use of a differential clock has some advantages (as with any other ADC) at
the system level. The first advantage is that it allows for common-mode noise rejection at the PCB level.
A differential clock also allows for the use of bigger clock amplitudes without exceeding the absolute maximum
ratings. In the case of a sinusoidal clock, this results in higher slew rates and reduces the impact of clock noise
on jitter. See Clocking High Speed Data Converters (SLYT075) for more details.
Figure 17 shows this approach. The back-to-back Schottky diodes can be added to limit the clock amplitude in
cases where this would exceed the absolute maximum ratings, even when using a differential clock.
100 nF
MC100EP16DT
Q
100 nF
100 nF
CLK
D
D
V
BB
Q
ADS5444
CLK
100 nF
499 W
499 W
50 Ω
50 Ω
100 nF
113 Ω
Figure 18. Differential Clock Using PECL Logic
Another possibility is the use of a logic-based clock, such as PECL. In this case, the slew rate of the edges is
most likely much higher than the one obtained for the same clock amplitude based on a sinusoidal clock. This
solution would minimize the effect of the slope dependent ADC jitter. Using logic gates to square a sinusoidal
clock may not produce the best results, as logic gates may not have been optimized to act as comparators,
adding too much jitter while squaring the inputs.
The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1 kΩ resistors. It is
recommended to use ac coupling, but if this scheme is not possible due to, for instance, asynchronous clocking,
the ADS5444 features good tolerance to clock common-mode variation.
Additionally, the internal ADC core uses both edges of the clock for the conversion process. Ideally, a 50% duty
cycle clock signal should be provided.
Digital Outputs
The ADC provides 13 data outputs (D12 to D0, with D12 being the MSB and D0 the LSB), a data-ready signal
(DRY), and an over-range indicator (OVR) that equals a logic high when the output reaches the full-scale limits.
The output format is offset binary. It is recommended to use the DRY signal to capture the output data of the
ADS5444.
The ADS5444 digital outputs are LVDS compatible.
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Power Supplies
The use of low-noise power supplies with adequate decoupling is recommended. Linear supplies are the
preferred choice versus switched ones, which tend to generate more noise components that can be coupled to
the ADS5444.
The ADS5444 uses two power supplies. For the analog portion of the design, a 5 V AVDD is used, while for the
digital outputs supply (DRVDD) TI recommends the use of 3.3 V. All the ground pins are marked as GND,
although AGND pins and DRGND pins are not tied together inside the package.
Layout Information
The evaluation board represents a good guideline of how to lay out the board to obtain the maximum
performance out of the ADS5444. General design rules such as the use of multilayer boards, single ground plane
for ADC ground connections and local decoupling ceramic chip capacitors should be applied. The input traces
should be isolated from any external source of interference or noise including the digital outputs, as well as the
clock traces. The clock signal traces should also be isolated from other signals, especially in applications where
low jitter is required as high IF sampling.
Besides performance-oriented rules, care has to be taken when considering the heat dissipation out of the
device.
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PACKAGE OPTION ADDENDUM
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28-Aug-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
5962-0720701VXC
ACTIVE
CFP
HFG
84
1
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ADS5444-SP :
Catalog: ADS5444
•
Enhanced Product: ADS5444-EP
•
NOTE: Qualified Version Definitions:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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Catalog - TI's standard catalog product
•
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
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