ADS5463-EP_14 [TI]
12-BIT, 500-MSPS ANALOG-TO-DIGITAL CONVERTER;
| 型号： | ADS5463-EP_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12-BIT, 500-MSPS ANALOG-TO-DIGITAL CONVERTER |
| 文件： | 总33页 (文件大小：1238K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS5463
ADS5463-EP
www.ti.com ......................................................................................................................................... SGLS382C –NOVEMBER 2006–REVISED OCTOBER 2009
12-BIT, 500-MSPS ANALOG-TO-DIGITAL CONVERTER
Check for Samples :ADS5463-EP
1
FEATURES
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
23
•
500-MSPS Sample Rate
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C)
Temperature Range(1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
•
12-Bit Resolution, 10.5-Bits Effective Number
of Bits (ENOB)
•
•
•
•
•
•
•
•
2-GHz Input Bandwidth
SFDR = 75 dBc at 450 MHz and 500 MSPS
SNR = 64.6 dBFS at 450 MHz and 500 MSPS
2.2-Vpp Differential Input Voltage
LVDS-Compatible Outputs
•
•
•
Total Power Dissipation: 2.2 W
Offset Binary Output Format
APPLICATIONS
•
•
•
•
•
•
Test and Measurement Instrumentation
Software-Defined Radio
Data Acquisition
Power Amplifier Linearization
Communication Instrumentation
Radar
Output Data Transitions on the Rising and
Falling Edges of a Half-Rate Output Clock
•
•
•
On-Chip Analog Buffer, Track and Hold, and
Reference Circuit
80-Pin TQFP PowerPAD™ Package
(14 mm × 14 mm)
Pin Similar to ADS5440/ADS5444
(1) Additional temperature ranges available - contact factory
DESCRIPTION/ORDERING INFORMATION
The ADS5463 is a 12-bit, 500-MSPS analog-to-digital converter (ADC) that operates from both a 5-V supply and
3.3-V supply, while providing LVDS-compatible digital outputs. The ADS5463 input buffer isolates the internal
switching of the onboard track and hold (T&H) from disturbing the signal source while providing a high
impedance input. An internal reference generator also is provided to simplify the system design.
Designed to optimize conversion of wide-bandwidth signals up to 500-MHz of input frequency at 500 MSPS, the
ADS5463 has outstanding low noise and linearity over a large input frequency range. Input signals above 500
MHz also can be converted due to the large input bandwidth of the device.
The ADS5463 is available in an 80-pin TQFP PowerPAD™ package. The ADS5463 is built on state-of-the-art
Texas Instruments complementary bipolar process (BiCom3X) and is specified over the full extended
temperature range (–55°C to 125°C).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2009, Texas Instruments Incorporated
ADS5463-EP
SGLS382C –NOVEMBER 2006–REVISED OCTOBER 2009 ......................................................................................................................................... www.ti.com
VIN
VIN
+
+
A1
TH1
TH2
A2
TH3
A3
ADC3
Σ
Σ
–
–
ADC1
DAC1
ADC2
DAC2
VREF
Reference
5
5
5
Digital Error Correction
CLK
CLK
Timing
OVR
OVR
DRY
DRY
D[11:0]
B0061-03
Figure 1. Analog-to-Digital Converter Functional Block Diagram
Table 1. PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE LEAD
(2)
HTQFP-80(3)
PowerPAD
ADS5463-EP
PFP
–55°C to 125°C
ADS5463MEP ADS5463MPFPEP
Tray, 96
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) Thermal pad size: 9.5 mm × 9.5 mm (minimum), 10 mm × 10 mm (maximum).
2
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
6
UNIT
AVDD5 to GND
AVDD3 to GND
DVDD3 to GND
Supply voltage
5
V
5
AC signal
–0.3 to (AVDD5 + 0.3)
0.4 to 4.4
1.0 to 3.8
–5.2 to 5.2
–4 to 4
Voltage difference between
pin and ground
AIN, AIN to GND(2)
DC signal, TJ = 105°C
DC signal, TJ = 125°C
AC signal
V
V
V
V
Voltage difference between
these pins
(2)
AIN to AIN
DC signal, TJ = 105°C
DC signal, TJ = 125°C
AC signal
–2.8 to 2.8
–0.3 to (AVDD5 + 0.3)
0.1 to 4.7
1.1 to 3.7
–3.3 to 3.3
–3.3 to 3.3
–2.6 to 2.6
–0.3 to (DVDD3 + 0.3)
–55 to 125
150
Voltage difference between
pin and ground
CLK, CLK to GND(2)
DC signal, TJ = 105°C
DC signal, TJ = 125°C
AC signal
Voltage difference between
these pins
(2)
CLK to CLK
DC signal, TJ = 105°C
DC signal, TJ = 125°C
Data output to GND(2) LVDS digital outputs
Characterized case operating temperature range
Maximum junction temperature
V
°C
°C
°C
kV
Storage temperature range
–65 to 150
2
ESD Human Body Model (HBM)
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) Valid when supplies are within recommended operating range.
THERMAL CHARACTERISTICS(1)
PARAMETER
TEST CONDITIONS
TYP
23.7
17.8
16.4
2.99
UNIT
°C/W
°C/W
Soldered thermal pad, no airflow
(2)
R
Soldered thermal pad, 150 LFM airflow
Soldered thermal pad, 250 LFM airflow
Bottom of package (thermal pad)
θJA
(3)
R
θJP
(1) Using 36 thermal vias (6 × 6 array). See Application Information section.
(2)
(3)
R
θJA is the thermal resistance from junction to ambient.
RθJP is the thermal resistance from junction to the thermal pad.
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Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may
result in a reduction of overall device life. See Figure 2 for additional information on thermal derating.
Electromigration failure mode applies to powered part. Kirkendall voiding failure mode is a function of
temperature only.
10000
Electromigration Fail Mode
1000
Wirebond Voiding
Fail Mode
100
10
1
Note:
Silicon operating life design goal is 10 years @105°C junction temperature (does not include package interconnect
life).
0.1
100
110
120
130
140
150
160
170
180
Continuous Tj (°C)
Figure 2. ADS5463-EP Operating Life Derating Chart
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RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLIES
AVDD5
Analog supply voltage
Analog supply voltage
Output driver supply voltage
4.75
3
5
3.3
3.3
5.25
3.6
V
V
V
AVDD3
DVDD3
3
3.6
ANALOG INPUT
Differential input range
Input common mode
2.2
2.4
Vpp
V
VCM
DIGITAL OUTPUT (DRY, DATA, OVR)
Maximum differential output load
CLOCK INPUT (CLK)
10
pF
CLK input sample rate (sine wave)
Clock amplitude, differential sine wave
Clock duty cycle
20
500 MSPS
Vpp
3
50%
TA
Open free-air temperature
–55
125
°C
ELECTRICAL CHARACTERISTICS
Typical values at TA = 25°C, minimum and maximum values over full temperature range TMIN = –55°C to TMAX = 125°C,
sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input,
and 3 VPP differential clock (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
ANALOG INPUTS
Differential input range
12
Bits
2.2
2.4
500
2.5
2
Vpp
V
VCM
Input common mode
Input resistance (dc)
Input capacitance
Each input to ground
Each input to ground
Ω
pF
Analog input bandwidth (–3 dB) Dependent on source impedance
GHz
dB
CMRR Common Mode Rejection Ratio Common Mode Signal = 10MHz
80
INTERNAL REFERENCE VOLTAGE
VREF
Reference voltage
2.4
V
DYNAMIC ACCURACY
No missing codes
Assured
±0.25
DNL
INL
Differential linearity error
fIN = 10 MHz
fIN = 10 MHz
–0.95
0.95
2.5
11
LSB
LSB
Integral linearity error
Offset error
–2.5 +0.8/–0.3
–11
0.0005
–5.2
–0.02
85
mV
Offset temperature coefficient
Gain error
mV/°C
%FS
Δ%/°C
dB
5.2
Gain temperature coefficient
PSRR
100kHz supply noise (see Figure 34)
POWER SUPPLY
IAVDD5
IAVDD3
IDVDD3
5-V analog supply current
300
125
82
365
145
92
mA
mA
mA
W
VIN = full scale, fIN = 10 MHz,
fS = 500 MSPS
3.3-V analog supply current
3.3-V digital supply current
Total Power dissipation
Power-up time
2.18 2.575
200
μs
DYNAMIC AC CHARACTERISTICS
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ELECTRICAL CHARACTERISTICS (continued)
Typical values at TA = 25°C, minimum and maximum values over full temperature range TMIN = –55°C to TMAX = 125°C,
sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input,
and 3 VPP differential clock (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
65.3
65.4
65.3
65.3
65.1
65
MAX
UNIT
fIN = 10 MHz
fIN = 70 MHz
25C
63.5
63
fIN = 100 MHz
Temp
fIN = 230 MHz
fIN = 300 MHz
SNR
Signal-to-noise ratio
25C
63.25
61.75
dBFS
Temp
65
fIN = 450 MHz
fIN = 650 MHz
fIN = 900 MHz
fIN = 1.3 GHz
fIN = 10 MHz
fIN = 70 MHz
64.6
63.9
62.6
59.3
85
82
25C
70
67
82
fIN = 100 MHz
Temp
82
fIN = 230 MHz
fIN = 300 MHz
78
SFDR
Spurious free dynamic range
25C
64
62
77
dBc
Temp
77
fIN = 450 MHz
fIN = 650 MHz
fIN = 900 MHz
fIN = 1.3 GHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 230 MHz
fIN = 300 MHz
fIN = 450 MHz
fIN = 650 MHz
fIN = 900 MHz
fIN = 1.3 GHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 230 MHz
fIN = 300 MHz
fIN = 450 MHz
fIN = 650 MHz
fIN = 900 MHz
fIN = 1.3 GHz
75
65
56
45
87
82
67
80
81
HD2
Second harmonic
62.5
77
dBc
80
77
66
50
85
90
67.5
63
87
90
HD3
Third harmonic
80
dBc
75
65
56
45
6
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ELECTRICAL CHARACTERISTICS (continued)
Typical values at TA = 25°C, minimum and maximum values over full temperature range TMIN = –55°C to TMAX = 125°C,
sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input,
and 3 VPP differential clock (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
86
MAX
UNIT
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 230 MHz
fIN = 300 MHz
fIN = 450 MHz
fIN = 650 MHz
fIN = 900 MHz
fIN = 1.3 GHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 230 MHz
fIN = 300 MHz
fIN = 450 MHz
fIN = 650 MHz
fIN = 900 MHz
fIN = 1.3 GHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 230 MHz
fIN = 300 MHz
fIN = 450 MHz
fIN = 650 MHz
fIN = 900 MHz
fIN = 1.3 GHz
86
86
77
Worst harmonic/spur (other
than HD2 and HD3)
81
dBc
86
85
78
67
80
79
77
75
THD
Total Harmonic Distortion
73
dBc
73
64
55
44
65.2
65.2
65.1
64.7
64.5
64.1
61.5
55.4
45.1
90
62
SINAD Signal-to-noise and distortion
58.75
dBc
fIN1 = 65 MHz, fIN2 = 70 MHz, Each tone at –7 dBFS
fIN1 = 65 MHz, fIN2 = 70 MHz, Each tone at –16 dBFS
89
fIN1 = 350 MHz, fIN2 = 355 MHz, Each tone at –7
dBFS
82
Two-Tone SFDR
dBc
fIN1 = 350 MHz, fIN2 = 355 MHz, Each tone at –16
dBFS
89
fIN = 100 MHz
9.9
10.5
10.4
0.7
ENOB
Effective number of bits
RMS idle-channel noise
Bits
fIN = 300 MHz
Inputs tied to common-mode
LSB
LVDS DIGITAL OUTPUTS
VOD
VOC
Differential output voltage (±)
Common mode output voltage
TA = 25°C
247
400
454
mV
V
1.125
1.375
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Sample
N–1
N+4
N+2
ta
N
N+1
N+3
N+5
tCLKH
tCLKL
CLK
CLK
Latency = 4 Clock Cycles
tDRY
DRY
DRY
tDATA
D[11:0], OVR
N–1
N
N+1
D[11:0], OVR
T0158-01
Figure 3. Timing Diagram
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TIMING CHARACTERISTICS(1)
Typical values at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V,
DVDD3 = 3.3 V, and 3 VPP differential clock (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
200
160
3.5
MAX
UNIT
ps
tA
Aperture delay
Aperture jitter, rms
fs
Latency
cycles
ns
tCLK
Clock period
2
1
1
tCLKH
tCLKL
tDRY
Clock pulse duration, high
Clock pulse duration, low
CLK to DRY delay(1)
CLK to DATA/OVR delay
DRY to DATA skew
DRY/DATA/OVR rise time
DRY/DATA/OVR fall time
ns
ns
Zero crossing, 7 pF diff loading
Zero crossing, 7 pF diff loading
tDATA – tDRY, 7 pF diff loading
7 pF differential loading
1100
1100
0
ps
(1)
tDATA
tSKEW
tRISE
tFALL
ps
ps
500
500
ps
7 pF differential loading
ps
(1) DRY, DATA, and OVR are updated on the falling edge of CLK. The latency must be added to tDATA to determine the data propagation
delay.
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PFP PACKAGE
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
DVDD3
GND
AVDD5
NC
1
2
60
59
D3
D3
D2
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
3
4
D2
NC
D1
5
VREF
GND
AVDD5
GND
CLK
D1
6
D0
7
8
D0
9
GND
DVDD3
NC
NC
NC
NC
NC
NC
NC
NC
OVR
OVR
10
11
12
13
14
15
16
17
18
19
20
ADS5463
CLK
GND
AVDD5
AVDD5
GND
AIN
AIN
GND
AVDD5
GND
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P0027-02
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Table 2. TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
AIN
NO.
16
Differential input signal (positive)
Differential input signal (negative)
AIN
17
3, 8, 13, 14, 19, 21,
23, 25, 27, 31
AVDD5
Analog power supply (5 V)
Analog power supply (3.3 V) (Suggestion for ≤250 MSPS: leave option to connect to 5 V for
ADS5440/4 compatibility)
AVDD3
DVDD3
35, 37, 39
1, 51, 66
Output driver power supply (3.3 V)
2, 7, 9, 12, 15, 18,
20, 22, 24, 26, 28,
30, 32, 34, 36, 38,
40, 52, 65
GND
Ground
CLK
10
11
Differential input clock (positive). Conversion is initiated on rising edge.
Differential input clock (negative)
CLK
D0, D0
54, 53
LVDS digital output pair, least-significant bit (LSB)
D1–D10,
D1–D10
55–64,
67–76
LVDS digital output pairs
D11, D11
78, 77
80, 79
LVDS digital output pair, most-significant bit (MSB)
Data ready LVDS output pair
DRY, DRY
No connect (4 and 5 should be left floating, 43–50 are possible future bit additions for this pinout
and therefore can be connected to a digital bus or left floating)
NC
4, 5, 43–50
42, 41
Overrange indicator LVDS output. A logic high signals an analog input in excess of the full-scale
range.
OVR, OVR
Pin 29 is reserved for possible future Vcm output for this pinout; pin 33 is reserved for possible
future power-down control pin for this pinout.
RESERVED
VREF
29, 33
6
Reference voltage
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TYPICAL CHARACTERISTICS
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3 VPP differential clock, (unless otherwise noted)
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
FFT FOR 30-MHz INPUT SIGNAL
FFT FOR 100-MHz INPUT SIGNAL
0
−20
0
−20
SFDR = 82.4 dBc
SFDR = 80.6 dBc
SINAD = 65.3 dBFS
SNR = 65.4 dBFS
THD = 79 dBc
SINAD = 65.1 dBFS
SNR = 65.3 dBFS
THD = 77.1 dBc
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
25 50 75 100 125 150 175 200 225 250
Frequency − MHz
0
25 50 75 100 125 150 175 200 225 250
Frequency − MHz
G001
G002
Figure 4.
Figure 5.
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
FFT FOR 230-MHz INPUT SIGNAL
FFT FOR 300-MHz INPUT SIGNAL
0
−20
0
−20
SFDR = 77.5 dBc
SINAD = 64.7 dBFS
SNR = 65.2 dBFS
THD = 73.7 dBc
SFDR = 77.1 dBc
SINAD = 64.5 dBFS
SNR = 65 dBFS
THD = 73.1 dBc
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
25 50 75 100 125 150 175 200 225 250
Frequency − MHz
0
25 50 75 100 125 150 175 200 225 250
Frequency − MHz
G003
G004
Figure 6.
Figure 7.
12
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3 VPP differential clock, (unless otherwise noted)
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
FFT FOR 450-MHz INPUT SIGNAL
FFT FOR 650-MHz INPUT SIGNAL
0
−20
0
−20
SFDR = 74.3 dBc
SFDR = 65.5 dBc
SINAD = 61.8 dBFS
SNR = 64 dBFS
THD = 64.9 dBc
SINAD = 64.3 dBFS
SNR = 64.8 dBFS
THD = 73 dBc
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
25 50 75 100 125 150 175 200 225 250
Frequency − MHz
0
25 50 75 100 125 150 175 200 225 250
Frequency − MHz
G005
G006
Figure 8.
Figure 9.
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
FFT FOR 900-MHz INPUT SIGNAL
FFT FOR 1,300-MHz INPUT SIGNAL
0
−20
0
−20
SFDR = 55.5 dBc
SFDR = 45.6 dBc
SINAD = 45.1 dBFS
SNR = 59.3 dBFS
THD = 44.3 dBc
SINAD = 55.3 dBFS
SNR = 62.8 dBFS
THD = 55.1 dBc
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
25 50 75 100 125 150 175 200 225 250
Frequency − MHz
0
25 50 75 100 125 150 175 200 225 250
Frequency − MHz
G007
G008
Figure 10.
Figure 11.
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3 VPP differential clock, (unless otherwise noted)
TWO-TONE INTERMODULATION DISTORTION
(FFT FOR 65.1 MHz AND 70.1 MHz AT –7 dBFS)
TWO-TONE INTERMODULATION DISTORTION
(FFT FOR 65.1 MHz AND 70.1 MHz AT –16 dBFS)
0
0
f
f
= 65.1 MHz, −7 dBFS
= 70.1 MHz, −7 dBFS
f
f
= 65.1 MHz, −16 dBFS
= 70.1 MHz, −16 dBFS
IN1
IN2
IN1
IN2
IMD3 = 90.5 dBFS
SFDR = 90.3 dBFS
IMD3 = 96.1 dBFS
SFDR = 88.8 dBFS
−20
−20
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
25 50 75 100 125 150 175 200 225 250
Frequency − MHz
0
25 50 75 100 125 150 175 200 225 250
Frequency − MHz
G009
G010
Figure 12.
Figure 13.
TWO-TONE INTERMODULATION DISTORTION
(FFT FOR 350 MHz AND 355 MHz AT –7 dBFS)
TWO-TONE INTERMODULATION DISTORTION
(FFT FOR 350 MHz AND 355 MHz AT –16 dBFS)
0
0
f
f
= 350 MHz, −7 dBFS
= 355 MHz, −7 dBFS
f
f
= 350 MHz, −16 dBFS
= 355 MHz, −16 dBFS
IN1
IN2
IN1
IN2
IMD3 = 81.6 dBFS
SFDR = 81.6 dBFS
IMD3 = 101.1 dBFS
SFDR = 88.9 dBFS
−20
−20
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
25 50 75 100 125 150 175 200 225 250
Frequency − MHz
0
25 50 75 100 125 150 175 200 225 250
Frequency − MHz
G011
G012
Figure 14.
Figure 15.
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3 VPP differential clock, (unless otherwise noted)
FULLSCALE GAIN RESPONSE
vs
INPUT FREQUENCY
DIFFERENTIAL NONLINEARITY
4
3
0.3
0.2
f
f
= 500 MSPS
= 10 MHz
S
IN
2
1
0.1
0
−1
−2
−3
−4
−5
−6
0.0
−0.1
−0.2
−0.3
f
A
= 500 MSPS
S
= –1 dBFS
IN
0
200 400 600 800 100012001400160018002000
50
550 1050 1550 2050 2550 3050 3550 4050
Code
f
IN
− Input Frequency − MHz
G013
G014
Figure 16.
Figure 17.
NOISE HISTOGRAM WITH INPUTS SHORTED
INTEGRAL NONLINEARITY
1.0
0.8
60
55
50
45
40
35
30
25
20
15
10
5
f
f
= 500 MSPS
S
f
S
= 500 MSPS
= 10 MHz
IN
0.6
0.4
0.2
0.0
−0.2
−0.4
−0.6
−0.8
−1.0
0
50
550 1050 1550 2050 2550 3050 3550 4050
Code
2050
2049
2048
2047
2046
Code Number
G015
G016
Figure 18.
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3 VPP differential clock, (unless otherwise noted)
AC PERFORMANCE
AC PERFORMANCE
vs
vs
INPUT AMPLITUDE (100-MHz INPUT SIGNAL)
INPUT AMPLITUDE (300-MHz INPUT SIGNAL)
120
100
80
120
100
80
SFDR (dBFS)
SNR (dBFS)
SFDR (dBFS)
SNR (dBFS)
60
60
40
40
SFDR (dBc)
SFDR (dBc)
20
20
0
0
SNR (dBc)
SNR (dBc)
−20
−40
−60
−20
−40
−60
f
f
= 500 MSPS
= 100.3 MHz
f
f
= 500 MSPS
= 301.1 MHz
S
S
IN
IN
−120
−100
−80
−60
−40
−20
0
−120
−100
−80
−60
−40
−20
0
Input Amplitude − dBFS
Input Amplitude − dBFS
G017
G018
Figure 20.
Figure 21.
AC PERFORMANCE
vs
INPUT AMPLITUDE (350-MHz AND 355-MHz TWO-TONE INPUT
SIGNAL)
SFDR
vs
CLOCK DUTY CYCLE
85
80
75
70
65
60
55
50
100
f
= 100 MHz
IN
Worst Spur (dBFS)
80
SNR (dBFS)
60
f
= 300 MHz
IN
Worst Spur (dBc)
40
20
SNR (dBc)
0
f
f
f
= 500 MSPS
S
= 350 MHz
= 355 MHz
IN1
IN2
f
S
= 500 MSPS
30
−20
20
40
50
60
70
80
−80 −70 −60 −50 −40 −30 −20 −10
0
Duty Cycle − %
Input Amplitude − dBFS
G021
G020
Figure 22.
Figure 23.
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3 VPP differential clock, (unless otherwise noted)
SFDR
vs
SNR
vs
CLOCK LEVEL
CLOCK LEVEL
80
79
78
77
76
75
74
73
72
71
66.0
65.5
65.0
64.5
64.0
63.5
63.0
62.5
f
= 100 MHz
f
= 100 MHz
= 300 MHz
IN
IN
f
IN
f
= 300 MHz
IN
f
S
= 500 MSPS
4
f
S
= 500 MSPS
4
0
1
2
3
5
0
1
2
3
5
Clock Amplitude − V
Clock Amplitude − V
P−P
P−P
G022
G023
Figure 24.
Figure 25.
SFDR
vs
SNR
vs
CLOCK COMMON MODE
CLOCK COMMON MODE
66
65
64
63
62
61
60
85
80
75
70
65
60
f
= 100 MHz
IN
f
= 100 MHz
IN
f
IN
= 300 MHz
f
IN
= 300 MHz
f
S
= 500 MSPS
f
S
= 500 MSPS
1
0
1
2
3
4
5
0
2
3
4
5
Clock Common Mode − V
Clock Common Mode − V
G024
G025
Figure 26.
Figure 27.
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3 VPP differential clock, (unless otherwise noted)
SFDR
SNR
vs
vs
AVDD5 ACROSS TEMPERATURE
AVDD5 ACROSS TEMPERATURE
80
75
70
65
60
55
67.0
66.5
66.0
65.5
65.0
64.5
64.0
63.5
63.0
f
f
= 500 MSPS
= 100 MHz
S
IN
T
= −405C
A
T
= 05C
A
T
= 255C
A
T
A
= 05C
T
A
= 405C
T
= 405C
A
T
A
= 655C
T
= 655C
= 855C
T
= 255C
A
A
T
= −405C
A
T
A
T
A
= 855C
T
A
= 1005C
f
f
= 500 MSPS
= 100 MHz
S
IN
T
A
= 1005C
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
AV − Supply Voltage − V
AV − Supply Voltage − V
DD
DD
G026
G027
Figure 28.
Figure 29.
SFDR
SNR
vs
vs
AVDD3 ACROSS TEMPERATURE
AVDD3 ACROSS TEMPERATURE
80
78
76
74
72
70
68
66.5
66.0
65.5
65.0
64.5
64.0
63.5
T
A
= 405C
T
= 255C
A
T
= −405C
A
T
A
= 05C
T
= 05C
A
T
= 255C
A
T
= 655C
A
T
A
= 405C
T
A
= 655C
T
A
= 855C
T
A
= 855C
T
A
= 1005C
T
A
= −405C
f
S
= 500 MSPS
= 100 MHz
f
f
= 500 MSPS
= 100 MHz
S
IN
T
A
= 1005C
f
IN
2.7
2.9
3.1
3.3
3.5
3.7
2.7
2.9
3.1
3.3
3.5
3.7
AV − Supply Voltage − V
AV − Supply Voltage − V
DD
DD
G028
G029
Figure 30.
Figure 31.
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3 VPP differential clock, (unless otherwise noted)
SFDR
SNR
vs
vs
DVDD3 ACROSS TEMPERATURE
DVDD3 ACROSS TEMPERATURE
80
78
76
74
72
70
68
66.5
66.0
65.5
65.0
64.5
64.0
63.5
f
f
= 500 MSPS
= 100 MHz
S
IN
T
= 255C
A
T
= −405C
A
T
= 405C
A
T
A
= 05C
T = 05C
A
T
= 255C
= 655C
A
T
A
= 655C
T
= 405C
A
T
A
= 855C
T
A
T
A
= −405C
T
= 855C
A
T
= 1005C
A
f
f
= 500 MSPS
= 100 MHz
S
IN
T
A
= 1005C
2.7
2.9
3.1
3.3
3.5
3.7
2.7
2.9
3.1
3.3
3.5
3.7
DV − Supply Voltage − V
DV − Supply Voltage − V
DD
DD
G030
G031
Figure 32.
Figure 33.
PSRR
vs
CMRR
vs
SUPPLY INJECTED FREQUENCY
COMMON-MODE INPUT FREQUENCY
100
90
80
70
60
50
40
100
90
80
70
60
50
40
30
20
10
0
f
S
= 500 MSPS
AVDD3
AVDD5
f
f
= 500 MSPS
= None
S
IN
0.01
0.1
1
10
100
0.1
1
10
100
1000
Frequency − MHz
Common-Mode Input Frequency − MHz
G032
G033
Figure 34.
Figure 35.
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3 VPP differential clock, (unless otherwise noted)
SNR
vs
INPUT FREQUENCY AND SAMPLING FREQUENCY
550
63
64
61
62
64
65
63
500
450
400
350
300
250
65
64
63
62
65
64
63
62
58
59
61
200
170
65
10
100
58
200
300
60
400
500
600
700
800
900
1000
67
fIN - Input Frequency - MHz
57
59
61
62
63
64
65
66
SNR - dBFS
M0048-09
Figure 36.
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3 VPP differential clock, (unless otherwise noted)
SFDR
vs
INPUT FREQUENCY AND SAMPLING FREQUENCY
550
70
60
75
80
75
55
65
500
450
400
350
300
250
80
80
70
75
65
55
80
60
80
85
70
75
85
60
55
200
170
65
80
10
100
200
300
400
500
600
700
800
900
1000
90
fIN - Input Frequency - MHz
45
50
55
60
65
70
75
80
85
SFDR - dBc
Figure 37.
M0048-10
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APPLICATION INFORMATION
Theory of Operation
The ADS5463 is a 12-bit, 500-MSPS, monolithic-pipeline, analog-to-digital converter. Its bipolar analog core
operates from 5-V and 3.3-V supplies, while the output uses a 3.3-V supply to provide LVDS-compatible outputs.
The conversion process is initiated by the rising edge of the external input clock. At that instant, the differential
input signal is captured by the input track-and-hold (T&H), and the input sample is sequentially converted by a
series of lower resolution stages, with the outputs combined in a digital correction logic block. Both the rising and
the falling clock edges are used to propagate the sample through the pipeline every half clock cycle. This
process results in a data latency of 3.5 clock cycles, after which the output data is available as a 12-bit parallel
word, coded in offset binary format.
Input Configuration
The analog input for the ADS5463 consists of an analog pseudodifferential buffer followed by a bipolar transistor
track-and-hold. The analog buffer isolates the source driving the input of the ADC from any internal switching.
The input common mode is set internally through a 500-Ω resistor connected from 2.4 V to each of the inputs.
This results in a differential input impedance of 1 kΩ.
For a full-scale differential input, each of the differential lines of the input signal (pins 16 and 17) swings
symmetrically between 2.4 V + 0.55 V and 2.4 V – 0.55 V. This means that each input has a maximum signal
swing of 1.1 Vpp for a total differential input signal swing of 2.2 Vpp. The maximum swing is determined by the
internal reference voltage generator, eliminating the need for any external circuitry for this purpose.
The ADS5463 obtains optimum performance when the analog inputs are driven differentially. The circuit in
Figure 38 shows one possible configuration using an RF transformer with termination either on the primary or on
the secondary of the transformer. In addition, the evaluation module is configured with two back-to-back
transformers, which also demonstrates good performance. If voltage gain is required, a step-up transformer can
be used.
Besides the transformer configurations, Texas Instruments offers a wide selection of single-ended operational
amplifiers that can be selected depending on the application. An RF gain-block amplifier, such as Texas
Instruments' THS9001, can also be used for high-input-frequency applications. For large voltage gains at
intermediate-frequencies in the 50-MHz to 500-MHz range, the configuration shown in Figure 39 can be used.
The component values can be tuned for different intermediate frequencies. The example shown is located on the
evaluation module and is tuned for an IF of 170 MHz. More information regarding this configuration can be found
in the ADS5463 EVM User Guide (SLAU194) and the THS9001 50 MHz to 350 MHz Cascadeable Amplifier data
sheet (SLOS426).
Z0
R0
50 W
50 W
AIN
1:1
R
50 W
AC Signal
Source
ADS5463
AIN
Mini-Circuits
JTX4-10T
S0176-03
Figure 38. Converting a Single-Ended Input to a Differential Signal Using an RF Transformer
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1000 pF
1000 pF
THS9001
VIN
VIN
AIN
AIN
50 W
50 W
18 mH
39 pF
ADS5463
0.1 mF
THS9001
1000 pF
1000 pF
S0177-03
Figure 39. Using the THS9001 IF Amplifier With the ADS5463
VIN
From
50 W
Source
100 W
348 W
+5V
78.9 W
49.9 W
49.9 W
0.22 mF
100 W
AIN
ADS5463
THS4509
CM
18 pF
VREF
AIN
49.9 W
0.22 mF
78.9 W
49.9 W
0.22 mF
0.1 mF
0.1 mF
348 W
S0193-02
Figure 40. Using the THS4509 With the ADS5463
For applications requiring dc-coupling with the signal source, a differential input/differential output amplifier like
the THS4509 (see Figure 40) is a good solution, as it minimizes board space and reduces the number of
components.
In this configuration, the THS4509 amplifier circuit provides 10-dB of gain, converts the single-ended input to
differential, and sets the proper input common-mode voltage to the ADS5463. The 50-Ω resistors and 18-pF
capacitor between the THS4509 outputs and ADS5463 inputs (along with the input capacitance of the ADC) limit
the bandwidth of the signal to about 70 MHz (–3 dB). Input termination is accomplished via the 78.9-Ω resistor
and 0.22-μF capacitor to ground, in conjunction with the input impedance of the amplifier circuit. A 0.22-μF
capacitor and 49.9-Ω resistor are inserted to ground across the 78.9-Ω resistor and 0.22-μF capacitor on the
alternate input to balance the circuit. Gain is a function of the source impedance, termination, and 348-Ω
feedback resistor. See the THS4509 data sheet for further component values to set proper 50-Ω termination for
other common gains. Because the ADS5463 recommended input common-mode voltage is 2.4 V, the THS4509
is operated from a single power supply input with V S+ = 5 V and V S– = 0 V (ground). This maintains maximum
headroom on the internal transistors of the THS4509.
Clock Inputs
The ADS5463 clock input can be driven with either a differential clock signal or a single-ended clock input, with
little or no difference in performance between both configurations. In low-input-frequency applications, where
jitter may not be a big concern, the use of a single-ended clock (see Figure 41) could save some cost and board
space without any trade-off in performance. When clocked with this configuration, it is best to connect CLK to
ground with a 0.01-μF capacitor, while CLK is ac-coupled with a 0.01-μF capacitor to the clock source, as shown
in Figure 41.
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Square Wave or
CLK
Sine Wave
0.01 mF
ADS5463
CLK
0.01 mF
S0168-05
Figure 41. Single-Ended Clock
0.1 mF
Clock
CLK
Source
ADS5463
CLK
S0194-02
Figure 42. Differential Clock
For jitter-sensitive applications, the use of a differential clock has some advantages (as with any other ADC) at
the system level. The differential clock allows for common-mode noise rejection at the PCB level. With a
differential clock, the signal-to-noise ratio of the ADC is better for high intermediate frequency applications
because the board clock jitter is superior.
A differential clock also allows for the use of bigger clock amplitudes without exceeding the absolute maximum
ratings. In the case of a sinusoidal clock, this results in higher slew rates and reduces the impact of clock noise
on jitter. Figure 42 shows this approach. See Clocking High Speed Data Converters (SLYT075) for more details.
The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1-kΩ resistors. It is
recommended to use ac coupling, but if this scheme is not possible due to, for instance, asynchronous clocking,
the ADS5463 features good tolerance to clock common-mode variation (see Figure 26 and Figure 27).
Additionally, the internal ADC core uses both edges of the clock for the conversion process. Ideally, a 50%
duty-cycle clock signal should be provided.
Digital Outputs
The ADC provides 12 data outputs (D11 to D0, with D11 being the MSB and D0 the LSB), a data-ready signal
(DRY), and an overrange indicator (OVR) that equals a logic high when the output reaches the full-scale limits.
The output format is offset binary. It is recommended to use the DRY signal to capture the output data of the
ADS5463. DRY is source-synchronous to the DATA/OVR bits and operates at the same frequency, creating a
half-rate DDR interface that updates data on both the rising and falling edges of DRY. The ADS5463 digital
outputs are LVDS-compatible. Due to the high data rates, care should be taken not to overload the digital outputs
with too much capacitance, which shortens the data-valid timing window. The values given for timing were
obtained with a measured 14-pF parasitic board capacitance to ground on each LVDS line (or 7-pF differential
parasitic capacitance).
Power Supplies
The ADS5463 uses three power supplies. For the analog portion of the design, a 5-V and 3.3-V supply (AVDD5
and AVDD3) are used, while the digital portion uses a 3.3-V supply (DVDD3). The use of low-noise power
supplies with adequate decoupling is recommended. Linear supplies are preferred to switched supplies; switched
supplies tend to generate more noise components that can be coupled to the ADS5463. The user may be able to
supply power to the device with a less-than-ideal supply and still achieve good performance. It is not possible to
make a single recommendation for every type of supply and level of decoupling for all systems.
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The power consumption of the ADS5463 does not change substantially over clock rate or input frequency as a
result of the architecture and process.
Because there are two diodes connected in reverse between AVDD3 and DVDD3 internally, a power-up
sequence is recommended. When there is a delay in power up between these two supplies, the one that lags
could have current sinking through an internal diode before it powers up. The sink current can be large or small
depending on the impedance of the external supply and could damage the device or affect the supply source.
The best power up sequence is one of the following options (regardless of when AVDD5 powers up):
•
•
Power up both AVDD3 and DVDD3 at the same time (best scenario), OR
Keep the voltage difference less than 0.8 V between AVDD3 and DVDD3 during the power up (0.8 V is not a
hard specification - a smaller delta between supplies is safer).
If the above sequences are not practical then the sink current from the supply needs to be controlled or
protection added externally. The max transient current (on the order of msec) for the DVDD3 or AVDD3 pin is
500 mA to avoid potential damage to the device or reduce its lifetime.
The values for the analog and clock inputs given in the Absolute Maximum Ratings are valid when the supplies
are on. When the power supplies are off and the clock or analog inputs are still being actively driven, the input
voltage and current need to be limited to avoid device damage. If the ADC supplies are off, max/min continuous
dc voltage is ±0.95 V and max dc current is 20 mA for each input pin (clock or analog), relative to ground.
Layout Information
The evaluation board represents a good guideline of how to lay out the board to obtain the maximum
performance from the ADS5463. General design rules, such as the use of multilayer boards, single ground plane
for ADC ground connections, and local decoupling ceramic chip capacitors, should be applied. The input traces
should be isolated from any external source of interference or noise, including the digital outputs as well as the
clock traces. The clock signal traces also should be isolated from other signals, especially in applications where
low jitter is required like high IF sampling. Besides performance-oriented rules, care must be taken when
considering the heat dissipation of the device. The thermal heat sink should be soldered to the board as
described in the PowerPad Package section. See ADS5463 EVM User Guide (SLAU194) on the TI Web site for
the evaluation board schematic.
PowerPAD Package
The PowerPAD package is a thermally enhanced standard-size IC package designed to eliminate the use of
bulky heatsinks and slugs traditionally used in thermal packages. This package can be easily mounted using
standard printed circuit board (PCB) assembly techniques, and can be removed and replaced using standard
repair procedures.
The PowerPAD package is designed so that the leadframe die pad (or thermal pad) is exposed on the bottom of
the IC. This provides an extremely low thermal resistance path between the die and the exterior of the package.
The thermal pad on the bottom of the IC can then be soldered directly to the printed circuit board (PCB), using
the PCB as a heatsink.
Assembly Process
1. Prepare the PCB top-side etch pattern including etch for the leads as well as the thermal pad as illustrated in
the Mechanical Data section.
2. Place a 6-by-6 array of thermal vias in the thermal pad area. These holes should be 13-mils in diameter. The
small size prevents wicking of the solder through the holes.
3. It is recommended to place a small number of 25-mil diameter holes under the package, but outside the
thermal pad area, to provide an additional heat path.
4. Connect all holes (both those inside and outside the thermal pad area) to an internal copper plane (such as a
ground plane).
5. Do not use the typical web or spoke via-connection pattern when connecting the thermal vias to the ground
plane. The spoke pattern increases the thermal resistance to the ground plane.
6. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area.
7. Cover the entire bottom side of the PowerPAD vias to prevent solder wicking.
8. Apply solder paste to the exposed thermal pad area and all of the package terminals.
Copyright © 2006–2009, Texas Instruments Incorporated
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For more detailed information regarding the PowerPAD package and its thermal properties, see either the
PowerPAD Made Easy application brief (SLMA004) or the PowerPAD Thermally Enhanced Package application
report (SLMA002).
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Product Folder Link(s) :ADS5463-EP
ADS5463-EP
www.ti.com ......................................................................................................................................... SGLS382C –NOVEMBER 2006–REVISED OCTOBER 2009
DEFINITION OF SPECIFICATIONS
Offset Error
Offset error is the deviation of output code from
mid-code when both inputs are tied to
common-mode.
Analog Bandwidth
The analog input frequency at which the power of the
fundamental is reduced by 3 dB with respect to the
low-frequency value
Power-Supply Rejection Ratio (PSRR)
PSRR is a measure of the ability to reject frequencies
present on the power supply. The injected frequency
level is translated into dBFS, the spur in the output
FFT is measured in dBFS, and the difference is the
PSRR in dB. The measurement calibrates out the
benefit of the board supply decoupling capacitors.
Aperture Delay
The delay in time between the rising edge of the input
sampling clock and the actual time at which the
sampling occurs
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS)
to the noise floor power (PN), excluding the power at
dc and in the first five harmonics.
Clock Pulse Duration/Duty Cycle
The duty cycle of a clock signal is the ratio of the time
the clock signal remains at a logic high (clock pulse
duration) to the period of the clock signal, expressed
as a percentage.
P
10
P
S
SNR + 10log
N
(2)
Differential Nonlinearity (DNL)
SNR is given either in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full scale) when the
power of the fundamental is extrapolated to the
converter’s full-scale range.
An ideal ADC exhibits code transitions at analog input
values spaced exactly 1 LSB apart. DNL is the
deviation of any single step from this ideal value,
measured in units of LSB.
Common-Mode Rejection Ratio (CMRR)
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental
(PS) to the power of all the other spectral components
including noise (PN) and distortion (PD), but excluding
dc.
CMRR measures the ability to reject signals that are
presented to both analog inputs simultaneously. The
injected common-mode frequency level is translated
into dBFS, the spur in the output FFT is measured in
dBFS, and the difference is the CMRR in dB.
P
S
Effective Number of Bits (ENOB)
SINAD + 10log
10
P
) P
ENOB is a measure in units of bits of a converter's
performance as compared to the theoretical limit
based on quantization noise
N
D
(3)
SINAD is given either in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full scale) when the
power of the fundamental is extrapolated to the
converter’s full-scale range.
ENOB = (SINAD – 1.76)/6.02
Gain Error
Gain error is the deviation of the ADC actual input
full-scale range from its ideal value, given as a
percentage of the ideal input full-scale range.
Temperature Drift
Temperature drift (with respect to gain error and
offset error) specifies the change from the value at
Integral Nonlinearity (INL)
the nominal temperature to the value at TMIN or TMAX
It is computed as the maximum variation the
parameters over the whole temperature range divided
.
INL is the deviation of the ADC transfer function from
a best-fit line determined by a least-squares curve fit
of that transfer function. The INL at each analog input
value is the difference between the actual transfer
function and this best-fit line, measured in units of
LSB.
by TMIN – TMAX
.
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS)
to the power of the first five harmonics (PD).
P
10
P
S
THD + 10log
D
(4)
THD is typically given in units of dBc (dB to carrier).
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Two-Tone Intermodulation Distortion (IMD3)
IMD3 is the ratio of the power of the fundamental (at
frequencies f1, f2) to the power of the worst spectral
component at either frequency 2f1 – f2 or 2f2 – f1).
IMD3 is given in units of either dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full scale) when the
power of the fundamental is extrapolated to the
converter’s full-scale range.
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Product Folder Link(s) :ADS5463-EP
PACKAGE OPTION ADDENDUM
www.ti.com
6-Oct-2009
PACKAGING INFORMATION
Orderable Device
ADS5463MPFPEP
V62/07607-01XE
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
HTQFP
PFP
80
96 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
HTQFP
PFP
80
96 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ADS5463-EP :
Catalog: ADS5463
Space: ADS5463-SP
•
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
•
•
Addendum-Page 1
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