ADS54J20IRMPT [TI]
双通道、12 位、1.0GSPS 模数转换器 (ADC) | RMP | 72 | -40 to 85;
| 型号： | ADS54J20IRMPT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双通道、12 位、1.0GSPS 模数转换器 (ADC) | RMP | 72 | -40 to 85 转换器 模数转换器 |
| 文件： | 总86页 (文件大小：3247K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADS54J20
ZHCSF28B –MAY 2016–REVISED JANUARY 2017
ADS54J20 双通道 12 位、1.0GSPS 模数转换器
1 特性
3 说明
1
•
•
•
12 位分辨率、双通道、1GSPS 模数转换器 (ADC)
ADS54J20 是一款低功耗、高带宽、12 位、1.0GSPS
双通道模数转换器 (ADC)。该器件经设计具有高
SNR，可提供 -157dBFS/Hz 的噪底，从而 协助应用
在宽瞬时带宽内 实现最高动态范围。该器件支持
JESD204B 串行接口，数据传输速率高达 10Gbps，每
个 ADC 可支持 2 或 4 条通道。经缓冲的模拟输入可
在较宽频率范围内提供统一输入阻抗并最大程度地降低
采样和保持毛刺脉冲能量。可选择将每条 ADC 通道与
宽带数字下变频器 (DDC) 模块相连。ADS54J20 以超
低功耗在宽输入频率范围内提供出色的无杂散动态范围
(SFDR)。
噪底：–157dBFS/Hz
频谱性能（–1dBFS 时的 fIN = 170MHz）：
–
–
–
SNR：67.8dBFS
NSD：–155dBFS/Hz
无杂散动态范围 (SFDR)：86dBc（包括交错音
调）
–
SFDR：89dBc（不包括 HD2、HD3 和交错音
调）
•
频谱性能（–1dBFS 时的 fIN = 350MHz）：
–
–
–
–
SNR：65.6dBFS
NSD：–152.6dBFS/Hz
SFDR：75dBc
JESD204B 接口减少了接口线路数，从而实现高系统
集成度。内部锁相环 (PLL) 会将 ADC 采样时钟加倍，
以获得对各通道的 12 位数据进行串行化所使用的位时
钟。
SFDR：85dBc（不包括 HD2、HD3 和交错音
调）
•
•
•
•
•
•
通道隔离：fIN = 170MHz 时为 100dBc
输入满量程：1.9 VPP
器件信息
输入带宽 (3dB)：1.2GHz
片上抖动
器件编号
ADS54J20
封装
封装尺寸（标称值）
VQFNP (72)
10.00mm x 10.00mm
集成宽带数字下变频器 (DDC) 模块
支持 JESD204B 子类 1 接口：
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
–
–
–
10.0Gbps 时每个 ADC 2 条通道
5.0Gbps 时每个 ADC 4 条通道
支持多芯片同步
170MHz 输入信号的快速傅立叶变换 (FFT)
0
•
•
功耗：1GSPS 时为 1.35W/通道
{bw = 67.8 dꢀC{
{C5w = 86 dꢀc
bon I52,I53 {pur = 89 dꢀc
-20
封装：72 引脚超薄型四方扁平无引线 (10mm ×
10mm)
-40
2 应用
-60
-80
•
•
•
•
•
•
•
•
雷达和天线阵列
无线宽带
电缆 CMTS、DOCSIS 3.1 接收器
通信测试设备
-100
-120
微波接收器
0
100
200
300
400
500
软件定义无线电 (SDR)
数字转换器
Input Frequency (MHz)
5000
医疗成像和诊断功能
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBAS766
ADS54J20
ZHCSF28B –MAY 2016–REVISED JANUARY 2017
www.ti.com.cn
目录
8.3 Feature Description................................................. 25
8.4 Device Functional Modes........................................ 33
8.5 Register Maps......................................................... 44
Application and Implementation ........................ 68
9.1 Application Information............................................ 68
9.2 Typical Application .................................................. 73
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 7
7.6 AC Characteristics .................................................... 8
7.7 Digital Characteristics ............................................. 11
7.8 Timing Characteristics............................................. 12
7.9 Typical Characteristics............................................ 14
7.10 Typical Characteristics: Contour ........................... 23
Detailed Description ............................................ 24
8.1 Overview ................................................................. 24
8.2 Functional Block Diagram ....................................... 24
9
10 Power Supply Recommendations ..................... 75
10.1 Power Sequencing and Initialization..................... 76
11 Layout................................................................... 77
11.1 Layout Guidelines ................................................. 77
11.2 Layout Example .................................................... 78
12 器件和文档支持 ..................................................... 79
12.1 文档支持................................................................ 79
12.2 接收文档更新通知 ................................................. 79
12.3 社区资源................................................................ 79
12.4 商标....................................................................... 79
12.5 静电放电警告......................................................... 79
12.6 Glossary................................................................ 79
13 机械、封装和可订购信息....................................... 79
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (May 2016) to Revision B
Page
•
•
•
•
•
•
•
•
•
Changed the Device Comparison Table................................................................................................................................. 3
Added the FOVR latency parameter to the Timing Characteristics table............................................................................. 12
Added SYSREF Not Present (Subclass 0, 2) section .......................................................................................................... 30
Changed the number of clock cycles in the Fast OVR section ............................................................................................ 31
Changed the Register Map................................................................................................................................................... 45
Deleted register 39h, 3Ah, and 56h ..................................................................................................................................... 45
Changed Power Supply Recommendations section ........................................................................................................... 75
Added the Power Sequencing and Initialization section....................................................................................................... 76
已添加 接收文档更新通知部分.............................................................................................................................................. 79
Changes from Original (May 2016) to Revision A
Page
•
已发布为“量产数据”................................................................................................................................................................. 1
2
Copyright © 2016–2017, Texas Instruments Incorporated
ADS54J20
www.ti.com.cn
ZHCSF28B –MAY 2016–REVISED JANUARY 2017
5 Device Comparison Table
PART NUMBER
ADS54J20
ADS54J42
ADS54J40
ADS54J60
ADS54J66
ADS54J69
SPEED GRADE (MSPS)
RESOLUTION (Bits)
CHANNEL
1000
625
12
14
14
16
14
16
2
2
2
2
4
2
1000
1000
500
500
6 Pin Configuration and Functions
RMP Package
72-Pin VQFNP
Top View
DB3M
DB3P
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
DA3M
DA3P
DGND
IOVDD
PDN
2
DGND
IOVDD
SDIN
3
4
5
SCLK
6
RES
SEN
7
RESET
DVDD
AVDD
AVDD3V
AVDD
AVDD
INAP
DVDD
AVDD
AVDD3V
SDOUT
AVDD
INBP
8
9
Thermal
Pad
10
11
12
13
14
15
16
17
18
INBM
INAM
AVDD
AVDD3V
AVDD
AGND
AVDD
AVDD3V
AVDD
AGND
Not to scale
Copyright © 2016–2017, Texas Instruments Incorporated
3
ADS54J20
ZHCSF28B –MAY 2016–REVISED JANUARY 2017
www.ti.com.cn
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
CLOCK, SYSREF
CLKINM
28
27
34
33
I
I
I
I
Negative differential clock input for the ADC
Positive differential clock input for the ADC
Negative external SYSREF input
CLKINP
SYSREFM
SYSREFP
Positive external SYSREF input
CONTROL, SERIAL
Power-down. Can be configured via an SPI register setting.
Can be configured as a fast overrange output for channel A via the SPI.
PDN
50
I/O
RESET
SCLK
SDIN
48
6
I
I
I
Hardware reset; active high. This pin has an internal 20-kΩ pulldown resistor.
Serial interface clock input
5
Serial interface data input
Serial interface data output.
Can be configured as a fast overrange output for channel B via the SPI.
SDOUT
11
7
O
I
SEN
Serial interface enable
DATA INTERFACE
DA0M
DA1M
DA2M
DA3M
DA0P
62
59
56
54
61
58
55
53
65
68
71
1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
JESD204B serial data negative output for channel A
DA1P
JESD204B serial data positive output for channel A
JESD204B serial data negative output for channel B
DA2P
DA3P
DB0M
DB1M
DB2M
DB3M
DB0P
66
69
72
2
DB1P
JESD204B serial data positive output for channel B
Synchronization input for the JESD204B port
DB2P
DB3P
SYNC
INPUT, COMMON MODE
INAM
63
41
42
14
13
I
I
I
I
Differential analog negative input for channel A
Differential analog positive input for channel A
Differential analog negative input for channel B
Differential analog positive input for channel B
Common-mode voltage, 2.1 V.
INAP
INBM
INBP
VCM
22
O
Note that analog inputs are internally biased to this pin through 600 Ω (effective), no external
connection from the VCM pin to the INxP or INxM pin is required.
POWER SUPPLY
AGND
AVDD
18, 23, 26, 29, 32, 36, 37
I
I
Analog ground
9, 12, 15, 17, 25, 30, 35, 38,
40, 43, 44, 46
Analog 1.9-V power supply
AVDD3V
DGND
DVDD
IOVDD
NC, RES
NC
10, 16, 24, 31, 39, 45
3, 52, 60, 67
8, 47
I
I
I
I
Analog 3.0-V power supply for the analog buffer
Digital ground
Digital 1.9-V power supply
4, 51, 57, 64, 70
Digital 1.15-V power supply for the JESD204B transmitter
19, 20, 21
49
—
I
Unused pin, do not connect
RES
Reserved pin. Connect to DGND.
4
Copyright © 2016–2017, Texas Instruments Incorporated
ADS54J20
www.ti.com.cn
ZHCSF28B –MAY 2016–REVISED JANUARY 2017
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.2
–0.3
–0.3
–0.3
–0.3
–0.2
–65
MAX
UNIT
V
AVDD3V
3.6
AVDD
Supply voltage range
DVDD
2.1
2.1
IOVDD
Voltage between AGND and DGND
INAP, INBP, INAM, INBM
1.4
0.3
3
V
CLKINP, CLKINM
Voltage applied to input pins
AVDD + 0.3
AVDD + 0.3
2.1
V
SYSREFP, SYSREFM
SCLK, SEN, SDIN, RESET, SYNC, PDN
Storage temperature, Tstg
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±1000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V HBM allows safe manufacturing with a standard ESD control process.
Copyright © 2016–2017, Texas Instruments Incorporated
5
ADS54J20
ZHCSF28B –MAY 2016–REVISED JANUARY 2017
www.ti.com.cn
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
2.85
1.8
NOM
3.0
MAX
UNIT
AVDD3V
3.6
2.0
2.0
1.2
AVDD
Supply voltage range
DVDD
1.9
V
1.7
1.9
IOVDD
1.1
1.15
1.9
Differential input voltage range
VPP
V
Input common-mode voltage
2.0
Analog inputs
Maximum analog input frequency for a 1.9-VPP input
amplitude(3)(4)
400
MHz
MHz
Input clock frequency, device clock frequency
250(5)
0.75
0.8
1000
Sine wave, ac-coupled
1.5
1.6
Input clock amplitude differential
Clock inputs
Temperature
LVPECL, ac-coupled
LVDS, ac-coupled
VPP
(VCLKP – VCLKM
)
0.7
Input device clock duty cycle
Operating free-air, TA
45%
–40
50%
55%
85
ºC
Operating junction, TJ
105(6)
125
(1) SYSREF must be applied for the device to initialize; see the SYSREF Signal section for details.
(2) After power-up, always use a hardware reset to reset the device for the first time; see Table 65 for details.
(3) Operating 0.5 dB below the maximum-supported amplitude is recommended to accommodate gain mismatch in interleaving ADCs.
(4) At high frequencies, the maximum supported input amplitude reduces; see Figure 36 for details.
(5) See Table 10 and Table 12.
(6) Prolonged use above the nominal junction temperature can increase the device failure-in-time (FIT) rate.
7.4 Thermal Information
ADS54J20
THERMAL METRIC(1)
RMP (VQFNP)
UNIT
72 PINS
22.3
5.1
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
2.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.1
ψJB
2.3
RθJC(bot)
0.4
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6
Copyright © 2016–2017, Texas Instruments Incorporated
ADS54J20
www.ti.com.cn
ZHCSF28B –MAY 2016–REVISED JANUARY 2017
7.5 Electrical Characteristics
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 1.0 GSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital
gain (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GENERAL
ADC sampling rate
Resolution
1000 MSPS
Bits
12
POWER SUPPLIES
AVDD3V
AVDD
3.0-V analog supply
2.85
1.8
3.0
1.9
3.6
2.0
V
V
1.9-V analog supply
DVDD
IOVDD
IAVDD3V
IAVDD
1.9-V digital supply
1.7
1.9
2.0
V
1.15-V SerDes supply
3.0-V analog supply current
1.9-V analog supply current
1.1
1.15
334
359
197
1.2
V
VIN = full-scale on both channels
VIN = full-scale on both channels
8 lanes active (LMFS = 8224)
360
510
260
mA
mA
mA
4 lanes active (LMFS = 4222),
2X decimation
197
mA
IDVDD
IIOVDD
PD
1.9-V digital supply current
2 lanes active (LMFS = 2221),
4X decimation
176
566
593
mA
mA
mA
8 lanes active (LMFS = 8224)
920
3.1
4 lanes active (LMFS = 4222),
2X decimation
1.15-V SerDes supply current
2 lanes active (LMFS = 2221),
4X decimation
562
2.71
2.74
mA
W
8 lanes active (LMFS = 8224)
4 lanes active (LMFS = 4222),
2X decimation
W
Total power dissipation(1)
2 lanes active (LMFS = 2221),
4X decimation
2.66
139
W
Global power-down power dissipation
315
mW
ANALOG INPUTS (INAP, INAM, INBP, INBM)
Differential input full-scale voltage
1.9
2.0
0.6
4.7
VPP
V
VIC
RIN
CIN
Common-mode input voltage
Differential input resistance
Differential input capacitance
At 170-MHz input frequency
At 170-MHz input frequency
kΩ
pF
50-Ω source driving ADC inputs
terminated with 50 Ω
Analog input bandwidth (3 dB)
1.2
GHz
CLOCK INPUT (CLKINP, CLKINM)
CLKINP and CLKINM are
connected to internal biasing
voltage through 400 Ω
Internal clock biasing
1.15
V
(1) See the Power-Down Mode section for details.
Copyright © 2016–2017, Texas Instruments Incorporated
7
ADS54J20
ZHCSF28B –MAY 2016–REVISED JANUARY 2017
www.ti.com.cn
7.6 AC Characteristics
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 1.0 GSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input amplitude, and
0-dB digital gain (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fIN = 10 MHz, AIN = –1 dBFS
MIN
TYP
68.4
68.3
67.8
67.4
67.0
66.7
65.8
66.3
65.5
61.5
155.4
155.3
154.8
154.4
154.0
153.7
152.8
153.3
152.5
148.5
68.3
68.1
67.7
67.2
66.7
66.3
65.0
65.7
64.7
60.8
85.0
83.0
86.0
85.0
81.0
78.0
73.0
72.0
68.0
69.0
MAX
UNIT
fIN = 100 MHz, AIN = –1 dBFS
fIN = 170 MHz, AIN = –1 dBFS
fIN = 230 MHz, AIN = –1 dBFS
fIN = 270 MHz, AIN = –1 dBFS
fIN = 300 MHz, AIN = –1 dBFS
fIN = 370 MHz, AIN = –1 dBFS
fIN = 470 MHz, AIN = –3 dBFS
64
SNR
Signal-to-noise ratio
dBFS
AIN = –6 dBFS
fIN = 720 MHz
AIN = –6 dBFS, gain = 5 dB
fIN = 10 MHz, AIN = –1 dBFS
fIN = 100 MHz, AIN = –1 dBFS
fIN = 170 MHz, AIN = –1 dBFS
fIN = 230 MHz, AIN = –1 dBFS
fIN = 270 MHz, AIN = –1 dBFS
fIN = 300 MHz, AIN = –1 dBFS
fIN = 370 MHz, AIN = –1 dBFS
fIN = 470 MHz, AIN = –3 dBFS
151
63.2
74
NSD
Noise spectral density
dBFS/Hz
dBFS
dBc
AIN = –6 dBFS
fIN = 720 MHz
AIN = –6 dBFS, gain = 5 dB
fIN = 10 MHz, AIN = –1 dBFS
fIN = 100 MHz, AIN = –1 dBFS
fIN = 170 MHz, AIN = –1 dBFS
fIN = 230 MHz, AIN = –1 dBFS
fIN = 270 MHz, AIN = –1 dBFS
fIN = 300 MHz, AIN = –1 dBFS
fIN = 370 MHz, AIN = –1 dBFS
fIN = 470 MHz, AIN = –3 dBFS
Signal-to-noise and
distortion ratio
SINAD
AIN = –6 dBFS
fIN = 720 MHz
AIN = –6 dBFS, gain = 5 dB
fIN = 10 MHz, AIN = –1 dBFS
fIN = 100 MHz, AIN = –1 dBFS
fIN = 170 MHz, AIN = –1 dBFS
fIN = 230 MHz, AIN = –1 dBFS
fIN = 270 MHz, AIN = –1 dBFS
fIN = 300 MHz, AIN = –1 dBFS
fIN = 370 MHz, AIN = –1 dBFS
fIN = 470 MHz, AIN = –3 dBFS
Spurious-free dynamic range
(excluding IL spurs)
SFDR
AIN = –6 dBFS
fIN = 720 MHz
AIN = –6 dBFS, gain = 5 dB
8
Copyright © 2016–2017, Texas Instruments Incorporated
ADS54J20
www.ti.com.cn
ZHCSF28B –MAY 2016–REVISED JANUARY 2017
AC Characteristics (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 1.0 GSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input amplitude, and
0-dB digital gain (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fIN = 10 MHz, AIN = –1 dBFS
MIN
TYP
85.0
90.0
92.0
85.0
81.0
81.0
76.0
72.0
68.0
69.0
85.0
83.0
86.0
87.0
81.0
78.0
73.0
70.0
77.0
79.0
94.0
97.0
93.0
95.0
95.0
91.0
85.0
88.0
80.0
83.0
11.1
11.0
11.0
10.9
10.8
10.7
10.5
10.6
10.5
9.8
MAX
UNIT
fIN = 100 MHz, AIN = –1 dBFS
fIN = 170 MHz, AIN = –1 dBFS
fIN = 230 MHz, AIN = –1 dBFS
fIN = 270 MHz, AIN = –1 dBFS
fIN = 300 MHz, AIN = –1 dBFS
fIN = 370 MHz, AIN = –1 dBFS
fIN = 470 MHz, AIN = –3 dBFS
74
Second-order harmonic
distortion
HD2
dBc
AIN = –6 dBFS
fIN = 720 MHz
AIN = –6 dBFS, gain = 5 dB
fIN = 10 MHz, AIN = –1 dBFS
fIN = 100 MHz, AIN = –1 dBFS
fIN = 170 MHz, AIN = –1 dBFS
fIN = 230 MHz, AIN = –1 dBFS
fIN = 270 MHz, AIN = –1 dBFS
fIN = 300 MHz, AIN = –1 dBFS
fIN = 370 MHz, AIN = –1 dBFS
fIN = 470 MHz, AIN = –3 dBFS
74
Third-order harmonic
distortion
HD3
dBc
dBFS
Bits
AIN = –6 dBFS
fIN = 720 MHz
AIN = –6 dBFS, gain = 5 dB
fIN = 10 MHz, AIN = –1 dBFS
fIN = 100 MHz, AIN = –1 dBFS
fIN = 170 MHz, AIN = –1 dBFS
fIN = 230 MHz, AIN = –1 dBFS
fIN = 270 MHz, AIN = –1 dBFS
fIN = 300 MHz, AIN = –1 dBFS
fIN = 370 MHz, AIN = –1 dBFS
fIN = 470 MHz, AIN = –3 dBFS
77
Non
HD2,
HD3
Spurious-free dynamic range
(excluding HD2, HD3, and
IL spur)
AIN = –6 dBFS
fIN = 720 MHz
AIN = –6 dBFS, gain = 5 dB
fIN = 10 MHz, AIN = –1 dBFS
fIN = 100 MHz, AIN = –1 dBFS
fIN = 170 MHz, AIN = –1 dBFS
fIN = 230 MHz, AIN = –1 dBFS
fIN = 270 MHz, AIN = –1 dBFS
fIN = 300 MHz, AIN = –1 dBFS
fIN = 370 MHz, AIN = –1 dBFS
fIN = 470 MHz, AIN = –3 dBFS
10.2
ENOB
Effective number of bits
AIN = –6 dBFS
fIN = 720 MHz
AIN = –6 dBFS, gain = 5 dB
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AC Characteristics (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 1.0 GSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input amplitude, and
0-dB digital gain (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fIN = 10 MHz, AIN = –1 dBFS
MIN
TYP
82.0
80.0
83.0
82.0
78.0
75.0
70.0
71.0
67.0
69.0
84.0
85.0
84.0
83.0
82.0
81.0
81.0
78.0
79.0
82.0
MAX
UNIT
fIN = 100 MHz, AIN = –1 dBFS
fIN = 170 MHz, AIN = –1 dBFS
fIN = 230 MHz, AIN = –1 dBFS
fIN = 270 MHz, AIN = –1 dBFS
fIN = 300 MHz, AIN = –1 dBFS
fIN = 370 MHz, AIN = –1 dBFS
fIN = 470 MHz, AIN = –3 dBFS
72
THD
Total harmonic distortion
dBc
AIN = –6 dBFS
fIN = 720 MHz
AIN = –6 dBFS, gain = 5 dB
fIN = 10 MHz, AIN = –1 dBFS
fIN = 100 MHz, AIN = –1 dBFS
fIN = 170 MHz, AIN = –1 dBFS
fIN = 230 MHz, AIN = –1 dBFS
fIN = 270 MHz, AIN = –1 dBFS
fIN = 300 MHz, AIN = –1 dBFS
fIN = 370 MHz, AIN = –1 dBFS
fIN = 470 MHz, AIN = –3 dBFS
69
SFDR_IL Interleaving spur
dBc
AIN = –6 dBFS
fIN = 720 MHz
AIN = –6 dBFS, gain = 5 dB
fIN1 = 185 MHz, fIN2 = 190 MHz,
AIN = –7 dBFS
85
79
Two-tone, third-order
IMD3
fIN1 = 365 MHz, fIN2 = 370 MHz,
AIN = –7 dBFS
dBFS
dB
intermodulation distortion
fIN1 = 465 MHz, fIN2 = 470 MHz,
AIN = –7 dBFS
75
Crosstalk isolation between
channel A and B
Full-scale, 170-MHz signal on aggressor, idle
channel is victim
100
10
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7.7 Digital Characteristics
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 1.0 GSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital
gain (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (RESET, SCLK, SEN, SDIN, SYNC, PDN)(1)
VIH
VIL
High-level input voltage
Low-level input voltage
All digital inputs support 1.2-V and 1.8-V logic levels
All digital inputs support 1.2-V and 1.8-V logic levels
SEN
0.8
V
V
0.4
0
50
50
0
IIH
High-level input current
Low-level input current
µA
µA
RESET, SCLK, SDIN, PDN, SYNC
SEN
IIL
RESET, SCLK, SDIN, PDN, SYNC
DIGITAL INPUTS (SYSREFP, SYSREFM)
VD
Differential input voltage
Common-mode voltage for SYSREF(2)
0.35
0.45
1.3
1.4
V
V
V(CM_DIG)
DIGITAL OUTPUTS (SDOUT, PDN(2)
)
DVDD –
0.1
VOH
VOL
High-level output voltage
Low-level output voltage
DVDD
V
V
0.1
DIGITAL OUTPUTS (JESD204B Interface: DxP, DxM)(3)
VOD
VOC
Output differential voltage
With default swing setting
700
450
mVPP
mV
Output common-mode voltage
Transmitter pins shorted to any voltage between
–0.25 V and 1.45 V
Transmitter short-circuit current
Single-ended output impedance
Output capacitance
–100
100
mA
Ω
zos
50
2
Output capacitance inside the device,
from either output to ground
pF
(1) The RESET, SCLK, SDIN, and PDN pins have a 20-kΩ (typical) internal pulldown resistor to ground, and the SEN pin has a 20-kΩ
(typical) pullup resistor to IOVDD.
(2) When functioning as an OVR pin for channel B.
(3) 100-Ω differential termination.
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7.8 Timing Characteristics
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 1.0 GSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input (unless
otherwise noted)
MIN
TYP
MAX
UNITS
SAMPLE TIMING
Aperture delay
0.75
1.6
ns
ps
Aperture delay matching between two channels on the same device
Aperture delay matching between two devices at the same temperature and supply voltage
Aperture jitter
±70
±270
120
ps
fS rms
WAKE-UP TIMING
Wake-up time to valid data after coming out of global power-down
150
µs
LATENCY
Input
clock
cycles
Data latency(1): ADC sample to digital output
OVR latency: ADC sample to OVR bit
134
62
Input
clock
cycles
Input
clock
cycles
FOVR latency: ADC sample to FOVR signal on pin
18 + 4 ns
4
tPD
Propagation delay: logic gates and output buffers delay (does not change with fS)
ns
SYSREF TIMING
tSU_SYSREF Setup time for SYSREF, referenced to the input clock falling edge
300
100
900
ps
ps
tH_SYSREF
Hold time for SYSREF, referenced to the input clock falling edge
JESD OUTPUT INTERFACE TIMING CHARACTERISTICS
Unit interval
100
2.5
400
ps
Gbps
ps
Serial output data rate
6.25
Total jitter for BER of 1E-15 and lane rate = 6.25 Gbps
Random jitter for BER of 1E-15 and lane rate = 6.25 Gbps
Deterministic jitter for BER of 1E-15 and lane rate = 6.25 Gbps
26
0.75
12
ps rms
ps, pk-pk
Data rise time, data fall time: rise and fall times are measured from 20% to 80%,
differential output waveform, 2.5 Gbps ≤ bit rate ≤ 6.25 Gbps
tR, tF
35
ps
(1) Overall ADC latency = data latency + tPDI
.
Sample N
tH_SYSREF
tSU_SYSREF
CLKIN
1.0 GSPS
SYSREF
Figure 1. SYSREF Timing
12
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N+1
N+2
N
N+3
Sample
tPD
Data Latency: 134 Clock Cycles
CLKINM
CLKINP
D
20
D
11
D
20
D
11
D
20
DA0P, DA0M,
DB0P, DB0M
Sample N-1
Sample N
Sample N+1
Sample N+2
D
10
D
1
D
10
D
1
D
10
DA1P, DA1M,
DB1P, DB1M
Sample N-1
Sample N
Sample N+1
Sample N+2
Figure 2. Sample Timing Requirements
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7.9 Typical Characteristics
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 1.0 GSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital
gain (unless otherwise noted)
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
100
200
300
400
500
0
100
200
300
400
500
Input Frequency (MHz)
Input Frequency (MHz)
D001
D002
SNR = 68.4 dBFS, SINAD = 68.3 dBFS,
SNR = 67.9 dBFS, SINAD = 67.8 dBFS,
THD = 84 dBc, IL spur = 89 dBc, SFDR = 87 dBc,
non HD2, HD3 spur = 93 dBc
SFDR = 87 dBc, THD = 85 dBc, IL spur = 88 dBc,
non HD2, HD3 spur = 96 dBc
Figure 3. FFT for 10-MHz Input Signal
Figure 4. FFT for 140-MHz Input Signal
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
100
200
300
400
500
0
100
200
300
400
500
Input Frequency (MHz)
Input Frequency (MHz)
D003
D004
SNR = 67.8 dBFS, SINAD = 67.7 dBFS,
SNR = 67.4 dBFS, SINAD = 67.2 dBFS,
SFDR = 86 dBc, THD = 81 dBc, IL spur = 88 dBc,
non HD2, HD3 spur = 89 dBc
IL spur = 87 dBc, SFDR = 84 dBc, THD = 82 dBc,
non HD2, HD3 spur = 90 dBc
Figure 5. FFT for 170-MHz Input Signal
Figure 6. FFT for 230-MHz Input Signal
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
100
200
300
400
500
0
100
200
300
400
500
Input Frequency (MHz)
Input Frequency (MHz)
D005
D006
SNR = 66.7 dBFS, SINAD = 66.3 dBFS,
IL spur = 85 dBc, SFDR = 77 dBc, THD = 76 dBc,
non HD2, HD3 spur = 92 dBc
SNR = 65.8 dBFS, SINAD = 65 dBFS,
SFDR = 74 dBc, THD = 72 dBc,
IL spur = 85 dBc, non HD2, HD3 spur = 86 dBc
Figure 7. FFT for 300-MHz Input Signal
Figure 8. FFT for 370-MHz Input Signal
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Typical Characteristics (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 1.0 GSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital
gain (unless otherwise noted)
0
0
-20
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
100
200
300
400
500
0
100
200
300
400
500
Input Frequency (MHz)
Input Frequency (MHz)
D007
D008
SNR = 66.3 dBFS, SINAD = 65.7 dBFS,
SFDR = 72 dBc, THD = 71 dBc,
fIN1 = 185 MHz, fIN2 = 190 MHz, each tone at –7 dBFS,
IMD = 85 dBFS
IL spur = 81 dBc, non HD2, HD3 spur = 90 dBc
Figure 9. FFT for 470-MHz Input Signal
Figure 10. FFT for Two-Tone Input Signal (–7 dBFS)
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
100
200
300
400
500
0
100
200
300
400
500
Input Frequency (MHz)
Input Frequency (MHz)
D009
D010
fIN1 = 185 MHz, fIN2 = 190 MHz, each tone at –36 dBFS,
IMD = 103 dBFS
fIN1 = 370 MHz, fIN2 = 365 MHz, each tone at –7 dBFS,
IMD = 80 dBFS
Figure 11. FFT for Two-Tone Input Signal (–36 dBFS)
Figure 12. FFT for Two-Tone Input Signal (–7 dBFS)
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
100
200
300
400
500
0
100
200
300
400
500
Input Frequency (MHz)
Input Frequency (MHz)
D011
D012
fIN1 = 370 MHz, fIN2 = 365 MHz, each tone at –36 dBFS,
IMD = 109 dBFS
fIN1 = 470 MHz, fIN2 = 465 MHz, each tone at –7 dBFS,
IMD = 74.9 dBFS
Figure 13. FFT for Two-Tone Input Signal (–36 dBFS)
Figure 14. FFT for Two-Tone Input Signal (–7 dBFS)
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Typical Characteristics (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 1.0 GSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital
gain (unless otherwise noted)
0
-80
-84
-20
-88
-40
-92
-60
-96
-80
-100
-100
-120
-104
-35
-31
-27
-23
-19
-15
-11
-7
0
100
200
300
400
500
Each Tone Amplitude (dBFS)
D014
Input Frequency (MHz)
D013
fIN1 = 185 MHz, fIN2 = 190 MHz
fIN1 = 470 MHz, fIN2 = 465 MHz, each tone at –36 dBFS,
IMD = 109.2 dBFS
Figure 16. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
Figure 15. FFT for Two-Tone Input Signal
(–36 dBFS)
-76
-80
-70
-74
-78
-84
-82
-88
-86
-90
-92
-94
-96
-98
-100
-104
-102
-106
-35
-31
-27
-23
-19
-15
-11
-7
-35
-31
-27
-23
-19
-15
-11
-7
Each Tone Amplitude (dBFS)
Each Tone Amplitude (dBFS)
D015
D016
fIN1 = 365 MHz, fIN2 = 370 MHz
fIN1 = 465 MHz, fIN2 = 470 MHz
Figure 17. Intermodulation Distortion vs Input Amplitude
(365 MHz and 370 MHz)
Figure 18. Intermodulation Distortion vs Input Amplitude
(465 MHz and 470 MHz)
95
90
86
82
78
74
70
AIN = -6 dBFS
AIN = -3 dBFS
AIN = -1 dBFS
90
85
80
75
70
65
60
55
0
100
200
300
400
500
600
700
0
40 80 120 160 200 240 280 320 360 400 440 480
Input Frequency (MHz)
Input Frequency (MHz)
D043
D018
Figure 19. Spurious-Free Dynamic Range vs
Input Frequency
Figure 20. Interleaving Spur vs Input Frequency
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Typical Characteristics (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 1.0 GSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital
gain (unless otherwise noted)
71
70
69
68
67
66
65
71
70.5
70
AIN = -6 dBFS
AIN = -3 dBFS
AIN = -1 dBFS
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.95 V
AVDD = 2 V
69.5
69
68.5
68
67.5
67
0
100
200
300
400
500
600
700
-40
-15
10
35
60
85
Input Frequency (MHz)
Temperature (°C)
D042
D020
fIN = 170 MHz
Figure 21. Signal-to-Noise Ratio vs Input Frequency
Figure 22. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
94
72
71
70
69
68
67
66
65
64
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.95 V
AVDD = 2 V
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.95 V
AVDD = 2 V
92
90
88
86
84
82
80
78
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
D021
D022
fIN = 170 MHz
fIN = 350 MHz
Figure 23. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature
Figure 24. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
79
78
77
76
75
74
73
71
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.95 V
AVDD = 2 V
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.85 V
DVDD = 1.9 V
DVDD = 1.95 V
DVDD = 2 V
70.2
69.4
68.6
67.8
67
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
D023
D024
fIN = 350 MHz
fIN = 170 MHz
Figure 25. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature
Figure 26. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
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Typical Characteristics (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 1.0 GSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital
gain (unless otherwise noted)
92
90
88
86
84
82
70
69
68
67
66
65
64
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.85 V
DVDD = 1.9 V
DVDD = 1.95 V
DVDD = 2 V
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.85 V
DVDD = 1.9 V
DVDD = 1.95 V
DVDD = 2 V
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
D025
D026
fIN = 170 MHz
fIN = 350 MHz
Figure 27. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature
Figure 28. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
70
82
80
78
76
74
72
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.85 V
DVDD = 1.9 V
DVDD = 1.95 V
DVDD = 2 V
AVDD3V = 2.85 V
AVDD3V = 3 V
AVDD3V = 3.1 V
AVDD3V = 3.2 V
AVDD3V = 3.3 V
AVDD3V = 3.4 V
AVDD3V = 3.5 V
AVDD3V = 3.6 V
69.5
69
68.5
68
67.5
67
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
D027
D028
fIN = 350 MHz
fIN = 170 MHz
Figure 29. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature
Figure 30. Signal-to-Noise Ratio vs
AVDD3V Supply and Temperature
71
70
69
68
67
66
65
64
94
92
90
88
86
84
82
80
AVDD3V = 2.85 V
AVDD3V = 3 V
AVDD3V = 3.1 V
AVDD3V = 3.2 V
AVDD3V = 3.3 V
AVDD3V = 3.4 V
AVDD3V = 3.5 V
AVDD3V = 3.6 V
AVDD3V = 2.85 V
AVDD3V = 3 V
AVDD3V = 3.1 V
AVDD3V = 3.2 V
AVDD3V = 3.3 V
AVDD3V = 3.4 V
AVDD3V = 3.5 V
AVDD3V = 3.6 V
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
D030
D029
fIN = 350 MHz
fIN = 170 MHz
Figure 32. Signal-to-Noise Ratio vs
AVDD3V Supply and Temperature
Figure 31. Spurious-Free Dynamic Range vs
AVDD3V Supply and Temperature
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Typical Characteristics (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 1.0 GSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital
gain (unless otherwise noted)
82
80
78
76
74
72
79
76
73
70
67
64
61
58
55
AVDD3V = 2.85 V
AVDD3V = 3 V
AVDD3V = 3.1 V
AVDD3V = 3.2 V
AVDD3V = 3.3 V
AVDD3V = 3.4 V
AVDD3V = 3.5 V
AVDD3V = 3.6 V
Gain = 0 dB
Gain = 2 dB
Gain = 4 dB
Gain = 6 dB
Gain = 8 dB
Gain = 10 dB
Gain = 12 dB
-40
-15
10
35
60
85
10
102
194
286
378
470
Temperature (°C)
Input Frequency (MHz)
D031
D053
fIN = 350 MHz
Figure 33. Spurious-Free Dynamic Range vs
AVDD3V Supply and Temperature
Figure 34. Signal-to-Noise Ratio vs
Gain and Input Frequency
110
105
100
95
2
Gain = 0 dB
Gain = 2 dB
Gain = 4 dB
Gain = 6 dB
Gain = 8 dB
Gain = 10 dB
Gain = 12 dB
0
-2
90
-4
85
80
-6
75
-8
70
65
-10
10
102
194
286
378
470
0
100 200 300 400 500 600 700 800 900 1000
Input Frequency (MHz)
Input Frequency (MHz)
D054
D046
Figure 35. Spurious-Free Dynamic Range vs
Gain and Input Frequency
Figure 36. Maximum Supported Amplitude vs Frequency
73
71
69
67
65
63
150
SNR (dBFS)
SFDR (dBc)
73.5
72
210
180
150
120
90
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS)
SFDR (dBFS)
120
70.5
69
90
60
30
0
67.5
66
60
64.5
63
30
0
-70
-60
-50
-40
-30
-20
-10
0
-70
-60
-50
-40
-30
-20
-10
0
Amplitude (dBFS)
Amplitude (dBFS)
D032
D033
fIN = 170 MHz
fIN = 350 MHz
Figure 37. Performance vs Input Amplitude
Figure 38. Performance vs Input Amplitude
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Typical Characteristics (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 1.0 GSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital
gain (unless otherwise noted)
74
72
70
68
66
64
100
90
80
70
60
50
75
72
69
66
63
60
125
100
75
50
25
0
SNR
SFDR
SNR
SFDR
0.2
0.6
1
1.4
1.8
2.2
0.2
0.6
1
1.4
1.8
2.2
Differential Clock Amplitude (Vpp)
Differential Clock Amplitude (Vpp)
D034
D035
fIN = 170 MHz
fIN = 350 MHz
Figure 39. Performance vs Sampling Clock Amplitude
Figure 40. Performance vs Sampling Clock Amplitude
(Differential)
71
70
69
68
67
66
95
90
85
80
75
70
71
70
69
68
67
66
65
64
88
84
80
76
72
68
64
60
SNR
SFDR
SNR
SFDR
30
35
40
45
50
55
60
65
70
30
35
40
45
50
55
60
65
70
Input Clock Duty Cycle (%)
Input Clock Duty Cycle (%)
D036
D037
fIN = 170 MHz
fIN = 350 MHz
Figure 41. Performance vs Clock Duty Cycle
Figure 42. Performance vs Clock Duty Cycle
0
-20
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
PSRR with 25-mVpp Signal on AVDD
PSRR with 50-mVpp Signal on AVDD3V
-40
-60
-80
-100
-120
0
100
200
300
400
500
Input Frequency (MHz)
0
50
100
150
200
250
300
D039
Frequency of Signal on Supply (MHz)
D038
SNR = 66.7 dBFS, SINAD = 65.7 dBFS,
SFDR = 79 dBc, fIN = 170.1 MHz,
fPSRR = 5 MHz, non HD2, HD3 spur = 84 dBc
Figure 44. Power-Supply Rejection Ratio FFT for
Test Signals on the AVDD Supply
Figure 43. Power-Supply Rejection Ratio vs Supply Signal
20
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Typical Characteristics (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 1.0 GSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital
gain (unless otherwise noted)
-20
-25
-30
-35
-40
-45
-50
-55
0
-20
-40
-60
-80
-100
-120
0
50
100
150
200
250
300
0
100
200
300
400
500
Frequency of Input Common-Mode Signal (MHz)
Input Frequency (MHz)
D040
D041
Figure 45. Common-Mode Rejection Ratio vs Signal
Frequency
Figure 46. Common-Mode Rejection Ratio FFT
4
3.5
3
800
700
600
500
400
300
200
100
2.78
I DVDD (mA)
I AVDD (mA)
I IOVDD (mA)
I AVDD3 (mA)
Total Power (W)
2.76
2.74
2.72
2.7
2.5
2
2.68
2.66
2.64
1.5
1
500 550 600 650 700 750 800 850 900 950 1000
-40
-15
10
35
60
85
Sampling Speed (MSPS)
Temperature (°C)
D042
D045
Figure 47. Power Consumption vs Sampling Speed
Figure 48. Power vs Temperature
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
25
50
75
100
125
0
25
50
75
100
125
Input Frequency (MHz)
Input Frequency (MHz)
D047
D048
SNR = 70.5 dBFS, SINAD = 69.9 dBFS,
SNR = 70.2 dBFS, SINAD = 69.6 dBFS,
fS = 250 MHz, fIN = 60 MHz, SFDR = 88.6 dBc,
THD = 83 dBc, non HD2, HD3 spur = 99.96 dBc
fS = 250 MHz, fIN = 170 MHz, SFDR = 87 dBc,
non HD2, HD3 spur = 90.42 dBc
Figure 49. FFT for 60-MHz Input Signal in
Decimate-by-4 Mode
Figure 50. FFT for 170-MHz Input Signal in
Decimate-by-4 Mode
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Typical Characteristics (continued)
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 1.0 GSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital
gain (unless otherwise noted)
0
0
-20
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
25
50
75
100
125
0
25
50
75
100
125
Input Frequency (MHz)
Input Frequency (MHz)
D049
D050
SNR = 69.3 dBFS, SINAD = 68.6 dBFS,
SNR = 67.6 dBFS, SINAD = 66.8 dBFS,
fS = 250 MHz, fIN = 300 MHz, SFDR = 86 dBc,
non HD2, HD3 spur = 94.42 dBc
fS = 250 MHz, fIN = 450 MHz, SFDR = 83 dBc,
non HD2, HD3 spur = 90.44 dBc
Figure 51. FFT for 300-MHz Input Signal in
Decimate-by-4 Mode
Figure 52. FFT for 450-MHz Input Signal in
Decimate-by-4 Mode
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
50
100
150
200
250
0
50
100
150
200
250
Input Frequency (MHz)
Input Frequency (MHz)
D051
D052
SNR = 68.9 dBFS, SINAD = 68.2 dBFS,
SNR = 66.7 dBFS, SINAD = 65.9 dBFS,
fS = 500 MHz, fIN = 170 MHz, SFDR = 86 dBc,
non HD2, HD3 spur = 81.94 dBc
fS = 500 MHz, fIN = 350 MHz, SFDR = 80 dBc,
non HD2, HD3 spur = 80.83 dBc
Figure 53. FFT for 170-MHz Input Signal in
Decimate-by-2 Mode
Figure 54. FFT for 350-MHz Input Signal in
Decimate-by-2 Mode
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7.10 Typical Characteristics: Contour
typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = +85°C, ADC sampling rate = 1.0 GSPS,
50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital
gain (unless otherwise noted)
1000
950
900
850
800
750
700
69.0
68.5
68.0
67.5
67.0
66.5
66.0
65.5
65.0
1000
950
900
850
800
750
700
90
87
84
81
78
75
72
69
66
0
50
100 150 200 250 300 350 400 450
Input Fre que ncy (MHz)
0
50
100 150 200 250 300 350 400 450
Input Fre que ncy (MHz)
Figure 55. Signal-to-Noise-Ratio with
0-dB Digital Gain
Figure 56. Spurious-Free Dynamic Range with
0-dB Digital Gain
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8 Detailed Description
8.1 Overview
The ADS54J20 is a low-power, wide-bandwidth, 12-bit, 1.0-GSPS, dual-channel, analog-to-digital converter
(ADC). The ADS54J20 employs four interleaving ADCs for each channel to achieve a noise floor of
–157 dBFS/Hz. The ADS54J20 uses TI's proprietary interleaving and dither algorithms to achieve a clean
spectrum with a high spurious-free dynamic range (SFDR). The device also offers various programmable
decimation filtering options for systems requiring higher signal-to-noise ratio (SNR) and SFDR over a wide range
of frequencies.
Analog input buffers isolate the ADC driver from glitch energy generated from sampling process, thereby
simplifying the driving network on-board. The JESD204B interface reduces the number of interface lines with
two-lane and four-lane options, allowing for a high system integration density. The JESD204B interface operates
in subclass 1, enabling multi-chip synchronization with the SYSREF input.
8.2 Functional Block Diagram
DA0P, DA0M,
DA1P, DA1M
DDC Block:
2X, 4X Decimation
Mixer: fS / 16, fS / 4
Buffer
Digital Block
ADC
Interleaving
Correction
INAP, INAM
DA2P, DA2M,
DA3P, DA3M
PLL:
x20
x40
Divide-
by-4
CLKINP,
CLKINM
SYNC
SYSREFP,
SYSREFM
DDC Block:
2X, 4X Decimation
Mixer: fS / 16, fS / 4
DB0P, DB0M,
DB1P, DB1M
Buffer
Digital Block
ADC
Interleaving
Correction
INBP, INBM
DB2P, DB2M,
DB3P, DB3M
FOVR
Control and SPI
Common
Mode
VCM
TI Device
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8.3 Feature Description
8.3.1 Analog Inputs
The ADS54J20 analog signal inputs are designed to be driven differentially. The analog input pins have internal
analog buffers that drive the sampling circuit. Resulting from the analog buffer, the input pins present a high
impedance input across a very wide frequency range to the external driving source that enables great flexibility in
the external analog filter design as well as excellent 50-Ω matching for RF applications. The buffer also helps
isolate the external driving circuit from the internal switching currents of the sampling circuit, resulting in a more
constant SFDR performance across input frequencies.
The common-mode voltage of the signal inputs is internally biased to VCM using 600-Ω resistors, allowing for ac-
coupling of the input drive network. Each input pin (INP, INM) must swing symmetrically between (VCM +
0.475 V) and (VCM – 0.475 V), resulting in a 1.9-VPP (default) differential input swing. The input sampling circuit
has a 3-dB bandwidth that extends up to 1.2 GHz. An equivalent analog input network diagram is shown in
Figure 57.
0.77 W
1 W
3.3 W
2 nH
0.6 W
150 fF
200 fF
3 pF
375 fF
375 fF
375 fF
375 fF
INP
40 W
500 fF
150 fF
0.77 W
1 W
3.3 W
600 W
150 fF
200 fF
3 pF
VCM
40 W
600 W
0.77 W
1 W
3.3 W
150 fF
200 fF
3 pF
2 nH
0.6 W
INM
40 W
500 fF
150 fF
0.77 W
1 W
3.3 W
150 fF
200 fF
3 pF
40 W
TI Device
Copyright © 2016, Texas Instruments Incorporated
Figure 57. Analog Input Network
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Feature Description (continued)
The input bandwidth shown in Figure 58 is measured with respect to a 50-Ω differential input termination at the
ADC input pins.
0
-3
-6
-9
-12
-15
-18
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Input Frequency (MHz)
D056
Figure 58. Transfer Function versus Frequency
8.3.2 DDC Block
The ADS54J20 has an optional digital down-converter (DDC) block that can be enabled via an SPI register write.
Each ADC channel is followed by a DDC block consisting of three different decimate-by-2 and decimate-by-4
finite impulse response (FIR) half-band filter options. The different decimation filter options can be selected via
SPI programming.
Figure 59 shows the signal processing done inside the DDC block of the ADS54J20.
Default 12-Bit Data (At 1.0 GSPS)
Decimate-by-2 Data (At 500 MSPS)
LPF
BPF
2
4
Decimate-by-4 Data (At 250 MSPS)
Interleaving
Engine,
Digital
Features
1.0 GSPS
Data, x(n)
Ch X
To JESD
Encoder
4
LPF
Decimate-by-4, I-Data (At 250 MSPS)
cos(2 n Πfmix / fS)(1)
sin(2 n Πfmix / fS)(1)
Decimate-by-4 Q-Data (At 250 MSPS)
4
LPF
Mode Selection Using
DECFIL MODE[3:0] Register Bits
Copyright © 2016, Texas Instruments Incorporated
(1) In IQ decimate-by-4 mode, the mixer frequency is fixed at fmix = fS / 4. For fS = 1.0 GSPS and fmix = 250 MHz.
Figure 59. DDC Block
26
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Feature Description (continued)
8.3.2.1 Decimate-by-2 Filter
This decimation filter has 41 taps. The stop-band attenuation is approximately 90 dB and the pass-band flatness
is ±0.05 dB. Table 1 shows corner frequencies for the low-pass and high-pass filter options.
Table 1. Corner Frequencies for the Decimate-by-2 Filter
CORNERS (dB)
LOW PASS
0.202 × fS
0.210 × fS
0.215 × fS
0.227 × fS
HIGH PASS
0.298 × fS
0.290 × fS
0.285 × fS
0.273 × fS
–0.1
–0.5
–1
–3
Figure 60 and Figure 61 show the frequency response of the decimate-by-2 filter from dc to fS / 2.
5
-20
0.5
0
-0.5
-1
-45
-1.5
-2
-70
-95
-2.5
-3
-120
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Frequency Response
0
0.05
0.1
0.15
0.2
0.25
Frequency Response
D013
D014
Figure 60. Decimate-by-2 Filter Response
Figure 61. Decimate-by-2 Filter Response (Zoomed)
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8.3.2.2 Decimate-by-4 Filter Using a Digital Mixer
This band-pass decimation filter consists of a digital mixer and three concatenated FIR filters with a combined
latency of approximately 28 output clock cycles. The alias-band attenuation is approximately 55 dB and the pass-
band flatness is ±0.1 dB. By default after reset, the band-pass filter is centered at fS / 16. Using the SPI, the
center frequency can be programmed at N × fS / 16 (where N = 1, 3, 5, or 7). Table 2 shows corner frequencies
for two extreme options.
Table 2. Corner frequencies for the Decimate-by-4 Filter
CORNER FREQUENCY AT LOWER SIDE
(Center Frequency fS / 16)
CORNER FREQUENCY AT HIGHER SIDE
(Center Frequency fS / 16)
CORNERS (dB)
–0.1
–0.5
–1
0.011 × fS
0.010 × fS
0.008 × fS
0.006 × fS
0.114 × fS
0.116 × fS
0.117 × fS
0.120 × fS
–3
Figure 62 and Figure 63 show the frequency response of the decimate-by-4 filter for center frequencies fS / 16
and 3 × fS / 16 (N = 1 and N = 3, respectively).
10
0
0.2
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Frequency Response
0
0.05
0.1
0.15
0.2
0.25
Frequency Response
D015
D016
Figure 62. Decimate-by-4 Filter Response
Figure 63. Decimate-by-4 Filter Response (Zoomed)
8.3.2.3 Decimate-by-4 Filter with IQ Outputs
In this configuration, the DDC block includes a fixed digital fS / 4 mixer. Thus, the IQ pass band is approximately
±0.11 fS, centered at fS / 4. This decimation filter has 41 taps with a latency of approximately ten output clock
cycles. The stop-band attenuation is approximately 90 dB and the pass-band flatness is ±0.05 dB. Table 3 shows
the corner frequencies for a low-pass, decimate-by-4 IQ filter.
Table 3. Corner Frequencies for a Decimate-by-4 IQ Output Filter
CORNERS (dB)
LOW PASS
0.107 × fS
0.112 × fS
0.115 × fS
0.120 × fS
–0.1
–0.5
–1
–3
28
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Figure 64 and Figure 65 show the frequency response of a decimate-by-4 IQ output filter from dc to fS / 2.
5
-20
0.5
0
-0.5
-1
-45
-1.5
-2
-70
-95
-2.5
-3
-120
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Frequency Response
0
0.025
0.05
0.075
0.1
0.125
D012
Frequency Response
D011
Figure 64. Decimate-by-4 IQ Output Filter Response
Figure 65. Decimate-by-4 IQ Output Filter Response
(Zoomed)
8.3.3 SYSREF Signal
The SYSREF signal is a periodic signal that is sampled by the ADS54J20 device clock and used to align the
boundary of the local multiframe clock inside the data converter. SYSREF is required to be a sub-harmonic of the
local multiframe clock (LMFC) internal timing. To meet this requirement, the timing of SYSREF is dependent on
the device clock frequency and the LMFC frequency, as determined by the selected DDC decimation and frames
per multiframe settings. The SYSREF signal is recommended to be a low-frequency signal in the range of 1 MHz
to 5 MHz to reduce coupling to the signal path both on the printed circuit board (PCB) as well as internal to the
device.
The external SYSREF signal must be a sub-harmonic of the internal LMFC clock, as shown in Equation 1 and
Table 4.
SYSREF = LMFC / 2N
where
•
N = 0, 1, 2, and so forth
(1)
Table 4. LMFSC Clock Frequency
LMFS CONFIGURATION
DECIMATION
LMFC CLOCK(1)(2)
fS / K
4211
4244
8224
4222
2242
2221
2441
4421
1241
—
—
(fS / 4) / K
(fS / 4) / K
(fS / 4) / K
(fS / 4) / K
(fS / 4) / K
(fS / 4) / K
(fS / 4) / K
(fS / 4) / K
—
2X
2X
4X
4X (IQ)
4X (IQ)
4X
(1) K = Number of frames per multiframe (JESD digital page 6900h, address 06h, bits 4-0).
(2) fS = sampling (device) clock frequency.
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For example, if LMFS = 8224, the default value of K is 8 + 1 = 9 (the actual value for K = the value set in the SPI
register + 1). If the device clock frequency is fS = 1.0 GSPS, then the local multiframe clock frequency becomes
(1000 / 4) / 9 = 27.778 MHz. The SYSREF signal frequency can be chosen as LMFC frequency / 8 =
3.47222 MHz.
8.3.3.1 SYSREF Not Present (Subclass 0, 2)
A SYSREF pulse is required by the ADS54J20 to reset internal counters. If SYSREF is not present, as can be
the case in subclass 0 or 2, this pulse can be done by doing the following register writes shown in Table 5.
Table 5. Internally Pulsing SYSREF Twice Using Register Writes
ADDRESS (Hex)
0-011h
DATA (Hex)
80h
COMMENT
Set the master page
Enable manual SYSREF
Set SYSREF high
Set SYSREF low
0-054h
80h
0-053h
01h
0-053h
00h
0-053h
01h
Set SYSREF high
Set SYSREF low
0-053h
00h
30
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8.3.4 Overrange Indication
The ADS54J20 provides a fast overrange indication that can be presented in the digital output data stream via
SPI configuration. Alternatively, if not used, the SDOUT (pin 11) and PDN (pin 50) pins can be configured via the
SPI to output the fast OVR indicator.
The JESD 8b, 10b encoder receives 16-bit data that are formed by 12-bit ADC data padded with four 0s as
LSBs. When the FOVR indication is embedded in the output data stream, the LSB of the 16-bit data stream
going to the 8b, 10b encoder is replaced, as shown in Figure 66.
16-Bit Data Output (12-Bit ADC Data Padded with Four 0s)
D0,
OVR
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
16-Bit Data Going to 8b, 10b Encoder
Figure 66. Overrange Indication in a Data Stream
8.3.4.1 Fast OVR
The fast OVR is triggered if the input voltage exceeds the programmable overrange threshold and is presented
after only 18 clock cycles + tPD (tPD of the gates and buffers is approximately 4 ns), thus enabling a quicker
reaction to an overrange event.
The input voltage level that the overload is detected at is referred to as the threshold. The threshold is
programmable using the FOVR THRESHOLD bits, as shown in Figure 67. The FOVR is triggered 18 clock cycles
+ tPD (tPD of the gates and buffers is approximately 4 ns) after the overload condition occurs.
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
0
32
64
96
128
160
192
224
255
Threshold Decimal Value
D055
Figure 67. Programming Fast OVR Thresholds
The input voltage level that the fast OVR is triggered at is defined by Equation 2:
Full-Scale × [Decimal Value of the FOVR Threshold Bits] / 255)
(2)
(3)
The default threshold is E3h (227d), corresponding to a threshold of –1 dBFS.
In terms of full-scale input, the fast OVR threshold can be calculated as Equation 3:
20log (FOVR Threshold / 255)
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8.3.5 Power-Down Mode
The ADS54J20 provides a highly-configurable power-down mode. Power-down can be enabled using the PDN
pin or SPI register writes.
A power-down mask can be configured that allows a trade-off between wake-up time and power consumption in
power-down mode. Two independent power-down masks can be configured: MASK 1 and MASK 2, as shown in
Table 6. See the master page registers in Table 15 for further details.
Table 6. Register Addresses for Power-Down Modes
REGISTER
ADDRESS
REGISTER DATA
COMMENT
A[7:0] (Hex)
MASTER PAGE (80h)
20
7
6
5
4
3
2
1
0
PDN ADC CHA
PDN BUFFER CHB
PDN ADC CHA
PDN BUFFER CHB
GLOBAL OVERRIDE
PDN ADC CHB
MASK 1
21
23
24
PDN BUFFER CHA
PDN BUFFER CHA
0
0
0
0
PDN ADC CHB
MASK 2
CONFIG
0
0
0
0
0
0
0
0
PDN MASK
26
0
PDN
PDN PIN
SEL
MASK
SYSREF
53
55
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PDN MASK
To save power, the device can be put in complete power-down by using the GLOBAL PDN register bit. However,
when JESD is required to remain active when putting the device in power-down, the ADC and analog buffer can
be powered down by using the PDN ADC CHx and PDN BUFFER CHx register bits after enabling the PDN
MASK register bit. The PDN MASK SEL register bit can be used to select between MASK 1 or MASK 2. Table 7
shows the power consumption for different combinations of the GLOBAL PDN, PDN ADC CHx, and PDN BUFF
CHx register bits.
Table 7. Power Consumption in Different Power-Down Settings
TOTAL
IAVDD3V
(mA)
IAVDD
(mA)
IDVDD
(mA)
IIOVDD
(mA)
POWER
(W)
REGISTER BIT
Default
COMMENT
After reset, with a full-scale input signal to both
channels
247
3
260
6
137
23
382
192
1.94
0.28
GBL PDN = 1
The device is in a complete power-down state
GBL PDN = 0,
PDN ADC CHx = 1
(x = A or B)
The ADC of one channel is powered down
206
195
166
258
97
367
381
1.54
1.78
GBL PDN = 0,
PDN BUFF CHx = 1
(x = A or B)
The input buffer of one channel is powered down
137
GBL PDN = 0,
PDN ADC CHx = 1,
PDN BUFF CHx = 1
(x = A or B)
The ADC and input buffer of one channel are
powered down
152
55
166
70
97
56
363
356
1.37
0.81
GBL PDN = 0,
PDN ADC CHx = 1,
PDN BUFF CHx = 1
(x = A and B)
The ADC and input buffer of both channels are
powered down
32
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8.4 Device Functional Modes
8.4.1 Device Configuration
The ADS54J20 can be configured by using a serial programming interface, as described in the Serial Interface
section. In addition, the device has one dedicated parallel pin (PDN) for controlling the power-down mode.
The ADS54J20 supports a 24-bit (16-bit address, 8-bit data) SPI operation and uses paging (see the Register
Maps section) to access all register bits.
8.4.1.1 Serial Interface
The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock), and SDIN (serial interface data) pins, as shown in Figure 68. SPI
bits in Figure 68 are explained in Table 8. Serially shifting bits into the device is enabled when SEN is low. Serial
data on SDIN are latched at every SCLK rising edge when SEN is active (low). The interface can function with
SCLK frequencies from 2 MHz down to very low speeds (of a few Hertz) and also with a non-50% SCLK duty
cycle.
Register Address[11:0]
Register Data[7:0]
SDIN
R/W
M
P
CH
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
tDH
D0
tSCLK
tDSU
SCLK
SEN
tSLOADS
tSLOADH
RESET
Figure 68. SPI Timing Diagram
Table 8. SPI Timing Diagram Legend
SPI BITS
DESCRIPTION
BIT SETTINGS
0 = SPI write
1 = SPI read back
R/W
Read/write bit
0 = Analog SPI bank (master and ADC pages)
1 = JESD SPI bank (main digital, JESD analog, and
JESD digital pages)
M
SPI bank access
JESD page selection bit
0 = Page access
1 = Register access
P
0 = Channel A
1 = Channel B
By default, both channels are being addressed.
SPI access for a specific channel of the JESD SPI
bank
CH
A[11:0]
D[7:0]
SPI address bits
SPI data bits
—
—
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Table 9 shows the timing requirements for the serial interface signals in Figure 68.
Table 9. SPI Timing Requirements
MIN
TYP
MAX
UNIT
MHz
ns
fSCLK
tSLOADS
tSLOADH
tDSU
SCLK frequency (equal to 1 / tSCLK
SEN to SCLK setup time
SCLK to SEN hold time
SDIN setup time
)
> dc
100
100
100
100
2
ns
ns
tDH
SDIN hold time
ns
8.4.1.2 Serial Register Write: Analog Bank
The analog SPI bank contains two pages (the master and ADC pages). The internal register of the ADS54J20
analog SPI bank can be programmed by:
1. Driving the SEN pin low.
2. Initiating a serial interface cycle specifying the page address of the register whose content must be written.
–
–
Master page: write address 0011h with 80h.
ADC page: write address 0011h with 0Fh.
3. Writing the register content as shown in Figure 69. When a page is selected, multiple writes into the same
page can be done.
Register Address[11:0]
Register Data[7:0]
0
0
0
0
SDIN
SCLK
R/W
M
P
CH A11 A10
A9
A8
A7 A6 A5 A4
A3
A2
A1
A0
D7
D6
D5 D4 D3 D2
D1
D0
SEN
RESET
Figure 69. Serial Register Write Timing Diagram
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8.4.1.3 Serial Register Readout: Analog Bank
The content from one of the two analog banks can be read out by:
1. Driving the SEN pin low.
2. Selecting the page address of the register whose content must be read.
–
–
Master page: write address 0011h with 80h.
ADC page: write address 0011h with 0Fh.
3. Setting the R/W bit to 1 and writing the address to be read back.
4. Reading back the register content on the SDOUT pin, as shown in Figure 70. When a page is selected,
multiple read backs from the same page can be done.
Register Address[11:0]
Register Data[7:0] = XX
1
0
0
0
SDIN
SCLK
R/W
M
P
CH
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SEN
RESET
SDOUT
D7
D6
D5
D4
D3
D2
D1
D0
SDOUT[7:0]
Figure 70. Serial Register Read Timing Diagram
8.4.1.4 JESD Bank SPI Page Selection
The JESD SPI bank contains three pages (main digital, JESD digital, and JESD analog pages). The individual
pages can be selected by:
1. Driving the SEN pin low.
2. Setting the M bit to 1 and specifying the page with two register writes. Note that the P bit must be set to 0, as
shown in Figure 71.
–
–
Write address 4003h with 00h (LSB byte of the page address).
Write address 4004h with the MSB byte of the page address.
–
–
–
For the main digital page: write address 4004h with 68h.
For the JESD digital page: write address 4004h with 69h.
For the JESD analog page: write address 4004h with 6Ah.
Register Address[11:0]
Register Data[7:0]
D5 D4 D3 D2
0
1
0
0
SDIN
R/W
M
P
CH A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D1
D0
SCLK
SEN
RESET
Figure 71. SPI Page Selection
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8.4.1.5 Serial Register Write: JESD Bank
The ADS54J20 is a dual-channel device and the JESD204B portion is configured individually for each channel by
using the CH bit. Note that the P bit must be set to 1 for register writes.
1. Drive the SEN pin low.
2. Select the JESD bank page. Note that the M bit = 1 and the P bit = 0.
–
–
Write address 4003h with 00h.
Write address 4005h with 01h to enable separate control for both channels.
–
–
–
For the main digital page: write address 4004h with 68h.
For the JESD digital page: write address 4004h with 69h.
For the JESD analog page: write address 4004h with 6Ah.
3. Set the M and P bits to 1, select channel A (CH = 0) or channel B (CH = 1), and write the register content as
shown in Figure 72. When a page is selected, multiple writes into the same page can be done.
Register Address[11:0]
Register Data[7:0]
0
1
1
0
SDIN
SCLK
R/W
M
P
CH A11 A10
A9
A8
A7 A6 A5 A4
A3
A2
A1
A0
D7
D6
D5 D4 D3 D2
D1
D0
SEN
RESET
Figure 72. JESD Serial Register Write Timing Diagram
8.4.1.5.1 Individual Channel Programming
By default, register writes are applied to both channels. To enable individual channel writes, write address 4005h
with 01h (default is 00h).
8.4.1.6 Serial Register Readout: JESD Bank
The content from one of the pages of the JESD bank can be read out by:
1. Driving the SEN pin low.
2. Selecting the JESD bank page. Note that the M bit = 1 and the P bit = 0.
–
–
Write address 4003h with 00h.
Write address 4005h with 01h to enable separate control for both channels.
–
–
–
For the main digital page: write address 4004h with 68h.
For the JESD digital page: write address 4004h with 69h.
For the JESD analog page: write address 4004h with 6Ah.
3. Setting the R/W, M, and P bits to 1, selecting channel A or channel B, and writing the address to be read
back.
4. Reading back the register content on the SDOUT pin; see Figure 73. When a page is selected, multiple read
backs from the same page can be done.
36
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Register Address[11:0]
A7 A6 A5 A4
Register Data[7:0] = XX
1
1
1
0
SDIN
SCLK
R/W
M
P
CH A11 A10 A9
A8
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SEN
RESET
SDOUT
D7
D6
D5
D4
D3
D2
D1
D0
SDOUT[7:0]
Figure 73. JESD Serial Register Read Timing Diagram
8.4.2 JESD204B Interface
The ADS54J20 supports device subclass 1 with a maximum output data rate of 6.25 Gbps for each serial
transmitter.
An external SYSREF signal is used to align all internal clock phases and the local multiframe clock to a specific
sampling clock edge, allowing synchronization of multiple devices in a system and minimizing timing and
alignment uncertainty. The SYNC input is used to control the JESD204B SerDes blocks.
Depending on the ADC output data rate, the JESD204B output interface can be operated with either two or four
lanes per single ADC, as shown in Figure 74. The JESD204B setup and configuration of the frame assembly
parameters is controlled via the SPI interface.
SYSREF
SYNC
JESD204B
DA[3:0]
INA
INB
JESD204B
JESD204B
JESD204B
DB[3:0]
Sample Clock
Figure 74. ADS54J20 Block Diagram
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The JESD204B transmitter block shown in Figure 75 consists of the transport layer, the data scrambler, and the
link layer. The transport layer maps the ADC output data into the selected JESD204B frame data format. The link
layer performs the 8b, 10b data encoding as well as the synchronization and initial lane alignment using the
SYNC input signal. Optionally, data from the transport layer can be scrambled.
JESD204B Block
Transport Layer
Link Layer
8b, 10b
Encoding
Frame Data
Mapping
Scrambler
1 + x14 + x15
D[3:0]
Comma Characters,
Initial Lane Alignment
SYNC
Figure 75. JESD204B Transmitter Block
8.4.2.1 JESD204B Initial Lane Alignment (ILA)
The initial lane alignment process is started when the receiving device deasserts the SYNC signal, as shown in
Figure 76. When a logic low is detected on the SYNC input pin, the ADS54J20 starts transmitting comma (K28.5)
characters to establish a code group synchronization.
When synchronization is complete, the receiving device asserts the SYNC signal and the ADS54J20 starts the
initial lane alignment sequence with the next local multiframe clock boundary. The ADS54J20 transmits four
multiframes, each containing K frames (K is SPI programmable). Each of the multiframes contains the frame start
and end symbols and the second multiframe also contains the JESD204 link configuration data.
SYSREF
LMFC Clock
LMFC Boundary
Multi
Frame
SYNC
Transmit Data
xxx
K28.5
Code Group
K28.5
Initial Lane
ILA
ILA
DATA
DATA
Data Transmission
Synchronization
Alignment
Figure 76. Lane Alignment Sequence
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8.4.2.2 JESD204B Test Patterns
There are three different test patterns available in the transport layer of the JESD204B interface. The ADS54J20
supports a clock output, encoded, and a PRBS (215 – 1) pattern. These test patterns can be enabled via an SPI
register write and are located in the JESD digital page of the JESD bank.
8.4.2.3 JESD204B Frame
The JESD204B standard defines the following parameters:
•
•
•
•
L is the number of lanes per link.
M is the number of converters per device.
F is the number of octets per frame clock period, per lane.
S is the number of samples per frame per converter.
8.4.2.4 JESD204B Frame
Table 10 lists the available JESD204B formats and valid ranges for the ADS54J20 when the decimation filter is
not used. The ranges are limited by the SerDes lane rate and the maximum ADC sample frequency.
NOTE
The 16-bit data going to the JESD 8b, 10b encoder are formed by padding four 0s as
LSBs into the 12-bit ADC data.
Table 10. Default Interface Rates
MINIMUM RATES
MAXIMUM RATES
L
M
F
S
DECIMATION
SAMPLING
RATE (MSPS)
SERDES BIT
RATE (Gbps)
SAMPLING
RATE (MSPS)
SERDES BIT
RATE (Gbps)
4
4
8
2
2
2
1
4
2
1
4
4
Not used
Not used
Not used
250
250
500
2.5
2.5
2.5
1000
10.0
10.0
5.0
1000
1000
NOTE
In the LMFS = 8224 row of Table 11, the sample order on the lanes is DA2, DA3, DA1,
and DA0 for channel A. Similarly for channel B, the sample order on the lanes is DB2,
DB3, DB1, and DB0.
The detailed frame assembly is shown in Table 11.
Table 11. Default Frame Assembly(1)
OUTPUT
LANE
LMFS = 4211
LMFS = 4244
LMFS = 8224
A3[11:4]
DA0
DA1
DA2
DA3
DB0
DB1
DB2
DB3
A3[3:0], 0000
A2[3:0], 0000
A0[3:0], 0000
A1[3:0], 0000
B3[3:0], 0000
B2[3:0], 0000
B0[3:0], 0000
B1[3:0], 0000
A0[3:0], 0000
A0[11:4]
A2[11:4]
A0[11:4]
A2[3:0], 0000
A3[11:4]
A1[11:4]
A3[3:0], 0000
A1[3:0], 0000
A2[11:4]
A0[11:4]
A1[11:4]
B3[11:4]
B2[11:4]
B0[11:4]
B1[11:4]
A0[3:0], 0000
B0[3:0], 0000
B0[11:4]
B2[11:4]
B0[11:4]
B2[3:0], 0000
B0[3:0], 0000
B3[11:4]
B1[11:4]
B3[3:0], 0000
B1[3:0], 0000
(1) Blue shading indicates channel A and yellow shading indicates channel B.
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8.4.2.5 JESD204B Frame Assembly with Decimation
Table 12 lists the available JESD204B formats and valid ranges for the ADS54J20 when enabling the decimation
filter. The ranges are limited by the SerDes lane rate (2.5 Gbps to 10.0 Gbps) and the ADC sample frequency
(300 MSPS to 1000 MSPS).
Table 12. Interface Rates with Decimation Filter
MINIMUM RATES
MAXIMUM RATES
DEVICE
CLOCK
FREQUENCY
(MSPS)
DEVICE
CLOCK
FREQUENCY
(MSPS)
OUTPUT
SAMPLE
RATE (MSPS)
OUTPUT
SAMPLE
RATE (MSPS)
L
M
F
S
DECIMATION
SERDES BIT
RATE (Gbps)
SERDES BIT
RATE (Gbps)
4
4
2
2
2
1
4
2
2
2
4
2
2
2
4
2
4
4
1
2
2
1
1
1
4X (IQ)
2X
500
500
300
500
300
300
125
250
150
125
75
2.5
2.5
3
1000
1000
1000
1000
1000
1000
250
500
500
250
250
250
5
5
2X
10
5
4X
2.5
3
4X (IQ)
4X
10
10
75
3
Table 13 lists the detailed frame assembly with different decimation options.
Table 13. Frame Assembly with Decimation Filter(1)
OUTPUT
LANE
LMFS = 4222, 2X
DECIMATION
LMFS = 2242,
2X DECIMATION
LMFS = 2221, 4X
DECIMATION
LMFS = 2441,
4X DECIMATION (IQ)
LMFS = 4421, 4X
DECIMATION (IQ)
LMFS = 1241,
4X DECIMATION
A1
AQ0
AQ0
A1
DA0
DA1
[3:0],
[11:4]
0000
[3:0],
[11:4]
0000
A0
A0
A1
[3:0],
0000
A0
AI0
AQ0
[3:0],
0000
AI0
AI0
A0
B0
[3:0],
0000
A0
A0
[11:4]
A1
A0
AI0
[11:4]
AQ0
A0
[11:4]
B0
[3:0],
[11:4]
0000
[3:0],
[11:4]
0000
[3:0],
[11:4]
0000
[3:0],
[11:4]
0000
[3:0],
[3:0],
[11:4]
0000
[11:4]
0000
DA2
DA3
B1
BQ0
BQ0
B1
DB0
DB1
[3:0],
[11:4]
0000
[3:0],
[11:4]
0000
B0
B0
B1
[3:0],
0000
B0
BI0
BQ0
[3:0],
0000
BI0
BI0
B0
B0
[11:4]
B1
B0
BI0
[11:4]
BQ0
[3:0],
[11:4]
0000
[3:0],
[11:4]
0000
[3:0],
[11:4]
0000
[3:0],
[11:4]
0000
[3:0],
[11:4]
0000
DB2
DB3
(1) Blue shading indicates channel A and yellow shading indicates channel B.
40
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Appropriate register bits must be programmed to enable different options when the decimation filter is enabled. Table 14 summarizes all the decimation
filter options available in the DDC block, the corresponding JESD link parameters (L, M, F, and S), and the register bits required to be programmed for
each option.
Table 14. Program Summary of DDC Modes and JESD Link Configuration(1)(2)
LMFS OPTIONS
DDC MODES PROGRAMMING
JESD LINK (LMFS) PROGRAMMING
DECIMATION
OPTIONS
DEC MODE EN,
JESD PLL
MODE(7)
DA_BUS_
DB_BUS_
BUS_REORDER BUS_REORDER
L
M
F
S
DECFIL MODE[3:0](4)
JESD FILTER(5)
JESD MODE(6)
LANE SHARE(8)
DECFIL EN(3)
REORDER(9)
REORDER(10)
EN1(11)
EN2(12)
4
4
2
2
1
4
1
4
No decimation
No decimation
00
00
00
00
000
000
100
010
10
10
0
0
00h
00h
00h
00h
0
0
0
0
No decimation
(Default after
reset)
8
2
2
4
00
00
000
001
00
0
00h
00h
0
0
4
4
2
4
2
2
2
2
4
1
2
2
4X (IQ)
2X
11
11
11
0011 (LPF with fS / 4 mixer)
0010 (LPF) or 0110 (HPF)
0010 (LPF) or 0110 (HPF)
111
110
110
001
001
010
00
00
10
0
0
0
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
1
1
1
1
1
1
2X
0000, 0100, 1000, or 1100
(all BPFs with different
center frequencies).
2
2
1
2
4
2
2
4
4
1
1
1
4X
4X (IQ)
4X
11
11
11
100
111
100
001
010
010
00
10
10
0
0
1
0Ah
0Ah
0Ah
0Ah
0Ah
0Ah
1
1
1
1
1
1
0011 (LPF with an fS / 4
mixer)
0000, 0100, 1000, or 1100
(all BPFs with different
center frequencies)
(1) Keeping the same LMFS settings for both channels is recommended.
(2) The PULSE RESET register bit must be pulsed after the registers in the main digital page are programmed.
(3) The DEC MODE EN and DECFIL EN register bits are located in the main digital page, register 04Dh (bit 3) and register 041h (bit 4).
(4) The DECFIL MODE[3:0] register bits are located in the main digital page, register 041h (bits 5 and 2-0).
(5) The JESD FILTER register bits are located in the JESD digital page, register 001h (bits 5-3).
(6) The JESD MODE register bits are located in the JESD digital page, register 001h (bits 2-0).
(7) The JESD PLL MODE register bits are located in the JESD analog page, register 016h (bits 1-0).
(8) The LANE SHARE register bit is located in the JESD digital page, register 016h (bit 4).
(9) The DA_BUS_REORDER register bits are located in the JESD digital page, register 031h (bits 7-0).
(10) The DB_BUS_REORDER register bits are located in the JESD digital page, register 032h (bits 7-0).
(11) The BUS_REORDER EN1 register bit is located in the main digital page, register 052h (bit 7).
(12) The BUS_REORDER EN2 register bit is located in the main digital page, register 072h (bit 3).
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8.4.2.5.1 JESD Transmitter Interface
Each of the 6.25-Gbps SerDes JESD transmitter outputs require ac-coupling between the transmitter and
receiver. The differential pair must be terminated with 100-Ω resistors as close to the receiving device as
possible to avoid unwanted reflections and signal degradation, as shown in Figure 77.
0.1 mF
DA[3:0]P,
DB[3:0]P
Rt = ZO
Transmission Line, Zo
VCM
Receiver
Rt = ZO
DA[3:0]M,
DB[3:0]M
0.1 mF
Figure 77. Output Connection to Receiver
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8.4.2.5.2 Eye Diagrams
Figure 78 to Figure 81 show the serial output eye diagrams of the ADS54J20 at 5.0 Gbps and 10 Gbps with
default and increased output voltage swing against the JESD204B mask.
Figure 79. Eye Diagram at 5-Gbps Bit Rate with
Increased Output Swing
Figure 78. Eye Diagram at 5-Gbps Bit Rate with
Default Output Swing
Figure 81. Eye Diagram at 10-Gbps Bit Rate with
Increased Output Swing
Figure 80. Eye Diagram at 10-Gbps Bit Rate with
Default Output Swing
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8.5 Register Maps
Figure 82 shows a conceptual diagram of the serial registers.
Initiate an SPI Cycle
R/W, M, P, CH, Bits Decoder
M = 0
M = 1
Analog Bank
JESD Bank
General Register
General Register
(Address 005h,
Keep M = 1, P = 0)
JESD Bank Page Selection
(Address 003h and Address 004h,
Keep M = 1, P = 0)
Unused Registers
(Address 01h, Address 02h.
Keep M = 1, P = 0)
Analog Bank Page Selection
(Address 00h,
(Address 011h, Keep M = 0, P = 0)
Keep M = 0, P = 0)
Value 80h
Addr 5Fh
Value 0Fh
Value 6800h
Value 6900h
Value 6A00h
Addr 0h
Addr 20h
Addr 0h
Addr 12h
Main
Digital Page
JESD
ADC Page
(Fast OVR)
JESD
Digital Page
Master Page
(PDN, OVR,
DC Coupling)
Analog Page
(PLL Configuration,
Output Swing,
(Nyquist Zone,
Gain,
OVR, Filter)
Keep
M = 0, P = 0
(JESD
Configuration)
Pre-Emphasis)
Keep
M = 0, P = 0
Keep M = 1,
P = 1
Keep M = 1,
P = 1
Keep M = 1,
P = 1
Addr F7h
Addr 59h
Addr 32h
Addr 1Bh
Figure 82. Serial Interface Registers
44
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8.5.1 Detailed Register Information
The ADS54J20 contains two main SPI banks. The analog SPI bank provides access to the ADC analog blocks
and the digital SPI bank controls the interleaving engine and anything related to the JESD204B serial interface.
The analog SPI bank is divided into two pages (master and ADC) and the digital SPI bank is divided into three
pages (main digital, JESD digital, and JESD analog). Table 15 lists a register map for the ADS54J20.
Table 15. Register Map
REGISTER
ADDRESS
REGISTER DATA
A[11:0] (Hex)
7
6
5
4
3
2
1
0
GENERAL REGISTERS
0
3
4
RESET
0
0
0
0
0
0
RESET
JESD BANK PAGE SEL[7:0]
JESD BANK PAGE SEL[15:8]
DISABLE
BROADCAST
5
0
0
0
0
0
0
0
11
ANALOG BANK PAGE SEL
MASTER PAGE (80h)
20
21
23
24
PDN ADC CHA
PDN ADC CHA
PDN ADC CHB
PDN ADC CHB
PDN BUFFER CHB
PDN BUFFER CHB
PDN BUFFER CHA
PDN BUFFER CHA
0
0
0
0
0
0
0
0
0
0
0
0
OVERRIDE
PDN MASK
26
4F
53
GLOBAL PDN
0
0
0
PDN PIN
SEL
EN INPUT DC
COUPLING
0
0
0
0
0
0
0
0
0
EN SYSREF
DC COUPLING
MASK SYSREF
0
0
SET SYSREF
0
ENABLE
MANUAL
SYSREF
54
0
0
0
0
0
0
55
59
0
0
0
PDN MASK
0
0
0
0
0
0
0
0
0
ALWAYS
WRITE 1
FOVR CHB
ADC PAGE (0Fh)
5F
FOVR THRESHOLD PROG
MAIN DIGITAL PAGE (6800h)
0
0
0
0
0
0
0
0
0
0
0
0
PULSE RESET
FORMAT SEL
DECFIL
MODE[3]
41
DECFIL EN
DECFIL MODE[2:0]
42
43
44
4B
4D
0
0
0
0
0
0
0
0
0
0
0
0
NYQUIST ZONE
0
0
DIGITAL GAIN
0
0
0
FORMAT EN
0
0
0
0
0
0
0
0
0
DEC MODE EN
CTRL
NYQUIST
4E
52
0
0
0
0
0
0
0
0
0
0
0
0
0
BUS_
REORDER
EN1
DIG GAIN EN
BUS_
REORDER
EN2
72
0
0
0
0
0
0
0
0
AB
AD
F7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LSB SEL EN
LSB SELECT
DIG RESET
0
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Table 15. Register Map (continued)
REGISTER
ADDRESS
REGISTER DATA
A[11:0] (Hex)
7
6
5
4
3
2
1
0
JESD DIGITAL PAGE (6900h)
TESTMODE
EN
FLIP ADC
DATA
0
1
2
CTRL K
0
0
LANE ALIGN
FRAME ALIGN
JESD MODE
0
TX LINK DIS
SYNC REG
SYNC REG EN
JESD FILTER
LINK LAYER
RPAT
LMFC MASK
RESET
LINK LAYER TESTMODE
0
0
FORCE LMFC
3
5
LMFC COUNT INIT
0
RELEASE ILANE SEQ
COUNT
SCRAMBLE
EN
0
0
0
0
0
0
6
0
0
1
0
0
0
0
0
0
FRAMES PER MULTI FRAME (K)
7
0
SUBCLASS
0
0
0
0
0
0
16
31
32
LANE SHARE
0
DA_BUS_REORDER[7:0]
DB_BUS_REORDER[7:0]
JESD ANALOG PAGE (6A00h)
12
13
14
15
SEL EMP LANE 1
0
0
0
0
0
0
0
0
SEL EMP LANE 0
SEL EMP LANE 2
SEL EMP LANE 3
16
17
1A
1B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
JESD PLL MODE
PLL RESET
0
0
0
0
0
0
0
0
0
FOVR CHA
0
JESD SWING
FOVR CHA EN
46
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8.5.2 Example Register Writes
This section provides three different example register writes. Table 16 describes a global power-down register
write, Table 17 describes the register writes when the default lane setting (eight active lanes per device) is
changed to four active lanes (LMFS = 4211), and Table 18 describes the register writes for 2X decimation with
four active lanes (LMFS = 4222).
Table 16. Global Power Down
ADDRESS (Hex)
0-011h
DATA (Hex)
80h
COMMENT
Set the master page
0-026h
C0h
Set the global power-down
Table 17. Two Lanes per Channel Mode (LMFS = 4211)
ADDRESS (Hex)
4-004h
DATA (Hex)
69h
COMMENT
Select the JESD digital page
Select the JESD digital page
Select the digital to 40X mode
Select the JESD analog page
Set the SerDes PLL to 40X mode
4-003h
00h
6-001h
02h
4-004h
6Ah
6-016h
02h
Table 18. 2X Decimation (LPF for Both Channels) with Four Active Lanes (LMFS = 4222)
ADDRESS (Hex)
4-004h
DATA (Hex)
68h
COMMENT
Select the main digital page (6800h)
Select the main digital page (6800h)
Set decimate-by-2 (low-pass filter)
Enable decimation filter control
BUS_REORDER EN2
4-003h
00h
6-041h
12h
6-04Dh
6-072h
08h
08h
6-052h
80h
BUS_REORDER EN1
6-000h
01h
Pulse the PULSE RESET bit (so that register writes to the main digital page go into effect).
6-000h
00h
4-004h
69h
Select the JESD digital page (6900h)
4-003h
00h
Select the JESD digital page (6900h)
6-031h
0Ah
Output bus reorder for channel A
6-032h
0Ah
Output bus reorder for channel B
6-001h
31h
Program the JESD MODE and JESD FILTER register bits for LMFS = 4222.
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8.5.3 Register Descriptions
8.5.3.1 General Registers
8.5.3.1.1 Register 0h (address = 0h)
Figure 83. Register 0h
7
6
0
5
0
4
0
3
0
2
0
1
0
0
RESET
W-0h
RESET
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: W = Write only; -n = value after reset
Table 19. Register 0h Field Descriptions
Bit
Field
Type
Reset
Description
7
RESET
W
0h
0 = Normal operation
1 = Internal software reset, clears back to 0
6-1
0
0
W
W
0h
0h
Must write 0
RESET
0 = Normal operation
1 = Internal software reset, clears back to 0
8.5.3.1.2 Register 3h (address = 3h)
Figure 84. Register 3h
7
6
5
4
3
2
1
0
JESD BANK PAGE SEL[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 20. Register 3h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
JESD BANK PAGE SEL[7:0]
R/W
0h
Program these bits to access the desired page in the JESD bank.
6800h = Main digital page selected
6900h = JESD digital page selected
6A00h = JESD analog page selected
8.5.3.1.3 Register 4h (address = 4h)
Figure 85. Register 4h
7
6
5
4
3
2
1
0
JESD BANK PAGE SEL[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 21. Register 4h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
JESD BANK PAGE SEL[15:8]
R/W
0h
Program these bits to access the desired page in the JESD bank.
6800h = Main digital page selected
6900h = JESD digital page selected
6A00h = JESD analog page selected
48
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8.5.3.1.4 Register 5h (address = 5h)
Figure 86. Register 5h
7
0
6
0
5
0
4
3
0
2
1
0
0
0
0
DISABLE BROADCAST
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 22. Register 5h Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
DISABLE BROADCAST
R/W
0h
0 = Normal operation; channel A and B are programmed as a pair
1 = Channel A and B can be individually programmed based on the
CH bit
8.5.3.1.5 Register 11h (address = 11h)
Figure 87. Register 11h
7
6
5
4
3
2
1
0
ANALOG PAGE SELECTION
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 23. Register 11h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
ANALOG BANK PAGE SEL
R/W
0h
Program these bits to access the desired page in the analog bank.
Master page = 80h
ADC page = 0Fh
8.5.3.2 Master Page (080h) Registers
8.5.3.2.1 Register 20h (address = 20h), Master Page (080h)
Figure 88. Register 20h
7
6
5
4
3
2
1
0
PDN ADC CHA
R/W-0h
PDN ADC CHB
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 24. Registers 20h Field Descriptions
Bit
7-4
3-0
Field
Type
R/W
R/W
Reset
0h
Description
PDN ADC CHA
PDN ADC CHB
There are two power-down masks that are controlled via the
PDN mask register bit in address 55h. The power-down mask 1
or mask 2 are selected via register bit 5 in address 26h.
Power-down mask 1: addresses 20h and 21h.
Power-down mask 2: addresses 23h and 24h.
0Fh = Power-down CHB only.
0h
F0h = Power-down CHA only.
FFh = Power-down both.
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8.5.3.2.2 Register 21h (address = 21h), Master Page (080h)
Figure 89. Register 21h
7
6
5
4
3
0
2
0
1
0
0
0
PDN BUFFER CHB
R/W-0h
PDN BUFFER CHA
R/W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 25. Register 21h Field Descriptions
Bit
7-6
5-4
Field
Type
R/W
R/W
Reset
0h
Description
PDN BUFFER CHB
PDN BUFFER CHA
There are two power-down masks that are controlled via the
PDN mask register bit in address 55h. The power-down mask 1
or mask 2 are selected via register address 26h, bit 5.
Power-down mask 1: addresses 20h and 21h.
Power-down mask 2: addresses 23h and 24h.
There are two buffers per channel. One buffer drives two ADC
cores.
0h
PDN BUFFER CHx:
00 = Both buffers of a channel are active.
11 = Both buffers are powered down.
01–10 = Do not use.
3-0
0
W
0h
Must write 0.
8.5.3.2.3 Register 23h (address = 23h), Master Page (080h)
Figure 90. Register 23h
7
6
5
4
3
2
1
0
PDN ADC CHA
R/W-0h
PDN ADC CHB
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 26. Register 23h Field Descriptions
Bit
7-4
3-0
Field
Type
R/W
R/W
Reset
0h
Description
PDN ADC CHA
PDN ADC CHB
There are two power-down masks that are controlled via the
PDN mask register bit in address 55h. The power-down mask 1
or mask 2 are selected via register address 26h, bit 5.
Power-down mask 1: addresses 20h and 21h.
Power-down mask 2: addresses 23h and 24h.
0Fh = Power-down CHB only.
0h
F0h = Power-down CHA only.
FFh = Power-down both.
50
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8.5.3.2.4 Register 24h (address = 24h), Master Page (080h)
Figure 91. Register 24h
7
6
5
4
3
0
2
0
1
0
0
0
PDN BUFFER CHB
R/W-0h
PDN BUFFER CHA
R/W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 27. Register 24h Field Descriptions
Bit
7-6
5-4
Field
Type
R/W
R/W
Reset
0h
Description
PDN BUFFER CHB
PDN BUFFER CHA
There are two power-down masks that are controlled via the
PDN mask register bit in address 55h. The power-down mask 1
or mask 2 are selected via register address 26h, bit 5.
Power-down mask 1: addresses 20h and 21h.
Power-down mask 2: addresses 23h and 24h.
Power-down mask 2: addresses 23h and 24h.
There are two buffers per channel. One buffer drives two ADC
cores.
0h
PDN BUFFER CHx:
00 = Both buffers of a channel are active.
11 = Both buffers are powered down.
01–10 = Do not use.
3-0
0
W
0h
Must write 0.
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8.5.3.2.5 Register 26h (address = 26h), Master Page (080h)
Figure 92. Register 26h
7
6
5
4
0
3
0
2
0
1
0
0
0
OVERRIDE
PDN PIN
PDN MASK
SEL
GLOBAL PDN
R/W-0h
R/W-0h
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 28. Register 26h Field Descriptions
Bit
Field
Type
Reset
Description
7
GLOBAL PDN
R/W
0h
Bit 6 (OVERRIDE PDN PIN) must be set before this bit can be
programmed.
0 = Normal operation
1 = Global power-down via the SPI
6
5
OVERRIDE PDN PIN
R/W
R/W
W
0h
0h
0h
This bit ignores the power-down pin control.
0 = Normal operation
1 = Ignores inputs on the power-down pin
PDN MASK SEL
0
This bit selects power-down mask 1 or mask 2.
0 = Power-down mask 1
1 = Power-down mask 2
4-0
Must write 0
8.5.3.2.6 Register 4Fh (address = 4Fh), Master Page (080h)
Figure 93. Register 4Fh
7
0
6
0
5
0
4
3
2
1
0
0
0
0
0
EN INPUT DC COUPLING
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 29. Register 4Fh Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
EN INPUT DC COUPLING
R/W
0h
This bit enables dc-coupling between the analog inputs and the
driver by changing the internal biasing resistor between the
analog inputs and VCM from 600 Ω to 5 kΩ.
0 = The dc-coupling support is disabled
1 = The dc-coupling support is enabled
52
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8.5.3.2.7 Register 53h (address = 53h), Master Page (080h)
Figure 94. Register 53h
7
0
6
5
0
4
0
3
0
2
0
1
0
MASK
SYSREF
EN SYSREF
DC COUPLING
SET SYSREF
R/W-0h
W-0h
R/W-0h
W-0h
W-0h
W-0h
W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 30. Register 53h Field Descriptions
Bit
7
Field
Type
W
Reset
0h
Description
0
Must write 0
6
MASK SYSREF
R/W
0h
0 = Normal operation
1 = Ignores the SYSREF input
5-2
1
0
W
0h
0h
Must write 0
EN SYSREF DC COUPLING
R/W
This bit enables a higher common-mode voltage input on the
SYSREF signal (up to 1.6 V).
0 = Normal operation
1 = Enables a higher SYSREF common-mode voltage support
0
SET SYSREF
R/W
0h
0 = Set SYSREF low
1 = Set SYSREF high
8.5.3.2.8 Register 54h (address = 54h), Master Page (080h)
Figure 95. Register 54h
7
6
0
5
0
4
3
2
0
1
0
0
0
ENABLE
MANUAL
SYSREF
0
0
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 31. Register 54h Field Descriptions
Bit
7
Field
Type
R/W
W
Reset
0h
Description
ENABLE MANUAL SYSREF
0
This bit enables manual SYSREF
Must write 0
6-0
0h
8.5.3.2.9 Register 55h (address = 55h), Master Page (080h)
Figure 96. Register 55h
7
0
6
0
5
0
4
3
2
0
1
0
0
0
PDN MASK
R/W-0h
0
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 32. Register 55h Field Descriptions
Bit
7-5
4
Field
Type
W
Reset
0h
Description
0
Must write 0
PDN MASK
R/W
0h
This bit enables power-down via a register bit.
0 = Normal operation
1 = Power-down is enabled by powering down the internal
blocks as specified in the selected power-down mask
3-0
0
W
0h
Must write 0
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8.5.3.2.10 Register 59h (address = 59h), Master Page (080h)
Figure 97. Register 59h
7
6
0
5
4
0
3
0
2
0
1
0
0
0
FOVR CHB
W-0h
ALWAYS WRITE 1
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 33. Register 59h Field Descriptions
Bit
Field
Type
Reset
Description
7
FOVR CHB
W
0h
This bit outputs the FOVR signal for channel B on the SDOUT pin.
0 = Normal operation
1 = The FOVR signal is available on the SDOUT pin
6
5
0
W
0h
0h
0h
Must write 0
Must write 1
Must write 0
ALWAYS WRITE 1
0
R/W
W
4-0
8.5.3.3 ADC Page (0Fh) Register
8.5.3.3.1 Register 5F (addresses = 5F), ADC Page (0Fh)
Figure 98. Register 5F
7
6
5
4
3
2
1
0
FOVR THRESHOLD PROG
R/W-E3h
LEGEND: R/W = Read/Write; -n = value after reset
Table 34. Register 5F Field Descriptions
Bit
Field
Type
Reset
Description
7-0
FOVR THRESHOLD PROG
R/W
E3h
Program the fast OVR thresholds together for channel A and B,
as described in the Overrange Indication section.
54
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8.5.3.4 Main Digital Page (6800h) Registers
8.5.3.4.1 Register 0h (address = 0h), Main Digital Page (6800h)
Figure 99. Register 0h
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
PULSE RESET
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 35. Register 0h Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
PULSE RESET
R/W
0h
This bit must be pulsed after power-up or after configuring
registers in the main digital page of the JESD bank. Any register
bits in the main digital page (6800h) take effect only after this bit
is pulsed; see the Start-Up Sequence section for the correct
sequence.
0 = Normal operation
0 → 1 → 0 = This bit is pulsed
8.5.3.4.2 Register 41h (address = 41h), Main Digital Page (6800h)
Figure 100. Register 41h
7
0
6
0
5
4
3
2
1
0
DECFIL MODE[3]
R/W-0h
DECFIL EN
R/W-0h
0
DECFIL MODE[2:0]
R/W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 36. Register 41h Field Descriptions
Bit
7-6
5
Field
Type
W
Reset
0h
Description
0
Must write 0
DECFIL MODE[3]
R/W
0h
This bit selects the decimation filter mode. Table 37 lists the bit settings.
The decimation filter control (DEC MODE EN, register 4Dh, bit 3) and
decimation filter enable (DECFIL EN, register 41h, bit 4) must be enabled.
4
DECFIL EN
R/W
0h
This bit enables the digital decimation filter.
0 = Normal operation, full rate output
1 = Digital decimation enabled
3
0
W
0h
0h
Must write 0
2-0
DECFIL MODE[2:0]
R/W
These bits select the decimation filter mode. Table 37 lists the bit settings.
The decimation filter control (DEC MODE EN, register 4Dh, bit 3) and
decimation filter enable (DECFIL EN, register 41h, bit 4) must be enabled.
Table 37. DECFIL MODE Bit Settings
BITS (5, 2-0)
FILTER MODE
DECIMATION
0000
0100
1000
1100
0010
0110
0011
Band-pass filter centered on 3 × fS / 16
Band-pass filter centered on 5 × fS / 16
4X
4X
Band-pass filter centered on 1 × fS / 16
Band-pass filter centered on 7 × fS / 16
Low-pass filter
4X
4X
2X
High-pass filter
2X
Low-pass filter with fS / 4 mixer
4X (IQ)
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8.5.3.4.3 Register 42h (address = 42h), Main Digital Page (6800h)
Figure 101. Register 42h
7
0
6
0
5
0
4
0
3
0
2
1
0
NYQUIST ZONE
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 38. Register 42h Field Descriptions
Bit
7-3
2-0
Field
Type
W
Reset
0h
Description
0
Must write 0
NYQUIST ZONE
R/W
0h
The Nyquist zone must be selected for proper interleaving
correction. Nyquist refers to the device clock / 2. For a 1.0-
GSPS device clock, the Nyquist frequency is 500 MHz. The
CTRL NYQUIST register bit (register 4Eh, bit 7) must also be
set.
000 = First Nyquist zone (0 MHz to 500 MHz)
001 = Second Nyquist zone (500 MHz to 1000 MHz)
010 = Third Nyquist zone (1000 MHz to 1500 MHz)
All others = Not used
8.5.3.4.4 Register 43h (address = 43h), Main Digital Page (6800h)
Figure 102. Register 43h
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
FORMAT SEL
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 39. Register 43h Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
FORMAT SEL
R/W
0h
This bit changes the output format. Set the FORMAT EN bit to
enable control using this bit.
0 = Twos complement
1 = Offset binary
8.5.3.4.5 Register 44h (address = 44h), Main Digital Page (6800h)
Figure 103. Register 44h
7
0
6
5
4
3
2
1
0
DIGITAL GAIN
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 40. Register 44h Field Descriptions
Bit
7
Field
Type
R/W
R/W
Reset
0h
Description
0
Must write 0
6-0
DIGITAL GAIN
0h
These bits set the digital gain setting. The DIG GAIN EN register
bit (register 52h, bit 0) must be enabled to use these bits.
Gain in dB = 20log (digital gain / 32).
7Fh = 127 equals a digital gain of 9.5 dB.
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8.5.3.4.6 Register 4Bh (address = 4Bh), Main Digital Page (6800h)
Figure 104. Register 4Bh
7
0
6
0
5
4
0
3
0
2
0
1
0
0
0
FORMAT EN
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 41. Register 4Bh Field Descriptions
Bit
7-6
5
Field
Type
W
Reset
0h
Description
0
Must write 0
FORMAT EN
R/W
0h
This bit enables control for data format selection using the FORMAT
SEL register bit.
0 = Default, output is in twos complement format
1 = Output is in offset binary format after the FORMAT SEL bit is set
4-0
0
W
0h
Must write 0
8.5.3.4.7 Register 4Dh (address = 4Dh), Main Digital Page (6800h)
Figure 105. Register 4Dh
7
0
6
0
5
0
4
0
3
2
0
1
0
0
0
DEC MOD EN
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 42. Register 4Dh Field Descriptions
Bit
7-4
3
Field
Type
W
Reset
0h
Description
0
Must write 0
DEC MOD EN
R/W
0h
This bit enables control of the decimation filter mode via the
DECFIL MODE[3:0] register bits.
0 = Default
1 = Decimation mode control is enabled
2-0
0
W
0h
Must write 0
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8.5.3.4.8 Register 4Eh (address = 4Eh), Main Digital Page (6800h)
Figure 106. Register 4Eh
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
CTRL NYQUIST
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 43. Register 4Eh Field Descriptions
Bit
Field
Type
Reset
Description
7
CTRL NYQUIST
R/W
0h
This bit enables selecting the Nyquist zone using register 42h, bits 2-0.
0 = Selection disabled
1 = Selection enabled
6-0
0
W
0h
Must write 0
8.5.3.4.9 Register 52h (address = 52h), Main Digital Page (6800h)
Figure 107. Register 52h
7
6
0
5
0
4
0
3
0
2
0
1
0
0
BUS_REORDER EN1
W-0h
DIG GAIN EN
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 44. Register 52h Field Descriptions
Bit
7
Field
Type
R/W
W
Reset
0h
Description
BUS_REORDER EN1
Must write 1 in DDC mode only.
Must write 0
6-1
0
0
0h
DIG GAIN EN
R/W
0h
This bit enables selecting the digital gain for register 44h.
0 = Digital gain disabled
1 = Digital gain enabled
8.5.3.4.10 Register 72h (address = 72h), Main Digital Page (6800h)
Figure 108. Register 72h
7
0
6
0
5
0
4
0
3
2
0
1
0
0
0
BUS_REORDER EN2
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 45. Register 72h Field Descriptions
Bit
7-4
3
Field
Type
W
Reset
0h
Description
0
Must write 0
BUS_REORDER EN2
0
R/W
W
0h
Must write 1 in DDC mode only.
Must write 0
2-0
0h
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8.5.3.4.11 Register ABh (address = ABh), Main Digital Page (6800h)
Figure 109. Register ABh
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
LSB SEL EN
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 46. Register ABh Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
LSB SEL EN
R/W
0h
This bit enables control for the LSB SELECT register bit.
0 = Default
1 = LSB of the 16-bit data (12-bit ADC data padded with four 0s
as the LSBs) can be programmed as fast OVR using the LSB
SELECT register bit.
8.5.3.4.12 Register ADh (address = ADh), Main Digital Page (6800h)
Figure 110. Register ADh
7
0
6
0
5
0
4
0
3
0
2
0
1
0
LSB SELECT
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 47. Register ADh Field Descriptions
Bit
7-2
1-0
Field
Type
W
Reset
0h
Description
0
Must write 0
LSB SELECT
R/W
0h
These bits enable the output of the FOVR flag instead of the output data
LSB. Ensure that the LSB SEL EN register bit is set to 1.
00 = Output is 16-bit data (12-bit ADC data padded with four 0s as the
LSBs)
11 = The LSB of the 16-bit output data is replaced by the FOVR
information for each channel
8.5.3.4.13 Register F7h (address = F7h), Main Digital Page (6800h)
Figure 111. Register F7h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
DIG RESET
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: W = Write only; -n = value after reset
Table 48. Register F7h Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
DIG RESET
W
0h
This bit is the self-clearing reset for the digital block and does
not include interleaving correction.
0 = Normal operation
1 = Digital reset
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8.5.3.5 JESD Digital Page (6900h) Registers
8.5.3.5.1 Register 0h (address = 0h), JESD Digital Page (6900h)
Figure 112. Register 0h
7
6
0
5
0
4
3
2
1
0
TESTMODE
EN
FLIP ADC
DATA
CTRL K
R/W-0h
LANE ALIGN
R/W-0h
FRAME ALIGN
R/W-0h
TX LINK DIS
R/W-0h
W-0h
W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 49. Register 0h Field Descriptions
Bit
Field
Type
Reset
Description
7
CTRL K
R/W
0h
This bit is the enable bit for a number of frames per multiframe.
0 = Default is five frames per multiframe
1 = Frames per multiframe can be set in register 06h
6-5
4
0
W
0h
0h
Must write 0
TESTMODE EN
R/W
This bit generates the long transport layer test pattern mode, as
per section 5.1.6.3 of the JESD204B specification.
0 = Test mode disabled
1 = Test mode enabled
3
2
FLIP ADC DATA
LANE ALIGN
R/W
R/W
0h
0h
0 = Normal operation
1 = Output data order is reversed: MSB to LSB.
This bit inserts the lane alignment character (K28.3) for the
receiver to align to the lane boundary, as per section 5.3.3.5 of
the JESD204B specification.
0 = Normal operation
1 = Inserts lane alignment characters
1
0
FRAME ALIGN
TX LINK DIS
R/W
R/W
0h
0h
This bit inserts the lane alignment character (K28.7) for the
receiver to align to the lane boundary, as per section 5.3.3.5 of
the JESD204B specification.
0 = Normal operation
1 = Inserts frame alignment characters
This bit disables sending the initial link alignment (ILA) sequence
when SYNC is deasserted.
0 = Normal operation
1 = ILA disabled
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8.5.3.5.2 Register 1h (address = 1h), JESD Digital Page (6900h)
Figure 113. Register 1h
7
6
5
4
3
2
1
0
SYNC REG
R/W-0h
SYNC REG EN
R/W-0h
JESD FILTER
R/W-0h
JESD MODE
R/W-01h
LEGEND: R/W = Read/Write; -n = value after reset
Table 50. Register 1h Field Descriptions
Bit
Field
Type
Reset
Description
7
SYNC REG
R/W
0h
This bit is the register control for the sync request.
0 = Normal operation
1 = ADC output data are replaced with K28.5 characters; the SYNC
REG EN register bit must also be set to 1
6
SYNC REG EN
JESD FILTER
R/W
R/W
0h
0h
This bit enables register control for the sync request.
0 = Use the SYNC pin for sync requests
1 = Use the SYNC REG register bit for sync requests
5-3
These bits and the JESD MODE bits set the correct LMFS
configuration for the JESD interface. The JESD FILTER setting
must match the configuration in the decimation filter page.
000 = Filter bypass mode
See Table 51 for valid combinations for register bits JESD FILTER
along with JESD MODE.
2-0
JESD MODE
R/W
01h
These bits select the number of serial JESD output lanes per ADC.
The JESD PLL MODE register bit located in the JESD analog page
must also be set accordingly.
001 = Default after reset(Eight active lanes)
See Table 51 for valid combinations for register bits JESD FILTER
along with JESD MODE.
Table 51. Valid Combinations for JESD FILTER and JESD MODE Bits
NUMBER OF ACTIVE LANES
PER DEVICE
REGISTER BIT JESD FILTER
REGISTER BIT JESD MODE
DECIMATION FACTOR
000
000
100
010
No decimation
No decimation
Four lanes are active
Four lanes are active
No decimation
(default after reset)
000
001
Eight lanes are active
111
110
110
100
111
100
001
001
010
001
010
010
4X (IQ)
2X
Four lanes are active
Four lanes are active
Two lanes are active
Two lanes are active
Two lanes are active
One lane is active
2X
4X
4X (IQ)
4X
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8.5.3.5.3 Register 2h (address = 2h), JESD Digital Page (6900h)
Figure 114. Register 2h
7
6
5
4
3
2
0
1
0
0
0
LINK LAYER TESTMODE
R/W-0h
LINK LAYER RPAT
R/W-0h
LMFC MASK RESET
R/W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 52. Register 2h Field Descriptions
Bit
Field
Type
Reset
Description
7-5
LINK LAYER TESTMODE
R/W
0h
These bits generate a pattern as per section 5.3.3.8.2 of the
JESD204B document.
000 = Normal ADC data
001 = D21.5 (high-frequency jitter pattern)
010 = K28.5 (mixed-frequency jitter pattern)
011 = Repeat initial lane alignment (generates a K28.5 character
and continuously repeats lane alignment sequences)
100 = 12-octet RPAT jitter pattern
All others = Not used
4
LINK LAYER RPAT
R/W
0h
This bit changes the running disparity in the modified RPAT pattern
test mode (only when the link layer test mode = 100).
0 = Normal operation
1 = Changes disparity
3
LMFC MASK RESET
0
R/W
W
0h
0h
This bit masks the LMFC reset coming to the digital block.
0 = LMFC reset is not masked
1 = Ignore the LMFC reset request
2-0
Must write 0
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8.5.3.5.4 Register 3h (address = 3h), JESD Digital Page (6900h)
Figure 115. Register 3h
7
6
5
4
3
2
1
0
FORCE LMFC COUNT
R/W-0h
LMFC COUNT INIT
R/W-0h
RELEASE ILANE SEQ
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 53. Register 3h Field Descriptions
Bit
Field
Type
Reset
Description
7
FORCE LMFC COUNT
R/W
0h
This bit forces the LMFC count.
0 = Normal operation
1 = Enables using a different starting value for the LMFC counter
6-2
1-0
MASK SYSREF
R/W
R/W
0h
0h
When SYSREF transmits to the digital block, the LMFC count resets to
0 and K28.5 stops transmitting when the LMFC count reaches 31. The
initial value that the LMFC count resets to can be set using LMFC
COUNT INIT. In this manner, the receiver can be synchronized early
because the LANE ALIGNMENT SEQUENCE is received early. The
FORCE LMFC COUNT register bit must be enabled.
RELEASE ILANE SEQ
These bits delay the generation of the lane alignment sequence by 0, 1,
2, or 3 multiframes after the code group synchronization.
00 = 0
01 = 1
10 = 2
11 = 3
8.5.3.5.5 Register 5h (address = 5h), JESD Digital Page (6900h)
Figure 116. Register 5h
7
6
0
5
4
3
2
0
1
0
0
0
SCRAMBLE EN
R/W-Undefined
0
0
0
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 54. Register 5h Field Descriptions
Bit
Field
Type
Reset
Description
7
SCRAMBLE EN
R/W
Undefined This bit is the scramble enable bit in the JESD204B interface.
0 = Scrambling disabled
1 = Scrambling enabled
6-0
0
W
0h
Must write 0
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8.5.3.5.6 Register 6h (address = 6h), JESD Digital Page (6900h)
Figure 117. Register 6h
7
0
6
0
5
0
4
3
2
1
0
FRAMES PER MULTI FRAME (K)
R/W-8h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 55. Register 6h Field Descriptions
Bit
7-5
4-0
Field
Type
W
Reset
0h
Description
0
Must write 0
FRAMES PER MULTI FRAME (K)
R/W
8h
These bits set the number of multiframes.
Actual K is the value in hex + 1 (that is, 0Fh is K = 16).
8.5.3.5.7 Register 7h (address = 7h), JESD Digital Page (6900h)
Figure 118. Register 7h
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
SUBCLASS
R/W-1h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 56. Register 7h Field Descriptions
Bit
7-4
3
Field
Type
W
Reset
0h
Description
0
Must write 0
SUBCLASS
R/W
1h
This bit sets the JESD204B subclass.
000 = Subclass 0 is backward compatible with JESD204A
001 = Subclass 1 deterministic latency using the SYSREF signal
2-0
0
W
0h
Must write 0
8.5.3.5.8 Register 16h (address = 16h), JESD Digital Page (6900h)
Figure 119. Register 16h
7
1
6
0
5
0
4
3
0
2
0
1
0
0
0
LANE SHARE
W-0h
W-1h
W-0h
R/W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 57. Register 16h Field Descriptions
Bit
7
Field
Type
W
Reset
1h
Description
Must write 1
Must write 0
1
6-5
4
0
W
0h
LANE SHARE
R/W
0h
When using decimate-by-4, the data of both channels are output
over one lane (LMFS = 1241).
0 = Normal operation (each channel uses one lane)
1 = Lane sharing is enabled, both channels share one lane
(LMFS = 1241)
3-0
0
W
0h
Must write 0
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8.5.3.5.9 Register 31h (address = 31h), JESD Digital Page (6900h)
Figure 120. Register 31h
7
6
5
4
3
2
1
0
DA_BUS_REORDER[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 58. Register 31h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DA_BUS_REORDER[7:0]
R/W
0h
Use these bits to program output connections between data
streams and output lanes in decimate-by-2 and decimate-by-4
mode. Table 14 lists the supported combinations of these bits.
8.5.3.5.10 Register 32h (address = 32h), JESD Digital Page (6900h)
Figure 121. Register 32h
7
6
5
4
3
2
1
0
DB_BUS_REORDER[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 59. Register 32h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DB_BUS_REORDER[7:0]
R/W
0h
Use these bits to program output connections between data
streams and output lanes in decimate-by-2 and decimate-by-4
mode. Table 14 lists the supported combinations of these bits.
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8.5.3.6 JESD Analog Page (6A00h) Registers
8.5.3.6.1 Registers 12h-5h (addresses = 12h-5h), JESD Analog Page (6A00h)
Figure 122. Register 12h
7
6
5
4
3
2
2
2
2
1
0
0
0
SEL EMP LANE 1
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
W-0h
W-0h
Figure 123. Register 13h
7
6
5
4
3
1
0
0
0
SEL EMP LANE 0
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
W-0h
W-0h
Figure 124. Register 14h
7
6
5
4
3
1
0
0
0
SEL EMP LANE 2
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
W-0h
W-0h
Figure 125. Register 15h
7
6
5
4
3
1
0
0
0
SEL EMP LANE 3
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
W-0h
W-0h
Table 60. Registers 12h-15h Field Descriptions
Bit
Field
Type
Reset
Description
7-2
SEL EMP LANE x
(where x = 1, 0, 2, or 3)
R/W
0h
These bits select the amount of de-emphasis for the JESD
output transmitter. The de-emphasis value in decibels (dB) is
measured as the ratio between the peak value after the signal
transition to the settled value of the voltage in one bit period.
000000 = 0 dB
000001 = –1 dB
000011 = –2 dB
000111 = –4.1 dB
001111 = –6.2 dB
011111 = –8.2 dB
111111 = –11.5 dB
1-0
0
W-0h
0h
Must write 0
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8.5.3.6.2 Register 16h (address = 16h), JESD Analog Page (6A00h)
Figure 126. Register 16h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
JESD PLL MODE
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 61. Register 16h Field Descriptions
Bit
7-2
1-0
Field
Type
W
Reset
0h
Description
0
Must write 0
JESD PLL MODE
R/W
0h
These bits select the JESD PLL multiplication factor and must
match the JESD MODE setting.
00 = 20X mode
01 = Not used
10 = 40X mode
11 = Not used
See Table 14 for a programming summary of the DDC modes
and JESD link configuration.
8.5.3.6.3 Register 17h (address = 17h), JESD Analog Page (6A00h)
Figure 127. Register 17h
7
0
6
5
0
4
0
3
0
2
0
1
0
0
0
PLL RESET
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 62. Register 17h Field Descriptions
Bit
7
Field
Type
W
Reset
0h
Description
0
Must write 0
6
PLL RESET
R/W
0h
Pulse this bit after powering up the device; see Table 65.
0 = Default
0 → 1 → 0 = The PLL RESET bit is pulsed.
5-0
0
W
0h
Must write 0
8.5.3.6.4 Register 1Ah (address = 1Ah), JESD Analog Page (6A00h)
Figure 128. Register 1Ah
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
FOVR CHA
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 63. Register 1Ah Field Descriptions
Bit
7-2
1
Field
Type
W
Reset
0h
Description
0
Must write 0
FOVR CHA
R/W
0h
This bit outputs the FOVR signal for channel A on the PDN pin.
FOVR CHA EN (register 1Bh, bit 3) must be enabled for this bit
to function.
0 = Normal operation
1 = The FOVR signal of channel A is available on the PDN pin
0
0
W
0h
Must write 0
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8.5.3.6.5 Register 1Bh (address = 1Bh), JESD Analog Page (6A00h)
Figure 129. Register 1Bh
7
6
5
4
0
3
2
0
1
0
0
0
JESD SWING
R/W-0h
FOVR CHA EN
R/W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 64. Register 1Bh Field Descriptions
Bit
Field
Type
Reset
Description
7-5
JESD SWING
R/W
0h
These bits select the output amplitude VOD (mVPP) of the JESD
transmitter (for all lanes).
0 = 860 mVPP
1 = 810 mVPP
2 = 770 mVPP
3 = 745 mVPP
4 = 960 mVPP
5 = 930 mVPP
6 = 905 mVPP
7 = 880 mVPP
4
3
0
W
0h
0h
Must write 0
FOVR CHA EN
R/W
This bit enables overwrites of the PDN pin with the FOVR signal
from channel A.
0 = Normal operation
1 = PDN is overwritten
2-0
0
W
0h
Must write 0
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Start-Up Sequence
The steps described in Table 65 are recommended as the power-up sequence with the ADS54J20 in 20X mode
(LMFS = 8224).
68
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Table 65. Initialization Sequence
PAGE BEING
PROGRAMMED
STEP
1
SEQUENCE
Power-up the device
DESCRIPTION
COMMENT
Bring up IOVDD to 1.15 V before applying power to DVDD. Bring up
DVDD to 1.9 V, AVDD to 1.9 V, and AVDD3V to 3.0 V.
See the Power Sequencing and Initialization section for power sequence
—
requirements.
Hardware reset
Apply a hardware reset by pulsing pin 48 (low → high → low).
Register writes are equivalent to a hardware reset.
—
A hardware reset clears all registers to their default values.
Reset registers in the ADC and master pages of the analog bank.
This bit is a self-clearing bit.
Write address 0-000h with 81h.
General register
2
Reset the device
Write address 4-001h with 00h and address 4-002h with 00h.
Write address 4-003h with 00h and address 4-004h with 68h.
Unused page
—
Clear any unwanted content from the unused pages of the JESD bank.
Select the main digital page of the JESD bank.
Use the DIG RESET register bit to reset all pages in the JESD bank.
This bit is a self-clearing bit.
Write address 6-0F7h with 01h for channel A.
Main digital page
(JESD bank)
Write address 6-000h with 01h, then address 6-000h with 00h.
Write address 0-011h with 80h.
Pulse the PULSE RESET register bit for channel A.
Select the master page of the analog bank.
—
3
Performance modes
Master page
(analog bank)
Write address 0-059h with 20h.
Set the ALWAYS WRITE 1 bit.
Default register writes for DDC modes and JESD link configuration (LMFS = 8224).
Write address 4-003h with 00h and address 4-004h with 69h.
Write address 6-000h with 80h.
—
Select the JESD digital page.
Set the CTRL K bit for both channels by programming K according to the
SYSREF signal later on in the sequence.
JESD
digital page
(JESD bank)
See Table 14 for configuring the JESD digital page registers for the desired
LMFS and programming appropriate DDC mode.
JESD link is configured with LMFS = 8224 by default with no decimation.
Write address 4-003h with 00h and address 4-004h with 6Ah.
—
Select the JESD analog page.
Program desired registers for
decimation options and
JESD link configuration
See Table 14 for configuring the JESD analog page registers for the desired
LMFS and programming appropriate DDC mode.
4
JESD link is configured with LMFS = 8224 by default with no decimation.
JESD
analog page
(JESD bank)
Write address 6-017h with 40h.
PLL reset.
Write address 6-017h with 00h.
PLL reset clear.
Write address 4-003h with 00h and address 4-004h with 68h.
—
Select the main digital page.
See Table 14 for configuring the main digital page registers for the desired
LMFS and programming appropriate DDC mode.
JESD link is configured with LMFS = 8224 by default with no decimation.
Write address 6-000h with 01h and address 6-000h with 00h.
Main digital page
(JESD bank)
Pulse the PULSE RESET register bit. All settings programmed in the main
digital page take effect only after this bit is pulsed.
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Table 65. Initialization Sequence (continued)
PAGE BEING
STEP
SEQUENCE
DESCRIPTION
PROGRAMMED
COMMENT
Write address 4-003h with 00h and address 4-004h with 69h.
—
Select the JESD digital page.
Set the value of K and the
SYSREF signal frequency
accordingly
JESD
digital page
(JESD bank)
5
Write address 6-006h with XXh (choose the value of K).
See the SYSREF Signal section to choose the correct frequency for SYSREF.
Pull the SYNCB pin (pin 63) low.
Pull the SYNCB pin high.
Transmit K28.5 characters.
6
JESD lane alignment
—
After the receiver is synchronized, initiate an ILA phase and subsequent
transmissions of ADC data.
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9.1.2 Hardware Reset
Figure 130 and Table 66 show the timing for a hardware reset.
Power Supplies
tPU
RESET
tRST
tWR
SEN
Figure 130. Hardware Reset Timing Diagram
Table 66. Timing Requirements for Figure 130
MIN
TYP
MAX
UNIT
ms
ns
tPU
Power-on delay from power-up to an active high RESET pulse
Reset pulse duration: active high RESET pulse duration
Register write delay from RESET disable to SEN active
1
10
tRST
tWR
100
ns
9.1.3 SNR and Clock Jitter
The signal-to-noise ratio (SNR) of the ADC is limited by three different factors: quantization noise, thermal noise,
and jitter, as shown in Equation 4. The quantization noise is typically not noticeable in pipeline converters and is
74 dBFS for a 12-bit ADC. The thermal noise limits SNR at low input frequencies and the clock jitter sets SNR for
higher input frequencies.
(4)
The SNR limitation resulting from sample clock jitter can be calculated by Equation 5:
(5)
The total clock jitter (TJitter) has two components: the internal aperture jitter (130 fS) is set by the noise of the
clock input buffer and the external clock jitter. TJitter can be calculated by Equation 6:
(6)
External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass
filters at the clock input. A faster clock slew rate also improves the ADC aperture jitter.
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The ADS54J20 has a thermal noise of approximately 71.1 dBFS and an internal aperture jitter of 120 fS. SNR,
depending on the amount of external jitter for different input frequencies, is shown in Figure 131.
71
35 fs
50 fs
100 fs
150 fs
200 fs
69
67
65
63
10
100
Input Frequency (MHz)
500
D057
Figure 131. SNR versus Input Frequency and External Clock Jitter
72
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9.2 Typical Application
The ADS54J20 is designed for wideband receiver applications demanding excellent dynamic range over a large
input frequency range. A typical schematic for an ac-coupled receiver is shown in Figure 132.
DVDD
10 kꢀ
5 W
5 W
50 W
50 W
Driver
0.1 mF
2 pF
0.1 mF
SPI Master
GND
GND
IOVDD GND
0.1 mF
0.1 mF
0.1 mF
10nF
GND
0.1 mF
AVDD3V
AVDD
AVDD
AVDD3V
DVDD
100-W Differential
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
10 nF
DB2P
DB2M
IOVDD
DB1P
DB1M
DGND
DB0P
DB0M
IOVDD
SYNC
DA0M
DA0P
DGND
DA1M
DA1P
IOVDD
DA2M
DA2P
NC
NC
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
IOVDD
10 nF
GND
NC
10 nF
10 nF
VCM
0.1 mF
AGND
AVDD3V
AVDD
AGND
CLKINP
CLKINM
AGND
AVDD
AVDD3V
AGND
GND
0.1 mF
AVDD3V
GND
AVDD
0.1 mF
GND
10 nF
IOVDD
0.1 mF
GND
GND Pad
(Back Side)
GND
0.1 mF
FPGA
Low-Jitter Clock
Generator
AVDD3V
0.1 mF
GND
10 nF
10 nF
GND
SYSREFP
SYSREFM
AVDD
100 W
IOVDD
10 nF
GND
AVDD
AGND
GND
10 nF
10 nF
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
100-W Differential
AVDD3V
DVDD
AVDD
AVDD
AVDD3V
0.1 mF
GND
GND
0.1 mF
IOVDD GND
0.1 mF
GND
5 W
5 W
50 W
50 W
Driver
0.1 mF
0.1 mF
2 pF
GND
Copyright © 2016, Texas Instruments Incorporated
NOTE: GND = AGND and DGND are connected in the PCB layout.
Figure 132. AC-Coupled Receiver
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Typical Application (continued)
9.2.1 Design Requirements
9.2.1.1 Transformer-Coupled Circuits
Typical applications involving transformer-coupled circuits are discussed in this section. Transformers (such as
ADT1-1WT or WBC1-1) can be used up to 300 MHz to achieve good phase and amplitude balances at the ADC
inputs. When designing dc-driving circuits, the ADC input impedance must be considered. Figure 133 and
Figure 134 show the impedance (ZIN = RIN || CIN) across the ADC input pins.
5
4.75
4.5
1.4
1.2
1
4.25
4
0.8
0.6
0.4
0.2
0
3.75
3.5
3.25
3
2.75
2.5
2.25
0
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
Frequency (MHz)
Frequency (MHz)
D103
D102
Figure 133. RIN vs Input Frequency
Figure 134. CIN vs Input Frequency
By using the simple drive circuit of Figure 135, uniform performance can be obtained over a wide frequency
range. The buffers present at the analog inputs of the device help isolate the external drive source from the
switching currents of the sampling circuit.
0.1 ꢁF
T2
CHx_INP
T1
5 ꢀ
0.1 ꢁF
25 ꢀ
0.1 ꢁF
RIN
CIN
25 ꢀ
5 ꢀ
0.1 ꢁF
CHx_INM
1:1
1:1
TI Device
Copyright © 2016, Texas Instruments Incorporated
Figure 135. Input Drive Circuit
9.2.2 Detailed Design Procedure
For optimum performance, the analog inputs must be driven differentially. This architecture improves common-
mode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with each input
pin is recommended to damp out ringing caused by package parasitics, as shown in Figure 135.
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Typical Application (continued)
9.2.3 Application Curves
Figure 136 and Figure 137 show the typical performance at 170 MHz and 230 MHz, respectively.
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
100
200
300
400
500
0
100
200
300
400
500
Input Frequency (MHz)
Input Frequency (MHz)
D003
D004
SNR = 67.8 dBFS, SINAD = 67.7 dBFS,
SNR = 67.4 dBFS, SINAD = 67.2 dBFS,
SFDR = 86 dBc, THD = 81 dBc, IL spur = 88 dBc,
non HD2, HD3 spur = 89 dBc
IL spur = 87 dBc, SFDR = 84 dBc, THD = 82 dBc,
non HD2, HD3 spur = 90 dBc
Figure 136. FFT for 170-MHz Input Signal
Figure 137. FFT for 230-MHz Input Signal
10 Power Supply Recommendations
The device requires a 1.15-V nominal supply for IOVDD, a 1.9-V nominal supply for DVDD, a 1.9-V nominal
supply for AVDD, and a 3.0-V nominal supply for AVDD3V. For detailed information regarding the operating
voltage minimum and maximum specifications of different supplies, see the Recommended Operating Conditions
table.
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10.1 Power Sequencing and Initialization
Figure 138 shows the suggested power-up sequencing for the device. Note that the 1.15-V IOVDD supply must
rise before the 1.9-V DVDD supply. If the 1.9-V DVDD supply rises before the 1.15-V IOVDD supply, then the
internal default register settings may not load properly. The other supplies (the 3-V AVDD3V and the 1.9-V
AVDD), can come up in any order during the power sequence. The power supplies can ramp up at any rate and
there is no hard requirement for the time delay between IOVDD ramp up to DVDD ramp-up (can be in orders of
microseconds but is recommend to be a few milliseconds).
IOVDD = 1.15 V
DVDD = 1.9 V
AVDD = 1.9 V
AVDD = 3 V
Figure 138. Power Sequencing for the ADS54Jxx Family of Devices
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11 Layout
11.1 Layout Guidelines
The device evaluation module (EVM) layout can be used as a reference layout to obtain the best performance. A
layout diagram of the EVM top layer is provided in Figure 139. The ADS54J20EVM User's Guide (SLAU687),
provides a complete layout of the EVM. Some important points to remember during board layout are:
•
•
•
Analog inputs are located on opposite sides of the device pinout to ensure minimum crosstalk on the package
level. To minimize crosstalk onboard, the analog inputs must exit the pinout in opposite directions, as
illustrated in the reference layout of Figure 139 as much as possible.
In the device pinout, the sampling clock is located on a side perpendicular to the analog inputs in order to
minimize coupling between them. This configuration is also maintained on the reference layout of Figure 139
as much as possible.
Keep digital outputs away from the analog inputs. When these digital outputs exit the pinout, the digital output
traces must not be kept parallel to the analog input traces because this configuration can result in coupling
from the digital outputs to the analog inputs and degrade performance. All digital output traces to the receiver
[such as a field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs)] must
be matched in length to avoid skew among outputs.
•
At each power-supply pin (AVDD, DVDD, or AVDDD3V), keep a 0.1-µF decoupling capacitor close to the
device. A separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF
capacitors can be kept close to the supply source.
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11.2 Layout Example
Copyright © 2016, Texas Instruments Incorporated
Figure 139. ADS54J20EVM Layout
78
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12 器件和文档支持
12.1 文档支持
12.1.1 相关文档ꢀ
相关文档如下：
•
•
•
•
•
•
ADS54J40 双通道 14 位 1.0GSPS 模数转换器
ADS54J42 双通道、14 位、625MSPS 模数转换器
ADS54J60 双通道 16 位 1.0GSPS 模数转换器
ADS54J66 具有集成 DDC 的四通道、14 位、500MSPS ADC
ADS54J69 双通道、16 位、500 MSPS 模数转换器
《ADS54J20EVM 用户指南》
12.2 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
12.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS54J20IRMP
ADS54J20IRMPT
ACTIVE
ACTIVE
VQFN
VQFN
RMP
RMP
72
72
168
250
RoHS & Green
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
AZ54J20
AZ54J20
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TRAY
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
ADS54J20IRMP
RMP
VQFNP
72
168
8 X 21
150
315 135.9 7620 14.65
11
11.95
Pack Materials-Page 1
PACKAGE OUTLINE
RMP0072A
VQFN - 0.9 mm max height
SCALE 1.700
VQFN
10.1
9.9
A
B
PIN 1 ID
10.1
9.9
0.9 MAX
0.05
0.00
C
SEATING PLANE
0.08 C
(0.2)
4X (45 X0.42)
19
36
18
37
SYMM
4X
8.5
8.5 0.1
PIN 1 ID
(R0.2)
1
54
0.30
0.18
72X
72
55
68X 0.5
SYMM
0.5
0.3
0.1
C B
A
72X
0.05
C
4221047/B 02/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RMP0072A
VQFN - 0.9 mm max height
VQFN
(
8.5)
SYMM
72X (0.6)
SEE DETAILS
55
72
1
54
72X (0.24)
(0.25) TYP
SYMM
(9.8)
(1.315) TYP
68X (0.5)
(
0.2) TYP
VIA
37
18
19
36
(1.315) TYP
(9.8)
LAND PATTERN EXAMPLE
SCALE:8X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4221047/B 02/2014
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON PCB application report
in literature No. SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
RMP0072A
VQFN - 0.9 mm max height
VQFN
(9.8)
72X (0.6)
(1.315) TYP
72
55
1
54
72X (0.24)
(1.315)
TYP
(0.25) TYP
SYMM
(9.8)
(1.315)
TYP
68X (0.5)
METAL
TYP
37
18
(
0.2) TYP
VIA
19
36
36X ( 1.115)
(1.315) TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
62% PRINTED SOLDER COVERAGE BY AREA
SCALE:8X
4221047/B 02/2014
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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