ADS54J66IRMP_技术文档

ADS54J66

ZHCSEE2B –DECEMBER 2015 –REVISED JANUARY 2023

ADS54J66 具有集成DDC 的四通道、14 位、500MSPS ADC

1 特性

3 说明

• 四通道

• 14 位分辨率

• 最大时钟频率：500MSPS

• 输入带宽(3dB)：900MHz

• 片上抖动

• 具有高阻抗输入的模拟输入缓冲器

• 输出选项：

ADS54J66 是一款低功耗、高带宽、14 位、

500MSPS、四通道电信接收器。ADS54J66 支持

JESD204B 串行接口，每个通道上具有 1 条信道，数

据传输速率高达 10Gbps。经缓冲的模拟输入可在较宽

频率范围内提供统一输入阻抗，并最大程度地降低采样

和保持毛刺脉冲能量。ADS54J66 以超低功耗在宽输

入频率范围内提供出色的无杂散动态范围 (SFDR)。数

字信号处理模块包含复混频器，后接低通滤波器。低通

滤波器具有 2 倍抽取率和 4 倍抽取率两个选项，支持

高达200MHz 的接收器带宽。

– Rx：通过低通滤波器实现2 倍抽取率

和4 倍抽取率选项

– 200MHz 复杂带宽或100MHz 实际带宽支持

– DPD FB：500MSPS

• 1.9V_PP差分满量程输入

• JESD204B 接口：

JESD204B 接口减少了接口线路数，从而实现高系统

集成度。内部锁相环 (PLL) 会将传入的模数转换器

(ADC) 采样时钟加倍，以获得串行化各通道的 14 位数

据时所使用的位时钟。

– 子类1 支持

– 每个ADC 一条信道，速率高达10Gsps

– 专用于通道对的SYNC 引脚

• 支持多芯片同步

• 72 引脚VQFN 封装(10mm × 10mm)

• 主要规格：

封装信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

ADS54J66

VQFN (72)

10.00mm x 10.00mm

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

– 功耗：675mW/ch

– 频谱性能（未抽取）

Digital Block

Interleaving

Correction

2x

• f_IN= 190MHz 中频(IF)（–1dBFS 时）：

INAP,

INAM

14-Bit

ADC

DAP,

DAM

fS

/

4

4x

2x

JESD204B

– SNR：69.5dBFS

– NSD：-153.5dBFS/Hz

Digital Block

Interleaving

Correction

K

x

/

16

INBP,

INBM

14-Bit

ADC

DBP,

DBM

fS / 8

TRIGAB

– SFDR：86dBc（HD2，HD3），

93dBFS（非HD2，HD3）

• f_IN= 370 MHz IF（–3dBFS 时）：

TRIGCD

TRDYAB

TRDYCD

SYSREFP,

SYSREFM

– SNR：68.5dBFS

CLKINP,

CLKINM

PLL

x10, x20

SYNCbAB

SYNCbCD

– NSD：-152.5dBFS/Hz

– SFDR：81dBc（HD2，HD3），

86dBFS（非HD2，HD3）

Digital Block

Interleaving

Correction

INCP,

INCM

14-Bit

ADC

DCP,

DCM

2x

fS / 4

JESD204B

4x

2x

Digital Block

Interleaving

Correction

INDP,

INDM

14-Bit

ADC

DDP,

DDM

K

x fS / 16

fS / 8

2 应用

Configuration

Registers

• 雷达和天线阵列

• 宽带无线和数字转换器

• 电缆CMTS、DOCSIS 3.1 接收器

• 通信测试设备

简化版方框图

• 微波接收器

• 软件定义无线电(SDR)

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBAS745

ADS54J66

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ZHCSEE2B –DECEMBER 2015 –REVISED JANUARY 2023

Table of Contents

7.2 Functional Block Diagram.........................................23

7.3 Feature Description...................................................24

7.4 Device Functional Modes..........................................25

7.5 Programming............................................................ 34

7.6 Register Maps...........................................................44

8 Application Information Disclaimer.............................71

8.1 Application Information............................................. 71

8.2 Typical Application.................................................... 77

8.3 Power Supply Recommendations.............................79

8.4 Layout....................................................................... 80

9 Device and Documentation Support............................81

9.1 接收文档更新通知..................................................... 81

9.2 支持资源....................................................................81

9.3 商标...........................................................................81

9.4 Electrostatic Discharge Caution................................81

9.5 术语表....................................................................... 81

10 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 3

5 Pin Configuration and Functions...................................4

6 Specifications.................................................................. 6

6.1 Absolute Maximum Ratings........................................ 6

6.2 ESD Ratings............................................................... 6

6.3 Recommended Operating Conditions.........................7

6.4 Thermal Information....................................................7

6.5 Electrical Characteristics.............................................8

6.6 AC Performance......................................................... 9

6.7 Digital Characteristics............................................... 11

6.8 Timing Requirements................................................12

6.9 Typical Characteristics: General (DDC Mode-8).......14

6.10 Typical Characteristics: Mode 2..............................21

6.11 Typical Characteristics: Mode 0.............................. 22

7 Detailed Description......................................................23

7.1 Overview...................................................................23

Information.................................................................... 81

2

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ZHCSEE2B –DECEMBER 2015 –REVISED JANUARY 2023

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (December 2015) to Revision B (January 2023)

Page

• Changed rising to falling in the t_{SU_SYSREF}and t_{H_SYSREF}parameter descriptions...........................................12

• Deleted the t_{SU_SYSREF}maximum value........................................................................................................... 12

• Added second table note to Timing Characteristics table.................................................................................12

• Added SYSREF Timing Diagram figure............................................................................................................12

• Deleted One threshold is set per channel pair A, B, and C, D. from Overrange Indication section..................32

• Added note to Overrange Indication section.....................................................................................................32

• Changed FFh to 0Fh in 表7-8 .........................................................................................................................32

• Deleted 5th row (LMFS = 2881) from 表7-13 ..................................................................................................41

• Deleted LMFS = 2881 section from 表7-14 .................................................................................................... 41

• Changed bit 0, register 53, master page (80h) from 0 to SET SYSREF ......................................................... 45

• Added register 54 to master page registers......................................................................................................45

• Removed registers 19h to 20h from JESD Digital Page (6900h)..................................................................... 45

• Added register 17h to JESD Analog Page (6A00h)..........................................................................................45

• Changed 00h26 to 0026h in ADDRESS column and 80h to C0h in DATA column of Example Register Writes

table..................................................................................................................................................................47

• Added 表7-16, deleted legends from Register Descriptions section............................................................... 47

• Changed register description of Register 53h (address = 53h) [reset = 0h], Master Page (80h)..................... 52

• Added Register 54h (address = 54h) [reset = 0h], Master Page (80h).............................................................53

• Deleted the tables and description for registers 0x19-0x20..............................................................................64

• Changed Register 16h Field Descriptions table in Register 16h (address = 16h) [reset = 0h], JESD Analog

Page (6A00h)....................................................................................................................................................69

• Added Register 17h (address = 17h) [reset = 0h], JESD Analog Page (6A00h)..............................................69

• Changed 6Ah to 6A00h in register title and changed description of bits 7-5 in Register 1Bh (address = 1Bh)

[reset = 0h], JESD Analog Page (6A00h)......................................................................................................... 69

• Changed description for Step 1 in Start-Up Sequence section ....................................................................... 71

• Changed Hardware Reset Timing Diagram figure............................................................................................72

• Added SYSREF Signal section.........................................................................................................................72

• Added Idle Channel Histogram section............................................................................................................ 73

• Changed Power Supply Recommendations section ........................................................................................79

Changes from Revision * (November 2015) to Revision A (December 2015)

Page

• 表7-8: changed several comments, added rows ............................................................................................ 32

• Changed 表7-13: added footnotes, changed JESD Mode and JESD Mode PLL column headers ................ 41

• Changed Serial Interface Registers figure: changed last value of JESD bank page address .........................44

• Changed Register Map table: changed ADC page registers 5Fh to 6Dh.........................................................45

• Changed description of decimation mode 0 to mode 4 in Example Register Writes section: deleted (default) ...

47

• Changed Register 5Fh, Register 60h, and Register 61h .................................................................................55

• Changed Register 6Ch and Register 6Dh ....................................................................................................... 56

• Changed Start-Up Sequence section .............................................................................................................. 71

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ZHCSEE2B –DECEMBER 2015 –REVISED JANUARY 2023

5 Pin Configuration and Functions

NC

1

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

NC

2

NC

DGND

IOVDD

SDIN

3

DGND

IOVDD

PDN

4

5

SCLK

SEN

6

RES

7

RESET

DVDD

AVDD

AVDD3V

AVDD

INAP

DVDD

AVDD

AVDD3V

SDOUT

AVDD

INDP

8

9

Thermal

Pad

10

11

12

13

14

15

16

17

18

INDM

INAM

AVDD

AVDD3V

AVDD

INCM

AVDD

AVDD3V

AVDD

INBM

Not to scale

图5-1. RMP Package, 72-Pin VQFN

(Top View)

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表5-1. Pin Functions

I/O

DESCRIPTION

NAME

Input, Reference

INAM

NUMBER

41

42

37

36

18

19

14

13

Differential analog input pins for channel A.

I

Connect INAP to AVDD and INAM to GND if unused.

INAP

INBM

Differential analog input pins for channel B. Connect INBP to AVDD and INBM to GND if unused.

INBP

INCM

Differential analog input pins for channel C. Connect INCP to AVDD and INCM to GND if unused.

Differential analog input pins for channel D. Connect INDP to AVDD and INDM to GND if unused.

INCP

INDM

INDP

Clock, SYNC

CLKINM

CLKINP

SYSREFM

SYSREFP

Control, Serial

DAM

28

27

34

33

I

Differential clock input pins for the ADC

External sync input pins

59

58

62

61

65

66

68

69

JESD204B Serial data output pins for channel A.

O

Connect a 100 Ohm resistor across DAM and DAP if unused.

DAP

DBM

JESD204B Serial data output pins for channel B. Connect a 100 Ohm resistor across DBM and DBP if

unused.

DBP

DCM

JESD204B Serial data output pins for channel C. Connect a 100 Ohm resistor across DCM and DCP if

unused.

DCP

DDM

JESD204B Serial data output pins for channel D. Connect a 100 Ohm resistor across DDM and DDP if

unused.

DDP

NC

1, 2, 22, 23, 53, 54

Do not connect

–

PDN

50

49

48

6

I/O

Power down. Can be configured via SPI register setting.

Reserve pin. Connect to GND

RES

–

I

RESET

SCLK

Hardware reset. Active high. This pin has an internal 150-kΩpulldown resistor.

Serial interface clock input

I

SDIN

5

I

Serial interface data input.

SDOUT

SEN

11

7

O

I

Serial interface data output.

Serial interface enable

SYNCbABM

SYNCbABP

SYNCbCDM

SYNCbCDP

Power Supply

AGND

56

55

71

72

Synchronization input pins for JESD204B port channel A, B. Can be configured via SPI to SYNCb signal for

all four channels. Needs external termination.

I

Synchronization input pins for JESD204B port channel C, D. Can be configured via SPI to SYNCb signal for

all four channels. Needs external termination.

21, 26, 29, 32

I

Analog ground

9, 12, 15, 17, 20,

25, 30, 35, 38, 40,

43, 44, 46

AVDD

Analog 1.9-V power supply

10, 16, 24, 31, 39,

45

AVDD3V

I

Analog 3 V for analog buffer

DGND

DVDD

IOVDD

3, 52, 60, 63, 67

8, 47

I

Digital ground

Digital 1.9-V power supply

4, 51, 57, 64, 70

Digital 1.15-V power supply for the JESD204B transmitter

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

V

AVDD3V

3.6

–0.3

–0.2

–0.3

AVDD

Supply voltage range

DVDD

2.1

IOVDD

Voltage between AGND and DGND

INAP, INBP, INAM, INBM, INCP, INDP, INCM, INDM

CLKINP, CLKINM

1.4

0.3

V

3

AVDD + 0.3

SYSREFP, SYSREFM

Voltage applied to input pins

V

SCLK, SEN, SDIN, RESET, SPI_MODE,

SYNCbABP, SYNCbABM, SYNCbCDP, SYNCbCDM,

PDN

2

–0.2

–65

Storage temperature, T_stg

150

°C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

VALUE

UNIT

V_(ESD)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±1000

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽²⁾

MIN

2.85

1.8

NOM

MAX

3.6

2

UNIT

AVDD3V

3

1.9

AVDD

Supply voltage range

DVDD

V

1.8

1.9

2

IOVDD

1.1

1.15

1.2

Differential input voltage range

Analog inputs

1.9

V_PP

V

Input common-mode voltage

2.0 ± 0.025

Input clock frequency, device clock frequency

250

500

MHz

V_PP

Input clock amplitude differential

(V_CLKP–V_CLKM

Sine wave, ac-coupled

1.5

1.6

)

Clock inputs

Temperature

LVPECL, ac-coupled

LVDS, ac-coupled

0.7

Input device clock duty cycle, default after reset

Operating free-air, T_A

45%

50%

55%

85

–40

°C

Operating junction, T_J

105⁽¹⁾

125

(1) Prolonged use above this junction temperature can increase the device failure-in-time (FIT) rate.

(2) SYSREF must be applied for the device initialization.

6.4 Thermal Information

ADS54J66

THERMAL METRIC⁽¹⁾

RMP (VQFNP)

UNIT

72 PINS

22.3

5.1

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

2.4

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.1

ψ_JT

2.3

ψ_JB

R_θJC(bot)

0.4

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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6.5 Electrical Characteristics

typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling frequency =

500 MSPS, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input for IF

≤250 MHz, and –3-dBFS differential input for IF > 250 MHz (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

General

ADC sampling rate

Resolution

500

MSPS

Bits

14

Power Supply

AVDD3V

AVDD

3-V analog supply

2.85

1.8

1.1

3

1.9

3.6

2

V

1.9-V analog supply

DVDD

IOVDD

I_AVDD3V

I_AVDD

1.9-V digital supply

1.9

2

V

1.15-V SERDES supply

3-V analog supply current

1.9-V analog supply current

1.15

340

365

1.2

V

370-MHz, full-scale input on all four channels

mA

2x decimation (4 channels), 370 MHz, full-scale input on

all four channels

190

184

533

2.68

2.67

250

I_DVDD

I_IOVDD

Pdis

1.9-V digital supply current

1.15-V SERDES supply current

Total power dissipation

mA

W

DDC mode-8 (no decimation), 370 MHz,

full-scale input on all four channels

DDC mode-8 (no decimation), 370 MHz,

full-scale input on all four channels

2x decimation (4 channels), 370 MHz, full-scale input on

all four channels

DDC mode-8 (no decimation), 370 MHz,

full-scale input on all four channels

Global power-down power

dissipation

Full-scale input on all four channels

mW

Analog Inputs

Differential input full-scale voltage

1.9

2.0

0.5

2.5

900

V_PP

V

Input common-mode voltage

Differential input resistance

Differential input capacitance

Analog input bandwidth (3 dB)

At f_IN= 370 MHz

kΩ

pF

MHz

Isolation

f_IN= 10 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 270 MHz

f_IN= 370 MHz

f_IN= 470 MHz

f_IN= 10 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 270 MHz

f_IN= 370 MHz

f_IN= 470 MHz

105

104

96

Crosstalk⁽¹⁾isolation between near

channels

(channels A and B are near to each

other, channels C and D are near

to each other)

dBFS

97

93

85

110

107

96

Crosstalk⁽¹⁾isolation between far

channels

(channels A and B, and channels C

and D are far channels)

dBFS

97

95

94

Clock Input

CLKINP and CLKINM pins are connected to internal

biasing voltage through 400 Ω

Internal clock biasing

1.15

V

(1) Crosstalk is measured with a –1-dBFS input signal on aggressor channel and no input on the victim channel.

8

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6.6 AC Performance

over operating free-air temperature range (unless otherwise noted)

NO DECIMATION,

500-MSPS OUTPUT

(DDC Mode 8)

DECIMATE-BY-2,

250-MSPS OUTPUT

(DDC Mode 2)

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

70.8

70.5

69.5

70.3

69

MAX

MIN

TYP

74.1

74

MAX

f_IN= 10 MHz

f_IN= 70 MHz

73.2

73.6

72.6

72

f_IN= 190 MHz, A_IN= –1 dBFS

f_IN= 190 MHz, A_IN= –3 dBFS

f_IN= 300 MHz

65.6

64.6

SNR

Signal-to-noise ratio

dBFS

f_IN= 350 MHz

68.7

68.4

67.5

154.8

154.5

153.5

154.3

153

152.7

152.4

151.5

70.7

70.4

69.4

70.2

68.9

68.6

68.2

66.9

89

f_IN= 370 MHz

71.5

70.7

155.1

155

f_IN= 470 MHz

f_IN= 10 MHz

f_IN= 70 MHz

154.2

154.6

153.6

153

f_IN= 190 MHz, A_IN= –1 dBFS

f_IN= 190 MHz, A_IN= –3 dBFS

f_IN= 300 MHz

149.6

148.6

NSD

Noise spectral density

dBFS/Hz

dBFS

dBc

f_IN= 350 MHz

f_IN= 370 MHz

152.5

151.7

73.9

73.1

73.5

72.5

71.7

f_IN= 470 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 190 MHz, A_IN= –1 dBFS

f_IN= 190 MHz, A_IN= –3 dBFS

f_IN= 300 MHz

Signal-to-noise and

distortion ratio

SINAD

SFDR

HD2

f_IN= 350 MHz

f_IN= 370 MHz

f_IN= 470 MHz

69.7

88

f_IN= 10 MHz

f_IN= 70 MHz

87

95

86

97

f_IN= 190 MHz, A_IN= –1 dBFS

f_IN= 190 MHz, A_IN= –3 dBFS

f_IN= 300 MHz

78

75

88

96

Spurious-free dynamic

range

82

94

f_IN= 350 MHz

82

f_IN= 370 MHz

81

f_IN= 470 MHz

73

74

91

f_IN= 10 MHz

89

f_IN= 70 MHz

94

103

101

97

86

f_IN= 190 MHz, A_IN= –1 dBFS

f_IN= 190 MHz, A_IN= –3 dBFS

f_IN= 300 MHz

78

75

88

Second-order harmonic

distortion

dBc

82

f_IN= 350 MHz

82

f_IN= 370 MHz

81

f_IN= 470 MHz

73

74

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6.6 AC Performance (continued)

over operating free-air temperature range (unless otherwise noted)

NO DECIMATION,

500-MSPS OUTPUT

(DDC Mode 8)

DECIMATE-BY-2,

250-MSPS OUTPUT

(DDC Mode 2)

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

93

87

98

97

95

90

85

83

94

93

92

91

90

87

88

85

86

81

79

78

72

89

MAX

MIN

TYP

88

MAX

f_IN= 10 MHz

f_IN= 70 MHz

99

100

98

f_IN= 190 MHz, A_IN= –1 dBFS

f_IN= 190 MHz, A_IN= –3 dBFS

f_IN= 300 MHz

78

75

Third-order harmonic

distortion

HD3

dBc

100

96

f_IN= 350 MHz

f_IN= 370 MHz

f_IN= 470 MHz

83

98

95

97

96

94

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 190 MHz, A_IN= –1 dBFS

f_IN= 190 MHz, A_IN= –3 dBFS

f_IN= 300 MHz

Non

HD2,

HD3

Spurious-free

dynamic range

(excluding HD2, HD3)

87

80

dBc

f_IN= 350 MHz

f_IN= 370 MHz

f_IN= 470 MHz

93

86

92

91

89

82

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 190 MHz, A_IN= –1 dBFS

f_IN= 190 MHz, A_IN= –3 dBFS

f_IN= 300 MHz

THD

Total harmonic distortion

dBc

f_IN= 350 MHz

f_IN= 370 MHz

f_IN= 470 MHz

73

f_IN= 185 MHz, f_IN= 190 MHz,

A_IN= –7 dBFS

f_IN= 365 MHz, f_IN= 370 MHz,

A_IN= –7 dBFS

82

77

Two-tone, third-order

intermodulation distortion

IMD3

dBFS

f_IN= 465 MHz, f_IN= 470 MHz,

A_IN= –7 dBFS

10

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6.7 Digital Characteristics

typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling rate = 500

MSPS, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Digital Inputs (RESET, SCLK, SEN, SDIN, PDN)⁽¹⁾

V_IH

V_IL

High-level input voltage

Low-level input voltage

All digital inputs support 1.2-V and 1.8-V logic levels

0.8

V

All digital inputs support 1.2-V and 1.8-V logic levels

0.4

SEN

0

100

50

I_IH

High-level input current

Low-level input current

µA

RESET, SCLK, SDIN, PDN

SEN

I_IL

RESET, SCLK, SDIN, PDN

0

Digital Inputs (SYSREFP, SYSREFM, SYNCbABM, SYNCbABP, SYNCbCDM, SYNCbCDP)

V_D

Differential input voltage

0.35

0.45

1.3

1.4

V

V_{(CM_DIG)}

Common-mode voltage for SYSREF

Digital Outputs (SDOUT, PDN)

DVDD –

V_OH

High-level output voltage

DVDD

V

0.1

V_OL

Low-level output voltage

0.1

Digital Outputs (JESD204B Interface: DxP, DxM)⁽²⁾

V_OD

V_OC

Output differential voltage

With default swing setting

700

450

mV_PP

mV

Output common-mode voltage

Transmitter pins shorted to any voltage between –

0.25 V and 1.45 V

Transmitter short-circuit current

Single-ended output impedance

Output capacitance

100

mA

–100

z_os

50

2

Ω

Output capacitance inside the device,

from either output to ground

pF

(1) The RESET, SCLK, SDATA, and PDN pins have a 20-kΩ(typical) internal pulldown resistor to ground, and the SEN pin has a 20-kΩ

(typical) pull up resistor to IOVDD.

(2) 50-Ω, single-ended external termination to IOVDD.

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6.8 Timing Requirements

typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling rate = 500

MSPS, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input

(unless otherwise noted)

MIN

TYP

MAX

UNIT

Sample Timing Characteristics (TBD are any of these Switching Characteristics?)

Aperture delay

0.75

1.6

ns

ps

Aperture delay matching between two channels on the same device

Aperture delay matching between two devices at the same temperature and supply voltage

Aperture jitter

±70

±270

135

ps

f_Srms

µs

Wake-up time to valid data after coming out of global power-down

150

Input clock

cycles

Data latency⁽¹⁾: ADC sample to digital output

OVR latency: ADC sample to OVR bit

77

44

4

Input clock

cycles

Clock propagation delay: input clock rising edge cross-over to output clock rising edge cross-

over

t_PDI

ns

(2)

t_{SU_SYSREF}

Setup time for SYSREF, referenced to input clock falling edge

Hold time for SYSREF, referenced to input clock falling edge

300

100

ps

(2)

t_{H_SYSREF}

JESD Output Interface Timing Characteristics

Unit interval

100

2.5

400

10

ps

Gbps

ps

Serial output data rate

Total jitter for BER of 1E-15 and lane rate = 10 Gbps

26

0.75

12

Random jitter for BER of 1E-15 and lane rate = 10 Gbps

Deterministic jitter for BER of 1E-15 and lane rate = 10 Gbps

ps rms

ps, pk-pk

Data rise time, data fall time: rise and fall times measured from 20% to 80%, differential

output waveform, 2.5 Gbps ≤bit rate ≤10 Gbps

t_R, t_F

35

ps

(1) Overall ADC latency = data latency + t_PDI

.

(2) SYSREF should arrive 'setup time' before the active edge of sampling clock and remain stable until 'hold time' after active edge of

sampling clock. See 图6-2.

12

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N+1

N+2

N

Sample

t_PD

Data Latency: 77 Clock Cycles

CLKINP

CLKINM

DAP, DAM

DBP, DBM

DCP, DCM

DDP, DDM

D20

D1

D20

Sample N-1

Sample N

Sample N+1

图6-1. Latency Timing Diagram

CLKIN

500 MSPS

t_SU

t_HO

t_SU

t_HO

SYSREF

图6-2. SYSREF Timing Diagram

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6.9 Typical Characteristics: General (DDC Mode-8)

typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling frequency =

500 MSPS, 14-bit resolution, no decimation filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD =

1.15 V, –1-dBFS differential input for IF ≤250 MHz, and –3-dBFS differential input for IF > 250 MHz (unless otherwise

noted)

0

-20

-40

-60

-80

-100

-120

-100

-120

0

50

100 150

Input Frequency (MHz)

200

250

0

50

100 150

Input Frequency (MHz)

200

250

D001

D002

f_IN= 10 MHz , A_IN= –1 dBFS, SNR = 71 dBFS, SFDR = 89

f_IN= 140 MHz , A_IN= –1 dBFS, SNR = 70 dBFS, SFDR = 88

dBc, SFDR = 89 dBc (non 23)

dBc, SFDR = 91 dBc (non 23)

图6-3. FFT for 10-MHz Input Signal

图6-4. FFT for 140-MHz Input Signal

0

-20

-40

-20

-40

-60

-80

-100

-120

-100

-120

0

50

100 150

Input Frequency (MHz)

200

250

0

50

100 150

Input Frequency (MHz)

200

250

D003

D004

f_IN= 190 MHz , A_IN= –1 dBFS, SNR = 69.4 dBFS, SFDR =

f_IN= 230 MHz , A_IN= –1 dBFS, SNR = 69.4 dBFS, SFDR =

88 dBc, SFDR = 96 dBc (non 23)

85 dBc, SFDR = 96 dBc (non 23)

图6-5. FFT for 190-MHz Input Signal

图6-6. FFT for 230-MHz Input Signal

0

-20

-40

-20

-40

-60

-80

-100

-120

-100

-120

0

50

100 150

Input Frequency (MHz)

200

250

0

50

100 150

Input Frequency (MHz)

200

250

D005

D006

f_IN= 300 MHz , A_IN= –3 dBFS, SNR = 69.4 dBFS, SFDR =

f_IN= 370 MHz , A_IN= –3 dBFS, SNR = 68.4 dBFS, SFDR =

80 dBc, SFDR = 95 dBc (non 23)

84 dBc, SFDR = 86 dBc (non 23)

图6-7. FFT for 300-MHz Input Signal

图6-8. FFT for 370-MHz Input Signal

14

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6.9 Typical Characteristics: General (DDC Mode-8) (continued)

typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling frequency =

500 MSPS, 14-bit resolution, no decimation filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD =

1.15 V, –1-dBFS differential input for IF ≤250 MHz, and –3-dBFS differential input for IF > 250 MHz (unless otherwise

noted)

0

-20

-40

-60

-80

-100

-120

-100

-120

0

50

100 150

Input Frequency (MHz)

200

250

0

50

100 150

Input Frequency (MHz)

200

250

D007

D008

f_IN1= 185 MHz, f_IN2= 190 MHz, IMD = 89 dBFS, each tone at

f_IN= 470 MHz , A_IN= –3 dBFS, SNR = 67.4 dBFS, SFDR =

73 dBc, SFDR = 80 dBc (non 23)

–7 dBFS

图6-9. FFT for 470-MHz Input Signal

图6-10. FFT for Two-Tone Input Signal

0

-20

-40

-20

-40

-60

-80

-100

-120

-100

-120

0

50

100 150

Input Frequency (MHz)

200

250

0

50

100 150

Input Frequency (MHz)

200

250

D009

D010

f_IN1= 185 MHz, f_IN2= 190 MHz, IMD = 103 dBFS, each tone

f_IN1= 370 MHz, f_IN2= 365 MHz, IMD = 81.7 dBFS, each tone

at –36 dBFS

at –7 dBFS

图6-11. FFT for Two-Tone Input Signal

图6-12. FFT for Two-Tone Input Signal

0

-20

-40

-20

-40

-60

-80

-100

-120

-100

-120

0

50

100 150

Input Frequency (MHz)

200

250

0

50

100 150

Input Frequency (MHz)

200

250

D011

D012

f_IN1= 370 MHz, f_IN2= 365 MHz, IMD = 102 dBFS, each tone

f_IN1= 470 MHz, f_IN2= 465 MHz, IMD = 76.7 dBFS, each tone

at –36 dBFS

at –7 dBFS

图6-13. FFT for Two-Tone Input Signal

图6-14. FFT for Two-Tone Input Signal

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6.9 Typical Characteristics: General (DDC Mode-8) (continued)

typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling frequency =

500 MSPS, 14-bit resolution, no decimation filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD =

1.15 V, –1-dBFS differential input for IF ≤250 MHz, and –3-dBFS differential input for IF > 250 MHz (unless otherwise

noted)

0

-88

-90

-20

-92

-40

-94

-60

-96

-98

-80

-100

-102

-104

-100

-120

0

50

100 150

Input Frequency (MHz)

200

250

-35

-31

-27

-23

Each Tone Amplitude (dBFS)

-19

-15

-11

-7

D013

D014

f_IN1= 470 MHz, f_IN2= 465 MHz, IMD = 98.8 dBFS, each tone

f_IN1= 185 MHz, f_IN2= 190 MHz

at –36 dBFS

图6-16. Intermodulation Distortion vs Input Amplitude

图6-15. FFT for Two-Tone Input Signal

-80

-74

-80

-84

-88

-86

-92

-96

-98

-100

-104

-35

-31

-27

Each Tone Amplitude (dBFS)

-23

-19

-15

-11

-7

-35

-31

-27

Each Tone Amplitude (dBFS)

-23

-19

-15

-11

-7

D015

D016

f_IN1= 365 MHz, f_IN2= 370 MHz

f_IN1= 465 MHz, f_IN2= 470 MHz

图6-17. Intermodulation Distortion vs Input Amplitude

图6-18. Intermodulation Distortion vs Input Amplitude

96

Ain = -1 dBFS

Ain = -3 dBFS

92

93

90

87

84

81

78

88

84

80

76

72

0

40 80 120 160 200 240 280 320 360 400 440 480

Input Frequency (MHz)

0

40 80 120 160 200 240 280 320 360 400 440 480

Input Frequency (MHz)

D017

D018

图6-19. Spurious-Free Dynamic Range vs Input Frequency

图6-20. IL Spur vs Input Frequency

16

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6.9 Typical Characteristics: General (DDC Mode-8) (continued)

typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling frequency =

500 MSPS, 14-bit resolution, no decimation filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD =

1.15 V, –1-dBFS differential input for IF ≤250 MHz, and –3-dBFS differential input for IF > 250 MHz (unless otherwise

noted)

71.5

70.5

69.5

68.5

67.5

66.5

72

71.2

70.4

69.6

68.8

68

AIN = -1 dBFS

AIN = -3 dBFS

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.95 V

AVDD = 2 V

0

40 80 120 160 200 240 280 320 360 400 440 480

Input Frequency (MHz)

-40

-15

10 35

Temperature (°C)

60

85

D019

D020

图6-21. Signal-to-Noise Ratio vs Input Frequency

f_IN= 190 MHz, A_IN= –1 dBFS

图6-22. Signal-to-Noise Ratio vs AVDD Supply and Temperature

93

72

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.95 V

AVDD = 2 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.95 V

AVDD = 2 V

71

70

69

68

67

66

91

89

87

85

-40

-15

10 35

Temperature (°C)

60

85

-40

-15

10 35

Temperature (°C)

60

85

D021

D022

f_IN= 190 MHz, A_IN= –1 dBFS

f_IN= 370 MHz, A_IN= –3 dBFS

图6-23. Spurious-Free Dynamic Range vs AVDD Supply and

图6-24. Signal-to-Noise Ratio vs AVDD Supply and Temperature

Temperature

84

71.4

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.95 V

AVDD = 2 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

DVDD = 1.95 V

DVDD = 2 V

71

70.6

70.2

69.8

69.4

83

82

81

80

-40

-15

10 35

Temperature (°C)

60

85

-40

-15

10 35

Temperature (°C)

60

85

D023

D024

f_IN= 370 MHz, A_IN= –3 dBFS

f_IN= 190 MHz, A_IN= –1 dBFS

图6-25. Spurious-Free Dynamic Range vs AVDD Supply and

图6-26. Signal-to-Noise Ratio vs DVDD Supply and

Temperature

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6.9 Typical Characteristics: General (DDC Mode-8) (continued)

typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling frequency =

500 MSPS, 14-bit resolution, no decimation filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD =

1.15 V, –1-dBFS differential input for IF ≤250 MHz, and –3-dBFS differential input for IF > 250 MHz (unless otherwise

noted)

92

91

90

89

88

87

86

71

70

69

68

67

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

DVDD = 1.95 V

DVDD = 2 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

DVDD = 1.95 V

DVDD = 2 V

-40

-15

10 35

Temperature (°C)

60

85

-40

-15

10 35

Temperature (°C)

60

85

D025

D026

f_IN= 190 MHz, A_IN= –1 dBFS

f_IN= 370 MHz, A_IN= –3 dBFS

图6-27. Spurious-Free Dynamic Range vs DVDD Supply and

图6-28. Signal-to-Noise Ratio vs DVDD Supply and

Temperature

84

72.2

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

DVDD = 1.95 V

DVDD = 2 V

AVDD3V = 2.85 V

AVDD3V = 3 V

AVDD3V = 3.1 V

AVDD3V = 3.2 V

AVDD3V = 3.3 V

AVDD3V = 3.4 V

AVDD3V = 3.5 V

AVDD3V = 3.6 V

71.7

71.2

70.7

70.2

69.7

69.2

83

82

81

80

-40

-15

10 35

Temperature (°C)

60

85

-40

-15

10 35

Temperature (°C)

60

85

D027

D028

f_IN= 370 MHz, A_IN= –3 dBFS

f_IN= 190 MHz, A_IN= –1 dBFS

图6-29. Spurious-Free Dynamic Range vs DVDD Supply and

图6-30. Signal-to-Noise Ratio vs AVDD3V Supply and

Temperature

92

73

AVDD3V = 2.85 V

AVDD3V = 3 V

AVDD3V = 3.1 V

AVDD3V = 3.2 V

AVDD3V = 3.3 V

AVDD3V = 3.4 V

AVDD3V = 3.5 V

AVDD3V = 3.6 V

AVDD3V = 2.85 V

AVDD3V = 3 V

AVDD3V = 3.1 V

AVDD3V = 3.2 V

AVDD3V = 3.3 V

AVDD3V = 3.4 V

AVDD3V = 3.5 V

AVDD3V = 3.6 V

91

90

89

88

87

86

72

71

70

69

68

67

-40

-15

10 35

Temperature (°C)

60

85

-40

-15

10 35

Temperature (°C)

60

85

D029

D030

f_IN= 190 MHz, A_IN= –1 dBFS

f_IN= 370 MHz, A_IN= –3 dBFS

图6-31. Spurious-Free Dynamic Range vs AVDD3V Supply and

图6-32. Signal-to-Noise Ratio vs AVDD3V Supply and

Temperature

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6.9 Typical Characteristics: General (DDC Mode-8) (continued)

typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling frequency =

500 MSPS, 14-bit resolution, no decimation filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD =

1.15 V, –1-dBFS differential input for IF ≤250 MHz, and –3-dBFS differential input for IF > 250 MHz (unless otherwise

noted)

84

83

82

81

80

74

72

70

68

66

64

150

125

100

75

AVDD3V = 2.85 V

AVDD3V = 3 V

AVDD3V = 3.1 V

AVDD3V = 3.2 V

AVDD3V = 3.3 V

AVDD3V = 3.4 V

AVDD3V = 3.5 V

AVDD3V = 3.6 V

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

50

25

-40

-15

10 35

Temperature (°C)

60

85

-70

-60

-50

-40 -30

Amplitude (dBFS)

-20

-10

0

D031

D032

f_IN= 190 MHz

图6-34. Performance vs Amplitude

f_IN= 370 MHz, A_IN= –3 dBFS

图6-33. Spurious-Free Dynamic Range vs AVDD3V Supply and

Temperature

74

72.5

71

180

150

120

90

75

73

71

69

67

65

110

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

SNR

SFDR

100

90

69.5

68

80

60

70

66.5

30

65

0

60

-70

-60

-50

-40 -30

Amplitude (dBFS)

-20

-10

0

0.2

0.6

1

Differential Clock Amplitude (Vpp)

1.4

1.8

2.2

D033

D034

f_IN= 370 MHz

图6-35. Performance vs Amplitude

f_IN= 190 MHz, A_IN= –1 dBFS

图6-36. Performance vs Clock Amplitude

75

72

69

66

63

60

125

100

75

50

25

0

73

95

90

85

80

75

70

SNR

SFDR

SNR

SFDR

72

71

70

69

68

0.2

0.6

1

Differential Clock Amplitude (Vpp)

1.4

1.8

2.2

30

35

40

45

50

Input Clock Duty Cycle (%)

55

60

65

70

D035

D036

f_IN= 370 MHz, A_IN= –3 dBFS

f_IN= 190 MHz, A_IN= –1 dBFS

图6-38. Performance vs Clock Duty Cycle

图6-37. Performance vs Clock Amplitude

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6.9 Typical Characteristics: General (DDC Mode-8) (continued)

typical values are at T_A= 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling frequency =

500 MSPS, 14-bit resolution, no decimation filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD =

1.15 V, –1-dBFS differential input for IF ≤250 MHz, and –3-dBFS differential input for IF > 250 MHz (unless otherwise

noted)

72

71

70

69

68

67

66

65

90

87

84

81

78

75

72

69

0

SNR

SFDR

-20

-40

-60

-80

-100

-120

30

35

40

45

Input Clock Duty Cycle (%)

50

55

60

65

70

0

50

100 150

Input Frequency (MHz)

200

250

D037

D038

f_IN= 370 MHz, A_IN= –3 dBFS

图6-39. Performance vs Clock Duty Cycle

f_IN= 190 MHz , A_IN= –1 dBFS SFDR = 49 dBc, f_PSRR= 5

MHz, A_PSRR= 50 mV_PP

图6-40. Power-Supply Rejection Ratio FFT for Test Signal on

AVDD Supply

-10

-15

0

-20

PSRR with 50-mVPP Signal on AVDD

PSRR with 50-mVPP Signal on AVDD3V

-20

-25

-30

-35

-40

-45

-50

-55

-40

-60

-80

-100

-120

0

50

100

Frequency of Signal on Supply (MHz)

150

200

250

300

0

50

100 150

Input Frequency (MHz)

200

250

D039

D040

f_IN= 190 MHz, A_IN= –1 dBFS

f_IN= 190 MHz , A_IN= –1 dBFS SFDR = 81 , f_CMRR= 5 MHz,

A_CMRR= 50 mV_PP

图6-41. Power-Supply Rejection Ratio vs Supplies

图6-42. Common-Mode Rejection Ratio FFT

-20

-25

-30

-35

-40

-45

-50

-55

-60

4

AVDD_Power (W)

DVDD_Power (W)

AVDD3V_Power (W)

IOVDD_Power (W)

TotalPower (W)

3.2

2.4

1.6

0.8

0

50

100

Frequency of Input Common-Mode Signal (MHz)

150

200

250

300

250

300

350 400

Sampling Speed (MSPS)

450

500

D041

D042

图6-44. Power vs Chip Clock

f_IN= 190 MHz, A_IN= –1 dBFS 50-mV_PPtest signal on input

common-mode

图6-43. Common-Mode Rejection Ratio

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6.10 Typical Characteristics: Mode 2

low-pass or high-pass decimation-by-2 filter selected as per input frequency; typical values are at T_A= 25°C, full temperature

range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling frequency = 500 MSPS, 14-bit resolution, no decimation filter,

50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input for IF ≤250 MHz,

and –3-dBFS differential input for IF > 250 MHz (unless otherwise noted)

0

-20

-40

-60

-80

-100

-120

-100

-120

0

25

50 75

Input Frequency (MHz)

100

125

0

25

50 75

Input Frequency (MHz)

100

125

D043

D044

f_IN= 100 MHz, A_IN= –1 dBFS, SNR = 74.1 dBFS, SFDR =

f_IN= 150 MHz, A_IN= –1 dBFS, SNR = 73.8 dBFS, SFDR =

98 dBc, SFDR = 100 dBc (non 23)

99 dBc, SFDR = 99 dBc (non 23)

图6-45. FFT for 100-MHz Input Signal

图6-46. FFT for 150-MHz Input Signal

0

-20

-40

-20

-40

-60

-80

-100

-120

-100

-120

0

25

50 75

Input Frequency (MHz)

100

125

0

25

50 75

Input Frequency (MHz)

100

125

D045

f_IN= 185 MHz, A_IN= –1 dBFS, SNR = 73.2 dBFS, SFDR =

f_IN= 230 MHz, A_IN= –1 dBFS, SNR = 72.4 dBFS, SFDR =

98 dBc, SFDR = 98 dBc (non 23)

91 dBc, SFDR = 98 dBc (non 23)

图6-47. FFT for 185-MHz Input Signal

图6-48. FFT for 230-MHz Input Signal

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6.11 Typical Characteristics: Mode 0

low-pass decimation-by-2 filter selected, complex FFT plotted, mixer frequency 125 MHz; typical values are at T_A= 25°C, full

temperature range is from T_MIN= –40°C to T_MAX= 85°C, ADC sampling frequency = 500 MSPS, 14-bit resolution, no

decimation filter, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input

for IF ≤250 MHz, and –3-dBFS differential input for IF > 250 MHz (unless otherwise noted)

0

-20

-40

-60

-80

-100

-120

-125

-75

-25 25

Input Frequency (MHz)

75

125

-125

-75

-25 25

Input Frequency (MHz)

75

125

D047

D048

f_IN= 270 MHz, A_IN= –3 dBFS, SNR = 69.5 dBFS, SFDR =

f_IN= 370 MHz, A_IN= –3 dBFS, SNR = 68.1 dBFS, SFDR =

83 dBc, SFDR = 87 dBc (non 23)

82 dBc, SFDR = 82 dBc (non 23)

图6-49. FFT for 270-MHz Input Signal

图6-50. FFT for 370-MHz Input Signal

0

-20

-40

-60

-80

-100

-120

-125

-75

-25 25

Input Frequency (MHz)

75

125

D049

f_IN= 470 MHz, A_IN= –3 dBFS, SNR = 66.3 dBFS, SFDR = 75 dBc, SFDR = 75 dBc (non 23)

图6-51. FFT for 470-MHz Input Signal

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7 Detailed Description

7.1 Overview

The ADS54J66 is a low-power, wide-bandwidth, 14-bit, 500-MSPS, quad-channel, telecom receiver device. The

ADS54J66 supports the JESD204B serial interface with data rates up to 10 Gbps supporting one lane per

channel. The buffered analog input provides uniform input impedance across a wide frequency range and

minimizes sample-and-hold glitch energy. The ADS54J66 provides excellent spurious-free dynamic range

(SFDR) over a large input frequency range with very low power consumption. The device digital block includes a

2x and 4x decimation low-pass filter with f_S/ 4 and k × f_S/ 16 mixers to support a receive bandwidth up to 200

MHz for use as a Digital Pre-Distortion (DPD) observation receiver.

The JESD204B interface reduces the number of interface lines allowing high system integration density. An

internal phase locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock which is

used to serialize the 14-bit data from each channel.

7.2 Functional Block Diagram

Digital Block

Interleaving

Correction

2x

INAP,

INAM

14-Bit

ADC

DAP,

DAM

FS / 4

4x

2x

JESD204B

Digital Block

Interleaving

Correction

K x FS / 16

INBP,

INBM

14-Bit

ADC

DBP,

DBM

FS / 8

SYSREFP,

SYSREFM

CLKINP,

CLKINM

PLL

x10/x20

SYNCbAB

SYNCbCD

Digital Block

Interleaving

Correction

INCP,

INCM

14-Bit

ADC

DCP, DCM

DDP, DDM

2x

FS / 4

JESD204B

4x

2x

Digital Block

Interleaving

Correction

INDP,

INDM

14-Bit

ADC

K x FS / 16

FS / 8

Configuration

Registers

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7.3 Feature Description

7.3.1 Analog Inputs

The ADS54J66 analog signal inputs are designed to be driven differentially. The analog input pins have internal

analog buffers that drive the sampling circuit. As a result of the analog buffer, the input pins present a high

impedance input across a very wide frequency range to the external driving source which enables great flexibility

in the external analog filter design as well as excellent 50-Ω matching for RF applications. The buffer also helps

isolate the external driving circuit from the internal switching currents of the sampling circuit, thus resulting in a

more constant SFDR performance across input frequencies.

The common-mode voltage of the signal inputs is internally biased to 1.9 V using 600-Ω resistors which allows

for ac coupling of the input drive network. Each input pin (INP, INM) must swing symmetrically between (VCM +

0.475 V) and (VCM –0.475 V), resulting in a 1.9-V_PP(default) differential input swing. The input sampling circuit

has a 3-dB bandwidth that extends up to 900 MHz.

7.3.2 Recommended Input Circuitry

In order to achieve optimum ac performance the circuitry shown in 图7-1 is recommended at the analog inputs.

T1

T2

0.1 mF

10 W

INxP

0.1 mF

25 W

0.1 mF

R_IN

C_IN

3.3 pF

25 W

INxM

1:1

10 W

0.1 mF

Device

图7-1. Analog Input Driving Circuit

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7.4 Device Functional Modes

7.4.1 Digital Features

The ADS54J66 supports decimation-by-2 and -4 and un-decimated output. The four channels can be configured

as pairs (A, B and C, D; however, the same decimation factor must be chosen for all four channels).

图7-2 shows signal processing done in the digital down-conversion (DDC) block of the ADS54J66. 表7-1 shows

available modes of operation for this block.

I Data

Filter

N

Real Data

0

2

4

5

6

7

8

cos (2pnf_mix2/ f_S

)

cos (2pnf_mix1/ f_S

)

500-MSPS

Data, x(n)

Channel x

2

To JESD

Encoder

Upscaled

Zero-Padded

Data

sin (2pnf_mix1/ f_S

)

sin (2pnf_mix2/ f_S

)

N

Filter

Q Data

Default 14-Bit

Mode

Default 14-Bit Data

Mode

Selection

图7-2. Digital Down-Conversion Block Diagram

表7-1. Overview of Operating Modes

BANDWIDTH

OPERATING

DIGITAL

MIXER

OUTPUT

FORMAT

MAX OUTPUT

DESCRIPTION

DECIMATION

MODE

RATE

491 MSPS

368 MSPS

150 MHz

75 MHz

0

2

4

5

6

7

8

±f_S/ 4

2

200 MHz

100 MHz

200 MHz

100 MHz

245.76 MHz

Complex

Real

250 MSPS

125 MSPS

500 MSPS

–

N × f_S/ 16

2

75 MHz

Real

Decimation

2

150 MHz

75 MHz

Complex

Real

4

2

75 MHz

No decimation

184.32 MHz

Real

–

表7-2 shows characteristics of different blocks of DDC signal processing blocks active in different modes.

表7-2. Features of DDC Block in Different Modes

MODE

f_mix1

FILTER AND DECIMATION

LPF cutoff at f_S/ 4, decimation-by-2

LPF or HPF cutoff at f_S/ 4, decimation-by-2

LPF cutoff at f_S/ 8, decimation-by-2

LPF cutoff at f_S/ 8, decimation-by-4

f_mix2

OUTPUT

0

2

4

5

6

f_S/ 4

Not used

f_S/ 8

I, Q data at 250 MSPS each are given out

Straight 250 MSPS data are given out

Real data at 250 MSPS are given out

I, Q data at 250 MSPS each are given out

I, Q data at 125 MSPS each are given out

Not used

k f_S/ 16

Not used

Real data are up-scaled, zero-padded and given

out at 500 MSPS

7

k f_S/ 16

LPF cutoff at f_S8, decimation-by-2

Not used

f_S/ 8

Default

Not used

Straight 500-MSPS, 14-bit data are given out

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7.4.2 Mode 0, Decimation-by-2 with IQ Outputs for up to 220 MHz of IQ Bandwidth

In this configuration, the DDC block includes a fixed frequency ±f_S/ 4 complex digital mixer preceding the digital

filter, so the IQ passband is approximately ±110 MHz (3 dB) centered at f_S/ 4. Mixing with +f_S/ 4 inverts the

spectrum. The stop-band attenuation is approximately 90 dB and the pass-band flatness is ±0.1 dB. 图 7-3

shows mixing operation in DDC mode 0. 表7-3 shows corner frequencies of decimation filter in DDC mode 0. 图

7-4 and 图7-5 show frequency response of the filter.

f_S/ 4

IQ:

500 MSPS

250 MSPS

14-Bit

ADC

2x

f_S/ 4

f_S/ 2

f_S/ 4

图7-3. Mixing in Mode 0

表7-3. Filter Specification Details, Mode 0

CORNERS

–0.1 dB

–0.5 dB

–1 dB

LOW PASS

0.204 × f_S

0.211 × f_S

0.216 × f_S

0.226 × f_S

–3 dB

20

0

0.5

0

-20

-40

-60

-80

-100

-120

-0.5

-1

-1.5

-2

-2.5

-3

0

0.1

0.2 0.3

Frequency Response

0.4

0.5

0

0.05

0.1 0.15

Frequency Response

0.2

0.25

D052

D053

图7-4. Frequency Response of Filter in Mode 0

图7-5. Zoomed View of Frequency Response

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7.4.3 Mode 2, Decimation-by-2 for up to 110 MHz of Real Bandwidth

In this configuration, the DDC block only includes a 2x decimation filter (high pass or low pass) with real outputs.

The pass band is approximately 110 MHz (3 dB). 图 7-6 shows the filtering operation in DDC mode 2. 表 7-4

shows corner frequencies of decimation filter in DDC mode 2. 图7-7 and 图7-8 show frequency response of the

filter.

500 MSPS

250 MSPS

14-Bit

ADC

2x

f_S/ 4

f_S/ 2

f_S/ 4

图7-6. Filtering in Mode 2

表7-4. Filter Specification Details, Mode 2

CORNERS

–0.1 dB

–0.5 dB

–1 dB

LOW PASS

0.204 × f_S

0.211 × f_S

0.216 × f_S

0.226 × f_S

HIGH PASS

0.296 × f_S

0.290 × f_S

0.284 × f_S

0.274 × f_S

–3 dB

20

0

0.5

0

-20

-40

-60

-80

-100

-120

-0.5

-1

-1.5

-2

-2.5

-3

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Frequency Response

0

0.05

0.1 0.15

Frequency Response

0.2

0.25

D056

D057

图7-7. Frequency Response for Decimate-by-2

图7-8. Zoomed View of Frequency Response

Low-Pass and High-Pass Filter (in Mode 2)

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7.4.4 Modes 4 and 7, Decimation-by-2 with Real Outputs for up to 110 MHz of Bandwidth

In this configuration, the DDC block includes a selectable N × f_S/ 16 complex digital mixer (N from –8 to +7)

preceding the decimation-by-2 digital filter also with an IQ passband of approximately ±55 MHz (3 dB) centered

at N × f_S/ 16. A positive value for N inverts the spectrum. In addition, a f_S/ 8 complex digital mixer is added after

the decimation filter transforming the output back to real format and centers the output spectrum within the

Nyquist zone.

In addition, the ADS54J66 supports a 0-pad feature where a sample with value = 0 is added after each sample.

In this way the output data rate is interpolated to 500 MSPS (real) with a second image inverted at f_S/ 2 –f_IN.

The stop-band attenuation is approximately 90 dB for in-band aliases from negative frequencies and

approximately 55 dB for out-of-band aliases. The passband flatness is ±0.1 dB. 图 7-9 shows the filtering

operation in DDC mode 4 and 7. 表 7-5 shows corner frequencies of decimation filter in DDC mode 4 and 7. 图

7-10 and 图7-11 show frequency response of the filter.

f_S/ 8

2^ndImage

N x f_S/ 16

f_S/ 8

Real:

500 MSPS

0 Pad

IQ:

500 MSPS

IQ: 250 MSPS

14-Bit

ADC

Real:

250 MSPS

2x

f_S/ 4

f_S/ 2

Example

:

N= -4

f_S/ 8

f_S/ 4

f_S/ 2

0

f_S/ 8

f_S/ 4

图7-9. Mixing and Filtering in Modes 4 and 7

表7-5. Filter Specification Details, Modes 4 and 7

CORNERS

–0.1 dB

–0.5 dB

–1 dB

LOW PASS

0.102 × f_S

0.105 × f_S

0.108 × f_S

0.113 × f_S

–3 dB

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20

0

0.5

0

-20

-40

-60

-80

-100

-0.5

-1

-1.5

-2

-2.5

-3

-120

0

0.05

0.1 0.15

Frequency Response

0.2

0.25

0

0.05

0.1 0.15

Frequency Response

0.2

0.25

D050

D051

图7-10. Frequency Response for Decimate-by-2,

图7-11. Zoomed View of Frequency Response

Low-Pass Filter (in Modes 4 and 7)

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7.4.5 Mode 5, Decimation-by-2 with IQ Outputs for up to 110 MHz of IQ Bandwidth

In this configuration, the DDC block includes a selectable N × f_S/ 16 complex digital mixer (N from –8 to +7)

preceding the decimation-by-2 digital filter, so the IQ passband is approximately ±55 MHz (3 dB) centered at N ×

f_S/ 16. A positive value for N inverts the spectrum.

The stop-band attenuation is approximately 90 dB for in-band aliases from negative frequencies. The pass-band

flatness is ±0.1 dB. Figure 62 shows the filtering operation in DDC mode 5. Table 6 shows corner frequencies of

decimation filter in DDC mode 5. Figure 63 and Figure 64 show frequency response of the filter. 图 7-12 shows

the filtering operation in DDC mode 5. 表 7-6 shows corner frequencies of decimation filter in DDC mode 5. 图

7-13 and 图7-14 show frequency response of the filter.

N x f_S/ 16

IQ:

500 MSPS

IQ:

250 MSPS

500 MSPS

14-Bit

ADC

2x

Example:

N = -4

f_S/ 4

f_S/ 2

f_S/ 8

f_S/ 4

图7-12. Mixing and Filtering in Mode 5

表7-6. Filter Specification Details, Mode 5

CORNERS

–0.1 dB

–0.5 dB

–1 dB

LOW PASS

0.102 × f_S

0.105 × f_S

0.108 × f_S

0.113 × f_S

–3 dB

20

0

0.5

0

-20

-40

-60

-80

-100

-120

-0.5

-1

-1.5

-2

-2.5

-3

0

0.05

0.1 0.15

Frequency Response

0.2

0.25

0

0.05

0.1 0.15

Frequency Response

0.2

0.25

D050

D051

图7-13. Frequency Response for Decimate-by-2,

图7-14. Zoomed View of Frequency Response

Low-Pass Filter (In Mode 5)

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7.4.6 Mode 6, Decimation-by-4 with IQ Outputs for up to 110 MHz of IQ Bandwidth

In this configuration, the DDC block includes a selectable N × f_S/ 16 complex digital mixer (n from –8 to +7)

preceding the decimation-by-4 digital filter, so the IQ passband is approximately ±55 MHz (3 dB) centered at N ×

f_S/ 16. A positive value for N inverts the spectrum. 图 7-15 shows the filtering operation in DDC mode 6. 表 7-7

shows corner frequencies of decimation filter in DDC mode 6. The decimation-by-4 filter is a cascade of two

decimation-by-2 filters with frequency response shown in 图7-16 and 图7-17.

The stop-band attenuation is approximately 90 dB for in-band aliases from negative frequencies and

approximately 55 dB for out-of-band aliases. The pass-band flatness is ±0.1 dB.

N x f_S/ 16

IQ:

500 MSPS

IQ:

250 MSPS

IQ:

125 MSPS

500 MSPS

14-Bit

ADC

2x

Example:

N = -6

3 f_S/ 8

f_S/ 4

f_S/ 2

f_S/ 8

f_S/ 4

图7-15. Mixing and Filtering in Mode 6

表7-7. Filter Specification Details, Mode 6

CORNERS

–0.1 dB

–0.5 dB

–1 dB

LOW PASS

0.102 × f_S

0.105 × f_S

0.108 × f_S

0.113 × f_S

–3 dB

20

0

0.5

0

-20

-40

-60

-80

-100

-120

-0.5

-1

-1.5

-2

-2.5

-3

0

0.05

0.1 0.15

Frequency Response

0.2

0.25

0

0.05

0.1 0.15

Frequency Response

0.2

0.25

D050

D051

图7-16. Frequency Response for Decimate-by-2,

图7-17. Zoomed View of Frequency Response

Low-Pass Filter (in Mode 6)

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7.4.7 Overrange Indication

The ADS54J66 provides a fast overrange indication (FOVR) that can be presented in the digital output data

stream via SPI configuration. When the FOVR indication is embedded in the output data stream, it replaces the

LSB (normal 0) of the 16 bit going to the 8b/10b encoder as shown in 图7-18.

14-Bit Data Output

0,

OVR

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

16-Bit Data Going Into 8b/10b Encoder

图7-18. Timing Diagram for FOVR

The fast OVR is triggered if the input voltage exceeds the programmable overrange threshold and it gets

presented after just 44 input clock cycles enabling a quicker reaction to an overrange event.

The input voltage level at which the overload is detected is referred to as the threshold. It is programmable using

the FOVR THRESHOLD bits.

备注

These register bits set the OVR threshold for all channels.

The input voltage level that fast OVR is triggered is:

Full-scale × [the decimal value of the FOVR threshold bits] / 255)

The default threshold is E3h (227), corresponding to a threshold of –1 dBFS.

In terms of full-scale input, the fast OVR threshold can be calculated as shown in 方程式1:

20 × log (<FOVR Threshold> / 255).

(1)

表7-8 is an example register write to set the FOVR threshold for all four channels.

表7-8. Register Sequence for FOVR Configuration

ADDRESS

DATA

COMMENT

11h

80h

Go to master page

59h

20h

Set the ALWAYS WRITE 1 bit. This bit configures the

OVR signal as fast OVR.

11h

0Fh

FFh

68h

00h

01h

03h

01h

00h

Go to ADC page

5Fh

Set FOVR threshold for all channels to 255

4004h

4003h

60ABh

70ABh

60ADh

70ADh

6000h

7000h

6000h

7000h

Go to main digital page of the JESD bank

Enable bit D0 overwrite

Select FOVR to replace bit D0

Pulse the IL RESET register bit. Register writes in

main digital page take effect when the IL RESET

register bit is pulsed.

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7.4.8 Power-Down Mode

The ADS54J66 provides a highly-configurable power-down mode. Power-down can be enabled using the PDN

pin or SPI register writes.

A power-down mask can be configured that allows a trade-off between wake-up time and power consumption in

power-down mode. Two independent power-down masks can be configured: MASK 1 and MASK 2, as shown in

表7-9. See the master page registers in 表7-15 for further details.

表7-9. Register Address for Power-Down Modes

REGISTER

ADDRESS

A[7:0] (Hex)

REGISTER DATA

COMMENT

7

6

5

4

3

2

1

0

MASTER PAGE (80h)

20

PDN ADC CHAB

PDN ADC CHCD

MASK 1

21

23

24

PDN BUFFER CHCD

PDN BUFFER CHAB

0

PDN ADC CHAB

PDN ADC CHCD

MASK 2

CONFIG

PDN BUFFER CHCD

PDN BUFFER CHAB

0

OVERRIDE

PDN MASK

26

GLOBAL PDN

0

PDN PIN

SEL

MASK

SYSREF

53

55

0

PDN MASK

To save power, the device can be put in complete power down by using the GLOBAL PDN register bit. However,

when JESD link must remain up when putting the device in power down, the ADC and analog buffer can be

powered down by using the PDN ADC CHx and PDN BUFFER CHx register bits after enabling the PDN MASK

register bit. The PDN MASK SEL register bit can be used to select between MASK 1 or MASK 2. 表 7-10 shows

power consumption for different combinations of the GLOBAL PDN, PDN ADC CHx, and PDN BUFF CHx

register bits.

表7-10. Power Consumption in Different Power-Down Settings

TOTAL

IAVDD3V

(mA)

IAVDD

(mA)

IDVDD

(mA)

IIOVDD

(mA)

POWER

(W)

REGISTER BIT

Default

COMMENT

After reset, with a full-scale input signal to

both channels

0.340

0.002

0.365

0.006

0.184

0.012

0.533

0.181

2.675

0.247

The device is in complete power-down

state

GBL PDN = 1

GBL PDN = 0,

PDN ADC CHx = 1

(x = AB or CD)

The ADCs of one pair of channels are

powered down

0.277

0.266

0.225

0.361

0.123

0.187

0.496

0.527

2.063

2.445

GBL PDN = 0,

PDN BUFF CHx = 1

(x = AB or CD)

The input buffers of one pair of channels

are powered down

GBL PDN = 0,

PDN ADC CHx = 1, PDN The ADCs and input buffers of one pair of

0.200

0.060

0.224

0.080

0.126

0.060

0.492

0.448

1.830

0.960

BUFF CHx = 1

(x = AB or CD)

channels are powered down

GBL PDN = 0,

PDN ADC CHx = 1, PDN The ADCs and input buffers of all channels

BUFF CHx = 1

are powered down

(x = AB and CD)

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7.5 Programming

7.5.1 Device Configuration

The ADS54J66 can be configured using a serial programming interface, as described in this section. In addition,

the device has one dedicated parallel pin (PDN) for controlling the power-down modes. The ADS54J66 supports

a 24-bit (16-bit address, 8-bit data) SPI operation and uses paging (see the 节 7.6.1 section) to access all

register bits. 图 7-19 shows timing diagram for serial interface signals. SPI registers are grouped in two banks

with each bank containing different pages (see 图7-34).

First 4 MSBs of 16-bit address are special bits carrying information about register bank, page and channel to be

programmed. 表7-11 lists the purpose of each special bit.

Register Address[11:0]

Register Data[7:0]

SDIN

R/W

M

P

CH

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

t_DH

D0

t_SCLK

t_DSU

SCLK

SEN

t_SLOADS

t_SLOADH

RESET

图7-19. Serial Interface Timing Diagram

表7-11. Programing Details of Serial Interface

SPI BITS

DESCRIPTION

OPTIONS

0 = SPI write

1 = SPI read back

R/W

M

Read/write bit

0 = Analog SPI bank (master and ADC page)

1 = Digital SPI bank (main digital, analog JESD, and

digital JESD pages)

SPI bank access

JESD page selection bit

0 = Page access

1 = Register access

P

0 = Channel AB

1 = Channel CD

By default, both channels are being addressed.

SPI access for a specific channel of the digital SPI

bank

CH

ADDR [11:0]

DATA [7:0]

SPI address bits

SPI data bits

—

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7.5.1.1 Details of the Serial Interface

The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial

interface enable), SCLK (serial interface clock) and SDIN (serial interface data) pins. Serially shifting bits into the

device is enabled when SEN is low. Serial data on SDIN are latched at every SCLK rising edge when SEN is

active (low). The interface can function with SCLK frequencies from 5 MHz down to very low speeds (of a few

hertz) and also with a non-50% SCLK duty cycle.

图7-24 shows timing requirements for serial interface signals.

表7-12. Serial Interface Timing Requirements⁽¹⁾

MIN

> dc

25

MAX

UNIT

MHz

ns

f_SCLK

t_SLOADS

t_SLOADH

t_DSU

SCLK frequency (equal to 1 / t_SCLK

SEN to SCLK setup time

SCLK to SEN hold time

SDATA setup time

)

20

25

ns

25

ns

t_DH

SDATA hold time

25

ns

(1) Typical values are at 25°C. Minimum and maximum values are across the full temperature range of T_MIN= –40°C to T_MAX= 100°C,

AVDD3V = 3 V, AVDD = 1.9 V, and DRVDD = 1.8 V, unless otherwise noted.

7.5.1.2 Serial Register Write: Analog Bank

The analog SPI bank contains of two pages (the master and ADC page). The internal register of the ADS54J66

analog SPI bank can be programmed by:

1. Drive the SEN pin low.

2. Initiate a serial interface cycle specifying the page address of the register whose content must be written.

• Master page: write address 0011h with 80h.

• ADC page: write address 0011h with 0Fh.

3. Write the register content as shown in 图7-20. When a page is selected, multiple writes into the same page

can be done.

Register Address[11:0]

Register Data[7:0]

0

SDIN

SCLK

R/W

M

P

CH A11 A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

SEN

RESET

图7-20. Serial Register Write Timing Diagram

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7.5.1.3 Serial Register Readout: Analog Bank

The content from one of the two analog banks can be read out by:

1. Drive the SEN pin low.

2. Select the page address of the register whose content must be read.

• Master page: write address 0011h with 80h.

• ADC page: write address 0011h with 0Fh.

3. Set the R/W bit to 1 and write the address to be read back.

4. Read back the register content on the SDOUT pin, as shown in 图7-21. When a page is selected, multiple

read backs from the same page can be done.

Register Address[11:0]

Register Data[7:0] = XX

1

0

SDIN

SCLK

R/W

M

P

CH

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

SEN

RESET

SDOUT

D7

D6

D5

D4

D3

D2

D1

D0

SDOUT[7:0]

图7-21. Serial Register Read Timing Diagram

7.5.1.4 JESD Bank SPI Page Selection

The JESD SPI bank contains five pages (main digital, interleaving engine, decimation filter, JESD digital, and

JESD analog). The individual pages can be selected following these steps:

1. Drive the SEN pin low.

2. Set the M bit to 1 and specify the page with two register writes (Note: the P bit is set to 0)

• Write address 4003h with 00h (LSB byte of the page address)

• Write address 4004h MSB byte of the page address

spacer

• Main digital page: write address = 4004h with 68h (default)

• Digital JESD page: write address = 4004h with 69h

• Analog JESD page: write address = 4004h with 6Ah

• Interleaving engine page: write address = 4004h with 61h

• Decimation filter page: write address = 4004h with 61h and 4003h with 41h

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图 7-22 shows the serial interface signals when pages in the JESD bank are being accessed. Note that the P bit

is set to 0.

Register Address[11:0]

Register Data[7:0]

0

1

0

SDIN

SCLK

R/W

M

P

CH A11 A10 A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

SEN

RESET

图7-22. SPI Timing Diagram for Accessing a Page in the JESD Bank

7.5.1.5 Serial Register Write: Digital Bank

The ADS54J66 is a quad-channel device and the JESD204B portion is configured individually for two channels

(A, B and C, D) using the CH bit. Note that the P bit must be set to 1 for register writes.

1. Drive the SEN pin low.

2. Select the JESD bank page (Note: M bit = 1, P bit = 0)

• Write address 4003h with 00h

• Main digital page: write address = 4004h with 68h (default)

• Digital JESD page: write address = 4004h with 69h

• Analog JESD page: write address = 4004h with 6Ah

• Interleaving Engine page: write address = 4004h with 61h

• Decimation Filter page: write address = 4004h with 61h and 4003h with 41h

3. Set the M and P bit to 1 and select channels A, B (CH = 0) or C, D (CH = 1) and write the register content.

When a page is selected, multiple writes into the same page can be done.

By default, register writes are applied to both channel pairs (broadcast mode). To disable broadcast mode

and enable individual channel writes, write address 4005h with 01h (default is 00h).

图 7-23 shows the serial interface signals when a register in the desired page of the JESD bank is programmed

(note that the P bit must be set to 1 in this step).

Register Address[11:0]

Register Data[7:0]

0

1

0

SDIN

SCLK

R/W

M

P

CH A11 A10 A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

SEN

RESET

图7-23. SPI Timing Diagram for Writing a Register in the JESD Bank (After Page is Accessed)

7.5.1.6 Individual Channel Programming

By default, register writes are applied to both channels in a group (for example, the register writes are applied to

channels A and B if the CH bit is 0, or the register writes are applied to channels C and D if the CH bit is 1). This

form of programming is referred to as broadcast mode.

For pages located in the JESD bank, the device gives flexibility to program each channel individually. To enable

individual channel writes, write address 4005h with 01h (default is 00h).

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7.5.1.7 Serial Register Readout: JESD Bank

SPI read out of content in one of the three digital banks can be accomplished with the following steps:

1. Drive the SEN pin low.

2. Select the digital bank page (Note: M bit = 1, P bit = 0)

• Write address 4003h with 00h

• Main digital page: write address = 4004h with 68h

• Digital JESD page: write address = 4004h with 69h

• Analog JESD page: write address = 4004h with 6Ah

• Interleaving engine page: write address = 4004h with 61h

• Decimation filter page: write address = 4004h with 61h and 4003h with 41h

3. Set the R/W bit, M and P bit to 1 and select channels A, B or C, D and write the address to be read back.

4. Read back register content on the SDOUT pin. When a page is selected, multiple read backs from the same

page can be done.

图 7-24 shows the serial interface signals when the contents of a register in the desired page of the JESD bank

are being read-back (note that the P bit must be set to 1 in this step).

Register Address[11:0]

Register Data[7:0] = XX

1

0

SDIN

SCLK

R/W

M

P

CH A11 A10 A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

SEN

RESET

SDOUT

D7

D6

D5

D4

D3

D2

D1

D0

SDOUT[7:0]

图7-24. Serial Register Read Timing Diagram

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7.5.2 JESD204B Interface

The ADS54J66 supports device subclass 1 with a maximum output data rate of 10 Gbps for each serial

transmitter. 图7-25 shows JESD20B block inside ADS54J66.

An external SYSREF signal is used to align all internal clock phases and the local multi frame clock to a specific

sampling clock edge. This process allows synchronization of multiple devices in a system and minimizes timing

and alignment uncertainty. The ADS54J66 supports single (for all four JESD links) or dual (for channel A, B and

C, D) SYNCb inputs and can be configured via SPI as shown in 图7-26.

JESD204B Block

Transport Layer

Link Layer

Frame Data

Mapping

8b/10b

Encoding

Scrambler

1+x¹⁴+x¹⁵

DX

Comma Characters

Initial Lane Alignment

Test Patterns

SYNCb

图7-25. JESD Interface Block Diagram

SYSREF

SYNCbAB

JESD

204B

JESD204B

DA

INA

INB

INC

IND

JESD

204B

JESD204B

DB

JESD

204B

JESD204B

DC

JESD

204B

JESD204B

DD

Sample Clock SYNCbCD

图7-26. JESD204B Transmitter Block

Depending on the ADC sampling rate, the JESD204B output interface can be operated with one lane per

channel. The JESD204B setup and configuration of the frame assembly parameters is controlled through the

SPI interface.

The JESD204B transmitter block consists of the transport layer, the data scrambler and the link layer. The

transport layer maps the ADC output data into the selected JESD204B frame data format and manages if the

ADC output data or test patterns are being transmitted. The link layer performs the 8b/10b data encoding as well

as the synchronization and initial lane alignment using the SYNC input signal. Optionally, data from the transport

layer can be scrambled.

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7.5.2.1 JESD204B Initial Lane Alignment (ILA)

The initial lane alignment process is started by the receiving device by de-asserting the SYNCb signal. Upon

detecting a logic low on the SYNC input pins, the ADS54J66 starts transmitting comma (K28.5) characters to

establish code group synchronization as shown in 图7-27.

When synchronization is completed the receiving device re-asserts the SYNCb signal and the ADS54J66 starts

the initial lane alignment sequence with the next local multi frame clock boundary. The ADS54J66 transmits four

multi-frames each containing K frames (K is SPI programmable). Each of the multi-frames contains the frame

start and end symbols and the second multi-frame also contains the JESD204 link configuration data.

SYSREF

LMFC Clock

LMFC Boundary

Multi

Frame

SYNCb

Transmit Data

xxx

K28.5

ILA

DATA

Code Group

Synchronization

Initial Lane Alignment

Data Transmission

图7-27. ILA Sequence

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7.5.2.2 JESD204B Frame Assembly

The JESD204B standard defines the following parameters:

• L is the number of lanes per link.

• M is the number of converters per device.

• F is the number of octets per frame clock period.

• S is the number of samples per frame.

表 7-13 lists the available JESD204B formats and valid ranges for the ADS54J66. The ranges are limited by the

Serdes line rate and the maximum ADC sample frequency.

表7-13. Available JESD204B Formats and Valid Ranges for the ADS54J66

MAX ADC

OUTPUT

RATE (MSPS)

OPERATING

MODE

OUTPUT

FORMAT

JESD

JESD PLL

MODE⁽²⁾

MAX f_SERDES

(Gbps)

L

M

F

S

DIGITAL MODE

MODE⁽¹⁾

4

2

4

8

4

8

4

2

4

1

0,5

2,4

6

2x decimation

4x decimation

Complex

Real

40x

20x

40x

20x

40x

20x

250

125

10.0

5.0

Real

10.0

5.0

Complex

2x decimation with 0-

4

2

1

7

8

Real

20x

40x

500

10.0

pad

No decimation

(1) In register 01h of the JESD digital page.

(2) In register 16h of the JESD analog page.

The detailed frame assembly is shown in 表7-14.

表7-14. Detailed Frame Assembly

LMFS = 4841

LMFS = 4421

LMFS = 4421 (0-Pad)

DA

DB

DC

DD

0000

A0[7:0]

0000

AI0[15:8] AI0[7:0] AQ0[15:8] AQ0[7:0]

BI0[15:8] BI0[7:0] BQ0[15:8] BQ0[7:0]

CI0[15:8] CI0[7:0] CQ0[15:8] CQ0[7:0]

DI0[15:8] DI0[7:0] DQ0[15:8] DQ0[7:0]

A0[15:8]

B0[15:8]

C0[15:8]

D0[15:8]

A0[7:0]

B0[7:0]

C0[7:0]

D0[7:0]

A1[15:8]

B1[15:8]

C1[15:8]

D1[15:8]

A1[7:0]

B1[7:0]

C1[7:0]

D1[7:0]

A0[15:8]

B0[15:8]

C0[15:8]

D0[15:8]

0000

B0[7:0]

0000

C0[7:0]

0000

D0[7:0]

0000

LMFS = 2441

DB

DC

A0[15:8]

C0[15:8]

A0[7:0]

C0[7:0]

B0[15:8]

D0[15:8]

B0[7:0]

D0[7:0]

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7.5.2.3 JESD Output Switch

The ADS54J66 provides a digital cross point switch in the JESD204B block which allows internal routing of any

output of the two ADCs within one channel pair to any of the two JESD204B serial transmitters in order to ease

layout constraints. The cross-point switch routing is configured via SPI (address 21h in the JESD digital page, as

shown in 图7-28).

JESD Switch

DAP,

ADCA

DAM

DBP,

ADCB

DBM

JESD Switch

DCP,

ADCC

DCM

DDP,

ADCD

DDM

图7-28. Switching the Output Lanes

7.5.2.3.1 SERDES Transmitter Interface

Each of the 10 Gbps serdes transmitter outputs requires ac coupling between transmitter and receiver. The

differential pair must be terminated with 100 Ω as close to the receiving device as possible to avoid unwanted

reflections and signal degradation as shown in 图7-29.

0.1 mF

DAP, DAB,

DAC, DAP

R_t= Z_O

Transmission Line,

VCM

Receiver

Zo

R_t= Z_O

DAM, DAB,

DAC, DAM

0.1 mF

图7-29. SERDES Transmitter Connection to Receiver

7.5.2.3.2 SYNCb Interface

The ADS54J66 supports single (either SYNCb input controls all four JESD204B links) or dual (one SYNCb input

controls two JESD204B lanes (DA, DB and DC, DD) SYNCb control. When using single SYNCb control, connect

the unused input to differential logic low (SYNCbxxP = 0 V, SYNCbxxM = IOVDD).

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7.5.2.3.3 Eye Diagram

图 7-30 to 图 7-33 show the serial output eye diagrams of the ADS54J66 at 5 Gbps and 10 Gbps with default

and increased output voltage swing against the JESD204B mask.

图7-30. Eye at 5-Gbps Bit Rate with Default Output

图7-31. Eye at 5-Gbps Bit Rate with Increased

Swing

Output Swing

图7-33. Eye at 10-Gbps Bit Rate with Increased

图7-32. Eye at 10-Gbps Bit Rate with Default

Output Swing

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7.6.1 Detailed Register Information

The ADS54J66 contains two main SPI banks. The analog SPI bank gives access to the ADC cores and the

digital SPI bank controls the serial interface. The analog SPI bank is divided into two pages (master and ADC)

and the digital SPI bank is divided into five pages (main digital, interleaving engine, decimation filter, JESD

digital, and JESD analog; see 图 7-34). 表 7-15 gives a summary of all programmable registers in the pages of

different banks in the ADS54J66.

表7-15. Register Map

REGISTER

ADDRESS

A[7:0] (Hex)

REGISTER DATA

7

6

5

4

3

2

1

0

GENERAL REGISTERS

0

RESET

0

RESET

3

JESD BANK PAGE SEL [7:0]

JESD BANK PAGE SEL [15:8]

4

5

0

DIS BROADCAST

11

ANALOG PAGE SELECTION [7:0]

MASTER PAGE (80h)

20

21

23

24

PDN ADC CHAB

PDN ADC CHCD

PDN BUFFER CHCD

PDN BUFFER CHAB

0

26

GLOBAL PDN

OVERRIDE PDN

PDN MASK SEL

0

3A

0

BUFFER CURR

INCREASE

0

39

53

54

ALWAYS WRITE 1

0

CLK DIV

MASK SYSREF

0

SET SYSREF

0

ENABLE

MANUAL

SYSREF

55

56

0

PDN MASK

0

INPUT BUFF

CURR EN

59

0

ALWAYS WRITE 1

0

ADC PAGE (0Fh)

5F

60

61

6C

6D

74

75

76

77

78

FOVR THRESH

PULSE BIT CHC

0

HD3 NYQ2 CHCD

PULSE BIT CHD

PULSE BIT CHA

0

HD3 NYQ2 CHAB

0

PULSE BIT CHB

0

TEST PATTERN ON CHANNEL

CUSTOM PATTERN 1 [13:6]

CUSTOM PATTERN 1 [5:0]

CUSTOM PATTERN 2 [13:6]

CUSTOM PATTERN 2 [5:0]

0

INTERLEAVING ENGINE PAGE (6100h)

18

68

0

IL BYPASS

0

DC CORR DIS

DDC MODE

0

DECIMATION FILTER PAGE (6141h)

0

CHB/C FINE MIX

CHB/C COARSE

MIX

1

2

0

DDC MODE6 EN1 ALWAYS WRITE 1 CHB/C HPF EN

CHA/D FINE MIX

CHA/D COARSE

MIX

CHA/D HPF EN

MAIN DIGITAL PAGE (6800h)

0

IL RESET

0

42

NYQUIST ZONE

CTRL NYQUIST

ZONE

4E

0

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表7-15. Register Map (continued)

REGISTER

ADDRESS

A[7:0] (Hex)

REGISTER DATA

7

6

5

4

3

2

1

0

AB

F7

0

OVR EN

DIG RESET

JESD DIGITAL PAGE (6900h)

0

1

CTRL K

JESD MODE EN DDC MODE6 EN2 TESTMODE EN

SYNCB SEL

0

LANE ALIGN

0

FRAME ALIGN

TX LINK DIS

SYNC REG

SYNC REG EN

0

DDC MODE6 EN3

JESD MODE

AB/CD

LINK LAYER

RPAT

LMFC MASK

RESET

2

3

LINK LAYER TESTMODE

0

FORCE LMFC

COUNT

LMFC COUNT INIT

0

RELEASE ILANE SEQ

5

6

SCRAMBLE EN

0

FRAMES PER MULTI FRAME (K)

OUTPUT CHC MUX SEL

21

22

OUPUT CHA MUX SEL

OUTPUT CHB MUX SEL

OUTPUT CHD MUX SEL

0

OUT CHA INV

OUT CHB INV

OUT CHC INV

OUT CHD INV

JESD ANALOG PAGE (6A00h)

12

13

SEL EMP LANE A/D

SEL EMP LANE B/C

0

16

17

1B

0

JESD PLL MODE

PLL RESET

JESD SWING

0

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7.6.2 Example Register Writes

Global power down:

ADDRESS

11h

DATA

COMMENT

80h

C0h

Set master page

0026h

Set global power down

Change decimation mode 0 to mode 4 adjusting both the LMFS configuration (LMFS = 4841 to 4421) as well as

serial output data rate (10 Gbps to 5 Gbps):

ADDRESS

4004h

4003h

6000h

6001h

4004h

6016h

4004h

4003h

6000h

DATA

69h

00h

40h

01h

6Ah

00h

61h

41h

CCh

COMMENT

Select digital JESD page

Enables JESD mode overwrite

Select digital to 20x mode

Select analog JESD page

Set serdes PLL to 20x mode

Select decimation filter page

Select mode 4

Digital mixer for channel AB set to –4 (f_S/ 4)

Digital mixer for channel CD set to –4 (f_S/ 4)

6002h

0Ch

表7-16 lists the access codes for the ADS54J66 registers.

表7-16. ADS54J66 Access Type Codes

Access Type

Code

Description

Read Type

R

Read

RW

R-W

Read or write

Write Type

W

Write

Reset or Default Value

-n

Value after reset or the default value

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7.6.3 Register Descriptions

7.6.3.1 General Registers

7.6.3.1.1 Register 0h (offset = 0h) [reset = 0h]

图7-35. Register 0h

7

6

0

5

0

4

3

2

0

1

0

RESET

R/W-0h

0

RESET

R/W-0h

W-0h

表7-17. Register 0h Field Description

Bit

Name

Type

Reset

Description

7⁽¹⁾

RESET

R/W

0h

0 = Normal operation

1 = Internal software reset, clears back to 0

6-0

0⁽¹⁾

0

W

0h

Must write 0.

RESET

R/W

0 = Normal operation

1 = Internal software reset, clears back to 0

(1) Both bits (7, 0) must be set simultaneously to exercise reset.

7.6.3.1.2 Register 3h, 4h (offset = 3h, 4h) [reset = 0h]

图7-36. Register 3h

7

6

5

4

3

2

1

0

JESD BANK PAGE SEL [7:0]

R/W-0h

图7-37. Register 4h

4

3

JESD BANK PAGE SEL [16:8]

R/W-0h

表7-18. Register 3h, 4h Field Description

Bit

Name

JESD BANK PAGE SEL

Type

Reset

Description

7-0

R/W

0h

Program these bits to access the desired page in the JESD bank.

6100h = Interleaving engine page selected

6141h = Decimation filter page selected

6800h = Main digital page selected

6900h = JESD digital page selected

6A00h = JESD analog page selected

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7.6.3.1.3 Register 5h (offset = 5h) [reset = 0h]

图7-38. Register 5h

7

0

6

0

5

0

4

0

3

2

0

1

0

DIS BROADCAST

R/W-0h

W-0h

表7-19. Register 5h Field Description

Bit

7-1

0

Name

Type

Reset

Description

0

W

0h

Must write 0.

DIS BROADCAST

R/W

0h

0 = Normal operation. Channel A and B are programmed as a pair. Channel

C and D are programmed as a pair.

1 = channel A and B can be individually programmed based on the CH bit.

Similarly channel C and D can be individually programmed based on the CH

bit.

7.6.3.1.4 Register 11h (offset = 11h) [reset = 0h]

图7-39. Register 11h

7

6

5

4

3

2

1

0

ANALOG PAGE SELECTION [7:0]

R/W-0h

表7-20. Register 11h Field Descriptions

Bit

Name

Type

Reset

Description

7-0

ANALOG PAGE SELECTION [7:0]

R/W

0h

Register page (only one page at a time can be addressed).

Master page = 80h

ADC page = 0Fh

The five digital pages (main digital, interleaving engine, analog

JESD, digital JESD, and decimation filter) are selected via the

M bit. See 表7-11 in the 节7.5.1.1 section for more details.

7.6.3.2 Master Page (80h)

7.6.3.2.1 Register 20h (address = 20h) [reset = 0h], Master Page (080h)

图7-40. Register 20h

7

6

5

4

3

2

1

0

PDN ADC CHAB

R/W-0h

PDN ADC CHCD

R/W-0h

表7-21. Registers 20h Field Descriptions

Bit

7-4

3-0

Field

Type

R/W

Reset

Description

PDN ADC CHAB

PDN ADC CHCD

0h

There are two power-down masks that are controlled via the

PDN mask register bit in address 55h. The power-down mask 1

or mask 2 are selected via register bit 5 in address 26h.

Power-down mask 1: addresses 20h and 21h.

0h

Power-down mask 2: addresses 23h and 24h.

See the 节7.4.8 section for details.

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7.6.3.2.2 Register 21h (address = 21h) [reset = 0h], Master Page (080h)

图7-41. Register 21h

7

6

5

4

3

2

0

1

0

PDN BUFFER CHCD

R/W-0h

PDN BUFFER CHAB

R/W-0h

0

W-0h

R/W-0h

W-0h

表7-22. Register 21h Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7-6

5-4

PDN BUFFER CHCD

PDN BUFFER CHAB

0h

There are two power-down masks that are controlled via the

PDN mask register bit in address 55h. The power-down mask 1

or mask 2 are selected via register address 26h, bit 5.

Power-down mask 1: addresses 20h and 21h.

0h

Power-down mask 2: addresses 23h and 24h.

See the 节7.4.8 section for details.

3-0

0

W

0h

Must write 0.

7.6.3.2.3 Register 23h (address = 23h), Master Page (080h)

图7-42. Register 23h

7

6

5

4

3

2

1

0

PDN ADC CHAB

R/W-0h

PDN ADC CHCD

W-0h

R/W-0h

W-0h

表7-23. Register 23h Field Descriptions

Bit

7-4

3-0

Field

Type

R/W

Reset

Description

PDN ADC CHAB

PDN ADC CHCD

0h

There are two power-down masks that are controlled via the

PDN mask register bit in address 55h. The power-down mask 1

or mask 2 are selected via register bit 5 in address 26h.

Power-down mask 1: addresses 20h and 21h.

0h

Power-down mask 2: addresses 23h and 24h.

See the 节7.4.8 section for details.

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7.6.3.2.4 Register 24h (address = 24h) [reset = 0h], Master Page (080h)

图7-43. Register 24h

7

6

5

4

3

2

0

1

0

PDN BUFFER CHCD

R/W-0h

PDN BUFFER CHAB

R/W-0h

0

W-0h

R/W-0h

表7-24. Register 24h Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7-6

5-4

PDN BUFFER CHCD

PDN BUFFER CHAB

0h

There are two power-down masks that are controlled via the

PDN mask register bit in address 55h. The power-down mask 1

or mask 2 are selected via register address 26h, bit 5.

Power-down mask 1: addresses 20h and 21h.

0h

Power-down mask 2: addresses 23h and 24h.

See the 节7.4.8 section for details.

3-0

0

W

0h

Must write 0.

7.6.3.2.5 Register 26h (address = 26h), Master Page (080h)

表7-25. Register 26h

7

6

5

4

3

0

2

0

1

0

GLOBAL PDN

R/W-0h

OVERRIDE PDN PIN

R/W-0h

PDN MASK SEL

R/W-0h

0

R/W-0h

表7-26. Register 26h Field Descriptions

Bit

Field

Type

Reset

Description

7

GLOBAL PDN

R/W

0h

Bit 6 (OVERRIDE PDN PIN) must be set before this bit can be

programmed.

0 = Normal operation

1 = Global power-down via the SPI

6

5

OVERRIDE PDN PIN

R/W

0h

This bit ignores the power-down pin control.

0 = Normal operation

1 = Ignores inputs on the power-down pin

PDN MASK SEL

0

This bit selects power-down mask 1 or mask 2.

0 = Power-down mask 1

1 = Power-down mask 2

4-0

Must write 0

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7.6.3.2.6 Register 3Ah (address = 3Ah) [reset = 0h], Master Page (80h)

图7-44. Register 3Ah

7

0

6

5

0

4

3

0

2

0

1

0

BUFFER CURR INCREASE

R/W-0h

0

W-0h

表7-27. Register 3Ah Field Descriptions

Bit

Name

Type

Reset

Description

7

6

0

W

0h

Must write 0.

BUFFER CURR INCREASE

R/W

0h

0 = Normal operation

1 = Increases AVDD3V current by 30 mA., improves HD3, helpful for

second and third Nyquist application. Make sure that the INPUT BUF

CUR EN regiser bit is also set to 1.

5-0

0

W

0h

Must write 0.

7.6.3.2.7 Register 39h (address = 39h) [reset = 0h], Master Page (80h)

图7-45. Register 39h

7

6

5

0

4

3

2

0

1

0

ALWAYS WRITE 1

R/W-0h

0

W-0h

表7-28. Register 39h Field Descriptions

Bit

7-6

5-0

Name

Type

R/W

W

Reset

Description

ALWAYS WRITE 1

0h

Always set these bits to 11.

Must write 0.

0

0h

7.6.3.2.8 Register 53h (address = 53h) [reset = 0h], Master Page (80h)

图7-46. Register 53h Register

7

6

5

4

3

2

0

1

0

CLK DIV

R/W-0h

MASK SYSREF

R/W-0h

0

SET SYSREF

W-0h

表7-29. Register 53h Field Descriptions

Bit

Name

Type

Reset

Description

7

CLK DIV

R/W

0h

This bit configures the input clock divider.

0 = Divide-by-4

1 = Divide-by-2 (must be enabled for proper operation of the ADS54J66)

6

MASK SYSREF

R/W

0h

0 = Normal operation

1 = Ignores the SYSREF input

5-1

0

W

0h

Must write 0.

SET SYSREF

R/W

0 = SYSREF signal inside device is set as 0

1 = SYSREF signal inside device is set as 1

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7.6.3.2.9 Register 54h (address = 54h) [reset = 0h], Master Page (80h)

图7-47. Register 54h Register

7

6

0

5

4

3

2

0

1

0

ENABLE MANUAL

SYSREF

0

R/W-0h

W-0h

表7-30. Register 54h Field Descriptions

Bit

Name

Type

Reset

Description

7

ENABLE MANUAL

SYSREF

R/W

0h

This bit enables manual SYSREF using SPI when disabling the pin control.

After setting this bit, the SET SYSREF register bit can be used to apply

SYSREF.

6-1

0

W

0h

Must write 0.

7.6.3.2.10 Register 55h (address = 55h) [reset = 0h], Master Page (80h)

图7-48. Register 55h

7

0

6

0

5

0

4

3

2

0

1

0

PDN MASK

R/W-0h

0

W-0h

表7-31. Register 55h Field Descriptions

Bit

Name

Type

Reset

Description

7-5

4

0

W

0h

Must write 0.

PDN MASK

R/W

0h

Power-down via register bit.

0 = Normal operation

1 = Power down enabled powering down internal blocks specified in the

selected power-down mask

3-0

0

W

0h

Must write 0.

7.6.3.2.11 Register 56h (address = 56h) [reset = 0h], Master Page (80h)

图7-49. Register 56h

7

0

6

0

5

0

4

0

3

2

0

1

0

INPUT BUFF CURR EN

R/W-0h

W-0h

表7-32. Register 56h Field Descriptions

Bit

7-4

3

Name

Type

Reset

Description

0

W

0h

Must write 0.

INPUT BUFF CURR EN R/W

0h

0 = Normal operation

1 = Increases AVDD3V current by 30 mA., improves HD3, helpful for

second Nyquist application. Make sure that the BUFFER CURR

INCREASE register bit is also set to 1.

2-0

0

W

0h

Must write 0.

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7.6.3.2.12 Register 59h (address = 59h) [reset = 0h], Master Page (80h)

图7-50. Register 59h

7

0

6

0

5

4

3

0

2

0

1

0

ALWAYS WRITE 1

R/W-0h

0

W-0h

表7-33. Register 59h Field Descriptions

Bit

7-6

5

Name

Type

Reset

Description

0

W

0h

Must write 0.

ALWAYS WRITE 1

0

R/W

W

0h

Always set this bit to 1.

Must write 0.

4-0

0h

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7.6.3.3 ADC Page (0Fh)

7.6.3.3.1 Register 5Fh (address = 5Fh) [reset = 0h], ADC Page (0Fh)

图7-51. Register 5Fh

7

6

5

4

3

2

1

0

FOVR THRESH

R/W-0h

表7-34. Register 5Fh Field Descriptions

Bit

Name

FOVR THRESH

Type

Reset

Description

7-0

R/W

0h

These bits control the location of FAST OVR threshold for all four channels

together; see the 节7.4.7 section.

7.6.3.3.2 Register 60h (address = 60h) [reset = 0h], ADC Page (0Fh)

图7-52. Register 60h

7

6

0

5

0

4

3

0

2

0

1

0

PULSE BIT CHC

R/W-0h

0

W-0h

表7-35. Register 60h Field Descriptions

Bit

Name

Type

Reset

Description

7

PULSE BIT CHC

R/W

0h

Pulse this bit to improve HD3 for 2nd Nyquist frequencies (f_IN> 250 MHz) for

channel C.⁽¹⁾

Before pulsing this bit, the HD3 NYQ2 CHCD register bit must be set to 1.

6-0

0

W

0h

Must write 0.

(1) Pulsing = set the bit to 1 and then reset to 0.

7.6.3.3.3 Register 61h (address = 61h) [reset = 0h], ADC Page (0Fh)

图7-53. Register 61h

7

0

6

0

5

0

4

0

3

2

0

1

0

HD3 NYQ2 CHCD

R/W-0h

PULSE BIT CHD

R/W-0h

W-0h

表7-36. Register 61h Field Descriptions

Bit

7-4

3

Name

Type

Reset

Description

0

W

0h

Must write 0.

HD3 NYQ2 CHCD

R/W

0h

Set this bit to improve HD3 for 2nd Nyquist frequencies (f_IN> 250 MHz) for

channel C and D. When this bit is set, the PULSE BIT CHx register bits must

be pulsed to obtain the improvement in corresponding channels.

2-1

0

W

0h

Must write 0.

PULSE BIT CHD

R/W

Pulse this bit to improve HD3 for 2nd Nyquist frequencies (f_IN> 250 MHz) for

channel D.⁽¹⁾

Before pulsing this bit, the HD3 NYQ2 CHCD register bit must be set to 1.

(1) Pulsing = set the bit to 1 and then reset to 0.

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7.6.3.3.4 Register 6Ch (address = 6Ch) [reset = 0h], ADC Page (0Fh)

图7-54. Register 6Ch

7

6

0

5

0

4

3

0

2

0

1

0

PULSE BIT CHA

R/W-0h

0

W-0h

表7-37. Register 6Ch Field Descriptions

Bit

Name

Type

Reset

Description

7

PULSE BIT CHA

R/W

0h

Pulse this bit to improve HD3 for 2nd Nyquist frequencies (f_IN> 250 MHz) for

channel A.⁽¹⁾

Before pulsing this bit, the HD3 NYQ2 CHCAB register bit must be set to 1.

6-0

0

W

0h

Must write 0.

(1) Pulsing = set the bit to 1 and then reset to 0.

7.6.3.3.5 Register 6Dh (address = 6Dh) [reset = 0h], ADC Page (0Fh)

图7-55. Register 6Dh

7

0

6

0

5

0

4

0

3

2

0

1

0

HD3 NYQ2 CHAB

R/W-0h

PULSE BIT CHB

R/W-0h

W-0h

表7-38. Register 6Dh Field Descriptions

Bit

7-4

3

Name

Type

Reset

Description

0

W

0h

Must write 0.

HD3 NYQ2 CHAB

R/W

0h

Set this bit to improve HD3 for 2nd Nyquist frequencies (f_IN> 250 MHz) for

channel A and B. When this bit is set, the PULSE BIT CHx register bits must

be pulsed to obtain the improvement in corresponding channels.

2-1

0

W

0h

Must write 0.

PULSE BIT CHB

R/W

Pulse this bit to improve HD3 for 2nd Nyquist frequencies (f_IN> 250 MHz) for

channel B.⁽¹⁾

Before pulsing this bit, the HD3 NYQ2 CHAB register bit must be set to 1.

(1) Pulsing = set the bit to 1 and then reset to 0.

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7.6.3.3.6 Register 74h (address = 74h) [reset = 0h], ADC Page (0Fh)

表7-39. Register 74h

7

6

5

4

3

2

0

1

0

TEST PATTERN ON CHANNEL

R/W-0h

0

W-0h

表7-40. Register 74h Field Descriptions

Bit

Field

Type

Reset

Description

7-4

TEST PATTERN ON CHANNEL

R/W

0h

Test pattern output on channel A and B

0000 = Normal operation using ADC output data

0001 = Outputs all 0s

0010 = Outputs all 1s

0011 = Outputs toggle pattern: Output data are an alternating

sequence of 101010101010 and 010101010101

0100 = Output digital ramp: output data increment by one LSB

every clock cycle from code 0 to 16384

0110 = Single pattern: output data are custom pattern 1 (75h

and 76h)

0111 = Double pattern: output data alternate between custom

pattern 1 and custom pattern 2

1000 = Deskew pattern: output data are 2AAAh

1001 = SYNC pattern: output data are 7FFFh

See the 节8.1.6 section for more details.

To use the test patterns, the interleave engine must be in

bypass and the DC correction disabled (page 6100h

addresses 0x18 and 0x68) and the ADC must be in bypass

mode.

3-0

0

W

0h

Must write 0.

7.6.3.3.7 Register 75h (address = 75h) [reset = 0h], ADC Page (0Fh)

表7-41. Register 75h

7

6

5

4

3

2

1

0

CUSTOM PATTERN 1[13:6]

R/W-0h

表7-42. Register 75h Field Descriptions

Bit

Name

CUSTOM PATTERN

Type

Reset

Description

7-0

R/W

0h

These bits set the custom pattern (13-6) for all channels; see the 节8.1.6

section for more details.

7.6.3.3.8 Register 76h (address = 76h) [reset = 0h], ADC Page (0Fh)

表7-43. Register 76h

7

6

5

4

3

2

1

0

CUSTOM PATTERN 1[ 5:0]

R/W-0h

W-0h

表7-44. Register 76h Field Descriptions

Bit

Name

Type

Reset

Description

7-2

CUSTOM PATTERN

R/W

0h

These bits set the custom pattern (5-0) for all channels; see the 节8.1.6

section for more details.

1-0

0

W

0h

Must write 0.

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7.6.3.3.9 Register 77h (address = 77h) [reset = 0h], ADC Page (0Fh)

表7-45. Register 77h

7

6

5

4

3

2

1

0

CUSTOM PATTERN 2[13:6]

R/W-0h

表7-46. Register 77h Field Descriptions

Bit

Name

CUSTOM PATTERN

Type

Reset

Description

7-0

R/W

0h

These bits set the custom pattern (13-6) for all channels; see the 节8.1.6

section for more details.

7.6.3.3.10 Register 78h (address = 78h) [reset = 0h], ADC Page (0Fh)

表7-47. Register 78h

7

6

5

4

3

2

1

0

CUSTOM PATTERN 2[ 5:0]

R/W-0h

W-0h

表7-48. Register 78h Field Descriptions

Bit

Name

Type

Reset

Description

7-2

CUSTOM PATTERN

R/W

0h

These bits set the custom pattern (5-0) for all channels; see the 节8.1.6

section for more details.

1-0

0

W

0h

Must write 0.

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7.6.3.4 Interleaving Engine Page (6100h)

7.6.3.4.1 Register 18h (address = 18h) [reset = 0h], Interleaving Engine Page (6100h)

图7-56. Register 18h

7

0

6

0

5

0

4

3

2

0

1

0

IL BYPASS

R/W-0h

W-0h

表7-49. Register 18h Field Descriptions

Bit

Name

Type

Reset

Description

7-2

1-0

0

W

0h

Must write 0.

IL BYPASS

R/W

0h

These bits allow bypassing of the interleaving correction, which is to be

used when ADC test patterns are enabled.

00 = Interleaving correction enabled

11 = Interleaving correction bypassed

7.6.3.4.2 Register 68h (address = 68h) [reset = 0h], Interleaving Engine Page (6100h)

图7-57. Register 68h

7

0

6

0

5

0

4

3

2

1

0

DC CORR DIS

R/W-0h

W-0h

表7-50. Register 68h Field Descriptions

Bit

Name

Type

Reset

Description

7-3

2-1

0

W

0h

Must write 0.

DC CORR DIS

R/W

0h

These bits enable the dc offset correction loop.

00 = DC offset correction enabled

11 = DC offset correction disabled

Others = Do not use

0

W

0h

Must write 0.

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7.6.3.5 Decimation Filter Page (6141h) Registers

7.6.3.5.1 Register 0h (address = 0h) [reset = 0h], Decimation Filter Page (6141h)

图7-58. Register 0h

7

6

5

4

3

2

1

0

CHB/C FINE MIX

R/W-0h

DDC MODE

R/W-0h

表7-51. 0h Field Descriptions

Bit Field

Type Reset Description

7-4 CHB/C FINE MIX

R/W

0h

These bits select fine mixing frequency for the N × f_S/ 16 mixer, where N is a twos

complement number varying from –8 to 7.

0000 = N is 0

0001 = N is 1

0010 = N is 2

...

0111 = N is 7

1000 = N is –8

...

1111 = N is –1

3-0 DDC MODE

R/W

0h

These bits select DDC mode for all channels; see 表7-52 for bit settings.

表7-52. DDC MODE Bit Settings

SETTING

000

MODE

DESCRIPTION

f_S/ 4 mixing with decimation-by-2, complex output

N/A

0

001

–

010

2

Decimation-by-2, high or low pass filter, real output

N/A

011

–

4

100

Decimation-by-2, N × f_S/ 16 mixer, real output

Decimation-by-2, N × f_S/ 16 mixer, complex output

101

5

6

Decimation-by-4, N × f_S/ 16 mixer, complex output. Make sure the

DDC MODE 6 EN[3:1] register bits are also set to 111.

110

111

7

8

Decimation-by-2, N × f_S/ 16 mixer, insert 0, real output

No decimation, no mixing, straight 500-MSPS data output

Do not use

1000

Others

–

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7.6.3.5.2 Register 1h (address = 1h) [reset = 0h], Decimation Filter Page (6141h)

图7-59. Register 1h

7

0

6

0

5

0

4

3

2

1

0

DDC MODE6

EN1

ALWAYS

WRITE 1

CHB/C

COARSE MIX

0

CHB/C HPF EN

R/W-0h

W-0h

R/W-0h

表7-53. Register 1h Field Descriptions

Bit

Name

Type

Reset

Description

7-4

3

0

W

0h

Must write 0.

DDC MODE6 EN1

R/W

0h

Set this bit along with the DDC MODE6 EN2 and DDC MODE6

EN3 register bits for proper operation of mode 6.

0 = Default

1 = Use for proper operation of DDC mode 6

2

1

ALWAYS WRITE 1

CHB/C HPF EN

R/W

0h

Always write this bit to 1.

This bit enables the high-pass filter for DDC mode 2 for channel

B and C.

0 = Low-pass filter enabled

1 = High-pass filter enabled

0

CHB/C COARSE MIX

R/W

0h

This bit selects the f_S/ 4 mixer phase for DDC mode 0 for

channel B and C.

0 = Mix with f_S/ 4

1 = Mix with –f_S/ 4

7.6.3.5.3 Register 2h (address = 2h) [reset = 0h], Decimation Filter Page (6141h)

图7-60. Register 2h

7

0

6

0

5

4

3

2

1

0

CHA/D

COARSE MIX

CHA/D HPF EN

R/W-0h

CHA/D FINE MIX

R/W-0h

W-0h

R/W-0h

表7-54. 2h Field Descriptions

Bit

Name

Type

Reset

Description

7-6

5

0

W

0h

Must write 0.

CHA/D HPF EN

R/W

0h

This bit enables the high-pass filter for DDC mode 2 for channel

A and D.

0 = Low-pass filter enabled

1 = High-pass filter enabled

4

CHA/D COARSE MIX

CHA/D FINE MIX

R/W

0h

This bit selects the f_S/ 4 mixer phase for DDC mode 0 for

channel A and D.

0 = Mix with f_S/ 4

1 = Mix with –f_S/ 4

3-0

These bits select the fine mixing frequency for the N × f_S/ 16

mixer, where N is a twos complement number varying from –8

to 7.

0000 = N is 0

0001 = N is 1

0010 = N is 2

...

0111 = N is 7

1000 = N is –8

...

1111 = N is –1

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7.6.3.6 Main Digital Page (6800h) Registers

7.6.3.6.1 Register 0h (address = 0h) [reset = 0h], Main Digital Page (6800h)

图7-61. Register 0h

7

0

6

0

5

0

4

3

2

0

1

0

IL RESET

R/W-0h

W-0h

表7-55. Register 0h Field Descriptions

Bit

Name

0

Type

Reset

Description

7-1

0

W

0h

Must write 0.

IL RESET

R/W

0h

This bit resets the interleaving engine. This bit is not a self-

clearing bit and must be pulsed⁽¹⁾

.

Any register bit in the main digital page (6800h) takes effect only

after this bit is pulsed. Also, note that pulsing this bit clears

registers in the interleaving page (6100h).

0 = Normal operation

0 →1 →0 = Interleaving engine reset

(1) Pulsing = set the bit to 1 and then reset to 0.

7.6.3.6.2 Register 42h (address = 42h) [reset = 0h], Main Digital Page (6800h)

图7-62. Register 42h

7

0

6

0

5

0

4

3

2

1

0

NYQUIST ZONE

R/W-0h

W-0h

表7-56. Register 42h Field Descriptions

Bit

Name

Type

W

Reset

Description

7-3

2-0

0

0h

Must write 0.

NYQUIST ZONE

R/W

0h

These bits provide Nyquist zone information to the interleaving engine. Make

sure the CTRL NYQUIST register bit is set to 1.

000 = 1^stNyquist zone (input frequencies between 0 to f_S/ 2)

001 = 2^ndNyquist zone (input frequencies between f_S/ 2 to f_S)

010 = 3^rdNyquist zone (input frequencies between f_Sto 3 f_S/ 2)

...

111 = 8^thNyquist zone (input frequencies between 7 f_S/ 2 to 4 f_S)

7.6.3.6.3 Register 4Eh (address = 4Eh) [reset = 0h], Main Digital Page (6800h)

图7-63. Register 4Eh

7

6

0

5

0

4

3

0

2

0

1

0

CTRL NYQUIST

R/W-0h

0

W-0h

表7-57. Register 4Eh Field Descriptions

Bit

Name

Type

Reset

Description

7

CTRL NYQUIST R/W

0h

Enables Nyquist zone control using register bits NYQUIST ZONE.

0 = Selection disabled

1 = Selection enabled

6-0

0

W

0h

Must write 0.

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7.6.3.6.4 Register ABh (address = ABh) [reset = 0h], Main Digital Page (6800h)

图7-64. Register ABh

7

0

6

0

5

0

4

3

2

0

1

0

OVR EN

R/W-0h

W-0h

表7-58. Register ABh Field Descriptions

Bit

Field

0

Type

W

Reset

Description

7-1

0

0h

Must write 0.

OVR EN

R/W

0h

Set this bit to enable the OVR ON LSB register bit.

0 = Normal operation

1 = OVR ON LSB enabled

7.6.3.6.5 Register ADh (address = ADh) [reset = 0h], Main Digital Page (6800h)

图7-65. Register ADh

7

0

6

0

5

0

4

3

2

1

0

OVR ON LSB

R/W-0h

W-0h

表7-59. Register ADh Field Descriptions

Bit

Field

0

Type

W

Reset

Description

7-4

3-0

0h

Must write 0.

OVR EN

R/W

0h

Set this bit to bring OVR on two LSBs of the 16-bit output. Make sure the OVR EN

register bit is set to 1.

0000 = Bits 0 and 1 of the 16-bit data are noise bits

0011 = OVR comes on bit 0 of the 16-bit data

1100 = OVR comes on bit 1 of the 16-bit data

1111 = OVR comes on both bits 0 and 1 of the 16-bit data

7.6.3.6.6 Register F7h (address = F7h) [reset = 0h], Main Digital Page (68h)

图7-66. Register F7h

7

0

6

0

5

0

4

3

2

0

1

0

DIG RESET

R/W-0h

W-0h

表7-60. Register F7h Field Descriptions

Bit

Field

Type

W

Reset

Description

7-1

0

0h

Must write 0.

DIG RESET

R/W

0h

Self-clearing reset for the digital block. Does not include the interleaving correction.

0 = Normal operation

1 = Digital reset

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7.6.3.7 JESD Digital Page (6900h) Registers

7.6.3.7.1 Register 0h (address = 0h) [reset = 0h], JESD Digital Page (6900h)

图7-67. Register 0h

7

6

5

4

3

2

1

0

JESD MODE

EN

DDC MODE6

EN2

CTRL K

R/W-0h

TESTMODE EN

R/W-0h

0

LANE ALIGN FRAME ALIGN

R/W-0h R/W-0h

TX LINK DIS

R/W-0h

W-0h

表7-61. Register 0h Field Descriptions

Bit

Name

Type

Reset

Description

7

CTRL K

R/W

0h

Enable bit for a number of frames per multi frame.

0 = Default is five frames per multi frame

1 = Frames per multi frame can be set in register 06h

6

JESD MODE EN

R/W

0h

Allows changing the JESD MODE setting in register 01h (bits 1-0)

0 = Disabled

1 = Enables changing the JESD MODE setting.

This setting is to be used with MODE2 and MODE4 only.

5

4

DDC MODE6 EN2

TESTMODE EN

R/W

0h

Set this bit along with the DDC MODE6 EN1 and DDC MODE6 EN3 register bits

for proper operation of mode 6.

0 = Default

1 = Use for proper operation of DDC mode 6

This bit generates the long transport layer test pattern mode, as per section

5.1.6.3 of the JESD204B specification.

0 = Test mode disabled

1 = Test mode enabled

3

2

0

W

0h

Must write 0.

LANE ALIGN

R/W

This bit inserts the lane alignment character (K28.3) for the receiver to align to

lane boundary, as per section 5.3.3.5 of the JESD204B specification.

0 = Normal operation

1 = Inserts lane alignment characters

1

0

FRAME ALIGN

TX LINK DIS

R/W

0h

This bit inserts the lane alignment character (K28.7) for the receiver to align to

lane boundary, as per section 5.3.3.5 of the JESD204B specification.

0 = Normal operation

1 = Inserts frame alignment characters

This bit disables sending the initial link alignment (ILA) sequence when SYNC is

de-asserted.

0 = Normal operation

1 = ILA disabled

64

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7.6.3.7.2 Register 1h (address = 1h) [reset = 0h], JESD Digital Page (6900h)

图7-68. Register 1h

7

6

5

4

3

2

0

1

0

SYNCB SEL

AB/CD

DDC MODE6

EN3

SYNC REG

R/W-0h

SYNC REG EN

R/W-0h

0

JESD MODE

R/W-0h

W-0h

R/W-0h

W-0h

表7-62. Register 1h Field Descriptions

Bit

Name

SYNC REG

Type

Reset

Description

7

R/W

0h

SYNC register (bit 6 must be enabled).

0 = Normal operation

1 = ADC output data are replaced with K28.5 characters

6

5

SYNC REG EN

R/W

0h

Enables bit for SYNC operation.

0 = Normal operation

1 = ADC output data overwrite enabled

SYNCB SEL AB/CD R/W

This bit selects which SYNCb input controls the JESD interface; must be

configured for ch AB and ch CD.

0 = SYNCbAB

1 = SYNCbCD

4

3

0

W

0h

Must write 0.

DDC MODE6 EN3

R/W

Set this bit along with the DDC MODE6 EN1 and DDC MODE6 EN2 register

bits for proper operation of mode 6.

0 = Default

1 = Use for proper operation of DDC mode 6

2

0

W

0h

Must write 0.

1-0

JESD MODE

R/W

These bits select the number of serial JESD output lanes per ADC. The JESD

MODE EN (00h) and JESD PLL MODE register (JESD ANALOG page, register

16h) must also be set accordingly.

01 = 20x mode

10 = 40x mode

11 = 80x mode

All others = Not used

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7.6.3.7.3 Register 2h (address = 2h) [reset = 0h], JESD Digital Page (6900h)

图7-69. Register 2h

7

6

5

4

3

2

0

1

0

LINK LAYER

RPAT

LMFC MASK

RESET

LINK LAYER TESTMODE

R/W-0h

W-0h

表7-63. Register 2h Field Descriptions

Bit

Name

Type

Reset

Description

7-5

LINK LAYER TESTMODE

R/W

0h

These bits generate a pattern according to clause 5.3.3.8.2 of

the JESD204B document.

000 = Normal ADC data

001 = D21.5 (high-frequency jitter pattern)

010 = K28.5 (mixed-frequency jitter pattern)

011 = Repeat initial lane alignment (generates a K28.5 character

and continuously repeats lane alignment sequences)

100 = 12-octet RPAT jitter pattern

4

LINK LAYER RPAT

R/W

0h

This bit changes the running disparity in the modified RPAT

pattern test mode (only when the link layer test mode = 100).

0 = Normal operation

1 = Changes disparity

3

LMFC MASK RESET

0

R/W

W

0h

0 = Default

1 = Resets the LMFC mask

2-0

Must write 0.

7.6.3.7.4 Register 3h (address = 3h) [reset = 0h], JESD Digital Page (6900h)

图7-70. Register 3h

7

6

5

4

3

2

1

0

FORCE LMFC COUNT

R/W-0h

LMFC COUNT INIT

R/W-0h

RELEASE ILANE SEQ

R/W-0h

表7-64. Register 3h Field Descriptions

Bit

Name

Type

Reset

Description

7

FORCE LMFC COUNT

R/W

0h

This bit forces the LMFC count.

0 = Normal operation

1 = Enables using a different starting value for the LMFC

counter

6-2

1-0

LMFC COUNT INIT

R/W

0h

SYSREF coming to the digital block resets the LMFC count to 0

and K28.5 stops coming when the LMFC count reaches 31. The

initial value that the LMFC count resets to can be set using

LMFC COUNT INIT. In this manner, Rx can be synchronized

early because it receives the LANE ALIGNMENT SEQUENCE

early. The FORCE LMFC COUNT register bit must be enabled.

RELEASE ILANE SEQ

These bits delay the generation of lane alignment sequence by

0, 1, 2, or 3 multi frames after code group synchronization.

00 = 0

01 = 1

10 = 2

11 = 3

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7.6.3.7.5 Register 5h (address = 5h) [reset = 0h], JESD Digital Page (6900h)

图7-71. Register 5h

7

6

0

5

0

4

3

0

2

0

1

0

SCRAMBLE EN

R/W-0h

0

W-0h

表7-65. Register 5h Field Descriptions

Bit

Name

Type

Reset

Description

7

SCRAMBLE EN

R/W

0h

Scramble enable bit in the JESD204B interface.

0 = Scrambling disabled

1 = Scrambling enabled

6-0

0

W

0h

Must write 0.

7.6.3.7.6 Register 6h (address = 6h) [reset = 0h], JESD Digital Page (6900h)

图7-72. Register 6h

7

0

6

0

5

0

4

3

2

1

0

FRAMES PER MULTI FRAME (K)

R/W-0h

W-0h

表7-66. Register 6h Field Descriptions

Bit

7-5

4-0

Name

Type

Reset

Description

0

W

0h

Must write 0.

FRAMES PER MULTI FRAME (K)

R/W

0h

These bits set the number of multi frames.

Actual K is the value in hex + 1 (that is, 0Fh is K = 16).

7.6.3.7.7 Register 21h (address = 21h) [reset = 0h], JESD Digital Page (6900h)

图7-73. Register 21h

7

6

5

4

3

2

1

0

OUTPUT CHA MUX SEL

R/W-0h

OUTPUT CHB MUX SEL

R/W-0h

OUTPUT CHC MUX SEL

R/W-0h

OUTPUT CHD MUX SEL

R/W-0h

表7-67. 21h Field Descriptions

Bit

Name

Type

Reset

Description

7-6

OUTPUT CHA MUX SEL

R/W

0h

SERDES lane swap with ch B.

00 = Ch A is output on lane DA

10 = Ch A is output on lane DB

01, 11 = Do not use.

Can only be used in 4 lane mode.

5-4

3-2

1-0

OUTPUT CHB MUX SEL

OUTPUT CHC MUX SEL

OUTPUT CHD MUX SEL

R/W

0h

SERDES lane swap with ch A.

00 = Ch B is output on lane DB

10 = Ch B is output on lane DA

01, 11 = Do not use. Can only be used in 4 lane mode.

SERDES lane swap with ch D.

00 = Ch C is output on lane DC

10 = Ch C is output on lane DD

01, 11 = Do not use. Can only be used in 4 lane mode.

SERDES lane swap with ch C.

00 = Ch D is output on lane DD

10 = Ch D is output on lane DC

01, 11 = Do not use. Can only be used in 4 lane mode.

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7.6.3.7.8 Register 22h (address = 22h) [reset = 0h], JESD Digital Page (6900h)

图7-74. Register 22h

7

0

6

0

5

0

4

3

2

1

0

OUT CHA INV OUT CHB INV OUT CHC INV OUT CHD INV

R/W-0h R/W-0h R/W-0h R/W-0h

W-0h

表7-68. 22h Field Descriptions

Bit

Name

Type

Reset

Description

7-4

3-0

0

W

0h

Must write 0.

OUT CHA, CHB, CHC and R/W

CH D INV

0h

Polarity inversion of JESD output of CHA, CHB, CHC and CHD.

00 = Normal operation

0011 = Output polarity of CHB and CHD inverted. 1100 = Output polarity

of CHA and CHC inverted. 1111 = Output of all channels inverted.

All others = Do not use.

7.6.3.8 JESD Analog Page (6A00h) Register

7.6.3.8.1 Register 12h, 13h (address 12h, 13h) [reset = 0h], JESD Analog Page (6Ah)

图7-75. Register 12h

7

6

5

4

3

2

1

0

SEL EMP LANE DA/DD

R/W-0h

W-0h

图7-76. Register 13h

7

6

5

4

3

2

1

0

SEL EMP LANE DB/DC

R/W-0h

W-0h

表7-69. 12h, 13h Field Descriptions

Bit

Name

Type

Reset

Description

7-2

SEL EMP LANE DA/DD

SEL EMP LANE DB/DC

R/W

0h

Selects the amount of de-emphasis for the JESD output transmitter. The

de-emphasis value in dB is measured as the ratio between the peak

value after the signal transition to the settled value of the voltage in one

bit period.

0 = 0 dB

1 = –1 dB

3 = –2 dB

7 = –4.1 dB

15 = –6.2 dB

31 = –8.2 dB

63 = –11.5 dB

1-0

0

W

0h

Must write 0.

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7.6.3.8.2 Register 16h (address = 16h) [reset = 0h], JESD Analog Page (6A00h)

图7-77. Register 16h

7

0

6

0

5

0

4

3

2

0

1

0

JESD PLL MODE

R/W-0h

W-0h

表7-70. Register 16h Field Descriptions

Bit

Name

Type

Reset

Description

7-2

1-0

0

W

0h

Must write 0.

JESD PLL MODE

R/W

0h

These bits select the JESD PLL multiplication factor and must

match the JESD MODE setting.

00 = 20x mode

01 = Not used

10 = 40x mode

11 = Not used

7.6.3.8.3 Register 17h (address = 17h) [reset = 0h], JESD Analog Page (6A00h)

图7-78. Register 17h

7

0

6

5

0

4

3

2

0

1

0

PLL RESET

R/W-0h

0

W-0h

表7-71. Register 17h Field Descriptions

Bit

Name

Type

Reset

Description

7

6

0

W

0h

Must write 0.

PLL RESET

R/W

0h

When SERDES line is < 5 Gbps, pulse this bit after powering up

the device.

0 = Default

0 > 1 > 0 = The PLL RESET bit is pulsed.

5-0

0

W

0h

Must write 0.

7.6.3.8.4 Register 1Bh (address = 1Bh) [reset = 0h], JESD Analog Page (6A00h)

图7-79. Register 1Bh

7

6

5

4

3

2

0

1

0

JESD SWING

R/W-0h

0

W-0h

表7-72. Register 1Bh Field Descriptions

Bit

Name

JESD SWING

Type

Reset Description

7-5

R/W

0h

To program the JESD swing, first disable broadcast mode by setting the DIS

BROADCAST register bit to 1. Then keep the bit CH = 1 while programming the

JESD SWING bits. For example, to set the swing as 930 mVpp:

i) Write address 4005h, value 01h to disable broadcast mode.

ii)Write address 4004h, value 6Ah; and 4003h, value 00h to access the JESD

analog page.

iii)Write address 701Bh, value A0h to set the swing as 930 mVpp.

0 = 860 mV_PP

1 = 810 mV_PP

2 = 770 mV_PP

3 = 745 mV_PP

4 = 960 mV_PP

5 = 930 mV_PP

6 = 905 mV_PP

7 = 880 mV_PP

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表7-72. Register 1Bh Field Descriptions (continued)

Bit

Name

Type

Reset Description

4-0

0

W

0h

Must write 0.

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8 Application Information Disclaimer

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

8.1.1 Start-Up Sequence

The following steps are recommended as the power-up sequence with the ADS54J66 in DDC mode 8 (no

decimation) with LMFS = 4421 (shown in 表8-1).

表8-1. Recommended Power-Up Sequence

REGISTER REGISTER

STEP

DESCRIPTION

COMMENT

ADDRESS

DATA

1

Power up the IOVDD 1.15-V supply before the

1.9-V supply. All other supplies (AVDD 1.9-V and

AVDD 3-V supply) can be supplied in any order.

—

2

Pulse a hardware reset (low to high to low) on pin

48.

—

Alternatively, the device can be reset with an

analog reset and a digital reset.

0000h

4004h

4003h

4002h

4001h

60F7h

70F7h

81h

68h

00h

01h

00h

01h

00h

3

4

5

Set the input clock divider.

0011h

0053h

0039h

0059h

80h

C0h

20h

Select the master page in the analog bank.

Set the clock divider to divide-by-2.

Set the ALWAYS WRITE 1 bit for all channels.

Reset the interleaving correction engine in

register 6800h of the main digital page of the

JESD bank. (Register access is already set to

page 6800h in step 2.)

6000h

7000h

01h

00h

01h

00h

Resets the interleaving engine for channel A, B

(because the device is in broadcast mode).

Resets the interleaving engine for channel C, D

(because the device is in broadcast mode).

Set DDC mode 8 for all channels (no decimation,

14-bit, 500-MSPS data output).

4004h

4003h

61h

41h

Select the decimation filter page of the JESD bank.

6000h

7000h

08h

Select DDC mode 8 for channel A, B.

Select DDC mode 8 for channel C, D.

6001h

7001h

04h

Set the ALWAYS WRITE 1 bit for channel A, B.

Set the ALWAYS WRITE 1 bit for channel C, D.

6

7

Default registers for the analog page of the JESD

bank.

4003h

4004h

00h

6Ah

Select the analog page in the JESD bank.

6016h

7016h

02h

PLL mode 40x for channel A, B.

PLL mode 40x for channel C, D.

Default registers for the digital page of the JESD

bank.

4003h

4004h

00h

69h

Select the digital page in the JESD bank.

6000h

6001h

7000h

7001h

20h

01h

20h

01h

Enable JESD MODE control for channel A, B.

Set JESD MODE to 20x mode for LMFS = 4421.

Enable JESD MODE control for channel C, D.

Set JESD MODE to 20x mode for LMFS = 4421.

6000h

6006h

7000h

7006h

80h

0Fh

80h

0Fh

Set CTRL K for channel A, B.

Set K to 16.

Set CTRL K for channel C, D.

Set K to 16.

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表8-1. Recommended Power-Up Sequence (continued)

REGISTER REGISTER

STEP

DESCRIPTION

COMMENT

ADDRESS

DATA

8

Enable a single SYNCb input (on the SYNCbAB

pin).

4005h

7001h

01h

20h

Disable broadcast mode.

Use SYNCbABP, SYNCbABM to issue a SYNC

request for all four channels.

9

Pulse SYNCbAB (pins 55 and 56) from high to

low.

K28.5 characters are transmitted by all four channels

(CGS phase).

—

10

Pulse SYNCbAB (pins 55 and 56) from low to

high.

The ILA sequence begins and lasts for four

multiframes. The device transmits ADC data after

the ILA sequence ends.

8.1.2 Hardware Reset

8.1.2.1 Register Initialization

After power-up, the internal registers can be initialized to their default values through a hardware reset by

applying a high pulse on the RESET pin (of durations greater than 10 ns), as shown in 图 8-1. Alternatively, the

serial interface registers can be cleared a set of register writes as described in the 节 8.1.1 section. 表 8-2 lists

the timing requirements for the pulse signal on the RESET pin.

8.1.2.2

Power

Supplies

t₁

RESET

t₃

t₂

CLK

(CLKP-CLKM)

SYSREF*

(SYSREFP-SYSREFM)

Power down SYSREF driver after

applying at least 2 SYSREF pulses

after SPI is configured.

SEN,

SCLK,

SDATA

SPI

Cycle

SPI

Cycle

* The SYSREF signal resets the input clock divider, the LMFC counter in the JESD block, and the NCO counters in the DDC block.

Applying the SYSREF signal before configuring SPI is recommended. After SPI is configured, either the SYSREF driver can be

powered down, or the SYSREF buffer inside the device can be powered down to avoid degradation in the ADC performance resulting

from the SYSREF signal coupling to the ADC analog inputs.

图8-1. Hardware Reset Timing Diagram

表8-2. Timing Requirements for Hardware Reset

MIN

1

TYP MAX UNIT

t₁

t₂

t₃

Power-on delay from power-up to active high RESET pulse

Reset pulse duration : active high RESET pulse duration

Register write delay from RESET disable to SEN active

ms

ns

10

100

8.1.3 SYSREF Signal

Apply SYSREF after reset and before configuring the device. After the device is configured to the desired mode,

the SYSREF driver can be disabled. Optionally, SYSREF can be masked inside the device using the MASK

SYSREF register bit.

The SYSREF signal is sampled by the ADS54J66 device clock, and is used to reset the input clock divider that

generates the sampling clock for the two interleaving ADC cores. The SYSREF signal also resets the local

multiframe clock (LMFC) counter inside the JESD block, and the divider in the decimation filter block of the data

converter. SYSREF is required to be a subharmonic of the LMFC frequency. The LMFC clock frequency

72

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depends upon the device clock frequency, the DDC decimation option, and the JESD link settings (LMFS). The

SYSREF signal is also recommended to be a low frequency signal (less than 5 MHz) in order to reduce coupling

to the signal path both on the PCB as well as internal to the device.

表8-3 shows that the external SYSREF signal must be a subharmonic of the internal LMFC clock.

The SYSREF frequency is equal to LMFC / N with N = 0, 1, 2, and so forth.

表8-3. LMFC Clock Frequency

LMFS CONFIGURATION

DECIMATION

LMFC CLOCK

4421

f_S⁽¹⁾/ K⁽²⁾

—

…

4x

2x

…

4841

2441

4421

4841

f_S/ (4 × K)

f_S/ (2 × K)

(1) f_S= sampling (device) clock frequency.

(2) K = number of frames per multiframe (JESD digital page 6900h, address 06h, D4-D0).

8.1.4 SNR and Clock Jitter

The signal-to-noise ratio of the ADC is limited by three different factors (as shown in 方程式 2): the quantization

noise is typically not noticeable in pipeline converters and is 84 dB for a 14-bit ADC. The thermal noise limits the

SNR at low input frequencies and the clock jitter sets the SNR for higher input frequencies.

(2)

The SNR limitation resulting from sample clock jitter can be calculated by 方程式3:

(3)

The total clock jitter (T_Jitter) has two components: the internal aperture jitter (120 fs for the ADS54J66) that is set

by the noise of the clock input buffer and the external clock jitter. T_Jittercan be calculated by 方程式4:

(4)

External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-

pass filters at the clock input; a faster clock slew rate also improves the ADC aperture jitter.

The ADS54J66 has a thermal noise of approximately 72 dBFS and an internal aperture jitter of 120 fs.

8.1.5 Idle Channel Histogram

图8-2 shows a histogram of output codes for when no signal is applied at the analog inputs of the ADS54J66. 图

8-3 shows that when the dc offset correction block of the device is bypassed, the output code histogram

becomes multi-modal with as many as four peaks. This (TBD this what?) happens because the ADS54J66 is a

4-way interleaved ADC with each ADC core having a different internal dc offset.

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6000

5000

4000

3000

2000

1000

0

3600

3000

2400

1800

1200

600

0

8040

8180

8185

8190

8195

8200

8205

8080

8120

8160 8200

Output Code

8240

8280

Output Code

D062

D063

图8-2. Idle Channel Histogram (No Signal at

图8-3. Idle Channel Histogram (No Signal at

Analog Inputs, DC Offset Correction is On)

Analog Inputs, DC Offset Correction is Off)

图8-4 shows that when the dc offset correction block is frozen (instead of bypassing), the output code histogram

improves (compared to when bypassed). However, when the temperature changes, the dc offset difference

among interleaving cores may increase resulting in increased spacing between peaks in the histogram.

6000

5000

4000

3000

2000

1000

0

8182 8184 8186 8188 8190 8192 8194 8196 8198 8200 8202

Output Code

D064

D107

图8-4. Idle Channel Histogram (No Signal at Analog Inputs, DC Offset Correction is Frozen)

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8.1.6 ADC Test Pattern

The ADS54J66 provides several different options to output test patterns instead of the actual output data of the

ADC in order to simplify bring up of the JESD204B digital interface link. The output data path is shown in 图8-5.

ADC Section

Transport Layer

Link Layer

PHY Layer

DDC

ADC

Data Mapping

Frame Construction

DDC

Block

8b/10b

Encoding

Interleaving

Correction

Scrambler

1+x¹⁴+x¹⁵

Serializer

ADC Test

Pattern

JESD204B Long

Transport Layer

Test Pattern

JESD204B

Link Layer

Test Pattern

图8-5. ADC Test Pattern

8.1.6.1 ADC Section

The ADC test pattern replaces the actual output data of the ADC. The following test patterns are available in

register 74h. In order to properly obtain the test pattern output, the interleaving correction must be disabled

(6100h, address 18h) and DDC mode-8 must be selected (un-decimated output).

In un-decimated output (DDC mode-8), the device supports LMFS = 4421 only. Available ADC test patterns are

summarized in 表8-4.

表8-4. ADC Test Pattern Settings

BIT

NAME

DEFAULT

DESCRIPTION

These bits provide the test pattern output on channels A and B.

0000 = Normal operation using ADC output data

0001 = Outputs all 0s

0010 = Outputs all 1s

0011 = Outputs toggle pattern: output data are an alternating

sequence of 101010101010 and 010101010101

0100 = Output digital ramp: output data increment by one LSB every

clock cycle from code 0 to 16384

7-4

TEST PATTERN

0000

0110 = Single pattern: output data are custom pattern 1 (75h and

76h)

0111 = Double pattern: output data alternate between custom pattern

1 and custom pattern 2

1000 = Deskew pattern: output data are 2AAAh

1001 = SYNC pattern: output data are 3FFFh

8.1.6.2 Transport Layer Pattern

The transport layer maps the ADC output data into 8-bit octets and constructs the JESD204B frames using the

LMFS parameters. Tail bits or 0s are added when needed. Alternatively, the JESD204B long transport layer test

pattern can be substituted as shown in 表8-5.

表8-5. Transport Layer Test Mode

BIT

NAME

DEFAULT

DESCRIPTION

This bit generates the long transport layer test pattern mode

according to clause 5.1.6.3 of the JESD204B specification.

0 = Test mode disabled

4

TESTMODE EN

0

1 = Test mode enabled

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8.1.6.3 Link Layer Pattern

The link layer contains the scrambler and the 8b/10b encoding of any data passed on from the transport layer.

Additionally, the link layer also controls the initial lane alignment sequence that can be manually restarted. The

link layer test patterns are intended for testing the quality of the link (jitter testing and so forth). The test patterns

do not pass through the 8b/10b encoder and contain the options shown in 表8-6.

表8-6. Link Layer Test Mode

BIT

NAME

DEFAULT

DESCRIPTION

These bits generate the pattern according to clause 5.3.3.8.2 of the

JESD204B document.

000 = Normal ADC data

001 = D21.5 (high-frequency jitter pattern)

010 = K28.5 (mixed-frequency jitter pattern)

011 = Repeat initial lane alignment (generates a K28.5 character and

repeats lane alignment sequences continuously)

100 = 12-octet RPAT jitter pattern

7-5

LINK LAYER TESTMODE

000

Furthermore, a 2¹⁵PRBS can be enabled by setting up a custom test pattern (AAAA) in the ADC section and

running that through the 8b/10b encoder with scrambling enabled.

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8.2 Typical Application

The ADS54J66 is designed for wideband receiver applications demanding excellent dynamic range over a large

input frequency range. A typical schematic for an ac-coupled dual receiver (dual FPGA with dual SYNC) is

shown in 图8-6.

DVDD

5 ꢀ

10 kꢀ

25 ꢀ

3.3 pF

0.1 uF

GND

Driver

SPI Master

25 ꢀ

5 ꢀ

GND

IOVDD GND

0.1 uF

GND

0.1 uF

AVDD

0.1 uF

DVDD

AVDD3V

AVDD

AVDD3V

5 ꢀ

25 ꢀ

3.3 pF

25 ꢀ

0.1 uF

100 ꢀ Differential

Driver

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

5 ꢀ

GND

INCP

SYNCbCDP

SYNCbCDM

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

50 ꢀ

Vterm=1.2 V

AVDD

AGND

AVDD

0.1 uF

IOVDD

FPGA

IOVDD

DDP

GND

10 nF

GND

10 nF

NC

DDM

GND

0.1 uF

AVDD3V

AVDD

DGND

DCP

AVDD3V

GND

AVDD

0.1 uF

DCM

AGND

GND

10 nF

IOVDD

0.1 uF

GND

IOVDD

DGND

DBM

CLKINP

CLKINM

AGND

100 ꢀ

ADS54J66

GND

GND PAD (backside)

0.1 uF

AVDD

Low Jitter

Clock

Generator

DBP

AVDD

DGND

DAM

AVDD3V

AGND

AVDD3V

0.1 uF

GND

10 nF

GND

DAP

SYSREFP

100 ꢀ

IOVDD

10 nF

IOVDD

SYNCbABM

SYNCbABP

SYSREFM

AVDD

5 ꢀ

GND

50 ꢀ

Vterm=1.2 V

INBP

FPGA

25 ꢀ

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

0.1 uF

100 ꢀ Differential

0.1 uF

GND

3.3 pF

Driver

25 ꢀ

5 ꢀ

AVDD3V

AVDD

DVDD

AVDD

AVDD3V

0.1 uF

GND

0.1 uF

IOVDD

0.1 uF

GND

5 ꢀ

25 ꢀ

0.1 uF

GND

3.3 pF

Driver

25 ꢀ

GND = AGND + DGND connected in Layout

25 ꢀ

5 ꢀ

GND = AGND and DGND are connected in the PCB layout.

图8-6. Application Diagram for the ADS54J66

8.2.1 Design Requirements

By using the simple drive circuit of 图8-6 (when the amplifier drives the ADC) or 图7-1 (when transformers drive

the ADC), uniform performance can be obtained over a wide frequency range. The buffers present at the analog

inputs of the device help isolate the external drive source from the switching currents of the sampling circuit.

8.2.2 Detailed Design Procedure

For optimum performance, the analog inputs must be driven differentially. This architecture improves the

common-mode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with

each input pin is recommended to damp out ringing caused by package parasitics, as shown in 图8-6.

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8.2.3 Application Curves

图8-7 and 图8-8 show the typical performance at 190 MHz and 230 MHz, respectively.

0

-20

0

-20

-40

-60

-80

-100

-120

-100

-120

0

50

100 150

Input Frequency (MHz)

200

250

0

50

100 150

Input Frequency (MHz)

200

250

D003

D004

f_IN= 190 MHz, A_IN= –1 dBFS, SNR = 69.4 dBFS, SFDR =

f_IN= 230 MHz, A_IN= –1 dBFS, SNR = 69.4 dBFS, SFDR =

88 dBc, SFDR = 96 dBc (non 23)

85 dBc, SFDR = 96 dBc (non 23)

图8-7. FFT for 190-MHz Input Signal

图8-8. FFT for 230-MHz Input Signal

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8.3 Power Supply Recommendations

The device requires a 1.15-V nominal supply for IOVDD, a 1.9-V nominal supply for DVDD, a 1.9-V nominal

supply for AVDD, and a 3.0-V nominal supply for AVDD3V. For detailed information regarding the operating

voltage minimum and maximum specifications of different supplies, see the 节6.3 table.

8.3.1 Power Sequencing and Initialization

图8-9 shows the suggested power-up sequencing for the device. The 1.15-V IOVDD supply must rise before the

1.9-V DVDD supply. If the 1.9-V DVDD supply rises before the 1.15-V IOVDD supply, then the internal default

register settings may not load properly. The other supplies (the 3-V AVDD3V and the 1.9-V AVDD), can come up

in any order during the power sequence. The power supplies can ramp up at any rate and there is no hard

requirement for the time delay between IOVDD ramp up to DVDD ramp-up (can be in orders of microseconds

but is recommend to be a few milliseconds).

IOVDD = 1.15 V

DVDD = 1.9 V

AVDD = 1.9 V

AVDD = 3 V

图8-9. Power Sequencing for the ADS54J66 Device

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8.4 Layout

8.4.1 Layout Guidelines

The device evaluation module (EVM) layout can be used as a reference layout to obtain the best performance. A

layout diagram of the EVM top layer is provided in 图 8-10. A complete layout of the EVM is available at the

ADS54J66 EVM folder. Some important points to remember during board layout are:

• Analog inputs are located on opposite sides of the device pinout for minimum crosstalk on the package level.

To minimize crosstalk onboard, the analog inputs must exit the pinout in opposite directions, as shown in the

reference layout of 图8-10 as much as possible.

• Connect INP of all unused analog inputs to AVDD and the INM to GND or vice versa.

• In the device pinout, the sampling clock is located on a side perpendicular to the analog inputs in order to

minimize coupling between them. This configuration is also maintained on the reference layout of 图8-10 as

much as possible.

• Keep digital outputs away from the analog inputs. When these digital outputs exit the pinout, the digital output

traces must not be kept parallel to the analog input traces because this configuration can result in coupling

from the digital outputs to the analog inputs and degrade performance. All digital output traces to the receiver

[such as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)] must be

matched in length to avoid skew among outputs.

• Connect a 100 Ohm differential resistor across unused SERDES outputs to limit the swing which will occur if

unterminated.

• At each power-supply pin (AVDD, DVDD, or AVDDD3V), keep a 0.1-µF decoupling capacitor close to the

device. A separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF

capacitors can be kept close to the supply source.

8.4.2 Layout Example

图8-10. ADS54J66EVM Layout

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9 Device and Documentation Support

9.1 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

9.2 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

9.3 商标

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

9.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

9.5 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

RMP0072A

VQFN - 0.9 mm max height

SCALE 1.700

VQFN

10.1

9.9

A

B

PIN 1 ID

10.1

9.9

0.9 MAX

0.05

0.00

C

SEATING PLANE

0.08 C

(0.2)

4X (45 X0.42)

19

36

18

37

SYMM

4X

8.5

8.5 0.1

PIN 1 ID

(R0.2)

1

54

0.30

0.18

72X

72

55

68X 0.5

SYMM

0.5

0.3

0.1

C B

A

72X

0.05

C

4221047/B 02/2014

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RMP0072A

VQFN - 0.9 mm max height

VQFN

(

8.5)

SYMM

72X (0.6)

SEE DETAILS

55

72

1

54

72X (0.24)

(0.25) TYP

SYMM

(9.8)

(1.315) TYP

68X (0.5)

(

0.2) TYP

VIA

37

18

19

36

(1.315) TYP

(9.8)

LAND PATTERN EXAMPLE

SCALE:8X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4221047/B 02/2014

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON PCB application report

in literature No. SLUA271 (www.ti.com/lit/slua271).

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EXAMPLE STENCIL DESIGN

RMP0072A

VQFN - 0.9 mm max height

VQFN

(9.8)

72X (0.6)

(1.315) TYP

72

55

1

54

72X (0.24)

(1.315)

TYP

(0.25) TYP

SYMM

(9.8)

(1.315)

TYP

68X (0.5)

METAL

TYP

37

18

(

0.2) TYP

VIA

19

36

36X ( 1.115)

(1.315) TYP

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

62% PRINTED SOLDER COVERAGE BY AREA

SCALE:8X

4221047/B 02/2014

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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型号：	ADS54J66IRMP
厂家：	TEXAS INSTRUMENTS
描述：	四通道、14 位、500MSPS 模数转换器 (ADC) \| RMP \| 72 \| -40 to 85 转换器模数转换器
文件：	总87页 (文件大小：5910K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS54J66IRMP [TI]

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