ADS5522IPAPG4 [TI]
12-Bit, 80 MSPS Analog-To-Digital Converter; 12位， 80 MSPS模拟数字转换器
| 型号： | ADS5522IPAPG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12-Bit, 80 MSPS Analog-To-Digital Converter |
| 文件： | 总32页 (文件大小：1154K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SBAS320C–MAY 2004–REVISED FEBRUARY 2007
12-Bit, 80 MSPS
Analog-To-Digital Converter
FEATURES
•
•
TQFP-64 PowerPAD™ Package
Recommended Op Amps:
OPA695, OPA847, THS3201, THS3202,
THS4503, THS4509, THS9001
•
•
•
•
•
•
•
•
•
12-Bit Resolution
80 MSPS Sample Rate
High SNR: 69.7 dBFS at 100 MHz fIN
High SFDR: 83 dBc at 100 MHz fIN
2.3-VPP Differential Input Voltage
Internal Voltage Reference
APPLICATIONS
•
Wireless Communication
–
–
Communication Receivers
Base Station Infrastructure
3.3-V Single-Supply Voltage
Analog Power Dissipation: 541 mW
Serial Programming Interface
•
•
•
Test and Measurement Instrumentation
Single and Multichannel Digital Receivers
Communication Instrumentation
–
Radar, Infrared
•
•
Video and Imaging
Medical Equipment
DESCRIPTION
The ADS5522 is a high-performance, 12-bit, 80 MSPS analog-to-digital converter (ADC). To provide a complete
converter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference.
Designed for applications demanding the highest speed and highest dynamic performance in little space, the
ADS5522 has excellent power consumption of 541 mW at 3.3-V single-supply voltage. This allows an even
higher system integration density. The provided internal reference simplifies system design requirements.
Parallel CMOS-compatible output ensures seamless interfacing with common logic.
The ADS5522 is available in a 64-pin TQFP PowerPAD package over the industrial temperature range.
ADS5500 PRODUCT FAMILY
80 MSPS
ADS5522
ADS5542
105 MSPS
ADS5521
ADS5541
125 MSPS
ADS5520
ADS5500
12 Bit
14 Bit
AV
DD
DRV
DD
CLK+
CLK−
Timing Circuitry
CLKOUT
12-Bit
D0
Digital
Error
Correction
V
IN+
.
.
.
Output
Control
Pipeline
ADC
Core
S&H
V
D11
IN−
OVR
DFS
Internal
Reference
Control Logic
CM
Serial Programming Register
ADS5522
A
GND
SEN
SDATA SCLK
DR
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADS5522
www.ti.com
SBAS320C–MAY 2004–REVISED FEBRUARY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT PACKAGE-LEAD
HTQFP-64(2)
ADS5522
ADS5522IPAP
Tray, 160
PAP
–40 C to 85
C
ADS5522I
PowerPAD
ADS5522IPAPR
Tape and Reel, 1000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet.
(2) Thermal pad size: 3,5 mm x 3,5 mm (min), 4 mm x 4 mm (max). θJA = 21.47 C/W and θJC = 2.99 C/W, when used with 2 oz. copper
trace and pad soldered directly to a JEDEC standard, four-layer, 3 in x 3 in PCB.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
ADS5522
UNIT
AVDD to AGND, DRVDD to DRGND
AGND to DRGND
–0.3 to 3.7
V
V
V
V
V
Supply Voltage
0.1
–0.3 to minimum (AVDD + 0.3, 3.6)
–0.3 to DRVDD
–0.3 to DRVDD
0 to 70
(2)(3)
Analog input to AGND
Logic input to DRGND
Digital data output to DRGND
Operating temperature range
C
–40 to 85
Junction temperature
105
C
C
Storage temperature range
–65 to 150
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) If the input signal can exceed 3.6 V, then a resistor greater than or equal to 25 Ω should be added in series with each of the analog
input pins to support input voltages up to 3.8 V. For input voltages above 3.8 V, the device can only handle transients and the duty cycle
of the overshoot should be limited to less than 5% for inputs up to 3.9 V.
(3) The overshoot duty cycle can be defined as the ratio of the total time of overshoot to the total intended device lifetime, expressed as a
percentage. The total time of overshoot is the integrated time of all overshoot occurences over the lifetime of the device.
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SBAS320C–MAY 2004–REVISED FEBRUARY 2007
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
UNIT
Supplies
AVDD
Analog supply voltage
3
3
3.3
3.3
3.6
3.6
V
V
DRVDD
Output driver supply voltage
Analog input
Differential input range
Input common-mode voltage
Digital Output
Maximum output load
Clock Input
2.3
VPP
V
(1)
VCM
1.45
1.55
1.65
10
pF
ADCLK input sample rate (sine wave) 1/tC
Clock amplitude, sine wave, differential(2)
Clock duty cycle(3)
2
1
80
85
MSPS
VPP
3
50%
Open free-air temperature range
–40
C
(1) Input common-mode should be connected to CM.
(2) See Figure 47 for more information.
(3) See Figure 46 for more information.
ELECTRICAL CHARACTERISTICS
Typical values given at TA = 25 C, min and max specified over the full recommended operating temperature range, AVDD
DRVDD = 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-VPP differential clock, and –1-dBFS differential input,
unless otherwise noted
=
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
12
Bits
Analog Inputs
Differential input range
2.3
6.6
4
VPP
kΩ
Differential input impedance
Differential input capacitance
Analog input common-mode current (per input)
Analog input bandwidth
See Figure 37
See Figure 37
pF
200
750
4
µA
Source impedance = 50 Ω
MHz
Voltage overload recovery time
Internal Reference Voltages
Reference bottom voltage, V(REFM)
Reference top voltage, V(REFP)
Reference error
Clock cycles
1
2.15
V
V
–4%
0.6%
4%
1.55
0.05
Common-mode voltage output, V(CM)
V
Dynamic DC Characteristics and Accuracy
No missing codes
Tested
0.25
Differential nonlinearity error, DNL
Integral nonlinearity error, INL
Offset error
fIN = 10 MHz
fIN = 10 MHz
–0.5
–1.5
-11
0.5
1.5
11
LSB
LSB
mV
0.55
±1.5
Offset temperature coefficient
0.02
%/ C
∆offset error/∆AVDD from AVDD = 3 V
to AVDD = 3.6 V
DC power-supply rejection ratio, DC PSRR
0.25
mV/V
%FS
(1)
Gain error
-2
±0.3
2
Gain temperature coefficient
–0.02
∆%/ C
(1) Gain error is specified by design and characterization; it is not tested in production.
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ELECTRICAL CHARACTERISTICS (continued)
Typical values given at TA = 25 C, min and max specified over the full recommended operating temperature range, AVDD
DRVDD = 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-VPP differential clock, and –1-dBFS differential input,
unless otherwise noted
=
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Dynamic AC Characteristics
25
C
68
70.5
69.5
70.3
70.2
69
fIN = 10 MHz
fIN = 55 MHz
fIN = 70 MHz
Full temp range
66.5
25
C
68
Signal-to-noise ratio. SNR
dBFS
LSB
dBc
Full temp range
66.5
fIN = 100 MHz
fIN = 150 MHz
fIN = 220 MHz
69.7
68.6
67.2
0.43
87
RMS idle channel noise
Input tied to common-mode
25
Full temp range
C
79
76
fIN = 10 MHz
fIN = 55 MHz
fIN = 70 MHz
84
87
25
C
78
76
84
Spurious-free dynamic range, SFDR
Full temp range
83
fIN = 100 MHz
fIN = 150 MHz
fIN = 220 MHz
83
78
71
25
C
79
76
87
fIN = 10 MHz
fIN = 55 MHz
fIN = 70 MHz
Full temp range
86
86
25
C
78
76
84
Second-harmonic, HD2
dBc
Full temp range
83
fIN = 100 MHz
fIN = 150 MHz
fIN = 220 MHz
83
78
71
25
C
79
76
91
fIN = 10 MHz
fIN = 55 MHz
fIN = 70 MHz
Full temp range
87
90
25
C
78
76
83
Third-harmonic, HD3
dBc
dBc
Full temp range
83
fIN = 100 MHz
fIN = 150 MHz
fIN = 220 MHz
fIN = 10 MHz
fIN = 70 MHz
83
86
84
25
25
25
C
C
C
90
Worst-harmonic/spur (other than HD2 and HD3)
89
67.5
66
70.4
69
fIN = 10 MHz
fIN = 55 MHz
fIN = 70 MHz
Full temp range
70.1
69.9
68.5
69.4
68.1
65.8
25
C
67.5
66
Signal-to-noise + distortion, SINAD
dBFS
Full temp range
fIN = 100 MHz
fIN = 150 MHz
fIN = 220 MHz
4
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ELECTRICAL CHARACTERISTICS (continued)
Typical values given at TA = 25 C, min and max specified over the full recommended operating temperature range, AVDD
=
DRVDD = 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-VPP differential clock, and –1-dBFS differential input,
unless otherwise noted
PARAMETER
CONDITIONS
25
Full temp range
MIN
78
TYP
85.2
82
MAX
UNIT
C
fIN = 10 MHz
fIN = 55 MHz
fIN = 70 MHz
75
83.6
82.1
81
25
C
77
75
Total harmonic distortion, THD
dBc
Full temp range
fIN = 100 MHz
fIN = 150 MHz
fIN = 220 MHz
fIN = 70 MHz
80.8
76.6
70.4
11.3
Effective number of bits, ENOB
Bits
dBFS
dB
f = 10.1 MHz, 15.1 MHz
(–7dBFS each tone)
88
85
f = 50.1 MHz, 55.1 MHz
(–7dBFS each tone)
Two-tone intermodulation distortion, IMD
f = 148.1 MHz, 153.1 MHz
(–7dBFS each tone)
93
35
AC power supply rejection ratio, ACPSRR
Power Supply
Supply noise frequency ≤ 100 MHz
Total supply current, ICC
fIN = 70 MHz
fIN = 70 MHz
201
164
230
180
mA
mA
Analog supply current, I(AVDD)
fIN = 70 MHz, 10-pF load from digital
outputs to ground
Output buffer supply current, I(DRVDD)
37
541
122
180
50
594
165
250
mA
Analog only
Power dissipation
Standby power
mW
mW
Output buffer power with 10-pF load on
digital output to ground
With Clocks running
DIGITAL CHARACTERISTICS
Valid over full recommended operating temperature range, AVDD = DRVDD = 3.3 V, unless otherwise noted
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Digital Inputs
VIH
VIL
IIH
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
Input current for RESET
Input capacitance
2.4
V
0.8
10
V
µA
µA
µA
pF
IIL
–10
–20
4
Digital Outputs
VOL
VOH
Low-level output voltage
CLOAD = 10 pF
CLOAD = 10 pF
0.3
3
0.4
V
V
High-level output voltage
Output capacitance
2.8
3
pF
5
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SBAS320C–MAY 2004–REVISED FEBRUARY 2007
N + 3
N + 4
N + 2
Sample
N
Analog
Input
N + 1
N + 17
N + 16
N + 14
N + 15
Signal
t
A
Input Clock
t
START
t
PDI
Output Clock
t
su
Data Out
(D0−D11)
N − 17
N − 16
N − 15
N − 14
N − 13
N − 3
N − 2
N − 1
N
Data Invalid
t
t
END
h
17.5 Clock Cycles
NOTE: It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above
timing matches closely with the specified values.
Figure 1. Timing Diagram
TIMING CHARACTERISTICS(1)
Typical values given at TA = 25 C, min and max specified over the full recommeded operating temperature range,
AVDD = DRVDD = 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-VPP differential clock, and CLOAD = 10 pF,
unless otherwise noted(2)
PARAMETER
Switching Specification
DESCRIPTION
MIN
TYP
MAX
UNIT
tA
Aperture delay
Input CLK falling edge to data sampling point
Uncertainty in sampling instant
Data valid(3) to 50% of CLKOUT rising edge
1
300
4.7
ns
fs
Aperture jitter (uncertainty)
Data setup time
tSU
tH
3.6
1.8
ns
ns
Data hold time
50% of CLKOUT rising edge to data becoming
invalid(3)
3.1
tSTART
tEND
Input clock to output data valid
start(4)(5)
Input clock rising edge to data valid start delay
Input clock rising edge to data valid end delay
Uncertainty in CLKOUT rising edge, peak-to-peak
3.3
5.0
ns
ns
Input clock to output data valid
end(4)(5)
8.4
7.1
11.1
tJIT
tr
Output clock jitter
210
2.5
315
2.8
ps
ns
Output clock rise time
Rise time of CLKOUT measured from 20% to 80%
of DRVDD
tf
Output clock fall time
Input clock to output clock delay
Data rise time
Fall time of CLKOUT measured from 80% to 20%
of DRVDD
2.1
8
2.3
8.9
ns
ns
ns
ns
tPDI
tr
Input clock rising edge zero crossing, to output
clock rising edge 50%
Data rise time measured from 20% to 80% of
DRVDD
5.6
4.4
6.1
tf
Data fall time
Data fall time measured from 80% to 20% of
DRVDD
5.1
Output enable(OE) to data output
delay
Time required for outputs to have stable timings
with regard to input clock(6) after OE is activated
1000
Clock
cycles
(1) Timing parameters are ensured by design and characterization, and not tested in production.
(2) See Table 5 through Table 6 in the Application Information section for timing information at additional sampling frequencies.
(3) Data valid refers to 2 V for LOGIC HIGH and 0.8 V for LOGIC LOW.
(4) See the Output Information section for details on using the input clock for data capture.
(5) These specifications apply when the CLKOUT polarity is set to rising edge (according to Table 2). Add 1/2 clock period for the valid
number for a falling edge CLKOUT polarity.
(6) Data outputs are available within a clock from assertion of OE; however, it takes 1000 clock cycles to ensure stable timing with respect
to input clock.
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TIMING CHARACTERISTICS (continued)
Typical values given at TA = 25 C, min and max specified over the full recommeded operating temperature range,
AVDD = DRVDD = 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-VPP differential clock, and CLOAD = 10 pF,
unless otherwise noted
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
Time to valid data after coming out of software
power down
1000
Clock
cycles
Wakeup time
Time to valid data after stopping and restarting the
clock
1000
Latency
Time for a sample to propagate to the ADC outputs
17.5
Clock
cycles
RESET TIMING CHARACTERISTICS
Typical values given at TA = 25 C, min and max specified over the full recommended operating temperature range, AVDD
DRVDD = 3.3 V, and 3-VPP differential clock, unless otherwise noted
=
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
Switching Specification
t1
t2
t3
Power-on delay
Reset pulse width
Register write delay
Power-up time
Delay from power-on of AVDD and DRVDD to RESET pulse active
Pulse width of active RESET signal
10
2
ms
µs
Delay from RESET disable to SEN active
2
µs
Delay from power-up of AVDD and DRVDD to output stable
40
ms
Power Supply
(AV , DRV
)
DD
DD
t . 10 ms
1
t . 2 ms
2
t . 2 ms
3
SEN Active
RESET (Pin 35)
Figure 2. Reset Timing Diagram
SERIAL PROGRAMMING INTERFACE CHARACTERISTICS
The ADS5522 has a three-wire serial interface. The device latches serial data SDATA on the falling edge of
serial clock SCLK when SEN is active.
•
•
•
•
•
•
Serial shift of bits is enabled when SEN is low. SCLK shifts serial data at the falling edge.
Minimum width of data stream for a valid loading is 16 clocks.
Data is loaded at every 16th SCLK falling edge while SEN is low.
In case the word length exceeds a multiple of 16 bits, the excess bits are ignored.
Data can be loaded in multiples of 16-bit words within a single active SEN pulse.
The first 4-bit nibble is the address of the register while the last 12 bits are the register contents.
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SERIAL PROGRAMMING INTERFACE CHARACTERISTICS (continued)
A3
A2
A1
A0
D11
D10
D9
D0
SDATA
ADDRESS
DATA
MSB
Figure 3. DATA Communication is 2-Byte, MSB First
t
SLOADS
t
SEN
SLOADH
t
t
t
SCLK
WSCLK WSCLK
SCLK
t
t
h(D)
su(D)
SDATA
MSB
LSB
MSB
LSB
16 x M
Figure 4. Serial Programming Interface Timing Diagram
Table 1. Serial Programming Interface Timing Characteristics
SYMBOL
tSCLK
PARAMETER
SCLK period
MIN(1)
TYP(1)
MAX(1)
UNIT
50
ns
tWSCLK
tSLOADS
tSLOADH
tDS
SCLK duty cycle
SEN to SCLK setup time
SCLK to SEN hold time
Data setup time
25%
50%
75%
8
6
8
6
ns
ns
ns
ns
tDH
Data hold time
(1) Typ, min, and max values are characterized, but not production tested.
Table 2. Serial Register Table(1)
A3 A2 A1 A0 D11
D10
D9
D8 D7 D6 D5 D4 D3 D2
D1
D0
DESCRIPTION
TP<1 TP<0
Test Mode
>
0
0
1
1
>
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
0
0
0
0
Normal mode of operation
All outputs forced to 0(2)
All outputs forced to 1(2)
0
(2)(3)
0
Each output bit toggles between 0 and 1.
Power Down
PDN
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
0
0
Normal mode of operation
1
Device is put in power-down (low-current) mode.
(1) The register contents default to the appropriate setting for normal operation up on RESET.
(2) The patterns given are applicable to the straight offset binary output format. If two's complement output format is selected, the test mode
outputs will be the binary two's complement equivalent of these patterns as described in the Output Information section.
(3) While each bit toggles between 1 and 0 in this mode, there is no assured phase relationship between the data bits D0 through D11. For
example, when D0 is a 1, D1 in not assured to be a 0, and vice versa.
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Table 3. Data Format Select (DFS) Table
DFS-PIN VOLTAGE (VDFS
)
DATA FORMAT
CLOCK OUTPUT POLARITY
2
12
V
AV
AV
V
t
AV
DD
Straight Binary
Data valid on rising edge
DFS
DD
5
12
4
12
t V
t V
t
AV
AV
Two's Complement
Straight Binary
Data valid on rising edge
Data valid on falling edge
Data valid on falling edge
DD
DFS
8
12
7
12
t
DD
DD
DFS
10
12
u
AV
DD
Two's Complement
DFS
PIN CONFIGURATION
PAP PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
47
46
DRGND
SCLK
DRGND
D1
2
3
SDATA
SEN
D0 (LSB)
4
45 NC
AVDD
AGND
AVDD
AGND
AVDD
CLKP
CLKM
AGND
5
44 NC
6
43 CLKOUT
7
42
41
DRGND
OE
ADS5522
PowerPAD
8
9
40 DFS
(Connected to Analog Ground)
10
11
12
39
38
37
AVDD
AGND
AVDD
AGND 13
AGND 14
AVDD 15
36 AGND
35 RESET
34 AVDD
16
33
AVDD
AGND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
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PIN ASSIGNMENTS
TERMINAL
NO. OF
NAME
NO.
PINS
I/O
DESCRIPTION
5, 7, 9, 15, 22,
24, 26, 28, 33,
34, 37, 39
AVDD
12
I
Analog power supply
Analog ground
6, 8, 12–14, 16,
18, 21, 23, 25,
27, 32, 36, 38
AGND
14
I
DRVDD
DRGND
49, 58
2
6
I
I
Output driver power supply
Output driver ground
1, 42, 48, 50,
57, 59
NC
44, 45
19
20
29
30
31
17
35
41
40
10
11
4
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
—
I
Not connected
INP
Differential analog input (positive)
Differential analog input (negative)
INM
I
REFP
REFM
IREF
CM
O
O
I
Reference voltage (positive); 1- F capacitor in series with a 1-Ω resistor to GND
Reference voltage (negative); 1- F capacitor in series with a 1-Ω resistor to GND
Current set; 56.2-kΩ resistor to GND; do not connect capacitors
Common-mode output voltage
O
I
(1)
RESET
OE
Reset (active high), Internal 200-kΩ resistor to AVDD
Output enable (active high)(2)
Data format and clock out polarity select(3)(2)
Data converter differential input clock (positive)
Data converter differential input clock (negative)
Serial interface chip select(2)
I
DFS
I
CLKP
CLKM
SEN
I
I
I
SDATA
SCLK
3
I
Serial interface data(2)
Serial interface clock(2)
2
I
D0 (LSB) to
D11 (MSB)
46, 47, 51–56,
60-63
14
O
Parallel data output
OVR
64
43
1
1
O
O
Over-range indicator bit
CLKOUT
CMOS clock out in sync with data
(1) If RESET pin is unused, it must be tied to AGND and serial interface should be used to reset the device. See the serial programming
interface section for details.
(2) Pins OE, DFS, SEN, SDATA, and SCLK have internal clamping diodes to the DRVDD supply. Any external circuit driving these pins
must also run off the same supply voltage as DRVDD.
(3) Table 3 defines the voltage levels for each mode selectable via the DFS pin.
10
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DEFINITION OF SPECIFICATIONS
Offset Error
Analog Bandwidth
The offset error is the difference, given in number of
LSBs, between the ADC's actual average idle
channel output code and the ideal average idle
channel output code. This quantity is often mapped
into mV.
The analog input frequency at which the power of the
fundamental is reduced by 3 dB with respect to the
low frequency value.
Aperture Delay
Temperature Drift
The delay in time between the falling edge of the
input sampling clock and the actual time at which the
sampling occurs.
The temperature drift coefficient (with respect to gain
error and offset error) specifies the change per
degree Celsius of the parameter from TMIN to TMAX. It
is calculated by dividing the maximum deviation of
the parameter across the TMIN to TMAX range by the
difference (TMAX – TMIN).
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle
Signal-to-Noise Ratio (SNR)
The duty cycle of a clock signal is the ratio of the
time the clock signal remains at a logic high (clock
pulse width) to the period of the clock signal. Duty
cycle is typically expressed as a percentage. A
perfect differential sine wave clock results in a 50%
duty cycle.
SNR is the ratio of the power of the fundamental (PS)
to the noise floor power (PN), excluding the power at
DC and the first eight harmonics.
PS
10 PN
SNR + 10Log
(1)
Maximum Conversion Rate
SNR is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full scale) when the
power of the fundamental is extrapolated to the
converter's full-scale range.
The maximum sampling rate at which certified
operation is given. All parametric testing is performed
at this sampling rate unless otherwise noted.
Minimum Conversion Rate
Signal-to-Noise and Distortion (SINAD)
The minimum sampling rate at which the ADC
functions.
SINAD is the ratio of the power of the fundamental
(PS) to the power of all the other spectral
components including noise (PN) and distortion (PD),
but excluding dc.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions at analog
input values spaced exactly 1 LSB apart. The DNL is
the deviation of any single step from this ideal value,
measured in units of LSBs.
PS
SINAD + 10Log
10 PN ) PD
(2)
Integral Nonlinearity (INL)
SINAD is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full scale) when the
power of the fundamental is extrapolated to the
converter's full-scale range.
The INL is the deviation of the ADC's transfer
function from a best fit line determined by a least
squares curve fit of that transfer function, measured
in units of LSBs.
Effective Number of Bits (ENOB)
Gain Error
The ENOB is
performance as compared to the theoretical limit
based on quantization noise.
a
measure of
a
converter's
The gain error is the deviation of the ADC's actual
input full-scale range from its ideal value. The gain
error is given as a percentage of the ideal input
full-scale range. Gain error does not account for
variations in the internal reference voltages (see the
Electrical Specifications section for limits on the
variation of V(REFP) and V(REFM)).
SINAD * 1.76
ENOB +
6.02
(3)
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS)
to the power of the first eight harmonics (PD).
PS
10 PD
THD + 10Log
(4)
THD is typically given in units of dBc (dB to carrier).
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Spurious-Free Dynamic Range (SFDR)
Reference Error
The ratio of the power of the fundamental to the
highest other spectral component (either spur or
harmonic). SFDR is typically given in units of dBc
(dB to carrier).
The reference error is the variation of the actual
reference voltage (V(REFP)– V(REFM)) from its ideal
value. The reference error is typically given as a
percentage.
Two-Tone Intermodulation Distortion (IMD3)
Voltage Overload Recovery Time
IMD3 is the ratio of the power of the fundamental (at
frequencies f1 and f2) to the power of the worst
spectral component at either frequency 2f1 – f2 or
2f2 – f1. IMD3 is either given in units of dBc (dB to
carrier) when the absolute power of the fundamental
is used as the reference, or dBFS (dB to full scale)
when the power of the fundamental is extrapolated to
the converter's full-scale range.
The voltage overload recovery time is defined as the
time required for the ADC to recover to within 1% of
the full-scale range in response to an input voltage
overload of 10% beyond the full-scale range.
DC Power Supply Rejection Ration (DC PSRR)
The DC PSSR is the ratio of the change in offset
error to a change in analog supply voltage. The DC
PSRR is typically given in units of mV/V.
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TYPICAL CHARACTERISTICS
Typical values given at TA = 25 C, AVDD = DRVDD = 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-Vpp
differential clock, and –1 dBFS differential input, unless otherwise noted
SPECTRAL PERFORMANCE
(FFT for 4 MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 16 MHz Input Signal)
0
0
SFDR = 90.0 dBc
THD = 86.4 dBc
SFDR = 86.8 dBc
THD = 85.2 dBc
−20
−20
SNR = 71.2 dBFS
SINAD = 71.1 dBFS
SNR = 70.9 dBFS
SINAD = 70.8 dBFS
−40
−60
−80
−40
−60
−80
−100
−120
−100
−120
0
0
0
5
10
15
20
25
30
35
40
40
40
0
0
0
5
10
15
20
25
30
35
40
40
40
f − Frequency − MHz
f − Frequency − MHz
Figure 5.
Figure 6.
SPECTRAL PERFORMANCE
(FFT for 55 MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 70 MHz Input Signal)
0
0
SFDR = 87.0 dBc
THD = 82.2 dBc
SNR = 70.6 dBFS
SINAD = 70.4 dBFS
SFDR = 85.9 dBc
THD = 83.7 dBc
SNR = 70.5 dBFS
SINAD = 70.3 dBFS
−20
−20
−40
−60
−80
−40
−60
−80
−100
−120
−100
−120
5
10
15
20
25
30
35
5
10
15
20
25
30
35
f − Frequency − MHz
f − Frequency − MHz
Figure 7.
Figure 8.
SPECTRAL PERFORMANCE
(FFT for 100 MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 125 MHz Input Signal)
0
0
SFDR = 87.2 dBc
THD = 82.8 dBc
SNR = 69.8 dBFS
SINAD = 69.6 dBFS
SFDR = 80.2 dBc
THD = 77.8 dBc
SNR = 69.3 dBFS
SINAD = 68.8 dBFS
−20
−20
−40
−60
−80
−40
−60
−80
−100
−120
−100
−120
5
10
15
20
25
30
35
5
10
15
20
25
30
35
f − Frequency − MHz
f − Frequency − MHz
Figure 9.
Figure 10.
13
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TYPICAL CHARACTERISTICS (continued)
Typical values given at TA = 25 C, AVDD = DRVDD = 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-Vpp
differential clock, and –1 dBFS differential input, unless otherwise noted
SPECTRAL PERFORMANCE
(FFT for 150 MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 220 MHz Input Signal)
0
0
SFDR = 81.7 dBc
THD = 79.9 dBc
SNR = 68.7 dBFS
SINAD = 68.4 dBFS
SFDR = 69.8 dBc
THD = 69.2 dBc
−20
−20
SNR = 67.0 dBFS
SINAD = 65.3 dBFS
−40
−60
−80
−40
−60
−80
−100
−120
−100
−120
0
0
0
5
10
15
20
25
30
35
40
40
40
0
0
0
5
5
5
10
15
20
25
30
35
40
40
40
f − Frequency − MHz
f − Frequency − MHz
Figure 11.
Figure 12.
SPECTRAL PERFORMANCE
(FFT for 300 MHz Input Signal)
TWO-TONE
INTERMODULATION
0
0
SFDR = 69.0 dBc
THD = 68.7 dBc
SNR = 64.8 dBFS
SINAD = 58.0 dBFS
f1 = 10 MHz, −7 dBFS
f1 = 15 MHz, −7 dBFS
2-Tone IMD = −88.0 dBFS
−20
−20
−40
−60
−80
−40
−60
−80
−100
−120
−100
−120
5
10
15
20
25
30
35
10
15
20
25
30
35
f − Frequency − MHz
f − Frequency − MHz
Figure 13.
Figure 14.
TWO-TONE
TWO-TONE
INTERMODULATION
INTERMODULATION
0
0
f1 = 50 MHz, −7 dBFS
f1 = 55 MHz, −7 dBFS
2-Tone IMD = −84.8 dBFS
f1 = 148 MHz, −7 dBFS
f1 = 153 MHz, −7 dBFS
2-Tone IMD = −92.8 dBFS
−20
−20
−40
−60
−80
−40
−60
−80
−100
−120
−100
−120
5
10
15
20
25
30
35
10
15
20
25
30
35
f − Frequency − MHz
f − Frequency − MHz
Figure 15.
Figure 16.
14
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TYPICAL CHARACTERISTICS (continued)
Typical values given at TA = 25 C, AVDD = DRVDD = 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-Vpp
differential clock, and –1 dBFS differential input, unless otherwise noted
DIFFERENTIAL
NONLINEARITY
INTEGRAL
NONLINEARITY
0.25
0.20
0.15
0.10
0.05
0
0.60
f
= 10.1 MHz
IN
0.50
0.40
0.30
0.20
A
= −0.5 dBFS
IN
0.10
−0.05
−0.10
−0.15
0
−0.10
−0.20
−0.25
−0.20
−0.30
f
IN
= 10.1 MHz, A = −0.5 dBFS
IN
0
512 1024 1536 2048 2560 3072 3584 4096
Code
0
512 1024 1536 2048 2560 3072 3584 4096
Code
Figure 17.
Figure 18.
SPURIOUS-FREE DYNAMIC RANGE
vs INPUT FREQUENCY
SIGNAL-TO-NOISE RATIO
vs INPUT FREQUENCY
90
85
80
75
70
65
60
55
50
72
71
70
69
68
67
66
f
A
= 80 MSPS
= −1 dBFS
S
f
A
= 80 MSPS
= −1 dBFS
S
IN
IN
0
50
100
150
200
250
300
0
50
100
150
200
250
300
Input Frequency − MHz
Input Frequency − MHz
Figure 19.
Figure 20.
AC PERFORMANCE
vs ANALOG SUPPLY VOLTAGE
AC PERFORMANCE
vs ANALOG SUPPLY VOLTAGE
90
85
80
75
70
90
85
80
75
70
f
IN
= 150 MHz
SFDR
SFDR
SNR
SNR
65
60
65
60
f
IN
= 70 MHz
3.00
3.15
3.30
3.45
3.60
3.00
3.15
3.30
3.45
3.60
AV − Analog Supply Voltage − V
DD
AV − Analog Supply Voltage − V
DD
Figure 21.
Figure 22.
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TYPICAL CHARACTERISTICS (continued)
Typical values given at TA = 25 C, AVDD = DRVDD = 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-Vpp
differential clock, and –1 dBFS differential input, unless otherwise noted
AC PERFORMANCE
vs DIGITAL SUPPLY VOLTAGE
AC PERFORMANCE
vs DIGITAL SUPPLY VOLTAGE
90
85
80
90
85
80
f
IN
= 150 MHz
f
IN
= 70 MHz
SFDR
SFDR
75
70
65
75
70
65
SNR
3.30
SNR
3.30
60
3.00
60
3.00
3.15
3.45
3.60
3.15
3.45
3.60
DV − Digital Supply Voltage − V
DD
DV − Digital Supply Voltage − V
DD
Figure 23.
Figure 24.
POWER DISSIPATION
vs SAMPLE RATE
POWER DISSIPATION
vs SAMPLE RATE
0.8
0.8
IF = 150 MHz
IF = 70 MHz
0.7
0.6
0.5
0.4
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.3
0.2
0.1
0
10
20
30
40
50
60
70
80
10
20
30
40
50
60
70
80
Sample Rate − MSPS
Sample Rate − MSPS
Figure 25.
Figure 26.
AC PERFORMANCE
vs TEMPERATURE
AC PERFORMANCE
vs INPUT AMPLITUDE
90
90
70
50
f
IN
= 70.1 MHz
SNR (dBFS)
85
80
75
70
SFDR
SFDR (dBc)
30
10
SNR (dBc)
SNR
−10
f
IN
= 70.1 MHz
65
−30
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10
Input Amplitude − dBFS
−40
−15
10
35
60
85
0
Temperature − °C
Figure 27.
Figure 28.
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TYPICAL CHARACTERISTICS (continued)
Typical values given at TA = 25 C, AVDD = DRVDD = 3.3 V, sampling rate = 80 MSPS, 50% clock duty cycle, 3-Vpp
differential clock, and –1 dBFS differential input, unless otherwise noted
AC PERFORMANCE
vs INPUT AMPLITUDE
AC PERFORMANCE
vs INPUT AMPLITUDE
90
70
50
90
70
50
SNR (dBFS)
SNR (dBFS)
SFDR (dBc)
30
10
30
10
SFDR (dBc)
SNR (dBc)
−10
−30
SNR (dBc)
−10
f
IN
= 220.1 MHz
f
IN
= 150.1 MHz
−30
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10
Input Amplitude − dBFS
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10
0
0
Input Amplitude − dBFS
Figure 29.
Figure 30.
OUTPUT
NOISE HISTOGRAM
AC PERFORMANCE
vs CLOCK AMPLITUDE
80
70
60
50
40
30
20
10
0
90
f
IN
= 70.1 MHz
85
80
SFDR
75
70
65
60
SNR
1.5
0
0.5
1
2
2.5
3
2052 2053 2054 2055 2056
2057 2058 2059
Differential Clock Amplitude − V
Code
Figure 31.
Figure 32.
WCDMA
CARRIER
AC PERFORMANCE
vs CLOCK DUTY CYCLE
0
−20
−40
−60
−80
90
85
80
f
f
= 76.8 MSPS
= 170 MHz
SFDR
S
IN
75
70
65
60
SNR
−100
−120
−140
f
IN
= 20.1 MHz
40
0
5
10
15
20
25
30
35
40
30
50
60
70
f − Frequency − MHz
Clock Duty Cycle − %
Figure 33.
Figure 34.
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TYPICAL CHARACTERISTICS
Typ, min, max values at TA = 25 C, full temperature range is TMIN = –40 C to TMAX = 85 C, AVDD = DRVDD = 3.3 V,
sampling rate = 80 MSPS, 50% clock duty cycle, 3-Vpp differential clock, and –1 dBFS differential input, unless otherwise
noted
SIGNAL-TO-NOISE RATIO (SNR)
100
71
70
69
69
90
80
70
60
50
40
30
20
10
71
70
68
67
66
65
69
71
71
68
66
70
69
64
63
68
67
70
71
69
62
61
63
67
68
65
66
64
63
67
66
70
40
62
61
60
220
64
65
120
69
68
60
63
160
20
80
100
140
180
200
Input Frequency − MHz
Figure 35.
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TYPICAL CHARACTERISTICS (continued)
Typ, min, max values at TA = 25 C, full temperature range is TMIN = –40 C to TMAX = 85 C, AVDD = DRVDD = 3.3 V,
sampling rate = 80 MSPS, 50% clock duty cycle, 3-Vpp differential clock, and –1 dBFS differential input, unless otherwise
noted
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
80
74
76
100
90
80
70
60
50
40
30
20
10
90
88
86
84
82
80
78
76
74
72
70
68
66
64
78
82
86
84
84
90
68
70
72
66
84
80
82
86
88
86
88
86
84
88
86
86
88
84
78
90
74
76
86
88
86
68
72
70
80
86
82
66
84
88
86
84
84
88
78
76
86
82
88
74
84
80
86
72
70
68
86
82
84
66
220
78
64
80
60
20
40
80
100
120 140
Input Frequency − MHz
160
180
200
Figure 36.
19
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APPLICATION INFORMATION
clock cycle. This process results in a data latency of
17.5 clock cycles, after which the output data is
available as a 12-bit parallel word, coded in either
straight offset binary or binary two's complement
format.
THEORY OF OPERATION
The ADS5522 is a low-power, 12-Bit, 80 MSPS,
CMOS, switched capacitor, pipeline ADC that
operates from a single 3.3-V supply. The conversion
process is initiated by a falling edge of the external
input clock. Once the signal is captured by the input
S&H, the input sample is sequentially converted by a
series of small resolution stages, with the outputs
combined in a digital correction logic block. Both the
rising and the falling clock edges are used to
propagate the sample through the pipeline every half
INPUT CONFIGURATION
The analog input for the ADS5522 consists of a
differential
sample-and-hold
architecture
implemented using the switched capacitor technique
shown in Figure 37.
S
3a
L1
R1a
C1a
INP
S
S
1a
CP1
CP3
S
2
R3
CA
L2
R1b
C1b
VINCM
1V
1b
INM
CP2
CP4
S
3b
L , L : 6 nH − 10 nH effective
1
2
R
1a
, R : 5W − 8W
1b
C , C : 2.2 pF − 2.6 pF
1a 1b
CP , CP : 2.5 pF − 3.5 pF
1
2
CP , CP : 1.2 pF − 1.8 pF
3
4
C : 0.8 pF − 1.2 pF
A
R : 80 W − 120 W
3
Swithches: S , S
On Resistance: 35 W − 50 W
1a 1b:
S : On Resistance: 7.5 W − 15 W
2
S
, S : On Resistance: 40 W − 60 W
3a 3b
All switches OFF Resistance: 10 GW
NOTE: All Switches are ON in sampling phase which is approximately one half of a clock period.
Figure 37. Analog Input Stage
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This differential input topology produces a high level
of ac-performance for high sampling rates. It also
results in a very high usable input bandwidth,
especially important for high intermediate-frequency
(IF) or undersampling applications. The ADS5522
requires each of the analog inputs (INP, INM) to be
externally biased around the common-mode level of
the internal circuitry (CM, pin 17). For a full-scale
differential input, each of the differential lines of the
input signal (pins 19 and 20) swings symmetrically
between CM + 0.575 V and CM –0.575 V. This
means that each input is driven with a signal of up to
CM 0.575 V, so that each input has a maximum
differential signal of 1.15 VPP for a total differential
input signal swing of 2.3 VPP. The maximum swing is
determined by the two reference voltages, the top
reference (REFP, pin 29), and the bottom reference
(REFM, pin 30).
Where:
fS > 2MSPS.
This equation helps to design the output capability
and impedance of the driving circuit accordingly.
When it is necessary to buffer or apply a gain to the
incoming analog signal, it is possible to combine
single-ended operational amplifiers with an RF
transformer, or to use a differential input/output
amplifier without a transformer, to drive the input of
the ADS5522. Texas Instruments offers a wide
selection of single-ended operational amplifiers
(including the THS3201, THS3202, OPA847, and
OPA695) that can be selected depending on the
application. An RF gain block amplifier, such as TI'ss
THS9001, can also be used with an RF transformer
for high input frequency applications. The THS4503
is a recommended differential input/output amplifier.
Table 4 lists the recommended amplifiers.
The ADS5522 obtains optimum performance when
the analog inputs are driven differentially. The circuit
shown in Figure 38 illustrates one possible
configuration using an RF transformer.
When using single-ended operational amplifiers
(such as the THS3201, THS3202, OPA847, or
OPA695) to provide gain, a three-amplifier circuit is
recommended with one amplifier driving the primary
of an RF transformer and one amplifier in each of the
legs of the secondary driving the two differential
inputs of the ADS5522. These three amplifier circuits
minimize even-order harmonics. For high frequency
inputs, an RF gain block amplifier can be used to
R
Z
O
O
50W
50W
25W
R
ADS5522
50W
25W
drive
a transformer primary; in this case, the
transformer secondary connections can drive the
input of the ADS5522 directly, as shown in
Figure 38, or with the addition of the filter circuit
shown in Figure 39.
10W
0.1 mF
Figure 39 illustrates how RIN and CIN can be placed
to isolate the signal source from the switching inputs
of the ADC and to implement a low-pass RC filter to
limit the input noise in the ADC. It is recommended
that these components be included in the ADS5522
circuit layout when any of the amplifier circuits
discussed previously are used. The components
allow fine-tuning of the circuit performance. Any
mismatch between the differential lines of the
Figure 38. Transformer Input to Convert
Single-Ended Signal to Differential Signal
The single-ended signal is fed to the primary winding
of an RF transformer. Since the input signal must be
biased around the common-mode voltage of the
internal circuitry, the common-mode voltage (VCM
)
from the ADS5522 is connected to the center-tap of
the secondary winding. To ensure a steady low-noise
VCM reference, best performance is attained when
the CM output (pin 17) is filtered to ground with a
0.1-µF and 0.001-µF low-inductance capacitors,
ADS5522 input produces
a
degradation in
performance at high input frequencies, mainly
characterized by an increase in the even-order
harmonics. In this case, special care should be taken
to keep as much electrical symmetry as possible
between both inputs.
Output VCM (pin 17) is designed to directly drive the
ADC input. When providing a custom CM level, be
aware that the input structure of the ADC sinks a
common-mode current in the order of 400 µA (200
µA per input) at 80 MSPS. Equation 5 describes the
dependency of the common-mode current and the
sampling frequency:
Another possible configuration for lower-frequency
signals is the use of differential input/output
amplifiers that can simplify the driver circuit for
applications requiring dc-coupling of the input.
Flexible in their configurations (see Figure 40), such
amplifiers can be used for single-ended-to-differential
conversion signal amplification.
400 mA x f (in MSPS)
s
80
(5)
21
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Table 4. Recommended Amplifiers to Drive the Input of the ADS5522
INPUT SIGNAL FREQUENCY
DC to 20 MHz
RECOMMENDED AMPLIFIER
THS4503
TYPE OF AMPLIFIER
Differential In/Out Amp
Operational Amp
USE WITH TRANSFORMER?
No
Yes
No
DC to 50 MHz
OPA847
DC to 100 MHz
THS4509
Differential In/Out Amp
Operational Amp
OPA695
Yes
Yes
Yes
Yes
10 MHz to 120 MHz
THS3201
Operational Amp
THS3202
Operational Amp
Over 100 MHz
THS9001
RF Gain Block
+5V 5V
RS
RIN
0.1 mF
100W
25 W
VIN
1:1
INP
OPA695
RT
ADS5522
CIN
1000 pF
RIN
25 W
100W
R1
INM
CM
400W
AV = 8V/V
(18dB)
R2
10 W
57.5 W
0.1 mF
Figure 39. Converting a Single-Ended Input Signal to a Differential Signal Using an RF Transformer
22
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SBAS320C–MAY 2004–REVISED FEBRUARY 2007
R
R
T
R
F
S
S
+5V
R
+3.3V
0.1 mF
10 mF
R
R
IN
IN
INP
ADS5522
V
COM
12-Bit / 80MSPS
INM
1 mF
CM
THS4503
10 mF
0.1 mF
10W
R
5V
R
F
G
0.1 mF
Figure 40. Using the THS4503 with the ADS5522
23
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SBAS320C–MAY 2004–REVISED FEBRUARY 2007
POWER-SUPPLY SEQUENCE
connected from IREF (pin 31) to AGND to set the
proper current for the operation of the ADC, as
shown in Figure 42. No capacitor should be
connected between pin 31 and ground; only the
56.2-kΩ resistor should be used.
The preferred power-up sequence is to ramp AVDD
first, followed by DRVDD, including a simultaneous
ramp of AVDD and DRVDD. In the event that DRVDD
ramps up first in the system, care must be taken to
ensure that AVDD ramps up within 10 ms. Optionally,
it is recommended to put a 2-kΩ resistor from REFP
(pin 29) to AVDD as shown in Figure 41. This helps
to make the device more robust to power supply
ramp-up timings.
1 W
REFP
REFM
29
30
1 mF
1 mF
1 W
28
AVDD
31 IREF
56.2 kW
2 kW
29
REFP
Figure 42. REFP, REFM, and IREF Connections
for Optimum Performance
1 W
1 mF
CLOCK INPUT
Figure 41. Power-Up Sequence
The ADS5522 clock input can be driven with either a
differential clock signal or a single-ended clock input,
with little or no difference in performance between
both configurations. The common-mode voltage of
the clock inputs is set internally to CM (pin 17) using
internal 5-kΩ resistors that connect CLKP (pin 10)
and CLKM (pin 11) to CM (pin 17), as shown in
Figure 43.
POWER-DOWN
The device enters power-down in one of two ways:
either by reducing the clock speed or by setting the
PDN bit throught the serial programming interface.
Using the reduced clock speed, power-down may be
initiated for clock frequency below 2 MSPS. The
exact frequency at which the power down occurs
varies from device to device.
CM
CM
5 kW
Using the serial interface PDN bit to power down the
device places the outputs in a high-impedance state
and only the internal reference remains on to reduce
the power-up time. The power-down mode reduces
power dissipation to approximately 180 mW.
5 kW
CLKM
CLKP
REFERENCE CIRCUIT
The ADS5522 has built-in internal reference
generation, requiring no external circuitry on the
printed circuit board (PCB). For optimum
performance, it is best to connect both REFP and
REFM to ground with a 1-µF decoupling capacitor
(the 1-Ω resistor shown in Figure 42 is optional). In
addition, an external 56.2-kΩ resistor should be
6 pF
3 pF
3 pF
Figure 43. Clock Inputs
24
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When driven with a single-ended CMOS clock input,
it is best to connect CLKM (pin 11) to ground with a
0.01-µF capacitor, while CLKP is ac-coupled with a
0.01-µF capacitor to the clock source, as shown in
Figure 44.
100
95
90
85
80
75
70
65
60
fIN = 20MHz
SFDR
Square Wave
or Sine Wave
CLKP
(3 V )
PP
0.01 mF
ADS5522
CLKM
SNR
0.01 mF
35
40
45
50
55
%
60
65
−
Clock Duty Cycle
Figure 44. AC-Coupled, Single-Ended Clock Input
The ADS5522 clock input can also be driven
Figure 46. AC Performance vs Clock Duty Cycle
differentially,
reducing
susceptibility
to
common-mode noise. In this case, it is best to
connect both clock inputs to the differential input
clock signal with 0.01-µF capacitors, as shown in
Figure 45.
Bandpass filtering of the source can help produce a
50% duty cycle clock and reduce the effect of jitter.
When using a sinusoidal clock, the clock jitter further
improves as the amplitude is increased. In that
sense, using a differential clock allows for the use of
larger amplitudes without exceeding the supply rails
and absolute maximum ratings of the ADC clock
input. Figure 47 shows the performance variation of
the device versus input clock amplitude. For detailed
clocking schemes based on transformer or
PECL-level clocks, see the ADS5522EVM User's
Guide (SLWU010), available for download from
www.ti.com.
0.01 mF
CLKP
Differential Square Wave
or Sine Wave
(3 V )
PP
ADS5522
CLKM
0.01 mF
Figure 45. AC-Coupled, Differential Clock Input
95
For high input frequency sampling, it is
recommended to use a clock source with low jitter.
Additionally, the internal ADC core uses both edges
of the clock for the conversion process. This means
that, ideally, a 50% duty cycle should be provided.
Figure 46 shows the performance variation of the
ADC versus clock duty cycle.
fIN = 70MHz
90
85
SFDR
80
75
SNR
70
65
60
0
0.5
1.0
1.5
2.0
2.5
3.0
−
Differential Clock Amplitude
V
Figure 47. AC Performance vs Clock Amplitude
25
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SBAS320C–MAY 2004–REVISED FEBRUARY 2007
OUTPUT INFORMATION
The output circuitry of the ADS5522, by design,
minimizes the noise produced by the data switching
transients, and, in particular, its coupling to the ADC
analog circuitry. Output D2 (pin 51) senses the load
capacitance and adjusts the drive capability of all the
output pins of the ADC to maintain the same output
slew rate described in the timing diagram of Figure 1.
Care should be taken to ensure that all output lines
(including CLKOUT) have nearly the same load as
D2 (pin 51). This circuit also reduces the sensitivity
of the output timing versus supply voltage or
temperature. Placing external resistors in series with
the outputs is not recommended.
The ADC provides 12 data outputs (D11 to D0, with
D11 being the MSB and D0 the LSB), a data-ready
signal (CLKOUT, pin 43), and an out-of-range
indicator (OVR, pin 64) that equals 1 when the
output reaches the full-scale limits.
Two different output formats (straight offset binary or
two's complement) and two different output clock
polarities (latching output data on rising or falling
edge of the output clock) can be selected by setting
DFS (pin 40) to one of four different voltages.
Table 3 details the four modes. In addition, output
enable control (OE, pin 41, active high) is provided to
put the outputs into a high-impedance state.
The timing characteristics of the digital outputs
change for sampling rates below the 80 MSPS
maximum sampling frequency. Table 5 and Table 6
show the values of various timing parameters at
lower sampling frequencies.
In the event of an input voltage overdrive, the digital
outputs go to the appropriate full-scale level. For a
positive overdrive, the output code is 0xFFF in
straight offset binary output format and 0x7FF in
two's complement output format. For a negative input
overdrive, the output code is 0x000 in straight offset
binary output format and 0x800 in two's complement
output format. These outputs to an overdrive signal
are ensured through design and characterization.
To use the input clock as the data capture clock, it is
necessary to delay the input clock by a delay, td, that
results in the desired setup or hold time. Use either
of the following equations to calculate the value of td.
Desired setup time = td – tSTART
Desired hold time = tEND – td
Table 5. Timing Characteristics at Additional Sampling Frequencies
tsu (ns)
th (ns)
tSTART (ns)
tEND (ns)
tr (ns)
tf (ns)
fS
(MSPS)
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
65
40
20
10
2
4.7
8.5
17
6.0
11
2.1
2.8
2.5
4
3.1
3.5
4.7
6.5
19
2.4
-1
4.2
1.5
2
8.3
8.9
12.0
14.5
21.6
31
6.6
7.5
7.5
7.2
8
5.5
7.3
7.6
6.4
7.8
8
25.7
51
-9.8
-30
185
9.5
8
27
-3
11.5
515
284
370
8
320
576
50
82
75
150
Table 6. Timing Characteristics at Additional Sampling Frequencies
CLKOUT, Rise Time
tr (ns)
CLKOUT, Fall Time
tf (ns)
CLKOUT Jitter, Peak-to-Peak
tJIT (ps)
Input-to-Output Clock Delay
tPDI (ns)
fS
(MSPS)
MIN
TYP
3.1
4.8
8.3
MAX
3.5
MIN
TYP
2.6
4
MAX
2.9
MIN
TYP
260
445
800
MAX
380
MIN
7.8
9.5
13
TYP
8.5
MAX
9.4
65
40
20
10
2
5.3
4.4
650
10.4
15.5
20.7
551
11.4
18
9.5
7.6
8.2
1200
16
25.5
567
31
52
36
65
2610
4400
537
26
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SBAS320C–MAY 2004–REVISED FEBRUARY 2007
SERIAL PROGRAMMING INTERFACE
The PowerPAD package is designed so that the lead
frame die pad (or thermal pad) is exposed on the
bottom of the IC. This provides a low thermal
resistance path between the die and the exterior of
the package. The thermal pad on the bottom of the
IC can then be soldered directly to the printed circuit
board (PCB), using the PCB as a heatsink.
The ADS5522 has internal registers for the
programming of some of the modes described in the
previous sections. The registers should be reset after
power-up by applying a 2 µs (minimum) high pulse
on RESET (pin 35); this also resets the entire ADC
and sets the data outputs to low. This pin has a
200-kΩ internal pullup resistor to AVDD
programming is done through a three-wire interface.
.
The
Assembly Process
1. Prepare the PCB top-side etch pattern
including etch for the leads as well as the
thermal pad as illustrated in the Mechanical
Data section. The recommended thermal pad
dimension is 8 mm x 8 mm.
Table 2 shows the different modes and the bit values
to be written to the register to enable them.
Note that some of these modes may modify the
standard operation of the device and possibly vary
the performance with respect to the typical data
shown in this data sheet.
2. Place a 5-by-5 array of thermal vias in the
thermal pad area. These holes should be 13
mils in diameter. The small size prevents
wicking of the solder through the holes.
Applying a RESET signal is absolutely essential to
set the internal registers to their default states for
normal operation. If the hardware RESET function is
not used in the system, the RESET pin must be tied
to ground and it is necessary to write the default
values to the internal registers through the serial
programming interface. The registers must be written
in the following order.
3. It is recommended to place a small number of
25 mil diameter holes under the package, but
outside the thermal pad area to provide an
additional heat path.
4. Connect all holes (both those inside and
outside the thermal pad area) to an internal
copper plane (such as a ground plane).
Write 9000h (Address 9, Data 000)
Write A000h (Address A, Data 000)
Write B000h (Address B, Data 000)
Write C000h (Address C, Data 000)
Write D000h (Address D, Data 000)
Write E000h (Address E, Data 804)
Write 0000h (Address 0, Data 000)
Write 1000h (Address 1, Data 000)
Write F000h (Address F, Data 000)
5. Do not use the typical web or spoke via
connection pattern when connecting the
thermal vias to the ground plane. The spoke
pattern increases the thermal resistance to the
ground plane.
6. The top-side solder mask should leave
exposed the terminals of the package and the
thermal pad area.
7. Cover the entire bottom side of the PowerPAD
vias to prevent solder wicking.
NOTE:
8. Apply solder paste to the exposed thermal
pad area and all of the package terminals.
This procedure is only required if a RESET pulse
is not provided to the device.
For more detailed information regarding the
PowerPAD package and its thermal properties, see
either the application brief SLMA004B (PowerPAD
Made Easy) or technical brief SLMA002 (PowerPAD
Thermally Enhanced Package).
PowerPAD PACKAGE
The PowerPAD package is a thermally enhanced
standard size IC package designed to eliminate the
use of bulky heatsinks and slugs traditionally used in
thermal packages. This package can be easily
mounted using standard printed circuit board (PCB)
assembly techniques and can be removed and
replaced using standard repair procedures.
27
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ADS5522 Revision history
Revision
Date
02/05
04/06
Description
A
B
Production data sheet released
Added notes regarding the input voltage overstress requirements in the absolute max ratings table
Changed minimum recommended sampling rate to 2 MSPS
Clarified the Electrical Characteristics measurement conditions
Added min VOH and max VOL specifications
Added data valid with respect to the input clock, output clock jitter, wakeup time, output clock rise
and fall time and clock propagation delay timings
Clarified output capture test modes in Table 2
Updated the definitions section
Clarified measurement conditions for the specifications plots
Updated the Power Down section to reflect the newly specified 2 MSPS minimum sampling rate
Timings specified at various sampling speeds in Table 5 and Table 6
Information added in pin assignment table for pins RESET, OE, SEN, SDATA and SCLK
Removed the input voltage stress section
In serial programming section, note added about mandatory RESET
Latency spec corrected in timing diagram and timing table to 17.5 clocks
Added min/max spec for offset and gain error
C
02/07
28
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Feb-2007
PACKAGING INFORMATION
Orderable Device
ADS5522IPAP
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
HTQFP
PAP
64
64
64
64
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
ADS5522IPAPG4
ADS5522IPAPR
ADS5522IPAPRG4
HTQFP
HTQFP
HTQFP
PAP
PAP
PAP
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS5522IPAPR
HTQFP
PAP
64
1000
330.0
24.4
13.0
13.0
1.5
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTQFP PAP 64
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 41.0
ADS5522IPAPR
1000
Pack Materials-Page 2
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