ADS61JB23IRHAT [TI]
12-Bit Input-Buffered 80 MSPS ADC with JESD204A Output Interface; 12位输入缓冲80 MSPS ADC，具有JESD204A输出接口
| 型号： | ADS61JB23IRHAT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12-Bit Input-Buffered 80 MSPS ADC with JESD204A Output Interface |
| 文件： | 总45页 (文件大小：1378K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS61JB23
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SLOS755 –DECEMBER 2012
12-Bit Input-Buffered 80 MSPS ADC with JESD204A Output Interface
Check for Samples: ADS61JB23
1
FEATURES
APPLICATIONS
•
Output Interface:
•
•
Wireless Base-station Infrastructure
Test and Measurement Instrumentation
–
–
–
–
Single-Lane and Dual-Lane Interfaces
Maximum Data Rate of 1.6 Gbps
Meets JESD204A Specification
CML Outputs with Current Programmable
from 2 mA – 32 mA
•
Power Dissipation:
–
–
440 mW at 80 MSPS in Single Lane Mode
Power Scales Down with Clock Rate
•
•
•
•
Input Interface: Buffered Analog Inputs
71.7 dBFS SNR at 70 MHz IF
Analog Input FSR: 2 Vpp
External and Internal (trimmed) Reference
Support
•
1.8V Supply (Analog and digital), 3.3 V Supply
for Input Buffer
•
•
Programmable Digital Gain: 0dB – 6dB
Straight Offset Binary or Twos Complement
Output
•
Package:
–
6 mm x 6 mm QFN-40
DESCRIPTION
The ADS61JB23 is a high-performance, low-power, single channel analog-to-digital converter with an integrated
JESD204A output interface. Available in a 6 mm x 6 mm QFN package, with both single-lane and dual-lane
output modes, the ADS61JB23 offers an unprecedented level of compactness. The output interface is compatible
to the JESD204A standard, with an additional mode (as per IEEE Std 802.3-2002 part3, Clause 36.2.4.12) to
interface seamlessly to the TI TLK family of SERDES transceivers. Equally impressive is the inclusion of an on-
chip analog input buffer, providing isolation between the sample/hold switches and higher and more consistent
input impedance.
The ADS61JB23 is specified over the industrial temperature range (–40°C to 85°C).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADS61JB23
SLOS755 –DECEMBER 2012
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
CLOCKGEN
PLL
10X 20X
CML
/
OUTPUTS
ADC_OUTP<0>
ADC_OUTM<0>
INP
INM
JESD204A
Digital
12 bit ADC
Buffer
ADC_OUTP<1>
ADC_OUTM<1>
Signal level
detect
OVR
DETECT<3:0>
CONTROL
INTERFACE
VCM
REFERENCE
CMOS
OUTPUTS
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RHA PACKAGE
(TOP VIEW)
40
39
38
37
36
35
34
33
32
31
DRVDD
1
2
30
29
28
27
26
25
24
23
SYNC~M
Pad is connected to DRGND
DRGND
SYNC~P
DFS_EXTREF
PDN_ANA
3
SDOUT_TEST1
4
DRVDD
5
RESET
AVDD
AGND
CLKP
CLKM
40 QFN
SCLK_SERF0_SCR
6
7
SDATA_TEST0
SEN_FALIGN_IDLE
8
9
22 AVDD
21 PDN
AGND
VCM
10
11
12
13
14
15
16
17
18
19
20
PIN FUNCTIONS
PIN
DESCRIPTION
NAME
NO.
31
ADC_OUTM<1>
ADC_OUTM<0>
ADC_OUTP<1>
ADC_OUTP<0>
CML output Lane 2 – Negative output
CML output Lane 1 – Negative output
CML output Lane 2 – Positive output
CML output Lane 1 – Positive output
34
32
35
5, 6, 9, 11, 14,
16,
AGND
Analog ground
AVDD
15, 18, 22
Analog supply, 1.8 V
AVDD_3V
CLKM
17
8
Analog supply for input buffer, 3.3 V
Conversion clock – Negative input
Conversion clock – Positive input
Digital ground
CLKP
7
DRGND
DRVDD
29
27, 30
Digital supply, 1.8 V
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PIN FUNCTIONS (continued)
PIN
DESCRIPTION
NAME
DETECT<3>
DETECT<2>
DETECT<1>
DETECT<0>
DFS_EXTREF
FAVDD
NO.
36
37
38
39
3
Signal level detect output pins: Can be used to either output a 4-bit ADC code with low latency or to
output a 16-level RMS power estimate
4-level analog control for Data Format select and Internal/ External reference mode
Fuse supply – connect externally to AVDD, 1.8 V
CML buffer supply – 1.2 V to 1.9 V
20
33
13
12
19
40
21
IOVDD
INM
Analog input - Negative
INP
Analog input – Positive
MODE
4-level control for Serial interface/ Parallel interface modes selection
Over-range output
OVR
PDN
Full chip Powerdown (also referred to as Complete Powerdown mode)
Analog section power down, JESD interface still active. This is referred to as fast recovery powerdown
mode
PDN_ANA
4
RESET
26
25
24
28
Chip Reset input
SCLK_SERF0_
SCR
In Serial interface mode : Serial clock input In parallel interface mode : 4-level control for JESD modes
(single/dual lane & scrambling)
SDATA_TEST0
In Serial interface mode : Serial data input In parallel interface mode : JESD test mode
In Serial interface mode : Serial data output (for register readout) In parallel interface mode : JESD test
mode
SDOUT_TEST1
SEN_FALIGN_I
DLE
In Serial interface mode : Serial enable (Chip select) In parallel interface mode : 4-level control for
JESD modes
23
SYNC~M
SYNC~P
1
2
JESD Synchronization request – Negative input
JESD Synchronization request – Positive input
Common mode output for setting input common mode: 1.95V, Reference input in external reference
mode
VCM
10
ABSOLUTE MAXIMUM RATINGS(1)
VALUE
–0.3 to +2.2
UNIT
V
AVDD
DRVDD
–0.3 to +2.2
V
Supply voltage range
IOVDD
–0.3 to +2.2
V
AVDD_3V
–0.3 to +3.9
V
Voltage between AGND and DRGND
Voltage applied to external VCM pin
Voltage applied to analog input pins
Voltage applied to digital input pins
Voltage applied to clock input pins(2)
–0.3 to +0.3
V
–0.3 to +2.2
V
–0.3 to min (3, AVDD_3V + 0.3)
–0.3 to AVDD + 0.3
–0.3 to AVDD + 0.3
–40 to 85
V
V
V
TA
Operating free-air temperature range
Peak solder temperature
°C
°C
°C
260
Junction temperature
105
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability.
(2) When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP, CLKM is less than |0.3V|.
This prevents the ESD protection diodes at the clock input pins from turning on.
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THERMAL INFORMATION
ADS61JB23
THERMAL METRIC(1)
UNITS
QFN 40 PIN
θJA
Junction-to-ambient thermal resistance
30.7
17
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
5.7
0.2
5.7
1
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
θJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX UNIT
SUPPLIES, ANALOG INPUTS AND REFERENCE VOLTAGES
Analog supply voltage, AVDD
1.7
1.7
1.2
3.0
1.8
1.8
1.8
3.3
2
1.9
1.9
1.9
3.6
V
V
Digital supply voltage, DRVDD
CML buffer supply voltage, IOVDD
V
Analog buffer supply voltage, AVDD_3V
Differential input voltage range
V
VPP
VCM
±0.05
Input common-mode voltage
V
VCM (output) – Internal reference mode(1)
VCM (input) – External reference mode
CLOCK INPUT
1.95
1.4
V
V
Input clock rate in JESD204A single lane mode
Input clock rate in JESD204A dual lane mode
15.625
31. 25
0.2
80 MSPS
80 MSPS
VPP
Sine wave, ac-coupled
3.0
1.6
LVPECL, ac-coupled
VPP
Input clock amplitude differential (VCLKP
-
VCLKM
)
LVDS, ac-coupled
0.7
VPP
CMOS, single-ended, ac-coupled
1.5
V
Input clock duty cycle
DIGITAL OUTPUTS
35%
50%
65%
20x
Output data rate in single-lane mode
Output data rate in dual-lane mode
312.5 (sample
rate)
1600 MBPS
800 MBPS
10x
312.5 (sample
rate)
CLOAD
RLOAD
TA
Maximum external load capacitance from each pin to DRGND
External termination from each output pin to IOVDD
Operating free-air temperature
5
pF
50
Ω
-40
85
°C
HIGH SFDR MODE
Write register 2h, value 71h to get best HD3 for input frequencies between 150MHz to
250MHz.
(1) Typical VCM reduces to 1.85V after HIGH SFDR MODE is written.
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ELECTRICAL CHARACTERISTICS
Typical values at 25°C, MIN and MAX values are across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD =
1.8V, AVDD_3V = 3.3V, DRVDD = 1.8V, IOVDD = 1.8V, Clock frequency = 80MSPS, 50% clock duty cycle, –1dBFS
differential analog input, internal reference mode, CML buffer current setting = 16 mA, unless otherwise noted.
PARAMETER
REFERENCE VOLTAGES – INTERNAL
VCM analog input common mode voltage (output)
VCM output current (resulting in a VCM change of ±50 mV)
REFERENCE VOLTAGES – EXTERNAL
VCM reference voltage (Input)
ANALOG INPUT
TEST CONDITIONS
MIN
TYP MAX UNIT
1.95
2.5
V
mA
1.4±0.1
V
Differential input voltage range
Differential input capacitance
2.0
Vpp
pF
3
480
Analog input bandwidth
MHz
V
Analog input common mode range
Analog input common mode current (per input pin)
DC ACCURACY
VCM±0.05
1.6
µA
Offset error
–20
20
mV
Due to internal reference
inaccuracy alone
–2.5
2.5 %FS
Gain error
Due to channel alone
5
0.006
>30
%FS
mV/°C
dB
Gain error temperature coefficient
AC Power Supply Rejection Ratio, PSRR
POWERDOWN MODES
Complete powerdown mode
Fast recovery powerdown mode
Power with no clock
50 mVPP signal on AVDD supply
10
210
115
±0.3
mW
mW
mW
DNL differential nonlinearity
INL integral nonlinearity
POWER SUPPLY CURRENTS
AVDD current
–0.7
0.8
LSB
LSB
±0.7 ±1.5
105 122
mA
mA
mA
mA
mW
AVDD_3V current
40
50
16
51
61
21
DRVDD current
IOVDD current
Total power
440 500
DYNAMIC PERFORMANCE(1)
IF = 10 MHz
IF = 185 MHz
IF = 10 MHz
IF = 185 MHz
IF = 10 MHz
IF = 185 MHz
IF = 10 MHz
IF = 185 MHz
IF = 10 MHz
IF = 185 MHz
IF = 10 MHz
IF = 185 MHz
80
80
dBc
dBc
SFDR
SNR
70
68
71.7
70.5
71.2
70.1
80
dBFs
dBFs
dBFs
dBFs
dBc
SINAD
HD3
70
70
81
80
dBc
100
80
dBc
HD2
dBc
90
dBc
Worst spur (excluding HD2, HD3)
(1) HIGH SFDR MODE is enabled.
87
dBc
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DIGITAL CHARACTERISTICS
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1
PARAMETER
DIGITAL INPUTS
TEST CONDITIONS
MIN
TYP MAX
UNIT
High-level input voltage
Low-level input voltage
1.2
V
V
0.6
SEN
0
10
10
0
High-level input current
Low-level input current
μA
μA
SCLK, SDATA, RESET, PDN, PDN_ANA
SEN
SCLK, SDATA, RESET, PDN, PDN_ANA
DIGITAL OUTPUTS (SDOUT)
High-level output voltage
Low-level output voltage
DRVDD-
0.1
DRVDD
V
V
0
0.1
1.9
CML OUTPUTS – 50 Ω SINGLE-ENDED EXTERNAL TERMINATION TO IOVDD
IOVDD supply range
1.2
1.8
V
V
High-level output voltage
IOVDD
IOVDD-
0.4
Low-level output voltage
V
V
V
Output differential voltage, |VOD|
Output common-mode voltage, VOCM
0.4
IOVDD-
0.2
Transmitter terminals shorted to any voltage between
Transmitter short circuit current
–0.25V and 1.45V
-90
50
mA
Single-ended output impedance
Unit interval, UI
50
Ω
UI
625
3200
Total Jitter, TJ
0.35
175
p-pUI
ps
Rise/ fall times
5 pF single-ended load capacitance to ground
WAKE-UP TIMING CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
TYP
50
50
10
5
MAX UNIT
Time to valid data after coming out of COMPLETE POWERDOWN mode
Time to valid data after coming out of FAST RECOVERY POWERDOWN mode
Time to valid data after coming out of SOFTWARE POWERDOWN mode
Time to valid data after stopping and restarting the input clock
μs
μs
μs
μs
Wake-up time
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DETAILED DESCRIPTION
JESD204A OUTPUT INTERFACE
The 12-bit ADC output is padded with 4 zeros on the LSB side to form a 16-bit output. Two 8B10B codes are
formed – one from the 8 MSBs and the other from the 6 LSBs and the 2 padded zeros .
ADCOUT<3:0>,0,0,0,0
ADCOUT<11:4>
8B10B code1
MSB octet
8B10B code2
LSB octet
Figure 1. Mapping of ADC Output to Two 8B10B Codes
The two octets can be either transmitted on the same lane (single lane interface) or on two lanes (dual lane
interface). By default, the device operates in single lane interface.
Conversion clock
(CLKP-CLKM)
CML output Lane1
(ADC_OUTP<0> -
Dx.y
(ADC data N, MSB octet)
Dx.y
(ADC data N, LSB octet)
Dx.y Dx.y
(ADC data N+1, MSB octet) (ADC data N+1, LSB octet)
ADC_OUTM<0>)
Figure 2. Single Lane Timing
Conversion clock
(CLKP-CLKM)
CML output Lane1
(ADC_OUTP<0> -
ADC_OUTM<0>)
Dx.y
(ADC data N, MSB octet)
Dx.y
Dx.y
(ADC data N+1, MSB octet) (ADC data N+2, MSB octet) (ADC data N+3, MSB octet)
Dx.y
CML output Lane2
(ADC_OUTP<1> -
ADC_OUTM<1>)
Dx.y
(ADC data N, LSB octet)
Dx.y
(ADC data N+1, LSB octet)
Dx.y Dx.y
(ADC data N+2, LSB octet) (ADC data N+3, LSB octet)
Figure 3. Dual Lane Timing
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The detailed timing diagram in the dual lane mode is shown below:
N+22
N+3
N+4
N+21
N+2
N+1
N+20
Sample
N
INPUT
SIGNAL
t a
CLKP
CLKM
INPUT
CLOCK
20 clock cycles *
t PDI
CML OUTPUT
DATA LANE 1
N-20
N-20
N-21
N-21
N-19
N-19
N-18
N-18
N-1
N-1
N-17
N-17
N
N
N+1
N+1
N+2
N+2
CML OUTPUT
DATA LANE 2
* This is the ADC latency. At higher sampling frequencies, t PDI > 1 clock cycle.
Then, overall latency = ADC latency + 1.
Figure 4. Data Timing Diagram - Dual Lane Mode
PARAMETER
30 MSPS
560 ps
40 MSPS
560 ps
60 MSPS
560 ps
80 MSPS
560 ps
Aperture delay – TA
Aperture jitter (RMS) – TJ
Latency
125 fs
125 fs
125 fs
125 fs
20 clocks
33.3 ns
20 clocks
26.2 ns
20 clocks
18.9 ns
20 clocks
15.3 ns
tPDI Data propagation delay
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Whenever there is a need to synchronize to the frame boundary of the output data stream, the receiver issues a
synchronization request through the SYNC~P, SYNC~M pins. Below diagram shows how the transmission
switches from normal data (D) to code group synchronization symbols K28.5 symbols during and after a
synchronization request.
N+9
N+8
N+7
N+5
N+6
N+4
N+3
N+2
N+1
Sample
N
INPUT
SIGNAL
CLKP
CLKM
INPUT
CLOCK
tCLK-INT
INTERNAL CLOCK
FOR LATCHING SYNC~
(CLK_INT)
tSYNC-
t SYNC-H
SYNC ~input
(SYNC~P)-(SYNC~M)
tSYNC-PDI
‘SYNC~ active’ latency = 9 clock cycles
CML OUTPUT
DATA LANE1
N-21
N-21
N-20
N-20
N-13
N-13
N-19
N-19
N-18
N-18
K28.5
K28.5
N-12
N-12
N-17
N-17
N-16
N-16
N-14
N-14
N-15
N-15
CML OUTPUT
DATA LANE 2
Figure 5. SYNC~ ACTIVE Timing Diagram
Table 1. SYNC~ Falling Edge Timing at 80 MSPS
PARAMETER
DESCRIPTION
TYP
UNIT
Delay from input clock rising edge to the rising edge of the internal clock
(CLK_INT) used to latch falling edge of SYNC~
tCLK-INT
10.5
ns
tSYNC-SU SYNC~ active edge setup time Minimum delay required from SYNC~ falling edge to CLK_INT rising edge
tSYNC-H SYNC~ active edge hold time Minimum delay required from CLK_INT rising edge to SYNC~ falling edge
2
2
ns
ns
SYNC~ active latency
Number of clocks for K28.5 to appear at the output after a SYNC~ request
Similar to data propagation delay
9
clocks
ns
tSYNC-PDI SYNC~ data propagation
delay
15.3
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N+8
N+7
N+5
N+6
N+4
N+3
N+2
N+1
Sample
N
INPUT
SIGNAL
CLKP
CLKM
INPUT
CLOCK
tCLK-INT
INTERNAL CLOCK
FOR LATCHING SYNC
(CLK_INT)
tSYNCZ-SU
t SYNCZ-H
SYNC~ input
(SYNC~P)-(SYNC~M)
tSYNCZ-PDI
‘SYNC~ de-active’ latency = 8 clock cycles
CML OUTPUT
DATA LANE 1
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
N-12
N-12
N-11
N-11
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
CML OUTPUT
DATA LANE 2
K28.5
Figure 6. SYNC~ DE-ACTIVE Timing Diagram
Table 2. SYNC~ Rising Edge Timing at 80 MSPS
PARAMETER
DESCRIPTION
TYP
UNIT
Delay from input clock rising edge to the rising edge of the internal
clock (CLK_INT) used to latch rising edge of SYNC~
10.5
ns
tCLK-INT
tSYNCZ-SU
SYNC~ active edge setup time Minimum delay required from SYNC~ rising edge to CLK_INT rising
edge
2
2
ns
ns
tSYNCZ-H
SYNC~ active edge hold time Minimum delay required from CLK_INT rising edge to SYNC~ rising
edge
SYNC~ de-active latency
Number of clocks for normal data to appear at the output after a
SYNC~ de-activate request
8
clocks
ns
tSYNCZ-PDI SYNC~ de-active data
propagation delay
Similar to data propagation delay
15.3
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4-LEVEL CONTROL
In the ADS61JB23 the DFS_EXTREF and MODE pins function as 4-level control pins as described in Table 3
and Table 4. A simple scheme to generate 4-level voltage is shown in Figure 7.
AVDD
(5/8)AVDD
3R
(5/8)AVDD
2R
AVDD
GND
(3/8)AVDD
3R
To parallel pin
(3/8)AVDD
GND
Figure 7. Simple Scheme to Configure 4-Level Control Pins
Table 3. Pin 3 – DFS_EXTREF
DFS_EXTREF
DESCRIPTION
0
EXTREF = 0, DFS = 0
+150 mV/–0 mV
(3/8)AVDD
±150 mV
EXTREF = 1, DFS = 0
EXTREF = 1, DFS = 1
EXTREF = 0, DFS = 1
(5/8)AVDD
±150 mV
AVDD
+0 mV/–150 mV
Key:
EXTREF: 0 = Internal reference mode,
1 = External reference mode.
1 = Offset binary output.
DFS:
0 = 2's complement output,
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PARALLEL INTERFACE MODE
The ADS61JB23 operates in parallel interface mode when a suitable voltage is applied on the MODE pin as
described in Table 4. In parallel interface mode, the SEN, SDATA, SCLK, and SDOUT pins function differently
compared to serial interface mode. In this mode, the SEN_FALIGN_IDLE and SCLK_SERF0_SCR pins turn into
4-level control pins for JESD interface as described in Table 5 and Table 6, whereas the SDATA_TEST0 and
SDOUT_TEST1 pins turn into 2-level control pins as described in Table 7.
Table 4. Pin 19 - Mode
MODE
DESCRIPTION
0
Serial interface mode. Pins 23, 24 and 25 are configured as SEN, SDATA, SCLK. Pins 36, 37, 38, 39 are
configured to output either early signal estimate or signal power estimate – selection is based on register settings.
+150 mV/–0 mV
(3/8)AVDD
±150 mV
Do not use
(5/8)AVDD
±150 mV
Parallel interface mode. Pins 23, 24 and 25 are configured as parallel input pins for controlling JESD204A modes.
Pins 36,37,38, 39 outputs early signal estimate always.
AVDD
+0 mV/–150 mV
Do not use.
Table 5. Pin 23 - SEN_FALIGN_IDLE (in Parallel Interface Mode)
SEN_FALIGN_IDLE
DESCRIPTION
0
FALIGN = 0, IDLE = 0
FALIGN = 1, IDLE = 0
FALIGN = 1, IDLE = 1
FALIGN = 0, IDLE = 1
+150 mV/–0 mV
(3/8)AVDD
±150 mV
(5/8)AVDD
±150 mV
AVDD
+0 mV/–150 mV
Key:
When the last octet of the current frame is the same as the last octet of the previous frame, then FALIGN determines
whether the last octet of the current frame is transmitted as is, or replaced by a K28.7 control symbol. When FALIGN=0, it is
transmitted as is. When FALIGN=1, it is replaced with a K28.7 control symbol.
FALIGN:
IDLE:
IDLE determines the synchronization characters transmitted during and immediately after a SYNC event. When IDLE=0, the
device transmits K28.5 as per the JESD204A spec. When IDLE=1, the device alternately transmits K28.5 and D5.6/D16.2
characters as per IEEE Std 802.3-2002 part3, Clause 36.2.4.12. This is the case in both single and dual lane modes.
Table 6. Pin 25 - SCLK_SERF0_SCR (in Parallel Interface Mode)
SCLK_SERF0_SCR
DESCRIPTION
0
SERF0 = 0, SCR = 0
SERF0 = 1, SCR = 0
SERF0 = 1, SCR = 1
SERF0 = 0, SCR = 1
+150 mV/–0 mV
(3/8)AVDD
±150 mV
(5/8)AVDD
±150 mV
AVDD
+0 mV/–150 mV
Key:
SERF0: Output serialization factor. When SERF0=0, the device transmits 2 octets per frame (entire ADC channel in a single lane) with an
output serialization factor of 20. When SERF0=1, the device transmits 1 octet per frame (ADC channel over 2 lanes) with an
output serialization factor of 10.
SCR:
SCR=0: Scrambling disabled. SCR=1: Scrambling (as per JESD204A) enabled
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Table 7. Pins 24 and 28 - SDATA_TEST0 and SDOUT_TEST1 (in Parallel Interface Mode)
TEST1
TEST0
MODE
Normal mode. Input to JESD204A encoder is ADC data
Input to JESD204A encoder is B5B5. Output is a stream of D21.5 (alternating 1 and 0)
Input to JESD204A encoder is FF00
Input to JESD204A encoder is a pseudo random pattern 1+ X14 + X15 (irrespective of whether scrambler
is enabled or not)
0
0
1
1
0
1
0
1
SERIAL INTERFACE
The ADC has a set of internal registers, which can be accessed by the serial interface formed by pins Serial
interface Enable (SEN), Serial Interface Clock (SCLK) and Serial Interface Data (SDATA).
Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge
of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge
when SEN is low. In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be
loaded in multiple of 16-bit words within a single active SEN pulse.
The first 8 bits form the register address and the remaining 8 bits are the register data. The interface can work
with SCLK frequency from 20 MHz down to very low speeds (few Hertz) and also with non-50% SCLK duty
cycle.
REGISTER INITIALIZATION
After power-up, the internal registers MUST be initialized to their default values. This can be done in one of two
ways:
1. Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10ns) as
shown in Figure 8
OR
2. By applying software reset. Using the serial interface, set the S_RESET bit (D1 in register 0x00) to HIGH.
This initializes internal registers to their default values and then self-resets the S_RESET bit to LOW. In this
case the RESET pin is kept LOW.
Register Address
A4 A3
Register Data
D4 D3
SDATA
SCLK
SEN
A7
A6
A5
A2
A1
A0
D7
D6
D5
D2
tDH
D1
D0
tSCLK
tDSU
tSLOADS
tSLOADH
RESET
T0109-04
Figure 8. Serial Interface Timing
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SERIAL INTERFACE TIMING CHARACTERISTICS
Typical values at 25°C, MIN and MAX values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 1.8V,
DRVDD = 1.8V, unless otherwise noted.
PARAMETER
MIN TYP
MAX UNIT
fSCLK
tSLOADS
tSLOADH
tDS
SCLK frequency (= 1/ tSCLK
SEN to SCLK setup time
SCLK to SEN hold time
SDATA setup time
)
> DC
25
20
MHz
ns
25
ns
25
ns
tDH
SDATA hold time
25
ns
Serial Register Readout
The device includes an option where the contents of the internal registers can be read back. This may be useful
as a diagnostic check to verify the serial interface communication between the external controller and the ADC.
1. First, set register bit <SERIAL READOUT> = 1. This also disables any further writes into the registers
(EXCEPT register bit <SERIAL READOUT> itself).
2. Initiate a serial interface cycle specifying the address of the register (A7-A0) whose content has to be read.
3. The device outputs the contents (D7-D0) of the selected register on SDOUT_TEST1 pin.
4. The external controller can latch the contents at the falling edge of SCLK.
5. To enable register writes, reset register bit <SERIAL READOUT> = 0.
RESET TIMING
Typical values at 25°C, MIN and MAX values across the full temperature range TMIN = –40°C to TMAX = 85°C, unless
otherwise noted.
PARAMETER
Power-on delay
Reset pulse width
CONDITIONS
MIN TYP
MAX UNIT
t1
t2
t3
Delay from power-up of AVDD and DRVDD to RESET pulse active
Pulse width of active RESET signal that will reset the serial registers
Delay from RESET disable to SEN active
1
ms
10
100
ns
POWER SUPPLY
AVDD, DRVDD
t
1
RESET
t
2
t
3
SEN
NOTE: A high-going pulse on RESET pin is required in case of initialization through hardware reset.
Figure 9. Reset Timing Diagram
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SERIAL INTERFACE REGISTER MAP
BIT LOCATION
MODE
(Address in Hex
<Bit location>)
DESCRIPTION
S_RESET
00<1>
Software RESET. Same function as hardware reset.
SERIAL_READOUT
HIGH SFDR MODE
00<0>
Default = 0 for serial interface write. 1 for serial readout.
2<6:4> and 2<0>
Set these bits to get best HD3 when input frequency is between 150MHz to 250MHz.
Override control of DFS_EXTREF pin in controlling DFS select mode, and control it using register bit
DFS_REG.
When ‘0’, DFS functionality determined by DFS_EXTREF pin.
When ‘1’, DFS functionality determined by DFS_REG.
DFS_OVERRIDE
DFS_REG
3C<7>
3C<6>
44<3>
44<2>
Register bit for DFS control.
When ‘0’, output format is 2’s complement.
When ‘1’, output format is offset binary.Takes effect when DFS_OVERRIDE is set to ‘1’.
Override control of DFS_EXTREF pin in controlling Internal/ External reference select mode, and control
it using register bit INT_REF_REG.
When ‘0’, Internal/ External reference mode determined by DFS_EXTREF pin.
When ‘1’, Internal/ External reference mode determined by INT_REF_REG.
INT_REF_OVERRIDE
INT_REF_REG
Register bit for Internal/ External reference mode control.
When ‘0’, Internal reference mode.
When ‘1’, External reference mode.Takes effect when INT_REF_OVERRIDE is set to ‘1’.
S_PDN
44<6>
45<7:4>
45<3>
Software powerdown.
FINE_GAIN<3:0>
BYPASS_FINE_GAIN
0-6 dB digital gain in steps of 0.5 dB. Default is 0 dB. Refer section titled “FINE GAIN CONTROL”
Digital gain bypass. When set to 1, fine gain is bypassed.
Output Test patterns:
000: ADC output data bus is input to JESD204A encoder block
001: ADC bus replaced by min code (00000000000000 in offset binary).
010: ADC bus replaced by max code (11111111111111 in offset binary).
100: ADC bus replaced by a ramping code pattern that increments by 1 LSB every 4 clocks (and folds
back to min code once max code is reached).
ADC_TEST_PAT<2:0>
TXMIT_LINKDATA_EN
45<2:0>
A0<0>
011,101,110,111: Do not use
When set to 1, initial lane alignment sequence (as per JESD204A) is sent after Code group sync in both
single lane and dual lane interfaces. When this bit is 0 (default) initial lane alignment sequence is not
transmitted.
Software Frame Align control.
Enables frame alignment monitoring. When this bit is set to 1 (with scrambling turned off) – If the last
octet in the previous frame is the same as the last octet in the current frame, then the last octet in the
current frame will be replaced with a frame alignment symbol K28.7. When this bit is 0, there is no
replacement.
S_FALIGN
A0<1>
When scrambling is ON and this bit is ‘1’: When the last scrambled octet in a frame equals 0xFC, it is
encoded as K28.7.
This bit control is similar to the FALIGN pin control.
Multi-frame Align control.
MFALIGN
A0<2>
A0<3>
Similar to frame align, this refers to multi-frame.
Multi-frame alignment symbol is K28.3.
By default, the last octet in the frame gets derived from the data octet on the LSB side. Since usually the
LSB octets switch more (frame to frame) than the MSB octets, the occurrence of consecutive “last
octets” might be rare. This might lead to infrequent occurrence of frame alignment symbols. To increase
the rate of consecutive last octets (and thereby the rate of frame and multi-frame alignment symbols),
this bit can be set to 1. Setting this bit to 1 will flip the bit order of the ADC inputs (N bits) to the
JESD204A logic. Note that the 2 zeros padded at the end to make the input to the JESD204A logic
remain unchanged.
FLIP_ADC_BUS
TESTMODE_EN
S_IDLE
A0<4>
A0<5>
Enables the transmission of test sequence mentioned in the JESD204A document.
Software idle generation control.
Normally the output during code group synchronization is K28.5. When idle_sync is set to 1, it is a K28.5
comma followed by either a D5.6 or a D16.2. This is as per IEEE Std 802.3-2002 part3, Clause
36.2.4.12 and enables compatibility with TI’s TLK family of devices.This bit control is similar to the IDLE
pin control.
S_TEST0
S_TEST1
CTRL_F
CTRL_K
S_SCR
A0<6>
A0<7>
A1<0>
A1<1>
A5<7>
These 2 bit controls are similar to the TEST1 and TEST0 pin controls.
Enables write into A6<7:0>.
Enables write into A7<4:0>.
Software Scrambling enable. This bit control is similar to the SCR pin control.
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BIT LOCATION
(Address in Hex
<Bit location>)
MODE
DESCRIPTION
Number of octets per frame. Default set to 00000001 (2-1) which is 2 octets per frame (single lane). For
2-lane output (1 octet per frame), set to 00000000. Note that to override default, CTRL_F needs to be
set to 1.
F<7:0>
K<4:0>
A6<7:0>
Number of frames per multiframe (minus 1). Default depends on value of F<7:0>.
When F=0 (10X mode): K=16 (17 frames per multiframe)
When F=1 (20X mode): K=8 (9 frames per multiframe)
Note that to override the default value of K<4:0>, CTRL_K needs to be set to 1. When CTRL_K is set to
1, the value programmed in A7<4:0> denotes the number of frames per multiframe (minus 1). For eg., to
set the number of frames per multiframe to 23, set CTRL_K=1 and A7<4:0>=10110.
A7<4:0>
CML buffer current select. Default (0000) is 16 mA.
Current is calculated as: 16 mA+16 mA×<3>–8 m×<2>–4 mA×<1>–2 mA×<0>
CML_I<3:0>
B0<3:0>
B4<3>
Replaces the output of the 8b/10b coder (corresponding to the MSB octet) with a 10-bit word specified in
OUT_WORD_LANE1<9:0>
FORCE_OUT_LANE1
OUT_WORD_LANE1<9:0>
FORCE_OUT_LANE2
B6<7:0>,
B7<7:6>
10-bit word replacing the output of the 8b/10b coder when FORCE_OUT_LANE1 is set to ‘1’
Replaces the output of the 8b/10b coder (corresponding to the LSB octet) with a 10-bit word specified in
OUT_WORD_LANE2<9:0>
B4<6>
B8<7:4>,
B9<7:2>
OUT_WORD_LANE2<9:0>
EN_SIG_EST
10-bit word replacing the output of the 8b/10b coder when FORCE_OUT_LANE2 is set to ‘1’
D6<0>
Outputs a 4-bit ADC code with low latency on pins DETECT<3:0>
Outputs a 4-bit average power estimate of input signal on DETECT<3:0>.
EN_PWR_EST
D6<5>
Power estimate is in dB scale in steps of roughly 1 dB. Refer section titled SIGNAL POWER
ESTIMATION
Determines number of samples to average for power estimation.
Programmable from 1K to 16K.
SAMPLES_PWR_EST<2:0>
D6<4:2>
REGISTER MODES
A brief summary of different register modes and their location in the digital processing flow of the ADS61JB23 is
shown in Figure 10 and Figure 11.
ADC Digital
block
ADC
(Data format,
Digital gain)
ADC test
pattern
generator
JESD test
pattern
generator
To “Frame to Octet
Coversion”
FINE_GAIN<3:0>
DFS
JESD
testmode
generator
ADC_TEST_PAT<2:0>
TEST0,TEST1
TESTMODE_EN
Figure 10. Register Modes Preceding Frame to Octet Conversion Block
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MSB octet
TXMIT_LINKDATA_EN
SYNC~
SYNC~
Decoder
To SERDES
TX
controller
ILAS
generator
1 <9:0>
OUT_WORD_LANE
8b/10b
Coder
FORCE_OUT_LANE1
Frame to
Octet
stream
Alignment
character
generator
Scrambler
LSB octet
conversion
To SERDES
OUT_WORD_LANE2 <9:0>
SCR, FALIGN,
MALIGN
FLIP_ADC_BUS
SCR
FORCE_OUT_LANE2
Figure 11. Register Modes Following Frame to Octet Conversion Block
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INITIAL LANE ALIGNMENT SEQUENCE
By default the initial lane alignment sequence is not transmitted. To enable transmission of the initial lane
alignment sequence,
For the two settings of F, the Mapping of link configuration fields to octets Table of the JESD204A spec is shown
in Table 8.
Table 8. Mapping of Link Configuration Fields to Octets
Configuration
Octet No.
MSB
6
5
4
3
2
1
LSB
F=1 (20X mode)
0
1
DID<7:0> = 00000000
X
X
X
X
X
X
X
X
BID<3:0> = 0000
LID<4:0> = 00000
L<4:0> = 00000
2
X
3
SCR<0> - set by S_SCR
4
F<7:0> = 00000001
5
X
X
X
K<4:0> = 01000 (or programmed value of A7<4:0> if CTRL_K = 1)
6
M<7:0> = 00000000
N<4:0> = 01101
7
CS<1:0>=00
X
X
X
X
8
X
X
X
X
X
N'<4:0> = 01111
9
S<4:0>=00000
10
11
12
13
HD<0>=0
CF<4:0>=00000
RES1<7:0> - Set to all 0
RES2<7:0> - Set to all 0
FCHK<7:0>
F=0 (10X mode)
0
1
DID<7:0> = 00000000
X
X
X
X
X
X
X
X
BID<3:0> = 0000
LID<4:0> = 00000 for Lane 1 and 00001 for Lane 2
L<4:0> = 00001
2
X
3
SCR<0> - set by S_SCR
4
F<7:0> = 00000000
K<4:0> = 10000 (or programmed value of A7<4:0> if CTRL_K = 1)
M<7:0> = 00000000
5
X
X
X
6
7
CS<1:0>=00
X
X
X
X
N<4:0> = 01101
8
X
X
X
X
X
N'<4:0> = 01111
9
S<4:0>=00000
10
11
12
13
HD<0>=0
CF<4:0>=00000
RES1<7:0> - Set to all 0
RES2<7:0> - Set to all 0
FCHK<7:0>
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TYPICAL CHARACTERISTICS
At +25°C, AVDD = 1.8V, AVDD_3V = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock,
1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, low-latency mode, DDR LVDS
output interface, and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode
AMPLITUDE
vs
AMPLITUDE
vs
FREQUENCY (for 20MHz IF)
FREQUENCY (for 70MHz IF)
0
−20
0
−20
SFDR = 75.6 dBc
SFDR = 75.4 dBc
SNR = 71.8 dBFS
SINAD = 70.6 dBFS
THD = 75.5 dBc
SFDR Non HD2,HD3
= 99.83 dBc
SNR = 71.6 dBFS
SINAD = 70.3 dBFS
THD = 75.1 dBc
SFDR Non HD2,HD3
= 97.9 dBc
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
Frequency (MHz)
Frequency (MHz)
G029
G030
Figure 12.
Figure 13.
AMPLITUDE
vs
AMPLITUDE
vs
FREQUENCY (for 150MHz IF)
FREQUENCY (for 300MHz IF)
0
−20
0
−20
SFDR = 85.6 dBc
SNR = 70.7 dBFS
SINAD = 70.4 dBFS
THD = 81.6 dBc
SFDR = 69.0 dBc
SNR = 68.6 dBFS
SINAD = 64.9 dBFS
THD = 66.2 dBc
SFDR Non HD2, HD3
= 88.93 dBc
SFDR Non HD2, HD3
= 85.38 dBc
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
Frequency (MHz)
Frequency (MHz)
G031
G032
Figure 14.
Figure 15.
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TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.8V, AVDD_3V = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock,
1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, low-latency mode, DDR LVDS
output interface, and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode
AMPLITUDE
AMPLITUDE
vs
vs
FREQUENCY (for TWO TONE INPUT SIGNAL)
FREQUENCY (for TWO TONE INPUT SIGNAL)
0
−10
0
−10
Each Tone at
Each Tone at
−7 dBFS Amplitude
fIN1 = 190 MHz
fIN2 = 185 MHz
−36 dBFS Amplitude
fIN1 = 190 MHz
fIN2 = 185 MHz
−20
−20
IMD3 = 82.4 dBFS
IMD3 = 104.9 dBFS
−30
−30
−40
−40
−50
−50
−60
−60
−70
−70
−80
−80
−90
−90
−100
−110
−120
−100
−110
−120
0
10
20
30
40
0
10
20
30
40
Frequency (MHz)
Frequency (MHz)
G033
G034
Figure 16.
Figure 17.
SFDR
vs
SFDR NON HD2, HD3
vs
INPUT FREQUENCY
INPUT FREQUENCY
100
95
90
85
80
75
70
65
60
55
50
104
101
98
Digital Gain = 0 dB
Digital Gain = 2 dB
Digital Gain = 6 dB
Digital Gain = 0 dB
Digital Gain = 2 dB
Digital Gain = 6 dB
95
92
89
86
83
80
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
G035
G036
Figure 18.
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.8V, AVDD_3V = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock,
1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, low-latency mode, DDR LVDS
output interface, and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode
SNR
vs
SNR
vs
INPUT FREQUENCY
AMPLITUDE
75.5
75
130
120
110
100
90
73
72
71
70
69
68
67
66
65
64
63
Input Frequency = 40 MHz
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS)
Digital Gain = 0 dB
Digital Gain = 2 dB
Digital Gain = 6 dB
74.5
74
73.5
73
80
72.5
72
70
60
71.5
71
50
40
70.5
30
−50
−40
−30
−20
−10
0
Amplitude (dBFS)
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
G038
G037
Figure 20.
Figure 21.
SFDR
vs
SNR
vs
DIGITAL GAIN
DIGITAL GAIN
105
100
95
90
85
80
75
70
65
60
55
50
74
73
72
71
70
69
68
67
66
65
64
63
20 MHz
70 MHz
150 MHz
220 MHz
270 MHz
300 MHz
400 MHz
500 MHz
20 MHz
70 MHz
150 MHz
220 MHz
270 MHz
300 MHz
400 MHz
500 MHz
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Digital Gain (dB)
Digital Gain (dB)
G039
G040
Figure 22.
Figure 23.
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TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.8V, AVDD_3V = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock,
1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, low-latency mode, DDR LVDS
output interface, and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode
SINAD
vs
SFDR
vs
DIGITAL GAIN
AVDD SUPPLY and TEMPERATURE
77
75
73
71
69
67
65
63
61
59
57
55
86
85
84
83
82
81
80
79
78
77
76
75
20 MHz
70 MHz
150 MHz
220 MHz
270 MHz
300 MHz
400 MHz
500 MHz
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.95 V
Input Frequency = 190 MHz
−15 10
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
−40
35
60
85
Digital Gain (dB)
Temperature (°C)
G041
G042
Figure 24.
Figure 25.
SNR
vs
SFDR
vs
AVDD SUPPLY and TEMPERATURE
AVDD_3V SUPPLY and TEMPERATURE
71
70.9
70.8
70.7
70.6
70.5
70.4
70.3
70.2
70.1
70
85
84
83
82
81
80
79
78
77
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.95 V
AVDD_3V = 3 V
AVDD_3V = 3.1 V
AVDD_3V = 3.2 V
AVDD_3V = 3.3 V
AVDD_3V = 3.4 V
AVDD_3V = 3.5 V
AVDD_3V = 3.6 V
Input Frequency = 190 MHz
−15 10
Input Frequency = 190 MHz
−15 10
−40
35
60
85
−40
35
60
85
Temperature (°C)
Temperature (°C)
G043
G044
Figure 26.
Figure 27.
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TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.8V, AVDD_3V = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock,
1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, low-latency mode, DDR LVDS
output interface, and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode
SNR
SFDR
vs
vs
AVDD_3V SUPPLY and TEMPERATURE
DRVDD SUPPLY and TEMPERATURE
70.8
70.7
70.6
70.5
70.4
70.3
70.2
70.1
70
85
84
83
82
81
80
79
78
AVDD_3V = 3 V
AVDD_3V = 3.1 V
AVDD_3V = 3.2 V
AVDD_3V = 3.3 V
AVDD_3V = 3.4 V
AVDD_3V = 3.5 V
AVDD_3V = 3.6 V
DRVDD = 1.75 V
DRVDD = 1.8 V
DRVDD = 1.85 V
DRVDD = 1.9 V
DRVDD = 1.95 V
69.9
Input Frequency = 190 MHz
−15 10
Input Frequency = 190 MHz
−15 10
69.8
−40
35
60
85
−40
35
60
85
Temperature (°C)
Temperature (°C)
G045
G046
Figure 28.
Figure 29.
SNR
vs
PERFORMANCE
vs
DRVDD SUPPLY and TEMPERATURE
INPUT COMMON-MODE VOLTAGE
73
72.5
72
82
81
80
79
78
77
76
75
74
73
72
71
70.9
70.8
70.7
70.6
70.5
70.4
70.3
70.2
70.1
70
Input Frequency = 40 MHz
SNR
DRVDD = 1.75 V
DRVDD = 1.8 V
DRVDD = 1.85 V
DRVDD = 1.9 V
DRVDD = 1.95 V
SFDR
71.5
71
70.5
70
69.5
69
68.5
68
1.85
Input Frequency = 190 MHz
−15 10
1.88
1.91
1.94
1.97
2
Input Common-Mode Voltage (V)
−40
35
60
85
G048
Temperature (°C)
G047
Figure 30.
Figure 31.
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TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.8V, AVDD_3V = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock,
1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, low-latency mode, DDR LVDS
output interface, and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode
PERFORMANCE
PERFORMANCE
vs
vs
INPUT COMMON-MODE VOLTAGE
EXTERNAL REFERENCE VOLTAGE
71
70.5
70
90
88
86
84
82
80
78
76
74
72
70
75.5
75
84
82
80
78
76
74
72
70
68
66
64
Input Frequency = 190 MHz
SNR
SFDR
Input Frequency = 40 MHz
SNR
SFDR
74.5
74
69.5
69
73.5
73
68.5
68
72.5
72
67.5
67
71.5
71
66.5
66
1.85
70.5
1.88
1.91
1.94
1.97
2
1.2 1.25 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7
External Reference Voltage (V)
Input Common-Mode Voltage (V)
G049
G050
Figure 32.
Figure 33.
PERFORMANCE
vs
PERFORMANCE
vs
EXTERNAL REFERENCE VOLTAGE
DIFFERENTIAL CLOCK AMPLITUDE
73.5
73
88
86
84
82
80
78
76
74
72
70
68
79
77
75
73
71
69
67
65
63
61
59
57
87
85
83
81
79
77
75
73
71
69
67
65
Input Frequency = 190 MHz
SNR
SFDR
Input Frequency = 190 MHz
SNR
SFDR
72.5
72
71.5
71
70.5
70
69.5
69
68.5
1.2 1.25 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7
External Reference Voltage (V)
0.2 0.5 0.8 1.1 1.4 1.7
2
2.3 2.6 2.9 3.2 3.5
Differential Clock Amplitude (Vpp)
G051
G052
Figure 34.
Figure 35.
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TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.8V, AVDD_3V = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock,
1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, low-latency mode, DDR LVDS
output interface, and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode
PERFORMANCE
vs
INPUT CLOCK DUTY CYCLE
75
74.5
74
78
Input Frequency = 20MHz
SNR
THD
77.5
77
73.5
73
76.5
76
72.5
72
75.5
75
71.5
71
74.5
74
70.5
70
73.5
73
20
30
40
50
60
70
80
Input Clock Duty Cycle (%)
G053
Figure 36.
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TYPICAL CHARACTERISTICS: COMMON
At +25°C, AVDD = 1.8V, AVDD_3V = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock,
1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, low-latency mode, DDR LVDS
output interface, and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode
PSRR SPECTRUM FOR AVDD SUPPLY
CMRR SPECTRUM FOR AVDD SUPPLY
0
−20
0
−20
fIN = 20 MHz
SFDR = 75.4 dBc
fPSRR = 10 MHz, 50 mVPP
Amplitude (fIN) = −1 dBFS
Amplitude (fPSRR
fIN = 20 MHz
SFDR = 75.3 dBc
fCM = 10 MHz, 50 mVPP
Amplitude (fIN) = −1 dBFS
Amplitude (fCM
fIN = 20 MHz
fIN = 20 MHz
)
)
= −104.5 dBFS
Amplitude (fIN + fPSRR
= −94.5 dBFS
= −92.8 dBFS
Amplitude (fIN + fCM
= −88.9 dBFS
)
)
−40
−40
Amplitude (fIN − fPSRR
)
Amplitude (fIN − fCM
)
= −99.4 dBFS
= −89.8 dBFS
−60
−60
fIN + fPSRR) = 30 MHz
fIN + fCM) = 30 MHz
−80
−80
fIN − fPSRR) = 10 MHz
fPSRR = 10 MHz
fIN − fCM) = 10 MHz
fCM = 10 MHz
−100
−120
−100
−120
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
Frequency (MHz)
Frequency (MHz)
G054
G055
Figure 37.
Figure 38.
TOTAL POWER
vs
POWER BREAK-UP
vs
SAMPLING SPEED
SAMPLING SPEED
0.54
0.48
0.42
0.36
0.3
0.28
0.24
0.2
Total Power
AVDD Power
AVDD_3V Power
DRVDD Power
IOVDD Power
0.16
0.12
0.08
0.04
0
0.24
0.18
5
20
35
50
65
80
5
20
35
50
65
80
Sampling Speed (MSPS)
Sampling Speed (MSPS)
G056
G057
Figure 39.
Figure 40.
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TYPICAL CHARACTERISTICS: COMMON (continued)
At +25°C, AVDD = 1.8V, AVDD_3V = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock,
1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, low-latency mode, DDR LVDS
output interface, and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode
IOVDD POWER
vs
SAMPLING SPEED
0.09
IOVDD Power
Double Lane
Single Lane
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
5
20
35
50
65
80
Sampling Speed (MSPS)
G058
Figure 41.
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TYPICAL CHARACTERISTICS: CONTOUR
At +25°C, AVDD = 1.8V, AVDD_3V = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock,
1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, low-latency mode, DDR LVDS
output interface, and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode
SFDR ACROSS INPUT AND SAMPLING FREQUENCIES
80
80
75
70
65
60
55
50
45
40
75
60
65
70
80
80
60
75
65
70
80
80
70
75
65
60
50
100
60
150
200 300
Input Frequency, MHz
250
350
400
450
500
85
55
65
70
75
80
Figure 42.
SFDR ACROSS INPUT AND SAMPLING FREQUENCIES with 6dB Gain
80
75
70
65
60
55
50
45
40
90
90
80
85
70
90
90
75
80
90
90
85
70
80
90
75
90
75
75
85
70
80
50
100
150
200
250
300
Input Frequency, MHz
350
400
85
450
500
65
70
75
80
90
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TYPICAL CHARACTERISTICS: CONTOUR (continued)
At +25°C, AVDD = 1.8V, AVDD_3V = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock,
1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, low-latency mode, DDR LVDS
output interface, and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode
SNR ACROSS INPUT AND SAMPLING FREQUENCIES
80
75
70
65
60
55
50
45
40
70
69
71
68
67
66
70
69
68
71
67
66
65
65
71
68
67
66
64
69
70
50
100
150
200 300
Input Frequency, MHz
250
350
400
450
500
72
63
64
65
66
67
68
69
70
71
Figure 43.
SNR ACROSS INPUT AND SAMPLING FREQUENCIES with 6dB Gain
80
75
70
65
60
55
50
45
40
68.5
67.5
66.5
68
67
66
65
68.5
67.5
66.5
68
67
66
65
64
66.5
68.5
67.5
67
66
65
68
64
63
50
100
150
200
250
300
Input Frequency, MHz
350
400
450
500
63
64
65
66
67
68
69
Figure 44.
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APPLICATION INFORMATION
THEORY OF OPERATION
The ADS61JB23 is a family of buffered analog input and ultralow power ADCs with maximum sampling rates up
to 80MSPS. The conversion process is initiated by a rising edge of the external input clock and the analog input
signal is sampled. The sampled signal is sequentially converted by a series of small resolution stages, with the
outputs combined in a digital correction logic block. At every clock edge the sample propagates through the
pipeline, resulting in a data latency of 21 clock cycles. The output is available as 12-bit data, coded in either
straight offset binary or binary twos complement format, with JESD207A interface in CML logic levels.
ANALOG INPUTS
The analog input pins have analog buffers (running off the AVDD3V supply) that internally drive the differential
sampling circuit. As a result of the analog buffer, the input pins present high input impedance to the external
driving source (10kΩ dc resistance and 2pF input capacitance). The buffer helps to isolate the external driving
source from the switching currents of the sampling circuit. This buffering makes it easy to drive the buffered
inputs compared to an ADC without the buffer.
The input common-mode is set internally using a 5kΩ resistor from each input pin to 1.95V, so the input signal
can be ac-coupled to the pins. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.5V) and
(VCM – 0.5V), resulting in a 2VPP differential input swing.
The input sampling circuit has a high 3dB bandwidth that extends up to 450 MHz (measured from the input pins
to the sampled voltage). Figure 45 shows an equivalent circuit for the analog input.
1 nH (+/- 0.2 nH)
(+/- 3 W)
15 W
INP_ADC
INP_PIN
LPIN1
ROUTE1
5 pF (+/- 0.5 pF)
CBUF1
0.5 pF
CESD1
5000 W (+/- 600 W)
RVCM1
5 W (+/- 2 W)
0.5 pF
RBUF1
CPBUF1
5000
RVCM2
600
1 nH (+/- 0.2 nH)
LPIN2
INM_ADC
(+/- 3 W)
INM_PIN
15 W
ROUTE2
5 pF (+/- 0.5 pF)
CBUF2
0.5 pF
CESD2
5 W (+/- 2 W)
RBUF2
0.5 pF
CPBUF2
Figure 45. Equivalent Circuit
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DRIVE CIRCUIT REQUIREMENTS
For optimum performance, the analog inputs must be driven differentially. This technique improves the common-
mode noise immunity and even-order harmonic rejection. A small resistor (5Ω) in series with each input pin is
recommended to damp out ringing caused by package parasitics.
and show the differential impedance (ZIN = RIN || CIN) seen by looking into the ADC input pins. The presence of
the analog input buffer results in an almost constant input capacitance up to 1GHz.
INP_PIN
RIN
CIN
INM_PIN
RIN and CIN change with frequency
At frequency F :
Real part of input impedance (input resistance) = RIN
= 1/(2. pF.CIN)
Imaginary part of input impedance
= CIN
Input capacitance
Frequency - MHz
Frequency - MHz
Frequency - MHz
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EXAMPLE DRIVING CIRCUITS
Two example driving circuit configurations are shown in Figure 46 and Figure 47—one optimized for low input
frequencies and the other optimized for high input frequencies.
The presence of internal analog buffers makes the ADS61JB23 simple to drive by absorbing kick-back noise of
ADC. The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-
order harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this
mismatch and good performance is obtained in input frequency range of interest.
The drive circuit for low input frequencies (<200MHz) in Figure 46 uses two back to back connected ADT1-1
transformers terminated by 50Ω near the ADC side.
An additional termination resistor pair may be required between the two transformers to improve even order
harmonic performance as shown in drive circuit for high input frequencies (>200MHz) in Figure 47. The center
point of this termination is connected to ground to improve the balance between the P (positive) and M (negative)
sides. The example circuit uses two back to back connected ADTL2-18 transformers with 200Ω termination
between them and 100Ω at secondary of second transformer to obtain an effective 50Ω (for a 50Ω source
impedance). The ac-coupling capacitors allow the analog inputs to self-bias around the required common-mode
voltage.
0.1mF
5 W
INP
25 W
25 W
0.1mF
INM
5 W
1:1
1:1
Figure 46. Drive Circuit with Low Bandwidth (for Low Input Frequencies)
0.1mF
5 W
INP
100 W
50 W
50 W
0.1mF
100 W
INM
5 W
1:2
2:1
Figure 47. Drive Circuit with High Bandwidth (for High Input Frequencies)
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CLOCK INPUT
The ADS61JB23 clock inputs can be driven differentially by sine, LVPECL, or LVDS source with little or no
difference in performance between them. The common-mode voltage of the clock inputs is set to 0.95V using
internal 5kΩ resistors as shown in Figure 48. This setting allows the use of transformer-coupled drive circuits for
sine-wave clock or ac-coupling for LVPECL and LVDS clock sources (see Figure 49, Figure 50, and Figure 51).
Clock Buffer
LPKG
~ 2 nH
20 Ω
CLKP
CBOND
~ 1 pF
CEQ
CEQ
5 kΩ
R
ESR
~ 100 Ω
0.95V
5 kΩ
L
PKG
~ 2 nH
20 Ω
CLKM
CBOND
~ 1 pF
R
ESR
~ 100 Ω
Note: CEQ is 1pF to 3pF and is the equivalent input capacitance of the clock buffer.
Figure 48. Internal Clock Buffer
For best performance, the clock inputs must be driven differentially, thereby reducing susceptibility to common-
mode noise. It is recommended to keep differential voltage between clock inputs less than 1.8VPP to get best
performance. For high input frequency sampling, it is recommended to use a clock source with very low jitter.
Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in performance
with a non-50% duty cycle clock input.
0.1 μF
CLKP
Differential
Sine-Wave
Clock Input
RT
0.1 μF
CLKM
Figure 49. Differential Sine-Wave Clock Driving Circuit
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Zo
0.1 μF
CLKP
Typical LVDS
Clock Input
100 Ω
Zo
0.1 μF
CLKM
Figure 50. LVDS Clock Driving Circuit
Zo
0.1 μF
CLKP
150 Ω
Typical LVPECL
Clock Input
100 Ω
Zo
0.1 μF
CLKM
150 Ω
Figure 51. LVPECL Clock Driving Circuit
FINE GAIN CONTROL
The ADS61JB23 includes gain settings that can be used to get improved SFDR performance (compared to no
gain). The gain is programmable from 0dB to 6dB (in 0.5dB steps). For each gain setting, the analog input full-
scale range scales proportionally, as shown in Table 9.
The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades about
0.5dB. The SNR degradation is less at high input frequencies. As a result, the fine gain is very useful at high
input frequencies as the SFDR improvement is significant with marginal degradation in SNR.
So, the fine gain can be used to trade-off between SFDR and SNR. Note that the default gain after reset is 0dB.
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Table 9. Full-scale Range Across Gains
FINE_GAIN<3:0>
GAIN, dB
TYPE
FULL-SCALE, Vpp
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
0.5
1
2.00
1.89
1.78
1.68
1.59
1.5
1.5
2
2.5
3
Fine gain, programmable
Default after reset
1.42
1.34
1.26
1.19
1.12
1.06
1.00
3.5
4
4.5
5
5.5
6
Do not use
SIGNAL POWER ESTIMATION
The ADS61JB23 includes a power estimation circuit that can be used to obtain a coarse power estimate
(accurate to within a dB) of the input signal averaged over a programmable number of samples. The power
estimate can be made available on pins DETECT<3:0> by enabling the bit EN_PWR_EST. The states of bits
DETECT<3:0> maps to the input signal power is shown in Table 10.
Table 10. State of DETECT<3:0> Versus Input Signal Power
INPUT SIGNAL POWER
RANGE IN dBFs
INPUT SIGNAL POWER RANGE
IN dBFs
DETECT<3:0>
DETECT<3:0>
–Inf to –12.5
–12.5 to –11.5
–11.5 to –10.5
–10.5 to –9.5
–9.5 to –8.5
–8.5 to –7.5
–7.5 to –6.5
0001
0010
0011
0100
0101
0110
0111
–6.5 to –5.5
–5.5 to –4.5
–4.5 to –3.5
–3.5 to –2.5
–2.5 to –1.5
–1.5 to 0
1000
1001
1010
1011
1100
1101
1110
0 to +1
The number of samples used for computing the average power is set by SAMPLES_PWR_EST<2:0> as shown
in Table 11.
Table 11. Number of Samples Used for Power
Estimation
SAMPLES_PWR_EST<2:0>
NUMBER OF SAMPLES
000
001
010
011
100
1K
2K
4K
8K
16K
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DEFINITION OF SPECIFICATIONS
Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with
respect to the low frequency value.
Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at
which the sampling occurs. This delay will be different across channels. The maximum variation is specified as
aperture delay variation (channel-channel).
Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle – The duty cycle of a clock signal is the ratio of the time the clock signal remains
at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a
percentage. A perfect differential sine-wave clock results in a 50% duty cycle.
Maximum Conversion Rate – The maximum sampling rate at which certified operation is given. All parametric
testing is performed at this sampling rate unless otherwise noted.
Minimum Conversion Rate – The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly
1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs.
Integral Nonlinearity (INL) – The INL is the deviation of the ADC's transfer function from a best fit line
determined by a least squares curve fit of that transfer function, measured in units of LSBs.
Gain Error – Gain error is the deviation of the ADC's actual input full-scale range from its ideal value. The gain
error is given as a percentage of the ideal input full-scale range. Gain error has two components: error due to
reference inaccuracy and error due to the channel. Both these errors are specified independently as EGREF and
EGCHAN
To a first order approximation, the total gain error will be ETOTAL ~ EGREF + EGCHAN
For example, if ETOTAL = ±0.5%, the full-scale input varies from (1-0.5/100) x FSideal to (1 + 0.5/100) x FSideal
.
.
.
Offset Error – The offset error is the difference, given in number of LSBs, between the ADC's actual average
idle channel output code and the ideal average idle channel output code. This quantity is often mapped into mV.
Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies the
change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation
of the parameter across the TMIN to TMAX range by the difference TMAX–TMIN
.
Signal-to-Noise Ratio – SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN),
excluding the power at DC and the first nine harmonics.
PS
SNR = 10Log10
PN
(1)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s full-
scale range.
Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (PS) to the power
of all the other spectral components including noise (PN) and distortion (PD), but excluding dc.
PS
SINAD = 10Log10
PN + PD
(2)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter's full-
scale range.
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ADS61JB23
SLOS755 –DECEMBER 2012
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Effective Number of Bits (ENOB) – The ENOB is a measure of the converter performance as compared to the
theoretical limit based on quantization noise.
SINAD - 1.76
ENOB =
6.02
(3)
Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (PS) to the power of the
first nine harmonics (PD).
PS
THD = 10Log10
PN
(4)
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other
spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f1
and f2) to the power of the worst spectral component at either frequency 2f1–f2 or 2f2–f1. IMD3 is either given in
units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to
full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range.
DC Power Supply Rejection Ratio (DC PSRR) – The DC PSSR is the ratio of the change in offset error to a
change in analog supply voltage. The DC PSRR is typically given in units of mV/V.
AC Power Supply Rejection Ratio (AC PSRR) – AC PSRR is the measure of rejection of variations in the
supply voltage by the ADC. If ΔVSUP is the change in supply voltage and ΔVout is the resultant change of the
ADC output code (referred to the input), then
DVOUT
PSRR = 20Log10
(Expressed in dBc)
DVSUP
(5)
Voltage Overload Recovery – The number of clock cycles taken to recover to less than 1% error after an
overload on the analog inputs. This is tested by separately applying a sine wave signal with 6dB positive and
negative overload. The deviation of the first few samples after the overload (from their expected values) is noted.
Common Mode Rejection Ratio (CMRR) – CMRR is the measure of rejection of variation in the analog input
common-mode by the ADC. If ΔVcm_in is the change in the common-mode voltage of the input pins and ΔVOUT
is the resultant change of the ADC output code (referred to the input), then
DVOUT
10
CMRR = 20Log
(Expressed in dBc)
DVCM
(6)
Cross-Talk (only for multi-channel ADC) – This is a measure of the internal coupling of a signal from adjacent
channel into the channel of interest. It is specified separately for coupling from the immediate neighboring
channel (near-channel) and for coupling from channel across the package (far-channel). It is usually measured
by applying a full-scale signal in the adjacent channel. Cross-talk is the ratio of the power of the coupling signal
(as measured at the output of the channel of interest) to the power of the signal applied at the adjacent channel
input. It is typically expressed in dBc.
38
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Dec-2012
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Samples
Drawing
(1)
(2)
(3)
(Requires Login)
ADS61JB23IRHAR
ACTIVE
VQFN
VQFN
RHA
40
40
2500
250
Green (RoHS
& no Sb/Br)
Call TI
Call TI
Level-3-260C-168 HR
ADS61JB23IRHAT
ACTIVE
RHA
Green (RoHS
& no Sb/Br)
Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Dec-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS61JB23IRHAR
ADS61JB23IRHAT
VQFN
VQFN
RHA
RHA
40
40
2500
250
330.0
330.0
16.4
16.4
6.3
6.3
6.3
6.3
1.5
1.5
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Dec-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS61JB23IRHAR
ADS61JB23IRHAT
VQFN
VQFN
RHA
RHA
40
40
2500
250
336.6
336.6
336.6
336.6
28.6
28.6
Pack Materials-Page 2
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