ADS62P43RGC [TI]
Dual Channel 14-Bit, 125/105/80/65 MSPS ADC with Parallel CMOS/DDR LVDS outputs; 双通道14位， 125/105/80/65 MSPS ADC，具有并行CMOS / DDR LVDS输出
| 型号： | ADS62P43RGC |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual Channel 14-Bit, 125/105/80/65 MSPS ADC with Parallel CMOS/DDR LVDS outputs |
| 文件： | 总67页 (文件大小：2886K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS62P45, ADS62P44
www.ti.com
ADS62P43, ADS62P42
REV1P0 SEP 2007
Dual Channel 14-Bit, 125/105/80/65 MSPS ADC with
Parallel CMOS/DDR LVDS outputs
FEATURES
§ Maximum Sample Rate: 125 MSPS
§ 14-bit Resolution with No Missing Codes
§ 92 dB Crosstalk at 50MHz
§ Clock duty cycle stabilizer
§ Internal reference, supports external
reference also
§ 64-QFN Package (9mm x 9mm)
§ Pin compatible 12-bit family (ADS62P2X)
§ Parallel CMOS and DDR LVDS Output Options
§ 3.5 dB Coarse Gain and Programmable Fine
Gain up to 6 dB for SNR/SFDR trade-off
§ Supports Sine, LVPECL, LVDS & CMOS clock
Table 1 ADS62PXX Dual Channel Family
inputs & amplitude down to 400 mV p-p
§
Digital Processing Block with
§ Offset correction
§ Fine gain correction, (0.05 dB step)
125 MSPS
105 MSPS
80 MSPS
65 MSPS
14 bit
12 bit
11 bit
ADS62P45 ADS62P44 ADS62P43 ADS62P42
ADS62P25 ADS62P24 ADS62P23 ADS62P22
§ Decimation by 2/4/8
ADS62P15
-
-
-
§ Built-in & Custom programmable 24-tap
Low / High / Band pass filters
Table 2 Performance Summary
ADS62P45
92
ADS62P44
92
ADS62P43
94
ADS62P42
Fin = 10 MHz
94
84
SFDR, dBc
Fin = 170 MHz, 3.5dB gain
Fin = 10 MHz
81
82
83
73.8
70.3
396
73.8
70.3
350
73.9
70.6
294
74
SINAD, dBFS
Fin = 170 MHz, 3.5dB gain
70.6
259
Power, mW per channel
DESCRIPTION
ADS62P4X is a family of dual channel 14-bit A/D converters with maximum sample rates up to 125 MSPS. It
combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample
and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has
coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.
PRODUCT PREVIEW information concerns products in
Copyright © 2007, Texas Instruments Incorporated
the formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
1
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ADS62P45, ADS62P44
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ADS62P43, ADS62P42
REV1P0 SEP 2007
ADS62P4X includes a digital processing block that consists of several useful & commonly used digital functions
such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 & in-built & custom
programmable filters. By default, the digital processing block is bypassed & its functions are disabled.
Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62P4X includes
internal references while traditional reference pins and associated decoupling capacitors have been eliminated.
The device also supports an external reference mode. The device is specified over the industrial temperature
range (-40°C to +85°C).
DIGITAL PROCESSING
BLOCK
DA0
DA1
DA2
DA3
DA4
Channel A
OUTPUT
BUFFERS
DA5
DA6
DA7
DA8
INA_P
INA_M
14 BIT ADC
DIGITAL
ENCODER
SHA
CHANNEL A
14bit
14bit
DA9
DA10
DA11
DA12
DA13
OUTPUT
CLOCK
BUFFER
CLKP
CLKM
CLOCKGEN
CLKOUT
DB0
DB1
DB2
DB3
DB4
OUTPUT
INB_P
INB_M
14bit
BUFFERS
DB5
DB6
14bit
14 BIT ADC
DIGITAL
ENCODER
SHA
CHANNEL B
DB7
DB8
DB9
DB10
DIGITAL PROCESSING
BLOCK
DB11
DB12
Channel B
DB13
CONTROL
INTERFACE
VCM
REFERENCE
CMOS INTERFACE
PRODUCT PREVIEW information concerns products in
the formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
2
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ADS62P45, ADS62P44
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ADS62P43, ADS62P42
REV1P0 SEP 2007
CLIPPER
From ADC
output
14 bits
14 bits
14 bits
14 bits
14 bits
To output buffers
LVDS or CMOS
24 TAP FILTER
- LOW PASS
- HIGH PASS
- BAND PASS
Fine Gain
(0 to 6 dB
0.5 dB steps)
Gain Correction
(0.05 dB steps)
DECIMATION
14 bits
BY 2/4/8
0
OFFSET
ESTIMATION
BLOCK
Filter Select
Disable offset
correction
Bypass filter
Bypass
decimation
Freeze offset
correction
DIGITAL
FILTER & DECIMATION
OFFSET
CORRECTION
GAIN
CORRECTION
FINE GAIN
DIGITAL PROCESSING BLOCK
Figure 1 Digital Processing Block Diagram
PACKAGE/ORDERING INFORMATION (1)
PRODUCT
PACKAGE-
PACKAGE
DESIGNATOR TEMPERATURE
RANGE
SPECIFIED
ECO
PLAN
(2)
LEAD/BALL PACKAGE
ORDERING
NUMBER
TRANSPORT
MEDIA,
LEAD
FINISH
MARKING
QUANTITY
TUBE
ADS62P45
ADS62P44
ADS62P43
ADS62P42
QFN-64
QFN-64
QFN-64
QFN-64
RGC
RGC
RGC
RGC
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
GREEN
(RoHS
& no
Cu NiPdAu
AZ62P45
AZ62P44
AZ62P43
AZ62P42
ADS62P45RGC
ADS62P44RGC
ADS62P43RGC
ADS62P42RGC
TUBE
TUBE
Sb/Br)
TUBE
(1) θ JA =TBD, θ JC =TBD.
(2) Eco Plan - The planned eco-friendly classification:
Green (RoHS & no Sb/Br) : TI defines "Green" to mean Pb-Free (RoHS compatible) and free of Bromine (Br) and Antimony (Sb)
based flame retardants.
PRODUCT PREVIEW information concerns products in
the formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
3
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ADS62P45, ADS62P44
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ADS62P43, ADS62P42
REV1P0 SEP 2007
(1)
ABSOLUTE MAXIMUM RATINGS
VALUE
UNIT
Supply voltage range, AVDD
- 0.3 V to 3.9
V
V
Supply voltage range, DRVDD
Voltage between AGND and DRGND
Voltage between AVDD to DRVDD
-0.3 V to 3.9
-0.3 to 0.3
V
-0.3 to 3.3
V
Voltage applied to external pin, CM (in external reference mode)
Voltage applied to analog input pins, INA_P, INA_M, INB_P, INB_M
Voltage applied to clock input pins, CLKP, CLKM
-0.3 to 2.0
V
-0.3V to minimum( 3.6, AVDD + 0.3V )
V
-0.3V to AVDD + 0.3V
V
Operating free-air temperature range, T
-40 to 85
125
°C
°C
°C
°C
A
Operating junction temperature range, T
J
Storage temperature range, T
-65 to 150
220
stg
Lead temperature 1.6 mm (1/16 “ ) from the case for 10 seconds
(1) Stresses beyond those listed under “ absolute maximum ratings” may cause permanent damage to thedevice. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolutemaximum rated conditions for extended periods may affect device reliability.
PRODUCT PREVIEW information concerns products in
the formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
4
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ADS62P45, ADS62P44
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ADS62P43, ADS62P42
REV1P0 SEP 2007
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
SUPPLIES
AVDD Analog supply voltage
3.0
1.65
3.0
3.3
1.8 to 3.3
3.3
3.6
3.6
3.6
V
V
V
CMOS interface
DRVDD Digital supply voltage
LVDS interface
ANALOG INPUTS
Differential input voltage range
Input common-mode voltage
2
V
PP
1.5 +/- 0.1
1.5 ± 0.05
V
V
Voltage applied on CM in external reference mode
CLOCK INPUT
ADS62P45
1
1
125
105
80
MSPS
MSPS
MSPS
MSPS
V pp
V pp
V pp
V
ADS62P44
Input clock sample rate, Fs
ADS62P43
1
ADS62P42
1
65
Sine wave, ac-coupled
0.3
3.0
1.6
0.7
LVPECL, ac-coupled
Input Clock amplitude
LVDS, ac-coupled
differential (V
-V
)
CLKP CLKM
LVCMOS, single-ended,
ac-coupled
3.3
Input clock duty cycle
35 %
50 %
65 %
DIGITAL OUTPUTS
Default strength
Maximum strength
Maximum strength
For CLOAD <= 5 pF and DRVDD >= 2.2V
Output buffer drive strength
For CLOAD > 5 pF and DRVDD > 2.2V
For DRVDD < 2.2V
CMOS interface
5
pF
pF
CLOAD
,
LVDS interface, without internal
termination
5
Maximum external load
capacitance from each output
pin to DRGND
LVDS interface, with 100 Ω internal
termination
10
pF
RLOAD,
100
Ω
Differential load resistance between the LVDS output pairs (LVDS mode)
Operating free-air temperature, TA
-40
85
°C
PRODUCT PREVIEW information concerns products in
the formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
5
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ADS62P45, ADS62P44
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ADS62P43, ADS62P42
REV1P0 SEP 2007
ELECTRICAL CHARACTERISTICS
Typical values at 25C, min & max values are across the full temperature range TMIN = -40C to TMAX = 85C, AVDD = 3.3V, DRVDD = 1.8V to
3.3V, 50% clock duty cycle, -1dBFS differential analog input, internal reference, applies to CMOS & LVDS interfaces unless otherwise noted.
ADS62P45
125 MSPS
TYP
ADS62P44
105 MSPS
TYP
ADS62P43
80 MSPS
TYP
ADS62P42
65 MSPS
PARAMETER
UNIT
MIN
MAX
MIN
MAX MIN
MAX MIN TYP
MAX
Resolution
14
14
14
14
bits
Analog Input
Differential input voltage range
V pp
2.0
1
2.0
1
2.0
1
2.0
1
Differential input resistance (at dc),
MΩ
see Figure 10
Differential input capacitance,
pF
MHz
µA
7
7
7
7
see Figure 11
Analog input bandwidth
450
165
450
140
450
110
450
91
Analog input common mode current
(per input pin of each channel)
VCM common mode voltage output
VCM output current capability
1.5
4
1.5
4
1.5
4
1.5
4
V
mA
Power Supply
IAVDD Analog supply current
232
15
205
13
172
152
9
mA
mA
IDRVDD Output buffer supply
current, CMOS interface
10.5
2.5MHz input signal,
(1)
no load capacitance
Total power – CMOS interface,
DRVDD = 1.8V
792
TBD
TBD
700
TBD
TBD
587
TBD
TBD
518
TBD
TBD
mW
Total power – LVDS interface,
DRVDD = 3.3V
TBD
50
TBD
50
TBD
50
TBD
50
mW
mW
Global power down
(1) In CMOS mode, the DRVDD current scales with the sampling frequency and the load capacitance on output pins.
PRODUCT PREVIEW information concerns products in
the formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
6
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ADS62P45, ADS62P44
www.ti.com
ADS62P43, ADS62P42
REV1P0 SEP 2007
ELECTRICAL CHARACTERISTICS
Typical values at 25C, min & max values are across the full temperature range TMIN = -40C to TMAX = 85C, AVDD = 3.3V, DRVDD = 3.3V, 50%
clock duty cycle, -1dBFS differential analog input, internal reference, applies to CMOS & LVDS interfaces, unless otherwise noted.
ADS62P45
125 MSPS
TYP
ADS62P44
105 MSPS
TYP
ADS62P43
80 MSPS
TYP
ADS62P42
65 MSPS
TYP
PARAMETERS
UNIT
MIN
MAX
MIN
MAX
MIN
MAX MIN
MAX
DC ACCURACY
No Missing Codes
Assured
+/- 0.8
+/- 3
Assured
+/- 0.7
+/- 2.5
TBD
Assured
+/- 0.5
+/-1.5
TBD
Assured
+/- 0.4
+/-1.5
TBD
DNL Differential Non-Linearity
INL Integral Non-Linearity
Offset Error
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD
TBD
TBD
LSB
LSB
mV
TBD
Offset error temperature
coefficient
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
μV/ °C
Offset error variation with
supply
mV/V
There are two sources of gain error – internal reference inaccuracy and channel gain error
Gain error due to internal
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD TBD
TBD
TBD
TBD
TBD TBD
TBD TBD
TBD
TBD
TBD
TBD
TBD
% FS
D%/ °C
% FS
reference inaccuracy alone
Reference gain error
temperature coefficient
Gain error of channel alone
(1)
TBD
TBD
TBD
TBD TBD
Channel gain error
D%/ °C
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
temperature coefficient
Gain matching
(1) This is specified by design and characterization; it is not tested in production.
PRODUCT PREVIEW information concerns products in
the formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
7
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ADS62P45, ADS62P44
www.ti.com
ADS62P43, ADS62P42
REV1P0 SEP 2007
ELECTRICAL CHARACTERISTICS
Typical values at 25C, min & max values are across the full temperature range TMIN = -40C to TMAX = 85C, AVDD = 3.3V, DRVDD = 3.3V, 50%
clock duty cycle, -1dBFS differential analog input, internal reference, applies to CMOS & LVDS interfaces, unless otherwise noted.
ADS62P45
125 MSPS
ADS62P44
105 MSPS
ADS62P43
80 MSPS
ADS62P42
65 MSPS
UNIT
PARAMETERS
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
Dynamic Characteristics
Fin= 10MHz
74.3
74.3
74.4
TBD 74.1
74
74.5
74.2
Fin = 50MHz
TBD 73.8
73.8
Fin = 70MHz
73.6
71.8
71
TBD 73.6
TBD 74.1
72.5
SNR
Signal to
dBFS
0 dB gain
71.8
72.5
Fin =
noise ratio,
170MHz
CMOS
3.5 dB gain
0 dB gain
71
71.4
71.4
71
71
72
72
Fin =
230MHz
3.5 dB gain
70
70
71
71
Fin= 10MHz
Fin = 50MHz
Fin = 70MHz
74.5
74.5
74.6
74.7
TBD
74
74
TBD 73.8
72.1
TBD 74.3
74.2
74.4
73.8
72.1
71
TBD 74.3
72.7
SNR
Signal to
dBFS
Fin =
0 dB gain
72.7
noise ratio,
170MHz
LVDS
3.5 dB gain
0 dB gain
71
71.8
71.8
Fin =
71.2
70.1
71
72.2
72.2
230MHz
3.5 dB gain
70.1
71.2
71.2
RMS output
noise
Inputs tied to common-
mode
0.96
0.96
0.96
0.96
LSB
PRODUCT PREVIEW information concerns products in
the formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
8
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ADS62P45, ADS62P44
www.ti.com
ADS62P43, ADS62P42
REV1P0 SEP 2007
ELECTRICAL CHARACTERISTICS
Typical values at 25C, min & max values are across the full temperature range TMIN = -40C to TMAX = 85C, AVDD = 3.3V, DRVDD = 3.3V, 50%
clock duty cycle, -1dBFS differential analog input, internal reference, applies to CMOS & LVDS interfaces, unless otherwise noted.
ADS62P45
125 MSPS
ADS62P44
105 MSPS
ADS62P43
80 MSPS
ADS62P42
65 MSPS
UNIT
PARAMETERS
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
Fin= 10MHz
Fin = 50MHz
Fin = 70MHz
73.8
TBD 73.2
73
73.8
73.2
73
73.9
TBD 73.6
73.4
74
73.7
SINAD
TBD
TBD 73.5
71.5
Signal to
noise &
distortion
ratio,
dBFS
Fin =
0 dB gain
70.6
70.7
70.2
68.7
68.5
74
71.5
170MHz
3.5 dB gain
0 dB gain
70.1
70.6
70.6
CMOS
Fin =
68.7
69.7
69.9
230MHz
3.5 dB gain
68.4
69.5
69.6
Fin= 10MHz
Fin = 50MHz
Fin = 70MHz
74
74.1
74.1
TBD 73.4
73.2
73.4
TBD 73.8
73.6
73.8
SINAD
TBD 73.4
70.8
TBD 73.6
71.6
Signal to
noise &
distortion
ratio,
dBFS
Fin =
0 dB gain
70.8
71.7
170MHz
3.5 dB gain
0 dB gain
70.5
70.5
70.8
70.7
LVDS
Fin =
68.9
68.9
68.1
68
230MHz
3.5 dB gain
68.6
68.7
69.7
69.7
ENOB,
Effective
number of
bits
Fin = 50 MHz
TBD 11.8
11.8
TBD 11.9
12
LSB
PRODUCT PREVIEW information concerns products in
the formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
9
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ADS62P45, ADS62P44
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ADS62P43, ADS62P42
REV1P0 SEP 2007
ELECTRICAL CHARACTERISTICS
Typical values at 25C, min & max values are across the full temperature range TMIN = -40C to TMAX = 85C, AVDD = 3.3V, DRVDD = 3.3V, 50%
clock duty cycle, -1dBFS differential analog input, internal reference, applies to CMOS & LVDS interfaces, unless otherwise noted.
ADS62P45
125 MSPS
ADS62P44
105 MSPS
ADS62P43
80 MSPS
ADS62P42
65 MSPS
UNIT
PARAMETERS
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
Fin= 10MHz
92
82
85
79
81
76
78
90
92
82
86
80
82
78
80
90
80.5
84
77
79
75
77
94
88
86
81
83
79
81
92
86
84
78
80
76
78
94
88
86
82
84
80
82
92
86
84
79
81
77
79
Fin = 50MHz
Fin = 70MHz
TBD
TBD
SFDR
TBD
TBD
Spurious
Free
dBc
Fin =
0 dB gain
Dynamic
Range
170MHz
3.5 dB gain
0 dB gain
Fin =
230MHz
3.5 dB gain
Fin= 10MHz
Fin = 50MHz
Fin = 70MHz
TBD 80.5
TBD
83.5
76
TBD
TBD
THD,
Total
dBc
Fin =
0 dB gain
Harmonic
Distortion
170MHz
3.5 dB gain
0 dB gain
78
Fin =
73
230MHz
3.5 dB gain
75
PRODUCT PREVIEW information concerns products in
the formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
10
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ADS62P45, ADS62P44
www.ti.com
ADS62P43, ADS62P42
REV1P0 SEP 2007
ELECTRICAL CHARACTERISTICS
Typical values at 25C, min & max values are across the full temperature range TMIN = -40C to TMAX = 85C, AVDD = 3.3V, DRVDD = 3.3V, 50%
clock duty cycle, -1dBFS differential analog input, internal reference, applies to CMOS & LVDS interfaces, unless otherwise noted.
ADS62P45
125 MSPS
ADS62P44
105 MSPS
ADS62P43
80 MSPS
ADS62P42
65 MSPS
UNIT
PARAMETERS
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
Fin= 10MHz
94
85
88
79
81
76
78
92
82
85
79
81
76
78
94
85
88
80
82
78
80
92
82
86
80
82
78
80
96
90
88
81
83
79
81
94
88
86
81
83
79
81
96
90
88
82
84
80
82
94
88
86
82
84
80
82
Fin = 50MHz
Fin = 70MHz
TBD
TBD
HD2
TBD
TBD
Second
dBc
Harmonic
Distortion
Fin =
0 dB gain
170MHz
3.5 dB gain
0 dB gain
Fin =
230MHz
3.5 dB gain
Fin= 10MHz
Fin = 50MHz
Fin = 70MHz
TBD
TBD
HD3
TBD
TBD
Third
dBc
Harmonic
Distortion
Fin =
0 dB gain
3.5 dB gain
0 dB gain
3.5 dB gain
170MHz
Fin =
230MHz
PRODUCT PREVIEW information concerns products in
the formative or design phase of development.
Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
11
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ADS62P45, ADS62P44
www.ti.com
ADS62P43, ADS62P42
REV1P0 SEP 2007
ELECTRICAL CHARACTERISTICS
Typical values at 25C, min & max values are across the full temperature range TMIN = -40C to TMAX = 85C, AVDD = 3.3V, DRVDD = 3.3V, 50%
clock duty cycle, -1dBFS differential analog input, internal reference, applies to CMOS & LVDS interfaces, unless otherwise noted.
ADS62P45
125 MSPS
ADS62P44
105 MSPS
ADS62P43
80 MSPS
ADS62P42
65 MSPS
UNIT
PARAMETERS
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
Fin= 10MHz
96
88
91
83
85
96
88
91
84
86
98
92
91
85
87
98
94
91
86
88
Fin = 50MHz
Worst Spur
Other than
second, third
harmonics
dBc
Fin = 70MHz
Fin = 170MHz
Fin = 230MHz
F1 = 46 MHz,
F2 = 50 MHZ,
each tone at -7 dBFS
IMD
2-Tone
95
95
98
98
dBFS
Intermodulation
Distortion
Recovery to within 1%
(of final value) for 6-dB
overload with sine
wave input
Input Overload
recovery
clock
1
1
1
1
cycles
Cross-talk signal
100
95
100
95
100
95
100
95
dB
dB
frequency = 10 MHZ
Cross-talk
Cross-talk signal
frequency = 50 MHZ
PSRR
AC Power
Supply
For 100 mV pp, 1MHz
signal on AVDD supply
TBD
TBD
TBD
TBD
dBc
Rejection Ratio
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DIGITAL CHARACTERISTICS
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1.
AVDD=3.3V, DRVDD=1.8V to 3.3V, unless otherwise specified.
ADS62P45 / ADS62P44 /
ADS62P43 / ADS62P42
TYP
PARAMETER
CONDITIONS
UNIT
MIN
MAX
DIGITAL INPUTS
High-level input voltage
2.4
V
V
Low-level input voltage
0.8
High-level input current
33
-33
4
μ A
μ A
pF
Low-level input current
Input capacitance
DIGITAL OUTPUTS – CMOS MODE
High-level output voltage
Low-level output voltage
Output capacitance (internal to device)
DRVDD
V
V
0
2
pF
(1) (2)
DIGITAL OUTPUTS – LVDS MODE
High-level output voltage
, DRVDD = 3.3V
1375
1025
350
1200
2
mV
mV
Low-level output voltage
Output Differential Voltage, |VOD|
VOS Output Offset Voltage
Output Capacitance
mV
Common-mode voltage of OUTP and
OUTM
Output capacitance inside the device,
from either output to ground
mV
pF
(1) LVDS buffer current setting, IO = 3.5 mA
(2) External differential load resistance between the LVDS output pairs, RLOAD = 50 Ω
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(1)
TIMING CHARACTERISTICS – LVDS AND CMOS MODES
Typical values at 25C, min and max values are across the full temperature range TMIN = -40C to TMAX = 85C, AVDD = 3.3V, DRVDD = 1.8V
(2)
(3)
to 3.3V, 3.0 Vpp sine wave input clock, C
= 5pF , I = 3.5mA, R
o
= 100Ω , no internal termination, unless otherwise noted.
LOAD
LOAD
ADS62P45
ADS62P44
ADS62P43
ADS62P42
PARAMETER
CONDITIONS
UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
TBD
TBD
TBD
TBD TBD
130
TBD TBD
130
TBD
130
TBD TBD
130
TBD
TBD
ns
t , Aperture delay
a
t , Aperture jitter
j
fs rms
from power down
global
15
15
15
15
μs
ns
ns
from channel
standby
100
100
100
100
Wake-up time
100
100
100
100
from output buffer
disable
Clock
cycles
14
10
14
10
Default
14
10
14
10
Latency
Clock
cycles
Low latency mode
DDR LVDS INTERFACE (4) DRVDD = 3.3V
(6)
Data valid
to
tsu
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
1.5
2.3
2.3
2.3
3.8
2.3
5.2
2.3
ns
ns
zero-crossing of
CLKOUTP
(5)
Data setup time
Zero-crossing of
CLKOUTP to data
th
(5)
Data hold time
(6)
becoming invalid
Input clock rising
edge cross-over to
output clock rising
edge cross-over
Duty cycle of
tPDI
TBD
TBD TBD
TBD TBD
TBD TBD
TBD
5.5
5.5
5.5
5.5
ns
Clock
propagation delay
LVDS bit clock
duty cycle
50%
110
50%
110
50%
110
50%
110
differential clock
tRISE, tFALL
Rise time measured
from -100mV to
+100mV,
ps
ps
Data rise time,
Data fall time
tCLKRISE, tCLKFALL
Fall time measured
from +100mV to -
100mV
Output clock rise
time,
Output clock fall
time
120
120
120
120
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ADS62P45
ADS62P44
ADS62P43
ADS62P42
PARAMETER
CONDITIONS
UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
PARALLEL CMOS INTERFACE, DRVDD = 2.5V TO 3.3V
(7)
tsu
Data valid
to zero-
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
3.5
3.2
4.3
4
5.8
5.5
7.2
7
ns
ns
crossing of CLKOUT
(5)
Data setup time
th
Zero-crossing of
CLKOUT to data
(7)
(5)
becoming invalid
Data hold time
tPDI
Input clock rising edge
cross-over to output
clock rising edge
cross-over
TBD
TBD TBD
TBD TBD
TBD TBD
TBD
7.3
53
7.3
53
7.3
53
7.3
53
ns
Clock propagation
delay
Output clock duty
cycle
Duty cycle of output
clock, CLKOUT
Rise time measured
from 20% to 80% of
DRVDD,
tRISE, tFALL
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
Data rise time,
Data fall time
Fall time measured
from 80% to 20% of
DRVDD
Rise time measured
from 20% to 80% of
DRVDD
tCLKRISE, tCLKFALL
Output clock rise
Fall time measured
from 80% to 20% of
DRVDD
time,
clock fall time
Output
Notes:
1. Timing parameters are ensured by design and characterization and not tested in production.
2. CLOAD is the effective external single-ended load capacitance between each output pin and ground
3. I refers to the LVDS buffer current setting; R
is the differential load resistance between the LVDS output pair.
LOAD
o
4. Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load.
5. Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume that
the data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as
reduced timing margin.
6. Data valid refers to LOGIC HIGH of +100.0mV and LOGIC LOW of -100.0mV.
7. Data valid refers to LOGIC HIGH of 2.0V and LOGIC LOW of 0.8V for DRVDD = 3.3V &
LOGIC HIGH of 1.7V and LOGIC LOW of 0.7V for DRVDD = 2.5V.
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the formative or design phase of development.
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N+16
N+3
N+4
N+15
N+2
N+1
N+14
Sample
N
INPUT
SIGNAL
t a
CLKM
INPUT
CLOCK
CLKP
CLKOUTM
CLKOUTP
t PDI
t SU
t h
DDR
LVDS
14 clock cycles *
OUTPUT DATA
DXP, DXM
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
E – Even bits D0, D2, D4, D6, D8, D10, D12
O – Odd bits D1, D3, D5, D7, D9, D11, D13
N+2
N+1
N-1
N
N-10
N-9
t PDI
CLKOUT
t SU
PARALLEL
CMOS
t h
14 clock cycles *
N-10
OUTPUT DATA
D0-D13
N-9
N-1
N
N+1
N+2
* Latency is 10 clock cycles in low latency mode
Figure 2 Latency diagram
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Figure 3 LVDS mode timing
Figure 4 CMOS mode timing
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DEVICE CONFIGURATION
ADS62P4X can be configured independently using either parallel interface control or serial interface programming.
USING PARALLEL INTERFACE CONTROL ONLY
To control the device using parallel interface, keep RESET tied to high (AVDD).
Pins SEN, SCLK, CTRL1, CTRL2 and CTRL3 can be used to directly control certain functions of the ADC. After power-up, the
device will automatically get configured as per the parallel pin voltage settings (Table 4 to Table 6).
In this mode, SEN and SCLK function as parallel analog control pins, which can be configured using a simple resistor divider as
shown in Figure 5. The table below has a description of the modes controlled by the parallel pins.
Table 3 PARALLEL PIN DEFINITION
Control Pin
Type of pin
Controls modes
SCLK
Coarse gain and Internal/external reference
Analog control pins (controlled by analog
voltage levels, see Figure 5).
SEN
LVDS/CMOS interface and Output Data Format
CTRL1
CTRL2
CTRL3
Digital control pins (controlled by digital logic
levels)
Together control various power down modes and
MUX mode.
USING SERIAL INTERFACE PROGRAMMING ONLY
To program the device using the serial interface, keep RESET low.
Pins SEN, SDATA, and SCLK function as serial interface digital pins and are used to access the internal registers of ADC. The
registers must first be reset to their default values either by applying a pulse on RESET pin or setting bit <RST> = 1. After
reset, the RESET pin must be kept low.
The serial interface section describes the register programming and register reset in more detail. Since the parallel pins
(CTRL1, CTRL2, CTRL3) are not used in this mode, they must be tied to ground.
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USING BOTH SERIAL INTERFACE AND PARALLEL CONTROLS
For increased flexibility, a combination of serial interface registers and parallel pin controls (CTRL1 to CTRL3) can also be used
to configure the device. To allow this, keep RESET low.
The parallel interface control pins CTRL1 to CTRL3 are available. After power-up, the device will automatically get configured
as per the voltage settings on these pins (Table 6).
SEN, SDATA, and SCLK function as serial interface digital pins and are used to access the internal registers of ADC. The
registers must first be reset to their default values either by applying a pulse on RESET pin or by setting bit <RST> = 1. After
reset, the RESET pin must be kept low. The serial interface section describes the register programming and register reset in
more detail.
Since the power down modes can be controlled using both the parallel pins and serial registers, the priority between the two is
determined by <OVRD> bit. When <OVRD> bit = 0, pins CTRL1 to CTRL3 control the power down modes. With <OVRD> = 1,
register bits <POWER DOWN> control these modes, over-riding the pin settings.
DETAILS OF PARALLEL CONFIGURATION ONLY
The functions controlled by each parallel pin are described below.
Table 4 SCLK (ANALOG CONTROL PIN)
SCLK
0
DESCRIPTION
0dB gain and Internal reference
(3/8)AVDD
(5/8)2AVDD
AVDD
0dB gain and External reference
3.5dB Coarse gain and External reference
3.5dB Coarse gain and Internal reference
Table 5 SEN (ANALOG CONTROL PIN)
DESCRIPTION
SEN
0
2’ s complement format and DDR LVDS output
(3/8)AVDD
(5/8)AVDD
AVDD
Straight binary and DDR LVDS output
Straight binary and parallel CMOS output
2’ s complement format and parallel CMOS output
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Table 6 CTRL1, CTRL2 and CTRL3 (DIGITAL CONTROL PINS)
CTRL1
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
CTRL2
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
CTRL3
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
DESCRIPTION
Normal operation
Channel A output buffer disabled
Channel B output buffer disabled
Channel A and B output buffer disabled
Power global down
Channel A standby
Channel B standby
MUX mode of operation, Channel A and B data is multiplexed and output on
HIGH
HIGH
HIGH
DB13 to DB0 pins. See Multiplexed output mode for detailed description.
Figure 5 Simple scheme to configure analog control pins (SCLK, SEN)
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SERIAL INTERFACE
The ADC has a set of internal registers, which can be accessed by the serial interface formed by pins SEN (Serial interface
Enable), SCLK (Serial Interface Clock) and SDATA (Serial Interface Data).
Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge of SCLK when
SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge when SEN is low. In case the
word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiple of 16-bit words within a
single active SEN pulse.
The first 8 bits form the register address & the remaining 8 bits the register data. The interface can work with SCLK frequency
from 20 MHz down to very low speeds (few Hertz) and also with non-50% SCLK duty cycle.
Register Initialization
After power-up, the internal registers must be initialized to their default values. This can be done in one of two ways –
1) Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10ns) as
shown in Figure 6
OR
2) By applying software reset. Using the serial interface, set bit <RST> = 1. This initializes internal registers to their
default values and then self-resets the <RST> bit to low. In this case, keep RESET pin low.
Figure 6 Serial Interface Timing
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SERIAL INTERFACE TIMING CHARACTERISTICS
Typical values at 25C, min and max values across the full temperature range TMIN = -40C to TMAX = 85C, AVDD = 3.3V, DRVDD = 1.8V to 3.3V,
unless otherwise noted.
PARAMETER
SCLK frequency
MIN
TYP
MAX
UNIT
> DC
20
MHz
f
t
t
t
t
SCLK
SLOADS
SLOADH
DS
SEN to SCLK setup time
SCLK to SEN hold time
SDATA setup time
25
25
25
25
ns
ns
ns
ns
SDATA hold time
DH
RESET TIMING
Typical values at 25C, min and max values across the full temperature range TMIN = -40C to TMAX = 85C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Delay from power-up of AVDD and DRVDD to
RESET pulse active
5
Power-on delay
ms
t1
10
25
Reset pulse width
Pulse width of active RESET signal
ns
ns
t2
t3
Register write delay
Delay from RESET disable to SEN active
Delay from power-up of AVDD and DRVDD to
output stable
Power-up time
7
ms
tPO
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Figure 7 Reset timing diagram
Note: A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset. For parallel
interface operation, RESET has to be tied permanently HIGH.
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SERIAL REGISTER MAP
Table 7 Summary of functions supported by serial interface (1) (2)
REGISTER
ADDRESS
A7 - A0 IN
HEX
REGISTER FUNCTIONS
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
D0
<RST>
00
10
0
0
Software Reset
<CLKOUT
0
0
0
0
0
STRENGTH>
<LVDS CURRENT>
LVDS buffer current
<CURRENT DOUBLE>
LVDS buffer current double
11
0
0
<DATAOUT STRENGTH>
programmability
<LVDS TERMINATION>
12
13
0
0
0
0
Internal termination programmability
<OFFSET
FREEZE>
0
0
0
0
0
<OUTPUT
INTERFACE>
LVDS or CMOS
interface
<REF>
Internal /
External
reference
<OVRD>
<COARSE GAIN>
14
0
<POWER DOWN MODES>
Over-ride bit
3.5 dB gain
<DATA FORMAT>
2s complement or
straight binary
Bit/Byte wise
(LVDS only)
16
17
0
0
0
0
0
0
0
<TEST PATTERNS>
<FINE GAIN>
0 to 6 dB gain in 0.5 dB steps
0
18
19
<CUSTOM LOW> Lower 8 bits
0
<CUSTOM HIGH> Upper 6 bits
<LOW
<OFFSET TC>
<GAIN CORRECTION>
1A
LATENCY>
<OFFSET EN>
Offset
Offset correction time constant
0 to 0.5 dB, steps of 0.05 dB
<FILTER COEFF
<DECIMATION
<ODD TAP
Enable>
<DECIMATION RATE>
SELECT>
In-built or custom
coefficients
1B
0
0
Enable>
correction
enable
Decimate by 2,4,8
Enable decimation
<DECIMATION FILTER FREQ
BANDS>
1D
0
0
0
0
0
<FILTER COEFFICIENTS>
1E to 2F
12 coefficients, each 12 bit signed
1) Multiple functions in a register can be programmed in a single write operation.
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DESCRIPTION OF SERIAL REGISTERS
A7 - A0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
D0
0
(hex)
<RST>
00
Software Reset
D1
<RST>
Software reset applied – resets all internal registers and self-clears to 0.
1
A7 - A0
(hex)
10
D7
D6
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
<CLKOUT STRENGTH>
D7-D6 <CLKOUT STRENGTH> Output clock buffer drive strength control
01
00
11
10
WEAKER than default drive
DEFAULT drive strength
STRONGER than default drive strength (recommended for load capacitances > 5 pF)
MAXIMUM drive strength (recommended for load capacitances > 5 pF)
A7 - A0
D7
0
D6
0
D5
D4
D3
D2
D1
D0
(hex)
<LVDS CURRENT>
LVDS buffer current
programmability
<CURRENT DOUBLE>
11
<DATAOUT STRENGTH>
LVDS buffer current double
D1-D0 <DATAOUT STRENGTH> Output data buffer drive strength control
01
00
11
10
WEAKER than default drive
DEFAULT drive strength
STRONGER than default drive strength (recommended for load capacitances > 5 pF)
MAXIMUM drive strength (recommended for load capacitances > 5 pF)
D3-D2 <LVDS CURRENT> LVDS Current programmability
00
01
10
11
3.5mA
2.5mA
4.5mA
1.75mA
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D5-D4 <CURRENT DOUBLE> LVDS Current double control
00
01
10
11
default current, set by <LVDS CURR>
LVDS clock buffer current is doubled, 2x <LVDS CURR>
LVDS data & clock buffers current are doubled, 2x <LVDS CURR>
unused
A7 - A0
D7
0
D6
0
D5
D4
D3
D2
D1
D0
(hex)
<LVDS TERMINATION>
12
Internal termination programmability
D5-D3 <LVDS DATA TERM> Internal termination control for data outputs
000
001
010
011
100
101
110
111
No internal termination
300 Ω
180 Ω
110 Ω
150 Ω
100 Ω
81 Ω
60 Ω
D2-D0 <LVDS CLK TERM> Internal termination control for clock output
000
001
010
011
100
101
110
111
No internal termination
300 Ω
180 Ω
110 Ω
150 Ω
100 Ω
81 Ω
60 Ω
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A7 - A0
D7
0
D6
0
D5
0
D4
D3
0
D2
0
D1
0
D0
0
(hex)
13
<OFFSET FREEZE>
D4
<OFFSET FREEZE> Offset correction becomes inactive and the last estimated offset value is used to cancel the
offset
0
1
Offset correction active
Offset correction inactive
A7 - A0
D7
D6
0
D5
D4
D3
D2
D1
D0
(hex)
<OUTPUT
INTERFACE>
LVDS or CMOS
interface
<OVRD>
Over-ride
bit
<COARSE
GAIN>
<REF>
Internal / External
reference
<POWER DOWN
MODES>
14
3.5 dB gain
D2-D0 <POWER DOWN MODES>
000
001
010
011
100
101
110
111
Normal operation
Channel A output buffer disabled
Channel B output buffer disabled
Channel A & B output buffers disabled
Power down global
Channel A standby
Channel B standby
Multiplexed mode, MUX- (only with CMOS interface)
Channel A and B data is multiplexed and output on DB13 to DB0 pins.
D3
0
<REF> Reference mode
Internal reference enabled
External reference enabled
1
D4
0
<COARSE GAIN> Coarse gain control
0 dB coarse gain
1
3.5 dB coarse gain
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D5
0
<OUTPUT INTERFACE> Output Interface selection
Parallel CMOS data outputs
1
DDR LVDS data outputs
D7
<OVRD> Over-ride bit - the power down modes can also be controlled using parallel pins. By setting <OVRD> = 1,
register bits <POWER DOWN MODES> will over-ride the settings of the parallel pins.
0
1
Disable over-ride – pins CTRL1 to CTRL3 control power down modes.
Enable over-ride - bits <POWER DOWN MODES> control power down modes.
A7 - A0
(hex)
D7
0
D6
0
D5
0
D4
D3
D2
D1
D0
<DATA FORMAT>
16
Bit / Byte wise (LVDS only)
<TEST PATTERNS>
2s complement or straight binary
D2-D0 <TEST PATTERNS> Test Patterns to verify capture
000
Normal ADC operation
001
010
011
100
101
110
111
Outputs all zeros
Outputs all ones
Outputs toggle pattern
Outputs digital ramp
Outputs custom pattern
Unused
Unused
D3
Bit-wise/Byte-wise selection (DDR LVDS mode ONLY)
0
Bit wise – Even bits (D0, D2, D4, D6, D8, D10, D12) on CLKOUT rising edge and Odd bits (D1, D3, D5, D7, D9, D11,
D13) on CLKOUT falling edge
1
Byte wise – Lower 7 bits (D0-D6) at CLKOUT rising edge and Upper 7 bits (D7-D13) at CLKOUT falling edge
D4
0
<DATA FORMAT> Data format selection
2s complement
1
Straight binary
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A7 - A0
(hex)
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
<FINE GAIN>
0 to 6 dB gain in 0.5 dB steps
17
D3-D0 <FINE GAIN> Gain programmability in 0.5 dB steps
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
0 dB gain, default after reset
0.5 dB gain
1.0 dB gain
1.5 dB gain
2.0 dB gain
2.5 dB gain
3.0 dB gain
3.5 dB gain
4.0 dB gain
4.5 dB gain
5.0 dB gain
5.5 dB gain
6.0 dB gain
Others Unused
A7 - A0
D7
0
D6
0
D5
D4
D3
D2
D1
D0
(hex)
18
<CUSTOM LOW> Lower 8 bits
<CUSTOM HIGH> Upper 6 bits
19
D7-D0
D5-D0
<CUSTOM LOW>
8 lower bits of custom pattern available at the output instead of ADC data.
<CUSTOM HIGH>
6 upper bits of custom pattern available at the output instead of ADC data
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A7 - A0
D7
D6
D5
D4
D3
D2
D1
D0
(hex)
<OFFSET TC>
<GAIN CORRECTION>
1A
<LOW LATENCY>
Offset correction time constant
0 to 0.5 dB, steps of 0.05 dB
D3-D0 <GAIN CORRECTION> Enables fine gain correction in steps of 0.05 dB (same correction applies to both channels)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
0 dB
+0.05 dB
+0.10 dB
+0.15 dB
+0.20 dB
+0.25 dB
+0.30 dB
+0.35 dB
+0.40 dB
+0.45 dB
+0.5 dB
D6-D4 <OFFSET TC>, Time constant of offset correction in number of clock cycles (seconds, for sampling frequency =
125MSPS)
000
001
010
011
100
101
110
111
227 (1.1 s)
226 (0.55 s)
225 (0.27 s)
224 (0.13 s)
228 (2.15 s)
229 (4.3 s)
227 (1.1 s)
227 (1.1 s)
D7
0
<LOW LATENCY>
Default latency, 14 clock cycles
Low latency enabled, 10 clock cycles
1
- Digital Processing Block is bypassed.
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A7 - A0
D7
D6
0
D5
D4
D3
D2
D1
D0
(hex)
<FILTER COEFF
SELECT>
<OFFSET Enable>
Offset correction
enable
<DECIMATION
Enable>
<DECIMATION
RATE>
1B
<ODD TAP Enable>
In-built or custom
coefficients
Enable decimation
Decimate by 2,4,8
D2-D0 <DECIMATION RATE>
000
001
011
100
Decimate by 2 (pre-defined or user coefficients can be used)
Decimate by 4 (pre-defined or user coefficients can be used)
No decimation (Pre-defined coefficients are disabled, only custom coefficients are available)
Decimate by 8 (Only custom coefficients are available)
D3
0
<ODD TAP ENABLE>
Even taps enabled (24 coefficients)
Odd taps enabled (23 coefficients)
1
D4
0
<DECIMATION ENABLE>
Decimation disabled
Decimation enabled
1
D5
0
<FILTER COEFF SELECT>
Pre-defined coefficients are loaded in the filter
1
User-defined coefficients are loaded in the filter (coefficients have to be loaded in registers – to - )
D7
0
<OFFSET Enable>
Offset correction disabled
Offset correction enabled
1
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A7 - A0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
D0
(hex)
1D
<DECIMATION FILTER FREQ BANDS>
D1-D0 <DECIMATION FILTER FREQ BAND>
With decimate by 2, <DECIMATION RATE> = 000:
Low pass filter (-6 dB frequency at Fs/4)
High pass filter (-6 dB frequency at Fs/4)
00
01
10,11 Unused
With decimate by 4, <DECIMATION RATE> = 001:
00
01
10
11
Low pass filter (-3 dB frequency at Fs/8)
Band pass filter (center frequency at 3Fs/16)
Band pass filter (center frequency at 5Fs/16)
High pass filter (-3 dB frequency at 3Fs/8)
A7 - A0
D7
D6
D5
D4
D3
D2
D1
D0
(hex)
Custom FIR coefficients
1E to 2F
See Table 14
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PIN DESCRIPTION (CMOS INTERFACE)
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PIN ASSIGNMENTS (CMOS INTERFACE)
Number
Pin
Pin Name
Description
of
Number
pins
AVDD
Analog power supply
AGND
Analog ground
CLKP, CLKM
INP_A, INM_A
INP_B, INM_B
VCM
Differential input clock
Differential input signal – channel A
Differential input signal – channel B
Internal reference mode – Common-mode voltage output.
External reference mode – Reference input. The voltage forced on
this pin sets the ADC internal references.
RESET
Serial interface RESET input.
In serial interface mode, the user MUST initialize internal registers through
hardware RESET by applying a high-going pulse on this pin or by using software
reset (refer to Serial Interface section).
In parallel interface mode, the user has to tie RESET pin permanently HIGH.
(SCLK, SDATA and SEN are used as parallel pin controls in this mode)
The pin has an internal 100KΩ pull-down resistor.
SCLK
This pin functions as serial interface clock input when RESET is low.
It functions as analog control pin when RESET is tied high & controls coarse gain
and internal/external reference selection. See Table 4 for details.
This pin has an internal pull-down resistor to ground.
SDATA
SEN
This pin functions as serial interface data input when RESET is low.
This pin has an internal pull-down resistor to ground.
This pin functions as serial interface enable input when RESET is low.
It functions as analog control pin when RESET is tied high & controls the output
interface (LVDS/CMOS) and data format selection. See Table 5 for details.
This pin has an internal pull-up resistor to AVDD.
CTRL1
These are digital logic input pins. They control various power down and multiplexed
mode. See Table 6 for details.
CTRL2
CTRL3
DA13 to DA0
Channel A 14-bit data outputs, CMOS
DB13 to DB0
CLKOUT
DRVDD
DRGND
PAD
Channel B 14-bit data outputs, CMOS
CMOS Output clock
Digital supply
Digital ground
Digital ground. Solder the pad to the digital ground on the board using multiple vias
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for good electrical & thermal performance.
Do not connect
NC
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PIN DESCRIPTION (LVDS INTERFACE)
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PIN ASSIGNMENTS (LVDS INTERFACE)
Pin
Pin Name
Description
Number of pins
Number
AVDD
AGND
Analog power supply
Analog ground
CLKP, CLKM
INP_A, INM_A
INP_B, INM_B
VCM
Differential input clock
Differential input signal – Channel A
Differential input signal – Channel B
Internal reference mode – Common-mode voltage output.
External reference mode – Reference input. The voltage forced on
this pin sets the ADC internal references.
RESET
Serial interface RESET input.
In serial interface mode, the user MUST initialize internal registers through
hardware RESET by applying a high-going pulse on this pin or by using
software reset (refer to Serial Interface section).
In parallel interface mode, the user has to tie RESET pin permanently HIGH.
(SCLK, SDATA and SEN are used as parallel pin controls in this mode)
The pin has an internal 100KΩ pull-down resistor.
SCLK
This pin functions as serial interface clock input when RESET is low.
It functions as analog control pin when RESET is tied high & controls coarse
gain and internal/external reference selection. See Table 4 for details.
This pin has an internal pull-down resistor to ground.
SDATA
SEN
This pin functions as serial interface data input when RESET is low.
This pin has an internal pull-down resistor to ground.
This pin functions as serial interface enable input when RESET is low.
It functions as analog control pin when RESET is tied high & controls the
output interface (LVDS/CMOS) and data format selection. See Table 5 for
details.
This pin has an internal pull-up resistor to AVDD.
CTRL1
These are digital logic input pins. Together they control various power
down and multiplexed mode. See Table 6 for details.
CTRL2
CTRL3
NC
Do not connect
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Number of
pins
Pin Name
Description
Pin Number
DA0P
Channel A Differential output data D0 & D1, true
Channel A Differential output data D0 & D1 , complement
Channel A Differential output data D2 & D3 , true
Channel A Differential output data D2 & D3 , complement
Channel A Differential output data D4 & D5 , true
Channel A Differential output data D4 & D5 , complement
Channel A Differential output data D6 & D7 , true
Channel A Differential output data D6 & D7 , complement
Channel A Differential output data D8 & D9 , true
Channel A Differential output data D8 & D9 , complement
Channel A Differential output data D10 & D11 , true
Channel A Differential output data D10 & D11 , complement
Channel A Differential output data D12 & D13 , true
Channel A Differential output data D12 & D13 , complement
Differential output clock, true
DA0M
DA2P
DA2M
DA4P
DA4M
DA6P
DA6M
DA8P
DA8M
DA10P
DA10M
DA12P
DA12M
CLKOUTP
CLKOUTM
DB0P
Differential output clock, complement
Channel B Differential output data D0 & D1 , true
Channel B Differential output data D0 & D1 , complement
Channel B Differential output data D2 & D3 , true
Channel B Differential output data D2 & D3 , complement
Channel B Differential output data D4 & D5 , true
Channel B Differential output data D4 & D5 , complement
Channel B Differential output data D6 & D7 , true
Channel B Differential output data D6 & D7 , complement
Channel B Differential output data D8 & D9 , true
Channel B Differential output data D8 & D9 , complement
Channel B Differential output data D10 & D11 , true
Channel B Differential output data D10 & D11 , complement
Channel B Differential output data D12 & D13 , true
Channel B Differential output data D12 & D13 , complement
Digital supply
DB0M
DB2P
DB2M
DB4P
DB4M
DB6P
DB6M
DB8P
DB8M
DB10P
DB10M
DB12P
DB12M
DRVDD
DRGND
PAD
Digital ground
Digital ground. Solder the pad to the digital ground on the board using
multiple vias for good electrical & thermal performance.
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APPLICATION INFORMATION
THEORY OF OPERATION
ADS62P4X is a low power 14 bit dual channel pipeline ADC family fabricated in a CMOS process using switched capacitor
techniques.
The conversion process is initiated by a rising edge of the external input clock. Once the signal is captured by the input sample
& hold, the input sample is sequentially converted by a series of small resolution stages, with the outputs combined in a digital
correction logic block. At every clock edge the sample propagates through the pipeline resulting in a data latency of 14 clock
cycles. The output is available as 14-bit data, in DDR LVDS or CMOS and coded in either straight offset binary or binary 2s
complement format.
ANALOG INPUT
The analog input consists of a switched-capacitor based differential sample and hold architecture. This differential topology
results in very good AC performance even for high input frequencies at high sampling rates. The INP and INM pins have to be
externally biased around a common-mode voltage of 1.5V, available on VCM pin 13. For a full-scale differential input, each
input pin INP, INM has to swing symmetrically between VCM + 0.5V and VCM - 0.5V, resulting in a 2Vpp differential input
swing. The maximum swing is determined by the internal reference voltages REFP (2.5V nominal) and REFM (0.5V, nominal).
Sampling
switch
Sampling
capacitor
Lpkg~ 2 nH
RCR Filter
INP
Ron
15 E
25 E
Cbond
~ 1 pF
Csamp
4.0 pF
Cpar2
1 pF
50 E
Resr
100 E
Ron
10 E
3.2 pF
Cpar1
0.8 pF
Csamp
4.0 pF
50 E
Ron
15 E
Lpkg~ 2 nH
25 E
INM
Cbond
~ 1 pF
Sampling
capacitor
Cpar2
1 pF
Resr
100 E
Sampling
switch
Figure 8 Analog Input Equivalent Circuit
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The input sampling circuit has a high 3-dB bandwidth that extends up to 450 MHz (measured from the input pins to the
sampled voltage).
TBD
Figure 9 ADC Analog Bandwidth
Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This improves the common-mode noise immunity
and even order harmonic rejection. A 5 Ω resistor in series with each input pin is recommended to damp out ringing caused by
the package parasitics.
It is also necessary to present low impedance (< 50 Ω) for the common mode switching currents. This can be achieved by
using two resistors from each input terminated to the common mode voltage (VCM).
In addition to the above, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency
range and matched impedance to the source. While doing this, the ADC input impedance must be considered. Figure 10 &
Figure 11 show the impedance (Zin = Rin || Cin) looking into the ADC input pins.
100.0
10.0
1.0
0.1
0.0
0
100
200
300
400
500
600
Frequency,MHz
Figure 10 ADC Analog Input Resistance (Rin) across frequency
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9
8
7
6
5
4
3
2
1
0
0
100
200
300
400
500
600
Frequency, MHz
Figure 11 ADC Analog Input Capacitance (Cin) across frequency
Using RF-Transformer based drive circuits
Figure 12 shows a configuration using a single 1:1 turns ratio transformer (for example, Coilcraft WBC1-1) that can be used for
low input frequencies (about 100 MHz). The single-ended signal is fed to the primary winding of the RF transformer. The
transformer is terminated on the secondary side. Putting the termination on the secondary side helps to shield the kickbacks
caused by the sampling circuit from the RF transformer’ s leakage inductances. The termination is accomplished by two
resistors connected in series, with the center point connected to the 1.5 V common mode (VCM pin). The value of the
termination resistors (connected to common mode) has to be low (< 100 Ω) to provide a low-impedance path for the ADC
common-mode switching currents.
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Figure 12 Drive circuit at low input frequencies
At high input frequencies, the mismatch in the transformer parasitic capacitance (between the windings) results in degraded
even-order harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch, and
good performance is obtained for high frequency input signals. Figure 13 shows an example using two transformers (Coilcraft
WBC1-1). An additional termination resistor pair (enclosed within the shaded box) may be required between the two
transformers to improve the balance between the P and M sides. The center point of this termination must be connected to
ground.
Figure 13 Drive circuit at high input frequencies
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Using Differential Amplifier drive circuits
Figure 14 shows a drive circuit using a differential amplifier (TI's THS4509) to convert a single-ended input to differential output
that can be interface to the ADC analog input pins. In addition to the single-ended to differential conversion, the amplifier also
provides gain (10 dB). RFIL helps to isolate the amplifier outputs from the switching input of the ADC. Together with CFIL it also
forms a low-pass filter that band-limits the noise (and signal) at the ADC input. As the amplifier output is ac-coupled, the
common-mode voltage of the ADC input pins is set using two 200 W resistors connected to VCM.
The amplifier output can also be dc-coupled. Using the output common-mode control of the THS4509, the ADC input pins can
be biased to 1.5 V. In this case, use +4 V and -1 V supplies for the THS4509 so that its output common-mode voltage (1.5 V) is
at mid-supply.
RF
+VS
500 E
5 E
RFIL
0.1 uF
0.1 uF 10 uF
0.1 uF
INP
RG
200 E
200 E
CFIL
RS
0.1 uF
RT
CM
THS4509
CFIL
INM
RG
VCM
0.1 uF
RFIL
5 E
500 E
RS || RT
0.1 uF
0.1 uF
- VS
10 uF
0.1 uF
RF
Figure 14 Drive Circuit using the THS4509
Input common-mode
To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1uF low-inductance capacitor connected to
ground. The VCM pin is designed to directly drive the ADC inputs. Each input pin of the ADC sinks a common-mode current,
about 165 uA (at 125MSPS). Equation 1 describes the dependency of the common-mode current and the sampling frequency.
165mAxFs
125MSPS
Equation 1
This equation helps to design the output capability and impedance of the CM driving circuit accordingly.
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REFERENCE
ADS62P4X has built-in internal references REFP and REFM, requiring no external components. Design schemes are used to
linearize the converter load seen by the references; this and the on-chip integration of the requisite reference capacitors
eliminates the need for external decoupling. The full-scale input range of the converter can be controlled in the external
reference mode as explained below. The internal or external reference modes can be selected by programming the serial
interface register bit <REF>.
Figure 15 Reference section
Internal reference
When the device is in internal reference mode, the REFP and REFM voltages are generated internally. Common-mode voltage
(1.5V nominal) is output on VCM pin, which can be used to externally bias the analog input pins.
External reference
When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on the VCM pin is
buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The differential input voltage corresponding
to full-scale is given by
Equation 2.
Full-scale differential input pp = (Voltage forced on VCM) x 1.33
Equation 2
In this mode, the 1.5V common-mode voltage to bias the input pins has to be generated externally.
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COARSE GAIN AND PROGRAMMABLE FINE GAIN
ADS62P4X includes gain settings that can be used to get improved SFDR performance (over 0dB gain mode). For each gain
setting, the analog input full-scale range scales proportionally, as shown in Table 8 .
The coarse gain is a fixed setting of 3.5 dB and is designed to improve SFDR with little degradation in SNR. The fine gain is
programmable in 0.5 dB steps from 0 to 6 dB; however the SFDR improvement is achieved at the expense of SNR. So, the
programmable fine gain makes it possible to trade-off between SFDR and SNR. The coarse gain makes it possible to get best
SFDR but without losing SNR significantly.
The gains can be programmed using the serial interface (bits <COARSE GAIN> and <FINE GAIN>). Note that the default gain
after reset is 0dB.
Table 8 Full-scale range across gains
Gain, dB
0
Type
Full-Scale, Vpp
2V
Default after reset
Coarse (fixed)
3.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
1.34
1.89
1.78
1.68
1.59
1.50
1.42
Fine (programmable)
1.34
1.26
1.19
1.12
1.06
1.00
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CLOCK INPUT
The clock inputs can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS), with little or no difference in
performance between them. The common-mode voltage of the clock inputs is set to VCM using internal 5 kΩ resistors as
shown in Figure 16. This allows using transformer-coupled drive circuits for sine wave clock or ac-coupling for LVPECL, LVDS
clock sources (Figure 18 and Figure 19).
Clock buffer
Lpkg
~ 2 nH
10 E
CLKP
Cbond
~ 1 pF
Ceq
Ceq
5 kE
Resr
~ 100 E
VCM
6 pF
5 kE
Lpkg
~ 2 nH
10 E
CLKM
Cbond
~ 1 pF
Resr
~ 100 E
Ceq ~ 1 to 3 pF, equivalent input capacitance of clock buffer
Figure 16 Internal Clock buffer
TBD
Figure 17 Clock Input Impedance
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Figure 18 Differential clock driving circuit
Single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM (pin 11) connected to ground with a 0.1-μ F
capacitor, as shown in Figure 19.
Figure 19 Single-ended clock driving circuit
For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode noise.
For high input frequency sampling, it is recommended to use a clock source with very low jitter. Bandpass filtering of the clock
source can help reduce the effect of jitter. There is no change in performance with a non-50% duty cycle clock input.
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POWER DOWN
ADS62P4X has three power down modes – power down global, channel standby and individual channel output buffer disable.
These can be set using either the serial register bits or using the control pins CTRL1 to CTRL3.
CONFIGURE USING
TOTAL
SERIAL INTERFACE
PARALLEL CONTROL PINS
POWER DOWN MODES
POWER,
WAKE-UP TIME
<POWER DOWN
(1)
mW
CTRL1
CTRL2
CTRL3
MODES>
000
Normal operation
low
low
low
low
low
high
low
792
782
782
772
50
-
Channel A output buffer disabled
Channel B output buffer disabled
Channel A & B output buffer disabled
Power down global
001
Fast (100 ns)
Fast (100 ns)
Fast (100 ns)
Slow (15 μ s)
Fast (100 ns)
Fast (100 ns)
010
low
high
high
low
011
low
high
low
100
high
high
high
high
Channel A standby
101
low
high
low
482
482
Channel B standby
110
high
high
Multiplexed (MUX) mode – Output data of
channel A & B is multiplexed & available on
DB13 to DB0 pins.
111
high
-
-
1. Sampling frequency = 125 MSPS, DRVDD = 1.8V
Power down global
In this mode, the entire chip including both the A/D converters, internal reference and the output buffers are powered down
resulting in reduced total power dissipation of about 50 mW. The output buffers are in high impedance state. The wake-up time
from the global power down to data becoming valid in normal mode is typically 15 μ s.
Channel standby (individual or both channels)
This mode allows the individual ADCs to be powered down. The internal references are active & this results in fast wake-up
time, about 100 ns. The total power dissipation in standby is about 482 mW.
Output buffer disable (individual or both channels)
Each channel’ s output buffer can be disabled & put in high impedance stat.eWakeup time is fast, about 100 ns.
Input clock stop
In addition to the above, the converter enters a low-power mode when the input clock frequency falls below 1 MSPS. The
power dissipation is about 140 mW.
POWER SUPPLY SEQUENCE
During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are separated in the
device. Externally, they can be driven from separate supplies or from a single supply.
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DIGITAL OUTPUT INFORMATION
ADS62P4X provides 14 bit data per channel and a common output clock synchronized with the data. The output interface can
be either parallel CMOS or DDR LVDS voltage levels and can be selected using serial register bit <OUTPUT INTERFACE> or
parallel pin SEN.
Parallel CMOS interface
In the CMOS mode, the output buffer supply (DRVDD) can be operated over a wide range from 1.8 V to 3.3 V (typical). Each
data bit is output on separate pin as CMOS voltage level, every clock cycle (Figure 20).
For DRVDD > 2.2 V, it is recommended to use the CMOS output clock (CLKOUT) to latch data in the receiving chip. The rising
edge of CLKOUT can be used to latch data in the receiver, even at the highest sampling speed. It is recommended to minimize
the load capacitance seen by data and clock output pins by using short traces to the receiver. Also, match the output data and
clock traces to minimize the skew between them.
For DRVDD < 2.2 V, it is recommended to use external clock (for example, input clock delayed to get desired setup / hold
times).
CMOS
Output Buffers
DA0
DA1
DA2
DA3
14 bit Channel A
data
DA12
DA13
CLKOUT
DB0
DB1
DB2
DB3
14 bit Channel B
Data
DB12
DB13
Figure 20 CMOS Output Interface
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Output Buffer Strength Programmability
Switching noise (caused by CMOS output data transitions) can couple into the analog inputs during the instant of sampling and
degrade the SNR. The coupling and SNR degradation increases as the output buffer drive is made stronger. To minimize this,
ADS62P4X CMOS output buffers are designed with controlled drive strength to get best SNR. The default drive strength also
ensures wide data stable window for load capacitances up to 5 pF and DRVDD supply voltage > 2.2 V.
To ensure wide data stable window for load capacitance > 5 pF, there exists option to increase the output data & clock drive
strengths using the serial interface (<DATAOUT STRENGTH> & <CLKOUT STRENGTH>). Note that for DRVDD supply
voltage < 2.2 V, it is recommended to use maximum drive strength (for any value of load capacitance).
CMOS Interface Power Dissipation
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every output pin. The
maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock cycle. In actual applications, this
condition is unlikely to occur. The actual DRVDD current would be determined by the average number of output bits switching,
which is a function of the sampling frequency and the nature of the analog input signal.
Digital current due to CMOS output switching = CL x DRVDD x (N x FAVG),
where CL = load capacitance, N x FAVG = average number of output bits switching.
Figure TBD shows the current with various load capacitances across sampling frequencies at 2 MHz analog input frequency.
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DDR LVDS Interface
The LVDS interface works only with 3.3V DRVDD supply. In this mode, the 14 data bits of each channel and a common output
clock are available as LVDS (Low Voltage Differential Signal) levels. Two successive data bits are multiplexed and output on
each LVDS differential pair every clock cycle (DDR - Double Data Rate,
Figure 22).
Pins
LVDS Buffers
DA0P
Data bits D0, D1
DA0M
DA2P
Data bits D2, D3
14 bit Channel A
data
DA2M
DA12P
DA12M
Data bits D12, D13
Output Clock
CLKOUTP
CLKOUTM
DB0P
DB0M
Data bits D0, D1
Data bits D2, D3
DB2P
DB2M
14 bit Channel B
data
DB12P
DB12M
Data bits D12, D13
Figure 21 DDR LVDS outputs
Even data bits D0, D2, D4, D6, D8, D10 and D12 are output at the rising edge of CLKOUTP and the odd data bits D1, D3, D5,
D7, D9, D11 and D13 are output at the falling edge of CLKOUTP. Both the rising and falling edges of CLKOUTP have to be
used to capture all the data bits.
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Figure 22 DDR LVDS interface
LVDS Buffer Current Programmability
The default LVDS buffer output current is 3.5 mA. When terminated by 100 Ω, this results in a 350-mV single-ended voltage
swing (700-mVPP differential swing). The LVDS buffer currents can also be programmed to 2.5 mA, 4.5 mA, and 1.75 mA
(<LVDS CURRENT>). In addition, there exists a current double mode, where this current is doubled for the data and output
clock buffers (register bits <CURRENT DOUBLE>).
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LVDS Buffer Internal Termination
An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially terminated
inside the device. The termination resistances available are – 300 Ω, 185 Ω, and 150 Ω (nominal with ±20% variation). Any
combination of these three terminations can be programmed; the effective termination is the parallel combination of the
selected resistances. This results in eight effective terminations from open (no termination) to 60 Ω.
The internal termination helps to absorb any reflections coming from the receiver end, improving the signal integrity. With 100 Ω
internal and 100 Ω external termination, the voltage swing at the receiver end is halved (compared to no internal termination).
The voltage swing can be restored by using the LVDS current double mode. Figure 23 &
TBD
Figure 24 compare the LVDS eye diagrams without and with 100 Ω internal termination. With internal termination, the eye looks
clean even with 10 pF load capacitance (from each output pin to ground). The terminations can be programmed using register
bits <LVDS TERMINATION>.
TBD
Figure 23 LVDS Eye Diagram – No Internal Termination
TBD
Figure 24 LVDS Eye Diagram – With 100Ω Internal Termination
Output Data Format
Two output data formats are supported – 2s complement and straight binary. They can be selected using the serial interface
register bit <DATA FORMAT> or controlling the SEN pin in parallel configuration mode.
In the event of an input voltage overdrive, the digital outputs go to the appropriate full scale level. For a positive overdrive, the
output code is 0x3FFF in offset binary output format, and 0x1FFF in 2s complement output format. For a negative input
overdrive, the output code is 0x0000 in offset binary output format and 0x2000 in 2s complement output format.
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Multiplexed Output mode
This mode is available only with CMOS interface. In this mode, the digital outputs of both the channels are multiplexed and
output on a single bus (DA0-DA13 pins), as per the timing diagram shown in Figure 25. The channel B output pins (DB0-DB13)
are tri-stated. Since the output data rate on the DB bus is effectively doubled, this mode is recommended only for low sampling
frequencies (< 65 MSPS).
This mode can be enabled using register bits <POWER DOWN MODES> or using the parallel pins CTRL1 -3 ().
CLKOUT
DA0
DA1
DB0
DB1
DA0
DA1
DB0
DB1
DB0
DB1
DA2
DB2
DA2
DB2
DB2
DA13
DB13
DA13
DB13
DB13
SAMPLE N
SAMPLE N+1
Figure 25 Multiplexed mode - Output Timing
Low Latency mode
The default latency of ADS62P4X is 14 clock cycles. For applications, which cannot tolerate large latency, ADS62P4X includes
a special mode with 10 clock cycles latency. In the low latency condition, the Digital Processing block is bypassed and its
features (offset correction, fine gain, decimation filters) are not available.
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DETAILS OF THE DIGITAL PROCESSING BLOCK
CLIPPER
From ADC
output
14 bits
14 bits
14 bits
14 bits
14 bits
To output buffers
LVDS or CMOS
24 TAP FILTER
- LOW PASS
- HIGH PASS
- BAND PASS
Fine Gain
(0 to 6 dB
0.5 dB steps)
Gain Correction
(0.05 dB steps)
DECIMATION
14 bits
BY 2/4/8
0
OFFSET
ESTIMATION
BLOCK
Filter Select
Disable offset
correction
Bypass filter
Bypass
decimation
Freeze offset
correction
DIGITAL
FILTER & DECIMATION
OFFSET
CORRECTION
GAIN
CORRECTION
FINE GAIN
DIGITAL PROCESSING BLOCK
Figure 26 Digital Processing Block Diagram
Several common digital processing functions have been integrated in the device – offset correction, fine gain, gain correction
decimation & digital filters. By default after reset, the digital processing block is bypassed & all its functions are disabled.
OFFSET CORRECTION
ADS62P4X has an internal offset correction algorithm that estimates and corrects dc offset up to +/-10mV. The correction can
be enabled using the serial register bit <OFFSET LOOP EN>. Once enabled, the algorithm estimates the channel offset and
applies the correction every clock cycle. The time constant of the correction loop is a function of the sampling clock frequency.
The time constant can be controlled using register bits <OFFSET LOOP TC> as described in Table 9.
It is also possible to freeze the offset correction using the serial interface (<OFFSET LOOP FREEZE>). Once frozen, the offset
estimation becomes inactive and the last estimated value is used for correction every clock cycle. Note that the offset
correction is disabled by default after reset.
Figure 27 shows the time response of the offset correction algorithm, after it is enabled.
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Table 9 Time Constant of Offset Correction Algorithm
<OFFSET LOOP TC>
Time constant (TCCLK),
Time constant, sec
D6-D5-D4
000
number of clock cycles
(=TCCLK x 1/Fs) (1)
227
226
225
224
228
229
227
227
1.1
0.55
0.27
0.13
2.15
4.3
001
010
011
100
101
110
1.1
111
1.1
(1) Sampling frequency, Fs = 125 MSPS
TBD
Figure 27 Time Response of Offset Correction
GAIN CORRECTION
ADS62P4X includes option to make fine corrections to the ADC channel gain. The corrections can be done in steps of 0.05 dB,
up to a maximum of 0.5 dB, using the register bits <GAIN CORRECTION>. Only positive corrections are supported and the
same correction applies to both the channels.
Table 10 Gain Correction Values
<GAIN CORRECTION>
Amount of correction, dB
D3-D2-D1-D0
0000
0001
0
+0.05
+0.1
0010
0011
+0.15
+0.20
+0.25
+0.30
+0.35
+0.40
+0.45
+0.5
0100
0101
0110
0111
1000
1001
1010
Other combinations
Unused
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DECIMATION FILTER
ADS62P4X includes option to decimate the ADC output data with in-built low pass, high pass or band pass filters.
The decimation rates & the type of filter can be selected using register bits <DECIMATION RATE> & <DECIMATION FILTER
TYPE>. Decimation rates of 2, 4 or 8 are available and either low pass, high pass or band pass filters can be selected (Table
11). By default, the decimation filter is disabled - use register bit <DECIMATION ENABLE> to enable it.
(1)
Table 11 Decimation Filter Modes
Combination of decimation rates & filter types
Decimation Type of filter
Serial interface settings
<DECIMATION
FILTER FREQ
BAND>
<FILTER
COEFF
SELECT>
<DECIMATION
RATE>
<DECIMATION
ENABLE>
In-built low pass filter
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
1
0
1
0
1
0
0
0
0
0
0
1
1
1
1
1
1
(pass band = 0 to Fs/4)
Decimate by 2
In-built high pass filter
(pass band = Fs/4 to Fs/2)
In-built low pass filter
(pass band = 0 to Fs/8)
nd
In-built 2 band pass filter
Decimate by 4
Decimate by 4
(pass band = Fs/8 to Fs/4)
In-built 3rd band pass filter
(pass band = Fs/4 to 3Fs/8)
In-built last band pass filter
(pass band = 3Fs/8 to Fs/2)
Decimate by 2
Decimate by 4
Decimate by 8
No decimation
Custom filter (user programmable coefficients)
Custom filter (user programmable coefficients)
Custom filter (user programmable coefficients)
Custom filter (user programmable coefficients)
0
0
1
0
0
0
0
1
0
1
0
1
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
0
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Decimation filter equation
The decimation filter is implemented as 24-tap FIR with symmetrical coefficients (each coefficient is 12-bit signed).
The filter equation is:
æ
ö
1
11
ç
ç
÷
÷
y(n) =
· (h0 · x(n) + h1· x(n -1) + h2 · x(n - 2) + ¼ + h11· x(n -11) + h11· x(n -12) + ¼ + h1· x(n - 22) + h0 · x(n - 23))
2
è
ø
By setting the register bit <ODD TAP ENABLE> = 1, a 23-tap FIR is implemented:
æ
ö
1
11
ç
ç
÷
÷
y(n) =
· (h0· x(n) + h1· x(n -1) + h2· x(n - 2) +¼ + h10· x(n -10) + h11· x(n -11) + h10· x(n -12) + ¼ + h1· x(n - 21) + h0· x(n - 22)
2
è
ø
In the above equations,
h0, h1 …h11 are 12 bit signed representation of the coefficients,
x(n) is the input data sequence to the filter &
y(n) is the filter output sequence.
Pre-defined coefficients
The in-built filter types (low pass, high pass & band pass) use pre-defined coefficients. The frequency response of the in-built
filters is shown in Figure 28 & Figure 29.
TBD
Figure 28 Decimate by 2 filter response
TBD
Figure 29 Decimate by 4 filter response
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Table 12 Pre-defined coefficients for Decimate by 2 filters
Decimate by 2
Coefficients
Low pass filter High pass filter
h0
h1
23
-37
-6
-22
-65
-52
30
h2
h3
68
h4
-36
-61
35
66
h5
-35
-107
38
h6
h7
118
-100
-197
273
943
h8
202
-41
-644
1061
h9
h10
h11
Table 13 Pre-defined coefficients for Decimate by 4 filters
Decimate by 4
1st Band-pass 2nd Band-pass
High pass
filter
32
Coefficients
Low pass filter
filter
-7
filter
-34
-34
-101
43
h0
h1
-17
-50
71
19
-15
h2
-47
127
73
-95
h3
46
22
h4
24
58
-8
h5
-42
-100
-97
8
0
-28
-5
-81
h6
86
106
-62
h7
117
-190
-464
-113
526
-179
294
86
h8
-97
h9
202
414
554
310
-501
575
h10
h11
-563
352
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Custom filter coefficients with decimation
The filter coefficients can also be programmed by the user (custom). For custom coefficients, set the register bit
<FILTER COEFF SELECT> & load the coefficients (h0 to h11) in registers 1E to 2F using the serial interface (Table 14) as:
Register content = 12 bit signed representation of [real coefficient value x 211]
Custom filter coefficients without decimation
The filter with custom coefficients can also be used with the decimation mode disabled. In this mode, the filter implementation
is 12-tap FIR:
æ
ö
1
11
ç
ç
÷
÷
y(n) =
·
(h6 · x(n) + h7· x(n -1) + h8 · x(n - 2) + ¼ + h11· x(n - 5) + h11· x(n - 6) +¼ + h7· x(n -10) + h6 · x(n -11)
)
2
è
ø
Table 14 Register Map for Custom FIR coefficients
REGISTER
ADDRESS
A7 - A0
in hex
REGISTER FUNCTIONS
D7
D6
D5
D4
D3
D2
D1
D0
1E
Coefficient h0 <7:0>
1F
Coefficient h1 <3:0>
Coefficient h3 <3:0>
Coefficient h5 <3:0>
Coefficient h7 <3:0>
Coefficient h9 <3:0>
Coefficient h11 <3:0>
Coefficient h0 <11:8>
Coefficient h2 <11:8>
Coefficient h4 <11:8>
Coefficient h6 <11:8>
Coefficient h8 <11:8>
Coefficient h10 <11:8>
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
Coefficient h1 <11:4>
Coefficient h2 <7:0>
Coefficient h3 <11:4>
Coefficient h4 <7:0>
Coefficient h5 <11:4>
Coefficient h6 <7:0>
Coefficient h7 <11:4>
Coefficient h8 <7:0>
Coefficient h9 <11:4>
Coefficient h10 <7:0>
Coefficient h11 <11:4>
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PACKAGE INFORMATION
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22-Jan-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
Drawing
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
ADS62P42IRGCR
ADS62P42IRGCT
ADS62P43IRGCR
ADS62P43IRGCT
ADS62P44IRGCR
ADS62P44IRGCT
ADS62P45IRGCR
ADS62P45IRGCT
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
64
64
64
64
64
64
64
64
2500
250
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
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Call TI
Call TI
2500
250
2500
250
2500
250
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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