ADS7067_V01 [TI]
ADS7067 Small, 8-Channel, 16-Bit, 800-kSPS SAR ADC With GPIOs;
| 型号： | ADS7067_V01 |
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TEXAS INSTRUMENTS |
| 描述： | ADS7067 Small, 8-Channel, 16-Bit, 800-kSPS SAR ADC With GPIOs |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS7067
SBASA78A – MARCH 2021 – REVISED OCTOBER 2021
ADS7067 Small, 8-Channel, 16-Bit, 800-kSPS SAR ADC With GPIOs
1 Features
3 Description
•
•
•
Small solution size:
The ADS7067 is a small, 16-bit, 8-channel, high-
precision successive-approximation register (SAR)
analog-to-digital converter (ADC). The ADS7067 has
an integrated capless reference and a reference
buffer that helps reduce the overall solution size by
requiring fewer external components. The wafer-level-
chip-scale package and fewer external components
make this device suitable for space-constrained
applications. The device family includes the ADS7067
(800 kSPS) and the ADS7066 (250 kSPS) speed
variants.
– 1.62-mm × 1.62-mm WCSP
– Space-saving, capless, 2.5-V internal reference
8 channels configurable as any combination of:
– Up to 8 analog inputs, digital inputs, or digital
outputs
Programmable averaging filters:
– Programmable sample size for averaging
– Averaging with internal conversions
– 20-bit resolution for average output
Low-leakage multiplexer with channel sequencer:
– Manual mode
•
•
The ADS7067 features built-in offset calibration for
improved accuracy over wide operating conditions
of the system. The programmable averaging filters
enable higher resolution measurement. The eight
channels of the ADS7067 can be individually
configured as analog inputs, digital inputs, or digital
outputs that enable smaller system size and simplify
circuit design for mixed signal feedback and digital
control.
– On-the-fly mode
– Auto-sequence mode
Excellent AC and DC performance:
– SNR: 90 dB, THD: –100 dB
– Improved SNR with programmable averaging
filters
– INL: ±1 LSB, 16-bit no missing codes
– Internal calibration improves offset and drift
– High sample rate with no latency output:
800 kSPS
The enhanced-SPI enables the ADS7067 in achieving
high throughput at lower clock speeds, thereby
simplifying the board layout and lowering system cost.
The ADS7067 features a cyclic redundancy check
(CRC) for data read and write operations and the
power-up configuration.
•
•
Wide operating range:
– ADC input range: 0 V to VREF and 2 × VREF
– Analog supply: 3 V to 5.5 V
– Digital supply: 1.65 V to 5.5 V
– Temperature range: –40°C to +125°C
Enhanced-SPI digital interface:
– High-speed, 60-MHz SPI interface
Device Information(1)
PART NAME
ADS7067
PACKAGE
BODY SIZE (NOM)
WCSP (16)
1.62 mm × 1.62 mm
2 Applications
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
•
•
•
Optical modules
Optical line cards
Multiparameter patient monitors
ADS7067 Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS7067
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SBASA78A – MARCH 2021 – REVISED OCTOBER 2021
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................6
6.6 Timing Requirements .................................................7
6.7 Switching Characteristics ...........................................7
6.8 Timing Diagrams.........................................................8
6.9 Typical Characteristics................................................9
7 Detailed Description......................................................13
7.1 Overview...................................................................13
7.2 Functional Block Diagram.........................................13
7.3 Feature Description...................................................14
7.4 Device Functional Modes..........................................24
7.5 ADS7067 Registers.................................................. 27
8 Application and Implementation..................................35
8.1 Application Information............................................. 35
8.2 Typical Application.................................................... 35
9 Power Supply Recommendations................................37
9.1 AVDD and DVDD Supply Recommendations...........37
10 Layout...........................................................................38
10.1 Layout Guidelines................................................... 38
10.2 Layout Example...................................................... 38
11 Device and Documentation Support..........................39
11.1 Device Support........................................................39
11.2 Documentation Support.......................................... 39
11.3 Receiving Notification of Documentation Updates..39
11.4 Support Resources................................................. 39
11.5 Trademarks............................................................. 39
11.6 Electrostatic Discharge Caution..............................39
11.7 Glossary..................................................................39
12 Mechanical, Packaging, and Orderable
Information.................................................................... 39
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (March 2021) to Revision A (October 2021)
Page
•
Changed document status from Advance Information to Production Data ........................................................1
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5 Pin Configuration and Functions
1
2
3
4
A
B
C
D
AIN5/GPIO5
DVDD
AVDD
REF
AIN4/GPIO4
AIN3/GPIO3
AIN2/GPIO2
AIN6/GPIO6
AIN1/GPIO1
SDI
AIN7/GPIO7
AIN0/GPIO0
SDO
GND
CS
SCLK
Not to scale
Figure 5-1. YBH Package, 16-Pin WCSP, Top View
Table 5-1. Pin Functions
PIN
NAME
FUNCTION(1)
DESCRIPTION
NO.
A1
Channel 5; configurable as either an analog input (default) or general-purpose input/output
(GPIO).
AIN5/GPIO5
AI, DI, DO
A2
A3
A4
B1
B2
B3
B4
C1
C2
C3
DVDD
AVDD
P
P
P
Digital I/O supply voltage. Connect a 1-µF capacitor to GND.
Analog supply voltage. Connect a 1-µF capacitor to GND.
REF
Internal reference buffer output; external reference input. Connect a 1-µF capacitor to GND.
AIN4/GPIO4
AIN6/GPIO6
AIN7/GPIO7
GND
AI, DI, DO Channel 4; configurable as either an analog input (default) or GPIO.
AI, DI, DO Channel 6; configurable as either an analog input (default) or GPIO.
AI, DI, DO Channel 7; configurable as either an analog input (default) or GPIO.
P
Ground for power supply, all analog and digital signals are referred to this pin.
AIN3/GPIO3
AIN1/GPIO1
AIN0/GPIO0
AI, DI, DO Channel 3; configurable as either an analog input (default) or GPIO.
AI, DI, DO Channel 1; configurable as either an analog input (default) or GPIO.
AI, DI, DO Channel 0; configurable as either an analog input (default) or GPIO.
Chip-select input pin; active low.
C4
CS
DI
The device takes control of the data bus when CS is low.
The SDO pin goes to Hi-Z when CS is high.
D1
D2
D3
D4
AIN2/GPIO2
SDI
AI, DI, DO Channel 2; configurable as either an analog input (default) or GPIO.
DI
DO
DI
Serial data input pin for SPI interface.
Serial data output pin for SPI interface.
Clock input pin for the SPI interface.
SDO
SCLK
(1) AI = analog input, DI = digital input, DO = digital output, P = power supply.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN
–0.3
MAX
UNIT
V
DVDD to GND
5.5
5.5
AVDD to GND
–0.3
V
AINx/GPIOx(2) to GND
GND – 0.3
GND – 0.3
GND – 0.3
–10
AVDD + 0.3
AVDD + 0.3
5.5
V
REF to GND
V
Digital inputs (CS, SDI, SCLK) to GND
Input current to any pin except supply pins(3)
Junction temperature, TJ
Storage temperature, Tstg
V
10
mA
°C
°C
–40
150
–60
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) AINx/GPIOx refers to AIN0/GPIO0, AIN1/GPIO1, AIN2/GPIO2, AIN3/GPIO3, AIN4/GPIO4, AIN5/GPIO5, AIN6/GPIO6, and AIN7/
GPIO7 pins.
(3) Pin current must be limited to 10 mA or less.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per ANSI/ESDA/
JEDEC JS-002, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER SUPPLY
AVDD
DVDD
Analog power supply
Digital power supply
AVDD to GND
DVDD to GND
3
3.3
3.3
5.5
5.5
V
V
1.65
REFERENCE VOLTAGE
Internal reference
External reference
2.5
Reference voltage to
VREF
V
the ADC
ANALOG INPUTS
2.4
AVDD
RANGE = 0b
RANGE = 1b
0
0
VREF
2 x VREF
FSR
Full-scale input range
V
V
VIN
Absolute input voltage AINx(1) to GND
–0.1
AVDD + 0.1
TEMPERATURE RANGE
TA
Ambient temperature
–40
25
125
°C
(1) AINx refers to analog inputs AIN0, AIN1, AIN2, AIN3, AIN4, AIN5, AIN6, and AIN7.
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6.4 Thermal Information
ADS7067
THERMAL METRIC(1)
YBH (WCSP)
16 PINS
80.2
UNIT
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
0.4
18.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.2
ΨJB
18.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
at AVDD = 3 V to 5.5 V, DVDD = 1.65 V to 5.5 V, VREF = 2.5 V (internal), and maximum throughput (unless otherwise noted);
minimum and maximum values at TA = -40°C to +125°C; typical values at TA = 25°C
PARAMETER
ANALOG INPUTS
CIN Input capacitance
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC and MUX capacitance
30
pF
DC PERFORMANCE
Resolution
No missing codes
16
±0.4
±1
Bits
LSB
DNL
Differential nonlinearity
–0.75
–4
0.75
4
INL
Integral nonlinearity
Input offset error
LSB
V(OS)
dVOS/dT
Post offset calibration, OSR[2:0] = 7
Post offset calibration, OSR[2:0] = 7
OSR[2:0] = 7
–9
±0.5
±0.6
0.5
9
LSB
Input offset thermal drift
Offset error match
Gain error(1)
ppm/°C
LSB
–2.75
–0.06
2.75
0.06
GE
External VREF = 2.5 V, OSR[2:0] = 7
External VREF = 2.5 V, OSR[2:0] = 7
OSR[2:0] = 7
±0.01
±0.5
±0.001
%FSR
ppm/°C
%FSR
dGE/dT
Gain error thermal drift
Gain error match
–0.005
0.005
AC PERFORMANCE
fIN = 2 kHz, VREF = 2.5 V (internal)
fIN = 2 kHz, VREF = 5 V, AVDD = 5 V
fIN = 2 kHz, VREF = 2.5 V (internal)
fIN = 2 kHz, VREF = 5 V, AVDD = 5 V
fIN = 2 kHz
82.3
86.7
82.4
87.7
85.1
89.3
85.3
90
SINAD
SNR
Signal-to-noise + distortion ratio
dB
dB
Signal-to-noise ratio
THD
Total harmonic distortion
Spurious-free dynamic range
Isolation crosstalk
–100
101
dB
dB
dB
SFDR
fIN = 2 kHz
fIN = 10 kHz
–110
REFERENCE
VREF
Internal reference output voltage(3)
at TA = 25℃
2.497
1
2.5
6
2.503
V
Internal reference voltage
temperature drift
dVREF/dT
CREF
19 ppm/°C
Decoupling capacitor at REF pin
10
µF
DIGITAL INPUTS
For CS, SCLK, and SDI pins
For GPIOX (2) pins
–0.3
–0.3
0.3 DVDD
0.3 AVDD
DVDD
VIL
VIH
Input low logic level
V
V
For CS, SCLK, and SDI pins
For GPIOX pins
0.7 DVDD
0.7 AVDD
Input high logic level
AVDD
DIGITAL OUTPUTS
VOL Output low logic level
For SDO pin, IOL = 500 µA sink
0
0
0.2 DVDD
0.2 AVDD
DVDD
V
V
For GPIOX (2) pins, IOL = 500 µA sink
For SDO pin, IOH = 500 µA source
For GPIOX (2) pins, IOH = 500 µA source
0.8 DVDD
0.8 AVDD
VOH
Output high logic level
AVDD
POWER SUPPLY
AVDD = 3.3 V, external reference
AVDD = 3.3 V, internal reference
No conversion, external reference
No conversion, internal reference
1
1.5
2
mA
µA
2.8
IAVDD
Analog supply current
250
800
(1) These specifications include full temperature range variation but not the error contribution from internal reference.
(2) GPIOX refers to GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, and GPIO7 pins.
(3) Does not include the variation in voltage resulting from solder shift effects.
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6.6 Timing Requirements
at AVDD = 3 V to 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum
values at TA = –40°C to +125°C; typical values at TA = 25°C.
MIN
MAX
UNIT
CONVERSION CYCLE
fCYCLE
tCYCLE
tQUIET
tACQ
Sampling frequency
800
kSPS
s
ADC cycle-time period
Quiet acquisition time
Acquisition time
1/fCYCLE
20
ns
300
ns
tWH_CSZ
tWL_CSZ
Pulse duration: CS high
Pulse duration: CS low
220
ns
210
ns
SPI INTERFACE TIMINGS
fCLK
Maximum SCLK frequency
60
MHz
ns
tCLK
Minimum SCLK time period
16.67
0.45
0.45
15
tPH_CK
tPL_CK
tSU_CSCK
tSU_CKDI
tHT_CKDI
tD_CKCS
SCLK high time
0.55
0.55
tCLK
tCLK
ns
SCLK low time
Setup time: CS falling to the first SCLK capture edge
Setup time: SDI data valid to the SCLK capture edge
Hold time: SCLK capture edge to data valid on SDI
Delay time: last SCLK falling to CS rising
6.4
ns
4
ns
0.8
ns
6.7 Switching Characteristics
at AVDD = 3 V to 5.5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum
values at TA = –40°C to +125°C; typical values at TA = 25°C.
PARAMETER
CONVERSION CYCLE
TEST CONDITIONS
MIN
MAX
UNIT
tCONV
RESET
tPU
ADC conversion time
950
ns
Power-up time for device
AVDD ≥ 3 V
5
5
ms
ms
Delay time; RST bit = 1b to device reset
complete(1)
tRST
SPI INTERFACE TIMINGS
tDEN_CSDO Delay time: CS falling to data enable
tDZ_CSDO
22
50
ns
ns
Delay time: CS rising to SDO going Hi-Z
Delay time: SCLK launch edge to (next)
data valid on SDO
tD_CKDO
16
ns
(1) RST bit is automatically reset to 0b after tRST
.
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6.8 Timing Diagrams
tCYCLE
tCONV
tACQ
Acquiring
Sample N
CS
Converting Sample N
Acquiring Sample N+1
SDI
MSB
MSB
MSB-1
MSB-2
MSB-2
LSB+1
LSB+1
LSB
LSB
HI-Z
SDO
MSB-1
tQUIET
SCLK
Figure 6-1. Conversion Cycle Timing
tCLK
tPH_CK
tPL_CK
SCLK(1)
CS
tSU_CKDI
tHT_CKDI
tSU_CSCK
tD_CKCS
SCLK(1)
SDI
tDEN_CSDO
tDZ_CSDO
tD_CKDO
SDO
SDO
Figure 6-2. SPI Interface Timing
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6.9 Typical Characteristics
at TA = 25°C, AVDD = 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted)
0.5
0.3
1.1
0.6
0.1
0.1
-0.1
-0.3
-0.5
-0.4
-0.9
-1.4
0
16384
32768
ADC Output Code
49152
65535
0
16384
32768
ADC Output Code
49152
65535
C002
C004
Typical DNL = ±0.4 LSB
Typical INL = ±1 LSB
Figure 6-3. Typical DNL
Figure 6-4. Typical INL
0.8
0.4
0
2.4
1.2
0
-0.4
-0.8
-1.2
Minimum
Maximum
Minimum
Maximum
-40
-7
26 59
Free-Air Temperature (°C)
92
125
-2.4
-40
-7
26 59
Free-Air Temperature (°C)
92
125
C003
C005
Figure 6-5. DNL vs Temperature
Figure 6-6. INL vs Temperature
0.8
2.5
1.5
Minimum
Maximum
Minimum
Maximum
0.4
0
0.5
-0.5
-1.5
-2.5
-0.4
-0.8
2.5
3
3.5
External Reference Voltage (V)
4
4.5
5
2.5
3
3.5
External Reference Volatge (V)
4
4.5
5
C020
C021
Figure 6-7. DNL vs External Reference Voltage
Figure 6-8. INL vs External Reference Voltage
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6.9 Typical Characteristics (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted)
0.5
0
0.015
0.014
0.013
0.012
0.011
0.01
-0.5
-1
-1.5
-2
-40
-7
26 59
Free-Air Temperature (°C)
92
125
-40
-7
26 59
Free-Air Temperature (°C)
92
125
C006
C007
Figure 6-9. Offset Error vs Temperature
Figure 6-10. Gain Error vs Temperature
-0.15
-0.22
-0.29
-0.36
-0.43
-0.5
0.014
0.011
0.008
0.005
0.002
2.5
3
3.5
External Reference Voltage (V)
4
4.5
5
2.5
3
3.5
External Reference Voltage (V)
4
4.5
5
C016
C017
Figure 6-11. Offset Error vs External Reference Voltage
Figure 6-12. Gain Error vs External Reference Voltage
0
24000
20099
19987
20000
16000
12000
8000
4000
0
-40
-80
9977
9994
-120
-160
2497
2420
283
254
10
14
1
0
80000
160000
Frequency (Hz)
240000
320000
400000
C001
C008
Standard deviation = 1.05 LSB
Figure 6-13. DC Input Histogram
fIN = 2 kHz, SNR = 85.3 dBFS, THD = –97 dB
Figure 6-14. Typical FFT
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6.9 Typical Characteristics (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted)
86.5
86
14.2
14.1
14
-97
-98.5
-100
111
108
105
102
99
SINAD (dBFS)
SNR (dBFS)
ENOB (Bits)
THD(dBFS)
SFDR(dBFS)
85.5
85
13.9
13.8
13.7
-101.5
84.5
84
-103
-40
-7
26 59
Free-Air Temperature (°C)
92
125
-40
-7
26 59
Free-Air Temperature (°C)
92
125
C009
C011
Figure 6-15. Noise Performance vs Temperature
Figure 6-16. Distortion Performance vs Temperature
91
14.7
-96
107.5
SINAD (dBFS)
SNR (dBFS)
ENOB (Bits)
THD (dBFS)
SFDR (dBFS)
90
89
88
87
86
85
14.55
14.4
-98
105
14.25
14.1
-100
-102
-104
102.5
100
13.95
13.8
97.5
2.5
3
3.5
External Reference Voltage (V)
4
4.5
5
2.5
3
3.5
External Reference Voltage (V)
4
4.5
5
C010
C012
Figure 6-17. Noise Performance vs External Reference Voltage
Figure 6-18. Distortion Performance vs External Reference
Voltage
2450
2390
2330
2270
2210
2150
2650
2560
2470
2380
2290
2200
3
3.5
4
4.5
AVDD (V)
5
5.5
-40
-7
26 59
Free-Air Temperature (°C)
92
125
C014
C013
TA = 25 °C
Figure 6-20. Analog Supply Current vs AVDD
AVDD = 5 V
Figure 6-19. Analog Supply Current vs Temperature
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6.9 Typical Characteristics (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted)
2400
2100
1800
1500
1200
900
-45
External reference
Internal reference
-60
-75
-90
-105
-120
600
0
200
400
Throughput (kSPS)
600
800
1
10
100
Frequency (kHz)
1000
10000
C015
C022
Figure 6-21. Analog Supply Current vs Throughput
Figure 6-22. PSRR vs Frequency
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7 Detailed Description
7.1 Overview
The ADS7067 is a 16-bit, successive approximation register (SAR) analog-to-digital converter (ADC) with
an analog multiplexer. This device integrates a reference, reference buffer, low-dropout regulator (LDO), and
features high performance at full throughput and low-power consumption.
The ADS7067 supports unipolar, single-ended analog input signals. The internal reference generates a low-drift,
buffered, 2.5-V reference output. The device uses an internal clock to perform conversions. At the end of the
conversion process, the device enters an acquisition phase.
7.2 Functional Block Diagram
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7.3 Feature Description
7.3.1 Analog Input and Multiplexer
The eight channels of the multiplexer can be independently configured as ADC inputs or general-purpose inputs/
outputs (GPIOs). As shown in Figure 7-1, each input pin has ESD protection diodes to AVDD and GND. On
power-up or after device reset, all eight channels of the multiplexer are configured as analog inputs.
GPO_VALUE[0]
GPIO_CFG[0]
AVDD
GPI_VALUE[0]
PIN_CFG[0]
AIN0 / GPIO0
RSW
SW
MUX
CSH
Multiplexer
AVDD
ADC
AIN7 / GPIO7
PIN_CFG[7]
GPI_VALUE[7]
GPIO_CFG[7]
GPO_VALUE[7]
Figure 7-1. Analog Inputs, GPIOs, and ADC Connections
Figure 7-1 shows an equivalent circuit for the pins configured as analog inputs. The ADC sampling switch is
represented by an ideal switch (SW) in series with a resistor (RSW, typically 150 Ω) and a sampling capacitor
(CSH, typically 30 pF). During acquisition, the SW switch is closed to allow the signal on the selected analog
input channel to charge the internal sampling capacitor. During conversion, the SW switch is opened to
disconnect the analog input channel from the sampling capacitor.
The multiplexer channels can be configured as GPIOs in the PIN_CFG register. On power-up, all channels of
the multiplexer are configured as analog inputs. The direction of a GPIO, input or output, can be set in the
GPIO_CFG register. The logic level of channels configured as digital inputs can be read from the GPI_VALUE
register. The digital outputs can be accessed by writing to the GPO_VALUE register. The digital outputs can be
configured as open-drain or push-pull in the GPO_DRIVE_CFG register.
7.3.2 Reference
The ADS7067 has a precision, low-drift voltage reference internal to the device.
7.3.2.1 External Reference
External reference is the default configuration on power-up or after device reset. An external reference voltage
source can be connected to the REF pin with an appropriate decoupling capacitor placed between the REF and
GND pins. Best SNR is achieved with a 5-V external reference because the internal reference is limited to 2.5 V.
For improved thermal drift performance, a reference from the REF60xx family (REF6025, REF6030, REF6033,
REF6041, REF6045, or REF6050) is recommended.
7.3.2.2 Internal Reference
The device features an internal reference source with a nominal output value of 2.5 V. On power-up, the internal
reference is disabled by default. To enable the internal reference, set EN_REF = 1b in the GENERAL_CFG
register. A minimum 1-µF decoupling capacitor is recommended to be placed between the REF and GND pins.
The capacitor must be placed as close to the REF pin as possible. The REF pin has ESD protection diodes
connected to the AVDD and GND pins.
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7.3.3 ADC Transfer Function
The ADC output is in straight binary format. The full-scale input range (FSR) of the ADC is determined by the
RANGE bit. On power-up, the FSR is 0 V to VREF. When using the 2 x VREF mode (RANGE = 1b), the ADC
can measure analog inputs up to two times the voltage reference. Equation 1 can be used to compute the ADC
resolution:
1 LSB = FSR / 2N
(1)
where:
•
•
FSR = Full-scale input range of the ADC
N = 16
Figure 7-2 and Table 7-1 show the ideal transfer characteristics for this device.
0xFFFF
0x8001
0x8001
0x0001
0x0000
VIN
(VREF œ 1 LSB)
RANGE = 0b
RANGE = 1b
1 LSB
1 LSB
VREF/2
VREF
(VREF/2 + 1 LSB)
(VREF + 1 LSB)
(2 x VREF œ 1 LSB)
Figure 7-2. Ideal Transfer Characteristics
Table 7-1. Transfer Characteristics
INPUT VOLTAGE
CODE
IDEAL OUTPUT CODE
RANGE = 0b
≤1 LSB
RANGE = 1b
≤1 LSB
Zero
0000
0001
8000
8001
FFFF
1 LSB to 2 LSBs
1 LSB to 2 LSBs
Zero + 1
(VREF / 2) to (VREF / 2) + 1 LSB
(VREF / 2) + 1 LSB to (VREF / 2) + 2 LSBs
≥ VREF – 1 LSB
VREF to VREF + 1 LSB
VREF + 1 LSB to VREF + 2 LSBs
≥ 2 x VREF – 1 LSB
Mid-scale code
Mid-scale code + 1
Full-scale code
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7.3.4 ADC Offset Calibration
The variation in ADC offset error resulting from changes in temperature or reference voltage can be calibrated by
setting the CAL bit in the GENERAL_CFG register. The CAL bit is reset to 0 after calibration. The host can poll
the CAL bit to check the ADC offset calibration completion status.
7.3.5 Programmable Averaging Filters
The ADS7067 features a programmable averaging filter that can be used to average analog input samples to
output a higher resolution measurement. The averaging filter can be enabled by programming the OSR[2:0] bits
in the OSR_CFG register to the averaging factor desired. The averaging configuration is common to all analog
input channels. As shown in Figure 7-3, the output of the averaging filter is 20 bits long. In manual mode and
auto-sequence mode of conversion, only the first conversion for the selected analog input channel must be
initiated by the host, as shown in Figure 7-3; any remaining conversions are generated internally. The time (tAVG
)
required to complete the averaging operation is determined by the sampling speed and number of samples to
be averaged; see the Oscillator and Timing Control section for more details. After completion, the averaged
20-bit result, as shown in Figure 7-3, can be read-out. For information on the programmable averaging filters and
performance results see the Resolution-Boosting ADS7066 Using Programmable Averaging Filter application
report.
In autonomous mode of operation, samples from analog input channels that are enabled in the
AUTO_SEQ_CH_SEL register are averaged sequentially.
Sample
AINx
(start of averaging)
Sample
AINx
Sample
AINx
CS
SCLK
SDO
N œ 1 conversions triggered
internally
Maximum tAVG = N samples x tCYCLE_OSR x 1.06
[19:0] Data
20 clocks
Figure 7-3. Averaged Output Data
7.3.6 CRC on Data Interface
The cyclic redundancy check (CRC) is an error checking code that detects communication errors to and from the
host. CRC is the division remainder of the data payload bytes by a fixed polynomial. The data payload is two or
three bytes, depending on the output data format; see the Output Data Format section for details on output data
format. The CRC mode is optional and is enabled by the CRC_EN bit in the GENERAL_CFG register.
The CRC data byte is the 8-bit remainder of the bitwise exclusive-OR (XOR) operation of the argument by
a CRC polynomial. The CRC polynomial is based on the CRC-8-CCITT: X8 + X2 + X1 + 1. The nine binary
polynomial coefficients are: 100000111. The CRC calculation is preset with 1 data values. For more details about
the CRC implementation and for a software example, see the Implementation of CRC for ADS7066 application
report.
The host must compute and append the appropriate CRC to the command string in the same SPI frame (see
the Register Read/Write Operation section). The ADC also computes the expected CRC corresponding to the
payload received from the host and compares the calculated CRC code to the CRC received from the host. The
CRC received from the host and the CRC calculated by the ADC over the received payload are compared to
check for an exact match.
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•
•
If the calculated CRC and received CRC match then the data payload received from the host is valid.
If the calculated CRC and received CRC do not match then the data payload received from the host is not
valid and the command does not execute. The CRCERR_IN flag is set to 1b. ADC conversion data read
and register read processes, with a valid CRC from the host, are still supported. The error condition can be
detected, as listed in Table 7-2, by either status flags or by a register read. Further register writes to the
device are blocked until the CRCERR_IN flag is cleared to 0b. Register write operations, with a valid CRC
from the host, to the SYSTEM_STATUS (address = 0x00) and GENERAL_CFG (address = 0x01) registers
are still supported.
Table 7-2. Configuring Notifications When a CRC Error is Detected
CRC ERROR NOTIFICATION
CONFIGURATION
APPEND_STATUS = 10b
—
DESCRIPTION
4-bit status flags, containing the CRCERR_IN bit appended to the
Status flags
ADC data; see the Output Data Format section for details.
Register read
Read the CRCERR_IN bit to check if a CRC error was detected.
For a conversion data read or register data read, the ADC responds with a CRC that is computed over the
requested data payload bytes. The response data payload is one, two, or three bytes depending on the data
operation (see the Output CRC (Device to Host) section).
7.3.7 Oscillator and Timing Control
The device uses an internal oscillator for conversion. When using the averaging module, the host initiates the
first conversion and subsequent conversions are generated internally by the device. When the device generates
the start of a conversion, the sampling rate can be controlled as described in Table 7-3 by the OSC_SEL and
CLK_DIV[3:0] register fields.
The conversion time of the device, given by tCONV in the Switching Characteristics table in the Specifications
section, is independent of the OSC_SEL and CLK_DIV[3:0] configuration.
Table 7-3. Configuring the Sampling Rate for Internal Conversion Start Control
OSC_SEL = 0
OSC_SEL = 1
CLK_DIV[3:0]
SAMPLING FREQUENCY, fCYCLE_OSR
(kSPS)
CYCLE TIME,
tCYCLE_OSR (µs)
SAMPLING FREQUENCY, fCYCLE_OSR
(kSPS)
CYCLE TIME,
tCYCLE_OSR (µs)
Reserved. Do not
use.
0000b
Reserved. Do not use.
31.25
32
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
666.67
500
1.5
2
20.83
15.63
10.42
7.81
5.21
3.91
2.60
1.95
1.3
48
64
333.33
250
3
96
4
128
192
256
384
512
768
1024
1536
2048
3072
166.7
125
6
8
83
12
16
24
32
48
64
96
62.5
41.7
31.3
20.8
15.6
10.4
0.98
0.65
0.49
0.33
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7.3.8 Diagnostic Modes
The ADS7067 features a programmable test voltage generation circuit that can be used for ADC diagnostics.
7.3.8.1 Bit-Walk Test Mode
To enable write access to the configuration registers for diagnostics, write 0x96 in the DIAGNOSTICS_KEY
register. To enable bit-walk test mode, configure BITWALK_EN = 1b. In the bit-walk test mode (see Figure 7-1),
the sampling switch (SW) remains open and the test voltage is applied on the sampling capacitor (CSH) during
the acquisition phase of the ADC. In diagnostic mode, the conversion process of the ADC remains the same as
normal device operation. The ADC starts the conversion phase on the rising edge of CS and outputs the code
corresponding to the sampled test voltage. The output code of the ADC is expected to be proportional to the test
voltage, as shown in Equation 2, after adjusting for DC errors (such as INL, gain error, offset error, and thermal
drift of offset and gain errors).
Test voltage
Output code = l
× 216p ± TUE
VREF
(2)
where
TUE = Total unadjusted error, given by the root sum square of the offset error, gain error, and INL
•
The test voltage is generated by a DAC configured by the BIT_SAMPLE_MSB and BIT_SAMPLE_LSB registers.
Because the test voltage is derived from the ADC reference, as given by Equation 3, this diagnostic mode is not
sensitive to variations in reference voltage.
VREF
Test voltage =
± TUE
BIT_SAMPLE[15: 0]
(3)
To resume conversion of the ADC input signal, configure BITWALK_EN = 0b.
7.3.8.2 Fixed Voltage Test Mode
For diagnostics, the ADS7067 features a fixed 1.8 V (typical) test voltage which can be internally connected to
AIN6. To connect AIN6 to the internal test voltage, set VTEST_EN = 1b. When using the fixed voltage test mode,
AIN6 pin must be left floating and should not be connected to any external circuit.
If bit-walk test mode is enabled (that is, BITWALK_EN = 1b), enabling the fixed voltage test mode will connect
AIN6 to the test voltage but the conversion result would be according to bit-walk test mode configuration.
7.3.9 Output Data Format
Figure 7-4 illustrates that the output data payload consists of a combination of the conversion result, data
bits from averaging filters, status flags, and channel ID. The conversion result is MSB aligned. If averaging
is enabled, the output data from the ADC are 20 bits long, otherwise the data are 16 bits long. Optionally,
the 4-bit channel ID or status flags can be appended at the end of the output data by configuring the
APPEND_STATUS[1:0] fields.
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CS
SCLK
16
17
18
19
20
22
23
24
21
1
2
Data output when averaging is disabled
OSR[2:0] = 00b
SDO
LSB
Channel ID / Status Flags
4 bits optional
MSB
16 bit ADC data
Data output when averaging is enabled
OSR[2:0] > 00b
SDO
LSB
Channel ID / Status Flags
4 bits optional
MSB
20 bit averaged ADC data
Figure 7-4. SPI Frames for Reading Data
7.3.9.1 Status Flags
Status flags can be appended to the ADC output by setting APPEND_STATUS = 10b. The status flag is
appended only to frames where ADC data are being read. Status flags are not appended to data corresponding
to a register read operation or when FIX_PAT = 1b. The 4-bit status flag field is constructed as follows:
Status flag[3:0] = { 1, VTEST_MODE, CRCERR_IN, DIAG_MODE }
where:
•
•
•
VTEST_MODE: This flag is set if the current data frame corresponds to fixed voltage test mode (see the
Fixed Voltage Test Mode section).
CRCERR_IN: This flag indicates the status of the CRC verification of data received from the digital interface.
This flag is the same as the CRCERR_IN bit in the SYSTEM_STATUS register.
DIAG_MODE: This flag is set if the current data frame corresponds to the bit-walk test mode (see the
Bit-Walk Test Mode section).
7.3.9.2 Output CRC (Device to Host)
A CRC byte can be appended to the output data by configuring CRC_EN to 1b. When the CRC module is
enabled, the host must use 32-bit frames for SPI communication. The device outputs the data payload followed
by the CRC byte computed over the data payload. Additional 0s can be appended by the ADC after the
CRC byte to complete the 32-bit SPI frame (see Table 7-4). The host must compute and compare the CRC
corresponding to the data payload with the CRC received from the ADC. The additional 0s appended by the
device after the CRC byte must be excluded by the host for computing the CRC.
7.3.9.3 Input CRC (Host to Device)
When the CRC module is enabled, the host must always communicate with the ADC using 32-bit SPI frames
comprised of a 24-bit data payload and an 8-bit CRC byte. The host must calculate the CRC byte to be
appended based on a 24-bit payload. The ADC computes a CRC over the 24-bit data payload and compares the
result with the CRC received from the host.Table 7-4 lists the output data frames for the CRC_EN bit.
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Table 7-4. Output Data Frames
CRC_EN
OSR[2:0]
APPEND_STATUS[1:0]
OUTPUT DATA FRAME
No flags (00b or 11b)
Channel ID (01b)
Status flags (10b)
No flags (00b or 11b)
Channel ID (01b)
Status flags (10b)
No flags (00b or 11b)
Channel ID (01b)
Status flags (10b)
No flags (00b or 11b)
Channel ID (01b)
Status flags (10b)
{Conversion result [15:0], 8'b0}
No averaging
{Conversion result [15:0], CHID[3:0], 4'b0}
{Conversion result [15:0], status flags[3:0], 4'b0}
{Conversion result [19:0], 4'b0}
CRC module
disabled
(CRC_EN = 0)
Averaging
enabled
{Conversion result [19:0], CHID[3:0]}
{Conversion result [19:0], status flags[3:0]}
{Conversion result [15:0], CRC[7:0], 8'b0}
No averaging
{Conversion result [15:0], CHID[3:0], 4'b0, CRC[7:0]}
{Conversion result [15:0], status flags[3:0], 4'b0, CRC[7:0]}
{Conversion result [19:0], 4'b0, CRC[7:0]}
CRC module
enabled
(CRC_EN = 1)
Averaging
enabled
{Conversion result [19:0], CHID[3:0], CRC[7:0]}
{Conversion result [19:0], status flags[3:0], CRC[7:0]}
7.3.10 Device Programming
7.3.10.1 Enhanced-SPI Interface
The device features an enhanced-SPI interface that allows the host controller to operate at slower SCLK
speeds and still achieve full throughput. As described in Table 7-5, the host controller can use any of the four
SPI-compatible protocols (SPI-00, SPI-01, SPI-10, or SPI-11) to access the device.
Table 7-5. SPI Protocols for Configuring the Device
SCLK POLARITY
(At the CS Falling Edge)
SCLK PHASE
(Capture Edge)
PROTOCOL
CPOL_CPHA[1:0]
DIAGRAM
SPI-00
SPI-01
SPI-10
SPI-11
Low
Low
High
High
Rising
Falling
Falling
Rising
00b
01b
10b
11b
Figure 7-5
Figure 7-6
Figure 7-5
Figure 7-6
On power-up, the device defaults to the SPI-00 protocol for data read and data write operations. To select a
different SPI-compatible protocol, program the CPOL_CPHA[1:0] field. This first write operation must adhere to
the SPI-00 protocol. Any subsequent data transfer frames must adhere to the newly-selected protocol.
CS
SCLK
SDO
CS
CPOL = 0
CPOL = 1
CPOL = 0
CPOL = 1
SCLK
MSB
MSB-1
LSB+1
LSB
SDO
MSB-2
0
MSB
MSB-1
LSB+1
LSB
Figure 7-5. Standard SPI Timing Protocol
(CPHA = 0)
Figure 7-6. Standard SPI Timing Protocol
(CPHA = 1)
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7.3.10.2 Daisy-Chain Mode
The ADS7067 can operate as a single converter or in a system with multiple converters. System designers
can take advantage of the simple, high-speed, enhanced-SPI serial interface by cascading converters in a
daisy-chain configuration when multiple converters are used. No register configuration is required to enable
daisy-chain mode. Figure 7-7 shows a typical connection of three converters in daisy-chain mode.
MISO
SDO
SDI
SDO
SDI
SDO
SDI
MOSI
ADS7067
(ADC C)
ADS7067
(ADC B)
ADS7067
(ADC A)
Host
SCLK
SCLK
SCLK
CS
CS
CS
SCLK
CS
Figure 7-7. Multiple Converters Connected Using Daisy-Chain Mode
When the ADS7067 is connected in daisy-chain mode, the serial input data passes through the ADS7067 with a
24-SCLK delay, as long as CS is active. Figure 7-8 shows a detailed timing diagram of this mode. In Figure 7-8,
the conversion in each converter is performed simultaneously.
Sample ADC A
Sample ADC B
Sample ADC C
CS
tCONV
SCLK
1
24
25
48
49
72
MISO
MOSI
ADC C
ADC B
ADC A
DIN for
ADC C
DIN for
ADC B
DIN for
ADC A
Figure 7-8. Simplified Daisy-Chain Mode Timing
The ADS7067 supports daisy-chain mode for output data payloads up to 24 bits long; see the Output Data
Format section for more details. If either the status flags or channel ID are appended (APPEND_STATUS ≠ 00b)
and the CRC module is enabled (CRC_EN = 1b), then the serial input data does not pass through the ADS7067
and daisy-chain mode is disabled.
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7.3.10.3 Register Read/Write Operation
The device supports the commands listed in Table 7-6 to access the internal configuration registers
Table 7-6. Opcodes for Commands
OPCODE
0000 0000b
0001 0000b
0000 1000b
0001 1000b
0010 0000b
COMMAND DESCRIPTION
No operation
Single register read
Single register write
Set bit
Clear bit
The clear bit command clears the specified bits (identified by 1) at the 8-bit address (without affecting the other
bits), and the set bit command sets the specified bits (identified by 1) at the 8-bit address (without affecting the
other bits).
7.3.10.3.1 Register Write
A 24-bit SPI frame is required to write data to configuration registers. The 24-bit data on SDI, as shown in
Figure 7-9, consists of an 8-bit write command (0000 1000b), an 8-bit register address, and 8-bit data. The write
command is decoded on the CS rising edge and the specified register is updated with the 8-bit data specified in
the register write operation.
CS
SCLK
18
1
2
8
9
10
16
17
24
0000 1000b
(WR_REG)
SDI
8-bit Address
8-bit Data
Figure 7-9. Register Write Operation
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7.3.10.3.2 Register Read
A register read operation consists of two SPI frames: the first SPI frame initiates a register read and the second
SPI frame reads data from the register address provided in the first frame. As shown in Figure 7-10, the read
command (0001 0000b), the 8-bit register address, and the 8-bit dummy data are sent over the SDI pin during
the first 24-bit frame. On the rising edge of CS, the read command is decoded and the requested register data
are available for reading during the next frame. During the second frame, the first eight bits on SDO correspond
to the requested register read. During the second frame, SDI can be used to initiate another operation or can be
set to 0.
CS
SCLK
18
18
1
2
8
9
10
16
17
24
1
2
8
9
10
16
17
24
0001 0000b
(RD_REG)
SDI
8-bit Address
0000 0000b
Command
8-bit Address
8-bit Data
Optional; can set SDI = 0
SDO
8-bit Register Data
Figure 7-10. Register Read Operation
7.3.10.3.2.1 Register Read With CRC
A register read consists of two SPI frames, as described in the Register Read section. When the CRC module is
enabled during a register read, as shown in Figure 7-11, the device appends an 8-bit output CRC byte along with
8-bit register data. The output CRC is computed by the device on the 8-bit register data.
CS
SCLK
1
8
9
1
8
9
16
17
24
25
32
16
17
24
25
32
Input
CRC[7:0]
0001 0000b
(RD_REG)
8-bit
Address
0000
0000b
Input
CRC[7:0]
SDI
NOP (SDI = 0)
Input CRC is calculated
on 24 bit payload
Input CRC is calculated
on 24 bit payload
Data Payload (24 bit)
Data Payload (24 bit)
Register
Data
Output
CRC[7:0]
SDO
Output CRC is calculated on 8 bit payload
Data Payload (8 bit)
Figure 7-11. Register Read With CRC
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7.4 Device Functional Modes
Table 7-7 lists the functional modes supported by the ADS7067.
Table 7-7. Functional Modes
FUNCTIONAL MODE
Manual
CONVERSION CONTROL
MUX CONTROL
Register write to MANUAL_CHID
First 5 bits after CS falling edge
Channel sequencer
SEQ_MODE[1:0]
CS rising edge
CS rising edge
00b
10b
01b
01b
On-the-fly
Auto-sequence
Autonomous
CS rising edge
Internal to the device
Channel sequencer
The device powers up in manual mode and can be configured into either of these modes by writing the
configuration registers for the desired mode.
7.4.1 Device Power-Up and Reset
On power up, the BOR bit is set indicating a power-cycle or reset event. The device can be reset by setting the
RST bit or by recycling the power on the AVDD pin.
7.4.2 Manual Mode
Manual mode allows the external host processor to directly select the analog input channel. Figure 7-12 shows
steps for operating the device in manual mode.
Idle
SEQ_MODE = 0b
Configure channels as AIN/GPIO using PIN_CFG
Calibrate offset error (CAL = 1b)
Select Manual mode
(SEQ_MODE = 00b)
Configure desired Channel ID in MANUAL_CHID field
Host starts conversion and reads conversion result
No
Yes
Same
Channel ID?
Figure 7-12. Device Operation in Manual Mode
In manual mode, the command to switch to a new channel, cycle N in Figure 7-13, is decoded by the device on
the CS rising edge. The CS rising edge is also the start of the conversion cycle, and thus the device samples
the previously selected MUX channel in cycle N+1. The newly selected analog input channel data are available
in cycle N+2. For switching the analog input channel, a register write to the MANUAL_CHID field requires 24
clocks; see the Register Write section for more details. After a channel is selected, the number of clocks required
for reading the output data depends on the device output data frame size; see the Output Data Format section
for more details.
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Sample
AINx
Sample
AINx
Sample
AINy
Sample
AINz
tCONV
tCYCLE
CS
SCLK
SDI
Switch to AINy
Switch to AINz
Switch to AINx
Data AINy
SDO
Data AINx
24 clocks
Data AINx
100-ns
MUX OUT = AINx
MUX OUT = AINy
MUX OUT = AINz
MUX
Cycle N
Cycle (N + 1)
Cycle (N + 2)
Figure 7-13. Starting a Conversion and Reading Data in Manual Mode
7.4.3 On-the-Fly Mode
In the on-the-fly mode of operation, as shown in Figure 7-14, the analog input channel is selected using the first
five bits on SDI without waiting for the CS rising edge. Thus, the ADC samples the newly selected channel on
the CS rising edge and there is no latency between the channel selection and the ADC output data. Table 7-8
lists the channel selection commands for this mode.
Sample
AINx
Sample
AINx
Sample
AINy
Sample
AINz
tCONV
tCYCLE
CS
SCLK
SDI
2
2
1
24
1
3
4
5
16
1
3
4
5
16
5 clocks
SEQ_MODE =
10b
4-bit AINy ID
1
4-bit AINz ID
1
16 clocks
Data AINx
16 clocks
SDO
Data AINx
24 clocks
Data AINy
MUX OUT = AINz
MUX OUT = AINx
100-ns
MUX OUT = AINx
MUX OUT = AINy
MUX
No Cycle Latency
Figure 7-14. Starting a Conversion and Reading data in On-the-Fly Mode
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Table 7-8. On-the-Fly Mode Channel Selection Commands
SDI BITS[15:11]
1 0000
SDI BITS [10:0]
Don't care
Don't care
Don't care
Don't care
Don't care
Don't care
Don't care
Don't care
Don't care
DESCRIPTION
Select analog input 0
Select analog input 1
Select analog input 2
Select analog input 3
Select analog input 4
Select analog input 5
Select analog input 6
Select analog input 7
Reserved
1 0001
1 0010
1 0011
1 0100
1 0101
1 0110
1 0111
1 1000 to 1 1111
The number of clocks required for reading the output data depends on the device output data frame size; see the
Output Data Format section for more details.
7.4.4 Auto-Sequence Mode
In auto-sequence mode, the internal channel sequencer switches the multiplexer to the next analog input
channel after every conversion. The desired analog input channels can be configured for sequencing in the
AUTO_SEQ_CHSEL register. To enable the channel sequencer, set SEQ_START = 1b. After every conversion,
the channel sequencer switches the multiplexer to the next analog input in ascending order. To stop the channel
sequencer from selecting channels, set SEQ_START = 0b.
In the example shown in Figure 7-15, AIN2 and AIN6 are enabled for sequencing in the AUTO_SEQ_CHSEL
register. The channel sequencer loops through AIN2 and AIN6 and repeats until SEQ_START is set to 0b. The
number of clocks required for reading the output data depends on the device output data frame size; see the
Output Data Format section for more details.
Sample
AINx
Sample
AIN2
Sample
AIN6
Sample
AIN2
Sample
AIN6
tCYCLE
CS
SCLK
SDI
SEQ_START
SDO
Data AIN6
Data AIN2
Data AINx
24 clocks
Data AINx
Data AIN2
12 clocks
MUX OUT = AIN2
MUX OUT = AIN6
MUX OUT = AIN2
MUX OUT = AIN6
MUX OUT = AINx
MUX
Scan channels AIN2 and AIN6 and repeat
Figure 7-15. Starting Conversion and Reading Data in Auto-Sequence Mode
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7.5 ADS7067 Registers
Table 7-9 lists the ADS7067 registers. All register offset addresses not listed in Table 7-9 should be considered
as reserved locations and the register contents should not be modified.
Table 7-9. ADS7067 Registers
Address Acronym
Register
Name
Section
0x0
0x1
SYSTEM_STATUS
Section 7.5.1
Section 7.5.2
Section 7.5.3
Section 7.5.4
Section 7.5.5
Section 7.5.6
Section 7.5.7
Section 7.5.8
Section 7.5.9
Section 7.5.10
Section 7.5.11
Section 7.5.12
Section 7.5.13
Section 7.5.14
Section 7.5.15
Section 7.5.16
Section 7.5.17
GENERAL_CFG
DATA_CFG
0x2
0x3
OSR_CFG
0x4
OPMODE_CFG
PIN_CFG
0x5
0x7
GPIO_CFG
0x9
GPO_DRIVE_CFG
GPO_OUTPUT_VALUE
GPI_VALUE
0xB
0xD
0x10
0x11
0x12
0xBF
0xC0
0xC1
0xC2
SEQUENCE_CFG
CHANNEL_SEL
AUTO_SEQ_CH_SEL
DIAGNOSTICS_KEY
DIAGNOSTICS_EN
BIT_SAMPLE_LSB
BIT_SAMPLE_MSB
Complex bit access types are encoded to fit into small table cells. Table 7-10 shows the codes that are used for
access types in this section.
Table 7-10. ADS7067 Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
- n
Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n
When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups
form a hierarchical structure and
the array is represented with a
formula.
y
When this variable is used in a
register name, an offset, or an
address it refers to the value of
a register array.
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7.5.1 SYSTEM_STATUS Register (Address = 0x0) [reset = 0x81]
SYSTEM_STATUS is shown in Figure 7-14 and described in Table 7-11.
Return to the Table 7-9.
Figure 7-14. SYSTEM_STATUS Register
7
6
5
4
3
2
1
0
RSVD
SEQ_STATUS
RESERVED
CRCERR_FUS CRCERR_IN
E
BOR
R-1b
R-0b
R-0b
R-0b
R/W-0b
R/W-1b
Table 7-11. SYSTEM_STATUS Register Field Descriptions
Bit
7
Field
Type
Reset
Description
RSVD
R
1b
Reads return 1b.
6
SEQ_STATUS
R
0b
Status of the channel sequencer.
0b = Sequence stopped
1b = Sequence in progress
5-3
2
RESERVED
R
R
0b
0b
Reserved Bit
CRCERR_FUSE
Device power-up configuration CRC check status. To re-evaluate this
bit, software reset the device or power cycle AVDD.
0b = No problems detected in power-up configuration.
1b = Device configuration not loaded correctly.
1
0
CRCERR_IN
BOR
R/W
R/W
0b
1b
Status of CRC check on incoming data. Write 1b to clear this error
flag.
0b = No CRC error.
1b = CRC error detected. All register writes, except to addresses
0x00 and 0x01, are blocked.
Brown out reset indicator. This bit is set if brown out condition occurs
or device is power cycled. Write 1b to this bit to clear the flag.
0b = No brown out since last time this bit was cleared.
1b = Brown out condition detected or device power cycled.
7.5.2 GENERAL_CFG Register (Address = 0x1) [reset = 0x0]
GENERAL_CFG is shown in Figure 7-15 and described in Table 7-12.
Return to the Table 7-9.
Figure 7-15. GENERAL_CFG Register
7
6
5
4
3
2
1
0
REF_EN
R/W-0b
CRC_EN
R/W-0b
RESERVED
R-0b
RANGE
R/W-0b
CH_RST
R/W-0b
CAL
RST
W-0b
R/W-0b
Table 7-12. GENERAL_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
REF_EN
R/W
0b
Enable or disable the internal reference.
0b = Internal reference is powered down.
1b = Internal reference is enabled.
6
CRC_EN
R/W
0b
Enable or disable the CRC on device interface.
0b = CRC module disabled.
1b = CRC appended to data output. CRC check is enabled on
incoming data.
5-4
3
RESERVED
RANGE
R
0b
0b
Reserved Bit
R/W
Select the input range of the ADC.
0b = Input range of the ADC is 1x VREF
1b = Input range of the ADC is 2x VREF
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Table 7-12. GENERAL_CFG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2
CH_RST
R/W
0b
Force all channels to be analog inputs.
0b = Normal operation
1b = All channels will be set as analog inputs irrespective of
configuration in other registers
1
0
CAL
RST
R/W
W
0b
0b
Calibrate ADC offset.
0b = Normal operation.
1b = ADC offset is calibrated. After calibration is complete, this bit is
set to 0b.
Software reset all registers to default values.
0b = Normal operation.
1b = Device is reset. After reset is complete, this bit is set to 0b and
BOR bit is set to 1b.
7.5.3 DATA_CFG Register (Address = 0x2) [reset = 0x0]
DATA_CFG is shown in Figure 7-16 and described in Table 7-13.
Return to the Table 7-9.
Figure 7-16. DATA_CFG Register
7
6
5
4
3
2
1
0
FIX_PAT
R/W-0b
RESERVED
R-0b
APPEND_STATUS[1:0]
R/W-0b
RESERVED
R-0b
CPOL_CPHA[1:0]
R/W-0b
Table 7-13. DATA_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
FIX_PAT
R/W
0b
Device outputs fixed data bits which can be helpful for debugging
communication with the device.
0b = Normal operation.
1b = Device outputs fixed code 0xA5A5 repeatitively when reading
ADC data.
6
RESERVED
R
0b
0b
Reserved Bit
5-4
APPEND_STATUS[1:0]
R/W
Append 4-bit channel ID or status flags to output data.
0b = Channel ID and status flags are not appended to ADC data.
1b = 4-bit channel ID is appended to ADC data.
10b = 4-bit status flags are appended to ADC data.
11b = Reserved.
3-2
1-0
RESERVED
R
0b
0b
Reserved Bit
CPOL_CPHA[1:0]
R/W
This field sets the polarity and phase of SPI communication.
0b = CPOL = 0, CPHA = 0.
1b = CPOL = 0, CPHA = 1.
10b = CPOL = 1, CPHA = 0.
11b = CPOL = 1, CPHA = 1.
7.5.4 OSR_CFG Register (Address = 0x3) [reset = 0x0]
OSR_CFG is shown in Figure 7-17 and described in Table 7-14.
Return to the Table 7-9.
Figure 7-17. OSR_CFG Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
OSR[2:0]
R/W-0b
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Table 7-14. OSR_CFG Register Field Descriptions
Bit
7-3
2-0
Field
Type
Reset
Description
RESERVED
OSR[2:0]
R
0b
Reserved Bit
R/W
0b
Selects the oversampling ratio for ADC conversion result.
0b = No averaging
1b = 2 samples
10b = 4 samples
11b = 8 samples
100b = 16 samples
101b = 32 samples
110b = 64 samples
111b = 128 samples
7.5.5 OPMODE_CFG Register (Address = 0x4) [reset = 0x1]
OPMODE_CFG is shown in Figure 7-18 and described in Table 7-15.
Return to the Table 7-9.
Figure 7-18. OPMODE_CFG Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
OSC_SEL
R/W-0b
CLK_DIV[3:0]
R/W-1b
Table 7-15. OPMODE_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
4
RESERVED
OSC_SEL
R
0b
Reserved Bit
R/W
0b
Selects the oscillator for internal timing generation.
0b = High-speed oscillator.
1b = Low-power oscillator.
3-0
CLK_DIV[3:0]
R/W
1b
Sampling speed control when using averaging filters. Refer to
section on oscillator and timing control for details.
7.5.6 PIN_CFG Register (Address = 0x5) [reset = 0x0]
PIN_CFG is shown in Figure 7-19 and described in Table 7-16.
Return to the Table 7-9.
Figure 7-19. PIN_CFG Register
7
6
5
4
3
2
1
0
PIN_CFG[7:0]
R/W-0b
Table 7-16. PIN_CFG Register Field Descriptions
Bit
7-0
Field
PIN_CFG[7:0]
Type
Reset
Description
R/W
0b
Configure device channels AIN/GPIO [7:0] as analog inputs or
GPIOs.
0b = Channel is configured as analog input.
1b = Channel is configured as GPIO.
7.5.7 GPIO_CFG Register (Address = 0x7) [reset = 0x0]
GPIO_CFG is shown in Figure 7-20 and described in Table 7-17.
Return to the Table 7-9.
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Figure 7-20. GPIO_CFG Register
7
6
5
4
3
2
1
0
GPIO_CFG[7:0]
R/W-0b
Table 7-17. GPIO_CFG Register Field Descriptions
Bit
Field
GPIO_CFG[7:0]
Type
Reset
Description
7-0
R/W
0b
Configure GPIO[7:0] as either digital inputs or digital outputs.
0b = GPIO is configured as digital input.
1b = GPIO is configured as digital output.
7.5.8 GPO_DRIVE_CFG Register (Address = 0x9) [reset = 0x0]
GPO_DRIVE_CFG is shown in Figure 7-21 and described in Table 7-18.
Return to the Table 7-9.
Figure 7-21. GPO_DRIVE_CFG Register
7
6
5
4
3
2
1
0
GPO_DRIVE_CFG[7:0]
R/W-0b
Table 7-18. GPO_DRIVE_CFG Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
GPO_DRIVE_CFG[7:0]
R/W
0b
Configure digital outputs GPO[7:0] as open-drain or push-pull
outputs.
0b = Digital output is open-drain; connect external pullup resistor.
1b = Push-pull driver is used for digital output.
7.5.9 GPO_OUTPUT_VALUE Register (Address = 0xB) [reset = 0x0]
GPO_OUTPUT_VALUE is shown in Figure 7-22 and described in Table 7-19.
Return to the Table 7-9.
Figure 7-22. GPO_OUTPUT_VALUE Register
7
6
5
4
3
2
1
0
GPO_OUTPUT_VALUE[7:0]
R/W-0b
Table 7-19. GPO_OUTPUT_VALUE Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
GPO_OUTPUT_VALUE[7: R/W
0]
0b
Logic level to be set on digital outputs GPO[7:0].
0b = Digital output set to logic 0.
1b = Digital output set to logic 1.
7.5.10 GPI_VALUE Register (Address = 0xD) [reset = 0x0]
GPI_VALUE is shown in Figure 7-23 and described in Table 7-20.
Return to the Table 7-9.
Figure 7-23. GPI_VALUE Register
7
6
5
4
3
2
1
0
GPI_VALUE[7:0]
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Figure 7-23. GPI_VALUE Register (continued)
R-0b
Table 7-20. GPI_VALUE Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GPI_VALUE[7:0]
R
0b
Readback the logic level on GPIO[7:0].
0b = GPIO is at logic 0.
1b = GPIO is at logic 1.
7.5.11 SEQUENCE_CFG Register (Address = 0x10) [reset = 0x0]
SEQUENCE_CFG is shown in Figure 7-24 and described in Table 7-21.
Return to the Table 7-9.
Figure 7-24. SEQUENCE_CFG Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
SEQ_START
R/W-0b
RESERVED
R-0b
SEQ_MODE[1:0]
R/W-0b
Table 7-21. SEQUENCE_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
4
RESERVED
SEQ_START
R
0b
Reserved Bit
R/W
0b
Control for start of channel sequence when using auto sequence
mode (SEQ_MODE = 01b).
0b = Stop channel sequencing.
1b = Start channel sequencing in ascending order for channels
enabled in AUTO_SEQ_CH_SEL register.
3-2
1-0
RESERVED
R
0b
0b
Reserved Bit
SEQ_MODE[1:0]
R/W
Selects the mode of scanning of analog input channels.
0b = Manual sequence mode; channel selected by MANUAL_CHID
field.
1b = Auto sequence mode; channel selected by
AUTO_SEQ_CHSEL.
10b = On-the-fly sequence mode.
11b = Reserved.
7.5.12 CHANNEL_SEL Register (Address = 0x11) [reset = 0x0]
CHANNEL_SEL is shown in Figure 7-25 and described in Table 7-22.
Return to the Table 7-9.
Figure 7-25. CHANNEL_SEL Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
MANUAL_CHID[3:0]
R/W-0b
Table 7-22. CHANNEL_SEL Register Field Descriptions
Bit
7-4
Field
RESERVED
Type
Reset
Description
R
0b
Reserved Bit
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Table 7-22. CHANNEL_SEL Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3-0
MANUAL_CHID[3:0]
R/W
0b
In manual mode (SEQ_MODE = 00b), this field contains the 4-bit
channel ID of the analog input channel for next ADC conversion.
For valid ADC data, the selected channel must not be configured as
GPIO in PIN_CFG register. 1xxx = Reserved.
0b = AIN0
1b = AIN1
10b = AIN2
11b = AIN3
100b = AIN4
101b = AIN5
110b = AIN6
111b = AIN7
1000b = Reserved.
7.5.13 AUTO_SEQ_CH_SEL Register (Address = 0x12) [reset = 0x0]
AUTO_SEQ_CH_SEL is shown in Figure 7-26 and described in Table 7-23.
Return to the Table 7-9.
Figure 7-26. AUTO_SEQ_CH_SEL Register
7
6
5
4
3
2
1
0
AUTO_SEQ_CH_SEL[7:0]
R/W-0b
Table 7-23. AUTO_SEQ_CH_SEL Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
AUTO_SEQ_CH_SEL[7:0] R/W
0b
Select analog input channels AIN[7:0] in for auto sequencing mode.
0b = Analog input channel is not enabled in scanning sequence.
1b = Analog input channel is enabled in scanning sequence.
7.5.14 DIAGNOSTICS_KEY Register (Address = 0xBF) [reset = 0x0]
DIAGNOSTICS_KEY is shown in Figure 7-27 and described in Table 7-24.
Return to the Table 7-9.
Figure 7-27. DIAGNOSTICS_KEY Register
7
6
5
4
3
2
1
0
DIAG_KEY[7:0]
R/W-0b
Table 7-24. DIAGNOSTICS_KEY Register Field Descriptions
Bit
7-0
Field
DIAG_KEY[7:0]
Type
Reset
Description
R/W
0b
Enable write access to diagnostics registers in address locations
0xC0, 0xC1, and 0xC2. Write 0x96 to this register to enable write
access to diagnostics registers.
7.5.15 DIAGNOSTICS_EN Register (Address = 0xC0) [reset = 0x0]
DIAGNOSTICS_EN is shown in Figure 7-28 and described in Table 7-25.
Return to the Table 7-9.
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Figure 7-28. DIAGNOSTICS_EN Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
VTEST_EN
R/W-0b
RESERVED
R-0b
BITWALK_EN
R/W-0b
Table 7-25. DIAGNOSTICS_EN Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
4
RESERVED
VTEST_EN
R
0b
Reserved Bit
R/W
0b
Enable measurement of internal 1.8 V (typical) test voltage using
AIN6. When using this mode, AIN6 pin should not be left floating and
should not be connected to any external circuit. If BITWALK_EN =
1b, this bit has no effect.
0b = Normal operation.
1b = AIN6 is internally connected to 1.8V (typical) test voltage. AIN6
pin should be floating and should not be connected to any external
circuit.
3-1
0
RESERVED
R
0b
0b
Reserved Bit
BITWALK_EN
R/W
Enable bit-walk mode of the ADC bit decisions.
0b = Normal operation.
1b = Bit walk mode enabled.
7.5.16 BIT_SAMPLE_LSB Register (Address = 0xC1) [reset = 0x0]
BIT_SAMPLE_LSB is shown in Figure 7-29 and described in Table 7-26.
Return to the Table 7-9.
Figure 7-29. BIT_SAMPLE_LSB Register
7
6
5
4
3
2
1
0
BIT_SAMPLE_LSB[7:0]
R/W-0b
Table 7-26. BIT_SAMPLE_LSB Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
BIT_SAMPLE_LSB[7:0]
R/W
0b
Define the [7:0] bit positions during sampling phase of the ADC. This
field has no effet when DIAG_EN = 0.
7.5.17 BIT_SAMPLE_MSB Register (Address = 0xC2) [reset = 0x0]
BIT_SAMPLE_MSB is shown in Figure 7-30 and described in Table 7-27.
Return to the Table 7-9.
Figure 7-30. BIT_SAMPLE_MSB Register
7
6
5
4
3
2
1
0
BIT_SAMPLE_MSB[7:0]
R/W-0b
Table 7-27. BIT_SAMPLE_MSB Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
BIT_SAMPLE_MSB[7:0]
R/W
0b
Define the [15:8] bit positions during sampling phase of the ADC.
This field has no effet when DIAG_EN = 0.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The primary circuit required to maximize the performance of a high-precision, successive approximation register
(SAR), analog-to-digital converter (ADC) is the input driver circuits. This section details some general principles
for designing the input driver circuit for the ADS7067.
8.2 Typical Application
AVDD
AVDD
ADS7067
107 ꢀ
+
150 ꢀ
680 pF
MUX
30 pF
OPA325
Charge-Kickback Filter
Figure 8-1. DAQ Circuit: Single-Supply DAQ
8.2.1 Design Requirements
The goal of this application is to design a single-supply digital acquisition (DAQ) circuit based on the ADS7067
with SNR greater than 80 dB and THD less than –80 dB for input frequencies of 2 kHz at full throughput.
8.2.2 Detailed Design Procedure
The optimal input driver circuit for a high-precision SAR ADC consists of a driving amplifier and a charge-
kickback filter (RC filter). The amplifier driving the ADC must have low output impedance and be able to charge
the internal sampling capacitor to a 16-bit settling level within the minimum acquisition time. The charge-kickback
filter helps attenuate the sampling charge injection from the switched-capacitor input stage of the ADC and helps
reduce the wide-band noise contributed by the front-end circuit.
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8.2.2.1 Charge-Kickback Filter and ADC Amplifier
As illustrated in Figure 8-1, a filter capacitor (CFLT) is connected from each input pin of the ADC to ground.
This capacitor helps reduce the sampling charge injection and provides a charge bucket to quickly charge the
internal sample-and-hold capacitors during the acquisition process. This capacitor must be a COG- or NPO-type.
One method for determining the required amplifier bandwidth and the values of the RC charge-kickback filter
is provided in this section. This optimization and more details on the math behind the component selection are
covered in ADC Precision Labs.
The minimum bandwidth of the amplifier for driving the ADC can be computed using the settling accuracy
(0.5 LSB) and settling time (acquisition time) information. Equation 4, Equation 5, Equation 6, and Equation 7
compute the unity-gain bandwidth (UGBW) of the amplifier.
84'( 2.5 8
=
.5$ =
= 38.2 ä8
20
216
(4)
FP#%3
F800 JO
ì? =
=
= 93.4 JO
0.5 ® .5$
100 I8
0.5 ® (38.2 ä8)
100 I8
ln @
A
ln l
p
(5)
(6)
(7)
ì?
93.4 JO
ìK=
=
=
= 22.7 JO
17
17
¾
¾
1
1
7)$9 =
=
= 7 /*V
2 ® è ® ìK= 2 ® è ® (22.7 JO)
Based on the result of Equation 7, select an amplifier that has more than 7-MHz UGBW. For this example,
OPA325 is used.
The value of Cfilt is computed in Equation 8 by taking 20 times the internal sample-and-hold capacitance.
The factor of 20 is a rule of thumb that is intended to minimize the droop in voltage on the charge-bucket
capacitor, Cfilt, after the start of the acquisition period. The filter resistor, Rfilt, is computed in Equation 9 using the
op-amp time constant and Cfilt. Equation 10 and Equation 11 compute the minimum and maximum Rfilt values,
respectively.
: ;
= 20 ® %5* = 20 ® 30L( = 600 L(
%
BEHP
(8)
The value of Cfllt can be approximated to the nearest standard value 680 pF.
4 × ìK= 4 × (22.7 JO)
=
BEHP
4BEHP
=
= 133.5 À
%
680 L(
(9)
(10)
(11)
4BEHP /EJ = 0.25 × 4BEHP = 0.25 × (133.5 À) = 33.4 À
4BEHP /=T = 2 × 4BEHP = 2 × (133.5 À) = 267 À
Copyright © 2021 Texas Instruments Incorporated
36
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ADS7067
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SBASA78A – MARCH 2021 – REVISED OCTOBER 2021
8.2.3 Application Curve
Figure 8-2 shows the FFT plot for the ADS7067 with a 2-kHz input frequency used for the circuit in Figure 8-1.
0
-40
-80
-120
-160
0
80000
160000
240000
320000
400000
Frequency (Hz)
C008
fIN = 2 kHz, SNR = 85.3 dBFS, THD = –97 dB
Figure 8-2. Test Results for the Single-Supply DAQ Circuit
9 Power Supply Recommendations
9.1 AVDD and DVDD Supply Recommendations
The ADS7067 has two separate power supplies: AVDD and DVDD. The device operates on AVDD; DVDD is
used for the interface circuits. AVDD and DVDD can be independently set to any value within the permissible
ranges. As shown in Figure 9-1, decouple the AVDD and DVDD pins individually with 1-µF ceramic decoupling
capacitors.
AVDD
AVDD
1 mF
GND
GND
1 mF
DVDD
DVDD
Figure 9-1. Power-Supply Decoupling
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SBASA78A – MARCH 2021 – REVISED OCTOBER 2021
10 Layout
10.1 Layout Guidelines
Figure 10-1 shows a board layout example for the ADS7067. Avoid crossing digital lines with the analog signal
path and keep the analog input signals and the reference input signals away from noise sources.
Use 1-µF ceramic bypass capacitors in close proximity to the analog (AVDD) and digital (DVDD) power-supply
pins. Avoid placing vias between the AVDD and DVDD pins and the bypass capacitors. Connect all ground pins
to the ground plane using short, low-impedance paths.
Place the reference decoupling capacitor (CREF) close to the device REF and GND pins. Avoid placing vias
between the REF pin and the bypass capacitors.
The charge-kickback RC filters are placed close to the device. Among ceramic surface-mount capacitors, COG-
or NPO-type ceramic capacitors provide the best capacitance precision. The type of dielectric used in COG-
or NPO-type ceramic capacitors provides the most stable electrical properties over voltage, frequency, and
temperature changes.
10.2 Layout Example
7.2 mm
REF
SPI
INTERFACE
5.5 mm
AVDD
DVDD
ANALOG INPUTS
Figure 10-1. Example Layout
Copyright © 2021 Texas Instruments Incorporated
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ADS7067
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SBASA78A – MARCH 2021 – REVISED OCTOBER 2021
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
Texas Instruments, ADC Precision Labs
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
•
•
Texas Instruments, REF60xx High-Precision Voltage Reference With Integrated ADC Drive Buffer data sheet
Texas Instruments, OPAx325 Precision, 10-MHz, Low-Noise, Low-Power, RRIO, CMOS Operational
Amplifiers data sheet
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: ADS7067
PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS7067IYBHR
ADS7067IYBHT
XADS7067IYBHR
ACTIVE
ACTIVE
ACTIVE
DSBGA
DSBGA
DSBGA
YBH
YBH
YBH
16
16
16
3000 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Call TI
-40 to 125
-40 to 125
-40 to 125
ADS7067
ADS7067
250
RoHS & Green
TBD
SNAGCU
Call TI
3000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS7067IYBHR
ADS7067IYBHT
DSBGA
DSBGA
YBH
YBH
16
16
3000
250
180.0
180.0
8.4
8.4
1.8
1.8
1.8
1.8
0.52
0.52
4.0
4.0
8.0
8.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS7067IYBHR
ADS7067IYBHT
DSBGA
DSBGA
YBH
YBH
16
16
3000
250
182.0
182.0
182.0
182.0
20.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
YBH0016
DSBGA - 0.4 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
A
B
E
BALL A1
CORNER
D
C
0.4 MAX
SEATING PLANE
0.05 C
BALL TYP
0.16
0.10
1.2 TYP
SYMM
D
C
1.2
TYP
SYMM
D: Max = 1.651 mm, Min = 1.59 mm
E: Max = 1.651 mm, Min = 1.59 mm
B
A
0.4
TYP
2
1
3
4
0.225
0.185
16X
0.015
0.4 TYP
C A B
4225022/A 06/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YBH0016
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
3
16X ( 0.2)
2
1
4
A
(0.4) TYP
B
C
SYMM
D
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 40X
0.05 MIN
0.05 MAX
METAL UNDER
SOLDER MASK
(
0.2)
METAL
(
0.2)
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225022/A 06/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YBH0016
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
3
(R0.05) TYP
4
16X ( 0.21)
1
2
A
(0.4) TYP
B
C
SYMM
METAL
TYP
D
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.075 mm THICK STENCIL
SCALE: 40X
4225022/A 06/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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