ADS7250IRTET [TI]
SAR ADC、双路、750 kSPS、12 位、同步采样 | RTE | 16 | -40 to 125;
| 型号： | ADS7250IRTET |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SAR ADC、双路、750 kSPS、12 位、同步采样 | RTE | 16 | -40 to 125 |
| 文件： | 总44页 (文件大小：3504K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADS8350, ADS7850, ADS7250
ZHCSCC6D –MAY 2013–REVISED MARCH 2018
ADSxx50 双路，750kSPS，16，14 和 12 位，同步采样，
模数转换器
1 特性
3 说明
1
•
16、14 和 12 位引脚兼容系列
两个通道同时采样
ADS8350、ADS7850 和 ADS7250 器件属于引脚兼容
型双路高速同步采样模数转换器 (ADC) 产品系列，它
们均支持伪差动模拟输入。所有器件支持一个由宽电源
电压范围供电运行的简单串行接口，从而实现与多种主
机控制器的轻松通信。
•
•
•
•
伪差分模拟输入
快速数据吞吐量：750kSPS
出色的直流性能：
–
线性：
所有器件的额定扩展工业范围均为 –40°C 至 125°C，
并且采用引脚兼容 WQFN-16 (3mm × 3mm) 封装。
–
ADS8350：
16 位丢码率 (NMC) 差分非线性
(DNL)，±2.5 最低有效位 (LSB)，最大积分
非线性 (INL)
器件信息(1)
器件型号
ADS7250
封装
封装尺寸（标称值）
–
–
ADS7850：
14 位 NMC DNL，±1.5 LSB，最大 INL
ADS7850
ADS8350
WQFN (16)
3.00mm x 3.00mm
ADS7250：
12 位 NMC DNL，±1 LSB，最大 INL
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
•
出色的交流性能：
–
ADS8350：85dB 信噪比 (SNR)，-96dB 总谐波
失真 (THD)
–
–
ADS7850: 81dB SNR，-90dB THD
ADS7250：73dB SNR，-88dB THD
功能方框图
ADS7250,
ADS7850,
ADS8350
•
•
简单串行接口
OPA322
在 -40°C 至 + 125°C 的扩展工业用温度范围内完全
额定运行
-
OPA322
AINP
-
+
+
+
+
+V
•
小型封装：超薄四方扁平无引线 (WQFN)-16 (3mm
+V
x 3mm)
AINM
2 应用范围
VREF
•
电机控制：
使用 SinCos 编码器进行位置测量
•
光网络互连：
掺铒光纤放大器 (EDFA) 增益控制环路
AINM
OPA322
+
•
•
•
•
•
保护中继器
OPA322
+
+
-
AINP
电源质量测量
三相电源控制
可编程逻辑控制器
工业自动化
+
-
+V
+V
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBAS580
ADS8350, ADS7850, ADS7250
ZHCSCC6D –MAY 2013–REVISED MARCH 2018
www.ti.com.cn
目录
7.1 Overview ................................................................. 20
7.2 Functional Block Diagram ....................................... 20
7.3 Feature Description................................................. 21
7.4 Device Functional Modes........................................ 24
Application and Implementation ........................ 26
8.1 Application Information............................................ 26
8.2 Typical Applications ................................................ 26
Power Supply Recommendations...................... 33
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics: All Devices....................... 5
6.6 Electrical Characteristics: ADS7250 ......................... 6
6.7 Electrical Characteristics: ADS7850 ......................... 7
6.8 Electrical Characteristics: ADS8350 ......................... 8
6.9 Timing Requirements................................................ 9
6.10 Switching Characteristics........................................ 9
6.11 Typical Characteristics: ADS7250 ........................ 10
6.12 Typical Characteristics: ADS7850 ........................ 13
6.13 Typical Characteristics: ADS8350 ........................ 16
6.14 Typical Characteristics: All Devices...................... 19
Detailed Description ............................................ 20
8
9
10 Layout................................................................... 34
10.1 Layout Guidelines ................................................. 34
10.2 Layout Example .................................................... 34
11 器件和文档支持 ..................................................... 35
11.1 文档支持................................................................ 35
11.2 相关链接................................................................ 35
11.3 接收文档更新通知 ................................................. 35
11.4 社区资源................................................................ 35
11.5 商标....................................................................... 35
11.6 静电放电警告......................................................... 35
11.7 Glossary................................................................ 35
12 机械、封装和可订购信息....................................... 35
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision C (June 2014) to Revision D
Page
•
Changed ESD Ratings title, updated to current format, moved Storage temperature parameter to Absolute
Maximum Ratings table .......................................................................................................................................................... 4
•
•
•
Changed Timing Characteristics table: split table into Timing Requirements and Switching Characteristics ....................... 9
Deleted tSU_DOCK and tHT_CKDO parameters, replaced with tD_CKDO parameter ........................................................................ 9
Changed Timing Diagram figure............................................................................................................................................. 9
Changes from Revision B (April 2014) to Revision C
Page
•
•
•
已将器件信息表更改为最新标准 ............................................................................................................................................ 1
已更正功能方框图中的伪差分输入和参考连接........................................................................................................................ 1
Changed Handling Ratings table to current standards ......................................................................................................... 4
Changes from Revision A (January 2014) to Revision B
Page
•
•
更改了格式，以符合最新数据表标准；添加了布局 部分，移动了现有部分............................................................................ 1
Deleted Ordering Information section .................................................................................................................................... 3
Changes from Original (May 2013) to Revision A
Page
•
已发布至生产 .......................................................................................................................................................................... 1
2
Copyright © 2013–2018, Texas Instruments Incorporated
ADS8350, ADS7850, ADS7250
www.ti.com.cn
ZHCSCC6D –MAY 2013–REVISED MARCH 2018
5 Pin Configuration and Functions
RTE Package
16-Pin WQFN
Top View
REFIN-A
REFGND-A
REFGND-B
REFIN-B
1
2
3
4
12 SDO-B
11
10
9
SDO-A
SCLK
CS
Thermal
Pad
Pin Functions
PIN
NAME
NO.
16
5
I/O
DESCRIPTION
AINM-A
AINM-B
AINP-A
AINP-B
AVDD
Analog input
Analog input
Analog input
Analog input
Supply
Negative analog input, ADC_A
Negative analog input, ADC_B
Positive analog input, ADC_A
Positive analog input, ADC_B
ADC supply voltage
15
6
14
9
CS
Digital input
Supply
Chip-select signal; active low
Digital I/O supply
DVDD
7
GND
8, 13
2
Supply
Device ground
REFGND-A
REFGND-B
REFIN-A
REFIN-B
SCLK
Supply
Reference ground potential, ADC_A
Reference ground potential, ADC_B
Reference voltage input, ADC_A
Reference voltage input, ADC_B
Serial communication clock
3
Supply
1
Analog input
Analog input
Digital input
Digital output
Digital output
4
10
11
12
SDO-A
SDO-B
Data output for serial communication, ADC_A
Data output for serial communication, ADC_B
Exposed thermal pad. TI recommends connecting the thermal pad to the printed
circuit board (PCB) ground.
Thermal pad
Supply
Copyright © 2013–2018, Texas Instruments Incorporated
3
ADS8350, ADS7850, ADS7250
ZHCSCC6D –MAY 2013–REVISED MARCH 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
MAX
UNIT
AVDD to GND
Supply voltage
7
7
V
DVDD to GND
–0.3
AINP_x to REFGND_x
REFGND_x – 0.3
REFGND_x – 0.3
REFGND_x – 0.3
GND – 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
DVDD + 0.3
0.3
Analog input voltage
AINM_x to REFGND_x
REFIN_x to REFGND_x
CS, SCLK to GND
V
Digital input voltage
Ground voltage difference
Input current
V
V
| REFGND_x – GND |
Any pin except supply pins
±10
mA
°C
°C
Maximum virtual junction temperature, TJ
Storage temperature, Tstg
150
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
5
MAX
UNIT
AVDD
DVDD
Analog power supply
Digital power supply
V
V
3.3
6.4 Thermal Information
ADS7250, ADS7850, ADS8350
THERMAL METRIC
RTE (WQFN)
16 PINS
33.3
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJCtop
RθJB
29.5
7.3
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
7.4
RθJCbot
0.9
4
Copyright © 2013–2018, Texas Instruments Incorporated
ADS8350, ADS7850, ADS7250
www.ti.com.cn
ZHCSCC6D –MAY 2013–REVISED MARCH 2018
6.5 Electrical Characteristics: All Devices
minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 5 V, VREFIN_A = VREFIN_B = VREF, and tDATA
750 kSPS (unless otherwise noted); typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V
=
PARAMETER
ANALOG INPUT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(1)
Full-scale input range,
(AINP_x – AINM_x)
AVDD ≥ 2 x VREF
AINM_x = VREF
,
FSR
VINP
VINM
–VREF
0
VREF
2 × VREF
V
V
V
(1)
Absolute input voltage,
(AINP_x to REFGND)
AVDD ≥ 2 x VREF
AINM_x = VREF
,
Absolute input voltage,
(AINM_x to REFGND)
VREF – 0.1
VREF
VREF + 0.1
In sample mode
In hold mode
40
4
CIN
IIN
Input capacitance
pF
nA
Input leakage current
1.5
SAMPLING DYNAMICS
fDATA
tA
Data rate
750
kSPS
ns
Aperture delay
tA match
8
40
10
ADC_A to ADC_B
ps
Aperture jitter
Clock frequency
ps
fCLK
24
AVDD / 2(1)
1
MHz
VOLTAGE REFERENCE INPUT
VREF
IREF
Reference input voltage
Reference input current
Reference leakage current
2.25
2.5
V
300
µA
µA
External ceramic reference
capacitance
CREF
10
µF
DIGITAL INPUTS(2)
VIH
Input voltage, high
0.7 DVDD
–0.3
DVDD + 0.3
0.3 DVDD
V
V
VIL
Input voltage, low
DIGITAL OUTPUTS(2)
VOH
VOL
Output voltage, high
Output voltage, low
IOH = 500-µA source
IOH = 500-µA sink
0.8 DVDD
0
DVDD
V
V
0.2 DVDD
POWER SUPPLY
Analog supply voltage,
AVDD to GND
AVDD
DVDD
IA-DYNA
IA-STAT
4.5(1)
1.65
5.0
5.5
5.5
9
V
V
Digital supply voltage,
DVDD to GND
Analog supply current,
during conversion
AVDD = 5 V, throughput = max
AVDD = 5 V, static
8
5
mA
Analog supply current,
no conversion
7
mA
mA
IDVDD
Digital supply current
DVDD = 3.3 V
0.25
40
PD-DYNA
PD-STAT
AVDD = 5 V, throughput = max
AVDD = 5 V, static
45
35
Power dissipation
mW
25
(1) The AVDD supply voltage defines the permissible voltage swing on the analog input pins. To use the maximum dynamic range of the
analog input pins, VREFIN_x and AVDD must be in the respective permissible range with AVDD ≥ 2 x VREFIN_x
.
(2) Specified by design; not production tested.
Copyright © 2013–2018, Texas Instruments Incorporated
5
ADS8350, ADS7850, ADS7250
ZHCSCC6D –MAY 2013–REVISED MARCH 2018
www.ti.com.cn
6.6 Electrical Characteristics: ADS7250
minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 5 V, VREFIN_A = VREFIN_B = VREF, and tDATA
750 kSPS (unless otherwise noted); typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V
=
PARAMETER
RESOLUTION
Resolution
DC ACCURACY
TEST CONDITIONS
MIN
TYP
MAX
UNIT
12
Bits
INL
Integral nonlinearity
Differential nonlinearity
Input offset error
VOS match
–1
–0.99
–2
±0.5
±0.4
1
1
2
2
LSB
LSB
mV
DNL
VOS
±0.75
±0.75
1
ADC_A to ADC_B
–2
mV
dVOS/dT Input offset thermal drift
µV/°C
GERR
Gain error
Referenced to voltage at REFIN_x
ADC_A to ADC_B
–0.1%
–0.1%
±0.05%
±0.05%
1
0.1%
0.1%
GERR match
GERR/dT Gain error thermal drift
Referenced to voltage at REFIN_x
ppm/°C
dB
CMRR
Common-mode rejection ratio Both ADCs, dc to 20 kHz
74
AC ACCURACY
–0.5 dBFS at 20-kHz input
–0.5 dBFS at 100-kHz input
–0.5 dBFS at 250-kHz input
–0.5 dBFS at 20-kHz input
–0.5 dBFS at 100-kHz input
–0.5 dBFS at 250-kHz input
–0.5 dBFS at 20-kHz input
–0.5 dBFS at 100-kHz input
–0.5 dBFS at 250-kHz input
–0.5 dBFS at 20-kHz input
71.5
72
72.9
72.9
72.5
73
SINAD
SNR
Signal-to-noise + distortion
dB
dB
dB
dB
Signal-to-noise ratio
73
73
–90
–90
–82
90
THD
Total harmonic distortion
SFDR
Spurious-free dynamic range –0.5 dBFS at 100-kHz input
–0.5 dBFS at 250-kHz input
90
82
Isolation between ADC_A and
fIN = 15 kHz, fNOISE = 25 kHz
ADC_B
–85
dB
At –3 dB
Full-power bandwidth
25
5
BW(FP)
MHz
At –0.1 dB
6
Copyright © 2013–2018, Texas Instruments Incorporated
ADS8350, ADS7850, ADS7250
www.ti.com.cn
ZHCSCC6D –MAY 2013–REVISED MARCH 2018
6.7 Electrical Characteristics: ADS7850
minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 5 V, VREFIN_A = VREFIN_B = VREF, and tDATA
750 kSPS (unless otherwise noted); typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V
=
PARAMETER
RESOLUTION
Resolution
DC ACCURACY
TEST CONDITIONS
MIN
TYP
MAX
UNIT
14
Bits
INL
Integral nonlinearity
Differential nonlinearity
Input offset error
VOS match
–1.5
–0.99
–1
±0.8
±0.7
1.5
1
LSB
LSB
mV
DNL
VOS
±0.25
±0.25
1
1
ADC_A to ADC_B
–1
1
mV
dVOS/dT Input offset thermal drift
µV/°C
GERR
Gain error
Referenced to voltage at REFIN_x
ADC_A to ADC_B
–0.1%
–0.1%
±0.05%
±0.05%
1
0.1%
0.1%
GERR match
GERR/dT Gain error thermal drift
Referenced to voltage at REFIN_x
ppm/°C
dB
CMRR
Common-mode rejection ratio Both ADCs, dc to 20 kHz
74
AC ACCURACY
–0.5 dBFS at 20-kHz input
–0.5 dBFS at 100-kHz input
–0.5 dBFS at 250-kHz input
–0.5 dBFS at 20-kHz input
–0.5 dBFS at 100-kHz input
–0.5 dBFS at 250-kHz input
–0.5 dBFS at 20-kHz input
–0.5 dBFS at 100-kHz input
–0.5 dBFS at 250-kHz input
–0.5 dBFS at 20-kHz input
79
81
81
SINAD
SNR
Signal-to-noise + distortion
dB
dB
dB
dB
79.9
81.5
81.5
81
79.5
Signal-to-noise ratio
–90
–90
–86
90
THD
Total harmonic distortion
SFDR
Spurious-free dynamic range –0.5 dBFS at 100-kHz input
–0.5 dBFS at 250-kHz input
90
86
Isolation between ADC_A and
fIN = 15 kHz, fNOISE = 25 kHz
ADC_B
–90
dB
At –3 dB
Full-power bandwidth
25
5
BW(FP)
MHz
At –0.1 dB
Copyright © 2013–2018, Texas Instruments Incorporated
7
ADS8350, ADS7850, ADS7250
ZHCSCC6D –MAY 2013–REVISED MARCH 2018
www.ti.com.cn
6.8 Electrical Characteristics: ADS8350
minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 5 V, VREFIN_A = VREFIN_B = VREF, and tDATA
750 kSPS (unless otherwise noted); typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V
=
PARAMETER
RESOLUTION
Resolution
DC ACCURACY
TEST CONDITIONS
MIN
TYP
MAX
UNIT
16
Bits
INL
Integral nonlinearity
Differential nonlinearity
Input offset error
VOS match
–2.5
–0.99
–1
±1
±0.7
2.5
2
LSB
LSB
mV
DNL
VOS
±0.25
±0.25
1
1
ADC_A to ADC_B
–1
1
mV
dVOS/dT Input offset thermal drift
µV/°C
GERR
Gain error
Referenced to voltage at REFIN_x
ADC_A to ADC_B
–0.1%
–0.1%
±0.05%
±0.05%
1
0.1%
0.1%
GERR match
GERR/dT Gain error thermal drift
Referenced to voltage at REFIN_x
ppm/°C
dB
CMRR
Common-mode rejection ratio Both ADCs, dc to 20 kHz
74
AC ACCURACY
–0.5 dBFS at 20-kHz input
–0.5 dBFS at 100-kHz input
–0.5 dBFS at 250-kHz input
–0.5 dBFS at 20-kHz input
–0.5 dBFS at 100-kHz input
–0.5 dBFS at 250-kHz input
–0.5 dBFS at 20-kHz input
–0.5 dBFS at 100-kHz input
–0.5 dBFS at 250-kHz input
–0.5 dBFS at 20-kHz input
83.5
84
84.7
83.7
83
SINAD
SNR
Signal-to-noise + distortion
dB
dB
dB
dB
85
Signal-to-noise ratio
84.8
84
–96
–90
–90
96
THD
Total harmonic distortion
SFDR
Spurious-free dynamic range –0.5 dBFS at 100-kHz input
–0.5 dBFS at 250-kHz input
90
90
Isolation between ADC_A and
fIN = 15 kHz, fNOISE = 25 kHz
ADC_B
–90
dB
At –3 dB
Full-power bandwidth
25
5
BW(FP)
MHz
At –0.1 dB
8
Copyright © 2013–2018, Texas Instruments Incorporated
ADS8350, ADS7850, ADS7250
www.ti.com.cn
ZHCSCC6D –MAY 2013–REVISED MARCH 2018
6.9 Timing Requirements
MIN
NOM
MAX UNIT
750 kSPS
µs
fCLK = max
fTHROUGHPUT Sample taken to data read
fCLK = max
1.33
fCLK
CLOCK frequency
CLOCK period
fTHROUGHPUT = max
fTHROUGHPUT = max
24
MHz
ns
tCLK
41.66
0.4
0.4
120
100
70
tPH_CK
tPL_CK
CLOCK high time
CLOCK low time
0.6
0.6
tCLK
tCLK
ADS8350, fCLK = max
ADS7850, fCLK = max
ADS7250, fCLK = max
tACQ
Acquisition time
ns
ns
ns
tPH_CS
CS high time
20
ADS8350
ADS7850
ADS7250
120
100
70
tPH_CS_SHRT
CS high time after frame abort
tD_CKCS
Delay time from last SCLK falling to CS rising
Setup time from CS falling to SCLK falling
15
ns
ns
tSU_CSCK
15
6.10 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Conversion time
TEST CONDITIONS
MIN
TYP
MAX
590
12
UNIT
tCONV
ns
ns
tDV_CSDO
Delay time from CS falling to data enable
Delay time from CS rising to DOUT going to
3-state
tDZ_CSDO
tD_CKDO
10
20
ns
ns
Delay time from SCLK falling to (next) data
valid on SDO
3
Sample
N
Sample
N + 1
tTHROUGHPUT
tCONV
tACQ
tPH_CS
CS
tSCLK
tD_CKCS
tSU_CSCK
tPH_CK
tPL_CK
22
23
25
1
2
13
14
15
16
17
24
26
27
28
SCLK
30
30
31
32
tDZ_CSDO
D1 D0
tDV_CSDO
tD_CKDO
SDO-A
SDO-B
ADS8350
D15
D13
D11
D14
D12
D10
D9
D8
D7
D6
D5
D3
D1
D4
D3
D2
D0
0
Data From Sample N
D6 D5 D4
SDO-A
SDO-B
ADS7850
D7
D5
D2
D0
D1
0
0
0
0
0
Data From Sample N
D4 D3 D2
SDO-A
SDO-B
ADS7250
Data From Sample N
Figure 1. Timing Diagram
Copyright © 2013–2018, Texas Instruments Incorporated
9
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6.11 Typical Characteristics: ADS7250
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, and fDATA = 750 kSPS (unless otherwise noted)
1
0.75
0.5
1
0.75
0.5
0.25
0
0.25
0
-0.25
-0.5
-0.75
-1
-0.25
-0.5
-0.75
-1
0
1024
2048
Code
3072
4096
0
1024
2048
Code
3072
4096
C01
C01
Figure 2. Typical DNL
Figure 3. Typical INL
1
0.75
0.5
1
0.75
0.5
Maximum INL
Minimum INL
Maximum DNL
Minimum DNL
0.25
0
0.25
0
-0.25
-0.5
-0.75
-1
-0.25
-0.5
-0.75
-1
-40
-7
26
59
92
125
C01
-40
-7
26
59
92
125
C01
Free-Air Temperature (oC)
Free-Air Temperature (oC)
Figure 4. DNL vs Device Temperature
Figure 5. INL vs Device Temperature
0
-20
0
-20
fIN = 2 kHz
fIN = 250 kHz
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-200
-100
-120
-140
-160
-180
-200
0
75
150
225
300
375
0
75
150
225
300
375
Input Frequency (kHz)
C00
C00
Input Frequency (kHz)
Figure 6. Typical FFT at 2-kHz Input
Figure 7. Typical FFT at 250-kHz Input
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Typical Characteristics: ADS7250 (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, and fDATA = 750 kSPS (unless otherwise noted)
75
74.5
74
-80
-84
73.5
73
-88
-92
72.5
72
-96
71.5
71
-100
0
75
150
225
300
375
0
75
150
225
300
375
Input Frequency (kHz)
C00
Input Frequency (kHz)
C00
Figure 8. SNR vs Input Frequency
Figure 9. THD vs Input Frequency
75
74.5
74
74
73.5
73
73.5
73
72.5
72
72.5
72
71.5
71
71.5
71
70.5
70
fIN = 2 kHz
0
75
150
225
300
375
C00
-40
-7
26
59
92
125
C00
Input Frequency (kHz)
Free-Air Temperature (oC)
Figure 10. SINAD vs Input Frequency
Figure 11. SNR vs Device Temperature
-88
-88.5
-89
74
73.5
73
fIN = 2 kHz
-89.5
-90
72.5
72
-90.5
-91
71.5
71
-91.5
-92
70.5
70
fIN = 2 kHz
-40
-7
26
59
92
125
C00
-40
-7
26
59
92
125
C00
Free-Air Temperature (oC)
Free-Air Temperature (oC)
Figure 12. THD vs Device Temperature
Figure 13. SINAD vs Device Temperature
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Typical Characteristics: ADS7250 (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, and fDATA = 750 kSPS (unless otherwise noted)
100
1000
600
60
20
200
-20
-60
-100
-200
-600
-1000
-40
-7
26
59
92
125
C01
-40
-7
26
59
92
125
C01
Free-Air Temperature (oC)
Free-Air Temperature (oC)
Figure 14. Offset Error vs Device Temperature
Figure 15. Gain Error vs Device Temperature
70000
60000
50000
40000
30000
20000
10000
0
2045
2046
Code
2047
C01
Figure 16. DC Histogram
12
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6.12 Typical Characteristics: ADS7850
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, and fDATA = 750 kSPS (unless otherwise noted)
1
1
0.75
0.75
0.5
0.5
0.25
0.25
0
0
-0.25
-0.25
-0.5
-0.5
-0.75
-0.75
-1
-1
0
4096
8192
Code
12288
16384
C01
0
4096
8192
Code
12288
16384
C01
Figure 18. Typical INL
Figure 17. Typical DNL
2
1.5
1
2
1.5
1
Maximum INL
Minimum INL
0.5
0
Maximum DNL
Minimum DNL
0.5
0
-0.5
-1
-0.5
-1
-1.5
-2
-40
-7
26
59
92
125
-40
-7
26
59
92
125
C01
Free-Air Temperature (oC)
Free-Air Temperature (oC)
C01
Figure 19. DNL vs Device Temperature
Figure 20. INL vs Device Temperature
0
-20
0
fIN = 2 kHz
fIN = 250 kHz
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-200
-100
-120
-140
-160
-180
-200
0
75
150
225
300
375
0
75
150
225
300
375
C00
C00
Input Frequency (kHz)
Input Frequency (kHz)
Figure 21. Typical FFT at 2-kHz Input
Figure 22. Typical FFT at 250-kHz Input
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Typical Characteristics: ADS7850 (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, and fDATA = 750 kSPS (unless otherwise noted)
-80
84
83.5
83
-84
82.5
82
-88
-92
81.5
81
-96
80.5
80
-100
0
75
150
225
300
375
C00
0
75
150
225
300
375
C00
Input Frequency (kHz)
Input Frequency (kHz)
Figure 23. SNR vs Input Frequency
Figure 24. THD vs Input Frequency
86
85
84
83
82
81
80
79
78
84
83
82
81
80
79
78
fIN = 2 kHz
0
75
150
225
300
375
-40
-7
26
59
92
125
C00
Input Frequency (kHz)
Free-Air Temperature (oC)
C00
Figure 25. SINAD vs Input Frequency
Figure 26. SNR vs Device Temperature
-88
-89
-90
-91
-92
-93
-94
84
83
82
81
80
79
78
fIN = 2 kHz
fIN = 2 kHz
-40
-7
26
59
92
125
C00
-40
-7
26
59
92
125
C00
Free-Air Temperature (oC)
Free-Air Temperature (oC)
Figure 27. THD vs Device Temperature
Figure 28. SINAD vs Device Temperature
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Typical Characteristics: ADS7850 (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, and fDATA = 750 kSPS (unless otherwise noted)
100
1000
750
75
50
500
25
250
0
0
-25
-50
-75
-100
-250
-500
-750
-1000
-40
-7
26
59
92
125
C01
-40
-7
26
59
92
125
C01
Free-Air Temperature (oC)
Free-Air Temperature (oC)
Figure 29. Offset Error vs Device Temperature
Figure 30. Gain Error vs Device Temperature
60000
50000
40000
30000
20000
10000
0
8181
8182
8183
Code
8184
8185
C01
Figure 31. DC Histogram
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6.13 Typical Characteristics: ADS8350
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, and fDATA = 750 kSPS (unless otherwise noted)
1
0.8
0.6
0.4
0.2
0
2
1.5
1
0.5
0
-0.2
-0.4
-0.6
-0.8
-1
-0.5
-1
-1.5
-2
0
16384
32768
49152
65536
0
œ40
0
16384
32768
49152
65536
ADC Output Code (LSB)
C010
C011
ADC Output Code (LSB)
Figure 32. Typical DNL
Figure 33. Typical INL
2
1.5
1
2
1.5
1
Maximum INL
Maximum DNL
0.5
0
0.5
0
-0.5
-1
Minimum INL
Minimum DNL
-0.5
-1
-1.5
-2
26
59
92
125
26
59
92
125
œ7
œ40
œ7
C015
Free-Air Temperature (°C)
Free-Air Temperature (°C)
C013
Figure 35. INL vs Device Temperature
Figure 34. DNL vs Device Temperature
0
œ50
0
œ20
fIN = 2 kHz
fIN = 100 kHz
œ40
œ60
œ80
œ100
œ150
œ200
œ100
œ120
œ140
œ160
œ180
œ200
0
75
150
225
300
375
75
150
225
300
375
fIN, Input Frequency (kHz)
fIN, Input Frequency (kHz)
C001
C002
Figure 36. Typical FFT at 2-kHz Input
Figure 37. Typical FFT at 100-kHz Input
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Typical Characteristics: ADS8350 (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, and fDATA = 750 kSPS (unless otherwise noted)
œ80
œ82
œ84
œ86
œ88
œ90
œ92
œ94
œ96
œ98
œ100
86
85.5
85
84.5
84
83.5
83
82.5
82
0
75
150
225
300
375
0
75
150
225
300
375
fIN, Input Frequency (kHz)
fIN, Input Frequency (kHz)
C005
C003
Figure 38. SNR vs Input Frequency
Figure 39. THD vs Input Frequency
86
85.5
85
88
87.5
87
fIN = 2 kHz
84.5
84
86.5
86
83.5
83
85.5
85
82.5
82
84.5
84
0
75
150
225
300
375
26
59
92
125
œ40
œ7
C004
C018
fIN, Input Frequency (kHz)
Free-Air Temperature (°C)
Figure 40. SINAD vs Input Frequency
Figure 41. SNR vs Device Temperature
88
87.5
87
œ90
œ92
fIN = 2 kHz
fIN = 2 kHz
œ94
86.5
86
œ96
œ98
œ100
œ102
œ104
œ106
85.5
85
84.5
84
26
59
92
125
œ40
œ7
26
59
92
125
œ40
œ7
C021
C019
Free-Air Temperature (°C)
Free-Air Temperature (°C)
Figure 42. THD vs Device Temperature
Figure 43. SINAD vs Device Temperature
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Typical Characteristics: ADS8350 (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, and fDATA = 750 kSPS (unless otherwise noted)
1000
100
750
75
500
50
250
25
0
0
-250
-500
-750
-1000
-25
-50
-75
-100
26
59
92
125
26
59
92
125
œ40
œ7
œ40
œ7
C008
C009
Free-Air Temperature (°C)
Free-Air Temperature (°C)
Figure 44. Offset Error vs Device Temperature
Figure 45. Gain Error vs Device Temperature
25000
20000
15000
10000
5000
0
C007
Code
Figure 46. DC Histogram
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6.14 Typical Characteristics: All Devices
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, and fDATA = 750 kSPS (unless otherwise noted)
8
7.8
7.6
7.4
7.2
7
8
7.5
7
6.5
6
5.5
5
6.8
6.6
6.4
6.2
6
4.5
4
3.5
3
26
59
92
125
0
6
12
18
24
œ40
œ7
C016
C017
Free-Air Temperature (°C)
SCLK Frequency (MHz)
Figure 47. Dynamic Current vs Device Temperature
Figure 48. Supply Current vs SCLK Frequency
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7 Detailed Description
7.1 Overview
The ADS8350, ADS7850, and ADS7250 belong to a family of dual, high-speed, simultaneous-sampling, analog-
to-digital converters (ADCs). The devices support pseudo-differential input signals with the input common-mode
equal to the reference voltage and the full-scale input range equal to twice the reference voltage. The devices
provide a simple serial interface to the host controller and operate over a wide range of digital power supplies.
7.2 Functional Block Diagram
Comparator
S/H
CDAC
SAR
SAR
ADC_A
ADC_B
Serial
Interface
CDAC
S/H
Comparator
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7.3 Feature Description
7.3.1 Reference
Each device has two simultaneous-sampling ADCs (ADC_A and ADC_B). ADC_A operates with reference
voltage VREFIN_A and ADC_B operates with reference voltage VREFIN_B. These reference voltages must be
provided on the REFIN_A and REFIN_B pins, respectively. REFIN_A and REFIN_B may be set to different
values as per the application requirement.
As shown in Figure 49, decouple the REFIN_A and REFIN_B pins with the REFGND_A and REFGND_B pins,
respectively, with individual 10-µF decoupling capacitors.
AINP_A
ADC_A
VREFIN_A
AINM_A
REFIN_A
10 mF
REFGND_A
Serial
Interface
AINP_B
ADC_B
VREFIN_B
AINM_B
REFIN_B
10 mF
REFGND_B
Figure 49. Reference Block Diagram
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Feature Description (continued)
7.3.2 Analog Input
The devices support pseudo-differential analog input signals. These inputs are sampled and converted
simultaneously by the two ADCs (ADC_A and ADC_B). ADC_A samples and converts (VAINP_A – VAINM_A), and
ADC_B samples and converts (VAINP_B – VAINM_B).
Figure 50a and Figure 50b show equivalent circuits for the ADC_A and ADC_B analog input pins, respectively.
RS (typically 50 Ω) represents the on-state sampling switch resistance, and CSAMPLE represents the device
sampling capacitor (typically 40 pF).
AVDD
AVDD
RS
CSAMPLE
RS
CSAMPLE
AINP_A
AINP_B
GND
GND
AVDD
AVDD
RS
CSAMPLE
RS
CSAMPLE
AINM_A
AINM_B
GND
GND
a) ADC_A
b) ADC_B
Figure 50. Equivalent Circuit for Analog Input Pins
7.3.2.1 Analog Input Full-Scale Range
The analog input full-scale range (FSR) for ADC_A and ADC_B is twice the reference voltage provided to the
particular ADC. By providing different reference voltages (VREFIN_A and VREFIN_B), ADC_A and ADC_B can have
different full-scale input ranges. Therefore, the FSR for ADC_A and ADC_B can be determined by Equation 1
and Equation 2, respectively:
FSR_ADC_A = 2 × VREFIN_A
,
(1)
VAINP_A = 0 to 2 × VREFIN_A
,
VAINM_A = VREFIN_A
The REFIN_A and AINM_A pins must be shorted and connected to the external reference voltage, VREFIN_A
.
FSR_ADC_B = 2 × VREFIN_B
,
(2)
VAINP_B = 0 to 2 × VREFIN_B
,
VAINM_B = VREFIN_B
The REFIN_B and AINM_B pins must be shorted and connected to the external reference voltage, VREFIN_B
.
To use the full dynamic input range on the analog input pins, AVDD must be as shown in Equation 3, Equation 4,
and Equation 5:
AVDD ≥ 2 × VREFIN_A
AVDD ≥ 2 × VREFIN_B
4.5 V ≤ AVDD ≤ 5.5 V
(3)
(4)
(5)
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Feature Description (continued)
7.3.3 ADC Transfer Function
The device output is in binary twos complement format. Device resolution is calculated by Equation 6:
1 LSB = (FSR_ADC_x) / (2N)
where:
•
•
FSR_ADC_x = 2 x VREFIN_x and
N is the resolution of the ADC : N = 16 for the ADS8350, N = 14 for the ADS7850, and N = 12 for the
ADS7250
(6)
Table 1 shows the different input voltages and the corresponding device output codes.
Table 1. Transfer Characteristics
INPUT
VOLTAGE
(AINM_x)
PSEUDO-DIFFERENTIAL INPUT TO
ADC
OUTPUT CODE (HEX)
INPUT VOLTAGE
(AINP_x)
CODE
ADS7250
ADS7850
ADS8350
(AINP_x - AINM_x)
0
–VREFIN_x
– VREFIN_x + 1 LSB
–1 LSB
NFSR
NFSR + 1 LSB
–1 LSB
NFSC
NFSC + 1
MC
800
801
FFF
000
7FF
2000
2001
3FFF
0000
1FFF
8000
8001
FFFF
0000
7FFF
1 LSB
VREFIN_x
VREFIN_x – 1 LSB
VREFIN_x
0
0
PLC
2 × VREFIN_x – 1 LSB
VREFIN_x – 1 LSB
PFSR – 1 LSB
PFSC
Figure 51 shows the ideal transfer characteristics for the device.
PFSC
PLC
MC
NFSC + 1
NFSC
VIN
0
PFSR œ 1 LSB
NFSR
-1 LSB
Pseudo-Differential Analog Input
(AINP_x œ AINM_x)
Figure 51. Ideal Transfer Characteristics
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7.4 Device Functional Modes
7.4.1 Serial Interface
The devices support a simple, SPI-compatible serial interface to the external digital host. The CS signal defines
one conversion and serial transfer frame. A frame starts with a CS falling edge and ends with a CS rising edge.
The SDO_A and SDO_B pins output the ADC_A and ADC_B conversion results, respectively. Figure 52 shows a
detailed timing diagram for these devices.
Sample
N
Sample
N + 1
tTHROUGHPUT
tCONV
tACQ
CS
22
D9
D7
D5
23
25
1
2
13
14
15
16
17
24
26
27
28
SCLK
30
30
31
32
SDO-A
SDO-B
ADS8350
D15
D13
D11
D14
D12
D10
D8
D7
D6
D5
D3
D1
D4
D3
D2
D1
D0
Data From Sample N
D6 D5 D4
SDO-A
SDO-B
ADS7850
D2
D0
D1
0
D0
0
0
0
0
0
Data From Sample N
D4 D3 D2
SDO-A
SDO-B
ADS7850
Data From Sample N
Figure 52. Serial Interface Timing Diagram
A CS falling edge brings the serial data bus out of 3-state and also outputs a '0' on the SDO_A and SDO_B pins.
The device converts the sampled analog input during the next 14 clocks. SDO_A and SDO_B read '0' during this
period. The sample-and-hold circuit goes back into sample mode on the 15th SCLK falling edge and the MSBs of
ADC_A and ADC_B are output on SDO_A and SDO_B, respectively. The subsequent clock edges are used to
shift out the conversion result using the serial interface, as shown in Table 2. Output data are in binary twos
complement format. A CS rising edge ends the frame and puts the serial bus into 3-state.
Table 2. Data Launch Edge
LAUNCH EDGE
SCLK
DEVICE
PIN
CS ↓
↓1
0
…
…
…
…
…
…
…
↓14
0
↓15
…
…
…
…
…
…
…
↓26
↓27
↓28
↓29
↓30
↓31
0
…
…
…
…
…
…
…
CS ↑
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SDO-A
SDO-B
SDO-A
SDO-B
SDO-A
SDO-B
0
0
0
0
0
0
D15_A
D15_B
D13_A
D13_B
D11_A
D11_B
D4_A D3_A D2_A D1_A D0_A
D4_B D3_B D2_B D1_B D0_B
ADS8350
0
0
0
0
0
D2_A D1_A D0_A
D2_B D1_B D0_B
0
0
0
0
0
0
0
0
0
ADS7850
ADS7250
0
0
0
0
0
D0_A
D0_B
0
0
0
0
0
0
0
0
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7.4.2 Short-Cycling, Frame Abort, and Reconversion Feature
Referring to Table 2, the ADS8350 requires a minimum of 31 SCLK falling edges between the beginning and end
of the frame to complete the 16-bit data transfer, the ADS7850 requires a minimum of 29 SCLK falling edges
between the beginning and end of the frame to complete the 14-bit data transfer, and the ADS7250 requires a
minimum of 27 SCLK falling edges between the beginning and end of the frame to complete the 12-bit data
transfer. However, CS can be brought high at any time during the frame to abort the frame or to short-cycle the
converter.
As shown in Figure 53, if CS is brought high before the 15th SCLK falling edge, the device aborts the conversion
and starts sampling the new analog input signal.
tPL_CS
tPH_CS_SHRT
CS
1
2
SCLK
tDZ_CSDO
SDO
Figure 53. Frame Aborted before 15th SCLK Falling Edge
If CS is brought high after the 15th SCLK falling edge (as shown in Figure 54), the output data bits latched into
the digital host before this CS rising edge are still valid data corresponding to sample N.
Sample
N
Sample
N + 1
tCONV
tACQ
tPH_CS_SHRT
CS
22
tDZ_CSDO
D9 D8
23
1
2
13
14
15
16
17
24
SCLK
SDO-A
SDO-B
ADS8350
D14
D15
D13
D11
D7
Data From Sample N
D12
SDO-A
SDO-B
ADS7850
D7
D6
D5
Data From Sample N
D10
SDO-A
SDO-B
ADS7250
D5
D4
D3
Data From Sample N
Figure 54. Frame Aborted after 15th SCLK Falling Edge
After aborting the current frame, CS must be kept high for tPH_CS_SHRT to ensure that the minimum acquisition
time (tACQ) is provided for the next conversion.
Copyright © 2013–2018, Texas Instruments Incorporated
25
ADS8350, ADS7850, ADS7250
ZHCSCC6D –MAY 2013–REVISED MARCH 2018
www.ti.com.cn
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The two primary circuits required to maximize the performance of a high-precision, successive approximation
register (SAR), analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This
section details some general principles for designing these circuits and provides some application circuits
designed using these devices.
8.2 Typical Applications
8.2.1 DAQ Circuit: Maximum SINAD for a 10-kHz Input Signal at 750-kSPS Throughput
10 µF
5 V+
X5R
REFGND-A
1 kꢀ
0.1 ꢀ
+
-
ADC_A
REF5025
REFIN-A
1 µF
VOUT
TRIM
ADS8350
5 V+
0.22 ꢀ
1 kꢀ
+
-
1 µF
X5R
REFIN-B
10 µF
X5R
1 µF
ADC_B
0.1 ꢀ
REFGND-B
10 µF
X5R
OPA2350
Figure 55. Reference Drive Circuit with VREF = 2.5 V
26
Copyright © 2013–2018, Texas Instruments Incorporated
ADS8350, ADS7850, ADS7250
www.ti.com.cn
ZHCSCC6D –MAY 2013–REVISED MARCH 2018
Typical Applications (continued)
AVDD
VCM = VREF/2
AVDD
OPA836
+
+
10 ꢀ
1 kꢀ
AVDD
AINP
-
VIN+
3.9 nF
ADS8350
1kꢀ
AINM
GND
10 ꢀ
VREF = 2.5 V
ADS8350 : 16-bit, 750kSPS, Pseudo Differential
Input
INPUT DRIVER
Figure 56. DAQ Circuit: Maximum SINAD for a 10-kHz Input Signal at 750-kSPS Throughput
8.2.1.1 Design Requirements
For the ADS8350, design an input driver and reference driver circuit to achieve > 84-dB SNR and < –90-dB THD
at a 100-kHz input frequency.
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 ADC Reference Driver
The external reference source to the device must provide low-drift and very accurate voltage for the ADC
reference input and support the dynamic charge requirements without affecting the noise and linearity
performance of the device. The output broadband noise of most references can be in the order of a few
100 µVRMS. Therefore, in order to prevent any degradation in the noise performance of the ADC, the output of
the voltage reference must be appropriately filtered by using a low-pass filter with a cutoff frequency of a few
hundred Hertz.
After band-limiting the noise from the reference source, the next important step is to design a reference buffer
that can drive the dynamic load posed by the reference input of the ADC. At the start of each conversion, the
reference buffer must regulate the voltage of the reference pin within 1 LSB of the intended value. This condition
necessitates the use of a large filter capacitor at the reference pin of the ADC. The amplifier selected to drive this
large capacitor should have low output impedance, low offset, and temperature drift specifications.
To reduce the dynamic current requirements and crosstalk between the channels, a separate reference buffer is
recommended for driving the reference input of each ADC channel.
The application circuit in Figure 55 shows the schematic of a complete reference driver circuit that generates a
voltage of 2.5-V dc using a single 5-V supply.
The 2.5-V reference voltage is generated by the high-precision, low-noise REF5025 circuit. The output
broadband noise of the reference is heavily filtered by a low-pass filter with a 3-dB cutoff frequency of 160 Hz.
The decoupling capacitor on each reference pin is selected to be 10 µF. The low output impedance, low noise,
and fast settling time makes the OPA2350 a good choice for driving this high capacitive load.
8.2.1.2.2 ADC Input Driver
The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and a fly-wheel
RC filter. The amplifier is used for signal conditioning of the input voltage and its low output impedance provides
a buffer between the signal source and the switched capacitor inputs of the ADC. The RC filter helps attenuate
the sampling charge injection from the switched-capacitor input stage of the ADC and functions as an antialiasing
filter to band-limit the wideband noise contributed by the front-end circuit. Careful design of the front-end circuit is
critical to meet the linearity and noise performance of a high-precision ADC.
Copyright © 2013–2018, Texas Instruments Incorporated
27
ADS8350, ADS7850, ADS7250
ZHCSCC6D –MAY 2013–REVISED MARCH 2018
www.ti.com.cn
Typical Applications (continued)
8.2.1.2.2.1 Input Amplifier Selection
Selection criteria for the input amplifiers is highly dependent on the input signal type and the performance goals
of the data acquisition system. Some key amplifier specifications to consider while selecting an appropriate
amplifier to drive the inputs of the ADC are:
•
Small-signal bandwidth. Select the small-signal bandwidth of the input amplifiers to be as high as possible
after meeting the power budget of the system. Higher bandwidth reduces the closed-loop output impedance
of the amplifier, thus allowing the amplifier to more easily drive the low cutoff frequency RC filter at the ADC
inputs. Higher bandwidth also minimizes the harmonic distortion at higher input frequencies. In order to
maintain the overall stability of the input driver circuit, the amplifier bandwidth should be selected as
described in Equation 7:
≈
’
1
∆
∆
÷
÷
Unity - Gain Bandwidth í 4ì
2p
ì(RFLT + RFLT )ìCFLT
«
◊
(7)
•
Noise. Noise contribution of the front-end amplifiers should be as low as possible to prevent any degradation
in SNR performance of the system. As a rule of thumb, to ensure that the noise performance of the data
acquisition system is not limited by the front-end circuit, the total noise contribution from the front-end circuit
should be kept below 20% of the input-referred noise of the ADC. Noise from the input driver circuit is band-
limited by designing a low cutoff frequency RC filter, as explained in Equation 8.
2
SNR
(
dB
)
≈
∆
’
÷
V
≈
∆
’
÷
-
1
_ AMP_PP
p
2
1
5
VREF
2
20
+ en2_RMS
ì
ì f-3dB
Ç
ì
ì10
f
«
◊
NG ì 2 ì
∆
∆
÷
÷
6.6
«
◊
where:
•
•
•
•
V1 / f_AMP_PP is the peak-to-peak flicker noise in µVRMS
,
en_RMS is the amplifier broadband noise density in nV/√Hz,
f–3dB is the 3-dB bandwidth of the RC filter, and
NG is the noise gain of the front-end circuit, which is equal to '1' in a buffer configuration.
(8)
•
•
Distortion. Both the ADC and the input driver introduce nonlinearity in a data acquisition block. As a rule of
thumb, to ensure that the distortion performance of the data acquisition system is not limited by the front-end
circuit, the distortion of the input driver should be at least 10 dB lower than the distortion of the ADC, as
shown in Equation 9.
THDAMP Ç THDADC - 10
dB
(9)
Settling Time. For dc signals with fast transients that are common in a multiplexed application, the input signal
must settle to the desired accuracy at the inputs of the ADC during the acquisition time window. This
condition is critical to maintain the overall linearity performance of the ADC. Typically, the amplifier data
sheets specify the output settling performance only up to 0.1% to 0.001%, which may not be sufficient for the
desired accuracy. Therefore, the settling behavior of the input driver should always be verified by TINA™-
SPICE simulations before selecting the amplifier.
28
Copyright © 2013–2018, Texas Instruments Incorporated
ADS8350, ADS7850, ADS7250
www.ti.com.cn
ZHCSCC6D –MAY 2013–REVISED MARCH 2018
Typical Applications (continued)
8.2.1.2.2.2 Antialiasing Filter
Converting analog-to-digital signals requires sampling an input signal at a constant rate. Any higher frequency
content in the input signal beyond half the sampling frequency is digitized and folded back into the low-frequency
spectrum. This process is called aliasing. Therefore, an analog, antialiasing filter must be used to remove the
harmonic content from the input signal before being sampled by the ADC. An antialiasing filter is designed as a
low-pass, RC filter, for which the 3-dB bandwidth is optimized based on specific application requirements. For dc
signals with fast transients (including multiplexed input signals), a high-bandwidth filter is designed to allow
accurately settling the signal at the ADC inputs during the small acquisition time window. For ac signals, the filter
bandwidth should be kept low to band-limit the noise fed into the ADC input, thereby increasing the signal-to-
noise ratio (SNR) of the system.
Besides filtering noise from the front-end drive circuitry, the RC filter also helps attenuate the sampling charge
injection from the switched-capacitor input stage of the ADC. A filter capacitor, CFLT, is connected across the
ADC inputs (as shown in Figure 57).
RFLT ≤ 22 ꢀ
AINP
1
f-3dB
=
ADS8350
CFLT ≥ 400 pF
2p ì
(
RFLT + RFLT ì CFLT
)
AINM
GND
RFLT ≤ 22 ꢀ
Figure 57. Antialiasing Filter
This capacitor helps reduce the sampling charge injection and provides a charge bucket to quickly charge the
internal sample-and-hold capacitors during the acquisition process. As a rule of thumb, the value of this capacitor
should be at least 10 times the specified value of the ADC sampling capacitance. For these devices, the input
sampling capacitance is equal to 40 pF. Thus, the value of CFLT should be greater than 400 pF. The capacitor
should be a COG- or NPO-type because these capacitor types have a high-Q, low-temperature coefficient, and
stable electrical characteristics under varying voltages, frequency, and time.
Note that driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier
marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of
the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a
result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance,
input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability
and distortion of the design. For these devices, TI recommends limiting the value of RFLT to a maximum of 22 Ω
in order to avoid any significant degradation in linearity performance. The tolerance of the selected resistors can
be chosen as 1% because the use of a differential capacitor at the input balances the effects resulting from any
resistor mismatch.
The input amplifier bandwidth should be much higher than the cutoff frequency of the antialiasing filter. TI
strongly recommends performing a SPICE simulation to confirm that the amplifier has more than 40° phase
margin with the selected filter. Simulation is critical because even with high-bandwidth amplifiers, some amplifiers
might require more bandwidth than others to drive similar filters. If an amplifier has less than a 40° phase margin
with 22-Ω resistors, using a different amplifier with higher bandwidth or reducing the filter cutoff frequency with a
larger differential capacitor is advisable.
The application circuit shown in Figure 56 is optimized to achieve lowest distortion and lowest noise for a 10-kHz
input signal. The input signal is processed through a high-bandwidth, low-distortion amplifier in an inverting gain
configuration and a low-pass RC filter before being fed into the ADS8350 operating at 750-kSPS throughput.
Copyright © 2013–2018, Texas Instruments Incorporated
29
ADS8350, ADS7850, ADS7250
ZHCSCC6D –MAY 2013–REVISED MARCH 2018
www.ti.com.cn
Typical Applications (continued)
As a rule of thumb, the distortion from the input driver should be at least 10 dB less than the ADC distortion. The
distortion resulting from variation in the common-mode signal is eliminated by using the amplifier in an inverting
gain configuration that establishes a fixed common-mode level for the circuit. The low-power OPA836, used as
an input driver, provides exceptional ac performance because of its extremely low-distortion, high-bandwidth
specifications. In addition, the components of the antialiasing filter are such that the noise from the front-end
circuit is kept low without adding distortion to the input signal.
NOTE
The same circuit can be used with the ADS7250 and ADS7850 to achieve their rated
specifications.
8.2.1.3 Application Curve
Figure 58 shows FFT plot and test results obtained with circuit configuration shown in Figure 56.
0
AVDD = 5 V
-20
REF = 2.5 V
TA = 25oC
-40
fIN = 10 kHz
SNR = 85.5 dB
THD = -94 dB
-60
-80
-100
-120
-140
-160
0
75
150
225
300
375
C10
Input Frequency (kHz)
Figure 58. FFT Plot and Test Results with ADS8350
30
Copyright © 2013–2018, Texas Instruments Incorporated
ADS8350, ADS7850, ADS7250
www.ti.com.cn
ZHCSCC6D –MAY 2013–REVISED MARCH 2018
Typical Applications (continued)
8.2.2 DAQ Circuit: Maximum SINAD for a 100-kHz Input Signal at 750-kSPS Throughput
10 µF
5 V+
X5R
REFGND-A
1 kꢀ
0.1 ꢀ
+
-
ADC_A
REF5025
REFIN-A
1 µF
VOUT
TRIM
ADS8350
5 V+
0.22 ꢀ
1 kꢀ
+
-
1 µF
X5R
REFIN-B
10 µF
X5R
1 µF
ADC_B
0.1 ꢀ
REFGND-B
10 µF
X5R
OPA2350
Figure 59. Reference Drive Circuit with VREF = 2.5 V
+15 V
VREF/2
AVDD
THS4032
+
4.7 ꢀ
602 ꢀ
AVDD
-
AINP
VIN+
1 nF
ADS8350
-15 V
602 ꢀ
AINM
GND
10 pF
4.7 ꢀ
+15 V
VREF
ADS8350 : 16-bit, 750kSPS, Pseudo
Differential Input
+
-
-15 V
INPUT DRIVER
THS4032
Figure 60. DAQ Circuit: Maximum SINAD for a 100-kHz Input Signal at 750-kSPS Throughput
Copyright © 2013–2018, Texas Instruments Incorporated
31
ADS8350, ADS7850, ADS7250
ZHCSCC6D –MAY 2013–REVISED MARCH 2018
www.ti.com.cn
Typical Applications (continued)
8.2.2.1 Design Requirements
For the ADS8350, design an input driver and reference driver circuit to achieve > 84-dB SNR and < –90-dB THD
at a 100-kHz input frequency.
8.2.2.2 Detailed Design Procedure
8.2.2.2.1 ADC Reference Driver
Refer to the ADC Reference Driver section for a detailed design procedure for the ADC reference driver.
The application circuit in Figure 55 shows the schematic of a complete reference driver circuit that generates a
voltage of 2.5-V dc using a single 5-V supply. This circuit is suitable to drive the reference of the ADS8350 at
sampling rates up to 750 kSPS.
The 2.5-V reference voltage is generated by the high-precision, low-noise REF5025 circuit. The output
broadband noise of the reference is heavily filtered by a low-pass filter with a 3-dB cutoff frequency of 160 Hz.
The decoupling capacitor on each reference pin is selected to be 10 µF. The low output impedance, low noise,
and fast settling time makes the OPA2350 a good choice for driving this high capacitive load.
8.2.2.2.2 ADC Input Driver
Refer to ADC Input Driver section for the detailed design procedure for an ADC input driver.
The application circuit shown in Figure 60 is optimized to achieve lowest distortion and lowest noise for a 100-
kHz input signal. The input signal is processed through a high-bandwidth, low-distortion amplifier in an inverting
gain configuration and a low-pass RC filter before being fed into the ADS8350 operating at 750-kSPS
throughput.
As a rule of thumb, the distortion from the input driver should be at least 10 dB less than the ADC distortion. The
distortion resulting from variation in the common-mode signal is eliminated by using the amplifier in an inverting
gain configuration that establishes a fixed common-mode level for the circuit. This configuration also eliminates
the requirement of a rail-to-rail swing at the input of the amplifier. The THS4032, used as an input driver,
provides exceptional ac performance because of its extremely low-distortion, low-noise, and high-bandwidth
specifications. The ADC AINM pin is also driven to VREF with the same amplifier to match the source impedance
and to take full advantage of the pseudo-differential input structure of the ADC. In addition, the components of
the antialiasing filter are such that the noise from the front-end circuit is kept low without adding distortion to the
input signal.
NOTE
The same circuit can be used with the ADS7250 and ADS7850 to achieve their rated
specifications.
32
Copyright © 2013–2018, Texas Instruments Incorporated
ADS8350, ADS7850, ADS7250
www.ti.com.cn
ZHCSCC6D –MAY 2013–REVISED MARCH 2018
Typical Applications (continued)
8.2.2.3 Application Curve
Figure 61 shows FFT plot and test results obtained with circuit configuration shown in Figure 60.
0
AVDD = 5 V
-20
-40
REF = 2.5 V
TA = 25oC
fIN = 100 kHz
SNR = 85 dB
THD = -91 dB
-60
-80
-100
-120
-140
-160
0
75
150
225
300
375
C10
Input Frequency (kHz)
Figure 61. FFT Plot and Test Results with ADS8350
9 Power Supply Recommendations
The devices have two separate power supplies: AVDD and DVDD. The ADC operates on AVDD; DVDD is used
for the interface circuits. AVDD and DVDD can be independently set to any value within the permissible range.
The AVDD supply voltage value defines the permissible voltage swing on the analog input pins. To avoid
saturation of output codes, the external reference voltages VREFIN_A and VREFIN_B should be as shown in
Equation 10:
2 V ≤ VREFIN_x ≤ AVDD / 2
(10)
In other words, in order to use the VREFIN_x external reference voltage and use the full dynamic range on the
analog input pins, AVDD must be set as shown in Equation 11, Equation 12, and Equation 13:
AVDD ≥ 2 × VREFIN_A
AVDD ≥ 2 × VREFIN_B
4.5 V ≤ AVDD ≤ 5.5 V
(11)
(12)
(13)
Decouple the AVDD and DVDD pins with the GND pin using individual 10-µF decoupling capacitors, as shown in
Figure 62.
AVDD
AVDD (pin 14)
GND (pin 13)
DVDD (pin 7)
10 mF
10 mF
DVDD
Figure 62. Power-Supply Decoupling
Copyright © 2013–2018, Texas Instruments Incorporated
33
ADS8350, ADS7850, ADS7250
ZHCSCC6D –MAY 2013–REVISED MARCH 2018
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
Figure 63 shows a board layout example for the ADS7250, ADS7850, and ADS8350. Use a ground plane
underneath the device and partition the PCB into analog and digital sections. Avoid crossing digital lines with the
analog signal path and keep the analog input signals and the reference input signals away from noise sources.
As shown in Figure 63, the analog input and reference signals are routed on the left side of the board and the
digital connections are routed on the right side of the device.
The power sources to the ADS8350 must be clean and well-bypassed. Use 10-µF ceramic bypass capacitors in
close proximity to the analog (AVDD) and digital (DVDD) power-supply pins. Avoid placing vias between the
AVDD and DVDD pins and the bypass capacitors. Connect all ground pins to the ground plane using short, low-
impedance paths.
The REFIN-A and REFIN-B reference inputs are bypassed with 10-µF, X7R-grade ceramic capacitors (CREF-x).
Although the reference inputs of the device draw little current on average, there are instantaneous dynamic
current demands placed on the reference circuitry characteristic of SAR ADCs. Place the reference bypass
capacitors as close as possible to the reference REFIN-x pins and connect the bypass capacitors using short,
low-inductance connections. Avoid placing vias between the REFIN-x pins and the bypass capacitors. If the
reference voltage originates from an op amp, make sure that the op amp can drive the bypass capacitor without
oscillation. Small 0.1-Ω to 0.2-Ω resistors (RREF-x) are used in series with the reference bypass capacitors to
improve stability.
The fly-wheel RC filters are placed immediately next to the input pins. Among ceramic surface-mount capacitors,
COG (NPO) ceramic capacitors provide the best capacitance precision. The type of dielectric used in COG
(NPO) ceramic capacitors provides the most stable electrical properties over voltage, frequency, and temperature
changes. Figure 63 shows the CIN-A and CIN-B filter capacitors placed across the analog input pins of the device.
10.2 Layout Example
AVDD
GND
CREF-A
CIN-A
CAVDD
GND
SDO-A
SDO-B
SCLK
/CS
REFIN-A
GND
GND
REFGND-A
REFGND-B
GND
REFIN-B
GND
CDVDD
CREF-B
CIN-B
DVDD
GND
GND
Figure 63. Layout Example
34
版权 © 2013–2018, Texas Instruments Incorporated
ADS8350, ADS7850, ADS7250
www.ti.com.cn
ZHCSCC6D –MAY 2013–REVISED MARCH 2018
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
如需相关文档，请参阅：
•
•
•
•
REF50xx 低噪声、极低温漂、高精度电压基准
MicroAmplifier 系列 OPAx350 高速单电源轨至轨运算放大器
OPAx836 极低功耗、轨至轨输出、负轨输入、电压反馈运算放大器
THS403x 100MHz 低噪声高速放大器
11.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即购买的快速链接。
表 3. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
工具和软件
请单击此处
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
请单击此处
ADS8350
ADS7850
ADS7250
11.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。请单击右上角的提醒我 进行注册，即可每周接收
产品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.5 商标
TINA, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，也
不会对此文档进行修订。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
版权 © 2013–2018, Texas Instruments Incorporated
35
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS7250IRTER
ADS7250IRTET
ADS7850IRTER
ADS7850IRTET
ADS8350IRTER
ADS8350IRTET
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
RTE
RTE
RTE
RTE
RTE
RTE
16
16
16
16
16
16
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
7250
7250
7850
7850
8350
8350
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS7250IRTER
ADS7250IRTET
ADS7850IRTER
ADS7850IRTET
ADS8350IRTER
ADS8350IRTET
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
RTE
RTE
RTE
RTE
RTE
RTE
16
16
16
16
16
16
3000
250
330.0
180.0
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
1.1
1.1
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2018
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS7250IRTER
ADS7250IRTET
ADS7850IRTER
ADS7850IRTET
ADS8350IRTER
ADS8350IRTET
WQFN
WQFN
WQFN
WQFN
WQFN
WQFN
RTE
RTE
RTE
RTE
RTE
RTE
16
16
16
16
16
16
3000
250
367.0
210.0
367.0
210.0
367.0
210.0
367.0
185.0
367.0
185.0
367.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
250
3000
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RTE 16
3 x 3, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225944/A
www.ti.com
PACKAGE OUTLINE
RTE0016D
WQFN - 0.8 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.15
2.85
A
B
PIN 1 INDEX AREA
3.15
2.85
C
0.8
0.7
SEATING PLANE
0.08 C
0.05
0.00
2X 1.5
SYMM
(0.2) TYP
5
8
EXPOSED
THERMAL PAD
4
9
SYMM
17
2X 1.5
0.8 0.1
12X 0.5
1
12
PIN 1 ID
0.30
0.18
16X
16
13
0.5
0.3
0.1
C A B
16X
0.05
4219118/A 11/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTE0016D
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
0.8)
SYMM
SEE SOLDER MASK
DETAIL
16
13
16X (0.6)
12
16X (0.24)
1
17
SYMM
(2.8)
12X (0.5)
(R0.05) TYP
4
9
(
0.2) TYP
VIA
5
8
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219118/A 11/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTE0016D
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
0.76)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
12X (0.5)
(2.8)
9
4
(R0.05) TYP
5
8
SYMM
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 17
90% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219118/A 11/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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