ADS7251IRTER [TI]
SAR ADC、双路、2 MSPS、12 位、同步采样 | RTE | 16 | -40 to 125;
| 型号： | ADS7251IRTER |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SAR ADC、双路、2 MSPS、12 位、同步采样 | RTE | 16 | -40 to 125 |
| 文件： | 总38页 (文件大小：1609K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADS7251, ADS7851
ZHCSCB7A –JANUARY 2014–REVISED APRIL 2014
ADS7x51 12 位，2MSPS 和 14 位，1.5MSPS，双路，差分输入，同步采
样模数转换器，具有内部基准
1 特性
3 说明
1
•
•
•
•
•
12 和 14 位引脚兼容系列
ADS7251 和 ADS7851 属于引脚兼容、双路、高速、
同步采样模数转换器 (ADC) 产品系列，此系列产品支
持全差分模拟输入，并且特有 2 个单独的内部电压基
准。 ADS7251 提供 12 位分辨率以及高达 2MSPS 的
采样速度。 ADS7851 提供 14 位分辨率以及高达
1.5MSPS 的采样速度。
两个通道同时采样
支持全差分模拟输入
独立内部基准（每个 ADC 一个）
高速：
–
–
使用 ADS7251（12 位）时高达 2MSPS
使用 ADS7851（14 位）时高达 1.5MSPS
此器件支持宽数字电源电压范围，从而通过一个简单串
口轻松实现与多种数字主机控制器的通信。 两个器件
都在扩展工业用温度范围（-40°C 至 +125°C）内完全
额定运行，并且采用引脚兼容、节省空间的 WQFN-16
(3mm x 3mm) 封装。
•
出色的性能：
–
ADS7251：
–
–
信噪比 (SNR)：73dB
积分非线性 (INL)：±1 最低有效位 (LSB)
–
ADS7851：
器件信息
–
–
信噪比 (SNR)：83.5dB
积分非线性 (INL)：±2LSB
订货编号
ADS7251RTE
ADS7851RTE
封装
WQFN (16)
WQFN (16)
封装尺寸
3mm x 3mm
•
•
在 -40°C 至 +125°C 的扩展工业用温度范围内完全
额定运行
3mm x 3mm
小型封装：超薄四方扁平无引线 (WQFN)-16 (3mm
x 3mm)
典型应用图
C
R
ADS7851,
ADS7251
2 应用范围
•
•
电机控制：与 SinCos 编码器的直接对接
AINP
光网络互连：掺铒光纤放大器 (EDFA) 增益控制环
路
VCM
+V
+V
+V
•
•
•
•
•
保护中继器
AINM
电源质量测量
三相电源控制
可编程逻辑控制器
工业自动化
R
C
Internal
C
R
Reference
AINP
VCM
+V
+V
+V
AINM
R
C
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SBAS587
ADS7251, ADS7851
ZHCSCB7A –JANUARY 2014–REVISED APRIL 2014
www.ti.com.cn
目录
7.1 Overview ................................................................. 17
7.2 Functional Block Diagram ....................................... 17
7.3 Feature Description................................................. 18
7.4 Device Functional Modes........................................ 21
Application and Implementation ........................ 23
8.1 Application Information............................................ 23
8.2 Typical Application ................................................. 23
Power Supply Recommendations...................... 27
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Terminal Configuration and Functions................ 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 Handling Ratings....................................................... 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics: ADS7251 ......................... 5
6.6 Electrical Characteristics: ADS7851 ......................... 6
6.7 Electrical Characteristics: Common .......................... 7
6.8 ADS7251 Timing Characteristics .............................. 8
6.9 ADS7851 Timing Characteristics .............................. 9
6.10 Typical Characteristics: ADS7251 ........................ 10
6.11 Typical Characteristics: ADS7851 ........................ 13
6.12 Typical Characteristics: Common ......................... 16
Detailed Description ............................................ 17
8
9
10 Layout................................................................... 28
10.1 Layout Guidelines ................................................. 28
10.2 Layout Example .................................................... 28
11 器件和文档支持 ..................................................... 29
11.1 文档支持................................................................ 29
11.2 相关链接................................................................ 29
11.3 Trademarks........................................................... 29
11.4 Electrostatic Discharge Caution............................ 29
11.5 Glossary................................................................ 29
12 机械封装和可订购信息 .......................................... 29
7
4 修订历史记录
Changes from Original (January 2014) to Revision A
Page
•
•
•
•
•
已将格式更改为最新的数据表标准；已添加 电路板布局 部分，已移动现有部分 ................................................................... 1
Deleted Ordering Information table ........................................................................................................................................ 3
Changed Supply Current, IDVDD parameter typical specification in Electrical Characteristics: ADS7251 table...................... 5
Changed Supply Current, IDVDD parameter typical specification in Electrical Characteristics: ADS7851 table...................... 6
Changed Input Voltage column in Table 1 ........................................................................................................................... 20
2
版权 © 2014, Texas Instruments Incorporated
ADS7251, ADS7851
www.ti.com.cn
ZHCSCB7A –JANUARY 2014–REVISED APRIL 2014
5 Terminal Configuration and Functions
RTE Package
WQFN-16
(Top View)
REFOUT-A
REFGND-A
REFGND-B
REFOUT-B
1
2
3
4
12 SDO-B
11
10
9
SDO-A
SCLK
CS
Thermal Pad
Terminal Descriptions
TERMINAL
NAME
NO.
16
15
5
I/O
DESCRIPTION
AINM-A
AINP-A
AINM-B
AINP-B
AVDD
Analog input
Analog input
Analog input
Analog input
Supply
Negative analog input, channel A
Positive analog input, channel A
Negative analog input, channel B
Positive analog input, channel B
ADC supply voltage
6
14
9
CS
Digital input
Supply
Chip-select signal; active low
Digital I/O supply
DVDD
7
GND
8, 13
2
Supply
Digital ground
REFGND-A
REFGND-B
REFOUT-A
REFOUT-B
SCLK
Supply
Reference ground potential, channel A
Reference ground potential, channel B
Reference voltage output, REF_A
3
Supply
1
Analog output
Analog output
Digital input
Digital output
Digital output
4
Reference voltage output, REF_B
10
11
12
Serial communication clock
SDO-A
Data output for serial communication, channel A
Data output for serial communication, channel B
SDO-B
Exposed thermal pad.
TI recommends connecting this pin to the printed circuit board (PCB) ground.
Thermal pad
Supply
Copyright © 2014, Texas Instruments Incorporated
3
ADS7251, ADS7851
ZHCSCB7A –JANUARY 2014–REVISED APRIL 2014
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
MAX
+7
UNIT
V
AVDD to GND
Supply voltage
DVDD to GND
–0.3
+7
V
AINP_x to REFGND_x
Analog input voltage
REFGND_x – 0.3
REFGND_x – 0.3
GND – 0.3
AVDD + 0.3
AVDD + 0.3
DVDD + 0.3
0.3
V
V
AINM_x to REFGND_x
Digital input voltage
Ground voltage difference
Input current
CS, SCLK to GND
V
| REFGND_x – GND |
Any pin except supply pins
V
±10
mA
°C
Maximum virtual junction temperature, TJ
+150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 Handling Ratings
MIN
MAX
UNIT
Tstg
Storage temperature range
–65
+150
°C
Human body model (HBM) ESD stress voltage(2)
JEDEC standard 22, test method A114-C.01
Charged device model (CDM) ESD stress voltage(3)
JEDEC standard 22, test method C101
,
±2000
±500
V
V
(1)
VESD
,
all pins
,
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in
to the device.
(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that ±2000-V HBM
allows safe manufacturing with a standard ESD control process.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that ±500-V CDM allows safe
manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
5
MAX
UNIT
V
AVDD
DVDD
Analog supply voltage
Digital supply voltage
3.3
V
6.4 Thermal Information
ADS7251,
ADS7851
THERMAL METRIC(1)
UNIT
RTE (WQFN)
16 TERMINALS
RθJA
Junction-to-ambient thermal resistance
33.3
29.5
7.3
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
7.4
RθJC(bot)
0.9
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2014, Texas Instruments Incorporated
ADS7251, ADS7851
www.ti.com.cn
ZHCSCB7A –JANUARY 2014–REVISED APRIL 2014
6.5 Electrical Characteristics: ADS7251
All minimum and maximum specifications are at TA = –40°C to +125°C, AVDD = 5 V, VREF_A = VREF_B = 2.5 V, and fDATA
2 MSPS, unless otherwise noted. Typical values are at TA = +25°C, AVDD = 5 V, and DVDD = 3.3 V.
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESOLUTION
Resolution
12
Bits
SAMPLING DYNAMICS
tCONV
tACQ
fDATA
fCLK
Conversion time
tSU_CSCK + 12 tCLK
ns
ns
Acquisition time
Data rate
75
2
MSPS
MHz
Clock frequency
32
DC ACCURACY
NMC
DNL
INL
No missing codes
12
–0.99
–1
Bits
LSB
LSB
mV
Differential nonlinearity
Integral nonlinearity
Input offset error
±0.3
±0.5
±0.2
±0.2
4
1
1
1
1
VOS
–1
VOS match
ADC_A to ADC_B
–1
mV
dVOS/dT
GE
Input offset thermal drift
μV/°C
Referenced to the voltage at
REFOUT_x
Gain error
–0.1%
–0.1%
±0.05%
±0.05%
1
0.1%
0.1%
GERR match
ADC_A to ADC_B
Referenced to the voltage at
REFOUT_x
GE/dT
Gain error thermal drift
Common-mode rejection ratio
ppm/°C
dB
CMRR
Both ADCs, dc to 20 kHz
72
AC ACCURACY
SINAD
SNR
Signal-to-noise + distortion
72.7
72.8
72.9
73
dB
dB
dB
dB
Signal-to-noise ratio
For 20-kHz input frequency,
at –0.5 dBFS
THD
Total harmonic distortion
Spurious-free dynamic range
–90
90
SFDR
Isolation between ADC_A and
ADC_B
fIN = 15 kHz, fNOISE = 25 kHz
–105
dB
SUPPLY CURRENT
Analog, during
conversion
Throughput = 2 MSPS,
AVDD = 5 V
IAVDD-DYNAMIC
11
12
60
mA
Supply
current
IAVDD-STATIC
IDVDD
POWER DISSIPATION
Analog, static
5.5
mA
mA
Digital, for code 800
0.15
Throughput = 2 MSPS,
AVDD = 5 V
PD-ACTIVE
PD-STATIC
During conversion
Static mode
55
mW
mW
Power
dissipation
27.5
Copyright © 2014, Texas Instruments Incorporated
5
ADS7251, ADS7851
ZHCSCB7A –JANUARY 2014–REVISED APRIL 2014
www.ti.com.cn
6.6 Electrical Characteristics: ADS7851
All minimum and maximum specifications are at TA = –40°C to +125°C, AVDD = 5 V, VREF_A = VREF_B = 2.5 V, and fDATA
1.5 MSPS, unless otherwise noted. Typical values are at TA = +25°C, AVDD = 5 V, and DVDD = 3.3 V.
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESOLUTION
Resolution
14
Bits
SAMPLING DYNAMICS
tCONV
tACQ
fDATA
fCLK
Conversion time
tSU_CSCK + 14 tCLK
ns
ns
Acquisition time
Data rate
90
1500
27
kSPS
MHz
Clock frequency
DC ACCURACY
NMC
DNL
INL
No missing codes
13
–1
–2
–1
–1
Bits
LSB
LSB
mV
Differential nonlinearity
Integral nonlinearity
Input offset error
±0.75
±1
2
2
1
1
VOS
±0.2
±0.2
1
VOS match
ADC_A to ADC_B
mV
dVOS/dT
GE
Input offset thermal drift
μV/°C
Referenced to the voltage at
REFOUT_x
Gain error
–0.1%
–0.1%
±0.05%
±0.05%
1
0.1%
0.1%
GERR match
ADC_A to ADC_B
Referenced to the voltage at
REFOUT_x
GE/dT
Gain error thermal drift
Common-mode rejection ratio
ppm/°C
dB
CMRR
Both ADCs, dc to 20 kHz
72
AC ACCURACY
SINAD
SNR
Signal-to-noise + distortion
81.4
82
82.6
83.5
–90
90
dB
dB
dB
dB
Signal-to-noise ratio
For 20-kHz input frequency,
at –0.5 dBFS
THD
Total harmonic distortion
Spurious-free dynamic range
SFDR
Isolation between ADC_A and
ADC_B
fIN = 15 kHz, fNOISE = 25 kHz
–120
dB
SUPPLY CURRENT
Analog, during
conversion
Throughput = 1.5 MSPS,
AVDD = 5 V
IAVDD-DYNAMIC
10
5.5
12
60
mA
mA
mA
Supply
current
IAVDD-STATIC
IDVDD
POWER DISSIPATION
Analog, static
Digital, for code
2000
0.15
Throughput = 1.5 MSPS,
AVDD = 5 V
PD-ACTIVE
PD-STATIC
During conversion
Static mode
50
mW
mW
Power
dissipation
27.5
6
Copyright © 2014, Texas Instruments Incorporated
ADS7251, ADS7851
www.ti.com.cn
ZHCSCB7A –JANUARY 2014–REVISED APRIL 2014
6.7 Electrical Characteristics: Common
All minimum and maximum specifications are at TA = –40°C to +125°C, AVDD = 5 V, VREF_A = VREF_B = 2.5 V, and fDATA
2 MSPS, unless otherwise noted. Typical values are at TA = +25°C, AVDD = 5 V, and DVDD = 3.3 V.
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
For AVDD ≥ 5 V
–2 VREF
2 VREF
AVDD
2 VREF
AVDD
V
V
Full-scale input range
(AINP_x – AINM_x)
FSR
For AVDD < 5 V
For AVDD ≥ 5 V
For AVDD < 5 V
VREF_A = VREF_B = VREF
In sample mode
In hold mode
–AVDD
0
0
V
Absolute input voltage
(AINP_x or AIM_x to REFGND_x)
VIN
V
VCM
CIN
Input common-mode voltage range
Input capacitance
VREF – 0.1
VREF VREF + 0.1
V
40
4
pF
pF
SAMPLING DYNAMICS
tA
Aperture delay
8
40
25
5
ns
ps
tA match
ADC_A to ADC_B
At 3 dB
MHz
MHz
Full-power
bandwidth
BW
At 0.1 dB
INTERNAL VOLTAGE REFERENCE
VREFOUT
Internal reference output voltage
At +25°C
2.495
2.500
±1
2.505
V
mV
VREFOUT-match VREFOUT matching
| REFOUT_A – REFOUT_B |
1000 hours
dVREFOUT/dt
Long-term voltage drift
150
±10
1
ppm
ppm/°C
Ω
dVREFOUT/dT Reference voltage drift with temperature
RO
Internal reference output impedance
External output capacitor
COUT
22
μF
Internal reference output settling time
COUT = 22 μF
10
ms
DIGITAL INPUTS(1)
VIH
VIL
CIN
IIN
Input voltage, high
0.7 DVDD
–0.3
DVDD + 0.3
0.3 DVDD
V
V
Input voltage, low
Input capacitance
Input leakage current
5
pF
μA
0 ≤ Vdigital-input ≤ DVDD
±0.1
1
DIGITAL OUTPUTS(1)
VOH
VOL
Output voltage, high
Output voltage, low
IOH = 500-µA source
IOH = 500-µA sink
0.8 DVDD
0
DVDD
V
V
0.2 DVDD
POWER SUPPLY
AVDD
Analog (AVDD to GND)
Digital (DVDD to GND)
4.75(2)
1.65
5.0
3.3
3
5.25
5.25
3.6
V
V
V
Supply voltage
Operational range
DVDD
For specified performance
1.65
TEMPERATURE RANGE
TA
Operating free-air temperature
–40
+125
°C
(1) Specified by design; not production tested.
(2) The AVDD supply voltage defines the permissible voltage swing on the analog input pins. Refer to the Power Supply Recommendations
section for more details.
Copyright © 2014, Texas Instruments Incorporated
7
ADS7251, ADS7851
ZHCSCB7A –JANUARY 2014–REVISED APRIL 2014
www.ti.com.cn
6.8 ADS7251 Timing Characteristics
PARAMETER
TEST CONDITIONS
fCLK = max
MIN
TYP
MAX
UNIT
kSPS
MHz
ns
fTHROUGHPUT Throughput
2000
32
fCLK
CLOCK frequency
CLOCK period
CLOCK high time
CLOCK low time
Conversion time
Acquisition time
CS high time
fTHROUGHPUT = max
fTHROUGHPUT = max
tCLK
31.25
0.45
0.45
tPH_CK
tPL_CK
tCONV
0.55
0.55
tCLK
tCLK
ns
tSU_CSCK + 12 tCLK
tACQ
fCLK = max
75
30
ns
tPH_CS
tD_CKDO
tDV_CSDO
tD_CKCS
tDZ_CSDO
tSU_CSCK
ns
SCLK rising edge to (next) data valid
15
10
ns
CS falling to data enable
ns
Delay time
Last SCLK rising to CS rising
CS rising to DOUT going to 3-state
5
ns
10
ns
Setup time CS falling to SCLK falling
15
ns
Figure 1 shows the details of the serial interface between the ADS7251 and the digital host controller.
Sample
N + 1
Sample
N
tTHROUGHPUT
tCONV
tACQ
tPH_CS
CS
tSCLK
tSU_CSCK
tPH_CK
tPL_CK
tD_CKCS
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
tD_CKDO
tDV_CSDO
tDZ_CSDO
ChA ChA ChA ChA ChA ChA ChA ChA
D11 D10 D9 D8 D7 D6 D5 D4
ChA ChA ChA ChA
D3 D2 D1 D0
0
0
0
SDO-A
SDO-B
Data From Sample N
ChB ChB ChB ChB ChB ChB ChB ChB
ChB ChB ChB ChB
D3 D2 D1 D0
0
D11 D10 D9 D8 D7 D6 D5 D4
Figure 1. ADS7251 Serial Interface Timing Diagram
8
Copyright © 2014, Texas Instruments Incorporated
ADS7251, ADS7851
www.ti.com.cn
ZHCSCB7A –JANUARY 2014–REVISED APRIL 2014
6.9 ADS7851 Timing Characteristics
PARAMETER
TEST CONDITIONS
fCLK = max
MIN
TYP
MAX
1500
27
UNIT
kSPS
MHz
ns
fTHROUGHPUT Sample taken to data read
fCLK
CLOCK frequency
CLOCK period
CLOCK high time
CLOCK low time
Conversion time
Acquisition time
CS high time
fTHROUGHPUT = max
fTHROUGHPUT = max
tCLK
37
0.45
0.45
tPH_CK
tPL_CK
tCONV
0.55
0.55
tCLK
tCLK
ns
tSU_CSCK + 14 tCLK
tACQ
fCLK = max
90
30
ns
tPH_CS
tD_CKDO
tDV_CSDO
tD_CKCS
tDZ_CSDO
tSU_CSCK
ns
SCLK rising edge to (next) data valid
15
10
ns
CS falling to data enable
ns
Delay time
Last SCLK rising to CS rising
CS rising to DOUT going to 3-state
5
ns
10
ns
Setup time CS falling to SCLK falling
15
ns
Figure 2 shows the details of the serial interface between the ADS7851 and the digital host controller.
Sample
N + 1
Sample
N
tTHROUGHPUT
tCONV
tACQ
tPH_CS
CS
tSU_CSCK
2
tPH_CK
tPL_CK
10
tSCLK
14
tD_CKCS
SCLK
1
3
4
5
6
7
8
9
11
12
13
15
16
tD_CKDO
tDV_CSDO
0
tDZ_CSDO
ChA ChA ChA ChA ChA ChA ChA ChA ChA ChA
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4
ChA ChA ChA ChA
D3 D2 D1 D0
0
0
SDO-A
SDO-B
Data From Sample N
ChB ChB ChB ChB ChB ChB ChB ChB ChB ChB
ChB ChB ChB ChB
D3 D2 D1 D0
0
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4
Figure 2. ADS7851 Serial Interface Timing Diagram
Copyright © 2014, Texas Instruments Incorporated
9
ADS7251, ADS7851
ZHCSCB7A –JANUARY 2014–REVISED APRIL 2014
www.ti.com.cn
6.10 Typical Characteristics: ADS7251
At TA = +25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
0
75
-20
74.5
-40
74
-60
73.5
-80
73
-100
72.5
-120
72
71.5
71
-140
-160
-180
0
200
400
600
800
1000
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (oC)
C00
C00
Input Frequency
fIN = 500 kHz
fIN = 10 kHz
Figure 3. Typical FFT for 500-kHz Input
Figure 4. SNR vs Device Temperature
75
74.5
74
-87
-88
-89
-90
-91
-92
-93
-94
-95
73.5
73
72.5
72
71.5
71
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (oC)
Free-Air Temperature (oC)
C00
C00
fIN = 10 kHz
fIN = 10 kHz
Figure 5. SINAD vs Device Temperature
Figure 6. THD vs Device Temperature
75
74
73
72
71
75
74
73
72
71
0
100
200
300
400
500
0
100
200
300
400
500
Input Frequency (kHz)
C00
C00
Input Frequency (kHz)
fIN = 10 kHz
Figure 7. SNR vs Input Frequency
Figure 8. SINAD vs Input Frequency
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Typical Characteristics: ADS7251 (continued)
At TA = +25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
-85
-87
-89
-91
-93
-95
-97
100
80
60
40
20
0
0
100
200
300
400
500
2046
2047
2048
2049
2050
C00
C01
Input Frequency (kHz)
ADC Output Code
VIN-DIFF = 0 V
65536 Data Points
Figure 9. THD vs Input Frequency
Figure 10. DC Histogram
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
0
512 1024 1536 2048 2560 3072 3584 4096
ADC Output Code
0
512 1024 1536 2048 2560 3072 3584 4096
C01
C01
ADC Output Code
Figure 11. Typical DNL
Figure 12. Typical INL
1
0.75
0.5
1
0.75
0.5
0.25
0
0.25
0
-0.25
-0.5
-0.75
-1
-0.25
-0.5
-0.75
-1
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (oC)
Free-Air Temperature (oC)
C01
C01
Figure 13. DNL vs Device Temperature
Figure 14. INL vs Device Temperature
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Typical Characteristics: ADS7251 (continued)
At TA = +25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
1
0.75
0.5
0.1
0.075
0.05
0.25
0
0.025
0
-0.25
-0.5
-0.75
-1
-0.025
-0.05
-0.075
-0.1
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (oC)
Free-Air Temperature (oC)
C01
C01
Figure 15. Offset Error vs Device Temperature
Figure 16. Gain Error vs Device Temperature
12
11.75
11.5
11.25
11
12
11
10
9
8
10.75
10.5
10.25
10
7
6
5
4
-40 -25 -10
5
20 35 50 65 80 95 110 125
0
500
1000
Throughput (kSPS)
1500
2000
Free-Air Temperature (oC)
C02
C02
Figure 17. IAVDD vs Device Temperature
Figure 18. IAVDD vs Throughput
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6.11 Typical Characteristics: ADS7851
At TA = +25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
0
-20
85
84.5
84
-40
-60
83.5
83
-80
-100
-120
-140
-160
-180
-200
82.5
82
81.5
81
0
150
300
450
600
750
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (oC)
Input Frequency (kHz)
C02
C02
fIN = 500 kHz
fIN = 10 kHz
Figure 19. Typical FFT for 500-kHz Input
Figure 20. SNR vs Device Temperature
-91
-91.5
-92
85
84.5
84
-92.5
-93
83.5
83
-93.5
-94
82.5
82
-94.5
-95
81.5
81
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (oC)
Free-Air Temperature (oC)
C02
C02
fIN = 10 kHz
fIN = 10 kHz
Figure 21. SINAD vs Device Temperature
Figure 22. THD vs Device Temperature
84
83.5
83
85
84.5
84
82.5
82
83.5
83
81.5
81
82.5
82
80.5
80
81.5
81
0
100
200
300
400
500
0
100
200
300
400
500
C02
C02
Input Frequency (kHz)
Input Frequency (kHz)
fIN = 10 kHz
Figure 23. SNR vs Input Frequency
Figure 24. SINAD vs Input Frequency
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Typical Characteristics: ADS7851 (continued)
At TA = +25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
-86
100
-87
80
-88
-89
60
-90
40
20
0
-91
-92
-93
-94
0
100
200
300
400
500
8190
8191
8192
ADC Output Code
8193
8194
8195
8196
Input Frequency (kHz)
C03
C03
VIN-DIFF = 0 V
65536 Data Points
Figure 25. THD vs Input Frequency
Figure 26. DC Histogram
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
0
0
4096
8192
12288
16384
4096
8192
12288
16384
ADC Output Code
C03
C03
ADC Output Code
Figure 27. Typical DNL
Figure 28. Typical INL
2
1.5
1
2
1.5
1
0.5
0
0.5
0
-0.5
-1
-0.5
-1
-1.5
-2
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (oC)
Free-Air Temperature (oC)
C03
C04
Figure 29. DNL vs Device Temperature
Figure 30. INL vs Device Temperature
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Typical Characteristics: ADS7851 (continued)
At TA = +25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
0.1
1
0.075
0.75
0.05
0.5
0.025
0.25
0
0
-0.025
-0.25
-0.05
-0.5
-0.075
-0.75
-0.1
-1
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (oC)
Free-Air Temperature (oC)
C03
C03
Figure 31. Offset Error vs Device Temperature
Figure 32. Gain Error vs Device Temperature
10
9
12
11.5
11
8
10.5
10
7
9.5
9
6
5
8.5
8
4
0
500
1000
1500
-40 -25 -10
5
20 35 50 65 80 95 110 125
Free-Air Temperature (oC)
Throughtput (kSPS)
C04
C04
Figure 33. IAVDD vs Device Temperature
Figure 34. IAVDD vs Throughput
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6.12 Typical Characteristics: Common
At TA = +25°C, AVDD = 5 V, DVDD = 3.3 V, and VREF = 2.5 V (internal), unless otherwise noted.
2.502
30
2.5015
25
2.501
20
2.5005
15
2.5
10
2.4995
5
2.499
0
2.4985
-5
2.498
-10
2.49
-40 -25 -10
5
20 35 50 65 80 95 110 125
2.495
2.5
2.505
Voltage (V)
2.51
2.515
2.52
C03
Free-Air Temperature (oC)
C03
Rout = 0.75 Ω Typ
Figure 35. Reference Output vs
Device Temperature
Figure 36. Internal Reference:
Output Current vs Output Voltage
110
100
90
80
70
60
50
40
0
100
200
300
400
500
Input Frequency (kHz)
C04
Figure 37. CMRR vs Input Frequency
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7 Detailed Description
7.1 Overview
The ADS7251 and ADS7851 are pin-compatible, dual, simultaneous-sampling, analog-to-digital converters
(ADCs). Each device features two independent internal voltage references and supports fully-differential input
signals with the input common-mode on each input pin equal to the reference voltage. The full-scale input signal
on each input pin is equal to twice the reference voltage. The devices provide a simple, serial interface to the
host controller and operate over a wide range of digital power supplies.
7.2 Functional Block Diagram
REF_A
Comparator
S/H
CDAC
SAR
SAR
ADC_A
ADC_B
Serial
Interface
CDAC
S/H
Comparator
REF_B
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7.3 Feature Description
7.3.1 Reference
The device has two simultaneous sampling ADCs (ADC_A and ADC_B) and two independent internal reference
sources (INTREF_A and INTREF_B). INTREF_A outputs voltage VREF_A on pin REFOUT_A and INTREF_B
outputs voltage VREF_B on pin REFOUT_B. As shown in Figure 38, the REFOUT_A and REFOUT_B pins must
be decoupled with the REFGND_A and REFGND_B pins, respectively, with individual 22-µF decoupling
capacitors. ADC_A operates with reference voltage VREF_A and ADC_B operates with reference voltage VREF_B
.
AINP_A
ADC_A
AINM_A
REFGND_A
REFOUT_A
22 PF
INTREF_A
REFOUT_B
INTREF_B
22 PF
REFGND_B
AINP_B
ADC_B
AINM_B
Figure 38. Reference Block Diagram
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Feature Description (continued)
7.3.2 Analog Input
The devices support fully-differential analog input signals. These inputs are sampled and converted
simultaneously by the two ADCs, ADC_A and ADC_B. Figure 39a and Figure 39b show equivalent circuits for
the ADC_A and ADC_B analog input pins, respectively.
Series resistance (RS) represents the on-state sampling switch resistance (typically 50 Ω) and CSAMPLE is the
device sampling capacitor (typically 40 pF). ADC_A samples VAINP_A and VAINM_A and converts for the difference
voltage (VAINP_A – VAINM_A). ADC_B samples VAINP_B and VAINM_B and converts for the difference voltage
(VAINP_B – VAINM_B).
AVDD
AVDD
RS CSAMPLE
RS CSAMPLE
AINP_A
AINP_B
GND
GND
AVDD
AVDD
RS CSAMPLE
RS CSAMPLE
AINM_A
AINM_B
GND
GND
a) ADC_A
b) ADC_B
Figure 39. Equivalent Circuit for the Analog Input Pins
7.3.2.1 Analog Input Full-Scale Range
The analog input full-scale range (FSR) for ADC_A and ADC_B is twice the reference voltage provided to the
particular ADC. Therefore, the FSR for ADC_A and ADC_B can be determined by Equation 1 and Equation 2,
respectively:
FSR_ADC_A = 2 × VREF_A
,
(1)
VAINP_A and VAINM_A = 0 to 2 × VREF_A
,
FSR_ADC_B = 2 × VREF_B
,
(2)
VAINP_B and VAINM_B = 0 to 2 × VREFIN_B
To use the full dynamic input range on the analog input pins, AVDD must be as shown in Equation 3, Equation 4,
and Equation 5:
AVDD ≥ 2 × VREF_A
AVDD ≥ 2 × VREF_B
4.5 V ≤ AVDD ≤ 5.5 V
(3)
(4)
(5)
7.3.2.2 Common-Mode Voltage Range
For the analog input, the devices support a common-mode voltage equal to the reference voltage provided to the
ADC. Therefore, the common-mode voltage for the ADC_A and ADC_B must be as shown in Equation 6 and
Equation 7, respectively.
VCM_A = VREF_A
VCM_B = VREF_B
(6)
(7)
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Feature Description (continued)
7.3.3 ADC Transfer Function
The device output is in twos compliment format. Device resolution for the fully-differential input can be computed
by Equation 8:
1 LSB = (4 × VREF) / (2N)
where:
•
•
VREF = VREF_A = VREF_B, and
N = 12 (ADS7251), or 14 (ADS7851).
(8)
Table 1 shows the different input voltages and the corresponding device output codes. Figure 40 shows the ideal
transfer characteristics for the device.
Table 1. Transfer Characteristics
OUTPUT CODE (Hex)
INPUT VOLTAGE
(AINP_x – AINM_x)
CODE
NFSC
NFSC + 1
MC
ADS7251
800
ADS7851
2000
< –2 × VREF
–2 × VREF + 1 LSB
–1 LSB
801
2001
FFF
3FFF
0
PLC
000
0000
> 2 × VREF – 1 LSB
PFSC
7FF
1FFF
PFSC
PLC
MC
NFSC + 1
NFSC
VIN
0
PFSR ± 1 LSB
NFSR + 1 LSB
ꢀ1 LSB
Fully-Differential Analog Input
(AINP_x ± AINM_x)
Figure 40. Ideal Transfer Characteristics
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7.4 Device Functional Modes
7.4.1 Serial Interface
The devices support a simple, SPI-compatible interface to the external digital host. The CS signal defines one
conversion and serial transfer frame. A frame starts with a CS falling edge and ends with a CS rising edge. The
SDO_A and SDO_B pins output the ADC_A and ADC_B conversion results, respectively. Figure 41 shows a
detailed timing diagram for the ADS7251.
Sample
N + 1
Sample
N
tTHROUGHPUT
tCONV
tACQ
CS
SCLK
1
0
2
3
4
5
6
7
8
9
10
11
12
13
14
ChA ChA ChA ChA ChA ChA ChA ChA
D11 D10 D9 D8 D7 D6 D5 D4
ChA ChA ChA ChA
D3 D2 D1 D0
0
0
SDO-A
SDO-B
Data From Sample N
ChB ChB ChB ChB ChB ChB ChB ChB
ChB ChB ChB ChB
0
D11 D10 D9 D8 D7 D6 D5 D4
D3
D2
D1 D0
Figure 41. ADS7251 Serial Interface Timing Diagram
Figure 42 shows a detailed timing diagram for the ADS7851.
Sample
N + 1
Sample
N
tTHROUGHPUT
tCONV
tACQ
CS
SCLK
1
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ChA ChA ChA ChA ChA ChA ChA ChA ChA ChA
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4
ChA ChA ChA ChA
D3 D2 D1 D0
0
0
SDO-A
SDO-B
Data From Sample N
ChB ChB ChB ChB ChB ChB ChB ChB ChB ChB
ChB ChB ChB ChB
D3 D2 D1 D0
0
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4
Figure 42. ADS7851 Serial Interface Timing Diagram
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Device Functional Modes (continued)
A CS falling edge brings the serial data bus out of 3-state and also outputs '0' on the SDO_A and SDO_B pins. A
minimum delay of tSU_CSCK must elapse between the CS falling edge and the first SCLK falling edge. The
subsequent clock edges are used to shift out the conversion result using the serial interface, as shown in
Table 2. The sample-and-hold circuit returns to sample mode as soon as the conversion process is over. Any
extra clock edges output a '0' on the SDO pins. A CS rising edge ends the frame and brings the serial data bus
to 3-state.
Table 2. Data Launch Edge
LAUNCH EDGE
SCLK
CS↑
DEVICE
PIN
CS↓
0
↓1
0
↓2
…
…
…
…
…
↓13
↓14
D1_A
D1_B
0
↓15
D0_A
D0_B
0
↓16
0
…
…
…
…
…
SDO-A
SDO-B
SDO-A
SDO-B
D13_A
D13_B
D11_A
D11_B
D2_A
D2_B
D0_A
D0_B
Hi-Z
Hi-Z
Hi-Z
Hi-Z
ADS7851
0
0
0
0
0
0
ADS7251
0
0
0
0
0
7.4.2 Short-Cycling Feature
For the ADS7851, a minimum of 16 SCLK rising edges must be provided between the beginning and end of the
frame to complete the 14-bit data transfer. For the ADS7251, a minimum of 14 SCLK rising edges must be
provided between the beginning and end of the frame to complete the 12-bit data transfer. As shown in
Figure 43, if CS is brought high before the expected number of SCLK rising edges are provided, the current
frame is aborted and the device starts sampling the new analog input signal. However, the output data bits
latched into the digital host before this CS rising edge are still valid data corresponding to sample N.
After aborting the current frame, CS must be kept high for tACQ to ensure minimum acquisition time is provided
for the next conversion.
Sample
N
Sample
N + 1
tACQ
CS
SCLK
1
2
3
SDO
ADS7251
0
0
0
D11 D10
Data From Sample N
D13 D12
SDO
ADS7851
0
Figure 43. Short-Cycling Feature
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8 Application and Implementation
8.1 Application Information
The two primary circuits required to maximize the performance of a high-precision, successive approximation
register (SAR), analog-to-digital converter (ADC) are the input driver and the reference driver circuits. The
ADS7851 and ADS7251 feature an internal reference designed to support device requirements. This section
details some general principles for designing the input driver circuit and provides some application circuits
designed using these devices.
8.2 Typical Application
The application circuit shown in Figure 44 is optimized for using the ADS7251 at a 2-MSPS throughput to
achieve lowest distortion and lowest noise for input signal frequencies up to 100 kHz.
1 Kꢀꢀ
1 Kꢀꢀ
AVDD
AVDD
VIN+
VCM
10 ꢀꢀ
AVDD
+
VREF
AINP
+
-
THS4521
820 pF
ADS7251
+
-
AINM
GND
10 ꢀꢀ
VIN-
1 Kꢀꢀ
1 Kꢀꢀ
AD7251 2 MSPS
32MHz SCLK
INPUT DRIVER
Figure 44. ADS7251 DAQ Circuit: Maximum SINAD for Input Signal Frequencies up to 100 kHz
The application circuit shown in Figure 45 is optimized for using the ADS7851 at a 1.5-MSPS throughput to
achieve lowest distortion and lowest noise for input signal frequencies up to 100 kHz.
1 Kꢀꢀ
1 Kꢀꢀ
AVDD
AVDD
VIN+
VCM
10 ꢀꢀ
AVDD
+
VREF
AINP
+
-
THS4521
820 pF
ADS7851
+
-
AINM
GND
10 ꢀꢀ
VIN-
1 Kꢀꢀ
1 Kꢀꢀ
AD7851 1.5 MSPS
27MHz SCLK
INPUT DRIVER
Figure 45. ADS7851 DAQ Circuit: Maximum SINAD for Input Signal Frequencies up to 100 kHz
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Typical Application (continued)
8.2.1 Design Requirements
For the ADS7251, design an input driver and reference driver circuit to achieve > 71-dB SNR and < –90-dB THD
at input frequencies of 10 kHz and 100 kHz.
For the ADS7851, design an input driver and reference driver circuit to achieve > 81-dB SNR and < –90-dB THD
at input frequencies of 10 kHz and 100 kHz.
8.2.2 Detailed Design Procedure
The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and an
antialiasing filter. Careful design of the front-end circuit is critical to meet the linearity and noise performance of a
high-precision ADC.
8.2.2.1 Input Amplifier Selection
Selection criteria for the input amplifiers is highly dependent on the input signal type and the performance goals
of the data acquisition system. Some key amplifier specifications to consider while selecting an appropriate
amplifier to drive the inputs of the ADC are:
•
Small-signal bandwidth. Select the small-signal bandwidth of the input amplifiers to be as high as possible
after meeting the power budget of the system. Higher bandwidth reduces the closed-loop output impedance
of the amplifier, thus allowing the amplifier to more easily drive the low cutoff frequency RC filter at the ADC
inputs. Higher bandwidth also minimizes the harmonic distortion at higher input frequencies. In order to
maintain the overall stability of the input driver circuit, the amplifier bandwidth should be selected as
described in Equation 9:
§
¨
¨
©
·
¸
¸
¹
1
Unity ꢀ Gain Bandwidth t 4u
2SuRFLT uCFLT
(9)
•
Noise. Noise contribution of the front-end amplifiers should be as low as possible to prevent any degradation
in SNR performance of the system. As a rule of thumb, to ensure that the noise performance of the data
acquisition system is not limited by the front-end circuit, the total noise contribution from the front-end circuit
should be kept below 20% of the input-referred noise of the ADC. Noise from the input driver circuit is
bandlimited by designing a low cutoff frequency RC filter, as explained in Equation 10.
2
SNR
ꢀ
dB
ꢁ
§
¨
·
¸
V
§
¨
·
¸
ꢂ
1
_ AMP_PP
S
2
1
5
VREF
2
20
ꢃ en2_RMS
u
u fꢂ3dB
d
u
u10
f
©
¹
NG u 2 u
¨
¨
¸
¸
6.6
©
¹
where:
•
•
•
•
V1 / f_AMP_PP is the peak-to-peak flicker noise in µVRMS
,
en_RMS is the amplifier broadband noise density in nV/√Hz,
f–3dB is the 3-dB bandwidth of the RC filter, and
NG is the noise gain of the front-end circuit, which is equal to '1' in a buffer configuration.
(10)
•
•
Distortion. Both the ADC and the input driver introduce nonlinearity in a data acquisition block. As a rule of
thumb, to ensure that the distortion performance of the data acquisition system is not limited by the front-end
circuit, the distortion of the input driver should be at least 10 dB lower than the distortion of the ADC, as
shown in Equation 11.
THDAMP d THDADC ꢂ 10
dB
(11)
Settling Time. For dc signals with fast transients that are common in a multiplexed application, the input signal
must settle to the desired accuracy at the inputs of the ADC during the acquisition time window. This
condition is critical to maintain the overall linearity performance of the ADC. Typically, the amplifier data
sheets specify the output settling performance only up to 0.1% to 0.001%, which may not be sufficient for the
desired accuracy. Therefore, the settling behavior of the input driver should always be verified by TINA™-
SPICE simulations before selecting the amplifier.
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ZHCSCB7A –JANUARY 2014–REVISED APRIL 2014
Typical Application (continued)
The distortion resulting from variation in the common-mode signal is eliminated by using a fully-differential
amplifier (FDA) in an inverting gain configuration that establishes a fixed common-mode level at the ADC input.
This configuration also eliminates the requirement of rail-to-rail swing at the amplifier input. The low-power
THS4521, used as an input driver, provides exceptional ac performance because of its extremely low-distortion
and high-bandwidth specifications. The device REFOUT_x pin can be directly connected to the VOCM pin of the
THS4521 to set the output common-mode voltage to 2.5 V, as required by the ADC.
8.2.2.2 Antialiasing Filter
Converting analog-to-digital signals requires sampling an input signal at a constant rate. Any higher frequency
content in the input signal beyond half the sampling frequency is digitized and folded back into the low-frequency
spectrum. This process is called aliasing. Therefore, an analog, antialiasing filter must be used to remove the
harmonic content from the input signal before being sampled by the ADC. An antialiasing filter is designed as a
low-pass, RC filter, for which the 3-dB bandwidth is optimized based on specific application requirements (as
shown in Figure 46). For dc signals with fast transients (including multiplexed input signals), a high-bandwidth
filter is designed to allow accurately settling the signal at the ADC inputs during the small acquisition time
window. For ac signals, the filter bandwidth should be kept low to band-limit the noise fed into the ADC input,
thereby increasing the signal-to-noise ratio (SNR) of the system.
Besides filtering the noise from the front-end drive circuitry, the RC filter also helps attenuate the sampling
charge injection from the switched-capacitor input stage of the ADC. A filter capacitor, CFLT, is connected across
the ADC inputs. This capacitor helps reduce the sampling charge injection and provides a charge bucket to
quickly charge the internal sample-and-hold capacitors during the acquisition process. As a rule of thumb, the
value of this capacitor should be at least 10 times the specified value of the ADC sampling capacitance. For
these devices, the input sampling capacitance is equal to 40 pF. Thus, the value of CFLT should be greater than
400 pF. The capacitor should be a COG- or NPO-type because these capacitor types have a high-Q, low-
temperature coefficient, and stable electrical characteristics under varying voltages, frequency, and time.
Note that driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier
marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of
the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a
result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance,
input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability
and distortion of the design. For these devices, TI recommends limiting the value of RFLT to a maximum of 22 Ω
in order to avoid any significant degradation in linearity performance. The tolerance of the selected resistors can
be chosen as 1% because the use of a differential capacitor at the input balances the effects resulting from any
resistor mismatch.
RFLT ꢀ22 ꢀꢀ
AINP
1
fꢃ3dB
ADS7851
ADS7251
CFLT ꢀꢀ400 pF
RFLT ꢀ22 ꢀꢀ
2S u
ꢀ
RFLT ꢂ RFLT u CFLT
ꢁ
AINM
GND
Figure 46. Antialiasing Filter
The input amplifier bandwidth should be much higher than the cutoff frequency of the antialiasing filter. TI
strongly recommends performing a SPICE simulation to confirm that the amplifier has more than 40° phase
margin with the selected filter. Simulation is critical because even with high-bandwidth amplifiers, some amplifiers
might require more bandwidth than others to drive similar filters. If an amplifier has less than a 40° phase margin
with 22-Ω resistors, using a different amplifier with higher bandwidth or reducing the filter cutoff frequency with a
larger differential capacitor is advisable.
In addition, the components of the antialiasing filter are such that the noise from the front-end circuit is kept low
without adding distortion to the input signal.
Copyright © 2014, Texas Instruments Incorporated
25
ADS7251, ADS7851
ZHCSCB7A –JANUARY 2014–REVISED APRIL 2014
www.ti.com.cn
Typical Application (continued)
8.2.3 Application Curves
Figure 47 shows an FFT plot for the ADS7251 with the circuit shown in Figure 44 and an input frequency of
10 kHz. Figure 48 shows an FFT plot for the ADS7251 with the same circuit configuration but for an input
frequency of 100 kHz.
0
-20
0
-20
AVDD = 5 V
TA = 25oC
AVDD = 5 V
TA = 25oC
fIN = 10 kHz
SNR = 73 dB
THD = -90 dB
fIN = 100 kHz
SNR = 72 dB
THD = -91 dB
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
0
200
400
600
800
1000
0
200
400
600
800
1000
Input Frequency (kHz)
C10
C10
Input Frequency (kHz)
Figure 47. Test Results for ADS7251 with a 10-kHz Input
Figure 48. Test Results for ADS7251 with a 100-kHz Input
Figure 49 shows an FFT plot for the ADS7851 with the circuit shown in Figure 45 and an input frequency of
10 kHz. Figure 50 shows an FFT plot for the ADS7251 with the same circuit configuration but for an input
frequency of 100 kHz.
0
-20
0
-20
AVDD = 5 V
TA = 25oC
AVDD = 5 V
TA = 25oC
fIN = 10 kHz
SNR = 82.3 dB
THD = -91 dB
fIN = 100 kHz
SNR = 82.3 dB
THD = -93 dB
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
0
150
300
450
600
750
0
150
300
450
600
750
C10
C10
Input Frequency (kHz)
Input Frequency (kHz)
Figure 49. Test Results with a 10-kHz Input
Figure 50. Test Results with a 100-kHz Input
26
Copyright © 2014, Texas Instruments Incorporated
ADS7251, ADS7851
www.ti.com.cn
ZHCSCB7A –JANUARY 2014–REVISED APRIL 2014
9 Power Supply Recommendations
The devices have two separate power supplies: AVDD and DVDD. The device operates on AVDD; DVDD is
used for the interface circuits. AVDD and DVDD can be independently set to any value within the permissible
ranges.
The AVDD supply voltage value defines the permissible voltage swing on the analog input pins. To avoid
saturation of output codes, and to use the full dynamic range on the analog input pins, AVDD must be set as
shown in Equation 12, Equation 13, and Equation 14:
AVDD ≥ 2 × VREF_A
AVDD ≥ 2 × VREF_B
4.75 V ≤ AVDD ≤ 5.25 V
(12)
(13)
(14)
Decouple the AVDD and DVDD pins with the GND pin using individual 10-µF decoupling capacitors, as shown in
Figure 51.
AVDD
AVDD (pin 14)
GND (pin 13)
DVDD (pin 7)
10 PF
10 PF
DVDD
Figure 51. Power-Supply Decoupling
Copyright © 2014, Texas Instruments Incorporated
27
ADS7251, ADS7851
ZHCSCB7A –JANUARY 2014–REVISED APRIL 2014
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
Figure 52 shows a board layout example for the ADS7251 and ADS7851. Use a ground plane underneath the
device and partition the PCB into analog and digital sections. Avoid crossing digital lines with the analog signal
path and keep the analog input signals and the reference input signals away from noise sources. As shown in
Figure 52, the analog input and reference signals are routed on the left side of the board and the digital
connections are routed on the right side of the device.
The power sources to the device must be clean and well-bypassed. Use 10-μF, ceramic bypass capacitors in
close proximity to the analog (AVDD) and digital (DVDD) power-supply pins. Avoid placing vias between the
AVDD and DVDD pins and the bypass capacitors. Connect all ground pins to the ground plane using short, low-
impedance paths.
The REFOUT-A and REFOUT-B reference outputs are bypassed with 10-μF, X7R-grade ceramic capacitors
(CREF-x). Place the reference bypass capacitors as close as possible to the reference REFOUT-x pins and
connect the bypass capacitors using short, low-inductance connections. Avoid placing vias between the
REFOUT-x pins and the bypass capacitors. Small 0.1-Ω to 0.2-Ω resistors (RREF-x) are used in series with the
reference bypass capacitors to improve stability.
The fly-wheel RC filters are placed immediately next to the input pins. Among ceramic surface-mount capacitors,
COG (NPO) ceramic capacitors provide the best capacitance precision. The type of dielectric used in COG
(NPO) ceramic capacitors provides the most stable electrical properties over voltage, frequency, and temperature
changes. Figure 52 shows CIN-A and CIN-B filter capacitors placed across the analog input pins of the device.
10.2 Layout Example
AVDD
GND
CREF-A
CIN-A
CAVDD
GND
SDO-A
SDO-B
SCLK
/CS
REFOUT-A
REFGND-A
REFGND-B
GND
GND
GND
REFOUT-B
GND
CDVDD
CREF-B
CIN-B
DVDD
GND
GND
Figure 52. Example Layout for the ADS7251 and ADS7851
28
Copyright © 2014, Texas Instruments Incorporated
ADS7251, ADS7851
www.ti.com.cn
ZHCSCB7A –JANUARY 2014–REVISED APRIL 2014
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档ꢀ
相关文档如下：
•
THS4521 数据表，SBOS458
11.2 相关链接
以下表格列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件，以及样片与购买的快速访问。
Table 3. 相关链接
部件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
ADS7251
ADS7851
11.3 Trademarks
TINA is a trademark of Texas Instruments Inc..
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
12 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
Copyright © 2014, Texas Instruments Incorporated
29
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS7251IRTER
ADS7251IRTET
ADS7851IRTER
ADS7851IRTET
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
WQFN
RTE
RTE
RTE
RTE
16
16
16
16
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
7251
7251
7851
7851
NIPDAU
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Nov-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS7251IRTET
ADS7851IRTER
ADS7851IRTET
WQFN
WQFN
WQFN
RTE
RTE
RTE
16
16
16
250
3000
250
180.0
330.0
180.0
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
1.1
1.1
1.1
8.0
8.0
8.0
12.0
12.0
12.0
Q2
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Nov-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS7251IRTET
ADS7851IRTER
ADS7851IRTET
WQFN
WQFN
WQFN
RTE
RTE
RTE
16
16
16
250
3000
250
210.0
367.0
210.0
185.0
367.0
185.0
35.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RTE 16
3 x 3, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225944/A
www.ti.com
PACKAGE OUTLINE
RTE0016D
WQFN - 0.8 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.15
2.85
A
B
PIN 1 INDEX AREA
3.15
2.85
C
0.8
0.7
SEATING PLANE
0.08 C
0.05
0.00
2X 1.5
SYMM
(0.2) TYP
5
8
EXPOSED
THERMAL PAD
4
9
SYMM
17
2X 1.5
0.8 0.1
12X 0.5
1
12
PIN 1 ID
0.30
0.18
16X
16
13
0.5
0.3
0.1
C A B
16X
0.05
4219118/A 11/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTE0016D
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
0.8)
SYMM
SEE SOLDER MASK
DETAIL
16
13
16X (0.6)
12
16X (0.24)
1
17
SYMM
(2.8)
12X (0.5)
(R0.05) TYP
4
9
(
0.2) TYP
VIA
5
8
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219118/A 11/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTE0016D
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
0.76)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
12X (0.5)
(2.8)
9
4
(R0.05) TYP
5
8
SYMM
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 17
90% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219118/A 11/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
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