ADS774TE [TI]
1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP28;
| 型号： | ADS774TE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP28 转换器 微处理器 |
| 文件： | 总23页 (文件大小：609K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS774H
www.ti.com ................................................................................................................................................................................................ SBAS443–AUGUST 2009
Microprocessor-Compatible Sampling
CMOS ANALOG-TO-DIGITAL CONVERTER
1
FEATURES
DESCRIPTION
2
•
Drop-In Replacement for the ADS774
The ADS774H is a 12-bit, successive-approximation
analog-to-digital converter (ADC) that uses an
innovative capacitor array (CDAC) implemented in
low-power CMOS technology. This device is a drop-in
replacement for the ADS774, with internal sampling,
much lower power consumption, and the ability to
operate from a single +5V supply.
•
•
•
Complete Sampling ADC with Reference,
Clock, and Microprocessor Interface
Fast Acquisition and Conversion: 8.5µs Max
Over Temperature
Eliminates External Sample/Hold in Most
Applications
The ADS774H is complete with an internal clock,
microprocessor interface, three-state outputs, and
internal scaling resistors for input ranges of 0V to
+10V, 0V to +20V, ±5V, or ±10V. The maximum
throughput time is 8.5µs over the full operating
temperature range, including both acquisition and
conversion.
•
•
•
•
Ensured AC and DC Performance
Single +5V Supply Operation
Low Power: 120mW Max
Package Options: SO, 0.6in and 0.3in DIPs(1)
APPLICATIONS
Complete user control over the internal sampling
function facilitates elimination of external sample/hold
amplifiers in most existing designs.
•
•
•
•
•
•
•
Medical Instrumentation
Data Acquisition Systems
Robotics
Industrial Control
Test Equipment
The ADS774H requires +5V, with –15V optional. No
+15V supply is required. Packages include a 28-pin
SO, and 0.3in-wide or 0.6in-wide 28-pin DIPs(1).
Digital Signal Processing
DSP Servo Control
(1) DIP-28 package is product preview.
Status
Control
Inputs
Control Logic
Bipolar
Offset
CDAC
Clock
Parallel
Data
Output
Successive
Approximation
Register
20V Range
10V Range
2.5V Reference
Input
Comparator
2.5V Reference
Output
2.5V
Reference
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
ADS774H
SBAS443–AUGUST 2009 ................................................................................................................................................................................................ www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
LINEARITY
ERROR
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
SINAD(2)
NT
–40°C to +85°C
–40°C to +85°C
ADS774HIBNT
ADS774HIBNTD
ADS774HIBDW
ADS774HIBEDWR
ADS774HINTD
ADS774HINT
Rail, 13
Rail, 13
70dB
±1/2 LSB
±1/2 LSB
±1LSB
DIP-28(3)
NTD
ADS774HIB
(High-Grade)
Tape and Reel, 28
Tape and Reel, 1000
Rail, 13
70dB
68dB
68dB
SO-28
DW
–40°C to +85°C
NT
–40°C to +85°C
–40°C to +85°C
DIP-28(3)
SO-28
NTD
Rail, 13
ADS774HI
(Standard-Grade)
ADS774HIDW
Tape and Reel, 28
Tape and Reel, 1000
±1LSB
DW
–40°C to +85°C
ADS774HIDWR
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) SINAD is Signal-to-(Noise + Distortion) expressed in dB.
(3) DIP-28 package is product preview.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range (unless otherwise noted).
ADS774H
+VDD to –16.5
0 to +7
UNIT
V
VEE to Digital Common
VDD to Digital Common
V
Analog Common to Digital Common
±1
V
Control inputs (CE, CS, A0, 12/8, R/C) to Digital Common
Analog inputs (REF IN, Bipolar Offset, 10V Range) to Analog Common
20V Range to Analog Common
–0.5 to VDD +0.5
±16.5
V
V
±24
V
Indefinite short to common,
momentary short to VDD
Ref Out
Maximum junction temperature
Power dissipation
+165
1000
+300
°C
mW
°C
Lead temperature (soldering, 10s)
DIP-28
SO-28
Thermal impedance,
θJA
100
°C/W
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2
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ADS774H
www.ti.com ................................................................................................................................................................................................ SBAS443–AUGUST 2009
ELECTRICAL CHARACTERISTICS
All specifications at TA = TMIN to TMAX, VDD = +5V, VEE = –15V to +5V, sampling frequency of 117kHz, and fIN = 10kHz, unless otherwise
noted.
ADS774HI
TYP
ADS774HIB(1)
TYP
PARAMETER
SYSTEM PERFORMANCE
Resolution
CONDITIONS
MIN
MAX
MIN
MAX
UNIT
12
12
Bits
ANALOG INPUTS
0 to +10,
0 to +20
0 to +10,
0 to +20
Unipolar
Bipolar
V
Voltage range
Impedance
±5, ±10
12
±5, ±10
12
V
0V to +10V, ±5V
±10V, 0V to +20V
8.5
35
8.5
35
kΩ
kΩ
50
50
DIGITAL INPUTS (CE, CS, R/C, A0, 12/8)
Logic 1
+2.0
–0.5
–5
+5.5
+0.8
+5
+2.0
–0.5
–5
+5.5
+0.8
+5
V
V
Voltages
Logic 0
Current
0.1
5
0.1
5
µA
pF
Capacitance
DC ACCURACY
At +25°C
±1
±1
±1/2
±1/2
±2
LSB
LSB
LSB
LSB
LSB
LSB
Linearity error
(2)
TMIN to TMAX
Unipolar offset error
Unipolar offset
At +25°C (adjustable to zero)
±2
(2)
TMIN to TMAX
±4
±3
Bipolar offset error
Bipolar offset
At +25°C (adjustable to zero)
±10
±12
±0.25
±0.47
±4
(2)
TMIN to TMAX
±5
At +25°C (adjustable to zero)
±0.25 % of FS(4)
±0.37 % of FS
Bits
Full-scale calibration error(3)
(2)
TMIN to TMAX
At +25°C
12
12
12
12
No missing codes resolution
(2)
TMIN to TMAX
Bits
AC ACCURACY(5)
Spurious free dynamic range
Total harmonic distortion
Signal-to-noise ratio
73
78
–77
72
76
78
–77
72
dB
–72
–75
dB
dB
dB
dB
69
68
71
70
Signal-to-(noise + distortion) ratio
Intermodulation distortion
TEMPERATURE COEFFICIENTS(6)
Unipolar offset
71
71
fIN1 = 20kHz, fIN2 = 23kHz
–75
–75
±1
±2
±1
±2
ppm/°C
ppm/°C
ppm/°C
Bipolar offset
Full-scale calibration
±12
±12
POWER-SUPPLY SENSITIVITY
Change in full-scale calibration(7)
+4.75V < VDD < +5.25V
±1/2
±1/2
LSB
CONVERSION TIME (Including Acquisition Time)
8-bit cycle
tAQ + tC at +25°C
5.5
7.5
8
5.9
8
5.5
7.5
8
5.9
8
µs
µs
µs
12-bit cycle
12-bit cycle, TMIN to TMAX
8.5
8.5
(1) Shaded cells indicate different specifications from standard grade version of device.
(2) Maximum error at TMIN and TMAX
(3) With fixed 50Ω resistor from REF OUT to REF IN. This parameter is also adjustable to zero at +25°C.
.
(4) FS in this parametric table means Full-Scale Range. That is, for a ±10V input range, FS = 20V; for a 0V to +10V range, FS = 10V.
(5) Based on VEE = +5V, which is the Control Mode; see the S/H Control Mode and ADC774 Emulation Mode section.
(6) Using internal reference.
(7) This parameter is the worst-case change in accuracy from accuracy with a +5V supply.
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ADS774H
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ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = TMIN to TMAX, VDD = +5V, VEE = –15V to +5V, sampling frequency of 117kHz, and fIN = 10kHz, unless otherwise
noted.
ADS774HI
TYP
ADS774HIB(1)
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNIT
SAMPLING DYNAMICS
At +25°C
125
117
125
117
kHz
kHz
Sampling rate
TMIN to TMAX
with VEE = +5V
20
1.6
300
10
20
1.6
300
10
ns
Aperture delay, tAP
Aperture uncertainty (jitter)
with VEE = 0V to –15V
with VEE = +5V
µs
ps RMS
ns RMS
with VEE = 0V to –15V
Settling time to 0.01% for
full-scale input change
1.4
1.4
µs
DIGITAL OUTPUTS (DB11 to DB0, STATUS)
Unipolar
Unipolar straight binary (USB)
Bipolar offset binary (BOB)
Unipolar straight binary (USB)
Bipolar offset binary (BOB)
Output codes
Bipolar
Logic 0 (ISINK = 1.6mA)
+0.4
+0.4
V
V
Logic levels
Logic 1 (ISOURCE = 500µA)
+2.4
–5
+2.4
–5
Leakage, data bits only, high-Z
state
0.1
5
+5
0.1
5
+5
µA
Capacitance
pF
INTERNAL REFERENCE VOLTAGE
Voltage
+2.4
0.5
+2.5
+2.6
+2.4
0.5
+2.5
+2.6
V
Source current available for
external loads
mA
POWER-SUPPLY REQUIREMENTS
(8)
VEE
–16.5
+4.5
VDD
–16.5
+4.5
VDD
V
V
Voltage
VDD
+5.5
+5.5
(8)
IEE
VEE = –15V
–1
+15
75
–1
+15
75
mA
mA
mW
Current
IDD
+24
120
+24
120
Power dissipation, tMIN to tMAX
TEMPERATURE RANGE
Specified
VEE = 0V to +5V
–40
–40
–65
+85
+85
–40
–40
–65
+85
+85
°C
°C
°C
Operating
Storage
+150
+150
(8) VEE is optional, and is only used to set the mode for the internal sample/hold. When VEE = –15V, IEE = –1mA typ; when VEE = 0V, IEE
±5mA typ; when VEE = +5V, IEE = +167mA typ.
=
4
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ADS774H
www.ti.com ................................................................................................................................................................................................ SBAS443–AUGUST 2009
TIMING DIAGRAMS
tHRL
R/C
R/C
tHRH
tDS
tDS
tCONVERSION
STATUS
tDDR
tHDR
STATUS
tCONVERSION
tHDR
tHS
High-Z
High-Z-State
Data Valid
DB11-DB0
High-Z-State
DB11-DB0
Data Valid
Data Valid
Figure 2. R/C Pulse High: Outputs Enabled Only
when R/C is High
Figure 1. R/C Pulse Low: Outputs Enabled After
Conversion
tHEC
CE
tSSC
CS
tHSC
R/C
A0
tSRC
tHRC
tSAC
tHAC
tDSC
Status
(1)
tX
High Impedance
DB11-DB0
NOTE (1): tX includes tAQ and tC in ADC774 Emulation Mode,
tC only in S/H Control Mode.
Figure 3. Conversion Cycle Timing
CE
tSSR
tHSR
CS
tHRR
R/C
A0
tSRR
tSAR
tHAR
Status
tHS
tHD
High-Z
tDD
DB11-DB0
Data Valid
tHL
Figure 4. Read Cycle Timing
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ADS774H
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TIMING REQUIREMENTS: Stand-Alone Mode
ADS774H
SYMBOL
tHRL
PARAMETER
MIN
TYP
MAX
UNIT
ns
Low R/C pulse width
STS delay from R/C
Data valid After R/C low
High R/C pulse width
Data access time
25
tDS
200
ns
tHDR
25
ns
tHRH
100
ns
tDDR
150
ns
TIMING REQUIREMENTS: Fully-Controlled Operation (Convert Mode)
ADS774H
SYMBOL
tDSC
PARAMETER
MIN
TYP
60
30
20
20
0
MAX
UNIT
ns
STS delay from CE
CE pulse width
200
tHEC
50
50
50
50
50
0
ns
tSSC
CS to CE setup
ns
tHSC
CS low during CE high
R/C to CE setup
ns
tSRC
ns
tHRC
R/C low during CE high
A0 to CE setup
20
ns
tSAC
ns
tHAC
A0 valid during CE high
50
20
ns
TIMING REQUIREMENTS: Fully-Controlled Operation (Read Mode)
ADS774H
SYMBOL
tDD
PARAMETER
MIN
TYP
75
MAX
UNIT
ns
Access time from CE
Data valid after CE low
Output float delay
150
tHD
25
35
ns
tHL
100
0
150
ns
tSSR
tSRR
tSAR
tHSR
tHRR
tHAR
tHS
CS to CE setup
50
0
ns
R/C to CE setup
ns
A0 to CE setup
50
0
25
ns
CS valid after CE low
R/C high after CE low
A0 valid after CE low
STATUS delay after data valid
ns
0
ns
50
75
ns
150
375
ns
6
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ADS774H
www.ti.com ................................................................................................................................................................................................ SBAS443–AUGUST 2009
PIN CONFIGURATION
NT, NTD PACKAGES(1)
DW PACKAGE
DIP-28
SO-28
(TOP VIEW)
(TOP VIEW)
VDD
1
2
3
4
5
6
7
8
9
28 STATUS
27 DB11
26 DB10
25 DB9
24 DB8
23 DB7
22 DB6
21 DB5
20 DB4
19 DB3
18 DB2
17 DB1
16 DB0
VDD
1
2
3
4
5
6
7
8
9
28 STATUS
27 DB11
26 DB10
25 DB9
24 DB8
23 DB7
22 DB6
21 DB5
20 DB4
19 DB3
18 DB2
17 DB1
16 DB0
12/8
12/8
CS
CS
A0
A0
R/C
CE
R/C
CE
NC
NC
ADS774H
ADS774H
Ref Out
Ref Out
Analog Common
Analog Common
Ref In 10
VEE 11
Ref In 10
VEE 11
Bipolar Offset
12
13
14
Bipolar Offset
12
13
14
10V Range
20V Range
10V Range
20V Range
Digital Common
15
Digital Common
15
(1) NT and NTD (DIP-28) packages are
product preview.
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ADS774H
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PIN DESCRIPTIONS
PIN
NAME
NO.
I/O
DESCRIPTION
VDD
1
Power
5V digital logic supply
Data mode select
'1' = read
12/8
2
Input
'0' = convert
CS
A0
3
4
Input
Input
Chip select (active low)
Byte address, short cycle
Read/Convert
'1' = 12-bit
'0' = 8-bit
R/C
5
Input
Input
CE
NC
6
7
Chip enable (active high)
Do not connect
Ref Out
Analog Common
Ref In
8
Output
Power
Input
2.5V reference output
Analog ground
9
10
11
2.5V reference input
–15V to +5V analog supply
VEE
Power
Connect this pin to REF OUT through a 50Ω resistor for bipolar operation, or connect to Analog
Common for unipolar operation.
Bipolar Offset
12
Input
10V Range
20V Range
Digital Common
DB0
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Input
0V to 10V or ±5V input span. Do not connect if using a 20V range.
0V to 20V or ±10V input span. Do not connect if using a 10V range.
Digital ground
Input
Power
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
DB1
These pins provide the lower four bits of data when A0 is high. When A0 is low, these pins/bits are
disabled.
DB2
DB3
DB4
DB5
In 12-bit format, these pins output the middle four bits of data. In 8-bit format, they output the
middle four bits when A0 is low, and all 0's when A0 is high.
DB6
DB7
DB8
DB9
In 12-bit format, these pins output the upper four bits of data. In 8-bit format, they output the upper
four bits when A0 is low, and they are disabled when A0 is high.
DB10
DB11
STATUS
Active high when conversion is in progress; active low when complete.
8
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ADS774H
www.ti.com ................................................................................................................................................................................................ SBAS443–AUGUST 2009
FUNCTIONAL BLOCK DIAGRAM
+5VDC Supply (VDD
)
Power-Up Reset
1
2
3
4
5
6
7
8
9
28 STATUS
DB11 (MSB)
12/8
27
26 DB10
25 DB9
24 DB8
23 DB7
22 DB6
21 DB5
20 DB4
19 DB3
18 DB2
17 DB1
CS
A0
Control
Logic
Clock
R/C
CE
NC(1)
2.5V Ref Out
12
2.5V
Reference
12 Bits
Bits
Analog Common
2.5V Ref In 10
VEE
11
12
13
14
Bipolar Offset
10V Range
20V Range
DB0 (LSB)
Digital Common
16
15
CDAC
NOTE (1): Not internally connected.
Input Voltages, Transition Values, and LSB Values
BINARY (BIN) OUTPUT
INPUT VOLTAGE RANGE and MSB VALUES
Analog Input Voltage
Range
Defined As:
±10V
±5V
0V to +10V
0V to +20V
FSR
2n
20V
2n
10V
2n
10V
2n
20V
2n
One least significant bit
(LSB)
n = 8
78.13mV
4.88mV
39.06mV
2.44mV
39.06mV
2.44mV
78.13mV
4.88mV
n = 12
Output transition values
xxx FFEh to FFFh
+Full-scale calibration
+10V – 3/2LSB
0V – 1/2LSB
+5V – 3/2LSB
0V – 1/2LSB
–5V + 1/2LSB
+10V – 3/2LSB
+5V – 1/2LSB
0V + 1/2LSB
+20V – 3/2LSB
+10V – 1/2LSB
0V + 1/2LSB
xxx 7FFFh to 800h
xxx 000h to 001h
Midscale calibration (Bipolar offset)
Zero calibration (–Full-scale calibration)
–10V – +1/2LSB
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TYPICAL CHARACTERISTICS
At TA = +25°C; VDD = VEE = +5V, bipolar ±10V input range, and sampling frequency of 110kHz, unless otherwise specified.
All plots use 4096 point FFTs.
SIGNAL/(NOISE + DISTORTION) vs
INPUT FREQUENCY AND AMBIENT TEMPERATURE
FREQUENCY SPECTRUM (±10V, 2kHz INPUT)
75
70
60
0
-20
S/(N+D) = 72.6dB
THD = -93.5dB
SNR = 72.6dB
+25°C
-40
-60
-80
-100
-120
0.1
1
10
100
0
10
20
30
40
50
55
Input Frequency (kHz)
Input Frequency (kHz)
Figure 5.
Figure 6.
FREQUENCY SPECTRUM (±10V, 20kHz INPUT)
FREQUENCY SPECTRUM (±1V, 20kHz INPUT)
0
-20
0
S/(N+D) = 70.6dB
THD = -77.5dB
SNR = 71.5dB
S/(N+D) = 53.1dB
THD = -74.2dB
SNR = 53.1dB
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
10
20
30
40
50
55
0
10
20
30
40
50
55
Input Frequency (kHz)
Input Frequency (kHz)
Figure 7.
Figure 8.
SPURIOUS FREE DYNAMIC RANGE, SNR, AND THD
vs INPUT FREQUENCY
POWER-SUPPLY REJECTION vs
SUPPLY RIPPLE FREQUENCY
80
60
40
20
0
100
Spurious Free Dynamic Range
90
80
70
60
Total Harmonic Distortion (THD)
Signal-to-Noise Ratio (SNR)
10
100
1k
10k
100k
1M
10M
0.1
1
10
100
Supply Ripple Frequency (Hz)
Input Frequency (kHz)
Figure 9.
Figure 10.
10
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ADS774H
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THEORY OF OPERATION
OVERVIEW
CONVERSION
In the ADS774H, the advantages of advanced CMOS
technology (such as high logic density, stable
capacitors, and precision analog switches) produce a
fast, low-power ADC with internal sample/hold.
When a conversion command is received, switch S1
opens to capture a charge on the MSB capacitor
proportional to the analog input level at the time of
the sampling command, and switch SC opens to float
the comparator input. The charge held in the
capacitor array can now be moved between the three
capacitors in the array by connecting switches S1, S2,
and S3 to either the R position (to connect to the
reference) or the G position (to connect to GND), thus
changing the voltage generated at the comparator
input.
The charge-redistribution successive-approximation
circuitry converts analog input voltages into digital
words.
A simple example of a charge-redistribution ADC with
only three bits is shown in Figure 11.
SAMPLING
During the first approximation, the MSB capacitor is
connected through switch S1 to the reference, while
switches S2 and S3 are connected to GND.
Depending on whether the comparator output is high
or low, the logic then latches S1 in position R or G.
Similarly, the second approximation is made by
connecting S2 to the reference and S3 to GND, and
latching S2 according to the output of the comparator.
After three successive approximation steps have
been made, the voltage level at the comparator is
within 1/2LSB of GND, and a digital word that
represents the analog input can be determined from
the positions of S1, S2 and S3.
While sampling, the capacitor array switch for the
MSB capacitor (S1) is in position S, so that the
charge on the MSB capacitor is proportional to the
voltage level of the analog input signal. The
remaining array switches (S2 and S3) are set to
position G. Switch SC is closed, setting the
comparator input offset to zero.
Analog
Input
SC
Comparator
4C
2C
C
Out
Signal
S
S1
G
S2
G
S3
G
R
R
R
+
Reference
Input
-
Figure 11. 3-Bit Charge Redistribution ADC
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DEVICE OPERATION
BASIC OPERATION
data output pins into a high-Z state and inhibits the
input lines. This condition means that pulses on pin 5
are ignored, so that new conversions cannot be
initiated during the conversion, either as a result of
spurious signals or to short-cycle the ADS774H.
Figure 12 shows the minimum connections required
to operate the ADS774H in a basic ±10V range in the
Control Mode (discussed in detail in the section,
Sample/Hold (S/H) Control Mode and ADC774
Emulation Mode). The falling edge of a Convert
Command (a pulse that takes pin 5 low for a
minimum of 25ns) initiates two actions: first, it
switches the ADS774H input to the hold state;
second, it begins the conversion process. Pin 28
(STATUS) outputs high during the conversion, and
falls only after the conversion is completed and the
data have been latched on the data output pins (pins
16 to 27). Thus, the falling edge of STATUS on pin
28 can be used to read the data from the conversion.
Also, during conversion, the STATUS signal puts the
The ADS774H begins acquiring a new sample as
soon as the conversion completes, even before the
STATUS output falls, and tracks the input signal until
the next conversion is started. The ADS774H is
designed to complete a conversion and accurately
acquire a new signal in 8.5µs (max) over the full
operating temperature range, so that conversions can
take place at a full 117kHz.
Status
Output
+5V
1
2
28
10mF
DB11 (MSB)
27
3
26 DB10
25 DB9
24 DB8
23 DB7
22 DB6
21 DB5
20 DB4
19 DB3
18 DB2
17 DB1
4
Convert Command
5
+5V
6
NC(1)
7
ADS774H
8
9
50W
10
11
12
(2)
50W
DB0 (LSB)
Leave Unconnected 13
14
16
15
±10V
Analog
Input
NOTES (1): Not internally connected.
(2): Connect to GND or VEE for Emulation Mode.
Connect to +5V for Control Mode.
Figure 12. Basic ±10V Operation
12
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CONTROLLING THE ADS774H
reading the output data when ready: choosing either
12 bits all at once, or the eight MSBs followed by the
four LSBs in a left-justified format. The five control
inputs (12/8, CS, A0, R/C, and CE) are all
TTL-/CMOS-compatible. The functions of the control
inputs are described in Table 1. The control function
truth table is shown in Table 2.
The ADS774H can easily interface with most
microprocessors and other digital systems. The
microprocessor may take full control of each
conversion, or the converter may operate in a
stand-alone mode, controlled only by the R/C input.
Full control consists of selecting an 8- or 12-bit
conversion cycle, initiating the conversion, and
Table 1. Control Line Functions
DESIGNATION
DEFINITION
FUNCTION
Must be high ('1') to either initiate a conversion or read output data. 0-to-1 edge
may be used to initiate a conversion.
CE (pin 6)
Chip Enable (active high)
Must be low ('0') to either initiate a conversion or read output data. 1-to-0 edge
may be used to initiate a conversion.
CS (pin 3)
R/C (pin 5)
Chip Select (active low)
Must be low ('0') to initiate either 8- or 12-bit conversions. 1-to-0 edge may be used
to initiate a conversion.
Must be high ('1') to read output data. 0-to-1 edge may be used to initiate a read
operation.
Read/Convert
'1' = Read
'0' = Convert
In the start-convert mode, A0 selects either 8-bit (A0 = '1') or 12-bit (A0 = '0')
A0 (pin 4)
Byte Address, short cycle conversion mode. When reading output data in two 8-bit bytes, A0 = '0' accesses
eight MSBs (high byte) and A0 = '1' accesses four LSBs and trailing 0s (low byte).
Data Mode select
When reading output data, 12/8 = '1' enables all 12 output bits simultaneously.
12/8 = '0' enables the MSBs or LSBs as determined by the A0 line.
12/8 (pin 2)
'1' = 12-bit
'0' = 8-bit
Table 2. Control Input Truth Table
CE
0
CS
X
1
R/C
X
X
0
12/8
X
A0
X
X
0
OPERATION
None
X
↑
X
None
0
X
Initiate 12-bit conversion
Initiate 8-bit conversion
Initiate 12-bit conversion
Initiate 8-bit conversion
Initiate 12-bit conversion
Initiate 8-bit conversion
Enable 12-bit output
Enable eight MSBs only
↑
0
0
X
1
1
↓
0
X
0
1
↓
0
X
1
1
0
↓
X
0
1
0
↓
X
1
1
0
1
1
X
0
1
0
1
0
Enable four LSBs plus four trailing
zeroes
1
0
1
0
1
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STAND-ALONE OPERATION
CONVERSION START
For stand-alone operation, control of the converter is
accomplished by a single control line connected to
R/C. In this mode, CS and A0 are connected to digital
common, and CE and 12/8 are connected to +5V.
The output data are presented as 12-bit words.
Stand-alone mode is used in systems that contain
dedicated input ports which do not require full bus
interface capability.
The converter initiates a conversion based on a
transition that occurs on any of three logic inputs (CE,
CS, and R/C) as shown in Table 2. Conversion is
initiated by the last of the three inputs to reach the
required state; therefore, all three inputs may be
dynamically controlled. If necessary, all three inputs
may change state simultaneously; in this case, the
nominal delay time is the same regardless of which
input actually starts the conversion. If it is desired that
Conversion is initiated by a high-to-low transition of
R/C. The three-state data output buffers are enabled
when R/C is high and STATUS is low. Thus, there
are two possible modes of operation: data can be
read with either a positive pulse on R/C, or a negative
pulse on STATUS. In either case, the R/C pulse must
remain low for a minimum of 25ns.
a
particular input establish the actual start of
conversion, the other two inputs should be stable for
a minimum of 50ns before the transition of the critical
input. Timing relationships for the start of conversion
timing are illustrated in Figure 3. The timing
specifications for timing are listed in the Timing
Requirements tables for Fully-Controlled Operation
Convert Mode and Read Mode.
Figure 1 illustrates timing with an R/C pulse that goes
low and returns high during the conversion. In this
case, the three-state outputs go to the
high-impedance state in response to the falling edge
of R/C and are enabled for external access of the
data after the conversion completes.
The STATUS output indicates the current state of the
converter because it is in a high state only during
conversion. During this time the three-state output
buffers remain in
a high-impedance state, and
therefore data cannot be read during conversion.
Furthermore, during this period, additional transitions
of the three digital inputs that control conversion are
ignored, so that conversion cannot be prematurely
terminated or restarted. However, if A0 changes state
after the beginning of the conversion, any additional
start conversion transition will latch the new state of
A0, and possibly generate an incorrect conversion
length (8 bits as opposed to 12 bits) for that
conversion.
Figure 2 illustrates the timing when a positive R/C
pulse is used. In this mode, the output data from the
previous conversion are enabled during the time R/C
is high. A new conversion starts on the falling edge of
R/C, and the three-state outputs return to the
high-impedance state until the next occurrence of a
high R/C pulse. Timing specifications for stand-alone
operation are listed in the TIming Requirements table
for Stand-Alone Mode.
READING OUTPUT DATA
FULLY-CONTROLLED OPERATION
Conversion Length
After conversion is initiated, the output data buffers
remain in a high-impedance state until the following
four logic conditions are simultaneously met: R/C
high, STATUS low, CE high, and CS low. Upon
satisfying these conditions, the data lines are enabled
according to the state of inputs 12/8 and A0. See
Figure 4 for the timing diagram, and the Timing
Requirements tables for Fully-Controlled Operation
Convert Mode and Read Mode for timing
specifications.
Conversion length (8-bit or 12-bit) is determined by
the state of the A0 input, which is latched upon
receipt of a conversion start transition (described in
the next section). If A0 is latched high, the conversion
continues for eight bits. The full 12-bit conversion
occurs if A0 is low. If all 12 bits are read following an
8-bit conversion, the four LSBs (DB0–DB3) are low
(logic 0). A0 is latched because it is also involved in
enabling the output buffers. No other control inputs
are latched.
14
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In most applications, the 12/8 input is hard-wired in
either the high or low condition, although it is fully
TTL- and CMOS-compatible and may be actively
driven if desired. When 12/8 is high, all 12 output
lines (DB0 to DB11) are enabled simultaneously for
full data word transfer to a 12-bit or 16-bit bus. In this
situation, the A0 state is ignored when reading the
data.
contains the four LSBs from the conversion followed
by four logic zeroes that have been forced by the
control logic. The left-justified formats of the two 8-bit
bytes are shown in Table 3. Connection of the
ADS774H to an 8-bit bus for data transfer is
illustrated in Figure 13. The design of the ADS774H
ensures that the A0 input may be toggled at any time
with no damage to the converter; the outputs that are
tied together in Figure 13 cannot be enabled at the
same time. The A0 input is usually driven by the least
significant bit of the address bus to allow storage of
the output data word in two consecutive memory
locations.
When 12/8 is low, the data is presented in the form of
two 8-bit bytes, with selection of the byte of interest
accomplished by the state of A0 during the read
cycle. When A0 is low, the byte addressed contains
the eight MSBs. When A0 is high, the byte addressed
Table 3. 12-Bit Data Format for 8-Bit Systems
Word 1
Word 2
Processor
Converter
DB7
DB6
DB5
DB9
DB4
DB8
DB3
DB7
DB2
DB6
DB1
DB5
DB0
DB4
DB11
DB10
Processor
Converter
DB7
DB3
DB6
DB2
DB5
DB1
DB4
DB0
DB3
0
DB2
0
DB1
0
DB0
0
28
27
26
25
24
23
22
21
20
19
18
17
16
15
STATUS
2
4
12/8
A0
DB11 (MSB)
A0
Address
Bus
Data
Bus
ADS774H
DB0 (LSB)
Digital Common
Figure 13. Connection to an 8-Bit Bus
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SAMPLE/HOLD (S/H) CONTROL MODE AND
ADC774 EMULATION MODE
about the input level after the convert command
arrives, because the input signal is sampled and
conversion begins immediately after the convert
command. This architecture means that a convert
command can also be used to switch an input
multiplexer or change gains on a programmable gain
amplifier, allowing the input signal to settle before the
next acquisition at the end of the conversion.
Because aperture jitter is minimized in the Control
Mode, a high input frequency can be converted
without an external sample/hold.
As with the ADS774, Emulation Mode allows the
ADS774H to be dropped into most existing ADC774
sockets without changes to other system hardware or
software. In existing sockets, the analog input is held
stable during the conversion period so that accurate
conversions can proceed, but the input can change
rapidly at any time before the conversion starts.
Emulation Mode uses the stability of the analog input
during the conversion period to both acquire and
convert in
a
maximum of 8µs (8.5µs over
In the Emulation Mode, a delay time is introduced
between the convert command and the start of
conversion to allow the ADS774H enough time to
acquire the input signal before converting. This delay
time increases the effective aperture delay time from
0.02µs to 1.6µs, but allows the ADS774H to replace
the ADC774 in most circuits without additional
changes. In designs where the input to the ADS774H
is changing rapidly in the 200ns before a convert
command, system performance may be enhanced by
delaying the convert command by 200ns.
temperature.) In fact, system throughput can be
increased, because the input to the ADS774H can
start slewing before the end of a conversion (after the
acquisition time), which is not possible with existing
ADC774s.
The Control Mode is provided to allow full use of the
internal sample/hold, eliminating the need for an
external sample/hold in most applications. As
compared with systems using separate sample/hold
and ADC stages, the ADS774H in the Control Mode
also eliminates the need for one of the control
signals, usually the convert command. The command
that puts the internal sample/hold in the hold state
When using the ADS774H in the Emulation Mode to
replace existing converters in current designs, a
sample/hold amplifier often precedes the converter. In
these cases, no additional delay in the convert
command is needed. The existing sample/hold does
not slew excessively when going from the sample
mode to the hold mode before a conversion. In both
modes, as soon as the conversion completes, the
internal sample/hold circuit immediately begins
slewing to track the input signal.
also initiates
constraints in many systems.
a
conversion, reducing timing
The basic difference between these two modes is the
assumptions about the state of the input signal both
before and during the conversion. These differences
are shown in Figure 14 and Table 4. In the Control
Mode, it is assumed that during the required 1.4µs
acquisition time, the signal is not changing faster than
the ADS774H can track. No assumption is made
R/C
tC
tAP
Signal
Acquistion
Signal
Conversion
S/H Control Mode
Pin 11 connected to +5V
Acquistion
tAQ
tC
tAP
ADC774 Control Mode(1)
Pin 11 connected to VEE or ground
Signal
Acquistion
Signal
Acquistion
Conversion
tAQ
NOTE (1): In the ADC774 Emulation Mode, a convert command triggers a delay that
allows the ADS774H adequate time to acquire the input signal before converting.
Figure 14. Signal Acquisition and Conversion Timing
16
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Table 4. Conversion Timing, TMIN to TMAX
ADC774 EMULATION MODE
S/H CONTROL MODE
(Pin 11 Connected to +5V)
(Pin 11 Connected to 0V to
–15V)
SYMBOL
PARAMETER
Throughput Time:
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
12-bit conversions
8-bit conversions
Conversion Time:
12-bit conversions
8-bit conversions
Acquisition time
8
6
8.5
6.3
8
6
8.5
6.3
µs
µs
tAQ + tC
6.4
4.4
1.4
20
6.4
4.4
µs
µs
µs
ns
ns
tC
tAQ
tAP
tJ
1.4
Aperture delay
1600
10
Aperture uncertainty
0.3
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INSTALLATION
LAYOUT CONSIDERATIONS
The +5V supply should be bypassed with a 10µF
tantalum capacitor located close to the converter to
promote noise-free operations, as shown in
Figure 12. Noise on the power-supply lines can
degrade the converter performance. Noise and spikes
Analog (pin 9) and digital (pin 15) commons are not
connected together internally in the ADS774H, but
should be connected together as close to the unit as
possible, and to an analog common ground plane
beneath the converter on the component side of the
board. In addition, a wide conductor pattern should
run directly from pin 9 to the analog supply common,
and a separate wide conductor pattern from pin 15 to
the digital supply common.
from
a switching power supply are especially
troublesome.
RANGE CONNECTIONS
The ADS774H offers four standard input ranges: 0V
to +10V, 0V to +20V, ±5V, or ±10V. Figure 15 and
Figure 16 show the necessary connections for each
of these ranges, along with the optional gain and
offset trim circuits. If a 10V input range is required,
the analog input signal should be connected to pin 13
of the converter. A signal that requires a 20V range is
connected to pin 14. In either case, the other pin of
the two is left unconnected. Pin 12 (Bipolar Offset) is
connected either to Pin 9 (Analog Common) for
unipolar operation, or to Pin 8 (2.5V Ref Out), or the
external reference, for bipolar operation. Full-scale
and offset adjustments are described in the Optional
External Full-Scale and Offset Adjustments section.
If the single-point system common cannot be
established directly at the converter, pin 9 and pin 15
must be connected together at the converter. A single
wide conductor pattern then connects these two pins
to the system common. In either case, the common
return of the analog input signal should be referenced
to pin 9 of the ADC. This configuration prevents any
voltage drops that may occur in the power-supply
common returns from appearing in series with the
input signal.
The speed of the ADS774H requires special caution
regarding whichever input pin is not used. For 10V
input ranges, pin 14 (20V range) must be
unconnected; for 20V input ranges, pin 13 (10V
range) must be unconnected. In both cases, the
unconnected input should be shielded with a ground
plane to reduce noise pickup.
The input impedance of the ADS774H is typically
50kΩ in the 20V ranges and 12kΩ in the 10V ranges.
+VCC
Unipolar
Offset
Full-Scale
Adjust
In particular, the unused input pin should not be
connected to any capacitive load, including
high-impedance switches. Even a few picofarads on
the unused pin can degrade acquisition time.
Adjust
R1
R2
100kW
10 Ref In
100W
ADS774H
Coupling between analog input and digital lines
should be minimized by careful layout. For instance, if
the lines must cross, these traces should do so at
right angles. Parallel analog and digital lines should
be separated from each other by a pattern connected
to common. If external full-scale and offset
potentiometers are used, the potentiometers and
associated resistors should be located as close as
possible to the ADS774H.
100kW
2.5V
8
Ref Out
-VCC
100W
R3
12 Bipolar Offset
10V
Range
13
14
9
Analog
Input
20V
Range
POWER-SUPPLY DECOUPLING
On the ADS774H, +5V (to Pin 1) is the only power
supply required for correct operation. Pin 7 is not
connected internally, so there is no problem in
existing ADC774 sockets where this is connected to
+15V. Pin 11 (VEE) is only used as a logic input to
select modes of control over the sampling function as
described above. When used in an existing ADC774
socket, the –15V on pin 11 selects the ADC774
Emulation Mode. Pin 11 is used as a logic input;
therefore, it is immune to typical supply variations.
Analog
Common
Figure 15. Unipolar Configuration
18
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Full-Scale
Adjust
42kW
Pin 14
20V Range
10V Range
R2
10 Ref In
100W
ADS774H
21kW
Pin 13
Capacitor
Array(1)
2.5V
8
Ref Out
21kW
100W
R1
Bipolar
Offset
Adjust
12 Bipolar Offset
10.5kW
Pin 12
Bipolar
Offset
Analog
Input
13
14
9
10V
Range
10kW
20V
Range
NOTE (1): 10pF when sampling
Figure 17. ADS774H Input Structure
SINGLE-SUPPLY OPERATION
Analog
Common
Figure 16. Bipolar Configuration
The ADS774H is designed to operate from a single
+5V supply and work with all of the unipolar and
bipolar input ranges, in either Control Mode or
Emulation Mode, as described in the Sample/Hold
(S/H) Control Mode and ADC744 Emulation Mode
section. Pin 7 is not connected internally. This input is
where +12V or +15V is supplied on traditional
ADC774s. Pin 11, the –12V or –15V supply input on
traditional ADC774s, is used only as a logic input on
the ADS774H. There is a resistor divider internally on
pin 11 to reduce that input to a correct logic level
within the ADS774H, and this resistor will add 10mW
to 15mW to the power consumption of the ADS774H
when –15V is supplied to pin 11. To minimize power
consumption in a system, pin 11 can be simply
grounded (for Emulation Mode) or tied to +5V (for
Control Mode.)
INPUT STRUCTURE
Figure 17 shows the resistor divider input structure of
the ADS774H. Because the input is driving
capacitor in the CDAC during acquisition, the input is
looking into a high impedance node.
a
To understand how this circuit works, it is necessary
to know that the input range on the internal sampling
capacitor is from 0V to +3.33V, and that the analog
input to the ADS774H must be converted to this
range. The unipolar 20V range can be used as an
example of how the divider network functions. In 20V
operation, the analog input goes into pin 14. Pin 13 is
left unconnected and pin 12 is connected to pin 9,
analog common. From Figure 17, it is clear that the
input to the capacitor array is the analog input voltage
on pin 14 divided by the resistor network (42kΩ +
42kΩ || 10.5kΩ). A 20V input at pin 14 is divided to
3.33V at the capacitor array, while a 0V input at pin
14 gives 0V at the capacitor array.
There are no other modifications required for the
ADS774H to function with a single +5V supply.
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CALIBRATION
3/2LSB, the value that should cause all bits to be on.
This value is +9.9963V for the 10V range and
+19.9927V for the 20V range. Adjust potentiometer
R2 until bits DB1 to DB11 are on, and DB0 is toggling
on and off.
Optional External Full-Scale and Offset
Adjustments
Offset and full-scale errors may be trimmed to zero
using
external
offset
and
full-scale
trim
Calibration Procedure: Bipolar Ranges
potentiometers connected to the ADS774H as shown
in Figure 15 and Figure 16, respectively, for unipolar
and bipolar operation.
If external adjustments of full-scale and bipolar offset
are not required, replace the potentiometers in
Figure 16 by 50Ω, 1% metal film resistors.
Calibration Procedure: Unipolar Ranges
If adjustments are required, connect the converter as
shown in Figure 16. The calibration procedure is
similar to that described above for unipolar operation,
except that the offset adjustment is performed with an
input voltage that is 1/2LSB above the minus
full-scale value (–4.9988V for the ±5V range,
–9.9976V for the ±10V range). Adjust R1 for DB0 to
toggle on and off with all other bits off. To adjust the
full-scale range, apply a dc input signal that is 3/2LSB
below the nominal plus full-scale value (+4.9963V for
±5V range, +9.9927V for ±10V range) and adjust R2
for DB0 to toggle on and off with all other bits off.
If external adjustments of full-scale and offset are not
required, replace R2 in Figure 15 with a 50Ω 1%
metal film resistor and connect pin 12 to pin 9,
omitting the other adjustment components.
If adjustment is required, connect the converter as
shown in Figure 15. Sweep the input through the
end-point transition voltage (0V + 1/2LSB; +1.22mV
for the 10V range, +2.44mV for the 20V range) that
causes the output code to be DB0 on (high). Adjust
potentiometer R1 until DB0 alternately toggles on and
off with all other bits off. Then, adjust the full-scale by
applying an input voltage of nominal full-scale minus
20
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PACKAGE OPTION ADDENDUM
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9-May-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
ADS774HIBDW
ADS774HIBDWR
ADS774HIDW
NRND
NRND
NRND
NRND
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
28
28
28
28
20
1000
20
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
ADS774HIDWR
1000
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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Addendum-Page 1
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