ADS7804UG4 [TI]
12 位 10us 采样 CMOS 模数转换器 | DW | 28 | -40 to 85;
| 型号： | ADS7804UG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12 位 10us 采样 CMOS 模数转换器 | DW | 28 | -40 to 85 光电二极管 转换器 模数转换器 |
| 文件： | 总20页 (文件大小：1049K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS7804
AD
S7804
A
D
S
7
8
0
4
SBAS019A – JANUARY 1992 – REVISED MAY 2003
12-Bit 10µs Sampling CMOS
ANALOG-to-DIGITAL CONVERTER
DESCRIPTION
FEATURES
The ADS7804 is a complete 12-bit sampling analog-to-digital
(A/D) converter using state-of-the-art CMOS structures. It
contains a complete 12-bit, capacitor-based, SAR A/D con-
verter with S/H, reference, clock, interface for microproces-
sor use, and three-state output drivers.
ꢀ 100kHz min SAMPLING RATE
ꢀ STANDARD ±10V INPUT RANGE
ꢀ 72dB min SINAD WITH 45kHz INPUT
ꢀ ±0.45 LSB max INL
ꢀ DNL: 12 Bits “No Missing Codes”
ꢀ SINGLE +5V SUPPLY OPERATION
ꢀ PIN-COMPATIBLE WITH 16-BIT ADS7805
The ADS7804 is specified at a 100kHz sampling rate, and
guaranteed over the full temperature range. Laser-trimmed
scaling
resistors
provide
an
industry-
standard ±10V input range, while the innovative design
allows operation from a single +5V supply, with power
dissipation under 100mW.
ꢀ USES INTERNAL OR EXTERNAL
REFERENCE
ꢀ COMPLETE WITH S/H, REF, CLOCK, ETC.
ꢀ FULL PARALLEL DATA OUTPUT
The 28-pin ADS7804 is available in plastic 0.3" DIP and SO
packages, both fully specified for operation over the indus-
trial –40°C to +85°C range.
ꢀ 100mW max POWER DISSIPATION
ꢀ 28-PIN 0.3" PLASTIC DIP AND SO PACKAGES
R/C
Clock
CS
BYTE
BUSY
Successive Approximation Register and Control Logic
CDAC
Output
Three
Latches
State
and
20kΩ
±10V Input
Parallel
Three
Data
10kΩ
4kΩ
State
Bus
Comparator
Drivers
CAP
REF
Internal
+2.5V Ref
Buffer
4kΩ
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1992-2003, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
Analog Inputs: VIN ............................................................................. ±25V
CAP ................................... +VANA +0.3V to AGND2 –0.3V
REF .......................................... Indefinite Short to AGND2
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper han-
dling and installation procedures can cause damage.
Momentary Short to VANA
Ground Voltage Differences: DGND, AGND1, AGND2 ................. ±0.3V
VANA ....................................................................................................... 7V
VDIG to VANA ..................................................................................... +0.3V
VDIG ....................................................................................................... 7V
Digital Inputs ........................................................... –0.3V to +VDIG +0.3V
Maximum Junction Temperature ................................................... +165°C
Internal Power Dissipation............................................................. 825mW
Lead Temperature (soldering, 10s) ............................................... +300°C
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
PACKAGE/ORDERING INFORMATION
MAXIMUM
LINEARITY
ERROR
MINIMUM
SIGNAL-TO-
SPECIFIED
(NOISE+DISTORTION) PACKAGE-LEAD TEMPERATURE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
(LSB)
RATIO (LSB)
(DESIGNATOR)(1)
RANGE
ADS7804P
±0.9
70
72
DIP-28 (NT)
DIP-28 (NT)
–40°C to +85°C
–40°C to +85°C
ADS7804P
ADS7804P
Tube, 13
Tube, 13
ADS7804PB
±0.45
ADS7804PB
ADS7804PB
ADS7804U
±0.9
70
SO-28 (DW)
–40°C to +85°C
ADS7804U
ADS7804U
Tube, 28
"
"
"
"
"
"
ADS7804U/1K
Tape and Reel, 1000
ADS7804UB
±0.45
72
SO-28 (DW)
–40°C to +85°C
ADS7804UB
ADS7804UB
Tube, 28
"
"
"
"
"
"
ADS7804UB/1K Tape and Reel, 1000
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
ELECTRICAL CHARACTERISTICS
At TA = –40°C to +85°C, fS = 100kHz, and VDIG = VANA = +5V, using internal reference, unless otherwise specified.
ADS7804P, U
ADS7804PB, UB
PARAMETER
RESOLUTION
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
12
ꢀ
Bits
ANALOG INPUT
Voltage Ranges
Impedance
±10V
23
35
ꢀ
ꢀ
ꢀ
V
kΩ
pF
Capacitance
THROUGHPUT SPEED
Conversion Time
Complete Cycle
5.7
8
10
ꢀ
ꢀ
ꢀ
µs
µs
Acquire and Convert
Throughput Rate
100
ꢀ
kHz
DC ACCURACY
Integral Linearity Error
Differential Linearity Error
No Missing Codes
±0.9
±0.9
±0.45
±0.45
LSB(1)
LSB
Bits
Ensured
0.1
ꢀ
ꢀ
Transition Noise(2)
LSB
Full Scale Error(3,4)
Full Scale Error Drift
Full Scale Error(3,4)
Full Scale Error Drift
Bipolar Zero Error(3)
Bipolar Zero Error Drift
Power Supply Sensitivity
(VDIG = VANA = VD)
±0.5
±0.5
±10
±0.25
±0.25
±10
%
ppm/°C
%
ppm/°C
mV
ppm/°C
LSB
±7
±2
±2
±5
ꢀ
ꢀ
Ext. 2.5000V Ref
Ext. 2.5000V Ref
+4.75V < VD < +5.25V
±0.5
ꢀ
AC ACCURACY
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise+Distortion)
Signal-to-Noise
f
IN = 45kHz
80
ꢀ
dB(5)
dB
dB
dB
kHz
fIN = 45kHz
f
f
–80
ꢀ
IN = 45kHz
IN = 45kHz
70
70
72
72
Full-Power Bandwidth(6)
250
40
ꢀ
ꢀ
SAMPLING DYNAMICS
Aperture Delay
ns
Aperture Jitter
Transient Response
Overvoltage Recovery(7)
Sufficient to meet AC specs
ꢀ
ꢀ
FS Step
2
µs
ns
150
ꢀ
ADS7804
2
SBAS019A
www.ti.com
ELECTRICAL CHARACTERISTICS (Cont.)
At TA = –40°C to +85°C, fS = 100kHz, and VDIG = VANA = +5V, using internal reference, unless otherwise specified.
ADS7804P, U
ADS7804PB, UB
TYP
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
REFERENCE
Internal Reference Voltage
Internal Reference Source Current
(Must use external buffer.)
Internal Reference Drift
2.48
2.5
1
2.52
ꢀ
ꢀ
ꢀ
ꢀ
V
µA
8
ppm/°C
External Reference Voltage Range
for Specified Linearity
External Reference Current Drain
2.3
2.5
2.7
ꢀ
ꢀ
ꢀ
ꢀ
V
Ext. 2.5000V Ref
100
µA
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
–0.3
+2.0
+0.8
VD +0.3V
±10
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
µA
µA
IIH
±10
DIGITAL OUTPUTS
Data Format
Data Coding
VOL
Parallel 12 Bits
Binary Two’s Complement
ISINK = 1.6mA
ISOURCE = 500µA
High-Z State,
+0.4
ꢀ
ꢀ
V
V
µA
VOH
+4
ꢀ
Leakage Current
±5
VOUT = 0V to VDIG
Output Capacitance
High-Z State
15
15
pF
DIGITAL TIMING
Bus Access Time
Bus Relinquish Time
83
83
ꢀ
ꢀ
ns
ns
POWER SUPPLIES
Specified Performance
VDIG
Must be ≤ VANA
+4.75
+4.75
+5
+5
0.3
16
+5.25
+5.25
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
mA
mA
VANA
+IDIG
+IANA
Power Dissipation
fS = 100kHz
100
ꢀ
mW
TEMPERATURE RANGE
Specified Performance
Derated Performance
Storage
–40
–55
–65
+85
+125
+150
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
°C
°C
°C
Thermal Resistance (θJA
)
Plastic DIP
SO
75
75
ꢀ
ꢀ
°C/W
°C/W
NOTES: (1) LSB means Least Significant Bit. For the 12-bit, ±10V input ADS7804, one LSB is 4.88mV. (2) Typical rms noise at worst case transitions and
temperatures. (3) As measured with fixed resistors shown in Figure 4. Adjustable to zero with external potentiometer. (4) Full scale error is the worst case of –Full
Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes
the effect of offset error. (5) All specifications in dB are referred to a full-scale ±10V input. (6) Full-Power Bandwidth defined as Full-Scale input frequency at which
Signal-to-(Noise + Distortion) degrades to 60dB, or 10 bits of accuracy. (7) Recovers to specified performance after 2 x FS input overvoltage.
ADS7804
SBAS019A
3
www.ti.com
PIN CONFIGURATION
VIN
AGND1
REF
1
2
3
4
5
6
7
8
9
28 VDIG
27 VANA
26 BUSY
25 CS
CAP
AGND2
D11 (MSB)
D10
24 R/C
23 BYTE
22 DZ
ADS7804
D9
21 DZ
D8
20 DZ
D7 10
D6 11
19 DZ
18 D0 (LSB)
17 D1
D5 12
D4 13
16 D2
DGND 14
15 D3
DIGITAL
PIN #
1
NAME
VIN
I/O
DESCRIPTION
Analog Input. See Figure 7.
2
AGND1
REF
CAP
AGND2
D11 (MSB)
D10
Analog Ground. Used internally as ground reference point.
3
Reference Input/Output. 2.2µF tantalum capacitor to ground.
4
Reference Buffer Capacitor. 2.2µF tantalum capacitor to ground.
Analog Ground.
5
6
O
O
O
O
O
O
O
O
Data Bit 11. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 10. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 9. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 8. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 7. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 6. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 5. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 4. Hi-Z state when CS is HIGH, or when R/C is LOW.
Digital Ground.
7
8
D9
9
D8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
D7
D6
D5
D4
DGND
D3
O
O
O
O
O
O
O
O
I
Data Bit 3. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 2. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 1. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 0. Lease Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.
LOW when CS LOW, R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.
LOW when CS LOW, R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.
LOW when CS LOW, R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.
LOW when CS LOW, R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.
Selects 8 most significant bits (LOW) or 8 least significant bits (HIGH).
D2
D1
D0 (LSB)
DZ
DZ
DZ
DZ
BYTE
R/C
I
With CS LOW and BUSY HIGH, a Falling Edge on R/C Initiates a New Conversion. With CS LOW, a rising edge on R/C
enables the parallel output.
25
26
CS
I
Internally OR’d with R/C. If R/C LOW, a falling edge on CS initiates a new conversion.
BUSY
O
At the start of a conversion, BUSY goes LOW and stays LOW until the conversion is completed and the digital outputs
have been updated.
27
28
VANA
VDIG
Analog Supply Input. Nominally +5V. Decouple to ground with 0.1µF ceramic and 10µF tantalum capacitors.
Digital Supply Input. Nominally +5V. Connect directly to pin 27. Must be ≤ VANA
.
TABLE I. Pin Assignments.
ADS7804
4
SBAS019A
www.ti.com
CS
1
R/C BUSY OPERATION
BASIC OPERATION
X
0
X
1
None. Databus is in Hi-Z state.
Figure 1 shows a basic circuit to operate the ADS7804 with
a full parallel data output. Taking R/C (pin 24) LOW for a
minimum of 40ns (6µs max) will initiate a conversion. BUSY
(pin 26) will go LOW and stay LOW until the conversion is
completed and the output registers are updated. Data will be
output in Binary Two’s Complement with the MSB on pin 6.
BUSY going HIGH can be used to latch the data. All convert
commands will be ignored while BUSY is LOW.
↓
Initiates conversion ‘n’. Databus remains
in Hi-Z state.
0
0
↓
↓
0
0
↓
1
1
1
↑
0
1
↑
1
0
0
↑
Initiates conversion ‘n’. Databus enters Hi-Z
state.
Conversion ‘n’ completed. Valid data from
conversion ‘n’ on the databus.
Enables databus with valid data from
conversion ‘n’.
Enables databus with valid data from
conversion ‘n-1’(1). Conversion n in process.
The ADS7804 will begin tracking the input signal at the end
of the conversion. Allowing 10µs between convert com-
mands assures accurate acquisition of a new signal.
Enables databus with valid data from
conversion ‘n-1’(1). Conversion ‘n’ in process.
New conversion initiated without acquisition
of a new signal. Data will be invalid. CS and/or
R/C must be HIGH when BUSY goes HIGH.
The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors compen-
sate for this adjustment and can be left out if the offset and gain
will be corrected in software (refer to the Calibration section).
X
X
0
New convert commands ignored. Conversion
‘n’ in process.
NOTE: (1) See Figures 2 and 3 for constraints on data valid from
conversion “n-1”.
STARTING A CONVERSION
Table II. Control Line Functions for Read and Convert.
The combination of CS (pin 25) and R/C (pin 24) LOW for a
minimum of 40ns immediately puts the sample/hold of the
ADS7804 in the hold state and starts conversion ‘n’. BUSY
(pin 26) will go LOW and stay LOW until conversion ‘n’ is
completed and the internal output register has been updated.
All new convert commands during BUSY LOW will be ig-
nored. CS and/or R/C must go HIGH before BUSY goes
HIGH or a new conversion will be initiated without sufficient
time to acquire a new signal.
CS and R/C are internally OR’d and level triggered. There is
not a requirement which input goes LOW first when initiating
a conversion. If, however, it is critical that CS or R/C initiates
conversion ‘n’, be sure the less critical input is LOW at least
10ns prior to the initiating input.
To reduce the number of control pins, CS can be tied LOW
using R/C to control the read and convert modes. This will
have no effect when using the internal data clock in the serial
output mode. However, the parallel output will become active
whenever R/C goes HIGH. Refer to the Reading Data sec-
tion.
The ADS7804 will begin tracking the input signal at the end
of the conversion. Allowing 10µs between convert com-
mands assures accurate acquisition of a new signal. Refer to
Table II for a summary of CS, R/C, and BUSY states and
Figures 3 through 5 for timing diagrams.
200Ω
1
28
+5V
2
27
26
25
24
23
22
21
20
19
18
17
16
15
+
+
33.2kΩ
2.2µF
0.1µF
10µF
+
3
BUSY
4
5
+
2.2µF
Convert Pulse
R/C
B11 (MSB)
6
B10
B9
B8
B7
B6
B5
B4
LOW
LOW
LOW
LOW
B0 (LSB)
B1
7
40ns min
6µs max
ADS7804
8
9
10
11
12
13
14
B2
B3
FIGURE 1. Basic Operation.
ADS7804
SBAS019A
5
www.ti.com
PARALLEL OUTPUT (During a Conversion)
READING DATA
After conversion ‘n’ has been initiated, valid data from con-
version ‘n-1’ can be read and will be valid up to 16µs after the
start of conversion ‘n’. Do not attempt to read data from 16µs
after the start of conversion ‘n’ until BUSY (pin 26) goes
HIGH; this may result in reading invalid data. Refer to Table
IV and Figures 3 and 5 for timing specifications.
The ADS7804 outputs full or byte-reading parallel data in
Binary Two’s Complement data output format. The parallel
output will be active when R/C (pin 24) is HIGH and CS (pin
25) is LOW. Any other combination of CS and R/C will tri-
state the parallel output. Valid conversion data can be read
in a full parallel, 12-bit word or two 8-bit bytes on pins 6-13
and pins 15-22. BYTE (pin 23) can be toggled to read both
bytes within one conversion cycle. Refer to Table III for ideal
output codes and Figure 2 for bit locations relative to the
state of BYTE.
Note! For the best possible performance, data should not be
read during a conversion. The switching noise of the asyn-
chronous data transfer can cause digital feedthrough de-
grading the converter’s performance.
The number of control lines can be reduced by tieing CS
LOW while using R/C to initiate conversions and activate the
output mode of the converter. See Figure 3.
DIGITAL OUTPUT
BINARY TWO’S COMPLEMENT
DESCRIPTION
ANALOG INPUT
±10V
BINARY CODE
HEX CODE
Full Scale Range
SYMBOL
DESCRIPTION
Convert Pulse Width
MIN TYP MAX UNITS
Least Significant
Bit (LSB)
4.88mV
t1
t2
40
6000
8
ns
Data Valid Delay after R/C LOW
µs
+Full Scale
9.99512V
0111 1111 1111
7FF
t3
t4
BUSY Delay from R/C LOW
BUSY LOW
65
8
ns
µs
(10V – 1LSB)
Midscale
0V
0000 0000 0000
1111 1111 1111
000
FFF
t5
BUSY Delay after
End of Conversion
220
ns
One LSB below
Midscale
–4.88mV
t6
t7
Aperture Delay
Conversion Time
40
ns
µs
µs
ns
ns
µs
–Full Scale
–10V
1000 0000 0000
800
7.6
8
2
Table III. Ideal Input Voltages and Output Codes.
t8
Acquisition Time
t9
Bus Relinquish Time
BUSY Delay after Data Valid
10
35
83
PARALLEL OUTPUT (After a Conversion)
t10
t11
50 200
7.4
Previous Data Valid
after R/C LOW
After conversion ‘n’ is completed and the output registers
have been updated, BUSY (pin 26) will go HIGH. Valid data
from conversion ‘n’ will be available on D11-D0 (pin 6-13 and
15-18 when BYTE is LOW). BUSY going HIGH can be used
to latch the data. Refer to Table IV and Figures 3 and 5 for
timing specifications.
t7 + t6
t12
Throughput Time
R/C to CS Setup Time
Time Between Conversions
9
10
83
µs
ns
µs
ns
10
t13
10
t14
Bus Access Time
and BYTE Delay
10
TABLE IV. Conversion Timing.
BYTE LOW
BYTE HIGH
+5V
6
7
23
22
21
20
19
18
17
16
15
6
7
23
22
21
20
19
18
17
16
15
Bit 11 (MSB)
Bit 10
Bit 9
Bit 3
Bit 2
LOW
LOW
LOW
LOW
Bit 0 (LSB)
Bit 1
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
ADS7804
ADS7804
8
8
Bit 1
9
9
Bit 8
Bit 0 (LSB)
LOW
10
11
12
13
14
10
11
12
13
14
Bit 7
Bit 6
LOW
Bit 5
LOW
Bit 4
Bit 2
LOW
Bit 10
Bit 11
Bit 3
FIGURE 2. Bit Locations Relative to State of BYTE (pin 23).
ADS7804
6
SBAS019A
www.ti.com
t1
R/C
BUSY
t13
t2
t4
t3
t6
t5
Convert
t7
Acquire
t8
Convert
Acquire
MODE
Previous
Data Valid
Previous
Data Valid
Hi-Z
Not Valid
Data Valid
t10
Hi-Z
Data Valid
DATA BUS
t9
t11
FIGURE 3. Conversion Timing with Outputs Enabled after Conversion (CS Tied LOW.)
t12
t12
t12
t12
R/C
CS
t1
t3
t4
BUSY
MODE
t6
Convert
t7
Acquire
Acquire
Hi-Z State
Data Valid
t9
Hi-Z State
DATA BUS
t14
FIGURE 4. Using CS to Control Conversion and Read Timing.
t12
t12
R/C
CS
BYTE
Pins 6 - 13
Hi-Z
Hi-Z
High Byte
t14
Low Byte
Hi-Z
t14
High Byte
t9
Pins 15 - 22
Low Byte
Hi-Z
FIGURE 5. Using CS and BYTE to Control Data Bus.
ADS7804
SBAS019A
7
www.ti.com
INPUT RANGES
HARDWARE CALIBRATION
The ADS7804 offers a standard ±10V input range. Figure 6
shows the necessary circuit connections for the ADS7804
with and without hardware trim. Offset and full scale error(1)
specifications are tested and guaranteed with the fixed
resistors shown in Figure 6b. Adjustments for offset and
gain are described in the Calibration section of this data
sheet.
To calibrate the offset and gain of the ADS7804, install the proper
resistors and potentiometers as shown in Figure 6a. The calibra-
tion range is ±15mV for the offset and ±60mV for the gain.
SOFTWARE CALIBRATION
To calibrate the offset and gain of the ADS7804 in software,
no external resistors are required. See the No Calibration
section for details on the effects of the external resistors.
Refer to Table V for range of offset and gain errors with and
without external resistors.
The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors compen-
sate for this adjustment and can be left out if the offset and
gain will be corrected in software (refer to the Calibration
section).
NO CALIBRATION
The nominal input impedance of 23kW results from the
combination of the internal resistor network shown on the
front page of the product data sheet and the external resis-
tors. The input resistor divider network provides inherent
overvoltage protection guaranteed to at least ±25V. The 1%
resistors used for the external circuitry do not compromise
the accuracy or drift of the converter. They have little influ-
ence relative to the internal resistors, and tighter tolerances
are not required.
See Figure 6b for circuit connections. The external resistors
shown in Figure 6b may not be necessary in some applications.
These resistors provide compensation for an internal adjustment
of the offset and gain which allows calibration with a single supply.
The nominal transfer function of the ADS7804 will be bound by
the shaded region seen in Figure 7 with a typical offset of –30mV
and a typical gain error of –1.5%. Refer to Table V for range of
offset and gain errors with and without external resistors.
NOTE: (1) Full scale error includes offset and gain errors measured at both
+FS and –FS.
WITH
EXTERNAL
RESISTORS
WITHOUT
EXTERNAL
RESISTORS
UNITS
CALIBRATION
BPZ
–10 < BPZ < 10
–2 < BPZ < 2
–45 < BPZ < 5
–8 < BPZ < 1
mV
LSBs
The ADS7804 can be trimmed in hardware or software. The
offset should be trimmed before the gain since the offset
directly affects the gain. To achieve optimum performance,
several iterations may be required.
Gain
Error
–0.5 < error < 0.5
–0.6 < error < –0.55
–0.45 < error < –0.3(1)
% of FSR
–0.25 < error < 0.25(1)
NOTE: (1) High Grade.
TABLE VII. Bipolar Offset and Gain Errors With and Without
External Resistors.
a)
±10V With Hardware
b)
±10V Without Hardware
Trim
Trim
200Ω
200Ω
1
2
3
4
5
1
±10V
±10V
VIN
VIN
2
33.2kΩ
AGND1
REF
AGND1
+5V
2.2µF
576kΩ
2.2µF
2.2µF
2.2µF
+
+
33.2kΩ
+
+
3
4
5
REF
50kΩ
Gain
Offset
CAP
CAP
50kΩ
AGND2
AGND2
NOTE: Use 1% metal film resistors.
FIGURE 6. Circuit Diagram With and Without External Resistors.
ADS7804
8
SBAS019A
www.ti.com
Digital
Output
7FF
–10V
–9.99983V
–9.9998V
–50mV
Analog
Input
–15mV
9.9997V
9.999815V
+10V
Ideal Transfer Function
With External Resistors
Range of Transfer Function
Without External Resistors
800
FIGURE 7. Full Scale Transfer Function.
The range for the external reference is 2.3V to 2.7V and
determines the actual LSB size. Increasing the reference
voltage will increase the full scale range and the LSB size of
the converter which can improve the SNR.
REFERENCE
The ADS7804 can operate with its internal 2.5V reference or
an external reference. By applying an external reference to
pin 5, the internal reference can be bypassed. The reference
voltage at REF is buffered internally with the output on CAP
(pin 4).
CAP
CAP (pin 4) is the output of the internal reference buffer. A
2.2µF capacitor should be placed as close to the CAP pin as
possible to provide optimum switching currents for the CDAC
throughout the conversion cycle and compensation for the
output of the internal buffer. Using a capacitor any smaller
than 1µF can cause the output buffer to oscillate and may not
have sufficient charge for the CDAC. Capacitor values larger
than 2.2µF will have little affect on improving performance.
The internal reference has an 8 ppm/°C drift (typical) and
accounts for approximately 20% of the full scale error
(FSE = ±0.5% for low grade, ±0.25% for high grade).
REF
REF (pin 3) is an input for an external reference or the output
for the internal 2.5V reference. A 2.2µF capacitor should be
connected as close to the REF pin as possible. The capacitor
and the output resistance of REF create a low pass filter to
bandlimit noise on the reference. Using a smaller value
capacitor will introduce more noise to the reference degrad-
ing the SNR and SINAD. The REF pin should not be used to
drive external AC or DC loads.
The output of the buffer is capable of driving up to 2mA of
current to a DC load. DC loads requiring more than 2mA of
current from the CAP pin will begin to degrade the linearity
of the ADS7804. Using an external buffer will allow the
internal reference to be used for larger DC loads and AC
loads. Do not attempt to directly drive an AC load with the
output voltage on CAP. This will cause performance degra-
dation of the converter.
ADS7804
SBAS019A
9
www.ti.com
SIGNAL CONDITIONING
LAYOUT
The FET switches used for the sample hold on many CMOS
A/D converters release a significant amount of charge injec-
tion which can cause the driving op amp to oscillate. The FET
switch on the ADS7804, compared to the FET switches on
other CMOS A/D converters, releases 5%-10% of the charge.
There is also a resistive front end which attenuates any
charge which is released. The end result is a minimal
requirement for the anti-alias filter on the front end. Any op
amp sufficient for the signal in an application will be sufficient
to drive the ADS7804.
POWER
For optimum performance, tie the analog and digital power pins
to the same +5V power supply and tie the analog and digital
grounds together. As noted in the electrical specifications, the
ADS7804 uses 90% of its power for the analog circuitry. The
ADS7804 should be considered as an analog component.
The +5V power for the A/D should be separate from the +5V
used for the system’s digital logic. Connecting VDIG (pin 28)
directly to a digital supply can reduce converter performance
due to switching noise from the digital logic. For best perfor-
mance, the +5V supply can be produced from whatever
analog supply is used for the rest of the analog signal
conditioning. If +12V or +15V supplies are present, a simple
+5V regulator can be used. Although it is not suggested, if
the digital supply must be used to power the converter, be
sure to properly filter the supply. Either using a filtered digital
supply or a regulated analog supply, both VDIG and VANA
should be tied to the same +5V source.
The resistive front end of the ADS7804 also provides a
guaranteed ±25V overvoltage protection. In most cases, this
eliminates the need for external input protection circuitry.
INTERMEDIATE LATCHES
The ADS7804 does have tri-state outputs for the parallel
port, but intermediate latches should be used if the bus will
be active during conversions. If the bus is not active during
conversion, the tri-state outputs can be used to isolate the
A/D from other peripherals on the same bus. Tri-state outputs
can also be used when the A/D is the only peripheral on the
data bus.
GROUNDING
Three ground pins are present on the ADS7804. DGND is
the digital supply ground. AGND2 is the analog supply
ground. AGND1 is the ground which all analog signals
internal to the A/D are referenced. AGND1 is more suscep-
tible to current induced voltage drops and must have the path
of least resistance back to the power supply.
Intermediate latches are beneficial on any monolithic A/D
converter. The ADS7804 has an internal LSB size of 610µV.
Transients from fast switching signals on the parallel port,
even when the A/D is tri-stated, can be coupled through the
substrate to the analog circuitry causing degradation of
converter performance. The effects of this phenomenon will
be more obvious when using the pin-compatible ADS7805 or
any of the other 16-bit converters in the ADS Family. This is
due to the smaller internal LSB size of 38µV.
All the ground pins of the A/D should be tied to the analog
ground plane, separated from the system’s digital logic ground,
to achieve optimum performance. Both analog and digital
ground planes should be tied to the “system” ground as near
to the power supplies as possible. This helps to prevent
dynamic digital ground currents from modulating the analog
ground through a common impedance to power ground.
ADS7804
10
SBAS019A
www.ti.com
PACKAGE DRAWINGS
NT (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
24 PINS SHOWN
A
PINS **
24
28
DIM
24
13
1.260
(32,04) (36,20)
1.425
A MAX
1.230
(31,24) (35,18)
1.385
A MIN
B MAX
B MIN
0.280 (7,11)
0.250 (6,35)
0.310
(7,87)
0.315
(8,00)
1
12
0.290
(7,37)
0.295
(7,49)
0.070 (1,78) MAX
B
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.010 (0,25)
0°–15°
0.021 (0,53)
0.015 (0,38)
M
0.010 (0,25) NOM
4040050/B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
ADS7804
SBAS019A
11
www.ti.com
PACKAGE DRAWINGS (Cont.)
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PINS SHOWN
0.050 (1,27)
16
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
9
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.291 (7,39)
Gage Plane
0.010 (0,25)
1
8
0° – 8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.012 (0,30)
0.004 (0,10)
0.104 (2,65) MAX
PINS **
16
18
20
24
0.610
28
DIM
0.410
0.462
0.510
0.710
A MAX
A MIN
(10,41) (11,73) (12,95) (15,49) (18,03)
0.400
0.453
0.500
0.600
0.700
(10,16) (11,51) (12,70) (15,24) (17,78)
4040000 /E 08/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
ADS7804
12
SBAS019A
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS7804U
ADS7804U/1K
ADS7804UB
ADS7804UG4
ACTIVE
SOIC
SOIC
SOIC
SOIC
DW
28
28
28
28
20
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
ADS7804U
B
ACTIVE
ACTIVE
ACTIVE
DW
1000 RoHS & Green
Call TI
Call TI
ADS7804U
B
DW
20
20
RoHS & Green
RoHS & Green
ADS7804U
B
DW
NIPDAU
ADS7804U
B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS7804U/1K
SOIC
DW
28
1000
330.0
32.4
11.35 18.67
3.1
16.0
32.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 28
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 55.0
ADS7804U/1K
1000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ADS7804U
ADS7804UB
ADS7804UG4
DW
DW
DW
SOIC
SOIC
SOIC
28
28
28
20
20
20
507
507
507
12.83
12.83
12.83
5080
5080
5080
6.6
6.6
6.6
Pack Materials-Page 3
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