ADS7805U/1KE4 [TI]
16 位 10us 采样 CMOS 模数转换器 | DW | 28 | -25 to 85;
| 型号： | ADS7805U/1KE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16 位 10us 采样 CMOS 模数转换器 | DW | 28 | -25 to 85 光电二极管 转换器 模数转换器 |
| 文件： | 总21页 (文件大小：1060K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS7805
ADS7805
A
D
S
7
8
0
5
SBAS020D – JANUARY 1996 – REVISED OCTOBER 2006
16-Bit, 10µs Sampling, CMOS
ANALOG-to-DIGITAL CONVERTER
FEATURES
DESCRIPTION
● 100kHz min SAMPLING RATE
● STANDARD ±10V INPUT RANGE
● 86dB min SINAD WITH 20kHz INPUT
● ±3.0 LSB max INL
The ADS7805 is a complete 16-bit sampling, Analog-to-
Digital (A/D) converter using state-of-the-art CMOS struc-
tures. It contains a complete 16-bit, capacitor-based, Suc-
cessive Approximation Register (SAR) A/D converter with
Sample-and-Hold (S/H), reference, clock, interface for micro-
processor use, and 3-state output drivers.
● DNL: 16 Bits No Missing Codes
● SINGLE +5V SUPPLY OPERATION
● PIN-COMPATIBLE WITH 12-BIT ADS7804
The ADS7805 is specified at a 100kHz sampling rate and
ensured over the full temperature range. Laser-trimmed
scaling resistors provide an industry-standard ±10V input
range while the innovative design allows operation from a
single +5V supply, with power dissipation under 100mW.
● USES INTERNAL OR EXTERNAL
REFERENCE
● FULL PARALLEL DATA OUTPUT
● 100mW max POWER DISSIPATION
● 0.3" DIP-28 AND SO-28
The ADS7805 is available in a 0.3" DIP-28 and an SO-28
package. Both are fully specified for operation over the
industrial –25°C to +85°C range; however, they will function
over the –40°C to +85C temperature range.
R/C
Clock
CS
BYTE
BUSY
Successive Approximation Register and Control Logic
CDAC
Output
Latches
and
3-State
Parallel
Data
20kΩ
±10V Input
3-State
Drivers
Bus
10kΩ
4kΩ
Comparator
CAP
REF
Internal
+2.5V Ref
Buffer
4kΩ
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1996-2006, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
Analog Inputs: VIN ............................................................................. ±25V
REF.................................................. +VANA + 0.3V to AGND2 – 0.3V
CAP ..................Indifinite Short to AGND2 Momentary Short to VANA
Ground Voltage Differences: DGND, AGND1, AGND2 ................... ±0.3V
VANA ....................................................................................................... 7V
V
V
DIG to VANA ...................................................................................... +0.3V
DIG ........................................................................................................ 7V
Digital Inputs .......................................................... –0.3V to +VDIG + 0.3V
Maximum Junction Temperature ................................................... +165°C
Internal Power Dissipation............................................................. 825mW
Lead Temperature (soldering, 10s)............................................... +300°C
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION(1)
MINIMUM
MAXIMUM
LINEARITY
ERROR
SIGNAL-TO-
(NOISE +
DISTORTION)
RATIO (dB)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
(LSB)
PACKAGE-LEAD
ADS7805P
ADS7805PB
ADS7805U
ADS7805U
ADS7805UB
ADS7805UB
±4
±3
±4
±4
±3
±3
83
86
83
83
86
86
DIP-28
DIP-28
SO-28
SO-28
SO-28
SO-28
NT
NT
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
NT
NT
ADS7805P
ADS7805PB
ADS7805U
Tube, 13
Tube, 13
DW
DW
DW
DW
DW
DW
DW
DW
Tube, 28
ADS7805U/1K
ADS7805UB
ADS7805UB/1K
Tape and Reel, 1000
Tube, 28
Tape and Reel, 1000
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com.
ELECTRICAL CHARACTERISTICS
TA = –25°C to +85°C, fS = 100kHz, VDIG = VANA = +5V, using internal reference, unless otherwise specified.
ADS7805P, U
TYP
ADS7805PB, UB
TYP
PARAMETER
RESOLUTION
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
16
16
Bits
ANALOG INPUT
Voltage Ranges
Impedance
±10
23
35
±10
23
35
V
kΩ
pF
Capacitance
THROUGHPUT SPEED
Conversion Cycle
Acquire and Convert
10
10
µs
Throughput Rate
100
15
100
16
kHz
DC ACCURACY
Integral Linearity Error
No Missing Codes
Transition Noise(2)
±4
±3
LSB(1)
Bits
LSB
%
ppm/°C
%
ppm/°C
mV
ppm/°C
LSB
1.3
±7
±2
±2
1.3
±5
±2
±2
Full-Scale Error(3,4)
Full-Scale Error Drift
Full-Scale Error(3,4)
Full-Scale Error Drift
Bipolar Zero Error(3)
Bipolar Zero Error Drift
Power Supply Sensitivity
(VDIG = VANA = VD)
±0.5
±0.5
±10
±8
±0.25
±0.25
±10
Ext. 2.5000V Ref
Ext. 2.5000V Ref
+4.75V < VD < +5.25V
±8
AC ACCURACY
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise+Distortion)
f
IN = 20kHz
fIN = 20kHz
IN = 20kHz
–60dB Input
90
83
83
94
86
86
dB(5)
dB
dB
dB
dB
–90
–94
f
30
32
Signal-to-Noise
Full-Power Bandwidth(6)
f
IN = 20kHz
250
250
kHz
SAMPLING DYNAMICS
Aperture Delay
Transient Response
Overvoltage Recovery(7)
40
40
ns
µs
ns
FS Step
2
2
150
150
ADS7805
2
SBAS020D
www.ti.com
ELECTRICAL CHARACTERISTICS (Cont.)
TA = –25°C to +85°C, fS = 100kHz, VDIG = VANA = +5V, using internal reference, unless otherwise specified.
ADS7805P, U
ADS7805PB, UB
TYP
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
REFERENCE
Internal Reference Voltage
Int. Ref. Source Current (must use external buffer)
Internal Reference Drift
2.48
2.5
1
8
2.52
2.48
2.5
1
8
2.52
V
µA
ppm/°C
V
Ext. Ref. Voltage Range for Specified Linearity
2.3
2.5
2.7
2.3
2.5
2.7
External Reference Current Drain
Ext. 2.5000V Ref
100
100
µA
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
–0.3
+2.0
+0.8
VD + 0.3V
±10
–0.3
+2.0
+0.8
VD + 0.3V
±10
V
V
µA
µA
IIH
±10
±10
Parallel 16 Bits
Binary Two’s Complement
DIGITAL OUTPUTS
Data Format
Data Coding
VOL
ISINK = 1.6mA
ISOURCE = 500µA
+0.4
+4
+0.4
V
V
VOH
+4
Leakage Current
Output Capacitance
High-Z State, VOUT = 0V to VDIG
High-Z State
±5
15
±5
15
µA
pF
DIGITAL TIMING
Bus Access Time
Bus Relinquish Time
83
83
83
83
ns
ns
POWER SUPPLIES
Specified Performance
VDIG
VANA
IDIG
IANA
Must be ≤ VANA
+4.75
+4.75
+5
+5
0.3
16
+5.25
+5.25
+4.75
+4.75
+5
+5
0.3
16
+5.25
+5.25
V
V
mA
mA
mW
Power Dissipation
fS = 100kHz
100
100
TEMPERATURE RANGE
Specified Performance
Operating Temperature(8)
Derated Performance
Storage
–25
–40
–55
–65
+85
+85
+125
+150
–25
–40
–55
–65
+85
+85
+125
+150
°C
°C
°C
°C
Thermal Resistance (θJA
)
DIP-28
SO-28
75
75
75
75
°C/W
°C/W
NOTES: (1) LSB means Least Significant Bit. For the 16-bit, ±10V input ADS7805, one LSB is 305µV.
(2) Typical rms noise at worst case transitions and temperatures.
(3) As measured with fixed resistors, see Figure 4. Adjustable to zero with external potentiometer.
(4) Full-scale error is the worst case of –Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the
transition voltage (not divided by the full-scale range) and includes the effect of offset error.
(5) All specifications in dB are referred to a full-scale ±10V input.
(6) Full-Power Bandwidth defined as Full-Scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60dB, or 10 bits of accuracy.
(7) Recovers to specified performance after 2 • FS input overvoltage.
(8) Functionality test at –40°C.
ADS7805
SBAS020D
3
www.ti.com
PIN CONFIGURATION
VIN
AGND1
REF
1
2
3
4
5
6
7
8
9
28 VDIG
27 VANA
26 BUSY
25 CS
CAP
AGND2
D15 (MSB)
D14
24 R/C
23 BYTE
22 D0 (LSB)
21 D1
ADS7805
D13
D12
20 D2
D11 10
D10 11
D9 12
19 D3
18 D4
17 D5
D8 13
16 D6
DGND 14
15 D7
DIGITAL
PIN #
1
NAME
VIN
I/O
DESCRIPTION
Analog Input. See Figure 7.
2
AGND1
REF
CAP
AGND2
D15 (MSB)
D14
Analog Ground. Used internally as ground reference point.
Reference Input/Output. 2.2µF tantalum capacitor to ground.
Reference Buffer Capacitor. 2.2µF tantalum capacitor to ground.
Analog Ground
3
4
5
6
O
O
O
O
O
O
O
O
Data Bit 15. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 14. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 13. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 12. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 11. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 10. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 9. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 8. Hi-Z state when CS is HIGH, or when R/C is LOW.
Digital Ground
7
8
D13
9
D12
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
D11
D10
D9
D8
DGND
D7
O
O
O
O
O
O
O
O
I
Data Bit 7. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 6. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 5. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 4. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 3. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 2. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 1. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Bit 0. Least Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.
Selects 8 most significant bits (LOW) or 8 least significant bits (HIGH).
D6
D5
D4
D3
D2
D1
D0 (LSB)
BYTE
R/C
I
With CS LOW and BUSY HIGH, a Falling Edge on R/C Initiates a new conversion. With CS LOW, a rising edge on R/C
enables the parallel output.
25
26
CS
I
Internally OR’d with R/C. If R/C LOW, a falling edge on CS initiates a new conversion.
BUSY
O
At the start of a conversion, BUSY goes LOW and stays LOW until the conversion is completed and the digital outputs
have been updated.
27
28
VANA
VDIG
Analog Supply Input. Nominally +5V. Decouple to ground with 0.1µF ceramic and 10µF tantalum capacitors.
Digital Supply Input. Nominally +5V. Connect directly to pin 27. Must be ≤ VANA
.
TABLE I. Pin Assignments.
4
ADS7805
SBAS020D
www.ti.com
TYPICAL CHARACTERISTICS
TA = +25°C, fS = 100kHz, VDIG = VANA = +5V, using internal reference and fixed resistors shown in Figure 6b, unless otherwise specified.
FREQUENCY SPECTRUM
FREQUENCY SPECTRUM
(8192 Point FFT; fIN = 20kHz, 0dB)
(8192 Point FFT; fIN = 45kHz, 0dB)
0
–20
0
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–100
–120
–140
0.0
12.5
25.0
37.5
50.0
0.0
12.5
25.0
37.5
50.0
Frequency (kHz)
Frequency (kHz)
SIGNAL-TO-(NOISE + DISTORTION) vs TEMPERATURE
(fIN = 20kHz, 0dB; fS = 50kHz, 100kHz)
SIGNAL-TO-(NOISE + DISTORTION)
vs INPUT FREQUENCY AND INPUT AMPLITUDE
100.0
95.0
90.0
85.0
80.0
75.0
90
80
70
60
50
40
30
20
10
0
0dB
–20dB
50kHz
100kHz
–60dB
–50
–25
0
25
50
75
100
125
150
0
5
10
15
20
25
30
35
40
45
Temperature (°C)
Input Signal Frequency (kHz)
AC PARAMETERS vs TEMPERATURE
(fIN = 20kHz, 0dB)
LINEARITY vs CODE
110
105
100
95
–80
3
2
All Codes INL
1
–85
SFDR
0
–1
–2
–3
–90
–95
THD
SNR
0
8192 16384 24576 32768 40960 49152 57344 65535
Decimal Code
90
–100
–105
–110
3
2
85
All Codes DNL
SINAD
1
80
0
–50
–25
0
25
50
75
100
125
150
–1
–2
–3
Temperature (°C)
0
8192 16384 24576 32768 40960 49152 57344 65535
Decimal Code
ADS7805
SBAS020D
5
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
TA = +25°C, fS = 100kHz, VDIG = VANA = +5V, using internal reference and fixed resistors shown in Figure 6b, unless otherwise specified.
INTERNAL REFERENCE VOLTAGE vs TEMPERATURE
CONVERSION TIME vs TEMPERATURE
8.0
7.9
7.8
7.7
7.6
7.5
7.4
7.3
7.2
2.520
2.515
2.510
2.505
2.500
2.495
2.490
2.485
2.480
–50
–25
0
25
50
75
100
125
150
–50
–25
0
25
50
75
100
125
150
Temperature (°C)
Temperature (°C)
BPZ ERROR (INTERNAL REFERENCE)
8
4
0
–4
–8
ENDPOINT ERRORS (EXTERNAL REFERENCE)
+FS Error
0.2
0.1
0.0
–0.1
–0.2
ENDPOINT ERRORS (EXTERNAL REFERENCE)
0.2
0.1
–FS Error
0.0
–0.1
–0.2
–50
–25
0
25
50
75
100
125
150
Temperature (°C)
ADS7805
6
SBAS020D
www.ti.com
Table II for a summary of CS, R/C, and BUSY states and
Figures 3 through 5 for timing diagrams.
BASIC OPERATION
Figure 1 shows a basic circuit to operate the ADS7805 with
a full parallel data output. Taking R/C (pin 24) LOW for a
minimum of 40ns (7µs max) will initiate a conversion. BUSY
(pin 26) will go LOW and stay LOW until the conversion is
completed and the output registers are updated. Data will be
output in Binary Two’s Complement with the MSB on pin 6.
BUSY going HIGH can be used to latch the data. All convert
commands will be ignored while BUSY is LOW.
CS and R/C are internally OR’d and level triggered. There is
not a requirement which input goes LOW first when initiating
a conversion. If, however, it is critical that CS or R/C initiates
conversion ‘n’, be sure the less critical input is LOW at least
10ns prior to the initiating input.
To reduce the number of control pins, CS can be tied LOW
using R/C to control the read and convert modes. This will
have no effect when using the internal data clock in the serial
output mode. However, the parallel output will become active
whenever R/C goes HIGH. Refer to the “Reading Data”
section.
The ADS7805 will begin tracking the input signal at the end
of the conversion. Allowing 10µs between convert com-
mands assures accurate acquisition of a new signal.
The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors com-
pensate for this adjustment and can be left out if the offset
and gain will be corrected in software (refer to the “Calibra-
tion” section).
CS
1
R/C BUSY OPERATION
X
0
X
1
None. Databus is in Hi-Z state.
↓
Initiates conversion “n”. Databus remains
in Hi-Z state.
0
0
↓
↓
0
0
↓
1
1
1
↑
0
1
↑
1
0
0
↑
Initiates conversion “n”. Databus enters Hi-Z
state.
STARTING A CONVERSION
Conversion “n” completed. Valid data from
conversion “n” on the databus.
The combination of CS (pin 25) and R/C (pin 24) LOW for a
minimum of 40ns immediately puts the sample-and-hold of
the ADS7805 in the hold state and starts conversion ‘n’.
BUSY (pin 26) will go LOW and stay LOW until conversion
‘n’ is completed and the internal output register has been
updated. All new convert commands during BUSY LOW will
be ignored. CS and/or R/C must go HIGH before BUSY goes
HIGH or a new conversion will be initiated without sufficient
time to acquire a new signal.
Enables databus with valid data from
conversion “n”.
Enables databus with valid data from
conversion “n-1”(1). Conversion n in progress.
Enables databus with valid data from
conversion “n-1”(1). Conversion “n” in progress.
New conversion initiated without acquisition
of a new signal. Data will be invalid. CS and/or
R/C must be HIGH when BUSY goes HIGH.
X
X
0
New convert commands ignored. Conversion
“n” in progress.
The ADS7805 will begin tracking the input signal at the end
of the conversion. Allowing 10µs between convert com-
mands assures accurate acquisition of a new signal. Refer to
NOTE: (1) See Figures 3 and 4 for constraints on data valid from
conversion “n-1”.
Table II. Control Line Functions for “Read” and “Convert”.
200Ω
1
28
+5V
2
27
26
25
24
23
22
21
20
19
18
17
16
15
+
+
0.1µF
10µF
2.2µF
2.2µF
33.2kΩ
+
+
3
4
BUSY
Convert Pulse
R/C
5
B15 (MSB)
B14
6
B0 (LSB)
B1
7
40ns min
ADS7805
6µs max
B13
8
B12
B2
9
B3
B11
10
11
12
13
14
B10
B4
B9
B5
B8
B6
B7
FIGURE 1. Basic Operation.
ADS7805
SBAS020D
7
www.ti.com
PARALLEL OUTPUT (During a Conversion)
READING DATA
After conversion ‘n’ has been initiated, valid data from con-
version ‘n – 1’ can be read and will be valid up to 7µs after
the start of conversion ‘n’. Do not attempt to read data from
7µs after the start of conversion ‘n’ until BUSY (pin 26) goes
HIGH; this may result in reading invalid data. Refer to Table
IV and Figures 3 to 5 for timing specifications.
The ADS7805 outputs full or byte-reading parallel data in
Binary Two’s Complement data output format. The parallel
output will be active when R/C (pin 24) is HIGH and CS (pin
25) is LOW. Any other combination of CS and R/C will tri-
state the parallel output. Valid conversion data can be read
in a full parallel, 16-bit word or two 8-bit bytes on pins 6-13
and pins 15-22. BYTE (pin 23) can be toggled to read both
bytes within one conversion cycle. Refer to Table III for ideal
output codes and Figure 2 for bit locations relative to the
state of BYTE.
Note! For the best possible performance, data should not be
read during a conversion. The switching noise of the asyn-
chronous data transfer can cause digital feedthrough de-
grading the converter’s performance.
The number of control lines can be reduced by tying CS LOW
while using R/C to initiate conversions and activate the
output mode of the converter (see Figure 3).
DIGITAL OUTPUT
BINARY TWO’S COMPLEMENT
DESCRIPTION
ANALOG INPUT
±10V
BINARY CODE
HEX CODE
Full-Scale Range
SYMBOL
DESCRIPTION
Convert Pulse Width
MIN TYP MAX UNITS
Least Significant
Bit (LSB)
305µV
t1
t2
40
7000
8
ns
Data Valid Delay after R/C LOW
µs
+Full Scale
9.999695V
0111 1111 1111 1111
7FFF
(10V – 1LSB)
t3
t4
BUSY Delay from R/C LOW
BUSY LOW
65
8
ns
µs
Mid-scale
0V
0000 0000 0000 0000
1111 1111 1111 1111
0000
FFFF
t5
BUSY Delay after
End of Conversion
220
ns
One LSB below
Mid-scale
–305µV
t6
t7
Aperture Delay
Conversion Time
40
ns
µs
µs
ns
ns
µs
–Full Scale
–10V
1000 0000 0000 0000
8000
7.6
8
2
Table III. Ideal Input Voltages and Output Codes.
t8
Acquisition Time
t9
Bus Relinquish Time
BUSY Delay after Data Valid
10
35
83
PARALLEL OUTPUT (After a Conversion)
t10
t11
50 200
7.4
After conversion ‘n’ is completed and the output registers
have been updated, BUSY (pin 26) will go HIGH. Valid data
from conversion ‘n’ will be available on D15-D0 (pins 6-13
and 15-22). BUSY going HIGH can be used to latch the data.
Refer to Table IV and Figures 3 to 5 for timing specifications.
Previous Data Valid
after R/C LOW
t7 + t6
t12
Throughput Time
R/C to CS Setup Time
Time Between Conversions
9
10
83
µs
ns
µs
ns
10
t13
10
t14
Bus Access Time
and BYTE Delay
10
TABLE IV. Conversion Timing.
BYTE LOW
BYTE HIGH
+5V
6
7
23
22
21
20
19
18
17
16
15
6
7
23
22
21
20
19
18
17
16
15
Bit 15 (MSB)
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 7
Bit 6
Bit 0 (LSB)
Bit 1
Bit 8
Bit 9
ADS7805
ADS7805
8
8
Bit 5
9
9
Bit 2
Bit 4
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
10
11
12
13
14
10
11
12
13
14
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 8
Bit 6
Bit 0 (LSB)
Bit 7
Bit 15 (MSB)
FIGURE 2. Bit Locations Relative to State of BYTE (pin 23).
ADS7805
8
SBAS020D
www.ti.com
t1
R/C
BUSY
t13
t2
t4
t3
t6
t5
Convert
t7
Acquire
t8
Convert
Acquire
MODE
Previous
Data Valid
Previous
Data Valid
Hi-Z
Not Valid
Data Valid
t10
Hi-Z
Data Valid
DATA BUS
t9
t11
FIGURE 3. Conversion Timing with Outputs Enabled after Conversion (CS Tied LOW).
t12
t12
t12
t12
R/C
CS
t1
t3
t4
BUSY
MODE
t6
Convert
t7
Acquire
Acquire
Hi-Z State
Data Valid
t9
Hi-Z State
DATA BUS
t14
FIGURE 4. Using CS to Control Conversion and Read Timing.
t12
t12
R/C
CS
BYTE
Pins 6-13
Hi-Z
Hi-Z
High Byte
t14
Low Byte
Hi-Z
t14
High Byte
t9
Pins 15-22
Low Byte
Hi-Z
FIGURE 5. Using CS and BYTE to Control Data Bus.
ADS7805
SBAS020D
9
www.ti.com
INPUT RANGES
SOFTWARE CALIBRATION
The ADS7805 offers a standard ±10V input range. Figure 6
shows the necessary circuit connections for the ADS7805
with and without hardware trim. Offset and full-scale error(1)
specifications are tested and specified with the fixed resistors
shown in Figure 6b. Adjustments for offset and gain are
described in the “Calibration” section of this data sheet.
To calibrate the offset and gain of the ADS7805 in software, no
external resistors are required. See the “No Calibration” sec-
tion for details on the effects of the external resistors. Range of
offset and gain errors with and without external resistors is
shown in Table V.
The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors com-
pensate for this adjustment and can be left out if the offset
and gain will be corrected in software (refer to the “Calibra-
tion” section).
NO CALIBRATION
Figure 6b shows circuit connections. The external resistors
shown in Figure 6b may not be necessary in some applica-
tions. These resistors provide compensation for an internal
adjustment of the offset and gain which allows calibration with
a single supply. The nominal transfer function of the ADS7805
will be bound by the shaded region (see Figure 7) with a typical
offset of –30mV and a typical gain error of –1.5%. Refer to
Table V for range of offset and gain errors with and without
external resistors.
The nominal input impedance of 23kΩ results from the combi-
nation of the internal resistor network shown on the front page
of the product data sheet and the external resistors. The input
resistor divider network provides inherent overvoltage protec-
tion ensured to at least ±25V. The 1% resistors used for the
external circuitry do not compromise the accuracy or drift of the
converter. They have little influence relative to the internal
resistors, and tighter tolerances are not required.
WITH
EXTERNAL
RESISTORS
WITHOUT
EXTERNAL
RESISTORS
UNITS
NOTE: (1) Full-scale error includes offset and gain errors measured at both +FS
BP0
–10 < BPO < 10
–30 < BPO < 30
–50 < BPO < –15
–150 < BPO < –45
mV
LSBs
and –FS.
Gain
Error
–0.5 < error < 0.5
–2 < error < –1
% of FSR
CALIBRATION
TABLE V. Offset and Gain Errors With and Without External
Resistors.
The ADS7805 can be trimmed in hardware or software. The
offset should be trimmed before the gain since the offset
directly affects the gain. To achieve optimum performance,
several iterations may be required.
HARDWARE CALIBRATION
To calibrate the offset and gain of the ADS7805, install the
proper resistors and potentiometers as shown in Figure 6a.
The calibration range is ±15mV for the offset and ±60mV for
the gain.
a)
±10V With Hardware
b)
±10V Without Hardware
Trim
Trim
200Ω
200Ω
1
1
2
3
4
5
±10V
VIN
±10V
VIN
2
AGND1
33.2kΩ
AGND1
REF
+5V
2.2µF
2.2µF
2.2µF
33.2kΩ
+
+
+
3
4
5
REF
576kΩ
50kΩ
Gain
Offset
CAP
CAP
50kΩ
+
2.2µF
AGND2
AGND2
NOTE: Use 1% metal film resistors.
FIGURE 6. Circuit Diagram With and Without External Resistors.
ADS7805
10
SBAS020D
www.ti.com
Digital
Output
7FFF
–10V
–9.99983V
–9.9998V
–50mV
Analog
Input
–15mV
9.9997V
9.999815V
+10V
Ideal Transfer Function
With External Resistors
Range of Transfer Function
Without External Resistors
8000
FIGURE 7. Full-Scale Transfer Function.
CAP
REFERENCE
CAP (pin 4) is the output of the internal reference buffer. A
2.2µF capacitor should be placed as close to the CAP pin as
possible to provide optimum switching currents for the CDAC
throughout the conversion cycle and compensation for the
output of the internal buffer. Using a capacitor any smaller
than 1µF can cause the output buffer to oscillate and may not
have sufficient charge for the CDAC. Capacitor values larger
than 2.2µF will have little effect on improving performance.
The ADS7805 can operate with its internal 2.5V reference or
an external reference. By applying an external reference to
pin 5, the internal reference can be bypassed. The reference
voltage at REF is buffered internally with the output on CAP
(pin 4).
The internal reference has an 8 ppm/°C drift (typical) and
accounts for approximately 20% of the full-scale error
(FSE = ±0.5% for low grade, ±0.25% for high grade).
The output of the buffer is capable of driving up to 2mA of
current to a DC load. DC loads requiring more than 2mA of
current from the CAP pin will begin to degrade the linearity
of the ADS7805. Using an external buffer will allow the
internal reference to be used for larger DC loads and AC
loads. Do not attempt to directly drive an AC load with the
output voltage on CAP. This will cause performance degra-
dation of the converter.
REF
REF (pin 3) is an input for an external reference or the output
for the internal 2.5V reference. A 2.2µF capacitor should be
connected as close to the REF pin as possible. The capacitor
and the output resistance of REF create a low-pass filter to
bandlimit noise on the reference. Using a smaller value
capacitor will introduce more noise to the reference degrad-
ing the SNR and SINAD. The REF pin should not be used to
drive external AC or DC loads.
The range for the external reference is 2.3V to 2.7V and
determines the actual LSB size. Increasing the reference
voltage will increase the full-scale range and the LSB size of
the converter which can improve the SNR.
ADS7805
SBAS020D
11
www.ti.com
SIGNAL CONDITIONING
LAYOUT
The FET switches used for the sample-and-hold on many
CMOS A/D converters release a significant amount of charge
injection which can cause the driving op amp to oscillate.
The FET switch on the ADS7805, compared to the FET
switches on other CMOS A/D converters, releases 5%-10%
of the charge. There is also a resistive front end which
attenuates any charge which is released. The end result is a
minimal requirement for the anti-alias filter on the front end.
Any op amp sufficient for the signal in an application will be
sufficient to drive the ADS7805.
POWER
For optimum performance, tie the analog and digital power
pins to the same +5V power supply and tie the analog and
digital grounds together. As noted in the electrical specifica-
tions, the ADS7805 uses 90% of its power for the analog
circuitry. The ADS7805 should be considered as an analog
component.
The +5V power for the A/D converter should be separate
from the +5V used for the system’s digital logic. Connecting
V
DIG (pin 28) directly to a digital supply can reduce converter
The resistive front end of the ADS7805 also provides an
ensured ±25V overvoltage protection. In most cases, this
eliminates the need for external input protection circuitry.
performance due to switching noise from the digital logic. For
best performance, the +5V supply can be produced from
whatever analog supply is used for the rest of the analog
signal conditioning. If +12V or +15V supplies are present, a
simple +5V regulator can be used. Although it is not sug-
gested, if the digital supply must be used to power the
converter, be sure to properly filter the supply. Either using a
filtered digital supply or a regulated analog supply, both VDIG
and VANA should be tied to the same +5V source.
INTERMEDIATE LATCHES
The ADS7805 does have tri-state outputs for the parallel
port, but intermediate latches should be used if the bus will
be active during conversions. If the bus is not active during
conversion, the tri-state outputs can be used to isolate the
A/D converter from other peripherals on the same bus. Tri-
state outputs can also be used when the A/D converter is the
only peripheral on the data bus.
GROUNDING
Three ground pins are present on the ADS7805. DGND is
the digital supply ground. AGND2 is the analog supply
ground. AGND1 is the ground which all analog signals
internal to the A/D converter are referenced. AGND1 is more
susceptible to current induced voltage drops and must have
the path of least resistance back to the power supply.
Intermediate latches are beneficial on any monolithic A/D
converter. The ADS7805 has an internal LSB size of 38µV.
Transients from fast switching signals on the parallel port,
even when the A/D converter is tri-stated, can be coupled
through the substrate to the analog circuitry causing degra-
dation of converter performance.
All the ground pins of the A/D converter should be tied to the
analog ground plane, separated from the system’s digital
logic ground, to achieve optimum performance. Both analog
and digital ground planes should be tied to the “system”
ground as near to the power supplies as possible. This helps
to prevent dynamic digital ground currents from modulating
the analog ground through a common impedance to power
ground.
ADS7805
12
SBAS020D
www.ti.com
Revision History
DATE
10/06
8/06
REVISION PAGE
SECTION
DESCRIPTION
D
C
3
2
Absolute Maximum Ratings CAP and REF were switched.
Package/Ordering Information Corrected typos in ordering table.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
ADS7805
SBAS020D
13
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
20-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS7805U
ADS7805U/1K
ADS7805U/1KE4
ADS7805UB
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
DW
28
28
28
28
28
28
28
28
20
RoHS & Green
NIPDAU-DCC
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
ADS7805U
B
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DW
1000 RoHS & Green
1000 RoHS & Green
NIPDAU-DCC
NIPDAU-DCC
NIPDAU-DCC
NIPDAU-DCC
NIPDAU-DCC
NIPDAU-DCC
NIPDAU-DCC
ADS7805U
B
DW
-25 to 85
ADS7805U
B
DW
20
RoHS & Green
ADS7805U
B
ADS7805UB/1K
ADS7805UBE4
ADS7805UBG4
ADS7805UG4
DW
1000 RoHS & Green
ADS7805U
B
DW
20
20
20
RoHS & Green
RoHS & Green
RoHS & Green
-25 to 85
ADS7805U
B
DW
ADS7805U
B
DW
ADS7805U
B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Aug-2021
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS7805U/1K
SOIC
SOIC
DW
DW
28
28
1000
1000
330.0
330.0
32.4
32.4
11.35 18.67
11.35 18.67
3.1
3.1
16.0
16.0
32.0
32.0
Q1
Q1
ADS7805UB/1K
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS7805U/1K
SOIC
SOIC
DW
DW
28
28
1000
1000
350.0
350.0
350.0
350.0
66.0
66.0
ADS7805UB/1K
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ADS7805U
ADS7805UB
DW
DW
DW
DW
DW
SOIC
SOIC
SOIC
SOIC
SOIC
28
28
28
28
28
20
20
20
20
20
506.98
506.98
506.98
506.98
506.98
12.7
12.7
12.7
12.7
12.7
4826
4826
4826
4826
4826
6.6
6.6
6.6
6.6
6.6
ADS7805UBE4
ADS7805UBG4
ADS7805UG4
Pack Materials-Page 3
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
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