ADS7808U [TI]
12 位 10µs 串行 CMOS 采样模数转换器 (ADC) | DW | 20 | -40 to 85;
| 型号： | ADS7808U |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12 位 10µs 串行 CMOS 采样模数转换器 (ADC) | DW | 20 | -40 to 85 PC 光电二极管 转换器 模数转换器 |
| 文件： | 总30页 (文件大小：1940K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS7808
7808
S
D
A
SBAS018A – JANUARY 1992 – REVISED SEPTEMBER 2003
12-Bit 10µs Serial CMOS Sampling
ANALOG-to-DIGITAL CONVERTER
FEATURES
DESCRIPTION
ꢀ 100kHz SAMPLING RATE
The ADS7808 is a complete 12-bit sampling analog-to-digital
using state-of-the-art CMOS structures. It contains a 12-bit
capacitor-based SAR A/D with S/H, reference, clock, and a
serial data interface. Data can be output using the internal
clock, or can be synchronized to an external data clock. The
ADS7808 also provides an output synchronization pulse for
ease of use with standard DSP processors.
ꢀ 72dB SINAD WITH 45kHz INPUT
ꢀ ±1/2 LSB INL AND DNL
ꢀ SIX SPECIFIED INPUT RANGES
ꢀ SERIAL OUTPUT
ꢀ SINGLE +5V SUPPLY OPERATION
ꢀ PIN-COMPATIBLE WITH 16-BIT ADS7809
The ADS7808 is specified at a 100kHz sampling rate, and
specified over the full temperature range. Laser-trimmed
scaling resistors provide various input ranges including ±10V
and 0V to 5V, while an innovative design operates from a
single +5V supply, with power dissipation under 100mW.
ꢀ USES INTERNAL OR EXTERNAL
REFERENCE
ꢀ 100mW MAX POWER DISSIPATION
ꢀ 0.3" SO-20
The ADS7808 is available in a 0.3" SO-20, fully specified for
ꢀ SIMPLE DSP INTERFACE
operation over the industrial –40°C to +85°C range.
CS
Power Down
R/C
Successive Approximation Register and Control Logic
Clock
20kΩ
10kΩ
CDAC
R1IN
R2IN
BUSY
Serial
20kΩ
5kΩ
Data
Out
Data Clock
Serial Data
Comparator
R3IN
CAP
Internal
+2.5V Ref
Buffer
4kΩ
REF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1992-2003, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
Analog Inputs: R1IN .......................................................................... ±25V
R2IN .......................................................................... ±25V
R3IN .......................................................................... ±25V
CAP ..................................... VANA+0.3V to AGND2 –0.3V
REF ....................................... Indefinite Short to AGND2,
Momentary Short to VANA
Ground Voltage Differences: DGND, AGND2 ................................. ±0.3V
VANA ...................................................................................................... 7V
V
V
DIG to VANA ....................................................................................... +0.3
DIG ....................................................................................................... 7V
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
Digital Inputs ............................................................. –0.3V to VDIG +0.3V
Maximum Junction Temperature .................................................. +165°C
Internal Power Dissipation ............................................................ 700mW
Lead Temperature (soldering, 10s) .............................................. +300°C
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
PACKAGE/ORDERING INFORMATION
MAXIMUM
INTEGRAL
MINIMUM
SIGNAL-TO-
SPECIFIED
LINEARITY
ERROR (LSB)
(NOISE + DISTORTION)
RATIO (DB)
PACKAGE
PACKAGE-LEAD DESIGNATOR(1)
TEMPERATURE PACKAGE
RANGE MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
ADS7808U
"
±0.9
"
70
"
SO-20
"
DW
"
–40°C to +85°C ADS7808U
ADS7808U
Tube, 38
"
"
ADS7808U/1K Tape and Reel, 1000
ADS7808UB Tube, 38
ADS7808UB/1K Tape and Reel, 1000
ADS7808UB
"
±0.45
"
72
"
"
"
"
"
"
"
ADS7808UB
"
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
ELECTRICAL CHARACTERISTICS
At TA = –40°C to +85°C, fS = 100kHz, VDIG = VANA = +5V, using internal reference and fixed resistors as shown in Figure 4, unless otherwise specified.
ADS7808U
TYP
ADS7808UB
TYP
PARAMETER
RESOLUTION
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
12
ꢀ
Bits
ANALOG INPUT
Voltage Ranges
Impedance
±10V, 0V to 5V, etc. (See Table I)
See Table I
Capacitance
35
ꢀ
pF
THROUGHPUT SPEED
Conversion Time
Complete Cycle
5.7
8
10
ꢀ
ꢀ
ꢀ
µs
µs
Acquire and Convert
Throughput Rate
100
ꢀ
kHz
DC ACCURACY
Integral Linearity Error
Differential Linearity Error
No Missing Codes
±0.9
±0.9
±0.45
±0.45
LSB(1)
LSB
Specified
0.1
ꢀ
ꢀ
Transition Noise(2)
LSB
%
ppm/°C
%
ppm/°C
mV
ppm/°C
mV
mV
mV
ppm/°C
ms
Full Scale Error(3,4)
Full Scale Error Drift
Full Scale Error(3,4)
Full Scale Error Drift
Bipolar Zero Error(3)
Bipolar Zero Error Drift
Unipolar Zero Error(3)
±0.5
±0.5
±10
±0.25
±0.25
ꢀ
±7
±2
±2
±5
ꢀ
±2
Ext. 2.5000V Ref
Ext. 2.5000V Ref
Bipolar Ranges
Bipolar Ranges
0V to 10V Range
0V to 4V Range
0V to 5V Range
Unipolar Ranges
1µF Capacitor to CAP
±5
±3
±3
ꢀ
ꢀ
ꢀ
Unipolar Zero Error Drift
Recovery to Rated Accuracy
after Power Down
±2
1
ꢀ
ꢀ
Power Supply Sensitivity
(VDIG = VANA = VD)
+4.75V < VD < +5.25V
±0.5
–80
ꢀ
ꢀ
LSB
AC ACCURACY
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise+Distortion)
Signal-to-Noise
fIN = 45kHz
fIN = 45kHz
80
90
–90
73
73
250
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
dB(5)
dB
dB
dB
kHz
f
f
IN = 45kHz
IN = 45kHz
70
70
72
72
Full-Power Bandwidth(6)
ADS7808
2
SBAS018A
www.ti.com
ELECTRICAL CHARACTERISTICS (Cont.)
At TA = –40°C to +85°C, fS = 100kHz, VDIG = VANA = +5V, using internal reference and fixed resistors shown in Figure 4, unless otherwise specified.
ADS7808U
TYP
ADS7808UB
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
SAMPLING DYNAMICS
Aperture Delay
Aperture Jitter
Transient Response
Overvoltage Recovery(7)
40
ꢀ
ꢀ
ns
ns
µs
ns
Sufficient to meet AC specs
FS Step
No Load
2
ꢀ
ꢀ
150
ꢀ
REFERENCE
Internal Reference Voltage
Internal Reference Source Current
(Must use external buffer)
External Reference Voltage Range
for Specified Linearity
2.48
2.3
2.5
1
2.52
ꢀ
ꢀ
ꢀ
ꢀ
V
µA
2.5
2.7
ꢀ
ꢀ
ꢀ
V
External Reference Current Drain
Ext. 2.5000V Ref
100
µA
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
–0.3
+2.0
+0.8
VD +0.3V
±10
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
µA
µA
(8)
VIL = 0V
VIH = 5V
IIH
±10
DIGITAL OUTPUTS
Data Format
Data Coding
Pipeline Delay
Data Clock
Serial 12 bits
Binary Two's Complement or Straight Binary
Conversion results only available after completed conversion.
Selectable for internal or external data clock
Internal
EXT/INT LOW
EXT/INT HIGH
2.3
ꢀ
MHz
MHz
(Output Only When
Transmitting Data)
External
0.1
+4
10
+0.4
±5
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
15
(Can Run Continually)
VOL
VOH
ISINK = 1.6mA
ISOURCE = 500µA
High-Z State,
OUT = 0V to VDIG
High-Z State
V
V
µA
Leakage Current
V
Output Capacitance
15
pF
V
POWER SUPPLIES
Specified Performance
VDIG
VANA
IDIG
IANA
Must be ≤ VANA
+4.75
+5
0.3
+5
+5.25
+5.25
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
mA
mA
ꢀ
+4.75
16
Power Dissipation: PWRD LOW
PWRD HIGH
VDIG = VANA = 5V, fS = 100kHz
100
mW
µW
50
ꢀ
TEMPERATURE RANGE
Specified Performance
Derated Performance
Storage
–40
–55
–65
+85
+125
+150
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
°C
°C
°C
Thermal Resistance (θJA
)
SO
75
ꢀ
°CW
ꢀ Specifications same as ADS7808U.
NOTES: (1) LSB means Least Significant Bit. For the ±10V input range, one LSB is 4.88mV. (2) Typical rms noise at worst case transitions and temperatures.
(3) As measured with fixed resistors in Figure 4. Adjustable to zero with external potentiometer. (4) For bipolar input ranges, full scale error is the worst case of
–Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and
includes the effect of offset error. For unipolar input ranges, full scale error is the deviation of the last code transition divided by the transition voltage. It also includes
the effect of offset error. (5) All specifications in dB are referred to a full-scale ±10V input. (6) Full-Power Bandwidth defined as Full-Scale input frequency at which
Signal-to (Noise + Distortion) degrades to 60dB. (7) Recovers to specified performance after 2 x FS input overvoltage. (8) The minimum VIH level for the DATACLK
signal is 3V.
ADS7808
SBAS018A
3
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PIN ASSIGNMENTS
PIN #
NAME
R1IN
DESCRIPTION
1
2
3
4
5
6
Analog Input. See Table I and Figure 4 for input range connections.
Analog Ground. Used internally as ground reference point. Minimal current flow.
Analog Input. See Table I and Figure 4 for input range connections.
Analog Input. See Table I and Figure 4 for input range connections.
Reference Buffer Capacitor. 2.2µF Tantalum to ground.
AGND1
R2IN
R3IN
CAP
REF
Reference Input/Output. Outputs internal 2.5V reference. Can also be driven by external system reference. In both cases,
bypass to ground with a 2.2µF Tantalum capacitor.
7
8
AGND2
SB/BTC
Analog Ground.
Select Straight Binary or Binary Two’s Complement data output format. If HIGH, data will be output in a Straight Binary format. If
LOW, data will be output in a Binary Two’s complement format.
9
EXT/INT
Select External or Internal Clock for transmitting data. If HIGH, data will be output synchronized to the clock input on DATACLK. If
LOW, a convert command will initiate the transmission of the data from the previous conversion, along with 12 clock pulses output
on DATACLK.
10
11
DGND
SYNC
Digital Ground.
Synch Output. If EXT/INT is HIGH, either a rising edge on R/C with CS LOW or a falling edge on CS with R/C HIGH will output a
pulse on SYNC synchronized to the external DATACLK.
12
13
DATACLK Either an input or an output depending on the EXT/INT level. Output data will be synchronized to this clock. If EXT/INT is LOW,
DATACLK will transmit 12 pulses after each conversion, and then remain LOW between conversions.
DATA
Serial Data Output. Data will be synchronized to DATACLK, with the format determined by the level of SB/BTC. In the external clock
mode, after 12-bits of data, the ADS7808 will output the level input on TAG as long as CS is LOW and R/C is HIGH (see Figure 3.) If
EXT/INT is LOW, data will be valid on both the rising and falling edges of DATACLK, and between conversions DATA will stay at the
level of the TAG input when the conversion was started.
14
15
TAG
R/C
Tag Input for use in external clock mode. If EXT/INT is HIGH, digital data input on TAG will be output on DATA with a delay of 12
DATACLK pulses as long as CS is LOW and R/C is HIGH. See Figure 3.
Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and starts a conversion.
When EXT/INT is LOW, this also initiates the transmission of the data results from the previous conversion. If EXT/INT is HIGH, a
rising edge on R/C with CS LOW, or a falling edge on CS with R/C HIGH, transmits a pulse on SYNC and initiates the transmission of
data from the previous conversion.
16
17
CS
Chip Select. Internally OR’ed with R/C.
BUSY
Busy Output. Falls when a conversion is started, and remains LOW until the conversion is completed and the data is latched into the
output shift register. CS or R/C must be HIGH when BUSY rises, or another conversion will start without time for signal acquisition.
18
19
20
PWRD
VANA
Power Down Input. If HIGH, conversions are inhibited and power consumption is significantly reduced. Results from the previous
conversion are maintained in the output shift register.
Analog Supply Input. Nominally +5V. Connect directly to pin 20, and decouple to ground with 0.1µF ceramic and 10µF Tantalum
capacitors.
VDIG
Digital Supply Input. Nominally +5V. Connect directly to pin 19. Must be ≤ VANA
.
PIN CONFIGURATION
ANALOG CONNECT R1IN CONNECT R2IN
INPUT
RANGE
VIA 200Ω
TO
VIA 100Ω
TO
CONNECT R3IN
TO
IMPEDANCE
R1IN
AGND1
R2IN
1
2
3
4
5
6
7
8
9
20 VDIG
±10V
±5V
±3.33
0V to 10V
0V to 5V
0V to 4V
VIN
AGND
VIN
AGND
AGND
VIN
AGND
VIN
VIN
VIN
AGND
AGND
CAP
CAP
CAP
AGND
VIN
22.9kΩ
13.3kΩ
10.7kΩ
13.3kΩ
10.0kΩ
10.7kΩ
19 VANA
18 PWRD
17 BUSY
16 CS
R3IN
VIN
CAP
ADS7808
TABLE I. Input Range Connections. See Figure 4 for
complete information.
REF
15 R/C
AGND2
SB/BTC
EXT/INT
14 TAG
13 DATA
12 DATACLK
11 SYNC
DGND 10
ADS7808
4
SBAS018A
www.ti.com
SYMBOL
DESCRIPTION
Convert Pulse Width
BUSY Delay
MIN TYP MAX UNITS
t1
CS, R/C
BUSY
t1
t2
t3
t4
40
4500
65
ns
ns
µs
ns
t3
BUSY LOW
8
t2
t4
t5
BUSY Delay after
End of Conversion
220
Convert
t6
Acquire
t7
MODE Acquire
t5
t6
Aperture Delay
Conversion Time
40
ns
µs
µs
µs
ns
ns
ns
5.7
8
2
t7
Acquisition Time
FIGURE 1. Basic Conversion Timing.
t6 + t7
t8
Throughput Time
9
10
R/C LOW to DATACLK Delay
DATACLK Period
450
440
75
t9
t10
Data Valid to DATACLK
HIGH Delay
20
t11
Data Valid after
100 125
ns
DATACLK LOW Delay
t12
t13
t14
t15
External DATACLK Period
External DATACLK HIGH
External DATACLK LOW
100
20
ns
ns
ns
30
DATACLK HIGH
Setup Time
20
t12 + 5 ns
t16
R/C to CS
Setup Time
10
15
ns
t17
SYNC Delay After
DATACLK HIGH
35
55
ns
t18
t19
t20
Data Valid Delay
25
25
ns
ns
µs
CS to Rising Edge Delay
Data Available after CS LOW
4.5
TABLE II. Conversion and Data Timing TA = –40°C to +85°C.
t8
R/C
t9
DATACLK
1
2
3
11
12
t11
t10
SDATA
BUSY
MSB Valid
Bit 10 Valid
Bit 9 Valid
Bit 1 Valid
LSB Valid
t2
t3
FIGURE 2. Serial Data Timing Using Internal Clock. (CS, EXT/INT and TAG Tied LOW.)
ADS7808
SBAS018A
5
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SPECIFIC FUNCTION
CS
R/C
BUSY EXT/INT DATACLK PWRD SB/BTC
OPERATION
Initiate Conversion and
Output Data Using
Internal Clock
1>0
0
1
0
Output
0
x
Initiates conversion “n”. Data from conversion “n–1”
clocked out on DATA synchronized to 12 clock
pulses output on DATACLK.
0
1>0
1
0
Output
0
x
Initiates conversion “n”. Data from conversion “n–1”
clocked out on DATA synchronized to 12 clock
pulses output on DATACLK.
Initiate Conversion and
Output Data Using External
Clock
1>0
0
0
1>0
1
1
1
1
1
1
1
Input
Input
Input
0
0
x
x
x
x
Initiates conversion “n”.
Initiates conversion “n”.
1>0
Outputs a pulse on SYNC followed by data from
conversion “n” clocked out synchronized to external
DATACLK.
1>0
0
1
0>1
0
0
0
1
1
x
Input
Input
x
0
0
0
x
x
x
Outputs a pulse on SYNC followed by data from
conversion “n–1” clocked out synchronized to
external DATACLK.(1) Conversion “n” in process.
Outputs a pulse on SYNC followed by data from
conversion “n–1” clocked out synchronized to
external DATACLK .(1) Conversion “n” in process.
Incorrect Conversions
Power Down
0
0>1
CS or R/C must be HIGH or a new conversion will
be initiated without time for acquisition.
x
x
x
x
x
x
x
x
x
x
0
1
x
x
Analog circuitry powered. Conversion can proceed.
Analog circuitry disabled. Data from previous
conversion maintained in output registers.
x
x
x
x
x
x
x
x
x
x
x
x
0
1
Serial data is output in Binary Two’s Complement
format.
Selecting Output Format
Serial data is output in Straight Binary format.
NOTE: (1) See Figure 3b for constraints on previous data valid during conversion.
Table III. Control Truth Table.
DIGITAL OUTPUT
BINARY TWO’S
COMPLEMENT
(SB/BTC LOW)
STRAIGHT BINARY
(SB/BTC HIGH)
HEX
HEX
DESCRIPTION
ANALOG INPUT
BINARY CODE
CODE
BINARY CODE CODE
Full-Scale Range
Least Significant Bit (LSB)
+Full Scale (FS – 1LSB)
Midscale
±10
±5
±3.33V
0V to 5V 0V to 10V
1.22mV 2.44mV
0V to 4V
0.98mV
4.88mV
2.44mV
1.63mV
9.99512V 4.99756V 3.33171V 4.99878V 9.99756V
0V 0V 0V 2.5V 5V
–4.88mV –2.44mV –1.63mV 2.49878V 4.99756V
–10V –5V –3.333333V 0V 0V
3.99902V 0111 1111 1111
2V 0000 0000 0000
1.99902V 1111 1111 1111
0V 1000 0000 0000
7FF
000
FFF
800
1111 1111 1111
FFF
1000 0000 0000 800
0111 1111 1111 7FF
0000 0000 0000 000
One LSB Below Midscale
–Full Scale
Table IV. Output Codes and Ideal Input Voltages.
ADS7808
6
SBAS018A
www.ti.com
FIGURE 3a. Conversion and Read Timing with External Clock. (EXT/INT Tied HIGH). Read After Conversion.
ADS7808
SBAS018A
7
www.ti.com
FIGURE 3b. Conversion and Read Timing with External Clock. (EXT/INT Tied HIGH.) Read During Conversion (Previous
Conversion Results).
ADS7808
8
SBAS018A
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With Trim
Input Range
Without Trim
(Adjust offset first at 0V, then adjust gain)
200Ω
200Ω
R1IN
R1IN
AGND1
AGND1
R2IN
100Ω
100Ω
R2IN
VIN
VIN
33.2kΩ
0V – 10V
R3IN
R3IN
33.2kΩ
+5V
2.2µF
+
CAP
REF
CAP
REF
+5V
+
50kΩ
576kΩ
2.2µF
50kΩ
+
+
2.2µF
2.2µF
AGND2
AGND2
200Ω
200Ω
R1IN
R1IN
AGND1
R2IN
AGND1
R2IN
100Ω
100Ω
33.2kΩ
33.2kΩ
R3IN
R3IN
0V – 5V
VIN
VIN
+5V
CAP
REF
CAP
REF
+5V
50kΩ
+
576kΩ
2.2µF
+
50kΩ
2.2µF
+
+
2.2µF
2.2µF
AGND2
AGND2
200Ω
200Ω
VIN
R1IN
VIN
R1IN
AGND1
R2IN
AGND1
R2IN
100Ω
100Ω
0V – 4V
R3IN
R3IN
33.2kΩ
33.2kΩ
+5V
+5V
CAP
REF
CAP
REF
+
+
+
2.2µF
576kΩ
2.2µF
50kΩ
50kΩ
+
2.2µF
2.2µF
AGND2
AGND2
FIGURE 4a. Offset/Gain Circuits for Unipolar Input Ranges.
ADS7808
SBAS018A
9
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With Trim
Input Range
Without Trim
(Adjust offset first at 0V, then adjust gain)
200Ω
200Ω
VIN
VIN
R1IN
R1IN
AGND1
R2IN
AGND1
R2IN
100Ω
100Ω
+5V
±10V
33.2kΩ
R3IN
R3IN
33.2kΩ
50kΩ
+5V
CAP
REF
CAP
REF
+
+
+
2.2µF
2.2µF
576kΩ
50kΩ
+
2.2µF
2.2µF
AGND2
AGND2
200Ω
200Ω
R1IN
R1IN
AGND1
R2IN
AGND1
R2IN
100Ω
100Ω
VIN
33.2kΩ
VIN
33.2kΩ
R3IN
R3IN
±5V
+
2.2µF
+5V
CAP
REF
CAP
REF
+5V
+
50kΩ
576kΩ
2.2µF
50kΩ
+
+
2.2µF
2.2µF
AGND2
AGND2
200Ω
200Ω
VIN
R1IN
VIN
R1IN
AGND1
R2IN
100Ω
100Ω
AGND1
R2IN
R3IN
R3IN
33.2kΩ
2.2µF
33.2kΩ
±3.33V
+
2.2µF
+5V
CAP
REF
CAP
REF
+5V
50kΩ
576kΩ
+
50kΩ
+
+
2.2µF
2.2µF
AGND2
AGND2
FIGURE 4b. Offset/Gain Circuits for Bipolar Input Ranges.
10
ADS7808
SBAS018A
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2015
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ADS7808P
ADS7808PB
ADS7808U
OBSOLETE
OBSOLETE
NRND
PDIP
PDIP
SOIC
N
N
20
20
20
TBD
TBD
Call TI
Call TI
Call TI
Call TI
DW
25
1000
1000
25
Green (RoHS
& no Sb/Br)
CU NIPDAU-DCC
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
ADS7808U
ADS7808U/1K
ADS7808U/1KE4
ADS7808UB
NRND
NRND
NRND
NRND
NRND
SOIC
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
DW
20
20
20
20
20
Green (RoHS
& no Sb/Br)
CU NIPDAU-DCC
CU NIPDAU-DCC
CU NIPDAU-DCC
CU NIPDAU-DCC
CU NIPDAU-DCC
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
ADS7808U
ADS7808U
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
ADS7808U
B
ADS7808UBG4
ADS7808UE4
25
Green (RoHS
& no Sb/Br)
ADS7808U
B
25
Green (RoHS
& no Sb/Br)
ADS7808U
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2015
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS7808U/1K
SOIC
DW
20
1000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Sep-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 20
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
ADS7808U/1K
1000
Pack Materials-Page 2
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
2
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
18X 1.27
20
1
13.0
12.6
NOTE 3
2X
11.43
10
11
0.51
0.31
20X
2.65 MAX
7.6
7.4
B
0.25
C A B
NOTE 4
0.33
0.10
TYP
0.25
SEE DETAIL A
GAGE PLANE
0 - 8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
10
11
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
2
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
18X 1.27
20
1
13.0
12.6
NOTE 3
2X
11.43
10
11
0.51
0.31
20X
2.65 MAX
7.6
7.4
B
0.25
C A B
NOTE 4
0.33
0.10
TYP
0.25
SEE DETAIL A
GAGE PLANE
0 - 8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
10
11
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS7808U
ADS7808U/1K
ADS7808UB
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
DW
DW
DW
20
20
20
25
RoHS & Green
Call TI
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
ADS7808U
Samples
Samples
Samples
1000 RoHS & Green
25 RoHS & Green
Call TI
Call TI
ADS7808U
ADS7808U
B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS7808U/1K
SOIC
DW
20
1000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 20
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
ADS7808U/1K
1000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ADS7808U
DW
DW
SOIC
SOIC
20
20
25
25
507
507
12.83
12.83
5080
5080
6.6
6.6
ADS7808UB
Pack Materials-Page 3
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
2
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
18X 1.27
20
1
13.0
12.6
NOTE 3
2X
11.43
10
11
0.51
0.31
20X
2.65 MAX
7.6
7.4
B
0.25
C A B
NOTE 4
0.33
0.10
TYP
0.25
SEE DETAIL A
GAGE PLANE
0 - 8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
10
11
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
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