ADS7825UB [TI]

4 通道、16 位采样 CMOS 模数转换器 | DW | 28 | -40 to 85;


型号：	ADS7825UB
厂家：	TEXAS INSTRUMENTS
描述：	4 通道、16 位采样 CMOS 模数转换器 \| DW \| 28 \| -40 to 85 光电二极管转换器模数转换器
文件：	总22页 (文件大小：394K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS7825

www.burr-brown.com/databook/ADS7825.html

4 Channel, 16-Bit Sampling CMOS A/D Converter

FEATURES

DESCRIPTION

● 25µs max SAMPLING AND CONVERSION

● SINGLE +5V SUPPLY OPERATION

● PIN-COMPATIBLE WITH 12-BIT ADS7824

● PARALLEL AND SERIAL DATA OUTPUT

● 28-PIN 0.3" PLASTIC DIP AND SOIC

● ±2.0 LSB max INL

The ADS7825 can acquire and convert 16 bits to

within ±2.0 LSB in 25µs max while consuming only

50mW max. Laser-trimmed scaling resistors provide

the standard industrial ±10V input range and channel-

to-channel matching of ±0.1%. The ADS7825 is a

low-power 16-bit sampling A/D with a four channel

input multiplexer, S/H, clock, reference, and a

parallel/serial microprocessor interface. It can be con-

figured in a continuous conversion mode to sequen-

tially digitize all four channels. The 28-pin ADS7825

is available in a plastic 0.3" DIP and in a SOIC, both

fully specified for operation over the industrial –40°C

to +85°C range.

● 50mW max POWER DISSIPATION

● 50µW POWER DOWN MODE

● ±10V INPUT RANGE, FOUR CHANNEL

MULTIPLEXER

● CONTINUOUS CONVERSION MODE

Channel

Continuous Conversion

CONTC

40kΩ

R/C

AIN₀

AIN₁

Successive Approximation Register

and Control Logic

Clock

PWRD

20kΩ

40kΩ

8kΩ

CDAC

BUSY

20kΩ

40kΩ

Serial

DATACLK

SDATA

Data

Out

AIN₂

AIN₃

Comparator

20kΩ

40kΩ

8kΩ

Parallel

Data

Out

D7-D0

BYTE

20kΩ

Internal

+2.5V Ref

Buffer

6kΩ

CAP

REF

International Airport Industrial Park

•

Mailing Address: PO Box 11400, Tucson, AZ 85734

FAXLine: (800) 548-6133 (US/Canada Only)

•

Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706

•

Tel: (520) 746-1111

•

Twx: 910-952-1111

Internet: http://www.burr-brown.com/

•

Cable: BBRCORP

•

Telex: 066-6491

•

FAX: (520) 889-1510

•

Immediate Product Info: (800) 548-6132

PDS-1304B

Printed in U.S.A. October, 1997

ADS7825

SBAS045

SPECIFICATIONS

ELECTRICAL

At T_A= –40°C to +85°C, f_S= 40kHz, V_S1= V_S2= V_S= +5V ±5%, using external reference, CONTC = 0V, unless otherwise specified.

ADS7825P, U

TYP

ADS7825PB, UB

PARAMETER

RESOLUTION

CONDITIONS

MIN

MAX

MIN

TYP

MAX

UNITS

(1)

✻

Bits

ANALOG INPUT

Voltage Range

Impedance

±10V

45.7

✻

kΩ

Channel On or Off

Capacitance

THROUGHPUT SPEED

Conversion Time

Acquisition Time

Multiplexer Settling Time

Complete Cycle (Acquire and Convert)

Throughput Rate

✻

µs

Includes Acquisition

CONTC = +5V

✻

kHz

DC ACCURACY

Integral Linearity Error

No Missing Codes

Transition Noise⁽³⁾

Full Scale Error⁽⁴⁾

Full Scale Error Drift

Full Scale Error⁽⁴⁾

Full Scale Error Drift

Bipolar Zero Error

±3

±2

LSB⁽²⁾

0.8

±7

±2

✻

±5

✻

LSB

ppm/°C

Internal Reference

±0.5

±10

±0.25

✻

Bipolar Zero Error Drift

Channel-to-Channel Mismatch

Power Supply Sensitivity

✻

±0.1

±8

±0.1

✻

+4.75 < V_S< +5.25

f_IN= 1kHz

LSB

AC ACCURACY

Spurious-Free Dynamic Range⁽⁵⁾

Total Harmonic Distortion

Signal-to-(Noise+Distortion)

Signal-to-Noise

✻

_IN= 1kHz

f_IN= 1kHz

–90

✻

100

✻

Channel Separation⁽⁶⁾

–3dB Bandwidth

Useable Bandwidth⁽⁷⁾

120

✻

MHz

kHz

SAMPLING DYNAMICS

Aperture Delay

Transient Response⁽⁸⁾

Overvoltage Recovery⁽⁹⁾

✻

µs

FS Step

REFERENCE

Internal Reference Voltage

Internal Reference Source Current

(Must use external buffer)

External Reference Voltage Range

for Specified Linearity

2.48

2.3

2.5

2.52

✻

µA

2.5

2.7

✻

External Reference Current Drain

V_REF= +2.5V

100

µA

DIGITAL INPUTS

Logic Levels

V_IL

V_IH

I_IL

–0.3

+2.4

+0.8

V_S+0.3V

±10

✻

µA

I_IH

±10

DIGITAL OUTPUTS

Data Format

Data Coding

V_OL

Parallel in two bytes; Serial

Binary Two's Complement

✻

I_SINK= 1.6mA

I_SOURCE= 500µA

High-Z State, V_OUT= 0V to V_S

High-Z State

+0.4

✻

µA

V_OH

±5

✻

Leakage Current

Output Capacitance

✻

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN

assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject

to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not

authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

ADS7825

SPECIFICATIONS (CONT)

ELECTRICAL

At T_A= –40°C to +85°C, f_S= 40kHz, V_S1= V_S2= V_S= +5V ±5%, using external reference, CONTC = 0V, unless otherwise specified.

ADS7825P, U

TYP

ADS7825PB, UB

PARAMETER

CONDITIONS

MIN

MAX

MIN

TYP

MAX

UNITS

DIGITAL TIMING

Bus Access Time

Bus Relinquish Time

Data Clock

Internal Clock (Output only when

transmitting data)

External Clock

PAR/SER = +5V

PAR/SER = 0V

EXT/INT LOW

✻

0.5

0.1

1.5

✻

MHz

EXT/INT HIGH

POWER SUPPLIES

V_S1= V_S2= V_S

Power Dissipation

+4.75

+5.25

✻

µW

f_S= 40kHz

PWRD HIGH

TEMPERATURE RANGE

Specified Performance

Storage

–40

–65

+85

+150

✻

°C

Thermal Resistance (θ_JA

)

Plastic DIP

SOIC

✻

°C/W

NOTES: (1) An asterik (✻) specifies same value as grade to the left. (2) LSB means Least Significant Bit. For the 16-bit, ±10V input ADS7825, one LSB is 305µV. (3)

Typical rms noise at worst case transitions and temperatures. (4) Full scale error is the worst case of –Full Scale or +Full Scale untrimmed deviation from ideal first and

last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. (5) All specifications in dB are referred

to a full-scale ±10V input. (6) A full scale sinewave input on one channel will be attenuated by this amount on the other channels. (7) Useable Bandwidth defined as

Full-Scale input frequency at which Signal-to-(Noise+Distortion) degrades to 60dB, or 10 bits of accuracy. (8) The ADS7825 will accurately acquire any input step if given

a full acquisition period after the step. (9) Recovers to specified performance after 2 x FS input overvoltage, and normal acquisitions can begin.

PACKAGE/ORDERING INFORMATION

PACKAGE

DRAWING

NUMBER⁽¹⁾

MINIMUM SIGNAL-

TO-(NOISE + DISTORTION)

RATIO (dB)

TEMPERATURE

RANGE

MAXIMUM INTEGRAL

LINEARITY ERROR (LSB)

PRODUCT

PACKAGE

ADS7825P

ADS7825PB

ADS7825U

ADS7825UB

Plastic Dip

SOIC

246

217

–40°C to +85°C

±3

±2

±3

±2

SOIC

NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

TOP VIEW

DIP/SOIC

Analog Inputs: AIN₀, AIN₁, AIN₂, AIN₃.............................................. ±15V

REF ................................... (AGND2 –0.3V) to (V_S+ 0.3V)

CAP ........................................Indefinite Short to AGND2,

Momentary Short to V_S

V_S1

V_S2

AGND1

AIN₀

V_S1and V_S2to AGND2........................................................................... 7V

V_S1to V_S2.......................................................................................... ±0.3V

Difference between AGND1, AGND2 and DGND ............................. ±0.3V

Digital Inputs and Outputs.......................................... –0.3V to (V_S+ 0.3V)

Maximum Junction Temperature ..................................................... 150°C

Internal Power Dissipation ............................................................. 825mW

Lead Temperature (soldering, 10s)................................................ +300°C

Maximum Input Current to Any Pin ................................................. 100mA

AIN₁

26 PWRD

25 CONTC

24 BUSY

23 CS

AIN₂

AIN₃

CAP

REF

22 R/C

ADS7825

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown

recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

AGND2

21 BYTE

20 PAR/SER

19 A0

TRI-STATE

EXT/INT

D6 10

D5 11

18 A1

D4 12

17 D0

TAG

16 D1

SYNC

D3 13

SDATA

DATACLK

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet its

published specifications.

DGND 14

15 D2

ADS7825

PIN ASSIGNMENTS

PIN #

NAME

I/O

DESCRIPTION

AGND1

AIN₀

AIN₁

AIN₂

AIN₃

CAP

Analog Ground. Used internally as ground reference point.

Analog Input Channel 0. Full-scale input range is ±10V.

Analog Input Channel 1. Full-scale input range is ±10V.

Analog Input Channel 2. Full-scale input range is ±10V.

Analog Input Channel 3. Full-scale input range is ±10V.

Internal Reference Output Buffer. 2.2µF Tantalum to ground.

REF

Reference Input/Output. Outputs +2.5V nominal. If used externally, must be buffered to maintain ADS7825 accuracy.

Can also be driven by external system reference. In both cases, bypass to ground with a 2.2µF Tantalum capacitor.

AGND2

Analog Ground.

Parallel Data Bit 7 if PAR/SER HIGH; Tri-state if PAR/SER LOW. See Table I.

Parallel Data Bit 6 if PAR/SER HIGH; Tri-state if PAR/SER LOW. See Table I.

Parallel Data Bit 5 if PAR/SER HIGH; Tri-state if PAR/SER LOW. See Table I.

I/O

Parallel Data Bit 4 if PAR/SER HIGH; if PAR/SER LOW, a LOW level input here will transmit serial data on SDATA from

the previous conversion using the internal serial clock; a HIGH input here will transmit serial data using an external serial

clock input on DATACLK (D2). See Table I.

DGND

Parallel Data Bit 3 if PAR/SER HIGH; SYNC output if PAR/SER LOW. See Table I.

Digital Ground.

I/O

Parallel Data Bit 2 if PAR/SER HIGH; if PAR/SER LOW, this will output the internal serial clock if EXT/INT (D4) is LOW;

will be an input for an external serial clock if EXT/INT (D4) is HIGH. See Table I.

I/O

Parallel Data Bit 1 if PAR/SER HIGH; SDATA serial data output if PAR/SER LOW. See Table I.

Parallel Data Bit 0 if PAR/SER HIGH; TAG data input if PAR/SER LOW. See Table I.

Channel Address. Input if CONTC LOW, output if CONTC HIGH. See Table I.

PAR/SER

Select Parallel or Serial Output. If HIGH, parallel data will be output on D0 thru D7. If LOW, serial data will be output on

SDATA. See Table I and Figure 1.

BYTE

R/C

Byte Select. Only used with parallel data, when PAR/SER HIGH. Determines which byte is available on D0 thru D7.

Changing BYTE with CS LOW and R/C HIGH will cause the data bus to change accordingly. LOW selects the 8 MSBs;

HIGH selects the 8 LSBs. See Figures 2 and 3

Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and starts a

conversion. With CS LOW, a rising edge on R/C enables the output data bits if PAR/SER HIGH, or starts transmission

of serial data if PAR/SER LOW and EXT/INT HIGH.

Chip Select. Internally OR'd with R/C. With CONTC LOW and R/C LOW, a falling edge on CS will initiate a conversion.

With R/C HIGH, a falling edge on CS will enable the output data bits if PAR/SER HIGH, or starts transmission of serial

data if PAR/SER LOW and EXT/INT HIGH.

BUSY

CONTC

PWRD

Busy Output. Falls when conversion is started; remains LOW until the conversion is completed and the data is latched

into the output register. In parallel output mode, output data will be valid when BUSY rises, so that the rising edge

can be used to latch the data.

Continuous Conversion Input. If LOW, conversions will occur normally when initiated using CS and R/C; if HIGH,

acquisition and conversions will take place continually, cycling through all four input channels, as long as CS, R/C and

PWRD are LOW. See Table I. For serial mode only.

Power Down Input. If HIGH, conversions are inhibited and power consumption is significantly reduced. Results from the

previous conversion are maintained in the output register. In the continuous conversion mode, the multiplexer address

channel is reset to channel 0.

V_S2

V_S1

Supply Input. Nominally +5V. Connect directly to pin 28. Decouple to ground with 0.1µF ceramic and 10µF Tantalum

capacitors.

Supply Input. Nominally +5V. Connect directly to pin 27.

ADS7825

TYPICAL PERFORMANCE CURVES

At T_A= +25°C, f_S= 40kHz, V_S1= V_S2= +5V, using internal reference, unless otherwise noted.

FREQUENCY SPECTRUM

(8192 Point FFT; f_IN= 1.02kHz, –0.5dB)

CROSSTALK vs INPUT FREQUENCY

(Active Channel Amplitude = –0.1dB)

–10

–60.0

–70.0

–20

Adjacent Channels, Worst Pair

–30

–80.0

–40

–50

–90.0

Adjacent Channels

–60

–100.0

–110.0

–120.0

–130.0

–140.0

–70

Non-Adjacent Channels

–80

–90

–100

–110

–120

–130

Measurement Limit

100

10k

100k

Frequency (kHz)

Active Channel Input Frequency (Hz)

ADJACENT CHANNEL CROSSTALK, WORST PAIR

(8192 Point FFT; AIN₃= 1.02kHz, –0.1dB; AIN₂= AGND)

ADJACENT CHANNEL CROSSTALK, WORST PAIR

(8192 Point FFT; AIN₃= 10.1kHz, –0.1dB; AIN₂= AGND )

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

–100

–110

–120

–130

Frequency (kHz)

SIGNAL-TO-(NOISE + DISTORTION)

vs INPUT FREQUENCY AND INPUT AMPLITUDE

SIGNAL-TO-(NOISE + DISTORTION)

vs INPUT FREQUENCY (f_IN= –0.1dB)

100

0dB

–20dB

–60dB

10 12 14

18 20

100

10k

100k

Input Signal Frequency (kHz)

Input Signal Frequency (Hz)

ADS7825

TYPICAL PERFORMANCE CURVES (CONT)

At T_A= +25°C, f_S= 40kHz, V_S1= V_S2= +5V, using internal reference, unless otherwise noted.

A. C. PARAMETERS vs TEMPERATURE

(f_IN= 1kHz, –0.1dB)

110

105

100

–110

–105

–100

–95

All Codes INL

SFDR

–1

–2

–3

8192

16384 24576 32768 40960 49152 57344 65535

Decimal Code

SNR

THD

–90

All Codes DNL

–85

SINAD

–50

–80

100

–1

–2

–3

–25

Temperature (°C)

8192

16384 24576 32768 40960 49152 57344 65535

Decimal Code

ENDPOINT ERRORS

POWER SUPPLY RIPPLE SENSITIVITY

INL/DNL DEGRADATION PER LSB OF P-P RIPPLE

BPZ Error

10^–1

10^–2

10^–3

10^–4

10^–5

–1

–2

0.2

INL

+FS Error

–0.2

0.2

DNL

–FS Error

10¹

10²

10³

10⁴

10⁵

10⁶

10⁷

Power Supply Ripple Frequency (Hz)

–0.2

–50

–25

100

Temperature (°C)

INTERNAL REFERENCE VOLTAGE

vs TEMPERATURE

CONVERSION TIME vs TEMPERATURE

20.4

20.2

2.520

2.515

2.510

2.505

2.500

2.495

2.490

2.485

2.480

19.8

19.6

–50

–25

100

–50

–25

100

Temperature (°C)

ADS7825

BASIC OPERATION

PARALLEL OUTPUT

SERIAL OUTPUT

Figure 1b shows a basic circuit to operate the ADS7825 with

serial output (Channel 0 selected). Taking R/C (pin 22)

LOW for 40ns (12µs max) will initiate a conversion and

output valid data from the previous conversion on SDATA

(pin 16) synchronized to 16 clock pulses output on

DATACLK (pin 15). BUSY (pin 24) will go LOW and stay

LOW until the conversion is completed and the serial data

has been transmitted. Data will be output in Binary Two’s

Complement format, MSB first, and will be valid on both the

rising and falling edges of the data clock. BUSY going

HIGH can be used to latch the data. All convert commands

will be ignored while BUSY is LOW.

Figure 1a shows a basic circuit to operate the ADS7825 with

parallel output (Channel 0 selected). Taking R/C (pin 22)

LOW for 40ns (12µs max) will initiate a conversion. BUSY

(pin 24) will go LOW and stay LOW until the conversion is

completed and the output register is updated. If BYTE (pin

21) is LOW, the 8 most significant bits will be valid when

pin 24 rises; if BYTE is HIGH, the 8 least significant bits

will be valid when BUSY rises. Data will be output in

Binary Two’s Complement format. BUSY going HIGH can

be used to latch the data. After the first byte has been read,

BYTE can be toggled allowing the remaining byte to be

read. All convert commands will be ignored while BUSY is

LOW.

The ADS7825 will begin tracking the input signal at the end

of the conversion. Allowing 25µs between convert com-

mands assures accurate acquisition of a new signal.

The ADS7825 will begin tracking the input signal at the end

of the conversion. Allowing 25µs between convert com-

mands assures accurate acquisition of a new signal.

Parallel Output

(a)

0.1µF 10µF

+5V

±10V

BUSY

Convert Pulse

R/C

BYTE

2.2µF

ADS7825

2.2µF

40ns min

+5V⁽¹⁾

(b)

Serial Output

Pin 21 D15 D14 D13 D12 D11

LOW

D10 D9 D8

D2 D1 D0

Pin 21 D7 D6 D5 D4 D3

HIGH

0.1µF 10µF

NOTE: (1) PAR/SER = 5V

+5V

±10V

BUSY

R/C

Convert Pulse

40ns min

2.2µF

ADS7825

2.2µF

(3)

NC⁽²⁾

EXT/INT

SYNC

SDATA

DATACLK⁽¹⁾

NOTES: (1) DATACLK (pin 15) is an output when EXT/INT (pin 12) is LOW

and an input when EXT/INT is HIGH. (2) NC = no connection. (3) PAR/SER = 0V.

FIGURE 1. Basic Connection Diagram, (a) Parallel Output, (b) Serial Output.

ADS7825

STARTING A CONVERSION

The combination of CS (pin 23) and R/C (pin 22) LOW for

a minimum of 40ns places the sample/hold of the ADS7825

in the hold state and starts conversion ‘n’. BUSY (pin 24)

will go LOW and stay LOW until conversion ‘n’ is com-

pleted and the internal output register has been updated. All

new convert commands during BUSY LOW will be ignored.

CS and/or R/C must go HIGH before BUSY goes HIGH or

a new conversion will be initiated without sufficient time to

acquire a new signal.

initiating a conversion. If, however, it is critical that CS or

R/C initiates conversion ‘n’, be sure the less critical input is

LOW at least 10ns prior to the initiating input. If EXT/INT

(pin 12) is LOW when initiating conversion ‘n’, serial data

from conversion ‘n – 1’ will be output on SDATA (pin 16)

following the start of conversion ‘n’. See Internal Data

Clock in the Reading Data section.

To reduce the number of control pins, CS can be tied LOW

using R/C to control the read and convert modes. This will

have no effect when using the internal data clock in the serial

output mode. However, the parallel output and the serial

output (only when using an external data clock) will be

affected whenever R/C goes HIGH. Refer to the Reading

Data section and Figures 2, 3, 5, and 6.

The ADS7825 will begin tracking the input signal at the end

of the conversion. Allowing 25µs between convert com-

mands assures accurate acquisition of a new signal. Refer to

Tables Ia and Ib for a summary of CS, R/C, and BUSY states

and Figures 2 through 6 and Table II for timing information.

CS and R/C are internally OR’d and level triggered. There

is not a requirement which input goes LOW first when

INPUTS

OUTPUTS

R/C

BYTE CONTC PWRD BUSY

COMMENTS

Hi-Z

D15

Hi-Z

D14

Hi-Z

D13

Hi-Z

D12

Hi-Z

D11

Hi-Z

D10

Hi-Z

Results from last

(MSB)

completed conversion.

Results from last

(LSB) completed conversion.

↑

↑↓

Data will change at the

end of a conversion.

TABLE Ia. Read Control for Parallel Data (PAR/SER = 5V.)

R/C

CONTC PWRD BUSY D7, D6, D5 EXT/INT SYNC DATACLK SDATA TAG

Input

Output

Input Output

I/O

Output Input COMMENTS

↓

Hi-Z

HI-Z

LOW

Output

Hi-Z

Output

Starts transmission of data from previous

conversion on SDATA synchronized to 16

pulses output on DATACLK.

↓

Hi-Z

LOW

Output

Starts transmission of data from previous

conversion on SDATA synchronized to 16

pulses output on DATACLK.

Hi-Z

HIGH

LOW

Input

Output

Input The level output on SDATA will be the level

input on TAG 16 DATACLK input cycles.

↑

Input At the end of the conversion, when BUSY

rises, data from the conversion will be shifted

into the output registers. If DATACLK is HIGH,

valid data will be lost.

↓

↑

↓

Hi-Z

HIGH

LOW

Input

Output

Initiates transmission of a HIGH pulse on

SYNC followed by data from last completed

conversion on SDATA synchronized to the

input on DATACLK.

Initiates transmission of a HIGH pulse on

SYNC followed by data from last completed

conversion on SDATA synchronized to the

input on DATACLK.

Output

Starts transmission of data from previous

conversion on SDATA synchronized to 16

pulses output on DATACLK

↓

↑

↓

Hi-Z

HIGH

LOW

Output

LOW

Input

Output

SDATA becomes active. Inputs on DATACLK

shift out data.

SDATA becomes active. Inputs on DATACLK

shift out data.

Output

Restarts continuous conversion mode (n – 1 data

transmitted when BUSY is LOW).

LOW

Restarts continuous conversion mode (n – 1 data

transmitted when BUSY is LOW).

TABLE Ib. Read Control for Serial Data (PAR/SER = 0V.)

ADS7825

t₁

R/C

t₃

t₄

BUSY

t₅

t₆

t₇

t₈

Convert

Acquire

Convert

t₁₂

Acquire

MODE

t₁₂

t₁₁

t₁₀

Parallel

Data Bus

High Byte Valid

Previous High

Byte Valid

Previous Low

Byte Valid

High Byte

Valid

Low Byte

Valid

High Byte

Valid

Hi-Z

Not Valid

Hi-Z

t₉

t₂

t₁₂

t₂₁

t₉

t₁₂

BYTE

FIGURE 2. Conversion Timing with Parallel Output (CS LOW).

t₂₁

R/C

t₁

t₃

t₄

BUSY

BYTE

t₂₁

DATA

BUS

Hi-Z State

High Byte Hi-Z State Low Byte

t₁₂t₉t₁₂

Hi-Z State

t₉

FIGURE 3. Using CS to Control Conversion and Read Timing with Parallel Outputs.

t₇+ t₈

CS or R/C⁽¹⁾

t₁₄

t₁₃

DATACLK

t₁₆

t₁₅

SDATA

BUSY

MSB Valid

Bit 14 Valid

Bit 13 Valid

Bit 1 Valid

LSB Valid

MSB Valid

Bit 14 Valid

Hi-Z

t₂₅

(Results from previous conversion.)

t₂₆

NOTE: (1) If controlling with CS, tie R/C LOW. If controlling with R/C, tie CS LOW.

FIGURE 4. Serial Data Timing Using Internal Data Clock (TAG LOW).

ADS7825

after the start of conversion ‘n’. Do not attempt to read data

beyond 12µs after the start of conversion ‘n’ until BUSY

(pin 24) goes HIGH; this may result in reading invalid data.

Refer to Table II and Figures 2 and 3 for timing constraints.

READING DATA

PARALLEL OUTPUT

To use the parallel output, tie PAR/SER (pin 20) HIGH. The

parallel output will be active when R/C (pin 22) is HIGH and

CS (pin 23) is LOW. Any other combination of CS and R/C

will tri-state the parallel output. Valid conversion data can be

read in two 8-bit bytes on D7-D0 (pins 9-13 and 15-17). When

BYTE (pin 21) is LOW, the 8 most significant bits will be

valid with the MSB on D7. When BYTE is HIGH, the 8 least

significant bits will be valid with the LSB on D0. BYTE can

be toggled to read both bytes within one conversion cycle.

SERIAL OUTPUT

When PAR/SER (pin 20) is LOW, data can be clocked out

serially with the internal data clock or an external data clock.

When EXT/INT (pin 12) is LOW, DATACLK (pin 15) is an

output and is always active regardless of the state of CS (pin

23) and R/C (pin 22). The SDATA output is active when

BUSY (pin 24) is LOW. Otherwise, it is in a tri-state

condition. When EXT/INT is HIGH, DATACLK is an input.

The SDATA output is active when CS is LOW and R/C is

HIGH. Otherwise, it is in a tri-state condition. Regardless of

the state of EXT/INT, SYNC (pin 13) is an output and always

active, while TAG (pin 17) is always an input.

Upon initial power up, the parallel output will contain

indeterminate data.

PARALLEL OUTPUT (After a Conversion)

After conversion ‘n’ is completed and the output registers

have been updated, BUSY (pin 24) will go HIGH. Valid data

from conversion ‘n’ will be available on D7-D0 (pins 9-13

and 15-17). BUSY going HIGH can be used to latch the

data. Refer to Table II and Figures 2 and 3 for timing

constraints.

INTERNAL DATA CLOCK (During A Conversion)

To use the internal data clock, tie EXT/INT (pin 12) LOW.

The combination of R/C (pin 22) and CS (pin 23) LOW will

initiate conversion ‘n’ and activate the internal data clock

(typically 900kHz clock rate). The ADS7825 will output 16

bits of valid data, MSB first, from conversion ‘n – 1’ on

SDATA (pin 16), synchronized to 16 clock pulses output on

PARALLEL OUTPUT (During a Conversion)

After conversion ‘n’ has been initiated, valid data from

conversion ‘n – 1’ can be read and will be valid up to 12µs

SYMBOL

t₁

DESCRIPTION

MIN

TYP

MAX

UNITS

µs

Convert Pulse Width

0.04

t₂

Start of Conversion to New Data Valid

Start of Conversion to BUSY LOW

BUSY LOW

t₃

t₄

t₅

End of Conversion to BUSY HIGH

Aperture Delay

t₆

t₇

Conversion Time

t₈

Acquisition Time

t₇+ t₈

t₉

Throughput Time

Bus Relinquish Time

t₁₀

t₁₁

t₁₂

t₁₃

t₁₄

t₁₅

t₁₆

t₁₇

t₁₈

t₁₉

t₂₀

t₂₁

t₂₂

t₂₃

t₂₄

t₂₅

t₂₆

t₂₇

t₂₈

t₂₉

t₃₀

Data Valid to BUSY HIGH

Start of Conversion to Previous Data Not Valid

Bus Access Time and BYTE Delay

Start of Conversion to DATACLK Delay

DATACLK Period

1.4

1.1

Data Valid to DATACLK HIGH

DATACLK LOW to Data Not Valid

External DATACLK Period

400

100

600

External DATACLK HIGH

External DATACLK LOW

CS LOW and R/C HIGH to External DATACLK HIGH (Enable Clock)

R/C to CS Setup Time

CS HIGH or R/C LOW to External DATACLK HIGH (Disable Clock)

DATACLK HIGH to SYNC HIGH

DATACLK HIGH to Valid Data

Start of Conversion to SDATA Active

End of Conversion to SDATA Tri-State

CS LOW and R/C HIGH to SDATA Active

CS HIGH or R/C LOW to SDATA Tri-State

BUSY HIGH to Address Valid

Address Valid to BUSY LOW

500

TABLE II. Conversion, Data, and Address Timing. T_A= –40°C to +85°C.

ADS7825

DATACLK (pin 15). The data will be valid on both the

rising and falling edges of the internal data clock. The rising

edge of BUSY (pin 24) can be used to latch the data. After

the 16th clock pulse, DATACLK will remain LOW until the

next conversion is initiated, while SDATA will go to what-

ever logic level was input on TAG (pin 17) during the first

clock pulse. The SDATA output will tri-state when BUSY

returns HIGH. Refer to Table II and Figure 4 for timing

information.

The first bit input on TAG will be valid on SDATA on the

18th falling edge and the 19th rising edge of DATACLK; the

second input bit will be valid on the 19th falling edge and the

20th rising edge, etc. With a continuous data clock, TAG

data will be output on DATA until the internal output

registers are updated with the results from the next conver-

sion. Refer to Table II and Figure 5 for timing information.

EXTERNAL DATA CLOCK (During a Conversion)

After conversion ‘n’ has been initiated, valid data from

conversion ’n-1’ can be read and will be valid up to 12µs

after the start of conversion ‘n’. Do not attempt to clock out

data from 12µs after the start of conversion ‘n’ until BUSY

(pin 24) rises; this will result in data loss.

EXTERNAL DATA CLOCK

To use an external clock, tie EXT/INT (pin 12) HIGH. The

external clock is not a conversion clock; it can only be used

as a data clock. To enable the output mode of the ADS7825,

CS (pin 23) must be LOW and R/C (pin 22) must be HIGH.

DATACLK must be HIGH for 20% to 70% of the total data

clock period; the clock rate can be between DC and 10MHz.

Serial data from conversion ‘n’ can be output on SDATA

(pin 16) after conversion ‘n’ is completed or during conver-

sion ‘n + 1’.

NOTE: For the best possible performance when using an

external data clock, data should not be clocked out during a

conversion. The switching noise of the asynchronous data clock

can cause digital feedthrough degrading the converter’s perfor-

mance. Refer to Table II and Figure 6 for timing information.

An obvious way to simplify control of the converter is to tie

CS LOW while using R/C to initiate conversions. While this

is perfectly acceptable, there is a possible problem when

using an external data clock. At an indeterminate point from

12µs after the start of conversion ‘n’ until BUSY rises, the

internal logic will shift the results of conversion ‘n’ into the

output register. If CS is LOW, R/C is HIGH and the external

clock is HIGH at this point, data will be lost. So, with CS

LOW, either R/C and/or DATACLK must be LOW during

this period to avoid losing valid data.

TAG FEATURE

TAG (pin 17) inputs serial data synchronized to the external

or internal data clock.

When using an external data clock, the serial bit stream input

on TAG will follow the LSB output on SDATA (pin 16)

until the internal output register is updated with new conver-

sion results. See Table II and Figures 5 and 6.

The logic level input on TAG for the first rising edge of the

internal data clock will be valid on SDATA after all 16 bits

of valid data have been output.

EXTERNAL DATA CLOCK (After a Conversion)

MULTIPLEXER TIMING

After conversion ‘n’ is completed and the output registers

have been updated, BUSY (pin 24) will go HIGH. With CS

LOW (pin 23) and R/C HIGH (pin 22), valid data from

conversion ‘n’ will be output on SDATA (pin 16) synchro-

nized to the external data clock input on DATACLK (pin

15). Between 15 and 35ns following the rising edge of the

first external data clock, the SYNC output pin will go HIGH

for one full data clock period (100ns minimum). The MSB

will be valid between 25 and 55ns after the rising edge of the

second data clock. The LSB will be valid on the 17th falling

edge and the 18th rising edge of the data clock. TAG (pin

17) will input a bit of data for every external clock pulse.

The four channel input multiplexer may be addressed manu-

ally or placed in a continuous conversion mode where all

four channels are sequentially addressed.

CONTINUOUS CONVERSION MODE (CONTC = 5V)

To place the ADS7825 in the continuous conversion mode,

CONTC (pin 25) must be tied HIGH. In this mode, acquisi-

tion and conversions will take place continually, cycling

through all four channels as long as CS, R/C and PWRD are

LOW (See Table III). Whichever address was last loaded

CONTC

R/C

BUSY

PWRD

A0 and A1 OPERATION

Inputs

Initiating conversion n latches in the levels input on A0 and A1 to select the channel for

conversion 'n + 1'.

↓

Inputs

Conversion in process. New convert commands ignored.

Initiates conversion on channel selected at start of previous conversion.

All analog functions powered down. Conversions in process or initiated will yield

meaningless data.

Outputs

The end of conversion 'n' (when BUSY rises) increments the internal channel latches and

outputs the channel address for conversion 'n + 1' on A0 and A1.

↓

Outputs

Conversion in process.

Restarts continuous conversion process on next input channel.

All analog functions powered down. Conversions in process or initiated will yield

meaningless data. Resets selected input channel for next conversion to AIN₀.

TABLE III. Conversion Control.

ADS7825

into the A0 and A1 registers (pins 19 and 18, respectively)

prior to CONTC being raised HIGH, becomes the first

address in the sequential continuous conversion mode (e.g.,

if Channel 1 was the last address selected then Channel 2

will follow, then Channel 3, and so on). The A0 and A1

address inputs become outputs when the device is in this

mode. When BUSY rises at the end of a conversion, A0 and

A1 will output the address of the channel that will be

converted when BUSY goes LOW at the beginning of the

next conversion. Data will be valid for the previous channel

when BUSY rises. See Table IVa and Figure 7 for channel

selection timing in continuous conversion mode.

conversions will proceed through each higher channel, cy-

cling back to zero after Channel 3.

If PWRD is held HIGH for a significant period of time, the

REF (pin 7) bypass capacitor may discharge (if the internal

reference is being utilized) and the CAP (pin 6) bypass

capacitor will discharge (for both internal and external

references). The continuous conversion mode should not be

enabled until the bypass capacitor(s) have recharged and

stabilized (1ms for 2.2µF capacitors recommended). In

addition, the continuous conversion mode should not be

enabled even with a short pulse on PWRD until the mini-

mum acquisition time has been met.

PWRD (pin 26) can be used to reset the multiplexer address

to zero. With the ADS7825 configured for no conversion,

PWRD can be taken HIGH for a minimum of 200ns. When

PWRD returns LOW, the multiplexer address will be reset

to zero. When the continuous conversion mode is enabled,

the first conversion will be done on channel 0. Subsequent

MANUAL CHANNEL SELECTION (CONTC= 0V)

The channels of the ADS7825 can be selected manually by

using the A0 and A1 address pins (pins 19 and 18, respec-

tively). See Table IVb for the multiplexer truth table and

Figure 8 for channel selection timing.

ADS7825 TIMING AND CONTROL

DATA AVAILABLE

FROM CHANNEL

CHANNEL TO BE OR

BEING CONVERTED

DESCRIPTION OF OPERATION

AIN₃

AIN₀

AIN₁

AIN₂

AIN₀

AIN₁

AIN₂

AIN₃

Channel being acquired or converted is output on these

address lines. Data is valid for the previous channel. These

lines are updated when BUSY rises.

TABLE IVa. A0 and A1 Outputs (CONTC HIGH).

CHANNEL SELECTED

WHEN BUSY GOES HIGH

DESCRIPTION OF OPERATION

AIN₀

AIN₁

AIN₂

AIN₃

Channel to be converted during conversion 'n + 1' is latched

when conversion 'n' is initiated (BUSY goes LOW). The selected

input starts being acquired as soon as conversion 'n' is done

(BUSY goes HIGH).

TABLE IVb. A0 and A1 Inputs (CONTC LOW).

Conversion Currently in Progress:

n – 2

n – 1

n + 1

n + 2

n + 3

n + 4

BUSY

Channel Address for Conversion:

n – 2 n – 1

A0, A1

(Output)

n + 2

t₂₉

n + 5

n + 4

Results from Conversion:

n – 3 n – 2

D7-D0

n – 1

n + 1

n + 2

n + 3

FIGURE 7. Channel Addressing in Continuous Conversion Mode (CONTC HIGH, CS and R/C LOW).

R/C

Conversion Currently in Progress:

n – 2

n – 1

n + 1

n + 2

n + 3

n + 4

n + 5

BUSY

Channel Address for Conversion:

n – 1 n + 1

A0, A1

(Input)

n + 2

t₃₀

Results from Conversion:

n – 3 n – 2

D7-D0

n – 1

n + 1

n + 2

n + 3

n + 4

FIGURE 8. Channel Addressing in Normal Conversion Mode (CONTC and CS LOW).

ADS7825

CDAC. Capacitor values larger than 2.2µF will have little

CALIBRATION

affect on improving performance.

The ADS7825 has no internal provision for correcting the

individual bipolar zero error or full-scale error for each

individual channel. Instead, the bipolar zero error of each

channel is guaranteed to be below a level which is quite

small for a 16-bit converter with a ±10V input range (slightly

more than ±32 LSBs). In addition, the channel errors should

match each other to within 16 LSBs.

The output of the buffer is capable of driving up to 1mA of

current to a DC load. Using an external buffer will allow the

internal reference to be used for larger DC loads and AC

loads. Do not attempt to directly drive an AC load with the

output voltage on CAP. This will cause performance degra-

dation of the converter.

For the full-scale error, the circuit of Figure 9 can be used.

This will allow the reference to be adjusted such that the

full-scale error for any single channel can be set to zero.

Again, the close matching of the channels will ensure that

the full-scale errors on the other channels will be small.

PWRD

PWRD (pin 26) HIGH will power down all of the analog

circuitry including the reference. Data from the previous

conversion will be maintained in the internal registers and

can still be read. With PWRD HIGH, a convert command

yields meaningless data. When PWRD is returned LOW,

adequate time must be provided in order for the capacitors

on REF (pin 7) and CAP (pin 6) to recharge. For 2.2µF

capacitors, a minimum recharge/settling time of 1ms is

recommended before the conversion results should be con-

sidered valid.

AIN₂

AIN₃

CAP

+5V

R₁

1MΩ

2.2µF

P₁

50kΩ

REF

LAYOUT

POWER

AGND2

The ADS7825 uses 90% of its power for the analog cir-

cuitry, and the converter should be considered an analog

component. For optimum performance, tie both power pins

to the same +5V power supply and tie the analog and digital

grounds together.

FIGURE 9. Full Scale Trim.

REFERENCE

The ADS7825 can operate with its internal 2.5V reference or

an external reference. By applying an external reference to

pin 7, the internal reference can be bypassed.

The +5V power for the converter should be separate from

the +5V used for the system’s digital logic. Connecting V_S1

and V_S2(pins 28 and 27) directly to a digital supply can

reduce converter performance due to switching noise from

the digital logic. For best performance, the +5V supply can

be produced from whatever analog supply is used for the rest

of the analog signal conditioning. If +12V or +15V supplies

are present, a simple +5V regulator can be used. Although it

is not suggested, if the digital supply must be used to power

the converter, be sure to properly filter the supply. Either

using a filtered digital supply or a regulated analog supply,

both V_S1and V_S2should be tied to the same +5V source.

REF

REF (pin 7) is an input for an external reference or the output

for the internal 2.5V reference. A 2.2µF capacitor should be

connected as close to the REF pin as possible. This capacitor

and the output resistance of REF create a low pass filter to

bandlimit noise on the reference. Using a smaller value

capacitor will introduce more noise to the reference degrad-

ing the SNR and SINAD. The REF pin should not be used

to drive external AC or DC loads.

GROUNDING

Three ground pins are present on the ADS7825. DGND is

the digital supply ground. AGND2 is the analog supply

ground. AGND1 is the ground which all analog signals

internal to the A/D are referenced. AGND1 is more suscep-

tible to current induced voltage drops and must have the path

of least resistance back to the power supply.

The range for the external reference is 2.3V to 2.7V and

determines the actual LSB size. Increasing the reference

voltage will increase the full scale range and the LSB size of

the converter which can improve the SNR.

CAP

All the ground pins of the A/D should be tied to an analog

ground plane, separated from the system’s digital logic

ground, to achieve optimum performance. Both analog and

digital ground planes should be tied to the ‘system’ ground

as near to the power supplies as possible. This helps to

prevent dynamic digital ground currents from modulating

the analog ground through a common impedance to power

ground.

CAP (pin 6) is the output of the internal reference buffer. A

2.2µF capacitor should be placed as close to the CAP pin as

possible to provide optimum switching currents for the

CDAC throughout the conversion cycle. This capacitor also

provides compensation for the output of the buffer. Using a

capacitor any smaller than 1µF can cause the output buffer

to oscillate and may not have sufficient charge for the

ADS7825

SIGNAL CONDITIONING

CROSSTALK

The FET switches used for the sample hold on many CMOS

A/D converters release a significant amount of charge injec-

tion which can cause the driving op amp to oscillate. The

amount of charge injection due to the sampling FET switch

on the ADS7825 is approximately 5-10% of the amount on

similar ADCs with the charge redistribution DAC (CDAC)

architecture. There is also a resistive front end which attenu-

ates any charge which is released. The end result is a

minimal requirement for the drive capability on the signal

conditioning preceding the A/D. Any op amp sufficient for

the signal in an application will be sufficient to drive the

ADS7825.

The worst-case channel-to-channel crosstalk versus input

frequency is shown in the Typical Performance Curves

section of this data sheet. With a full-scale 1kHz input

signal, worst case crosstalk on the ADS7825 is better than

–115dB. This should be adequate for even the most de-

manding applications. However, if crosstalk is a concern,

the following items should be kept in mind: The worst case

crosstalk is generally from channel 3 to 2. In addition,

crosstalk from Channel 3 to any other channel is worse than

from those channels to Channel 3. The reason for this is that

Channel 3 is nearer to the reference on the ADS7825. This

allows two coupling modes: channel-to-channel and Chan-

nel 3 to the reference. In general, when crosstalk is a

concern, avoid placing signals with higher frequency com-

ponents on Channel 3.

The resistive front end of the ADS7825 also provides a

guaranteed ±15V overvoltage protection. In most cases, this

eliminates the need for external overvoltage protection

circuitry.

The worst case crosstalk occurs from Channel 3 to Channel

2 as shown in the Crosstalk vs Input Frequency graph in the

Typical Performance Curves section. Other adjacent chan-

nels are typically several dB better than this while non-

adjacent channels are typically 10dB better. If a particular

channel should be as immune as possible from crosstalk,

channel 0 would be the best channel for the signal and

channel 1 should have the signal with the lowest frequency

content. If two signals are to have as little crosstalk as

possible, they should be placed on Channel 0 and Channel

2 with lower frequency, less-sensitive inputs on the other

channels.

INTERMEDIATE LATCHES

The ADS7825 does have tri-state outputs for the parallel

port, but intermediate latches should be used if the bus will

be active during conversions. If the bus is not active during

conversions, the tri-state outputs can be used to isolate the

A/D from other peripherals on the same bus.

Intermediate latches are beneficial on any monolithic A/D

converter. The ADS7825 has an internal LSB size of 38µV.

Transients from fast switching signals on the parallel port,

even when the A/D is tri-stated, can be coupled through the

substrate to the analog circuitry causing degradation of

converter performance.

If crosstalk is a concern for all channels, keep in mind that the

crosstalk graph shows crosstalk between any two channels.

Total crosstalk to any given channel is the sum of the

crosstalk contributions from all the other channels. Since non-

adjacent channels contribute very little, their contribution can

generally be ignored. A good approximation for absolute

worst case crosstalk would be to add 6dB to the highest curve

shown in the Crosstalk vs Input Frequency graph.

For an ADS7825 with proper layout, grounding, and bypass-

ing, the effect can be a few LSBs of error. In some cases, this

error can be treated as an increase in converter noise and

simply averaged out. In others, the error may not be random

and will produce an error in the conversion result, even with

averaging. Poor grounding, poor bypassing, and high-speed

digital signals will increase the magnitude of the errors—

possibly to many tens of LSBs.

ADS7825

PACKAGE OPTION ADDENDUM

www.ti.com

14-Oct-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

ADS7825U

ADS7825U/1K

ADS7825UB

ACTIVE

SOIC

RoHS & Green

Call TI

Level-3-260C-168 HR

-40 to 85

ADS7825U

Samples

1000 RoHS & Green

20 RoHS & Green

1000 RoHS & Green

Call TI

ADS7825U

ADS7825UB/1K

ACTIVE

SOIC

Call TI

Level-3-260C-168 HR

-40 to 85

ADS7825U

Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

14-Oct-2022

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADS7825U/1K

SOIC

1000

330.0

32.4

11.35 18.67

3.1

16.0

32.0

ADS7825UB/1K

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

ADS7825U/1K

SOIC

1000

367.0

55.0

ADS7825UB/1K

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TUBE

T - Tube

height

L - Tube length

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device

Package Name Package Type

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

ADS7825U

SOIC

507

12.83

5080

6.6

ADS7825UB

Pack Materials-Page 3

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