ADS7828-Q1_16 [TI]
12-Bit 8-Channel Sampling Analog-to-Digital Converter;
| 型号： | ADS7828-Q1_16 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12-Bit 8-Channel Sampling Analog-to-Digital Converter |
| 文件： | 总22页 (文件大小：340K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS7828-Q1
www.ti.com.......................................................................................................................................... SBAS456A –DECEMBER 2008–REVISED OCTOBER 2009
12-BIT 8-CHANNEL SAMPLING ANALOG-TO-DIGITAL CONVERTER
WITH I2C™ INTERFACE
Check for Samples: ADS7828-Q1
1
FEATURES
APPLICATIONS
•
•
•
•
•
Voltage-Supply Monitoring
Isolated Data Acquisition
Transducer Interfaces
Battery-Operated Systems
Remote Data Acquisition
2
•
Qualified for Automotive Applications
•
•
•
•
•
•
8-Channel Multiplexer
50-kHz Sampling Rate
No Missing Codes
2.7-V to 5-V Operation
Internal 2.5-V Reference
I2C™ Interface Supports Standard, Fast, and
High-Speed Modes
•
TSSOP-16 Package
DESCRIPTION
The ADS7828 is a single-supply low-power 12-bit data acquisition device that features a serial I2C interface and
an 8-channel multiplexer. The analog-to-digital (A/D) converter features a sample-and-hold amplifier and internal
asynchronous clock. The combination of an I2C serial 2-wire interface and micropower consumption makes the
ADS7828 ideal for applications requiring the A/D converter to be close to the input source in remote locations
and for applications requiring isolation. The ADS7828 is available in a TSSOP-16 package.
CH0
SAR
CH1
CH2
CH3
8-Channel
CH4
Multiplexer
S/H Amp
Comparator
CH5
CH6
CH7
COM
SDA
SCL
CDAC
Serial
Interface
A0
A1
2.5-V VREF
REFIN/REFOUT
Buffer
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
I2C is a trademark of NXP Semiconductors.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2009, Texas Instruments Incorporated
ADS7828-Q1
SBAS456A –DECEMBER 2008–REVISED OCTOBER 2009.......................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
MAXIMUM
INTEGRAL
LINEARITY ERROR
(LSB)
ORDERABLE
PART NUMBER
(2)
TA
PACKAGE
TOP-SIDE MARKING
±2
±1
ADS7828EIPWRQ1
ADS7828EBIPWRQ1
7828EI
–40°C to 85°C
TSSOP – PW
Reel of 2500
PREVIEW
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
+VDD
SDA
SCL
A1
A0
COM
REFIN/REFOUT
GND
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
GND
NO.
1
Analog input channel 0
Analog input channel 1
Analog input channel 2
Analog input channel 3
Analog input channel 4
Analog input channel 5
Analog input channel 6
Analog input channel 7
Analog ground
2
3
4
5
6
7
8
9
REFIN/REFOUT
10
11
12
13
14
15
16
Internal 2.5-V reference / external reference input
Common to analog input channel
Slave address bit 0
COM
A0
A1
Slave address bit 1
SCL
SDA
+VDD
Serial clock
Serial data
Power supply, 3.3 V (nominal)
2
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ABSOLUTE MAXIMUM RATINGS(1) (2)
over operating free-air temperature range (unless otherwise noted)
VDD
VIN
θJA
TA
Supply voltage
–0.3 V to 6 V
–0.3 V to (+VDD + 0.3 V)
108.4°C/W
Digital input voltage
Thermal impedance, junction to free air(3) (4)
Operating free-air temperature
Operating virtual-junction temperature
Storage temperature
–40°C to 85°C
150°C
TJ
Tstg
–65°C to 150°C
215°C
Vapor phase (60 seconds)
Infrared (15 seconds)
Tlead
Lead temperature during soldering
220°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to the GND terminal.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
(4) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can impact reliability.
ELECTROSTATIC DISCHARGE (ESD) RATINGS
TEST CONDITIONS
Human-Body Model (HBM)
RATING
2000 V
200 V
ESD
Electrostatic discharge rating
Machine Model (MM)
Charged-Device Model (CDM)
1000 V
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
NOM
MAX UNIT
2.7-V nominal
3.6
V
+VDD
Supply voltage
5-V nominal
4.75
–0.2
–0.2
5
5.25
Positive input
Negative input
+VDD + 0.2
V
0.2
VIN
Analog input voltage
Full-scale differential
(Positive input – Negative input)
0
VREF
V
V
VIN(RE
F)
Voltage reference input voltage
0.05
+VDD
VIH
High-level digital input voltage
Low-level digital input voltage
Operating free-air temperature
0.7 × +VDD
–0.3
+VDD + 0.5
0.3 × +VDD
85
V
V
VIL
TA
–40
°C
Copyright © 2008–2009, Texas Instruments Incorporated
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ELECTRICAL CHARACTERISTICS
+VDD = 2.7 V, VREF = 2.5 V, SCL clock frequency = 3.4 MHz (high-speed mode), over operating free-air temperature range
(unless otherwise noted)
ADS7828E
ADS7828EB
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
Analog Input
Ileak
Ci
Leakage current
Input capacitance
±1
25
±1
25
μA
pF
Overall Performance
No missing codes
Integral linearity error
Differential linearity error
Offset error
12
12
bits
±1 LSB(1)
±1
±1
±2
±0.5
±0.5 –1/+2 LSB
±1
±3
±1
±4
±1
±0.75
±0.2
±0.75
±0.2
33
±2 LSB
±1 LSB
±3 LSB
±1 LSB
μV
Offset error match
Gain error
±0.2
±1
Gain error match
±0.2
33
Vn
Noise
RMS
PSRR Power-supply ripple rejection
82
82
dB
Sampling Dynamics
High-speed mode: SCL = 3.4 MHz
Fast mode: SCL = 400 kHz
50
8
50
Throughput frequency
8
2
kHz
Standard mode: SCL = 100 kHz
2
Conversion time
6
6
μs
AC Accuracy
THD
Total harmonic distortion(2)
VIN = 2.5 VPP at 10 kHz
VIN = 2.5 VPP at 10 kHz
–82
72
–82
72
dB
dB
Signal-to- ratio
Signal-to-(noise+distortion)
ratio
VIN = 2.5 VPP at 10 kHz
71
71
dB
Spurious-free dynamic range VIN = 2.5 VPP at 10 kHz
Channel-to-channel isolation
86
86
dB
dB
120
120
Voltage Reference Output
VO
Output voltage
2.475
2.5 2.525 2.475
15
2.5 2.525
15
V
ppm/°
C
Internal reference drift
Internal reference on
Internal reference off
110
1
110
1
Ω
zo
IQ
Output impedance
Quiescent current
GΩ
μA
850
850
Voltage Reference Input
ri
Input resistance
Current drain
1
1
GΩ
μA
20
20
Digital Input/Output
VOL
IIH
Low-level output voltage
Minimum 3-mA sink current
VIH = +VDD + 0.5 V
VIL = –0.3 V
0.4
10
0.4
10
V
High-level input current
Low-level input current
μA
μA
IIL
–10
–10
(1) LSB means least significant bit; with VREF equal to 2.5 V, one LSB is 610 μV.
(2) THD is measured to the ninth harmonic.
4
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ELECTRICAL CHARACTERISTICS (continued)
+VDD = 2.7 V, VREF = 2.5 V, SCL clock frequency = 3.4 MHz (high-speed mode), over operating free-air temperature range
(unless otherwise noted)
ADS7828E
ADS7828EB
PARAMETER
Power Supply
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
High-speed mode: SCL = 3.4 MHz
Fast mode: SCL = 400 kHz
225
100
60
320
225
100
60
320
IQ
Quiescent current
Power dissipation
μA
Standard mode: SCL = 100 kHz
High-speed mode: SCL = 3.4 MHz
Fast mode: SCL = 400 kHz
675
300
180
70
1000
3000
675
300
180
70
1000
3000
PD
μW
Standard mode: SCL = 100 kHz
High-speed mode: SCL = 3.4 MHz
Fast mode: SCL = 400 kHz
Power-down current with
wrong address selected
25
25
μA
Standard mode: SCL = 100 kHz
SCL pulled high, SDA pulled high
6
6
IPD
Full power-down current
400
400
nA
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ELECTRICAL CHARACTERISTICS
+VDD = 5 V, VREF = External 5 V, SCL clock frequency = 3.4 MHz (high-speed mode), over operating free-air temperature
range (unless otherwise noted)
ADS7828E
ADS7828EB
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
Analog Input
Ileak
Ci
Leakage current
Input capacitance
±1
25
±1
25
μA
pF
Overall Performance
No missing codes
Integral linearity error
Differential linearity error
Offset error
12
12
bits
±1 LSB(1)
±1
±1
±1
±2
±0.5
±0.5 –1/+2 LSB
±3
±1.5
±3
±0.75
±2 LSB
±1 LSB
±2 LSB
±1 LSB
μV
Offset error match
Gain error
±1
±0.75
Gain error match
±1
Vn
Noise
RMS
33
82
33
82
PSRR Power-supply ripple rejection
dB
Sampling Dynamics
High-speed mode: SCL = 3.4 MHz
Fast mode: SCL = 400 kHz
50
8
50
Throughput frequency
8
2
kHz
Standard mode: SCL = 100 kHz
2
Conversion time
6
6
μs
AC Accuracy
THD
Total harmonic distortion(2)
VIN = 2.5 VPP at 10 kHz
VIN = 2.5 VPP at 10 kHz
–82
72
–82
72
dB
dB
Signal-to- ratio
Signal-to-(noise+distortion)
ratio
VIN = 2.5 VPP at 10 kHz
71
71
dB
Spurious-free dynamic range VIN = 2.5 VPP at 10 kHz
Channel-to-channel isolation
86
86
dB
dB
120
120
Voltage Reference Output
VO
Output voltage
2.475
2.5 2.525 2.475
15
2.5 2.525
15
V
ppm/°
C
Internal reference drift
Internal reference on
Internal reference off
110
1
110
1
Ω
zo
IQ
Output impedance
Quiescent current
GΩ
μA
1300
1300
Voltage Reference Input
ri
Input resistance
Current drain
1
1
GΩ
μA
20
20
Digital Input/Output
VOL
IIH
Low-level output voltage
Minimum 3-mA sink current
VIH = +VDD + 0.5 V
VIL = –0.3 V
0.4
10
0.4
10
V
High-level input current
Low-level input current
μA
μA
IIL
–10
–10
(1) LSB means least significant bit; with VREF equal to 5 V, one LSB is 1.22 mV.
(2) THD is measured to the ninth harmonic.
6
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ELECTRICAL CHARACTERISTICS (continued)
+VDD = 5 V, VREF = External 5 V, SCL clock frequency = 3.4 MHz (high-speed mode), over operating free-air temperature
range (unless otherwise noted)
ADS7828E
ADS7828EB
PARAMETER
Power Supply
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
High-speed mode: SCL = 3.4 MHz
Fast mode: SCL = 400 kHz
750
300
150
3.75
1.5
1000
750
300
150
3.75
1.5
1000
IQ
Quiescent current
Power dissipation
μA
Standard mode: SCL = 100 kHz
High-speed mode: SCL = 3.4 MHz
Fast mode: SCL = 400 kHz
5
5
PD
μW
Standard mode: SCL = 100 kHz
High-speed mode: SCL = 3.4 MHz
Fast mode: SCL = 400 kHz
0.75
400
150
35
0.75
400
150
35
Power-down current with
wrong address selected
μA
Standard mode: SCL = 100 kHz
SCL pulled high, SDA pulled high
IPD
Full power-down current
400
3000
400
3000
nA
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SWITCHING CHARACTERISTICS(1) (2)
+VDD = 2.7 V, over operating free-air temperature range (unless otherwise noted) (see Figure 1)
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
Standard mode
100
kHz
400
Fast mode
fSCL
SCL clock frequency
Cb = 100 pF max
Cb = 400 pF max
3.4
High-speed mode
MHz
1.7
Standard mode
Fast mode
4.7
1.3
4
Bus free time between Stop and Start
conditions
tBUF
μs
μs
ns
Standard mode
Fast mode
tHD; STA
Hold time (repeated) Start condition
Low period of the SCL clock
600
160
4.7
1.3
160
320
4
High-speed mode
Standard mode
Fast mode
μs
tlow
Cb = 100 pF max
Cb = 400 pF max
High-speed mode(3)
ns
Standard mode
Fast mode
μs
600
60
thigh
High period of the SCL clock
Cb = 100 pF max
Cb = 400 pF max
ns
High-speed mode(3)
120
4.7
600
160
250
100
10
Standard mode
Fast mode
μs
tSU; STA
Setup time for a repeated Start condition
Data setup time
ns
High-speed mode
Standard mode
Fast mode
tSU; DAT
ns
High-speed mode
Standard mode
Fast mode
0
3.45
μs
0
0.9
tHD; DAT
Data hold time
Cb = 100 pF max
Cb = 400 pF max
0
82
ns
High-speed mode(3) (4)
0
162
Standard mode
Fast mode
1000
20 + 0.1Cb
300
ns
trCL
Rise time of SCL signal
Cb = 100 pF max
Cb = 400 pF max
10
20
40
High-speed mode(3)
80
Standard mode
Fast mode
1000
20 + 0.1Cb
300
ns
Rise time of SCL signal after a repeated Start
condition and after an acknowledge bit
trCL1
Cb = 100 pF max
Cb = 400 pF max
10
20
80
High-speed mode(3)
160
300
Standard mode
Fast mode
20 + 0.1Cb
300
ns
tfCL
Fall time of SCL signal
Rise time of SDA signal
Cb = 100 pF max
Cb = 400 pF max
10
20
40
High-speed mode(3)
80
Standard mode
Fast mode
1000
20 + 0.1Cb
300
ns
trDA
Cb = 100 pF max
Cb = 400 pF max
10
20
80
High-speed mode(3)
160
(1) All values referred to VIH(MIN) and VIL(MAX) levels.
(2) Not production tested, except for the parameter tHD; DAT, data hold time, high-speed mode, Cb = 100 pF max.
(3) For bus line loads (CB) between 100 pF and 400 pF, the timing parameters must be linearly interpolated.
(4) A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH
signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.
8
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(1) (2)
SWITCHING CHARACTERISTICS
(continued)
+VDD = 2.7 V, over operating free-air temperature range (unless otherwise noted) (see Figure 1 )
PARAMETER
TEST CONDITIONS
Standard mode
MIN
MAX UNIT
300
Fast mode
20 + 0.1Cb
300
ns
tfDA
Fall time of SDA signal
Cb = 100 pF max
Cb = 400 pF max
10
20
80
High-speed mode(3)
160
Standard mode
Fast mode
4
μs
tSU; STO
Setup time for Stop condition
600
160
ns
High-speed mode
Cb
Capacitive load for SDA or SCL
Pulse width of spike suppressed
400
50
pF
ns
Fast mode
tSP
High-speed mode
10
Noise margin at the high level for each
connected device (including hysteresis)
VnH
VnL
0.2 × VDD
0.1 × VDD
V
V
Noise margin at the low level for each
connected device (including hysteresis)
SDA
tBUF
tHD;STA
tSP
tr
tf
tLOW
SCL
tSU;DAT
tHD;STA
tSU;STO
tHD;DAT
tSU;DAT
tHIGH
Stop
Start
Repeated
Start
Figure 1. I2C Timing
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TYPICAL CHARACTERISTICS
FREQUENCY SPECTRUM
INTEGRAL LINEARITY ERROR vs CODE
(2.5V Internal Reference)
(4096 Point FFT: fIN = 1 kHz, 0 dB)
2.00
1.50
0.00
–40.00
–80.00
–120.0
1.00
0.50
0.00
–0.50
–1.00
–1.50
–2.00
0
10
20
25
4095
4095
0
1024
2048
3072
4095
Output Code
Frequency (kHz)
DIFFERENTIAL LINEARITY ERROR vs CODE
(2.5-V Internal Reference)
INTEGRAL LINEARITY ERROR vs CODE
(2.5-V External Reference)
2.00
1.50
2.00
1.50
1.00
1.00
0.50
0.50
0.00
0.00
–0.50
–1.00
–1.50
–2.00
–0.50
–1.00
–1.50
–2.00
0
1024
2048
3072
0
1024
2048
3072
4095
Output Code
Output Code
DIFFERENTIAL LINEARITY ERROR vs CODE
(2.5-V External Reference)
CHANGE IN OFFSET vs TEMPERATURE
1.5
1.0
2.00
1.50
1.00
0.5
0.50
0.0
0.00
–0.5
–1.0
–1.5
–0.50
–1.00
–1.50
–2.00
–50
–25
0
25
50
75
100
0
1024
2048
3072
Temperature (°C)
Output Code
10
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TYPICAL CHARACTERISTICS (continued)
CHANGE IN GAIN vs TEMPERATURE
INTERNAL REFERENCE vs TEMPERATURE
1.5
1.0
2.51875
2.51250
2.50625
2.50000
2.49375
2.48750
2.48125
0.5
0.0
–0.5
–1.0
–1.5
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
POWER-DOWN SUPPLY CURRENT
vs TEMPERATURE
SUPPLY CURRENT vs TEMPERATURE
400
350
300
250
200
150
100
750
600
450
300
150
0
–150
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
SUPPLY CURRENT vs I2C BUS RATE
INTERNAL V
vs TURN-ON TIME
REF
100
80
60
40
20
0
300
250
200
150
100
50
No Cap
(42 µs)
12-Bit Settling
1-µF Cap
(1240 µs)
12-Bit Settling
0
0
200
400
600
800
1000
1200
1400
10
100
1k
10k
I2C Bus Rate (kHz)
Turn-On Time (µs)
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DEVICE INFORMATION
The ADS7828 is a classic Successive Approximation Register (SAR) A/D converter. The architecture is based on
capacitive redistribution which inherently includes a sample-and-hold function. The converter is fabricated on a
0.6μ CMOS process.
The ADS7828 core is controlled by an internally generated free-running clock. When the ADS7828 is not
performing conversions or being addressed, it keeps the A/D converter core powered off, and the internal clock
does not operate.
The simplified diagram of input and output for the ADS7828 is shown in Figure 2.
2.7 V to 3.6 V
5 W
+
1 µF to
10 µF
ADS7828
2 kW
2 kW
REFIN
/
VDD
+
REFOUT
0.1 µF
1 µF to
10 µF
Microcontroller
CH0
SDA
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
SCL
A0
A1
GND
Figure 2. Simplified I/O Diagram
Analog Input
When the converter enters the hold mode, the voltage on the selected CHx pin is captured on the internal
capacitor array. The input current on the analog inputs depends on the conversion rate of the device. During the
sample period, the source must charge the internal sampling capacitor (typically 25 pF). After the capacitor has
been fully charged, there is no further input current. The amount of charge transfer from the analog source to the
converter is a function of conversion rate.
Reference
The ADS7828 can operate with an internal 2.5-V reference or an external reference. If a 5-V supply is used, an
external 5-V reference is required in order to provide full dynamic range for a 0 V to +VDD analog input. This
external reference can be as low as 50 mV. When using a 2.7-V supply, the internal 2.5-V reference will provide
full dynamic range for a 0 V to +VDD analog input.
As the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. This is
often referred to as the LSB (least significant bit) size and is equal to the reference voltage divided by 4096. This
means that any offset or gain error inherent in the A/D converter will appear to increase, in terms of LSB size, as
the reference voltage is reduced.
The noise inherent in the converter will also appear to increase with lower LSB size. With a 2.5-V reference, the
internal noise of the converter typically contributes only 0.32 LSB peak-to-peak of potential error to the output
code. When the external reference is 50 mV, the potential error contribution from the internal noise is 50 times
larger—16 LSBs. The errors due to the internal noise are Gaussian in nature and can be reduced by averaging
consecutive conversion results.
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Digital Interface
The ADS7828 supports the I2C serial bus and data transmission protocol, in all three defined modes: standard,
fast, and high-speed. A device that sends data onto the bus is defined as a transmitter, and a device receiving
data as a receiver. The device that controls the message is called a master. The devices that are controlled by
the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL),
controls the bus access, and generates the Start and Stop conditions. The ADS7828 operates as a slave on the
I2C bus. Connections to the bus are made via the open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (see Figure 3):
•
•
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data
line while the clock line is high will be interpreted as control signals.
SDA
MSB
Slave Address
R/W
Direction
Bit
Acknowledgement
Signal from
Receiver
Acknowledgement
Signal from
Receiver
1
2
6
7
8
9
1
2
3-8
8
9
SCL
ACK
ACK
Start
Condition
Stop Condition
or Repeated
Start Condition
Repeated If More Bytes Are Transferred
Figure 3. Basic Operation
Accordingly, the following bus conditions have been defined:
•
•
•
•
Bus Not Busy
Both data and clock lines remain high.
Start Data Transfer
A change in the state of the data line, from high to low, while the clock is high, defines a Start condition.
Stop Data Transfer
A change in the state of the data line, from low to high, while the clock line is high, defines the Stop condition.
Data Valid
The state of the data line represents valid data, when, after a Start condition, the data line is stable for the
duration of the high period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of data
bytes transferred between Start and Stop conditions is not limited and is determined by the master device.
The information is transferred byte-wise and each receiver acknowledges with a ninth-bit.
Within the I2C bus specifications a standard mode (100-kHz clock rate), a fast mode (400-kHz clock rate), and
a highspeed mode (3.4-MHz clock rate) are defined. The ADS7828 works in all three modes.
•
Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each
byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of the acknowledge clock pulse. Of course, setup and
hold times must be taken into account. A master must signal an end of data to the slave by not generating an
acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the
data line high to enable the master to generate the Stop condition.
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Figure 3 shows how data transfer is accomplished on the I2C bus. Depending upon the state of the R/W bit, two
types of data transfer are possible:
•
Data transfer from a master transmitter to a slave receiver.
The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave
returns an acknowledge bit after the slave address and each received byte.
•
Data transfer from a slave transmitter to a master receiver.
The first byte, the slave address, is transmitted by the master. The slave then returns an acknowledge bit.
Next, a number of data bytes are transmitted by the slave to the master. The master returns an acknowledge
bit after all received bytes other than the last byte. At the end of the last received byte, a not-acknowledge is
returned.
The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended
with a Stop condition or a repeated Start condition. Since a repeated Start condition is also the beginning of the
next serial transfer, the bus will not be released.
The ADS7828 may operate in the following two modes:
•
Slave Receiver Mode
Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is
transmitted. Start and Stop conditions are recognized as the beginning and end of a serial transfer. Address
recognition is performed by hardware after reception of the slave address and direction bit.
•
Slave Transmitter Mode
The first byte (the slave address) is received and handled as in the slave receiver mode. However, in this
mode the direction bit will indicate that the transfer direction is reversed. Serial data is transmitted on SDA by
the ADS7828 while the serial clock is input on SCL. Start and Stop conditions are recognized as the
beginning and end of a serial transfer.
Address Byte
The address byte is the first byte received following the Start condition from the master device (see Figure 4).
The first five bits (MSBs) of the slave address are factory pre-set to 10010. The next two bits of the address byte
are the device select bits, A1 and A0. Input pins (A1-A0) on the ADS7828 determine these two bits of the device
address for a particular ADS7828. A maximum of four devices with the same pre-set code can therefore be
connected on the same bus at one time.
MSB
1
6
0
5
0
4
1
3
0
2
1
LSB
R/W
A1
A0
Figure 4. Address Byte
The A1/A0 address inputs can be connected to VDD or digital ground. The device address is set by the state of
these pins upon power-up.
The last bit of the address byte (R/W) defines the operation to be performed. When set to a 1, a read operation is
selected; when set to a 0, a write operation is selected. Following the Start condition, the ADS7828 monitors the
SDA bus, checking the device type identifier being transmitted. Upon receiving the 10010 code, the appropriate
device select bits, and the R/W bit, the slave device outputs an acknowledge signal on the SDA line.
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Command Byte
The operating mode is determined by a command byte (see Figure 5).
MSB
SD
6
5
4
3
2
1
LSB
X
C2
C1
C0
PD1
PD0
X
Figure 5. Command Byte
SD: Single-ended or differential inputs
0 = Differential inputs
1 = Single-ended inputs
C2 to C0: Channel selections (see Table 1)
PD1, PD0: Power-down selection (see Table 2)
X: Unused
Table 1. Channel Selection Control Addressed by Command Byte
COMMAND BYTE INPUTS
CHANNEL SELECTIONS
SD
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
C2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
C0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CH0
+IN
—
CH1
–IN
—
CH2
—
CH3
—
CH4
—
CH5
—
CH6
—
CH7
—
COM
—
—
+IN
—
–IN
—
—
—
—
—
—
—
+IN
—
–IN
—
—
—
—
—
—
—
—
+IN
—
–IN
—
—
–IN
—
+IN
—
—
—
—
—
—
–IN
—
+IN
—
—
—
—
—
—
—
—
–IN
—
+IN
—
—
—
—
—
—
—
—
–IN
—
+IN
—
—
+IN
—
—
—
—
—
—
–IN
–IN
–IN
–IN
–IN
–IN
–IN
–IN
—
+IN
—
—
—
—
—
—
—
—
—
+IN
—
—
—
—
—
—
—
—
—
+IN
—
—
—
+IN
—
—
—
—
—
—
—
—
+IN
—
—
—
—
—
—
—
—
—
+IN
—
—
—
—
—
—
—
—
—
+IN
Table 2. Power-Down Selection
PD1
PD0
DESCRIPTION
Power down between A/D converter conversions
Internal reference off and A/D converter on
Internal reference on and A/D converter off
Internal reference on and A/D converter on
0
0
1
1
0
1
0
1
Initiating Conversion
Provided the master has write-addressed it, the ADS7828 turns on the A/D converter section and begins
conversions when it receives bit 4 of the command byte shown in Figure 5. If the command byte is correct, the
ADS7828 returns an ACK condition.
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Reading Data
Data can be read from the ADS7828 by read addressing the part (LSB of address byte set to 1) and receiving
the transmitted bytes. Converted data can be read from the ADS7828 only after a conversion has been initiated
as described in the preceding section.
Each 12-bit data word is returned in two bytes (see Figure 6), where D11 is the MSB of the data word, and D0 is
the LSB. Byte 0 is sent first, followed by byte 1.
MSB
0
6
0
5
0
4
0
3
2
1
LSB
D8
Byte 0
Byte 1
D11
D3
D10
D2
D9
D1
D7
D6
D5
D4
D0
Figure 6. Reading Data
Reading in Fast or Standard (F/S) Mode
Figure 7 shows the interaction between the master and the slave ADS7828 in fast or standard (F/S) mode. At the
end of reading conversion data, the ADS7828 can be issued a repeated Start condition by the master to secure
bus operation for subsequent conversions of the A/D converter. This would be the most efficient way to perform
continuous conversions.
ADC Power-Down Mode
ADC Sampling Mode
S
1
0
0
1
0
A1 A0
W
A
SD C2 C1 C0 PD1 PD0
Command Byte
X
X
A
Write-Addressing Byte
ADC Converting Mode
ADC Power-Down Mode
(depending on power-down selection bits)
Sr
1
0
0
1
0
A1 A0
R
A
0
0
0
0
D11 D10 D9 D8
A
D7 D6...D1 D0
N
P
See Note (1)
Read-Addressing Byte
2 x (8 bits + ack/nack)
A = Acknowledge (SDA low)
N = Not acknowledge (SDA high)
S = Start condition
W = 0 (write)
R = 1 (read)
From Master to Slave
From Slave to Master
P = Stop condition
Sr = Repeated Start condition
NOTE: (1) To secure bus operation and loop back to the stage of write-addressing for next conversion, use Repeated Start.
Figure 7. Typical Read Sequence in F/S Mode
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Reading in High-Speed (HS) Mode
High Speed (HS) mode is fast enough that codes can be read out one at a time. In HS mode, there is not
enough time for a single conversion to complete between the reception of a repeated Start condition and the
read-addressing byte, so the ADS7828 stretches the clock after the read-addressing byte has been fully
received, holding it low until the conversion is complete.
See Figure 8 for a typical read sequence for HS mode. Included in the read sequence is the shift from F/S to HS
modes. It may be desirable to remain in HS mode after reading a conversion; to do this, issue a repeated Start
instead of a Stop at the end of the read sequence, since a Stop causes the part to return to F/S mode.
F/S Mode
S
0
0
0
0
1
X
X
X
N
HS Mode Master Code
HS Mode Enabled
ADC Power-Down Mode
ADC Sampling Mode
Sr
1
0
0
1
0
A1 A0
A
SD C2 C1 C0 PD1 PD0
Command Byte
X
X
A
W
Write-Addressing Byte
ADC Converting Mode
HS Mode Enabled
Sr
1
0
0
1
0
A1 A0
R
A
SCLH(2) is stretched low waiting for data conversion
Read-Addressing Byte
Return to F/S Mode(1)
HS Mode Enabled
ADC Power-Down Mode
(depending on power-down selection bits)
0
0
0
0
D11 D10 D9 D8
A
D7 D6...D1
D0
N
P
2 x (8 Bits + ack/not-ack)
A = Acknowledge (SDA low)
W = 0 (write)
R = 1 (read)
From Master to Slave
From Slave to Master
N = Not acknowledge (SDA high)
S = StartCondition
P = Stop Condition
Sr = Repeated Start condition
NOTES: (1) To remain in HS mode, use Repeated Start instead of Stop.
(2) SCLH is SCL in HS mode.
Figure 8. Typical Read Sequence in HS Mode
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Reading With Reference On/Off
The internal reference defaults to off when the ADS7828 power is on. To turn the internal reference on or off, see
Table 2. If the reference (internal or external) is constantly turned on and off, a proper amount of settling time
must be added before a normal conversion cycle can be started. The exact amount of settling time needed
varies depending on the configuration.
See Figure 9 for an example of the proper internal reference turn-on sequence before issuing the typical read
sequences required for the F/S mode when an internal reference is used.
Internal Reference
Turn-On
Settling Time
Internal ReferenceTurn-On Sequence
Wait until the required
settling time is reached
S
1
0
0
1
0
A1 A0
A
X
X
X
X
1
X
X
X
A
P
W
Write-Addressing Byte
Command Byte
Typical Read
Sequence(1)
in F/S Mode
Settled Internal Reference
ADC Power-Down Mode
ADC Sampling Mode
S
1
0
0
1
0
A1 A0
A
SD C2 C1 C0
1
PD0
X
X
A
W
Write-Addressing Byte
ADC Converting Mode
Command Byte
Settled Internal Reference
ADC Power-Down Mode
(depending on power-down selection bits)
Sr
1
0
0
1
0
A1 A0
R
A
0
0
0
0
D11 D10 D9 D8
A
D7 D6...D1 D0
N
P
See
Note (2)
Read-Addressing Byte
2 x (8 bits + ack/nack)
A = Acknowledge (SDA low)
W = 0 (write)
R = 1 (read)
From Master to Slave
From Slave to Master
N = Not acknowledge (SDA high)
S = Start condition
P = Stop condition
Sr = Repeated Start condition
NOTES: (1) Typical read sequences can be reused after the internal reference is settled.
(2) To secure bus operation and loop back to the stage of write-addressing for next conversion, use Repeated Start.
Figure 9. Internal Reference Turn-On Sequence and Typical Read Sequence (F/S Mode Shown)
When using an internal reference, there are three things that must be done:
1. To use the internal reference, the PD1 bit of Command Byte must always be set to logic 1 for each sample
conversion that is issued by the sequence, as shown in Figure 7.
2. To achieve 12-bit accuracy conversion when using the internal reference, the internal reference settling time
must be considered, as shown in the Internal VREF vs Turn-On Time Typical Characteristic plot. If the PD1
bit has been set to logic 0 while using the ADS7828, then the settling time must be reconsidered after PD1 is
set to logic 1. In other words, whenever the internal reference is turned on after it has been turned off, the
settling time must be long enough to get 12-bit accuracy conversion.
3. When the internal reference is off, it is not turned on until both the first Command Byte with PD1 = 1 is sent
and then a Stop condition or repeated Start condition is issued. (The actual turn-on time occurs once the
Stop or repeated Start condition is issued.) Any Command Byte with PD1 = 1 issued after the internal
reference is turned on serves only to keep the internal reference on. Otherwise, the internal reference would
be turned off by any Command Byte with PD1 = 0.
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The example in Figure 9 can be generalized for an HS mode conversion cycle by changing the timing of the
conversion cycle. If using an external reference, PD1 must be set to 0, and the external reference must be
settled. The typical sequence in Figure 7 or Figure 8 can then be used.
PCB Layout
For optimum performance, care should be taken with the physical layout of the ADS7828 circuitry. The basic
SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections,
and digital inputs that occur just prior to latching the output of the analog comparator. Therefore, during any
single conversion for an "n-bit" SAR converter, there are n "windows" in which large external transient voltages
can easily affect the conversion result. Such glitches might originate from switching power supplies, nearby
digital logic, and high-power devices.
With this in mind, power to the ADS7828 should be clean and well-bypassed. A 0.1-μF ceramic bypass capacitor
should be placed as close to the device as possible. A 1-μF to 10-μF capacitor may also be needed if the
impedance of the connection between +VDD and the power supply is high.
The ADS7828 architecture offers no inherent rejection of noise or voltage variation in regards to using an
external reference input. This is of particular concern when the reference input is tied to the power supply. Any
noise and ripple from the supply will appear directly in the digital results. While high-frequency noise can be
filtered out, voltage variation due to line frequency (50 Hz or 60 Hz) can be difficult to remove.
The GND pin should be connected to a clean ground point. In many cases, this will be the "analog" ground.
Avoid connections that are too near the grounding point of a microcontroller or digital signal processor. The ideal
layout will include an analog ground plane dedicated to the converter and associated analog circuitry.
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