ADS7829IBDRBTG4 [TI]
12 位高速 2.7V 微功耗采样模数转换器 | DRB | 8 | -40 to 85;
| 型号： | ADS7829IBDRBTG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12 位高速 2.7V 微功耗采样模数转换器 | DRB | 8 | -40 to 85 光电二极管 转换器 模数转换器 |
| 文件： | 总20页 (文件大小：477K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS7826
ADS7827
ADS7829
SLAS388–JUNE 2003
10/8/12-BIT HIGH SPEED 2.7 V microPOWER™ SAMPLING
ANALOG-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
•
High Throughput at Low Supply Voltage
(2.7 V VCC
– ADS7829: 12-bit 125 KSPS
– ADS7826: 10-bit 200 KSPS
– ADS7827: 8-bit 250 KSPS
The ADS7826/27/29 is a family of 10/8/12-bit sampling
analog-to-digital converters (A/D) with assured specifi-
cations at 2.7-V supply voltage. It requires very little
power even when operating at the full sample rate. At
lower conversion rates, the high speed of the device
enables it to spend most of its time in the power down
mode— the power dissipation is less than 60 µW at 7.5
kHz.
)
•
Very Wide Operating Supply VoltageL:
2.7 V to 5.25 V (as Low as 2.0 V With Reduced
Performance)
The ADS7826/27/29 also features operation from 2.0 V
to 5 V, a synchronous serial interface, and a differential
input. The reference voltage can be set to any level
•
•
•
Rail-to-Rail, Pseudo Differential Input
Wide Reference Voltage: 50 mV to VCC
within the range of 50 mV to VCC
.
Micropower Auto Power-Down:
– Less Than 60 µW at 75 kHz, 2.7 V VCC
Ultra-low power and small package size make the
ADS7826/27/29 family ideal for battery operated sys-
tems. It is also a perfect fit for remote data acquisition
modules, simultaneous multichannel systems, and iso-
lated data acquisition. The ADS7826/27/29 family is
available in a 3 x 3 8-pin PDSO (SON, same size as
QFN) package.
•
•
Low Power Down Current: 3 µA Max
Ultra Small Chip Scale Package:
8-pin 3 x 3 PDSO (SON, Same Size as QFN)
•
SPI™ Compatible Serial Interface
APPLICATIONS
•
•
•
•
Battery Operated Systems
Remote Data Acquisition
Isolated Data Acquisition
Simultaneous Sampling, Multichannel
Systems
Control
SAR
VREF
DOUT
+In
Serial
CDAC
Interface
DCLOCK
CS/SHDN
–In
Comparator
S/H Amp
microPOWER is a trademark of Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily in-
cludetestingofallparameters.
Copyright © 2003, Texas Instruments Incorporated
ADS7826
ADS7827
ADS7829
www.ti.com
SLAS388–JUNE 2003
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PACKAGE/ORDERING INFORMATION
MAXIMUM LINERARITY ERROR
SPECIFICATION
(LSB)
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA
(1)
(2)
PRODUCT
ADS7829I
ADS7829IB
ADS7826I
ADS7827I
ADS7829I
ADS7829IB
ADS7826I
ADS7827I
INTEGRAL
DIFFERENTIAL
PACKAGE
SON-8
SON-8
SON-8
SON-8
SON-8
SON-8
SON-8
SON-8
±2
±1.25
±1
±2
-1/1.25
±1
-40°C to 85°C
-40°C to 85°
F29
ADS7829IDRBR
ADS7829IBDRBR
ADS7826IDRBR
ADS7827IDRBR
ADS7829IDRBT
ADS7829IBDRBT
ADS7826IDRBT
ADS7827IDRBT
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
F29
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
F26
±1
±1
F27
±2
±2
F29
±1.25
±1
-1/1.25
±1
F29
F26
±1
±1
F27
(1)
(2)
For detail drawing and dimension table, see end of this data sheet or package drawing file on web.
Performance Grade information is marked on the reel.
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
VCC
6 V
-0.3 V to (VCC + 0.3 V)
-0.3 V to 6 V
100°C
Analog input
Logic input
Case temperature
Junction temperature
Storage temperature
External reference voltage
150°C
125°C
5.5 V
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
ADS7826
ADS7827
ADS7829
www.ti.com
SLAS388–JUNE 2003
SPECIFICATIONS
At -40°C to 85°C, VCC = 2.7 V, Vref = 2.5 V, unless otherwise specified.
ADS7829IB
TYP
ADS7829
TYP
ADS7826I
TYP
ADS7827I
TEST
CONDITIONS
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
TYP
MAX
ANALOG INPUT
Full-scale input
span
+In - (-In)
0
Vref
0
Vref
0
Vref
0
Vref
V
Absolute input
range
+In
-IN
-0.2
-0.2
VCC +0.2
1.0
-0.2
-0.2
VCC +0.2
1.0
-0.2
-0.2
VCC +0.2
1.0
-0.2
-0.2
VCC +0.2
1.0
V
V
Capacitance
25
25
25
25
pF
µA
Leakage current
±1
±1
±1
±1
SYSTEM PERFORMANCE
Resolution
12
12
10
8
Bits
Bits
No missing codes
Integral linearity error
Differential linearity error
Offset error
12
-1.25
-1
11
-2
-2
-3
-2
10
-1
-1
-2
-1
8
-1
-1
-1
-1
(1)
LSB
±0.4
±0.4
±0.3
±0.3
33
1.25
1.25
3
±0.8
±0.8
±0.6
±0.6
33
2
2
3
2
±0.3
±0.3
±0.4
±0.3
33
1
1
2
1
±0.2
±0.2
±0.4
±0.2
33
1
1
1
1
LSB
LSB
LSB
µVrms
dB
-3
Gain error
-2
2
Noise
Power supply rejection
SAMPLING DYNAMICS
Conversion time
82
82
94
98
12
12
10
8
DCLOCK
Cycles
Acquisition time
1.5
1.5
1.5
1.5
DCLOCK
Cycles
fDCLOCK
16 x fsample
16 x fsample
14 x fsample
12 x fsample
kHz
kHz
Throughput
(sample rate)
fsample
2.7 V ≤ VCC
(2)
125
75
125
75
200
85
250
100
≤ 5.25 V
2.0 V ≤ VCC
kHz
(3) (2)
< 2.7 V
DYNAMIC CHARACTERISTICS
Total harmonic distortion
-82
72
-80
70
-78
62
-72
50
dB
dB
SINAD
VIN = 2.5 Vpp at
1 kHz
Spurious free
dynamic range
(SFDR)
VIN = 2.5 Vpp at
1 kHz
85
82
81
68
dB
REFERENCE INPUT
Voltage range
Resistance
2.7 V ≤VCC≤3.6 V
0.05
VCC-0.2
0.05
VCC-0.2
0.05
VCC-0.2
0.05
VCC-0.2
V
CS = GND,
fSAMPLE = 0 Hz
5
5
5
5
GΩ
CS = VCC
Full speed at Vref/2
fSAMPLE = 7.5 kHz
CS = VCC
5
12
5
12
5
20
5
24
GΩ
µA
µA
µA
Current drain
60
3
60
3
100
3
120
3
0.8
0.8
0.8
0.8
0.001
0.001
0.001
0.001
DIGITAL INPUT/OUTPUT
Logic family
CMOS
CMOS
CMOS
CMOS
Logic levels
VIH
VIL
IIH = +5 µA
IIL = +5 µA
2.0
5.5
0.8
2.0
5.5
0.8
2.0
5.5
0.8
2.0
5.5
0.8
V
V
-0.3
-0.3
-0.3
-0.3
N
(1)
LSB means Least Significant Bit and is equal to Vref / 2 where N is the resolution of ADC. For example, with Vref equal to 2.5 V, one
LSB is 0.61 mV for a 12 bit ADC (ADS7829).
(2)
(3)
See the Typical Performance Curves for VCC = 5 V and Vref = 5 V.
The maximum clock rate of the ADS7826/27/29 are less than 1.2 MHz at 2 V ≤VCC <2.7 V. The recommended regerence voltage is
between 1.25 V to 1.024 V.
3
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ADS7826
ADS7827
ADS7829
www.ti.com
SLAS388–JUNE 2003
SPECIFICATIONS (continued)
At -40°C to 85°C, VCC = 2.7 V, Vref = 2.5 V, unless otherwise specified.
ADS7829IB
TYP
ADS7829
TYP
ADS7826I
TYP
ADS7827I
TYP
TEST
CONDITIONS
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
VOH
IOH = -250 µA
IOL = 250 µA
2.2
2.1
2.1
2.1
V
V
VOL
0.4
0.4
0.4
0.4
Data format
Straight binary
Straight binary
Straight binary
Straight binary
POWER SUPPLY REQUIREMENTS
VCC
Operating range
2.7
3.6
2.7
2.7
3.6
2.7
2.7
3.6
2.7
2.7
3.6
2.7
V
V
(3)
(2)
See
and
(2)
2.0
3.6
2.0
3.6
2.0
3.6
2.0
3.6
See
5.25
350
5.25
350
5.25
350
5.25
350
V
(4)
Quiescent cur-
rent
Full speed
220
20
220
20
250
20
260
20
µA
µA
fSAMPLE = 7.5 kHz
(5)
,
fSAMPLE = 7.5 kHz
(6)
180
180
180
180
µA
µA
Power down
CS = VCC
3
3
3
3
TEMPERATURE RANGE
Specified performance
-40
85
-40
85
-40
85
-40
85
°C
(4)
(5)
(6)
Full speed: 125 ksps for ADS7829, 200 ksps for ADS7826, and 250 ksps for ADS7827.
fDCLOCK = 1.2 MHz, CS = VCC for 145 clock cycles out of every 160 for the ADS7829I and ADS7829IB.
See the Power Dissipation section for more information regarding lower sample rates.
At -40°C to 85°C, VCC = 5 V, Vref = 5 V, unless otherwise specified.
ADS7829IB
ADS7829
TYP MAX
ADS7826I
MIN TYP MAX
ADS7827I
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP MAX
MIN
MIN
TYP MAX
SYSTEM PERFORMANCE
Resolution
12
12
10
8
Bits
Bits
No missing codes
Integral linearity error
Differential linearity error
ANALOG INPUT
Offset error
12
11
10
8
(7)
±0.6
±0.5
±0.8
±0.8
±0.15
±0.15
±0.1
±0.1
1
1
LSB
LSB
±2.6
±1.2
±2.6
±1.2
±1.2
±0.2
±0.7
±0.1
LSB
LSB
Gain error
REFERENCE INPUT
Voltage range
0.05
VCC
0.05
VCC
0.05
VCC
0.05
VCC
V
(7)
LSB means Least Significant Bit . With Vref equal to 5 V, one LSB is 1.22 mV for a 12 bit ADC.
4
ADS7826
ADS7827
ADS7829
www.ti.com
SLAS388–JUNE 2003
DEVICE INFORMATION
PIN DESCRIPTION
PDSO (SON−8) PACKAGE
(TOP VIEW)
REF
+IN
+VDD
8
7
6
5
1
DCLOCK
DOUT
2
−IN
3
4
GND
CS/ SHDN
Terminal Functions
PIN
1
NAME
DESCRIPTION
Vref
Reference input
2
+In
Noninverting input
3
-In
Inverting input. Connect to ground or to remote ground sense point.
Ground
4
GND
CS/SHDN
DOUT
5
Chip select when LOW, shutdown mode when HIGH
6
The serial output data word is comprised of 12 bits of data. In operation the data is valid
on the falling edge of DCLOCK. The second clock pulse after the falling edge of CS
enables the serial output. After one null bit, the data is valid for the next 12 edges.
7
8
DCLOCK
+VCC
Data Clock synchronizes the serial data transfer and determines conversion speed.
Power supply
5
www.ti.com
ADS7826
ADS7827
ADS7829
www.ti.com
SLAS388–JUNE 2003
TYPICAL CHARACTERISTICS
At TA = 25°C, VCC = 2.7 V, Vref = 25 V, (unless otherwise specified)
ADS7829 INTEGRAL LINEARITY
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
512
1024
1536
2048
2560
3072
3584
Decimal Code
Figure 1
ADS7826 INTEGRAL LINEARITY
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
128
256
384
512
640
768
896
Decimal Code
Figure 2
ADS7827 INTEGRAL LINEARITY
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
32
64
96
128
160
192
224
Decimal Code
Figure 3
6
ADS7826
ADS7827
ADS7829
www.ti.com
SLAS388–JUNE 2003
TYPICAL CHARACTERISTICS (continued)
At TA = 25°C, VCC = 2.7 V, Vref = 25 V, (unless otherwise specified)
ADS7829 DIFFERENTIAL LINEARITY
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
512
128
32
1024
1536
2048
Decimal Code
Figure 4
2560
3072
3584
ADS7826 DIFFERENTIAL LINEARITY
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
256
384
512
640
768
896
Decimal Code
Figure 5
ADS7827 DIFFERENTIAL LINEARITY
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
64
96
128
160
192
224
Decimal Code
Figure 6
7
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ADS7826
ADS7827
ADS7829
www.ti.com
SLAS388–JUNE 2003
TYPICAL CHARACTERISTICS (continued)
At TA = 25°C, VCC = 2.7 V, Vref = 25 V, (unless otherwise specified)
CHANGE IN MINIMUM INTEGRAL LINEARITY
CHANGE IN MAXIMUM INTEGRAL LINEARITY
vs
FREE-AIR TEMPERATURE
0.2
vs
FREE-AIR TEMPERATURE
0.2
0.15
0.1
0.15
0.1
ADS7829
ADS7826
ADS7826
0.05
0.05
0
0
−0.05
−0.1
ADS7827
−0.05
ADS7827
−0.1
−0.15
−0.2
ADS7829
−0.15
−0.2
−40
−20
0
20
40
60
80
−40
−20
0
20
40
60
80
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − ° C
Figure 7.
Figure 8.
CHANGE IN MINIMUM DIFFERENTIAL LINEARITY
vs
CHANGE IN MAXIMUM DIFFERENTIAL LINEARITY
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
0.4
0.4
0.3
0.3
0.2
ADS7826
0.2
ADS7827
0.1
0
0.1
ADS7827
0
ADS7826
−0.1
ADS7829
−0.1
−0.2
−0.2
ADS7829
−0.3
−0.3
−0.4
−0.4
−40
−20
0
20
40
60
80
−40
−20
20
40
60
80
0
T
A
− Free-Air Temperature − ° C
T
A
− Free-Air Temperature − ° C
Figure 9.
Figure 10.
CHANGE IN OFFSET ERROR
vs
FREE-AIR TEMPERATURE
CHANGE IN GAIN ERROR
vs
FREE-AIR TEMPERATURE
0.5
0.4
0.3
0.4
0.3
0.2
0.1
ADS7826
ADS7829
ADS7829
0.2
0.1
0
−0.1
−0.2
ADS7827
ADS7826
ADS7827
0
−0.1
−40
−20
0
20
40
60
80
−40
−20
0
20
40
60
80
T
A
− Free-Air Temperature − ° C
T
A
− Free-Air Temperature − ° C
Figure 11.
Figure 12.
8
ADS7826
ADS7827
ADS7829
www.ti.com
SLAS388–JUNE 2003
TYPICAL CHARACTERISTICS (continued)
At TA = 25°C, VCC = 2.7 V, Vref = 25 V, (unless otherwise specified)
CHANGE IN QUIESCENT CURRENT
vs
CHANGE IN MAXIMUM INTEGRAL LINEARITY
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
50
0.5
0.4
0.3
0.2
0.1
V
= 2.5 V
ref
40
30
20
10
ADS7829
ADS7827
0
−10
−20
−30
0
−0.1
−40
−50
ADS7826
4.2
−0.2
2.7
3.2
3.7
4.7
5.2
−40
−20
0
20
40
60
80
V
− Supply Voltage − V
T
A
− Free-Air Temperature − ° C
CC
Figure 13.
Figure 14.
CHANGE IN MINIMUM INTEGRAL LINEARITY
CHANGE IN MAXIMUM DIFFERENTIAL LINEARITY
vs
vs
SUPPLY VOLTAGE
0.2
SUPPLY VOLTAGE
0.3
V
ref
= 2.5 V
V
ref
= 2.5 V
0.1
0
0.2
0.1
ADS7829
ADS7827
ADS7826
−0.1
ADS7827
ADS7826
0
ADS7829
−0.2
−0.3
−0.1
−0.2
−0.3
−0.4
−0.5
2.7
3.2
3.7
4.2
4.7
5.2
2.7
3.2
3.7
4.2
4.7
5.2
V
− Supply Voltage − V
V
− Supply Voltage − V
CC
CC
Figure 15.
Figure 16.
CHANGE IN MINIMUM INTEGRAL LINEARITY
vs
CHANGE IN OFFSET ERROR
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
0.1
6
5
4
3
2
1
0
V
ref
= 2.5 V
0.08
0.06
0.04
0.02
0
V
ref
= 2.5 V
ADS7829
ADS7827
ADS7829
ADS7826
−0.02
−0.04
−0.06
ADS7826
ADS7827
−0.08
−0.1
2.7
3.2
3.7
4.2
4.7
5.2
2.7
3.2
3.7
4.2
4.7
5.2
V
− Supply Voltage − V
CC
V
− Supply Voltage − V
CC
Figure 17.
Figure 18.
9
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ADS7826
ADS7827
ADS7829
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SLAS388–JUNE 2003
TYPICAL CHARACTERISTICS (continued)
At TA = 25°C, VCC = 2.7 V, Vref = 25 V, (unless otherwise specified)
CHANGE IN GAIN
vs
SUPPLY VOLTAGE
CHANGE IN QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
1.2
200
180
160
140
120
100
ADS7827
V
= 2.5 V
ref
V
ref
= 2.5 V
1
ADS7826
ADS7829
0.8
0.6
0.4
ADS7829
80
60
40
20
0
ADS7826
ADS7827
4.2
0.2
0
2.7
3.2
3.7
4.2
4.7
5.2
2.7
3.2
3.7
4.7
5.2
V
− Supply Voltage − V
V
− Supply Voltage − V
CC
CC
Figure 19.
Figure 20.
ADS7829
REFERENCE CURRENT
vs
CHANGE IN OFFSET ERROR
vs
SAMPLE RATE
REFERENCE VOLTAGE
30
1.2
V
= 5 V
CC
1
25
20
15
10
0.8
0.6
0.4
0.2
0
-0.2
-0.4
5
0
-0.6
-0.8
0
25 50 75 100 125 150 175 200 225 250
1
2
3
4
5
Sample Rate − kHz
Reference Voltage - V
Figure 21.
Figure 22.
ADS7829
CHANGE IN GAIN ERROR
vs
ADS7829
PEAK-TO-PEAK NOISE
vs
REFERENCE VOLTAGE
REFERENCE VOLTAGE
2.5
10
V
= 5 V
V
= 5 V
CC
CC
9
8
7
2
1.5
1
0.5
0
6
5
4
3
2
-0.5
-1
1
0
-1.5
0
2
3
4
5
0.1
1
10
Reference Voltage - V
Reference Voltage - V
Figure 23.
Figure 24.
10
ADS7826
ADS7827
ADS7829
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SLAS388–JUNE 2003
TYPICAL CHARACTERISTICS (continued)
At TA = 25°C, VCC = 2.7 V, Vref = 25 V, (unless otherwise specified)
ADS7829
CHANGE IN INTEGRAL and
DIFFERENTIAL LINEARITY
vs
ADS7829
EFFECTIVE NUMBER OF BITS
vs
REFERENCE VOLTAGE
0.20
REFERENCE VOLTAGE
12
11.75
11.5
V
= 5 V
CC
V
= 5 V
CC
0.15
0.10
Change in Integral
Linearity - LSB
11.25
11
0.05
10.75
10.5
10.25
10
0
-0.05
-0.10
Change in Differential
Linearity - LSB
0.1
1
10
1
2
3
4
5
Reference Voltage - V
Reference Voltage - V
Figure 25.
Figure 26.
ADS7829
SPURIOUS FREE DYNAMIC RANGE
ADS7829
and SIGNAL-TO-NOISE RATIO
vs
SAMPLE FREQUENCY
100
SIGNAL-TO-NOISE + DISTORTION
vs
FREQUENCY
100
90
80
Spurious Free Dynamic Range
90
80
70
60
50
40
70
60
50
40
30
20
Signal-To-Noise
30
20
10
0
10
0
10
100
1000
1
10
100
1000
1
f - frequency - kHz
f − Frequency − kHz
Figure 27.
Figure 28.
ADS7826
ADS7829
SPURIOUS FREE DYNAMIC RANGE
TOTAL HARMONIC DISTORTION
and SIGNAL-TO-NOISE RATIO
vs
vs
FREQUENCY
FREQUENCY
100
0
-10
90
80
70
60
50
40
30
20
10
0
Spurious Free Dynamic Range
-20
-30
-40
-50
-60
-70
-80
Signal- To- Noise
-90
-100
1
10
100
1000
1
10
100
1000
f − Frequency − kHz
f - Frequency - kHz
Figure 29.
Figure 30.
11
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ADS7826
ADS7827
ADS7829
www.ti.com
SLAS388–JUNE 2003
TYPICAL CHARACTERISTICS (continued)
At TA = 25°C, VCC = 2.7 V, Vref = 25 V, (unless otherwise specified)
ADS7826
ADS7826
TOTAL HARMONIC DISTORTION
vs
SIGNAL-TO-NOISE + DISTORTION
vs
FREQUENCY
100
FREQUENCY
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
90
80
70
60
50
40
30
20
10
0
1
10
100
1000
1
10
100
1000
f - Frequency - kHz
f - frequency - kHz
Figure 31.
Figure 32.
ADS7827
SPURIOUS FREE DYNAMIC RANGE
ADS7827
and SIGNAL-TO-NOISE RATIO
SIGNAL-TO-NOISE + DISTORTION
vs
vs
FREQUENCY
FREQUENCY
100
100
80
80
60
40
20
0
Spurious Free Dynamic Range
60
40
Signal- To- Noise
20
0
10
100
1000
1
1
10
100
1000
f − Frequency − kHz
f - frequency - kHz
Figure 33.
Figure 34.
ADS7827
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
1
10
100
1000
f - Frequency - kHz
Figure 35.
12
ADS7826
ADS7827
ADS7829
www.ti.com
SLAS388–JUNE 2003
THEORY OF OPERATION
The ADS7826/27/29 is a family of micropower classic
The input current on the analog inputs depends on a
number of factors: sample rate, input voltage, source
impedance, and power down mode. Essentially, the
current into the ADS7826/27/29 family charges the
internal capacitor array during the sample period.
After this capacitance has been fully charged, there is
no further input current. The source of the analog
input voltage must be able to charge the input
capacitance (25 pF) to a 10/8/12-bit settling level
within 1.5 DCLOCK cycles. When the converter goes
into the hold mode or while it is in the power down
mode, the input impedance is greater than 1 GΩ.
successive
approximation
register
(SAR)
analog-to-digital (A/D) converters. The architecture is
based on capacitive redistribution which inherently
includes a sample/hold function. The converter is
fabricated on
a 0.6 µm CMOS process. The
architecture and process allow the ADS7826/27/29
family to acquire and convert an analog signal at up
to 200K/250K/125K conversions per second
respectively while consuming very little power.
The ADS7826/27/29 family requires an external
reference, an external clock, and a single power
source (VCC). The external reference can be any
voltage between 50 mV and VCC. The value of the
reference voltage directly sets the range of the
analog input. The reference input current depends on
the conversion rate of the ADS7826/27/29 family.
Care must be taken regarding the absolute analog
input voltage. To maintain the linearity of the
converter, the -In input should not drop below GND -
200 mV or exceed GND + 1 V. The +In input should
always remain within the range of GND - 200 mV to
VCC + 200 mV. Outside of these ranges, the
converter’s linearity may not meet specifications.
The minimum external clock input to DCLOCK can be
as low as 10 kHz. The maximum external clock
frequency is 2 MHz for ADS7829, 2.8 MHz for
ADS7826 and 3 MHz for ADS7827 respectively. The
duty cycle of the clock is essentially unimportant as
long as the minimum high and low times are at least
400 ns (VCC = 2.7 V or greater). The minimum
DCLOCK frequency is set by the leakage on the
capacitors internal to the ADS7826/27/29 family.
REFERENCE INPUT
The external reference sets the analog input range.
The ADS7826/27/29 family operates with a reference
in the range of 50 mV to VCC. There are several
important implications of this.
As the reference voltage is reduced, the analog
voltage weight of each digital output code is reduced.
This is often referred to as the LSB (least significant
bit) size and is equal to the reference voltage divided
by 2N (where N is 12 for ADS7829, 10 for ADS7826,
and 8 for ADS7827). This means that any offset or
gain error inherent in the A/D converter appears to
increase, in terms of LSB size, as the reference
voltage is reduced.
The analog input is provided to two input pins: +In
and -In. When a conversion is initiated, the differential
input on these pins is sampled on the internal
capacitor array. While a conversion is in progress,
both inputs are disconnected from any internal
function.
The digital result of the conversion is clocked out by
the DCLOCK input and is provided serially, most
significant bit first, on the DOUT pin. The digital data
that is provided on the DOUT pin is for the conversion
currently in progress—there is no pipeline delay.
The noise inherent in the converter also appears to
increase with lower LSB size. With a 2.5 V reference,
the internal noise of the converter typically contributes
only 0.32 LSB peak-to-peak of potential error to the
output code. When the external reference is 50 mV,
the potential error contribution from the internal noise
is 50 times larger —16 LSBs. The errors due to the
internal noise are gaussian in nature and can be
reduced by averaging consecutive conversion results.
ANALOG INPUT
The +In and -In input pins allow for a differential input
signal. Unlike some converters of this type, the -In
input is not re-sampled later in the conversion cycle.
When the converter goes into the hold mode, the
voltage difference between +In and -In is captured on
the internal capacitor array.
For more information regarding noise, consult the
typical performance curves Effective Number of Bits
vs Reference Voltage and Peak-to-Peak Noise vs
Reference Voltage (only curves for ADS7829 are
shown). Note that the effective number of bits
(ENOB) figure is calculated based on the converter’s
signal-to-(noise + distortion) ratio with a 1 kHz, 0 dB
input signal. SINAD is related to ENOB as follows:
The range of the -In input is limited to -0.2 V to 1 V.
Because of this, the differential input can be used to
reject only small signals that are common to both
inputs. Thus, the -In input is best used to sense a
remote signal ground that may move slightly with
respect to the local ground potential.
13
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ADS7826
ADS7827
ADS7829
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SLAS388–JUNE 2003
Serial Interface
SINAD = 6.02 × ENOB + 1.76
The ADS7826/27/29 family communicates with
microprocessors and other digital systems via a
synchronous 3-wire serial interface. Timings for
ADS7829 are shown in Figure 36 and Table 1. The
DCLOCK signal synchronizes the data transfer with
each bit being transmitted on the falling edge of
DCLOCK. Most receiving systems capture the
bitstream on the rising edge of DCLOCK. However, if
the minimum hold time for DOUT is acceptable, the
system can use the falling edge of DCLOCK to
capture each bit.
With lower reference voltages, extra care should be
taken to provide a clean layout including adequate
bypassing,
a clean power supply, a low-noise
reference, and a low-noise input signal. Because the
LSB size is lower, the converter is more sensitive to
external sources of error such as nearby digital
signals and electromagnetic interference.
DIGITAL INTERFACE
Signal Levels
The digital inputs of the ADS7826/27/29 family can
accommodate logic levels up to 6 V regardless of the
value of VCC. Thus, the ADS7826/27/29 family can be
powered at 3 V and still accept inputs from logic
powered at 5 V.
The timings for ADS7826 and ADS7827 serial
interface are shown in Figure 37 and Table 1. The
DCLOCK signal synchronizes the data transfer with
each bit being transmitted on the falling edge of
DCLOCK. Most receiving systems capture the
bitstream on the rising edge of DCLOCK. However, if
the minimum hold time for DOUT is acceptable, athe
system can use the fallng edge of DCLOCK to
capture each bit.
The CMOS digital output (DOUT) swings 0 V to VCC. If
VCC is 3 V and this output is connected to a 5-V
CMOS logic input, then that IC may require more
supply current than normal and may have a slightly
longer propagation delay.
t
CYC
CS/SHDN
DCLOCK
Power
Down
t
SU(CS)
t
CSD
Null
Bit
Null
Bit
Hi-Z
Hi-Z
1
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
(MSB)
B11 B10 B9 B8
D
OUT
t
CONV
t
t
DATA
SMPL
After completing the data transfer, if further clocks are applied with CS LOW, the A/D outputs LSB-First data then
followed with zeroes indefinitely.
Figure 36. ADS7829 Timing
t
CYC
CS/SHDN
Power
Down
t
SU(CS)
DCLOCK
ADS7826
t
CSD
Null
Bit
Null
Hi-Z
Hi-Z
Hi-Z
Bit
1
1
B9 B8
B7 B6
B4 B3 B2 B1 B0
D
OUT
(MSB)
MSB
MSB
Null
Bit
Null
Bit
ADS7827
Hi-Z
B4 B3 B2 B1 B0
D
OUT
(MSB)
t
CONV
t
SMPL
Figure 37. ADS7826 and ADS7827 Timing
14
ADS7826
ADS7827
ADS7829
www.ti.com
SLAS388–JUNE 2003
Table 1. Timing Specifications (VCC = 2.7 V and Above -40°C to 85°C
SYMBOL
tSAMPLE
DESCRIPTION
MIN
TYP MAX
2.0
UNIT
Analog input sample time
1.5
DCLOCK
Cycles
tCONV
Conversion time
Cycle time
ADS7829I or ADS7829IB
ADS7826I
12
11
9
DCLOCK
Cycles
ADS7827I
tCYC
ADS7829I or ADS7829IB
ADS7826
16
14
12
DCLOCK
Cycles
ADS7827
tCSD
tSU(CS)
th(DO)
td(DO)
tdis
CS falling to DCLOCK LOW
CS falling to DCLOCK rising
DCLOCK falling to current DOUT not valid
DCLOCK falling to next DOUT valid
CS rising to DOUT 3-state
DCLOCK falling to DOUT enabled
DOUT fall time
0
ns
ns
ns
ns
ns
ns
ns
ns
30
15
130 200
40 80
ten
75 175
90 200
110 220
tf
tr
DOUT rise time
A falling CS signal initiates the conversion and data
transfer. The first 1.5 to 2.0 clock periods of the
conversion cycle are used to sample the input signal.
After the second falling DCLOCK edge, DOUT is
enabled and outputs a LOW value for one clock
period. For the next N (N is 12 for ADS7829, 10 for
ADS7826, and 8 for ADS7827) DCLOCK periods,
DOUT outputs the conversion result, most significant
bit first. After the least significant bit has been sent,
DOUT goes to 3-state after the rising edge of CS. A
new conversion is initiated only when CS has been
taken high and returned low again.
DATA FORMAT
The output data from the ADS7826/27/29 family is in
straight binary format. ADS7829 out is shown in
Table 2, as an example. This table represents the
ideal output code for the given input voltage and does
not include the effects of offset, gain error, or noise.
For ADS7826 the last two LSB’s are don’t cares,
while for ADS7827 the last four LSB’s are don’t
cares.
Table 2. Ideal Input Voltages and Output Codes (ADS7829 Shown as an Example)
DESCRIPTION
FULL SCALE RANGE
LEAST SIGNIFICANT BIT (LSB)
Full scale
ANALOG VALUE
Vref
DIGITAL OUTPUT
STRAIGHT BINARY
Vref/4096
Vref - 1 LSB
Vref/2
BINARY CODE
HEX CODE
FFF
1111 1111 1111
1000 0000 0000
0111 1111 1111
0000 0000 0000
Midscale
800
Midscale - 1 LSB
Zero
Vref/2 - 1 LSB
0 V
7FF
000
15
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ADS7826
ADS7827
ADS7829
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SLAS388–JUNE 2003
1.4 V
V
V
3 kW
OH
D
OUT
D
OL
OUT
Test Point
t
t
f
r
100 pF
C
LOAD
Voltage Waveforms for D
Rise and Fall Times, t , t
r f
OUT
Load Circuit for t
, t , and t
r
dDO
f
Test Point
V
DCLOCK
IL
V
CC
t
Waveform 2, t
dis en
3 kW
t
h(DO)
D
OUT
V
V
OH
t
Waveform 1
dis
D
100 pF
OUT
C
LOAD
OL
t
h(DO)
Voltage Waveforms for D
Delay Times, t
Load Circuit for t and t
dis en
OUT
dDO
CS/SHDN
V
IH
CS/SHDN
DCLOCK
D
OUT
(1)
1
2
90%
Waveform 1
t
dis
D
D
V
OL
B11
OUT
(2)
OUT
10%
Waveform 2
t
en
Voltage Waveforms for t
Voltage Waveforms for t
dis
en
(1) Waveform 1 is for an output with internal conditions such that the output is HIGH unless disabled by the output control.
(2) Waveform 2 is for an output with internal conditions such that the output is LOW unless disabled by the output control.
Figure 38. Timing Diagrams and Test Circuits for the Parameters in Table 1.
POWER DISSIPATION
The architecture of the converter, the semiconductor
This way, the converter spends the longest possible
time in the power down mode. This is very important
as the converter not only uses power on each
DCLOCK transition (as is typical for digital CMOS
components) but also uses some current for the
analog circuitry, such as the comparator. The analog
section dissipates power continuously, until the
power-down mode is entered.
fabrication process, and a careful design allows the
ADS7826/27/29 family to convert at the full sample
rate while requiring very little power. But, for the
absolute lowest power dissipation, there are several
things to keep in mind.
The power dissipation of the ADS7826/27/29 family
scales directly with conversion rate. Therefore, the
first step to achieving the lowest power dissipation is
to find the lowest conversion rate that satisfies the
requirements of the system.
The current consumption of the ADS7826/27/29
family versus sample rate. For this graph, the
converter is clocked at maximum DCLOCK rate
regardless of the sample rate —CS is HIGH for the
remaining sample period. Figure 4 also shows current
consumption versus sample rate. However, in this
case, the minimum DCLOCK cylce time is used—CS
is HIGH for one DCLOCK cycle.
In addition, the ADS7826/27/29 family is in power
down mode under two conditions: when the
conversion is complete and whenever CS is HIGH.
Ideally, each conversion occurs as quickly as
possible, preferably, at DCLOCK rate.
16
ADS7826
ADS7827
ADS7829
www.ti.com
SLAS388–JUNE 2003
There is an important distinction between the power
down mode that is entered after a conversion is
complete and the full power-down mode which is
enabled when CS is HIGH. While both shutdown the
analog section, the digital section is completely
shutdown only when CS is HIGH. Thus, if CS is left
LOW at the end of a conversion and the converter is
continually clocked, the power consumption is not as
low as when CS is HIGH.
The reference should be similarly bypassed with a
0.1-µF capacitor. Again, a series resistor and large
capacitor can be used to lowpass filter the reference
voltage. If the reference voltage originates from an
op-amp, be careful that the op-amp can drive the
bypass capacitor without oscillation (the series
resistor can help in this case). Keep in mind that
while the ADS7826/27/29 family draws very little
current from the reference on average, there are still
instantaneous current demands placed on the
external reference circuitry.
Power dissipation can also be reduced by lowering
the power supply voltage and the reference voltage.
The ADS7826/27/29 family operates over a VCC
range of 2.0 V to 5.25 V. However, at voltages below
2.7 V, the converter does not run at the maximum
sample rate. See the typical performance curves for
more information regarding power supply voltage and
maximum sample rate.
Also, keep in mind that the ADS7826/27/29 family
offers no inherent rejection of noise or voltage
variation in regards to the reference input. This is of
particular concern when the reference input is tied to
the power supply. Any noise and ripple from the
supply appears directly in the digital results. While
high frequency noise can be filtered out as described
in the previous paragraph, voltage variation due to
the line frequency (50 Hz or 60 Hz), can be difficult to
remove.
LAYOUT
For optimum performance, care should be taken with
the physical layout of the ADS7826/27/29 family
circuitry. This is particularly true if the reference
voltage is low and/or the conversion rate is high. At a
The GND pin on the ADS7826/27/29 family must be
placed on a clean ground point. In many cases, this
is the analog ground. Avoid connecting the GND pin
too close to the grounding point for a microprocessor,
microcontroller, or digital signal processor. If needed,
run a ground trace directly from the converter to the
power supply connection point. The ideal layout
includes an analog ground plane for the converter
and associated analog circuitry.
125-kHz to
250-kHz
conversion
rate,
the
ADS7826/27/29 family makes a bit decision every
800 ns to 400 ns. That is, for each subsequent bit
decision, the digital output must be updated with the
results of the last bit decision, the capacitor array
appropriately switched and charged, and the input to
the comparator settled, for example the ADS7829, to
a 12-bit level all within one clock cycle.
APPLICATION CIRCUITS
The basic SAR architecture is sensitive to spikes on
the power supply, reference, and ground connections
that occur just prior to latching the comparator output.
Thus, during any single conversion for an n-bit SAR
converter, there are n windows in which large
external transient voltages can easily affect the
conversion result. Such spikes might originate from
switching power supplies, digital logic, and high
power devices, to name a few. This particular source
of error can be very difficult to track down if the glitch
is almost synchronous to the converter’s DCLOCK
signal—as the phase difference between the two
changes with time and temperature, causing sporadic
misoperation.
Figure 39 and Figure 40 show some typical
application circuits the ADS7826/27/29 family. Figure
39 uses an ADS7826/27/29 and a multiplexer to
provide for a flexible data acquisition circuit. A
resistor string provides for various voltages at the
multiplexer input. The selected voltage is buffered
and driven into Vref. As shown in Figure 39, the input
range of the ADS7826/27/29 family programmable to
100 mV, 200 mV, 300 mV, or 400 mV. The 100-mV
range would be useful for sensors such as
thermocouple shown.
Figure 39 shows a basic data acquisition system. The
ADS7826/27/29 family input range is 0 V to VCC, as
the reference input is connected directly to the power
supply. The 5-Ω resistor and 1-µF to 10-µF capacitor
filters the microcontroller noise on the supply, as well
as any high-frequency noise from the supply itself.
The exact values should be picked such that the filter
provides adequate rejection of the noise.
With this in mind, power to the ADS7826/27/29 family
should be clean and well bypassed. A 0.1-µF ceramic
bypass capacitor should be placed as close to the
ADS7826/27/29 family package as possible. In
addition, a 1-µ to 10-µF capacitor and a 5-Ω or 10-Ω
series resistor may be used to lowpass filter a noisy
supply.
17
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ADS7826
ADS7827
ADS7829
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SLAS388–JUNE 2003
+3 V
+3 V
+3 V
R8
26 kΩ
0.4 V
0.3 V
R7
5 Ω
R9
1 kΩ
R1
OPA237
C2
1
U2
R3
500 kΩ
0.1 µ F
R10
1 kΩ
C1
10 µ F
MUX
R6
1 MΩ
R2
59 kΩ
VREF
0.2 V
0.1 V
DCLOCK
R11
1 kΩ
DOUT
C3
0.1 µ
TC1
ADS7826/27/29
A0
F
TC2
TC3
CS/SHDN
A1
Thermocouple
R12
1 kΩ
U1
C4
10 µ F
R4
1 kΩ
U3
C5
0.1 µ
R5
500 Ω
F
µP
ISO Thermal Block
U4
Figure 39. Thermocouple Application Using a MUX to Scale the Input Range of the ADS7826/27/29 family
+2.7V to +3.6V
5 W
+
1 mF to
10 mF
ADS7826/27/29
V
V
CC
REF
+
1 mF to
10 mF
0.1 mF
Microcontroller
+In
CS
–In
D
OUT
DCLOCK
GND
Figure 40. Basic Data Acquisition System
18
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