ADS7844NG4 [TI]
12 位 8 通道串行输出采样模数转换器 | DB | 20;
| 型号： | ADS7844NG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12 位 8 通道串行输出采样模数转换器 | DB | 20 光电二极管 转换器 模数转换器 |
| 文件： | 总24页 (文件大小：648K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS7844
A
D
S
7
8
4
4
ADS7844
SBAS100A – JANUARY 1998 – REVISED OCTOBER 2003
12-Bit, 8-Channel Serial Output Sampling
ANALOG-TO-DIGITAL CONVERTER
DESCRIPTION
FEATURES
ꢀ SINGLE SUPPLY: 2.7V to 5V
The ADS7844 is an 8-channel, 12-bit sampling analog-to-
digital converter (ADC) with a synchronous serial interface.
Typical power dissipation is 3mW at a 200kHz throughput
rate and a +5V supply. The reference voltage (VREF) can be
varied between 100mV and VCC, providing a corresponding
input voltage range of 0V to VREF. The device includes a
shutdown mode that reduces power dissipation to under
1µW. The ADS7844 is ensured down to 2.7V operation.
ꢀ 8-CHANNEL SINGLE-ENDED OR
4-CHANNEL DIFFERENTIAL INPUT
ꢀ UP TO 200kHz CONVERSION RATE
ꢀ ±1 LSB MAX INL AND DNL
ꢀ NO MISSING CODES
ꢀ 72dB SINAD
Low power, high speed, and onboard multiplexer make the
ADS7844 ideal for battery-operated systems such as personal
digital assistants, portable multichannel data loggers, and
measurement equipment. The serial interface also provides
low-cost isolation for remote data acquisition. The ADS7844
is available in a 20-lead QSOP package and the MAX147
equivalent 20-lead SSOP package and is ensured over the
–40°C to +85°C temperature range.
ꢀ SERIAL INTERFACE
ꢀ 20-LEAD QSOP AND
20-LEAD SSOP PACKAGES
ꢀ ALTERNATE SOURCE FOR MAX147
APPLICATIONS
ꢀ DATA ACQUISITION
ꢀ TEST AND MEASUREMENT
ꢀ INDUSTRIAL PROCESS CONTROL
ꢀ PERSONAL DIGITAL ASSISTANTS
ꢀ BATTERY-POWERED SYSTEMS
CH0
CH1
CH2
SAR
DCLK
Eight
Channel
Multiplexer
CH3
CS
CH4
Comparator
SHDN
DIN
Serial
Interface
and
CH5
CH6
CH7
COM
VREF
CDAC
Control
DOUT
BUSY
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1998-2003, Texas Instruments Incorporated
www.ti.com
SPECIFICATION: +5V
At TA = –40°C to +85°C, +VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE = 3.2MHz, unless otherwise noted.
ADS7844E, N
TYP
ADS7844EB, NB
PARAMETER
CONDITIONS
MIN
MAX
MIN
TYP
MAX
UNITS
ANALOG INPUT
Full-Scale Input Span
Absolute Input Range
Positive Input - Negative Input
Positive Input
0
–0.2
–0.2
VREF
+VCC +0.2
+1.25
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
V
Negative Input
Capacitance
Leakage Current
25
±1
ꢀ
ꢀ
pF
µA
SYSTEM PERFORMANCE
Resolution
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Offset Error
Offset Error Match
Gain Error
Gain Error Match
Noise
12
ꢀ
Bits
Bits
12
ꢀ
±2
±1
±1
ꢀ
ꢀ
±3
ꢀ
LSB(1)
LSB
LSB
LSB
LSB
LSB
µVrms
dB
±0.8
±0.5
±3
1.0
±4
0.15
ꢀ
0.1
30
70
1.0
ꢀ
ꢀ
ꢀ
Power Supply Rejection
SAMPLING DYNAMICS
Conversion Time
Acquisition Time
Throughput Rate
Multiplexer Settling Time
Aperture Delay
12
ꢀ
ꢀ
Clk Cycles
Clk Cycles
3
ꢀ
200
kHz
ns
ns
500
30
100
ꢀ
ꢀ
ꢀ
Aperture Jitter
ps
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion(2)
Signal-to-(Noise + Distortion)
Spurious Free Dynamic Range
Channel-to-Channel Isolation
VIN = 5VPP at 10kHz
VIN = 5VPP at 10kHz
VIN = 5VPP at 10kHz
VIN = 5VPP at 50kHz
–76
71
76
–78
72
78
ꢀ
dB
dB
dB
dB
120
REFERENCE INPUT
Range
Resistance
0.1
+VCC
100
3
ꢀ
ꢀ
ꢀ
ꢀ
V
DCLK Static
5
45
2.5
ꢀ
ꢀ
ꢀ
ꢀ
GΩ
µA
µA
µA
Input Current
fSAMPLE = 12.5kHz
DCLK Static
0.001
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels
VIH
VIL
VOH
CMOS
ꢀ
| IIH | ≤ +5µA
| IIL | ≤ +5µA
IOH = –250µA
IOL = 250µA
3.0
–0.3
3.5
5.5
+0.8
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
V
V
VOL
0.4
ꢀ
Data Format
Straight Binary
ꢀ
ꢀ
POWER SUPPLY REQUIREMENTS
+VCC
Quiescent Current
Specified Performance
4.75
5.25
900
ꢀ
ꢀ
ꢀ
V
550
300
µA
µA
µA
mW
fSAMPLE = 12.5kHz
Power-Down Mode(3), CS = +VCC
3
ꢀ
ꢀ
Power Dissipation
4.5
TEMPERATURE RANGE
Specified Performance
–40
+85
ꢀ
ꢀ
°C
ꢀ Same specifications as ADS7844E, ADS7844N.
NOTE: (1) LSB means Least Significant Bit. With VREF equal to +5.0V, one LSB is 1.22mV. (2) First five harmonics of the test frequency. (3) Auto power-down mode
(PD1 = PD0 = 0) active or SHDN = GND.
ADS7844
2
SBAS100A
www.ti.com
SPECIFICATION: +2.7V
At TA = –40°C to +85°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted.
ADS7844E, N
TYP
ADS7844EB, NB
PARAMETER
CONDITIONS
MIN
MAX
MIN
TYP
MAX
UNITS
ANALOG INPUT
Full-Scale Input Span
Absolute Input Range
Positive Input - Negative Input
Positive Input
0
–0.2
–0.2
VREF
+VCC +0.2
+0.2
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
V
Negative Input
Capacitance
Leakage Current
25
±1
ꢀ
ꢀ
pF
µA
SYSTEM PERFORMANCE
Resolution
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Offset Error
Offset Error Match
Gain Error
Gain Error Match
Noise
12
ꢀ
Bits
Bits
12
ꢀ
±2
±1
±1
ꢀ
ꢀ
±3
ꢀ
LSB(1)
LSB
LSB
LSB
LSB
LSB
µVrms
dB
±0.8
±0.5
±3
1.0
±4
0.15
ꢀ
0.1
30
70
1.0
ꢀ
ꢀ
ꢀ
Power Supply Rejection
SAMPLING DYNAMICS
Conversion Time
Acquisition Time
Throughput Rate
Multiplexer Settling Time
Aperture Delay
12
ꢀ
ꢀ
Clk Cycles
Clk Cycles
3
ꢀ
125
kHz
ns
ns
500
30
100
ꢀ
ꢀ
ꢀ
Aperture Jitter
ps
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion(2)
Signal-to-(Noise + Distortion)
Spurious Free Dynamic Range
Channel-to-Channel Isolation
VIN = 2.5VPP at 10kHz
–75
71
78
–77
72
80
ꢀ
dB
dB
dB
dB
V
V
V
IN = 2.5VPP at 10kHz
IN = 2.5VPP at 10kHz
IN = 2.5VPP at 50kHz
100
REFERENCE INPUT
Range
Resistance
0.1
+VCC
40
ꢀ
ꢀ
ꢀ
ꢀ
V
DCLK Static
5
13
2.5
ꢀ
ꢀ
ꢀ
ꢀ
GΩ
µA
µA
µA
Input Current
fSAMPLE = 12.5kHz
DCLK Static
0.001
3
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels
VIH
VIL
VOH
CMOS
ꢀ
| IIH | ≤ +5µA
| IIL | ≤ +5µA
IOH = –250µA
IOL = 250µA
+VCC • 0.7
–0.3
+VCC • 0.8
5.5
+0.8
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
V
V
VOL
0.4
ꢀ
Data Format
Straight Binary
ꢀ
POWER SUPPLY REQUIREMENTS
+VCC
Quiescent Current
Specified Performance
2.7
3.6
650
ꢀ
ꢀ
ꢀ
V
280
220
ꢀ
ꢀ
µA
µA
µA
mW
fSAMPLE = 12.5kHz
Power-Down Mode(3), CS = +VCC
3
1.8
ꢀ
ꢀ
Power Dissipation
TEMPERATURE RANGE
Specified Performance
–40
+85
ꢀ
ꢀ
°C
ꢀ Same specifications as ADS7844E, ADS7844N.
NOTE: (1) LSB means Least Significant Bit. With VREF equal to +2.5V, one LSB is 610mV. (2) First five harmonics of the test frequency. (3) Auto power-down mode
(PD1 = PD0 = 0) active or SHDN = GND.
ADS7844
SBAS100A
3
www.ti.com
PACKAGE/ORDERING INFORMATION(1)
MINIMUM
RELATIVE
MAXIMUM
SPECIFIED
ACCURACY GAIN ERROR TEMPERATURE
PACKAGE
PACKAGE-LEAD DESIGNATOR
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
(LSB)
(LSB)
RANGE
ADS7844E
±2
"
"
"
±1
"
±4
"
"
"
±3
"
–40°C to +85°C
QSOP-20
DBQ
ADS7844E
ADS7844E/2K5
ADS7844N
ADS7844N/1K
ADS7844EB
ADS7844EB/2K5
ADS7844NB
ADS7844NB/1K
Rails, 56
Tape and Reel, 2500
Rails, 68
Tape and Reel,1000
Rails, 56
Tape and Reel, 2500
Rails, 68
Tape and Reel, 1000
"
"
"
"
"
"
DB
"
DBQ
"
ADS7844N
SSOP-20
"
"
ADS7844EB
–40°C to +85°C
QSOP-20
"
"
"
"
"
ADS7844NB
"
"
"
"
"
SSOP-20
"
DB
"
NOTES: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet.
PIN DESCRIPTIONS
PIN CONFIGURATION
Top View
PIN
NAME
DESCRIPTION
1
2
3
4
5
6
7
8
9
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
Analog Input Channel 0.
Analog Input Channel 1.
Analog Input Channel 2.
Analog Input Channel 3.
Analog Input Channel 4.
Analog Input Channel 5.
Analog Input Channel 6.
Analog Input Channel 7.
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
1
2
3
4
5
6
7
8
9
20 +VCC
19 DCLK
18 CS
17 DIN
Ground reference for analog inputs. Sets zero code
16 BUSY
15 DOUT
14 GND
13 GND
12 +VCC
11 VREF
ADS7844
voltage in single ended mode. Connect this pin to ground
or ground reference point.
10
11
SHDN
VREF
Shutdown. When LOW, the device enters a very low
power shutdown mode.
Voltage Reference Input. See Specification Table for
ranges.
12
13
14
15
+VCC
GND
GND
DOUT
Power Supply, 2.7V to 5V.
Ground
SHDN 10
Ground
Serial Data Output. Data is shifted on the falling edge of
DCLK. This output is high impedance when
CS is high.
16
BUSY
Busy Output. Busy goes low when the DIN control bits
are being read and also when the device is converting.
The Output is high impedance when CS is High.
Serial Data Input. If CS is LOW, data is latched on rising
ABSOLUTE MAXIMUM RATINGS(1)
17
18
DIN
CS
+VCC to GND ........................................................................ –0.3V to +6V
Analog Inputs to GND ............................................ –0.3V to +VCC + 0.3V
Digital Inputs to GND ........................................................... –0.3V to +6V
Power Dissipation .......................................................................... 250mW
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ........................................–40°C to +85°C
Storage Temperature Range .........................................–65°C to +150°C
Lead Temperature (soldering, 10s)............................................... +300°C
edge of DCLK
.
Chip Select Input. Active LOW. Data will not be clocked
into DIN unless CS is low. When CS is high DOUT is high
impedance.
19
20
CLK
External Clock Input. The clock speed determines the
conversion rate by the equation fCLK = 16 • fSAMPLE
Power Supply
.
+VCC
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
completedevicefailure.Precisionintegratedcircuitsmaybemore
susceptible to damage because very small parametric changes
could cause the device not to meet its published specifications.
ADS7844
4
SBAS100A
www.ti.com
TYPICAL PERFORMANCE CURVES:+5V
At TA = +25°C, +VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE = 3.2MHz, unless otherwise noted.
FREQUENCY SPECTRUM
FREQUENCY SPECTRUM
(4096 Point FFT; f = 1,123Hz, –0.2dB)
(4096 Point FFT; f = 10.3kHz, –0.2dB)
IN
IN
0
–20
0
–20
–40
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
25
50
75
100
0
25
50
75
100
100
100
Frequency (kHz)
Frequency (kHz)
SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-
(NOISE+DISTORTION) vs INPUT FREQUENCY
SPURIOUS FREE DYNAMIC RANGE AND TOTAL
HARMONIC DISTORTION vs INPUT FREQUENCY
–85
–80
–75
–70
–65
74
73
72
71
70
69
68
85
80
75
70
65
SNR
SFDR
SINAD
THD
1
10
1
10
100
Input Frequency (kHz)
Input Frequency (kHz)
EFFECTIVE NUMBER OF BITS
vs INPUT FREQUENCY
CHANGE IN SIGNAL-TO-(NOISE+DISTORTION)
vs TEMPERATURE
12.0
11.8
11.6
11.4
11.2
11.0
0.6
0.4
0.2
0.0
–0.2
–0.4
–0.6
fIN = 10kHz, –0.2dB
1
10
100
–40
–20
0
20
40
60
80
Input Frequency (kHz)
Temperature (°C)
ADS7844
SBAS100A
5
www.ti.com
TYPICAL PERFORMANCE CURVES:+2.7V
At TA = +25°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted.
FREQUENCY SPECTRUM
(4096 Point FFT; f = 10.6kHz, –0.2dB)
FREQUENCY SPECTRUM
(4096 Point FFT; f = 1,129Hz, –0.2dB)
IN
IN
0
–20
0
–20
–40
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
1
1
15.6
31.3
46.9
62.5
100
100
0
15.6
31.3
46.9
62.5
Frequency (kHz)
Frequency (kHz)
SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-
(NOISE+DISTORTION) vs INPUT FREQUENCY
SPURIOUS FREE DYNAMIC RANGE AND TOTAL
HARMONIC DISTORTION vs INPUT FREQUENCY
90
85
80
75
70
65
60
55
50
–90
–85
–80
–75
–70
–65
–60
–55
–50
78
74
70
66
62
58
54
SNR
SFDR
THD
SINAD
1
10
100
10
Input Frequency (kHz)
Input Frequency (kHz)
EFFECTIVE NUMBER OF BITS
vs INPUT FREQUENCY
CHANGE IN SIGNAL-TO-(NOISE+DISTORTION)
vs TEMPERATURE
12.0
11.5
11.0
10.5
10.0
9.5
0.4
0.2
fIN = 10kHz, –0.2dB
0.0
–0.2
–0.4
–0.6
–0.8
9.0
–40
–20
0
20
40
60
80
100
10
Temperature (˚C)
Input Frequency (kHz)
ADS7844
6
SBAS100A
www.ti.com
TYPICAL PERFORMANCE CURVES:+2.7V (CONT)
At TA = +25°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted.
POWER DOWN SUPPLY CURRENT
vs TEMPERATURE
SUPPLY CURRENT vs TEMPERATURE
140
120
100
80
400
350
300
250
200
150
100
60
40
20
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
Temperature (˚C)
Temperature (˚C)
INTEGRAL LINEARITY ERROR vs CODE
DIFFERENTIAL LINEARITY ERROR vs CODE
1.00
0.75
1.00
0.75
0.50
0.50
0.25
0.25
0.00
0.00
–0.25
–0.50
–0.75
–1.00
–0.25
–0.50
–0.75
–1.00
000H
800H
FFFH
000H
800H
FFFH
Output Code
Output Code
CHANGE IN GAIN vs TEMPERATURE
CHANGE IN OFFSET vs TEMPERATURE
0.6
0.15
0.10
0.4
0.2
0.05
0.0
0.00
–0.2
–0.4
–0.6
–0.05
–0.10
–0.15
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
Temperature (˚C)
Temperature (˚C)
ADS7844
SBAS100A
7
www.ti.com
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted.
REFERENCE CURRENT vs TEMPERATURE
REFERENCE CURRENT vs SAMPLE RATE
18
16
14
12
10
8
14
12
10
8
6
4
2
6
0
–40
–20
0
20
40
60
80
100
0
25
50
75
100
125
Temperature (˚C)
Sample Rate (kHz)
SUPPLY CURRENT vs +VCC
MAXIMUM SAMPLE RATE vs +VCC
1M
100k
10k
1k
320
300
280
260
240
220
200
180
fSAMPLE = 12.5kHz
VREF = +VCC
VREF = +VCC
2
2.5
3
3.5
4
4.5
5
2
2.5
3
3.5
4
4.5
5
+VCC (V)
+VCC (V)
ADS7844
8
SBAS100A
www.ti.com
ANALOG INPUT
THEORY OF OPERATION
Figure 2 shows a block diagram of the input multiplexer on
the ADS7844. The differential input of the converter is
derived from one of the eight inputs in reference to the COM
pin or four of the eight inputs. Table I and Table II show the
relationship between the A2, A1, A0, and SGL/DIF control
bits and the configuration of the analog multiplexer. The
control bits are provided serially via the DIN pin, see the
Digital Interface section of this data sheet for more details.
The ADS7844 is a classic successive approximation register
(SAR) analog-to-digital (A/D) converter. The architecture is
based on capacitive redistribution which inherently includes
a sample/hold function. The converter is fabricated on a
0.6µs CMOS process.
The basic operation of the ADS7844 is shown in Figure 1.
The device requires an external reference and an external
clock. It operates from a single supply of 2.7V to 5.25V. The
external reference can be any voltage between 100mV and
+VCC. The value of the reference voltage directly sets the
input range of the converter. The average reference input
current depends on the conversion rate of the ADS7844.
When the converter enters the hold mode, the voltage
difference between the +IN and –IN inputs (see Figure 2) is
captured on the internal capacitor array. The voltage on the
–IN input is limited between –0.2V and 1.25V, allowing the
input to reject small signals which are common to both the
+IN and –IN input. The +IN input has a range of –0.2V to
+VCC + 0.2V.
The analog input to the converter is differential and is
provided via an eight-channel multiplexer. The input can be
provided in reference to a voltage on the COM pin (which
is generally ground) or differentially by using four of the
eight input channels (CH0 - CH7). The particular configura-
tion is selectable via the digital interface.
The input current on the analog inputs depends on the
conversion rate of the device. During the sample period, the
source must charge the internal sampling capacitor (typi-
A2
A1
A0
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
A2
A1
A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+IN
–IN
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
+IN
–IN
–IN
–IN
–IN
–IN
–IN
–IN
–IN
+IN
–IN
+IN
+IN
–IN
+IN
+IN
–IN
+IN
–IN
+IN
+IN
–IN
+IN
+IN
–IN
+IN
+IN
–IN
+IN
+IN
TABLE I. Single-Ended Channel Selection (SGL/DIF HIGH).
TABLE II. Differential Channel Control (SGL/DIF LOW).
+2.7V to +5V
ADS7844
+VCC 20
1µF to 10µF
0.1µF
1
2
3
4
5
6
7
8
9
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
Serial/Conversion Clock
Chip Select
DCLK 19
CS 18
Single-ended
or differential
analog inputs
Serial Data In
DIN 17
BUSY 16
DOUT 15
GND 14
GND 13
+VCC 12
VREF 11
Serial Data Out
10 SHDN
1µF to 10µF
FIGURE 1. Basic Operation of the ADS7844.
ADS7844
SBAS100A
9
www.ti.com
Likewise, the noise or uncertainty of the digitized output will
increase with lower LSB size. With a reference voltage of
100mV, the LSB size is 24µV. This level is below the
internal noise of the device. As a result, the digital output
code will not be stable and vary around a mean value by a
number of LSBs. The distribution of output codes will be
gaussian and the noise can be reduced by simply averaging
consecutive conversion results or applying a digital filter.
A2-A0
(shown 000B)(1)
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
With a lower reference voltage, care should be taken to
provide a clean layout including adequate bypassing, a clean
(low noise, low ripple) power supply, a low-noise reference,
and a low-noise input signal. Because the LSB size is lower,
the converter will also be more sensitive to nearby digital
signals and electromagnetic interference.
+IN
Converter
−IN
The voltage into the VREF input is not buffered and directly
drives the capacitor digital-to-analog converter (CDAC)
portion of the ADS7844. Typically, the input current is
13µA with a 2.5V reference. This value will vary by
microamps depending on the result of the conversion. The
reference current diminishes directly with both conversion
rate and reference voltage. As the current from the reference
is drawn on each bit decision, clocking the converter more
quickly during a given conversion period will not reduce
overall current drain from the reference.
COM
DIGITAL INTERFACE
SGL/DIF
(shown HIGH)
NOTE: (1) See Truth Tables, Table 1,
and Table 2 for address coding.
Figure 3 shows the typical operation of the ADS7844’s
digital interface. This diagram assumes that the source of the
digital signals is a microcontroller or digital signal processor
with a basic serial interface (note that the digital inputs are
over-voltage tolerant up to 5.5V, regardless of +VCC). Each
communication between the processor and the converter
consists of eight clock cycles. One complete conversion can
be accomplished with three serial communications, for a
total of 24 clock cycles on the DCLK input.
FIGURE 2. Simplified Diagram of the Analog Input.
cally 25pF). After the capacitor has been fully charged, there
is no further input current. The rate of charge transfer from
the analog source to the converter is a function of conversion
rate.
The first eight clock cycles are used to provide the control
byte via the DIN pin. When the converter has enough
information about the following conversion to set the input
multiplexer appropriately, it enters the acquisition (sample)
mode. After three more clock cycles, the control byte is
complete and the converter enters the conversion mode. At
this point, the input sample/hold goes into the hold mode.
The next twelve clock cycles accomplish the actual analog-
to-digital conversion. A thirteenth clock cycle is needed for
the last bit of the conversion result. Three more clock cycles
are needed to complete the last byte (DOUT will be LOW).
These will be ignored by the converter.
REFERENCE INPUT
The external reference sets the analog input range. The
ADS7844 will operate with a reference in the range of
100mV to +VCC. Keep in mind that the analog input is the
difference between the +IN input and the –IN input as shown
in Figure 2. For example, in the single-ended mode, a 1.25V
reference, and with the COM pin grounded, the selected input
channel (CH0 - CH7) will properly digitize a signal in the
range of 0V to 1.25V. If the COM pin is connected to 0.5V,
the input range on the selected channel is 0.5V to 1.75V.
There are several critical items concerning the reference input
and its wide voltage range. As the reference voltage is re-
duced, the analog voltage weight of each digital output code
is also reduced. This is often referred to as the LSB (least
significant bit) size and is equal to the reference voltage
divided by 4096. Any offset or gain error inherent in the A/D
converter will appear to increase, in terms of LSB size, as the
reference voltage is reduced. For example, if the offset of a
given converter is 2 LSBs with a 2.5V reference, then it will
typically be 10 LSBs with a 0.5V reference. In each case, the
actual offset of the device is the same, 1.22mV.
Control Byte
Also shown in Figure 3 is the placement and order of the
control bits within the control byte. Tables III and IV give
detailed information about these bits. The first bit, the ‘S’ bit,
must always be HIGH and indicates the start of the control
byte. The ADS7844 will ignore inputs on the DIN pin until
the start bit is detected. The next three bits (A2 - A0) select
the active input channel or channels of the input multiplexer
(see Tables I and II and Figure 2).
ADS7844
10
SBAS100A
www.ti.com
The SGL/DIF bit controls the multiplexer input mode: either
single-ended (HIGH) or differential (LOW). In single-ended
mode, the selected input channel is referenced to the COM
pin. In differential mode, the two selected inputs provide a
differential input. See Tables I and II and Figure 2 for more
information. The last two bits (PD1 - PD0) select the power-
down mode as shown in Table V. If both inputs are HIGH,
the device is always powered up. If both inputs are LOW, the
device enters a power-down mode between conversions.
When a new conversion is initiated, the device will resume
normal operation instantly—no delay is needed to allow the
device to power up and the very first conversion will be
valid.
Bit 7
(MSB)
Bit 0
(LSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
S
A2
A1
A0
—
SGL/DIF
PD1
PD0
TABLE III. Order of the Control Bits in the Control Byte.
BIT
NAME
DESCRIPTION
7
S
Start Bit. Control byte starts with first HIGH bit on
DIN. A new control byte starts with every 15th clock
cycle.
6 - 4
A2 - A0
Channel Select Bits. Along with the SGL/DIF bit,
these bits control the setting of the multiplexer input
as detailed in Tables I and II.
3
2
—
Not Used.
16-Clocks per Conversion
SGL/DIF Single-Ended/Differential Select Bit. Along with bits
A2 - A0, this bit controls the setting of the multiplexer
input as detailed in Tables I and II.
The control bits for conversion n+1 can be overlapped with
conversion ‘n’ to allow for a conversion every 16 clock
cycles, as shown in Figure 4. This figure also shows possible
serial communication occurring with other serial peripherals
between each byte transfer between the processor and the
converter. This is possible provided that each conversion
completes within 1.6ms of starting. Otherwise, the signal
that has been captured on the input sample/hold may droop
enough to affect the conversion result. In addition, the
ADS7844 is fully powered while other serial communica-
tions are taking place.
1 - 0 PD1 - PD0 Power-Down Mode Select Bits. See Table V for
details.
TABLE IV. Descriptions of the Control Bits within the
Control Byte.
CS
tACQ
DCLK
DIN
1
8
1
8
1
8
SGL/
DIF
S
A2 A1 A0
Idle
PD1 PD0
Acquire
(START)
Conversion
Idle
BUSY
DOUT
11 10
(MSB)
9
8
7
6
5
4
3
2
1
0
Zero Filled...
(LSB)
FIGURE 3. Conversion Timing, 24-Clocks per Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated
serial port.
CS
DCLK
1
8
1
8
1
8
1
DIN
BUSY
DOUT
S
S
CONTROL BITS
CONTROL BITS
11 10
9
8
7
6
5
4
3
2
1
0
11 10 9
FIGURE 4. Conversion Timing, 16-Clocks per Conversion, 8-bit Bus Interface. No DCLK delay required with dedicated
serial port.
ADS7844
SBAS100A
11
www.ti.com
PD1
0
PD0
0
Description
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
Power-down between conversions. When each
conversion is finished, the converter enters a low
power mode. At the start of the next conversion,
the device instantly powers up to full power. There
is no need for additional delays to assure full
operation and the very first conversion is valid.
tACQ
tDS
Acquisition Time
DIN Valid Prior to DCLK Rising
DIN Hold After DCLK HIGH
DCLK Falling to DOUT Valid
CS Falling to DOUT Enabled
CS Rising to DOUT Disabled
CS Falling to First DCLK Rising
CS Rising to DCLK Ignored
DCLK HIGH
1.5
100
10
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDH
tDO
tDV
200
200
200
tTR
0
1
1
1
0
1
Reserved for future use.
Reserved for future use.
tCSS
tCSH
tCH
100
0
No power-down between conversions, device al-
ways powered.
200
200
tCL
DCLK LOW
tBD
DCLK Falling to BUSY Rising
CS Falling to BUSY Enabled
CS Rising to BUSY Disabled
200
200
200
TABLE V. Power-Down Selection.
tBDV
tBTR
Digital Timing
TABLE VI. Timing Specifications (+VCC = +2.7V to 3.6V,
Figure 5 and Tables VI and VII provide detailed timing for
the digital interface of the ADS7844.
TA = –40°C to +85°C, CLOAD = 50pF).
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
15-Clocks per Conversion
tACQ
tDS
Acquisition Time
DIN Valid Prior to DCLK Rising
DIN Hold After DCLK HIGH
DCLK Falling to DOUT Valid
CS Falling to DOUT Enabled
CS Rising to DOUT Disabled
CS Falling to First DCLK Rising
CS Rising to DCLK Ignored
DCLK HIGH
900
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 6 provides the fastest way to clock the ADS7844.
This method will not work with the serial interface of most
microcontrollers and digital signal processors as they are
generally not capable of providing 15 clock cycles per serial
transfer. However, this method could be used with field
programmable gate arrays (FPGAs) or application specific
integrated circuits (ASICs). Note that this effectively in-
creases the maximum conversion rate of the converter be-
yond the values given in the specification tables, which
assume 16 clock cycles per conversion.
tDH
10
tDO
tDV
100
70
tTR
70
tCSS
tCSH
tCH
50
0
150
150
tCL
DCLK LOW
tBD
DCLK Falling to BUSY Rising
CS Falling to BUSY Enabled
CS Rising to BUSY Disabled
100
70
tBDV
tBTR
70
TABLE VII. Timing Specifications (+VCC = +4.75V to
+5.25V, TA = –40°C to +85°C, CLOAD = 50pF).
CS
tCL
tCSH
tCSS
tCH
tBD
tBD
tD0
DCLK
DIN
tDH
tDS
PD0
tBDV
tBTR
BUSY
DOUT
tDV
tTR
11
10
FIGURE 5. Detailed Timing Diagram.
CS
DCLK
1
15
1
15
1
SGL/
SGL/
DIF
DIN
BUSY
DOUT
S
A2 A1 A0
PD1 PD0
S
A2 A1 A0
PD1 PD0
S
A2 A1 A0
DIF
11 10
9
8
7
6
5
4
3
2
1
0
11 10
9
8
7
6
5
4
3
2
FIGURE 6. Maximum Conversion Rate, 15-Clocks per Conversion.
ADS7844
12
SBAS100A
www.ti.com
Data Format
1000
100
10
The ADS7844 output data is in straight binary format as
shown in Figure 7. This figure shows the ideal output code
for the given input voltage and does not include the effects
of offset, gain, or noise.
fCLK = 16 • fSAMPLE
FS = Full-Scale Voltage = VREF
1 LSB = VREF/4096
fCLK = 2MHz
TA = 25°C
+VCC = +2.7V
1 LSB
11...111
V
REF = +2.5V
11...110
11...101
PD1 = PD0 = 0
1
1k
10k
100k
1M
f
SAMPLE (Hz)
00...010
00...001
00...000
FIGURE 8. Supply Current vs Directly Scaling the Fre-
quency of DCLK with Sample Rate or Keeping
DCLK at the Maximum Possible Frequency.
0V
FS – 1 LSB
Input Voltage(1) (V)
14
Note 1: Voltage at converter input, after
multiplexer: +IN–(–IN). See Figure 2.
TA = 25°C
+VCC = +2.7V
REF = +2.5V
CLK = 16 • fSAMPLE
PD1 = PD0 = 0
12
10
8
V
f
FIGURE 7. Ideal Input Voltages and Output Codes.
POWER DISSIPATION
6
CS LOW
(GND)
There are three power modes for the ADS7844: full power
(PD1 - PD0 = 11B), auto power-down (PD1 - PD0 = 00B),
and shutdown (SHDN LOW). The affects of these modes
varies depending on how the ADS7844 is being operated. For
example, at full conversion rate and 16 clocks per conver-
sion, there is very little difference between full power mode
and auto power-down. Likewise, if the device has entered
auto power-down, a shutdown (SHDN LOW) will not lower
power dissipation.
4
2
CS HIGH (+VCC
)
0
0.09
0.00
1k
10k
100k
1M
f
SAMPLE (Hz)
FIGURE 9. Supply Current vs State of CS.
When operating at full-speed and 16-clocks per conversion
(as shown in Figure 4), the ADS7844 spends most of its time
acquiring or converting. There is little time for auto power-
down, assuming that this mode is active. Thus, the differ-
ence between full power mode and auto power-down is
negligible. If the conversion rate is decreased by simply
slowing the frequency of the DCLK input, the two modes
remain approximately equal. However, if the DCLK fre-
quency is kept at the maximum rate during a conversion, but
conversion are simply done less often, then the difference
between the two modes is dramatic. Figure 8 shows the
difference between reducing the DCLK frequency (“scal-
ing” DCLK to match the conversion rate) or maintaining
DCLK at the highest frequency and reducing the number of
conversion per second. In the later case, the converter
spends an increasing percentage of its time in power-down
mode (assuming the auto power-down mode is active).
Operating the ADS7844 in auto power-down mode will
result in the lowest power dissipation, and there is no
conversion time “penalty” on power-up. The very first
conversion will be valid. SHDN can be used to force an
immediate power-down.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS7844 circuitry. This is particu-
larly true if the reference voltage is low and/or the conver-
sion rate is high.
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connec-
tions, and digital inputs that occur just prior to latching the
output of the analog comparator. Thus, during any single
conversion for an n-bit SAR converter, there are n “win-
dows” in which large external transient voltages can easily
affect the conversion result. Such glitches might originate
from switching power supplies, nearby digital logic, and
If DCLK is active and CS is LOW while the ADS7844 is in
auto power-down mode, the device will continue to dissipate
some power in the digital logic. The power can be reduced
to a minimum by keeping CS HIGH. The differences in
supply current for these two cases are shown in Figure 9.
ADS7844
SBAS100A
13
www.ti.com
high power devices. The degree of error in the digital output
depends on the reference voltage, layout, and the exact
timing of the external event. The error can change if the
external event changes in time with respect to the DCLK
input.
The ADS7844 architecture offers no inherent rejection of
noise or voltage variation in regards to the reference input.
This is of particular concern when the reference input is tied
to the power supply. Any noise and ripple from the supply
will appear directly in the digital results. While high fre-
quency noise can be filtered out as discussed in the previous
paragraph, voltage variation due to line frequency (50Hz or
60Hz) can be difficult to remove.
With this in mind, power to the ADS7844 should be clean
and well bypassed. A 0.1µF ceramic bypass capacitor should
be placed as close to the device as possible. In addition, a
1µF to 10µF capacitor and a 5Ω or 10Ω series resistor may
be used to lowpass filter a noisy supply.
The GND pin should be connected to a clean ground point.
In many cases, this will be the “analog” ground. Avoid
connections which are too near the grounding point of a
microcontroller or digital signal processor. If needed, run a
ground trace directly from the converter to the power supply
entry point. The ideal layout will include an analog ground
plane dedicated to the converter and associated analog
circuitry.
The reference should be similarly bypassed with a 0.1µF
capacitor. Again, a series resistor and large capacitor can be
used to lowpass filter the reference voltage. If the reference
voltage originates from an op amp, make sure that it can
drive the bypass capacitor without oscillation (the series
resistor can help in this case). The ADS7844 draws very
little current from the reference on average, but it does place
larger demands on the reference circuitry over short periods
of time (on each rising edge of DCLK during a conversion).
ADS7844
14
SBAS100A
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS7844E
ADS7844E/2K5
ADS7844EB
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SSOP
DBQ
DBQ
DBQ
20
20
20
50
RoHS & Green
Call TI
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
ADS7844E
Samples
Samples
Samples
2500 RoHS & Green
50 RoHS & Green
2500 RoHS & Green
Call TI
Call TI
-40 to 85
ADS7844E
ADS7844E
B
ADS7844EB/2K5
ADS7844EBG4
ACTIVE
ACTIVE
SSOP
SSOP
DBQ
DBQ
20
20
Call TI
Call TI
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
ADS7844E
B
Samples
Samples
50
RoHS & Green
ADS7844E
B
ADS7844EG4
ADS7844N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SSOP
SSOP
SSOP
DBQ
DB
20
20
20
20
20
50
70
RoHS & Green
RoHS & Green
Call TI
NIPDAU
Call TI
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
ADS7844E
ADS7844N
ADS7844N
ADS7844N
Samples
Samples
Samples
Samples
Samples
ADS7844N/1K
ADS7844N/1KG4
ADS7844NB
DB
1000 RoHS & Green
1000 RoHS & Green
-40 to 85
-40 to 85
DB
Call TI
DB
70
RoHS & Green
NIPDAU
ADS7844N
B
ADS7844NB/1K
ADS7844NBG4
ADS7844NG4
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SSOP
DB
DB
DB
20
20
20
1000 RoHS & Green
Call TI
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
ADS7844N
B
Samples
Samples
Samples
70
70
RoHS & Green
RoHS & Green
ADS7844N
B
ADS7844N
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Sep-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS7844E/2K5
ADS7844EB/2K5
ADS7844N/1K
SSOP
SSOP
SSOP
SSOP
DBQ
DBQ
DB
20
20
20
20
2500
2500
1000
1000
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
6.5
6.5
8.2
8.2
9.0
9.0
7.5
7.5
2.1
2.1
2.5
2.5
8.0
8.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
12.0
12.0
ADS7844NB/1K
DB
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Sep-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS7844E/2K5
ADS7844EB/2K5
ADS7844N/1K
SSOP
SSOP
SSOP
SSOP
DBQ
DBQ
DB
20
20
20
20
2500
2500
1000
1000
356.0
356.0
356.0
356.0
356.0
356.0
356.0
356.0
35.0
35.0
35.0
35.0
ADS7844NB/1K
DB
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Sep-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ADS7844E
ADS7844EB
ADS7844EBG4
ADS7844EG4
ADS7844N
DBQ
DBQ
DBQ
DBQ
DB
SSOP
SSOP
SSOP
SSOP
SSOP
SSOP
SSOP
SSOP
20
20
20
20
20
20
20
20
50
50
50
50
70
70
70
70
506.6
506.6
506.6
506.6
530
8
8
3940
3940
3940
3940
4000
4000
4000
4000
4.32
4.32
4.32
4.32
4.1
8
8
10.5
10.5
10.5
10.5
ADS7844NB
ADS7844NBG4
ADS7844NG4
DB
530
4.1
DB
530
4.1
DB
530
4.1
Pack Materials-Page 3
PACKAGE OUTLINE
DB0020A
SSOP - 2 mm max height
S
C
A
L
E
2
.
0
0
0
SMALL OUTLINE PACKAGE
C
8.2
7.4
TYP
A
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
18X 0.65
20
1
2X
7.5
6.9
5.85
NOTE 3
10
11
0.38
0.22
20X
5.6
5.0
0.1
C A B
B
NOTE 4
2 MAX
0.25
GAGE PLANE
(0.15) TYP
SEE DETAIL A
0.95
0.55
0.05 MIN
0 -8
A
15
DETAIL A
TYPICAL
4214851/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0020A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.85)
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
10
11
(7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4214851/B 08/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DB0020A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
20X (1.85)
SYMM
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
10
11
(7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4214851/B 08/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
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