ADS7864YB/250 [TI]
500kHz、12 位、6 通道同步采样模数转换器 | PFB | 48;
| 型号： | ADS7864YB/250 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 500kHz、12 位、6 通道同步采样模数转换器 | PFB | 48 转换器 模数转换器 |
| 文件： | 总27页 (文件大小：576K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADS7864
SBAS141A–SEPTEMBER 2000–REVISED MARCH 2005
500kHz, 12-Bit, 6-Channel Simultaneous Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
6 Simultaneous Sampling Channels
Fully Differential Inputs
2µs Total Throughput per Channel
No Missing Codes
The ADS7864 is
a
dual 12-bit, 500kHz
analog-to-digital (A/D) converter with 6 fully differen-
tial input channels grouped into three pairs for high
speed simultaneous signal acquisition. Inputs to the
sample-and-hold amplifiers are fully differential and
are maintained differential to the input of the A/D
converter. This provides excellent common-mode re-
jection of 80dB at 50kHz which is important in high
noise environments.
Parallel Interface
1MHz Effective Sampling Rate
Low Power: 50mW
6X FIFO
The ADS7864 offers a parallel interface and control
inputs to minimize software overhead. The output
data for each channel is available as a 16-bit word
(address and data). The ADS7864 is offered in a
TQFP-48 package and is fully specified over the
–40°C to +85°C operating range.
APPLICATIONS
•
•
•
Motor Control
Multi-Axis Positioning Systems
3-Phase Power Control
CH A0+
HOLDA
SAR
CH A0−
S/H
Amp
CH B0+
HOLDB
HOLDC
COMP
CH B0−
S/H
Amp
Interface
A2
CDAC
A1
CH C1+
A0
Conversion
and
CH C1−
MUX
S/H
Amp
BYTE
CLOCK
CS
Control
REFIN
RD
Internal
2.5V
Reference
BUSY
RESET
REFOUT
FIFO
Channel/
Registers
Data Output
CH A1+
16
CH A1−
COMP
S/H
Amp
CDAC
CH B1+
CH B1−
S/H
Amp
CH C1+
CH C1−
MUX
SAR
S/H
Amp
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2005, Texas Instruments Incorporated
ADS7864
www.ti.com
SBAS141A–SEPTEMBER 2000–REVISED MARCH 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
MINIMUM
RELATIVE
ACCURACY (LSB)
MAXIMUM
GAIN
ERROR (%)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
PRODUCT
ADS7864Y
ADS7864Y
ADS7864YB
ADS7864YB
Tape and Reel, 250
Tape and Reel, 2000
Tape and Reel, 250
Tape and Reel, 2000
ADS7864Y
±2
±1
±0.75
±0.5
TQFP-48
TQFP-48
PFB
PFB
–40°C to +85°C
–40°C to +85°C
ADS7864YB
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
ADS7864
–0.3 to (+VD + 0.3)
–0.3 to (+VD + 0.3)
–0.3 to (+VD + 0.3)
±0.3
UNIT
V
Analog Inputs to AGND: Any Channel Input
Analog Inputs to AGND: REFIN
Digital Inputs to DGND
V
V
Ground Voltage Differences: AGND, DGND
Ground Voltage Differences: +VD to AGND
Power Supply Difference: +VA, +VD
Power Dissipation
V
–0.3 to +6
±0.3
V
V
325
mW
°C
°C
°C
°C
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
+150
–40 to +85
–65 to +150
+300
Lead Temperature (soldering, 10s)
2
ADS7864
www.ti.com
SBAS141A–SEPTEMBER 2000–REVISED MARCH 2005
BASIC OPERATION
48 47 46 45 44 43 42 41 40 39 38 37
+5V
+5V
Analog Power
Supply
Analog Power
Supply
36
AGND 35
34
1
2
3
4
5
6
7
8
9
+VA
+VA
+
+
10µF
0.1µF
0.1µF
10µF
AGND
DB15
DB14
DB13
DB12
DB11
DB10
DB9
REFIN
REFOUT 33
RESET 32
A0 31
Global Reset
ADS7864Y
Address Select
30
29
A1
A2
BYTE 28
27
HOLDB 26
25
10 DB8
HOLDA
Sample and Hold
Inputs
11
12
DB7
DB6
HOLDC
13 14 15 16 17 18 19 20 21 22 23 24
+5V
Digital Power Supply
+
µ
µ
F
0.1
F
10
Data Ouput
DGND
AGND
3
ADS7864
www.ti.com
SBAS141A–SEPTEMBER 2000–REVISED MARCH 2005
ELECTRICAL CHARACTERISTICS
All specifications TMIN to TMAX, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz (unless otherwise
noted).
ADS7864Y
TYP
ADS7864YB
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
Resolution
12
12
Bits
Analog Input
Input Voltage Range-Bipolar
Absolute Input Range
VCENTER = +2.5V
–VREF
–0.3
+VREF
+VA + 0.3
+VA + 0.3
–VREF
+VREF
V
V
+IN
–IN
–0.3
V
Input Capacitance
15
±1
15
±1
pF
µA
Input Leakage Current
System Performance
No Missing Codes
CLK = GND
12
12
Bits
LSB
LSB
LSB
LSB
LSB
Integral Linearity
±0.75
0.5
2
±0.5
0.5
±1
Integral Linearity Match
Differential Linearity
–0.9
±0.6
±0.75
–0.9
±0.4
±0.5
Bipolar Offset Error
Referenced to REFIN
Referenced to REFIN
Referenced to REFIN
±4
3
±3
3
Bipolar Offset Error Match
Positive Gain Error
±0.15
±0.15
±0.75
3
±0.1
±0.1
±0.5 % of FSR
LSB
±0.5 % of FSR
Positive Gain Error Match
Negative Gain Error
3
±0.75
3
Negative Gain Error Match
Common-Mode Rejection Ratio
3
2
LSB
dB
At DC
84
80
84
80
VIN = ±1.25VPP at 50kHz
dB
Noise
120
0.3
120
0.3
µVRMS
LSB
Power Supply Rejection Ratio
Sampling Dynamics
Conversion Time per A/D
Acquisition Time
2
1.75
0.25
1.75
0.25
µs
µs
Throughput Rate
500
500
kHz
ns
Aperture Delay
3.5
100
50
3.5
100
50
Aperture Delay Matching
Aperture Jitter
ps
ps
Small-Signal Bandwidth
Dynamic Characteristics
Total Harmonic Distortion
SINAD
40
40
MHz
VIN = ±2.5VPP at 100kHz
VIN = ±2.5VPP at 100kHz
VIN = ±2.5VPP at 100kHz
VIN = ±2.5VPP at 50kHz
–75
71
–75
71
dB
dB
dB
dB
Spurious Free Dynamic Range
Channel-to-Channel Isolation
Voltage Reference
Internal Reference Voltage
Internal Drift
78
78
–76
–76
2.475
2.5
10
2.525
2.475
2.5
10
2.525
V
ppm/°C
µVPP
mA
Internal Noise
50
50
Internal Source Current
Internal Load Rejection
Internal PSRR
2
2
0.005
80
0.005
80
mV/µA
dB
External Reference Voltage Range
Input Current
1.2
2.5
2.6
1.2
2.5
2.6
V
100
100
µA
Input Capacitance
5
5
pF
4
ADS7864
www.ti.com
SBAS141A–SEPTEMBER 2000–REVISED MARCH 2005
ELECTRICAL CHARACTERISTICS (continued)
All specifications TMIN to TMAX, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz (unless otherwise
noted).
ADS7864Y
TYP
ADS7864YB
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
Digital Input/Output
Logic Family
CMOS
CMOS
Logic Levels:
VIH
IIH = +5µA
IIL = +5µA
3.0
–0.3
3.5
+VD + 0.3
0.8
3.0
–0.3
3.5
+VD + 0.3
0.8
V
V
VIL
VOH
IOH = –500µA
IOL = –500µA
V
VOL
0.4
8
0.4
8
V
External Clock
0.2
0.2
MHz
Data Format
Binary Two's Complement
Binary Two's Complement
Power-Supply Requirements
Power Supply Voltage, +VA, +VD
Quiescent Current, +VA, +VD
Power Dissipation
4.75
5
5.25
10
4.75
5
5.25
10
V
mA
mW
50
50
PIN CONFIGURATIONS
48 47 46 45 44 43 42 41 40 39 38 37
1
2
36
+VA
+VA
AGND
DB15
DB14
DB13
DB12
DB11
DB10
DB9
35 AGND
34
3
REFIN
4
33 REFOUT
32 RESET
5
31
6
A0
ADS7864
7
30 A1
29
28
27
8
A2
9
BYTE
HOLDA
10
DB8
DB7 11
12
26 HOLDB
25
DB6
HOLDC
13 14 15 16 17 18 19 20 21 22 23 24
5
ADS7864
www.ti.com
SBAS141A–SEPTEMBER 2000–REVISED MARCH 2005
PIN DESCRIPTIONS
PIN
1
NAME
+VA
DESCRIPTION
Analog Power Supply. Normally +5V.
Analog Ground
2
AGND
DB15
DB14
DB13
DB12
DB11
DB10
DB9
3
Data Valid Output: ‘1’ for data valid; ‘0’ for invalid data.
Channel Address Output Pin (see Table 2)
Channel Address Output Pin (see Table 2)
Channel Address Output Pin (see Table 2)
Data Bit 11 - MSB
4
5
6
7
8
Data Bit 10
9
Data Bit 9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
DB8
Data Bit 8
DB7
Data Bit 7
DB6
Data Bit 6
DB5
Data Bit 5
DB4
Data Bit 4
DB3
Data Bit 3
DB2
Data Bit 2
DB1
Data Bit 1
DB0
Data Bit 0 - LSB
BUSY
DGND
+VD
Low when a conversion is in progress.
Digital Ground
Digital Power Supply, +5VDC
An external clock must be applied to the CLOCK input.
RD Input. Enables the parallel output when used in conjunction with chip select.
Chip Select
CLOCK
RD
CS
HOLDC
HOLDB
HOLDA
BYTE
A2
Places Channels C0 and C1 in hold mode.
Places Channels B0 and B1 in hold mode.
Places Channels A0 and A1 in hold mode.
2 × 8 Output Capability. Active high.
A2 Address/Mode Select Pin (see Table 3).
A1 Address/Mode Select Pin (see Table 3).
A0 Address/Mode Select Pin (see Table 3).
Reset Pin
A1
A0
RESET
REFOUT
REFIN
AGND
+VA
Reference Out
Reference In
Analog Ground
Analog Power Supply. Normally +5V.
Noninverting Input Channel A1
Inverting Input Channel A1
Noninverting Input Channel B1
Inverting Input Channel B1
Noninverting Input Channel C1
Inverting Input Channel C1
Inverting Input Channel C0
Noninverting Input Channel C0
Inverting Input Channel B0
Noninverting Input Channel B0
Inverting Input Channel A0
Noninverting Input Channel A0
CH A1+
CH A1–
CH B1+
CH B1–
CH C1+
CH C1–
CH C0–
CH C0+
CH B0–
CH B0+
CH A0–
CH A0+
6
ADS7864
www.ti.com
SBAS141A–SEPTEMBER 2000–REVISED MARCH 2005
TYPICAL CHARACTERISTICS
All specifications TA = +25°C, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz (unless otherwise
noted)
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 99.9kHz, –0.2dB)
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 199.9kHz, -0.2dB)
0
20
40
60
80
0
20
40
60
80
−
−
−
−
−
−
−
−
−
−
−
−
100
120
100
120
0
62.5
125
187.5
250
0
62.5
125
187.5
250
Frequency (kHz)
Frequency (kHz)
Figure 1.
Figure 2.
SIGNAL-TO-NOISE RATIO AND
SIGNAL-TO-(NOISE+DISTORTION)
vs INPUT FREQUENCY
CHANGE IN SIGNAL-TO-NOISE RATIO
AND SIGNAL-TO-(NOISE+DISTORTION)
vs TEMPERATURE
1.0
0.6
0.2
75
70
65
60
55
50
SNR
SINAD
SNR
−
−
−
0.2
0.6
1.0
SINAD
−
−
20
40
0
20
40
60
80
1k
10k
100k
1M
Input Frequency (Hz)
_
Temperature ( C)
Figure 3.
Figure 4.
7
ADS7864
www.ti.com
SBAS141A–SEPTEMBER 2000–REVISED MARCH 2005
TYPICAL CHARACTERISTICS (continued)
All specifications TA = +25°C, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz (unless otherwise
noted)
CHANGE IN SPURIOUS FREE DYNAMIC RANGE
AND TOTAL HARMONIC DISTORTION
vs TEMPERATURE
POSITIVE GAIN MATCH vs TEMPERATURE
(Maximum Deviation for All Six Channels)
1.0
0.5
0.0
0.5
1.0
1.80
1.70
1.60
1.50
1.40
1.30
1.20
THD
SFDR
−
−
−
−
−
−
20
40
20
0
20
40
60
80
40
0
20
40
60
80
_
_
Temperature ( C)
Temperature ( C)
Figure 5.
Figure 6.
NEGATIVE GAIN MATCH vs TEMPERATURE
(Maximum Deviation for All Six Channels)
REFERENCE VOLTAGE vs TEMPERATURE
1.50
1.40
1.30
1.20
1.10
1.00
2.510
2.506
2.502
2.498
2.494
2.490
−
−
20
40
0
20
40
60
80
−
−
20
40
0
20
40
60
80
_
Temperature ( C)
_
Temperature ( C)
Figure 7.
Figure 8.
BIPOLAR ZERO vs TEMPERATURE
BIPOLAR ZERO MATCH vs TEMPERATURE
1.2
1.0
0.8
0.6
0.4
1.30
1.20
1.10
1.00
0.90
CH1
CH0
−
−
−
−
20
40
20
0
20
40
60
80
40
0
20
40
60
80
_
_
Temperature ( C)
Temperature ( C)
Figure 9.
Figure 10.
8
ADS7864
www.ti.com
SBAS141A–SEPTEMBER 2000–REVISED MARCH 2005
TYPICAL CHARACTERISTICS (continued)
All specifications TA = +25°C, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz (unless otherwise
noted)
DIFFERENTIAL LINEARITY ERROR vs CODE
INTEGRAL LINEARITY ERROR vs CODE
2.0
1.5
1.0
0.5
0
1
0.75
0.5
Typical of All Six Channels
0.25
0
−
−
−
−
−
0.25
0.5
1.0
1.5
2.0
−
0.5
−
0.75
−
1
800
000
7FF
800
000
7FF
Hex BTC Code
Hex BTC Code
Figure 11.
Figure 12.
INTEGRAL LINEARITY ERROR MATCH
vs TEMPERATURE
Channel A0/Channel C1
(Different Converter, Different Channels)
INTEGRAL LINEARITY ERROR vs TEMPERATURE
−
−
−
−
−
−
−
0.02
0.03
0.04
0.05
0.06
0.07
0.08
2.0
1.6
1.2
0.8
0.4
0
Positive ILE
Negative ILE
−
0.4
0.8
1.2
1.6
2.0
−
−
−
−
−
−
20
40
0
20
40
60
80
40
20
0
20
40
60
80
_
_
Temperature ( C)
Temperature ( C)
Figure 13.
Figure 14.
9
ADS7864
www.ti.com
SBAS141A–SEPTEMBER 2000–REVISED MARCH 2005
TYPICAL CHARACTERISTICS (continued)
All specifications TA = +25°C, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz (unless otherwise
noted)
INTEGRAL LINEARITY ERROR MATCH vs CODE
DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE
Channel A0/Channel B0
(Same Converter, Different Channels)
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
0.4
0.2
0
Positive DLE
−
−
−
−
−
0.2
0.4
0.6
0.8
1.0
−
−
−
−
0.2
0.4
0.6
0.8
Negative DLE
−
−
20
40
0
20
40
60
80
800
000
7FF
_
Temperature ( C)
Hex BTC Code
Figure 15.
Figure 16.
INTEGRAL LINEARITY ERROR MATCH vs CODE
Channel A0/Channel B1
(Different Converter, Different Channels)
CHANNEL SEPARATION
1.0
0.75
0.5
−
−
−
−
−
−
−
65
70
75
80
85
90
95
0.25
0
−
0.25
−
0.5
−
0.75
−
1.0
800
−
100
1k
10k
100k
000
7FF
fIN (Hz)
Hex BTC Code
Figure 17.
Figure 18.
10
ADS7864
www.ti.com
SBAS141A–SEPTEMBER 2000–REVISED MARCH 2005
APPLICATIONS INFORMATION
signal, is 5ns. The average delta of repeated aperture
delay values is typically 50ps (also known as aperture
jitter). These specifications reflect the ability of the
ADS7864 to capture AC input signals accurately at
the exact same moment in time.
INTRODUCTION
The ADS7864 is a high speed, low power, dual 12-bit
analog-to-digital converter (ADC) that operates from a
single +5V supply. The input channels are fully
differential with a typical common-mode rejection of
80dB. The part contains dual 2µs successive approxi-
mation ADCs, six differential sample-and-hold ampli-
fiers, an internal +2.5V reference with REFIN and
REFOUT pins and a high speed parallel interface.
There are six analog inputs that are grouped into
three channels (A, B and C). Each A/D converter has
three inputs (A0/A1, B0/B1 and C0/C1) that can be
sampled and converted simultaneously, thus pre-
serving the relative phase information of the signals
on both analog inputs. Each pair of channels has a
hold signal (HOLDA, HOLDB, HOLDC) to allow
simultaneous sampling on all six channels. The part
accepts an analog input voltage in the range of –VREF
to +VREF, centered around the internal +2.5V refer-
ence. The part will also accept bipolar input ranges
when a level shift circuit is used at the front end (see
Figure 25).
REFERENCE
Under normal operation, the REFOUT pin (pin 2)
should be directly connected to the REFIN pin (pin 1)
to provide an internal +2.5V reference to the
ADS7864. The ADS7864 can operate, however, with
an external reference in the range of 1.2V to 2.6V for
a corresponding full-scale range of 2.4V to 5.2V.
The internal reference of the ADS7864 is
double-buffered. If the internal reference is used to
drive an external load, a buffer is provided between
the reference and the load applied to pin 33 (the
internal reference can typically source 2mA of cur-
rent—load capacitance should not exceed 100pF). If
an external reference is used, the second buffer
provides isolation between the external reference and
the CDAC. This buffer is also used to recharge all of
the capacitors of both CDACs during conversion.
A conversion is initiated on the ADS7864 by bringing
the HOLDX pin low for a minimum of 15ns. HOLDX
low places both sample-and-hold amplifiers of the X
channels in the hold state simultaneously and the
conversion process is started on both channels. The
BUSY output will then go low and remain low for the
duration of the conversion cycle. The data can be
read from the parallel output bus following the con-
version by bringing both RD and CS low.
ANALOG INPUT
The analog input is bipolar and fully differential. There
are two general methods of driving the analog input
of the ADS7864: single-ended or differential (see
Figure 19 and Figure 20). When the input is
single-ended, the –IN input is held at the com-
mon-mode voltage. The +IN input swings around the
same common voltage and the peak-to-peak ampli-
tude is the (common-mode +VREF
)
and the
Conversion time for the ADS7864 is 1.75µs when an
8MHz external clock is used. The corresponding
acquisition time is 0.25µs. To achieve maximum
output rate (500kHz), the read function can be
performed during at the start of the next conversion.
(common-mode –VREF). The value of VREF determines
the range over which the common-mode voltage may
vary (see Figure 21).
NOTE: This mode of operation is described in more
detail in the Timing and Control section of this data
sheet.
−
VREF to +VREF
ADS7864
peak−to−peak
Common
Voltage
SAMPLE-AND-HOLD SECTION
Single−Ended Input
The sample-and-hold amplifiers on the ADS7864
allow the ADCs to accurately convert an input sine
wave of full-scale amplitude to 12-bit accuracy. The
input bandwidth of the sample-and-hold is greater
than the Nyquist rate of the ADC (Nyquist equals
one-half of the sampling rate) even when the ADC is
operated at its maximum throughput rate of 500kHz.
The typical small-signal bandwidth of the
sample-and-hold amplifiers is 40MHz.
VREF
peak−to−peak
ADS7864
Common
Voltage
VREF
peak−to−peak
Differential Input
Typical aperture delay time, or the time it takes for
the ADS7864 to switch from the sample to the hold
mode following the negative edge of the HOLDX
Figure 19. Methods of Driving the ADS7864
Single-Ended or Differential
11
ADS7864
www.ti.com
SBAS141A–SEPTEMBER 2000–REVISED MARCH 2005
+IN
CM +VREF
+VREF
CM Voltage
−
IN = CM Voltage
−
VREF
t
−
CM VREF
Single−Ended Inputs
+IN
+VREF
CM +1/2VREF
CM Voltage
−
VREF
−
IN
t
−
CM 1/2VREF
Differential Inputs
−
−
(IN+) (IN )
−
, Common−Mode Voltage (Single−Ended Mode) = IN .
NOTES: Common−Mode Voltage (Differential Mode) =
2
−
The maximum differential voltage between +IN and IN of the ADS7864 is VREF. See Figures 21 and 22 for a further
explanation of the common voltage range for single−ended and differential inputs.
Figure 20. Using the ADS7864 in the Single-Ended and Differential Input Modes
5
4
3
2
1
0
5
VCC = 5V
4.7
VCC = 5V
4.1
4
3
2
1
0
4.05
2.7
2.3
Single−Ended Input
Differential Input
0.90
0.9
0.3
−
1
−
1
1.2
2.6
2.5
1.2
2.6
2.5
1.0
1.5
2.0
3.0
1.0
1.5
2.0
VREF (V)
3.0
VREF (V)
Figure 21. Single-Ended Input: Common-Mode Voltage
Range vs VREF
Figure 22. Differential Input: Common-Mode
Voltage Range vs VREF
12
ADS7864
www.ti.com
SBAS141A–SEPTEMBER 2000–REVISED MARCH 2005
When the input is differential, the amplitude of the
input is the difference between the +IN and –IN input,
or: (+IN) – (–IN). The peak-to-peak amplitude of each
input is ±1/2VREF around this common voltage. How-
ever, since the inputs are 180° out of phase, the
peak-to-peak amplitude of the differential voltage is
+VREF to –VREF. The value of VREF also determines
the range of the voltage that may be common to both
inputs (see Figure 22).
8000
7000
6000
5000
4000
3000
2000
1000
0
In each case, care should be taken to ensure that the
output impedance of the sources driving the +IN and
–IN inputs are matched. Otherwise, this may result in
offset error, which will change with both temperature
and input voltage.
2044
2045
2046
2047
2048
Code (decimal)
The input current on the analog inputs depend on a
number of factors: sample rate, input voltage, and
source impedance. Essentially, the current into the
ADS7864 charges the internal capacitor array during
the sampling period. After this capacitance has been
fully charged, there is no further input current. The
source of the analog input voltage must be able to
charge the input capacitance (15pF) to a 12-bit
settling level within two clock cycles. When the
converter goes into the hold mode, the input im-
pedance is greater than 1GΩ.
Figure 23. Histogram of 8,000 Conversions of a
DC Input
1.4V
Ω
3k
DATA
Care must be taken regarding the absolute analog
input voltage. The +IN and –IN inputs should always
Test Point
100pF
CLOAD
remain within the range of GND – 300mV to VDD
300mV.
+
VOH
VOL
DATA
TRANSITION NOISE
Figure 23 shows a histogram plot for the ADS7864
following 8,000 conversions of a DC input. The DC
input was set at output code 2046. All but one of the
conversions had an output code result of 2046 (one
of the conversions resulted in an output of 2047). The
histogram reveals the excellent noise performance of
the ADS7864.
tR
tF
Voltage Waveforms for DATA Rise and Fall Times tR, and tF.
Figure 24. Test Circuits for Timing Specifications
13
ADS7864
www.ti.com
SBAS141A–SEPTEMBER 2000–REVISED MARCH 2005
BIPOLAR INPUTS
Hold signals. The FIFO mode will allow the six
registers to be used by a single channel pair, and
therefore three locations for CH X0 and three lo-
cations for CH X1 can be acquired before they are
read from the part.
The differential inputs of the ADS7864 were designed
to accept bipolar inputs (–VREF and +VREF) around the
internal reference voltage (2.5V), which corresponds
to a 0V to 5V input range with a 2.5V reference. By
using a simple op amp circuit featuring a single
amplifier and four external resistors, the ADS7864
can be configured to accept bipolar inputs. The
conventional ±2.5V, ±5V, and ±10V input ranges can
be interfaced to the ADS7864 using the resistor
values shown in Figure 25.
EXPLANATION OF CLOCK, RESET AND
BUSY PINS
CLOCK—An external clock has to be provided for the
ADS7864. The maximum clock frequency is 8MHz.
The minimum clock cycle is 125ns (see Figure 26, t5),
and the clock has to remain high (see Figure 26, t6)
or low (see Figure 26, t7) for at least 40ns.
R1
Ω
4k
CLOCK
HOLDA
t6
t1
+IN
OPA340
Ω
20k
t7
t5
Bipolar Input
−
IN
ADS7864
t3
R2
REFOUT (pin 33)
2.5V
BIPOLAR INPUT
R1
R2
HOLDB
HOLDC
t9
±
Ω
Ω
5k
10V
1k
2k
4k
±
Ω
Ω
Ω
Ω
5V
10k
20k
±
2.5V
t2
Figure 25. Level Shift Circuit for Bipolar Input
Ranges
t8
RESET
TIMING AND CONTROL
The ADS7864 uses an external clock (CLOCK, pin
22) which controls the conversion rate of the CDAC.
With an 8MHz external clock, the A/D sampling rate
is 500kHz which corresponds to a 2µs maximum
throughput time.
Figure 26. Start of the Conversion
RESET—Bringing reset low will reset the ADS7864. It
will clear all the output registers, stop any actual
conversions and will close the sampling switches.
Reset has to stay low for at least 20ns (see Fig-
ure 26, t8). The reset should be back high for at least
20ns (see Figure 26, t9), before starting the next
conversion (negative hold edge).
THEORY OF OPERATION
The ADS7864 contains two 12-bit A/D converters that
operate simultaneously. The three hold signals
(HOLDA, HOLDB, HOLDC) select the input MUX and
initiate the conversion. A simultaneous hold on all six
channels can occur with all three hold signals strobed
together. The converted values are saved in six
registers. For each read operation the ADS7864
outputs 16 bits of information (12 Data, 3 Channel
Address and Data Valid). The Address/Mode signals
(A0, A1, A2) select how the data is read from the
ADS7864. These Address/Mode signals can define a
selection of a single channel, a cycle mode that
cycles through all channels or a FIFO mode that
sequences the data determined by the order of the
BUSY—Busy goes low when the internal A/D con-
verters start a new conversion. It stays low as long as
the conversion is in progress (see Figure 27, 13
clock-cycles, t10) and rises again after the data is
latched to the output register. With Busy going high,
the new data can be read. It takes at least 16 clock
cycles (see Figure 27, t11) to complete conversion.
START OF A CONVERSION
By bringing one or all of the HOLDX signals low, the
input data of the corresponding channel X is immedi-
ately placed in the hold mode (5ns). The conversion
of this channel X follows as soon as the A/D
converter is available for the particular channel. If
14
ADS7864
www.ti.com
SBAS141A–SEPTEMBER 2000–REVISED MARCH 2005
other channels are already in the hold mode but not
converted, then the conversion of channel X is put in
the queue until the previous conversion has been
completed. If more than one channel goes into hold
mode within one clock cycle, then channel A will be
converted first if HOLDA is one of the triggered hold
signals. Next, channel B will be converted, and last,
channel C. If it is important to detect a hold command
during a certain clock cycle, then the falling edge of
the hold signal has to occur at least 10ns before the
falling edge of the clock. (see Figure 26, t1). The hold
signal can remain low without initiating a new conver-
sion. The hold signal has to be high for at least 15ns
(see Figure 26, t2) before it is brought low again and
hold has to stay low for at least 20ns (see Figure 26,
t3).
Once a particular hold signal goes low, further im-
pulses of this hold signal are ignored until the
conversion is finished or the part is reset. When the
conversion is finished (BUSY signal goes high), the
sampling switches will close and sample the selected
channel. The start of the next conversion must be
delayed to allow the input capacitor of the ADS7864
to be fully charged. This delay time depends on the
driving amplifier, but should be at least 175ns
(see Figure 27, t4).
The ADS7864 can also convert one channel continu-
ously, as it is shown in Figure 27 with channel B.
Therefore, HOLDA and HOLDC are kept high all the
time. To gain acquisition time, the falling edge of
HOLDB takes place just before the falling edge of
clock. One conversion requires 16 clock cycles. Here,
data is read after the next conversion is initiated by
HOLDB. To read data from channel B, A1 is set high
and A2 is low. As A0 is low during the first reading
(A2 A1 A0 = 010) data B0 is put to the output. Before
the second RD, A0 switches high (A2 A1 A0 = 011)
so data from channel B1 is read.
In the example of Figure 26, the signal HOLDB goes
low first and channel B0 and B1 will be converted
first. The falling edges of HOLDA and HOLDC occur
within the same clock cycle. Therefore, the channels
A0 and A1 will be converted as soon as the channels
B0 and B1 are finished (plus acquisition time). When
the A-channels are finished, the C-channels will be
converted. The second HOLDA signal is ignored, as
the A-channels are not converted at this point in time.
Table 1. Timing Specifications
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
ns
t1
t2
HOLD (A, B, C) before falling edge of clock
HOLD high time to be recognized again
HOLD low time
10
15
ns
t3
20
ns
t4
Input capacitor charge time
Clock period
175
125
40
ns
t5
ns
t6
Clock high time
ns
t7
Clock low time
40
ns
t8
Reset pulse width
20
ns
t9
First hold after reset
20
ns
t10
t11
t12
t13
t14
Conversion time
12.5 × t5
ns
Successive conversion time (16 × t5)
Address setup before RD
CS before end of RD
RD high time
2
µs
10
30
30
ns
ns
ns
15
ADS7864
www.ti.com
SBAS141A–SEPTEMBER 2000–REVISED MARCH 2005
t11
t10
BUSY
t4
CLOCK
HOLDB
CS
RD
A0
Figure 27. Timing of One Conversion Cycle
READING DATA (RD, CS)—In general, the chan-
nel/data outputs are in tristate. Both CS and RD have
to be low to enable these outputs. RD and CS have
to stay low together for at least 30ns (see Figure 28,
t13) before the output data is valid. RD has to remain
high for at least 30ns (see Figure 28, t14) before
bringing it back low for a subsequent read command.
BUSY
CLOCK
12.5 clock-cycles after the start of a conversion
(BUSY going low), the new data is latched into its
output register. If a read process is initiated around
12.5 clock cycles after BUSY went low, RD and CS
should stay low for at least 50ns to get the new data
stored to its register and switched to the output.
t1
t4
HOLDB
CS being low tells the ADS7864 that the bus on the
board is assigned to the ADS7864. If an A/D con-
verter shares a bus with digital gates, there is a
possibility that digital (high frequency) noise may be
coupled into the A/D converter. If the bus is just used
by the ADS7864, CS can be hardwired to ground.
Reading data at the falling edge of one of the hold
signals might cause distortion of the hold value.
t13
CS
RD
t14
t12
A0
Figure 28. Timing for Reading Data
16
ADS7864
www.ti.com
SBAS141A–SEPTEMBER 2000–REVISED MARCH 2005
Table 2. Channel Truth Table
OUTPUT CODE (DB15…DB0)
DATA CHANNEL
DB14
DB13
DB12
The ADS7864 has a 16-bit output word. DB15 is ‘1’ if
the output contains valid data. This is important for
the FIFO mode. Valid Data can be read until DB15
switches to 0. DB14, DB13 and DB12 store channel
information as indicated in Table 2 (Channel Truth
Table). The 12-bit output data is stored from DB11
(MSB) to DB0 (LSB).
A0
A1
B0
B1
C0
C1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
BYTE—If there is only an 8-bit bus available on a
board, then Byte can be set high (see Figure 29 and
Figure 30). In this case, the lower eight bits can be
read at the output pins DB7 to DB0 at the first RD
signal, and the higher bits after the second RD signal.
HOLDA
HOLDC
BUSY
CS
RD
BYTE
Figure 29. Reading Data in Cycling Mode
CS
RD
BYTE
A0
A0
A1
A1
B0
B0
B1
C0
C1
A0
LOW
HIGH
LOW
HIGH
LOW
HIGH
Figure 30. Reading Data in Cycling Mode
17
ADS7864
www.ti.com
SBAS141A–SEPTEMBER 2000–REVISED MARCH 2005
GETTING DATA
from channel A0 is read on the first RD signal, then
A1 on the second, followed by B0, B1, C0 and finally
C1 before reading A0 again. Data from channel A0 is
brought to the output first after a reset-signal or after
powering the part up.
The ADS7864 has three different output modes that
are selected with A2, A1 and A0. A2A1A0 are only
active when RD and CS are both low. After a reset
occurs, A2A1A0 are set to 000.
The third mode is a FIFO mode that is addressed
with (A2 A1 A0 = 111). Data of the channel that is
converted first will be read first. So, if a particular
channel is most interesting and is converted more
frequently (e.g., to get a history of a particular
channel) then there are three output registers per
channel available to store data. When the ADS7864
is operated in the FIFO mode, an initial RD/CS is
necessary (after power up and after reset), so that
the internal address is set to ‘111’, before the first
conversion starts.
With (A2 A1 A0) = 000 to 101 a particular channel
can directly be addressed (see Table 3 and Fig-
ure 27). The channel address should be set at least
10ns (see Figure 28, t12) before the falling edge of
RD and should not change as long as RD is low.
Table 3. Address/Mode Truth Table
CHANNEL
SELECTED/
MODE
A2
0
A1
0
A0
0
A0
If a read process is just going on (RD signal low) and
new data has to be stored, then the ADS7864 will
wait until the read process is finished (RD signal
going high) before the new data gets latched into its
output register.
A1
0
0
1
B0
B1
0
1
0
0
1
1
C0
1
0
0
C1
1
0
1
At time tA (see Figure 31) the ADS7864 resets. With
the reset signal, all conversions and scheduled con-
versions are cancelled. The data in the output regis-
ters are also cleared. With a reset, a running conver-
sion gets interrupted and all channels go into the
sample mode again.
Cycle Mode
FIFO Mode
1
1
0
1
1
1
With (A2 A1 A0) = 110 the interface is running in a
cycle mode (see Figure 29 and Figure 30). Here, data
RESET
CLOCK
HOLDA
HOLDB
HOLDC
tA
tB
tC
tD tE tF
Figure 31. Example of Hold Signals
18
ADS7864
www.ti.com
SBAS141A–SEPTEMBER 2000–REVISED MARCH 2005
At time tB a HOLDB signal occurs. With the next
falling clock edge (tC) the ADS7864 puts channel B
into the loop to be converted next. As the reset signal
occurred at tA, the conversion of channel B will be
started with the next rising edge of the clock after tC.
Bit 15 shows if the FIFO is empty (low) or if it
contains channel information (high). Bits 12 to 14
contain the Channel for the 12-bit data word (Bit 0 to
11). If the data is from channel A0, then bits 14 to 12
are ‘000’. The Channel bit pattern is outlined in
Table 2 (Channel Truth Table).
Within the next clock cycle (tC to tF), HOLDC (tD) and
HOLDA (tE) occur. If more than one hold signals get
active within one clock cycle, channel A will be
converted first. Therefore, as soon as the conversion
of channel B is done, the conversion of channel A will
be initiated. After this second conversion, channel C
will be converted.
New data is always written into the next available
register. At t0 (see Figure 32), the reset deletes all the
existing data. At t1 the new data of the channels A0
and A1 are put into registers 0 and 1. On t2 the read
process of channel A0 data is finished. Therefore,
this data is dumped and A1 data is shifted to register
0. At t3 new data is available, this time from channel
B0 and B1. This data is written into the next available
registers (register 1 and 2). The new data of channel
C0 and C1 at t4 is put on top (registers 3 and 4).
The 16 bit output word has following structure:
3-Bit Channel
Information
Valid Data
12-Bit Data Word
RESET
BUSY
Conversion
Channel A
Conversion
Channel B
Conversion
Channel C
RD
reg. 5
reg. 4
reg. 2
reg. 3
reg. 1
reg. 0
empty
empty
empty
empty
empty
empty
empty
empty
empty
empty
ch A1
ch A0
empty
empty
empty
empty
ch B1
ch B0
ch A1
empty
ch C1
ch C0
ch B1
ch B0
ch A1
empty
empty
empty
empty
ch A1
t0
t1
t2
t3
t4
Figure 32. Functionality Diagram of FIFO Registers
19
ADS7864
www.ti.com
SBAS141A–SEPTEMBER 2000–REVISED MARCH 2005
LAYOUT
10µF capacitor is recommended. If needed, an even
larger capacitor and a 5Ω or 10Ω series resistor may
be used to low-pass filter a noisy supply. On average,
the ADS7864 draws very little current from an exter-
nal reference as the reference voltage is internally
buffered. If the reference voltage is external and
originates from an op amp, make sure that it can
drive the bypass capacitor or capacitors without
oscillation. A bypass capacitor must not be used
when using the internal reference (tie pin 33 directly
to pin 34). The AGND and DGND pins should be
connected to a clean ground point. In all cases, this
should be the ‘analog’ ground. Avoid connections
which are too close to the grounding point of a
microcontroller or digital signal processor. If required,
run a ground trace directly from the converter to the
power supply entry point. The ideal layout will include
an analog ground plane dedicated to the converter
and associated analog circuitry.
For optimum performance, care should be taken with
the physical layout of the ADS7864 circuitry. This is
particularly true if the CLOCK input is approaching
the maximum throughput rate. The basic SAR archi-
tecture is sensitive to glitches or sudden changes on
the power supply, reference, ground connections and
digital inputs that occur just prior to latching the
output of the analog comparator. Thus, driving any
single conversion for an n-bit SAR converter, there
are n 'windows' in which large external transient
voltages can affect the conversion result. Such
glitches might originate from switching power
supplies, nearby digital logic or high power devices.
The degree of error in the digital output depends on
the reference voltage, layout, and the exact timing of
the external event. These errors can change if the
external event changes in time with respect to the
CLOCK input. With this in mind, power to the
ADS7864 should be clean and well-bypassed. A
0.1µF ceramic bypass capacitor should be placed as
close to the device as possible. In addition, a 1µF to
20
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS7864Y/250
ADS7864Y/250G4
ADS7864Y/2K
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TQFP
TQFP
TQFP
TQFP
PFB
PFB
PFB
PFB
48
48
48
48
250
250
RoHS & Green
RoHS & Green
Call TI
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
ADS7864Y
Samples
Samples
Samples
Samples
Call TI
NIPDAU
Call TI
ADS7864Y
ADS7864Y
2000 RoHS & Green
250 RoHS & Green
2000 RoHS & Green
ADS7864YB/250
ADS7864Y
B
ADS7864YB/2K
ACTIVE
TQFP
PFB
48
NIPDAU
Level-2-260C-1 YEAR
ADS7864Y
B
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Feb-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS7864Y/2K
TQFP
TQFP
PFB
PFB
48
48
2000
2000
330.0
330.0
16.4
16.4
9.6
9.6
9.6
9.6
1.5
1.5
12.0
12.0
16.0
16.0
Q2
Q2
ADS7864YB/2K
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Feb-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS7864Y/2K
TQFP
TQFP
PFB
PFB
48
48
2000
2000
350.0
350.0
350.0
350.0
43.0
43.0
ADS7864YB/2K
Pack Materials-Page 2
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
Gage Plane
6,80
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4073176/B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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