ADS7865_14 [TI]
Dual, 12-Bit, 33 or 22 Channel, Simultaneous Sampling Analog-to-Digital Converter;
| 型号： | ADS7865_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual, 12-Bit, 33 or 22 Channel, Simultaneous Sampling Analog-to-Digital Converter |
| 文件： | 总30页 (文件大小：695K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS7865
www.ti.com.............................................................................................................................................................................................. SBAS441–OCTOBER 2008
Dual, 12-Bit, 3+3 or 2+2 Channel, Simultaneous Sampling
Analog-to-Digital Converter
1
FEATURES
DESCRIPTION
2
•
Six Pseudo- or Four Fully Differential Inputs
The ADS7865 is
a
dual, 12-bit, 2MSPS
analog-to-digital converter (ADC) with four fully
differential or six pseudo-differential input channels
grouped into two pairs for high-speed, simultaneous
signal acquisition. Inputs to the sample-and-hold
(S/H) amplifiers are fully differential and are
maintained differentially to the input of the ADC. This
architecture provides excellent common-mode
rejection of 72dB at 100kHz, which is a critical
performance characteristic in noisy environments.
•
•
•
SNR: 71.7dB, THD: –87dB
Programmable Channel Sequencer
Programmable and Buffered Internal 2.5V
Reference
•
•
•
•
Flexible Power-Down Features
Variable Power-Supply Ranges: 2.7V to 5.5V
Low-Power Operation: 44mW Maximum at 5V
Operating Temperature Range:
–40°C to +125°C
The ADS7865 is pin-compatible with the ADS7862,
but offers additional features such as
a
•
Pin-Compatible Upgrade for the ADS7862
programmable channel sequencer and reference
output, flexible supply voltage (2.7V to 5.5V for AVDD
and BVDD), a pseudo-differential input multiplexer with
three channels per ADC, and several power-down
features.
APPLICATIONS
•
•
•
Motor Control
Multi-Axis Positioning Systems
Three-Phase Power Control
The ADS7865 is offered in a TQFP-32 package. It is
specified over the extended operating temperature
range of –40°C to +125°C.
SAR
BVDD
AVDD
CHA0+
DB[11:0]
CHA0-
Input
MUX
CDAC
S/H
CHA1+
CHA1-
Comparator
CS
CLOCK
WR
CHB0+
CHB0-
Input
MUX
CDAC
S/H
RD
CHB1+
BUSY
CHB1-
Comparator
CONVST
REFIN
BGND
SAR
REFOUT
AGND
10-Bit DAC
2.5V Reference
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
ADS7865
SBAS441–OCTOBER 2008.............................................................................................................................................................................................. www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PACKAGE
DESIGNATOR
TRANSPORT MEDIA,
QUANTITY
PRODUCT
PACKAGE-LEAD
ORDERING NUMBER
ADS7865IPBS
Tray, 250
ADS7865I
TQFP-32
PBS
ADS7865IPBSR
Tray, 2500
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
ADS7865
–0.3 to +6
UNIT
V
Supply voltage, AVDD to AGND
Supply voltage, BVDD to BGND
–0.3 to +6
V
Supply voltage, BVDD to AVDD
1.5 × AVDD
V
Analog and reference input voltage with respect to AGND
Digital input voltage with respect to BGND
Ground voltage difference |AGND – BGND|
Input current to all pins except power-supply pins
Maximum virtual junction temperature, TJ
Human body model (HBM),
AGND – 0.3 to AVDD + 0.3
BGND – 0.3 to BVDD + 0.3
0.3
V
V
V
–10 to +10
mA
°C
+150
±4000
±1500
V
V
JEDEC standard 22, test method A114-C.01, all pins
ESD ratings
Charged device model (CDM),
JEDEC standard 22, test method C101, all pins
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range, unless otherwise noted.
ADS7865
PARAMETER
MIN
2.7
NOM
MAX
5.5
UNIT
V
Supply voltage, AVDD to AGND
Supply voltage, BVDD to BGND
Reference input voltage on REFIN
5.0
Low voltage levels
5V logic levels
2.7
3.6
V
4.5
5.0
2.5
5.5
V
0.5
2.525
+VREF
+125
V
Analog differential input voltage (CHXX+) – (CHXX–)
Operating ambient temperature range, TA
–VREF
–40
V
°C
THERMAL CHARACTERISTICS(1)
Over operating free-air temperature range, unless otherwise noted.
PARAMETER
ADS7865
UNIT
°C/W
°C/W
mW
θJA
θJC
PD
Junction-to-air thermal resistance
High-K thermal resistance
56.4
20.8
44
Junction-to-case thermal resistance
Device power dissipation at AVDD = 5V and BVDD = 3.3V
(1) Tested in accordance with the High-K thermal metric definitions of EIA/JESD51-3 for leaded surface-mount packages with a 3×3 via
array.
2
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ADS7865
www.ti.com.............................................................................................................................................................................................. SBAS441–OCTOBER 2008
ELECTRICAL CHARACTERISTICS
At TA = –40°C to +125°C; over entire power-supply voltage range, VREF = 2.5V (internal), fCLK = 32MHz, and fDATA = 2MSPS,
unless otherwise noted.
ADS7865
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
RESOLUTION
12
Bits
ANALOG INPUT
FSR
VIN
Full-scale differential input range
Absolute input voltage
(CHxx+) – (CHxx–)
–VREF
–0.1
+VREF
V
CHxx+ or CHxx– to AGND
CHxx+ or CHxx– to AGND
AVDD + 0.1
V
CIN
Input capacitance
2
4
pF
pF
nA
dB
CID
Differential input capacitance
Input leakage current
IIL
–50
50
CMRR
Common-mode rejection ratio
Both ADCs, dc to 100kHz
72
DC ACCURACY
–40°C < TA < +125°C
–40°C < TA < +85°C
–1.25
–1
±0.6
±0.5
±0.4
±0.5
±0.5
±2
+1.25
+1
LSB
LSB
LSB
LSB
LSB
µV/°C
%
INL
Integral nonlinearity
DNL
Differential nonlinearity(2)
Input offset error
Match
–1
+1
–3
+3
VOS
–3
+3
dVOS/dT
GERR
Input offset thermal drift
Gain error(2)
–0.6
–0.6
0.15
±0.1
±2
+0.6
+0.6
Match
%
GERR/dT
PSRR
Gain error thermal drift
Power-supply rejection ratio
ppm/°C
dB
AVDD = 5V
70
AC ACCURACY
SINAD
SNR
Signal-to-noise + distortion
VIN = 5VPP at 100kHz
VIN = 5VPP at 100kHz
VIN = 5VPP at 100kHz
VIN = 5VPP at 100kHz
69
70
71.3
71.7
–87
88
dB
dB
dB
dB
Signal-to-noise ratio
THD
Total harmonic distortion
Spurious-free dynamic range
–74
SFDR
74
SAMPLING DYNAMICS
tCONV Conversion time per ADC
tACQ
1MHz < fCLK ≤ 32MHz
1MHz < fCLK ≤ 32MHz
13
62.5
62.5
Clocks
ns
Acquisition time
Data rate
fDATA
2000
6
kSPS
ns
Aperture delay
Match
tA
50
50
ps
tAJIT
fCLK
Aperture jitter
Clock frequency on CLOCK
ps
1
32
MHz
(1) All values at TA = +25°C.
(2) Ensured by design, not production tested.
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ELECTRICAL CHARACTERISTICS (continued)
At TA = –40°C to +125°C; over entire power-supply voltage range, VREF = 2.5V (internal), fCLK = 32MHz, and fDATA = 2MSPS,
unless otherwise noted.
ADS7865
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
INTERNAL VOLTAGE REFERENCE
Resolution
Reference output DAC resolution
10
Bits
V
Over 20% to 100% DAC range
0.496
2.515
2.515
2.505
DAC = 0x3FF,
–40°C < TA < +125°C
VREFOUT
Reference output voltage
2.485
2.495
2.500
V
DAC = 0x3FF at +25°C
2.500
±10
±1
V
ppm/°C
LSB
LSB
LSB
dB
dVREFOUT/dT Reference voltage drift
DNLDAC
INLDAC
VOSDAC
PSRR
DAC differential linearity error
DAC integral linearity error
DAC offset error
–4
–4
–4
4
4
4
±0.5
±1
VREFOUT = 0.5V
Power-supply rejection ratio
Reference output dc current
73
IREFOUT
–2
+2
mA
Reference output short-circuit
current
IREFSC
50
mA
ms
tREFON
Reference output settling time
0.5
VOLTAGE REFERENCE INPUT
VREF Reference input voltage range
IREF
0.5
2.525
V
Reference input current
50
10
µA
pF
CREF
Reference input capacitance
DIGITAL INPUTS
Logic family
CMOS
VIH
VIL
IIN
High-level input voltage
Low-level input voltage
Input current
0.7 × BVDD
–0.3
BVDD + 0.3
0.3 × BVDD
+50
V
V
VI = BVDD to BGND
–50
nA
pF
CI
Input capacitance
5
DIGITAL OUTPUTS
Logic family
CMOS
VOH
VOL
High-level output voltage
Low-level output voltage
IOH = –100µA
IOH = 100µA
BVDD – 0.2
–50
V
V
0.2
High-impedance-state output
current
IOZ
VI = BVDD to BGND
+50
nA
CO
CL
Output capacitance
Load capacitance
5
pF
pF
30
4
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ADS7865
www.ti.com.............................................................................................................................................................................................. SBAS441–OCTOBER 2008
ELECTRICAL CHARACTERISTICS (continued)
At TA = –40°C to +125°C; over entire power-supply voltage range, VREF = 2.5V (internal), fCLK = 32MHz, and fDATA = 2MSPS,
unless otherwise noted.
ADS7865
PARAMETER
POWER SUPPLY
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
AVDD
BVDD
Analog supply voltage
AVDD to AGND
BVDD to BGND
2.7
2.7
5.0
3.0
4.1
5.6
0.9
1.1
5.5
5.5
V
Buffer I/O supply current
V
AVDD = 2.7V
6.0
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
AVDD = 5V
7.5
AVDD = 2.7V, NAP power-down
AVDD = 5V, NAP power-down
AVDD = 2.7V, deep power-down
AVDD = 5V, deep power-down
BVDD = 2.7V, CLOAD = 10pF
BVDD = 3.3V, CLOAD = 10pF
AVDD = 2.7V, BVDD = 2.7V
AVDD = 5.0V, BVDD = 3.0V
1.6
AIDD
Analog supply current
1.8
0.001
0.001
1.7
0.6
0.8
BIDD
PD
Buffer I/O supply current
Power dissipation
1.9
12.7
30.6
21
44
EQUIVALENT INPUT CIRCUIT
RSER = 200W
RSW = 50W
CHXX+
CPAR = 5pF
CS = 2pF
CS = 2pF
CPAR = 5pF
CHXX-
RSER = 200W
RSW = 50W
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DEVICE INFORMATION
PBS PACKAGE
TQFP-32
(TOP VIEW)
32 31 30 29 28 27 26 25
REFIN
BVDD
23 BGND
1
2
3
4
5
6
7
8
24
REFOUT
AGND
AVDD
22
21
20
WR
RD
CS
DB11
DB10
DB9
19 CLOCK
18
17 BUSY
CONVST
DB8
9
10 11 12 13 14 15 16
TERMINAL FUNCTIONS
PIN NUMBER
NAME
REFIN
REFOUT
AGND
AVDD
DB11
DB10
DB9
DESCRIPTION
1
2
Reference voltage input. A ceramic capacitor of 470nF (min) is required at this terminal.
Reference voltage output. The programmable internal voltage reference output is available on this pin.
3
Analog ground. Connect to analog ground plane.
4
Analog power supply, 2.7V to 5.5V. Decouple to AGND with a 1µF ceramic capacitor.
5
Data bit 11, MSB
Data bit 10
Data bit 9
Data bit 8
Data bit 7
Data bit 6
Data bit 5
Data bit 4
Data bit 3
Data bit 2
Data bit 1
Data bit 0
6
7
8
DB8
9
DB7
10
11
12
13
14
15
16
DB6
DB5
DB4
DB3
DB2
DB1
DB0
ADC busy indicator. BUSY goes high when the inputs are in hold mode and returns to low after the
conversion has been finished.
17
BUSY
Conversion start. The ADC switches from the sample into the hold mode on the falling edge of
CONVST, independent of the status of the CLOCK. The conversion itself starts with the next rising
edge of CLOCK.
18
CONVST
19
20
CLOCK
CS
External clock input.
Chip select. When low, the parallel interface of the device is active; when high, input signals are
ignored and output signals are 3-state.
Read data. Falling edge active synchronization pulse for the parallel data outputs. RD only triggers,
when CS is low.
21
22
RD
WR
Write data. Rising edge latches in the parallel data inputs. WR only triggers, when CS is low.
6
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www.ti.com.............................................................................................................................................................................................. SBAS441–OCTOBER 2008
TERMINAL FUNCTIONS (continued)
PIN NUMBER
NAME
BGND
BVDD
DESCRIPTION
Buffer I/O ground. Connect to digital ground plane.
23
24
25
26
27
28
29
30
31
32
Buffer I/O power supply, 2.7V to 5.5V. Decouple to BGND with a 1µF ceramic capacitor.
Noninverting analog input channel B1
CHB1+
CHB1–
CHB0+
CHB0–
CHA1–
CHA1+
CHA0–
CHA0+
Inverting analog input channel B1
Noninverting analog input channel B0
Inverting analog input channel B0
Inverting analog input channel A1
Noninverting analog input channel A1
Inverting analog input channel A0
Noninverting analog input channel A0
TIMING CHARACTERISTICS
Conversion Cycle
tCONV
1
14
16
CLOCK
tCLK
t1
tACQ
tCLKH
tCLKL
CONVST
BUSY
t3
t2
t4
t5
CS
t8
t6
t7
t6
t7
WR
RD
t9
t14
t12
t10
t11
t13
CHAx
Output
CHBx
Output
Input
Data
DB[11:0]
Previous Conversion Results
Figure 1. Interface Timing Diagram
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TIMING REQUIREMENTS(1)
ADS7865
PARAMETER
Conversion time
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tCLK
ns
tCONV
tACQ
fCLK
tCLK
tCLKL
tCLKH
t1
fCLOCK = 32MHz
13
Acquisition time
CLOCK frequency
CLOCK period
62.5
1
32
MHz
ns
31.25
9.4
1000
CLOCK low time
CLOCK high time
CONVST low time
ns
9.4
ns
20
ns
CONVST falling edge to BUSY high
delay(2)
t2
3
ns
t3
t4
t5
CONVST high time
20
1
ns
tCLK
ns
RD falling edge to BUSY high setup time
14th CLOCK rising edge to BUSY low delay
3
See Figure 1
CS falling edge to RD or WR falling edge
setup time
t6
t7
0
0
ns
ns
CS rising edge to RD or WR rising edge
hold time
t8
WR low time
10
10
ns
ns
ns
ns
ns
ns
t9
RD high time between two read accesses
RD falling edge to output data valid delay
Output data hold time
t10
t11
t12
t13
20
5
10
5
Input data setup time
Input data hold time
Input data still valid to CONVST falling edge
setup time
t14
31.25
ns
(1) All input signals are specified with tR = tF = 1.5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2.
(2) Not applicable in auto-Nap power-down mode.
CLOCK
Cycle 1
5ns
Cycle 2
5ns
10ns
10ns
CONVST
A
B
C
NOTE: All CONVST commands that occur more than 10ns before the rising edge of cycle '1' of the external clock (Region 'A') initiate a
conversion on the rising edge of cycle '1'. All CONVST commands that occur 5ns after the rising edge of cycle '1' or 10ns before the rising
edge of cycle '2' (Region 'B') initiate a conversion on the rising edge of cycle '2'. All CONVST commands that occur 5ns after the rising edge
of cycle '2' (Region 'C') initiate a conversion on the rising edge of the next clock period.
The CONVST pin should never be switched from LOW to HIGH in the region 10ns before the rising edge of the CLOCK and 5ns after the
rising edge (gray areas). If CONVST is toggled in this gray area, the conversion could begin on either the same rising edge of the CLOCK or
the following edge.
Figure 2. CONVST Timing
8
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TYPICAL CHARACTERISTICS
Over the entire supply voltage range; VREF = 2.5V (internal), fCLK = 32MHz, and fDATA = 2MSPS, unless otherwise noted.
INTEGRAL NONLINEARITY vs
DATA RATE
INTEGRAL NONLINEARITY vs
TEMPERATURE
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
Positive
Positive
-0.25
-0.50
-0.75
-1.00
-0.25
-0.50
-0.75
-1.00
Negative
Negative
-40 -25 -10
5
20 35 50 65 80 95 110 125
0.50
0.75
1.00
1.25
1.50
1.75
2.00
Temperature (°C)
Data Rate (MSPS)
Figure 3.
Figure 4.
INTEGRAL NONLINEARITY vs CODE
DIFFERENTIAL NONLINEARITY vs CODE
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
512 1024 1536 2048 2560 3072 3584 4096
0
512 1024 1536 2048 2560 3072 3584 4096
Code
Code
Figure 5.
Figure 6.
DIFFERENTIAL NONLINEARITY vs
DATA RATE
DIFFERENTIAL NONLINEARITY vs
TEMPERATURE
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
Positive
Positive
-0.25
-0.50
-0.75
-1.00
-0.25
-0.50
-0.75
-1.00
Negative
Negative
-40 -25 -10
5
20 35 50 65 80 95 110 125
0.50
0.75
1.00
1.25
1.50
1.75
2.00
Temperature (°C)
Data Rate (MSPS)
Figure 7.
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
Over the entire supply voltage range; VREF = 2.5V (internal), fCLK = 32MHz, and fDATA = 2MSPS, unless otherwise noted.
OFFSET ERROR AND OFFSET MATCH vs
ANALOG SUPPLY VOLTAGE
OFFSET ERROR AND OFFSET MATCH vs
TEMPERATURE
2.0
1.5
1.0
0.8
Offset Match
Offset Error
0.6
1.0
0.4
Offset Match
Offset Error
0.5
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-0.5
-1.0
-1.5
-2.0
-1.0
-40 -25 -10
5
20 35 50 65 80 95 110 125
2.7
2.7
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
5.4
5.4
5.4
Temperature (°C)
AVDD (V)
Figure 9.
Figure 10.
GAIN ERROR AND GAIN MATCH vs
ANALOG SUPPLY VOLTAGE
GAIN ERROR AND GAIN MATCH vs
TEMPERATURE
0.20
0.15
0.10
0.05
0
0.5
0.4
Gain Error
0.3
Gain Error
0.2
Gain Match
0.1
Gain Match
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.05
-0.10
-0.15
-0.20
-40 -25 -10
5
20 35 50 65 80 95 110 125
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
Temperature (°C)
AVDD (V)
Figure 11.
Figure 12.
COMMON-MODE REJECTION RATIO vs
ANALOG SUPPLY VOLTAGE
COMMON-MODE REJECTION RATIO vs
TEMPERATURE
74.0
73.5
73.0
72.5
72.0
71.5
71.0
70.5
70.0
74.0
73.5
73.0
72.5
72.0
71.5
71.0
70.5
70.0
-40 -25 -10
5
20 35 50 65 80 95 110 125
3.0
3.3
3.6
3.9
4.2
4.5
4.8
5.1
Temperature (°C)
AVDD (V)
Figure 13.
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
Over the entire supply voltage range; VREF = 2.5V (internal), fCLK = 32MHz, and fDATA = 2MSPS, unless otherwise noted.
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 100kHz)
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 100kHz, fSAMPLE = 1.5MSPS)
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
200k
400k
600k
800k
1M
0
100
200
300
400
500
600
700 750
Frequency (Hz)
Frequency (kHz)
Figure 15.
Figure 16.
SIGNAL-TO-NOISE RATIO AND DISTORTION
vs INPUT SIGNAL FREQUENCY
SIGNAL-TO-RATIO AND DISTORTION
vs TEMPERATURE
74
73
72
71
70
69
73.0
72.5
72.0
71.5
71.0
70.5
70.0
69.5
69.0
AVDD = 5V
AVDD = 5V
AVDD = 2.7V
AVDD = 2.7V
68
10
30
40
70
90 110 130 150 170 190 200
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
fIN (kHz)
Figure 17.
Figure 18.
SIGNAL-TO-NOISE RATIO
vs INPUT SIGNAL FREQUENCY
SIGNAL-TO-NOISE RATIO
vs TEMPERATURE
74
73
72
71
70
69
73.0
72.5
72.0
71.5
71.0
70.5
70.0
AVDD = 5V
AVDD = 5V
AVDD = 2.7V
AVDD = 2.7V
68
10
30
50
70
90 110 130 150 170 190 200
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
fIN (kHz)
Figure 19.
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
Over the entire supply voltage range; VREF = 2.5V (internal), fCLK = 32MHz, and fDATA = 2MSPS, unless otherwise noted.
TOTAL HARMONIC DISTORTION
vs INPUT SIGNAL FREQUENCY
TOTAL HARMONIC DISTORTION
vs TEMPERATURE
-78
-80
-82
-84
-86
-88
-90
-76
-78
-80
-82
-84
-86
-88
-90
AVDD = 5V
AVDD = 5V
AVDD = 2.7V
AVDD = 2.7V
-92
-40 -25 -10
5
20 35 50 65 80 95 110 125
10
30
40
70
90 110 130 150 170 190 200
Temperature (°C)
fIN (kHz)
Figure 21.
Figure 22.
SPURIOUS-FREE DYNAMIC RANGE
vs INPUT SIGNAL FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE
vs TEMPERATURE
92
90
88
86
84
82
94
92
90
88
86
84
82
80
78
AVDD = 5V
AVDD = 5V
AVDD = 2.7V
AVDD = 2.7V
-40 -25 -10
5
20 35 50 65 80 95 110 125
10
30
40
70
90 110 130 150 170 190 200
Temperature (°C)
fIN (kHz)
Figure 23.
Figure 24.
ANALOG SUPPLY CURRENT
vs TEMPERATURE
DIGITAL SUPPLY CURRENT
vs TEMPERATURE
8
7
6
5
4
3
2
1
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
AVDD = 5V
BVDD = 3.3V
BVDD = 2.7V
AVDD = 2.7V
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Temperature (°C)
Figure 25.
Figure 26.
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TYPICAL CHARACTERISTICS (continued)
Over the entire supply voltage range; VREF = 2.5V (internal), fCLK = 32MHz, and fDATA = 2MSPS, unless otherwise noted.
ANALOG SUPPLY CURRENT
vs DATA RATE
ANALOG SUPPLY CURRENT
vs TEMPERATURE
(Auto-NAP Mode)
(Auto-NAP Mode)
6
5
4
3
2
1
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
AVDD = 5V
Reference ON
AVDD = 2.7V
Reference OFF
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
0
500
1000
1500
Temperature (°C)
Data Rate (kSPS)
Figure 27.
Figure 28.
ANALOG SUPPLY CURRENT
vs DATA RATE
(Deep Power-Down Mode)
REFERENCE OUTPUT VOLTAGE
vs TEMPERATURE
3500
3000
2500
2000
1500
1000
500
2.505
2.504
2.503
2.502
2.501
2.500
2.499
2.498
2.497
2.496
2.495
Clock ON
Clock OFF
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
0
10
20
30
40
50
60
70
Temperature (°C)
Data Rate (kSPS)
Figure 29.
Figure 30.
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APPLICATION INFORMATION
GENERAL DESCRIPTION
CHx1+
The ADS7865 includes two 12-bit analog-to-digital
converters (ADCs) that operate based on the
successive-approximation register (SAR) principle.
CHx1-
ADC+
Input
MUX
ADC-
CHx0+
The ADCs sample and convert simultaneously.
Conversion time can be as low as 406.25ns. Adding
CHx0-
the acquisition time of 62.5ns and an additional clock
cycle for setup/hold time requirements and skew
results in a maximum conversion rate of 2MSPS.
Figure 31. Input Multiplexer Configuration
Each ADC has a fully differential 2:1 multiplexer
front-end. In many common applications, all negative
input signals remain at the same constant voltage (for
example, 2.5V). In this type of application, the
multiplexer can be used in a pseudo-differential 3:1
mode, where CHx0– functions as a common-mode
input and the remaining three inputs (CHx0+, CHx1–,
and CHx1+) operate as separate inputs referred to
the common-mode input.
Table 1. Fully Differential 2:1 Multiplexer
Configuration
C1
0
C0
0
ADC+
CHx0+
CHx1+
ADC–
CHx0–
CHx1–
1
1
Table 2. Pseudo-Differential 3:1 Multiplexer
Configuration
The ADS7865 also includes a 2.5V internal reference.
C1
0
C0
0
ADC+
CHx0+
CHx1–
CHx1+
ADC–
CHx0–
CHx0–
CHx0–
The reference drives
a
10-bit digital-to-analog
converter (DAC), allowing the voltage at the REFOUT
pin to be adjusted via the internal DAC register in
2.44mV steps. A low-noise operational amplifier with
unity-gain buffers the DAC output voltage and drives
the REFOUT pin.
0
1
1
0
The input path for the converter is fully differential
and provides a common-mode rejection of 72dB at
100kHz. The high CMRR also helps suppress noise
in harsh industrial environments.
The ADS7865 offers a parallel interface that is
pin-compatible with the ADS7862. However, instead
of the A0 pin of the ADS7862 that controls channel
selection, the ADS7865 offers a write data input (WR)
pin that supports additional functions described in the
Digital section of this data sheet (see also the
ADS7862 Compatibility section).
Each of the 2pF sample-and-hold capacitors (shown
as CS in the Equivalent Input Circuit) is connected via
switches to the multiplexer output. Opening the
switches holds the sampled data during the
conversion process. After finishing the conversion,
both capacitors are pre-charged for the duration of
one clock cycle to the voltage present at the REFIN
pin. After the pre-charging, the multiplexer outputs
are connected to the sampling capacitors again. The
voltage at the analog input pin is usually different
from the reference voltage; therefore, the sample
capacitors must be charged to within one-half LSB for
12-bit accuracy during the acquisition time tACQ (see
the Timing Characteristics).
ANALOG
This section discusses the analog input circuit, the
ADCs, and the reference design of the device.
Analog Inputs
Each ADC is fed by an input multiplexer, as shown in
Figure 31. Each multiplexer is either used in a
fully-differential 2:1 configuration (as described in
Table 1) or a pseudo-differential 3:1 configuration (as
shown in Table 2). The channel selection is
performed using bits C1 and C0 in the configuration
register (see also the Configuration Register section).
Acquisition time is indicated with the BUSY signal
being held low. It starts by closing the input switches
(after finishing the previous conversion and
pre-charging) and finishes with the rising edge of the
CONVST signal. If the ADS7865 operates at full
speed, the acquisition time is typically 62.5ns.
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The minimum –3dB bandwidth of the driving
operational amplifier can be calculated as shown in
Equation 1, with n = 12 being the resolution of the
ADS7865:
sampling. With a minimum of 16 clocks used for the
entire process, one clock cycle is left for the required
setup and hold times along with some margin for
delay caused by layout. The clock input can remain
low between conversions (after applying the 16th
falling edge to complete a running conversion). It can
also remain low after applying the 14th falling edge
during a DAC register write access if the device is not
required to perform a conversion (for example, during
an initiation phase after power-up).
ln(2) ´ (n + 1)
f
=
-3dB
2p ´ tACQ
(1)
With tACQ = 62.5ns, the minimum bandwidth of the
driving amplifier is 23MHz. The required bandwidth
can be lower if the application allows a longer
acquisition time.
The CLOCK duty cycle should be 50%. However, the
ADS7865 functions properly with
between 30% and 70%.
a duty cycle
A gain error occurs if a given application does not
fulfill the settling requirement shown in Equation 1. As
a result of pre-charging the capacitors, linearity and
THD are not directly affected, however.
RESET
The ADS7865 features an internal power-on reset
(POR) function. However, an external reset can also
be issued using SDI Register bits A[2:0] (see the
Digital section).
The
OPA365
from
Texas
Instruments
is
recommended as a driver; in addition to offering the
required bandwidth, it provides a low offset and also
offers excellent THD performance.
REFIN
The phase margin of the driving operational amplifier
is usually reduced by the ADC sampling capacitor. A
resistor placed between the capacitor and the
amplifier limits this effect; therefore, an internal 200Ω
resistor (RSER) is placed in series with the switch. The
switch resistance (RSW) is typically 50Ω (see the
Equivalent Input Circuit).
The reference input is not buffered and is directly
connected to the ADC. The converter generates
spikes on the reference input voltage because of
internal switching. Therefore, an external capacitor to
the analog ground (AGND) should be used to
stabilize the reference input voltage. This capacitor
should be at least 470nF. Ceramic capacitors (X5R
type) with values up to 1µF are commonly available
as SMD in 0402 size.
The differential input voltage range of the ADC is
±VREF, the voltage at the REFIN pin.
It is important to keep the voltage to all inputs within
the 0.1V limit below AGND and above AVDD while not
allowing dc current to flow through the inputs. Current
is only necessary to recharge the sample-and-hold
capacitors.
REFOUT
The ADS7865 includes a low-drift, 2.5V internal
reference source. This source feeds a 10-bit string
DAC that is controlled via the DAC register. As a
result of this architecture, the voltage at the REFOUT
pin is programmable in 2.44mV steps and can be
adjusted to specific application requirements without
the use of additional external components.
Analog-to-Digital Converter (ADC)
The ADS7865 includes two SAR-type, 2MSPS, 12-bit
ADCs (shown in the Functional Block Diagram on the
front page of this data sheet).
However, the DAC output voltage should not be
programmed below 0.5V to ensure the correct
functionality of the reference output buffer. This buffer
is connected between the DAC and the REFOUT pin,
and is capable of driving the capacitor at the REFIN
pin. A minimum of 470nF is required to keep the
reference stable (see the previous discussion of
REFIN). For applications that use an external
reference source, the internal reference can be
disabled using bit RP in the SDI Register (see the
Digital section). The settling time of the REFOUT pin is
500µs (max) with the reference capacitor connected.
The default value of the REFOUT pin after power-up is
2.5V.
CONVST
The analog inputs are held with the falling edge of the
CONVST (conversion start) signal. The setup time of
CONVST referred to the next rising edge of CLOCK
(system clock) is 10ns (minimum). The conversion
automatically starts with the rising CLOCK edge.
CONVST should not be issued during a conversion,
that is, when BUSY is high.
CLOCK
The ADC uses an external clock in the range of
1MHz to 32MHz. 12 clock cycles are needed for a
complete conversion; the following clock cycle is used
for pre-charging the sample capacitors and
a
minimum of two clock cycles are required for the
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Table 6. R1 and R0: Register Update Enable
For operation with a 2.7V analog supply and a 2.5V
reference, the internal reference buffer requires a
rail-to-rail input and output. Such buffers typically
contain two input stages; when the input voltage
passes the mid-range area, a transition occurs at the
output because of switching between the two input
stages. In this voltage range, rail-to-rail amplifiers
generally show a very poor power-supply rejection.
R1
0
R0
0
FUNCTION
Register update disabled
Register update enabled
0
1
Reserved for factory test (don’t
use)
1
1
0
1
Register update disabled
As a result of this poor performance, the ADS7865
buffer has a fixed transition at DAC code 509
(0x1FD). At this code, the DAC may show a jump of
up to 10mV in its transfer function.
DP: Deep power-down enable
('1' = device in deep power-down mode)
N: Nap power-down enable
('1' = device in nap power-down mode)
Table 3 lists some examples of internal reference
DAC settings.
AN: AutoNap power-down enable
('1' = device in autonap power-down mode)
Table 3. Reference DAC Setting Examples
RP: Reference power-down
DECIMAL
CODE
HEXADECIMAL
CODE
VREFOUT
0.500V
1.241V
1.240V
2.500V
BINARY CODE
00 1100 1101
01 1111 1100
01 1111 1101
11 1111 1111
('1' = reference is turned off)
205
508
CD
1FC
1FD
3FF
Table 7. A2, A1, and A0: DAC, Sequencer, and
SW-Reset Control
509
A2
A1
A0
FUNCTION
1023
Configuration register
update only
0
0
0
DIGITAL
Write to reference DAC
register with next access
0
0
0
1
1
0
This section reviews the timing and control of the
ADS7865 parallel interface.
Configuration register
update only
Read from reference
DAC register with next
access
Configuration Register
0
1
1
The configuration register can be set by issuing a
write access on the parallel interface. The data
present on DB[11:0] are latched with the rising edge
of WR. The data word width of the configuration
register is 12 bits; its structure is shown in Table 4.
The default value of this register after power-up is
0x000.
Write to sequencer
register
1
1
1
0
0
1
0
1
0
Device SW-reset
Read from sequencer
register
Configuration register
update only
1
1
1
Table 4. Configuration Register Map
All enabled power-down features are activated by the
rising edge of the WR pulse immediately after writing
to the configuration register.
CONFIGURATION REGISTER BIT
11 10
9
8
7
6
5
4
3
2
1
0
C1 C0 R1 R0 DP
(1) X = Don't care.
N
AN RP X(1) A2 A1 A0
Because two write accesses are required to program
the reference DAC and the sequencer registers,
these settings are updated with the rising edge of WR
after the second write access. For more details, see
the Sequencer Register and Programming the
Reference DAC sections.
Table 5. C1 and C0: Channel Selection
ADC A/B
C1
0
C0
0
POSITIVE INPUT
CHA0+/CHB0+
CHA1–/CHB1–
CHA1+/CHB1+
CHA1+/CHB1+
NEGATIVE INPUT
CHA0–/CHB0–
CHA0–/CHB0–
CHA0–/CHB0–
CHA1–/CHB1–
0
1
1
0
1
1
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Figure 32 shows
a
complete timing diagram
The input multiplexer updates with the rising edge of
the WR input. The following falling edge of CONVST
triggers the conversion of the previously selected
channel. The data output register then updates with
the falling edge of BUSY and can be read thereafter.
The digital output code format of the ADS7865 is in
binary twos complement, as shown in Table 8.
consisting of a write access to set up the proper input
channel, followed by an initiation of a conversion and
the read access of both conversion results.
1
14
14 16
CLOCK
CONVST
WR
CS
RD
Output
CHAx
Output
CHBx
Output
CHA0
Output
CHB0
DB[11:0]
100h
D00h
Previous Conversion
of Both CHxx
Conversion of
Both Differential CHx0
Conversion of
Both Differential CHx1
BUSY
Figure 32. Channel Selection Timing Diagram
Table 8. ADS7865 Output Data Format
DIFFERENTIAL INPUT VOLTAGE
INPUT VOLTAGE AT CHXX+
(CHXX– = VREF = 2.5V)
HEXADECIMAL
CODE
DESCRIPTION
(CHXX+) – (CHXX–)
BINARY CODE
0111 1111 1111
0000 0000 0000
1111 1111 1111
Positive full-scale
Midscale
VREF
0V
5V
7FF
000
FFF
2.5V
Midscale – 1LSB
–VREF/4096
2.49878V
Negative
full-scale
–VREF
0V
1000 0000 0000
800
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Sequencer Register
The structure of the sequencer register is shown in
Table 9. The default value of this register after
power-up is 0x000.
The ADS7865 features a programmable sequencer
that controls the switching of the ADC input
multiplexer. To set up the sequencer, two write
accesses to the ADC are required. During the first
write access, the programming of the sequencer must
be enabled by setting R[1:0] = '01' and A[2:0] = '100'
in the configuration register. The data applied to the
data bus on the second write access contain the
updated sequencer register content.
Detailed timing diagrams of the different sequencer
modes are shown in Figure 33.
Figure 34 shows an example where the sequencer is
set to scan through the pseudo-differential inputs of
the ADS7865 beginning with CHx1+, followed by
CHx1–, and CHx0+ while using a single CONVST
and BUSY for the entire sequence.
Table 9. Sequencer Register Map
SEQUENCER REGISTER BIT
11
10
9
8
7
6
5
4
3
2
1
0
S1
S0
SL1
SL0
CH1
CM1
CH2
CM2
CH3
CM3
SP1
SP0
Table 10. S1 and S0: Sequencer Mode
S1
S0
FUNCTION
Individual CONVST and BUSY for each conversion
0
X
0
1
Single CONVST for entire sequence and individual BUSY for each
conversion
1
1
Single CONVST and BUSY for entire sequence
Table 11. SL1 and SL0: Sequence Length
Table 12. Channel Selection
SL1
SL0
FUNCTION
ADC A/B
0
0
Length = 0: Sequencer disabled
COMMON-MODE
CHx
CMx
SIGNAL INPUT
CHA0+/CHB0+
CHA1–/CHB1–
CHA1+/CHB1+
CHA1+/CHB1+
INPUT
Length = 1: Cx1 (bits 6/7)
enabled
0
1
1
0
0
0
1
1
0
1
0
1
CHA0–/CHB0–
CHA0–/CHB0–
CHA0–/CHB0–
CHA1–/CHB1–
Length = 2: Cx1 (bits 6/7) and
Cx2 (bits 4/5) enabled
Length = 3: Cx1 (bits 6/7), Cx2
(bits 4/5), and Cx3 (bits 2/3)
enabled
1
1
Table 13. SP1 and SP0: Sequence Position
(Read-Only)
CH1: Signal input of the first channel in sequence;
refer to Table 12 for details.
SP1
SP0
FUNCTION
CM1: Common-mode input of the first channel in
0
0
Sequencer disabled
sequence; refer to Table 12 for details.
CH1/CM1 (bits 6/7) to be
converted at next falling edge
of CONVST
0
1
1
1
0
1
CH2: Signal input of the second channel in
sequence; refer to Table 12 for details.
CH2/CM2 (bits 4/5) to be
converted at next falling edge
of CONVST
CM2: Common-mode input of the second channel in
sequence; refer to Table 12 for details.
CH3/CM3 (bits 2/3) to be
converted at next falling edge
of CONVST
CH3: Signal input of the third channel in sequence;
refer to Table 12 for details.
CM3: Common-mode input of the third channel in
sequence; refer to Table 12 for details.
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Mode 0 (one-shot conversion start, one BUSY for whole sequence)
CONVST
BUSY
Conv A
Conv B
Conv C
Conv C
Mode 1 (one-shot conversion start, one BUSY for each conversion)
CONVST
BUSY
Conv A
Conv B
Mode 2 (one-conversion and one BUSY for each conversion)
CONVST
BUSY
Conv A
Conv B
Conv C
Figure 33. Sequencer Modes (Example: SL = '11')
16
32
1
CLOCK
CONVST
WR
CS
RD
Output
CHA1+
Output
CHB1+
Output
Output
DB[11:0]
0x104 0xF90
CHA1-
CHB1-
Conversion of
Both CH1+
Conversion of
Both CH1-
Conversion of
Both CH0+
BUSY
Figure 34. Sequencer Programming Example
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Programming the Reference DAC
be generated while providing
a
control word
containing R[1:0] = '01' and A[2:0] = '011' to initialize
the DAC read access. Thereafter, triggering the RD
line causes the data bus to provide the 10-bit DAC
value on DB[9:0].
The internal reference DAC can be set by issuing a
WR pulse while providing a control word with R[1:0] =
'01' and A[2:0] = '001' (see Table 4). Thereafter, a
second WR pulse must be generated with the data
bus bits DB[11:10] = '00' and DB[9:0] containing the
actual 10-bit DAC value, with DB9 being the MSB
(see Figure 35).
Table 14 shows the content of this register; the
default value after power-up is 0x3FF (see also
Table 3).
To verify the current DAC setting, a WR pulse must
Table 14. DAC Register Contents
DAC REGISTER CONTENT
11
10
9
8
7
6
5
4
3
2
1
0
0
0
MSB
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WR
CS
RD
DB[11:0]
b01xxxxx001
DAC Value
b01xxxxx011
DAC Value
Figure 35. DAC Write and Read Access Timing Diagram
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Power-Down Modes and Reset
The ADS7865 has comprehensive built-in
The auto-nap power-down mode is very similar to
the nap mode. The only differences are the methods
of powering down and waking up the device. The
Configuration Register bit AN is only used to
enable/disable this feature. If the auto-nap mode is
enabled, the ADS7865 turns off the biasing
automatically after finishing a conversion; thus, the
end of conversion actually activates the auto-nap
power-down. The device powers down within 200ns
in this mode, as well. Triggering a new conversion by
applying a CONVST pulse returns the device to
normal operation and automatically starts a new
conversion six CLOCK cycles later. Therefore, a
complete conversion cycle takes 22 CLOCK cycles;
thus, the maximum throughput rate in auto-nap
power-down mode is reduced to 1.45MSPS.
a
power-down feature. There are three power-down
modes: deep power-down, nap power-down, and
auto-nap power-down. All three power-down modes
are activated with the rising WR edge after having
been activated by asserting the corresponding bit in
the Configuration Register (DP = '1', N = '1', or AN =
'1'). All modes are deactivated by de-asserting the
respective bit in the Configuration Register. The
contents of the Configuration Register are not
affected by any of the power-down modes. Any
ongoing conversion aborts when deep or nap
power-down is initiated. Table 15 lists the differences
among the three power-down modes.
In deep power-down mode, all functional blocks
except the digital interface are disabled. The analog
block has its bias currents turned off. In this mode,
the power dissipation reduces to 1µA within 2µs. The
wake-up time from deep power-down mode is 1µs.
To issue a device reset, a write access to the
Configuration Register must be generated to set
A[2:0] = '101'. With the rising edge of the WR input,
the entire device is forced into reset. After
approximately 20ns, the parallel interface becomes
active again.
In nap power-down mode, the ADS7865 turns off
the biasing of the comparator and the mid-voltage
buffer within 200ns. The device goes into nap
power-down mode regardless of the conversion state.
Table 15. Power-Down Modes
POWER-DOWN
TYPE
ENABLED
BY
ACTIVATION
TIME
RESUMED
BY
DISABLED
BY
ACTIVATED BY
Rising WR edge
Rising WR edge
REACTIVATION TIME
Deep
Nap
DP = ‘1’
N = ‘1’
2µs
DP = ‘0’
N = ‘0’
1µs
DP = ‘0’
N = ‘0’
200ns
6 clocks
Each end of
conversion
Auto-nap
AN = ‘1’
200ns
CONVST pulse
6 clocks
AN = ‘0’
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ADS7865
SBAS441–OCTOBER 2008.............................................................................................................................................................................................. www.ti.com
ADS7862 COMPATIBILITY
•
An additional external buffer between the resistor
divider and the required 470nF (minimum)
capacitor on the REFIN input.
The ADS7865IPBS is pin-compatible with the
ADS7862Y. However, there are some differences
between the two devices that must be considered
when migrating from the ADS7862 to the ADS7865 in
an existing design.
In the latter case, while the capacitor stabilizes the
reference voltage during the entire conversion, the
buffer must recharge it by providing an average
current only; thus, the required minimum bandwidth of
the buffer can be calculated using Equation 2:
ln(2) ´ 2
WR versus A0
One of the differences is that pin 22, which triggers
writing to the internal Configuration Register of the
ADS7865 (WR), is used to select the input channel
on the ADS7862 (A0).
f
=
-3dB
2p ´ 16 ´ tCLK
(2)
The buffer must also be capable of driving the 470nF
load while maintaining its stability.
Channel selection on the ADS7865 can only be
performed by setting bits C[1:0] in the Configuration
Register or, automatically, by the sequencer (see the
Sequencer Register section for details).
Timing
The only timing requirement that may cause the
ADS7865
to
malfunction
in
an
existing
ADS7862-based design is the CONVST low time (t1)
which is specified to be 20ns minimum, while the
ADS7862 works properly with a pulse as short as
15ns. All other required minimum setup and hold
times are specified to be either the same as or lower
than the ADS7865; therefore, there are no conflicts
with the ADS7862 requirements.
REFIN
The ADS7865 offers an unbuffered REFIN input with a
code-dependent input impedance while featuring a
programmable and buffered reference output
(REFOUT). The ADS7862 offers a high-impedance
(buffered)
reference
input.
If
an
existing
ADS7862-based design uses the internal reference of
the device and relies on an external resistor divider to
adjust the input voltage range of the ADC, migration
to the ADS7865 platform requires one of the following
conditions:
•
A software change to set up the internal reference
DAC properly via the DAC register while removing
the external resistors; or
22
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Product Folder Link(s): ADS7865
ADS7865
www.ti.com.............................................................................................................................................................................................. SBAS441–OCTOBER 2008
ln(2) ´ (n + 1)
APPLICATION INFORMATION
fFILTER
=
2 ´ p ´ 2 ´ R ´ C
(3)
The absolute minimum configuration of the ADS7865
in an application is shown in Figure 36. In this case,
the ADS7865 is used in dual-channel mode only, with
the default settings of the device after power up.
It is recommended to use a capacitor value of at least
20pF.
Keep the acquisition time in mind; the resistor value
can be calculated as shown in Equation 4 for each of
the series resistors (with n = 12, the resolution of the
ADS7865).
The input signal for the amplifiers must fulfill the
common-mode voltage requirements of the ADS7865
in this configuration. The actual values of the
resistors and capacitors depend on the bandwidth
and performance requirements of the application.
tACQ
R =
ln(2) ´ (n + 1) ´ 2 ´ C
(4)
Those values can be calculated using Equation 3,
with n = 12 being the resolution of the ADS7865.
BVDD
1mF
0.1mF
ADS7865
AVDD
BGND
CHB1+
CHB1-
CHB0+
CHB0-
CHA1+
CHA1-
CHA0+
CHA0-
REFIN
BVDD
DB[11:0]
BUSY
BGND
OPA2365
AGND
CLOCK
Controller
Device
WR
RD
CONVST
CS
AGND
OPA2365
BGND
BVDD
SDI
M0
AGND
AVDD
REFOUT
AGND
M1
470nF
(min)
AVDD
OPA2365
0.1mF (min)
1mF
AGND
OPA2365
AGND
Figure 36. Minimum ADS7865 Configuration
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ADS7865
SBAS441–OCTOBER 2008.............................................................................................................................................................................................. www.ti.com
LAYOUT
instance of a separated analog ground area, ensure a
low-impedance connection between the analog and
digital ground of the ADC by placing a bridge
underneath (or next to) the ADC. Otherwise, even
short undershoots on the digital interface with a value
lower than –300mV may lead to conduction of ESD
diodes, causing current flow through the substrate
and degrading the analog performance.
For optimum performance, care should be taken with
the physical layout of the ADS7865 circuitry. This
caution is particularly true if the CLOCK input
approaches the maximum throughput rate. In this
case, it is recommended to have a fixed phase
relationship between CLOCK and CONVST.
Additionally, the basic SAR architecture is quite
sensitive to glitches or sudden changes on the power
supply, reference, ground connections, and digital
inputs that occur just before latching the output of the
analog comparator. Therefore, when driving any
single conversion for an n-bit SAR converter, there
are n windows in which large external transient
voltages can affect the conversion result. Such
glitches might originate from switching power
supplies, nearby digital logic, or high-power devices.
The degree of error in the digital output depends on
the reference voltage, layout, and the exact timing of
the external event. These errors can change if the
external event also changes in time with respect to
the CLOCK input.
During the PCB layout process, care should also be
taken to avoid any return currents crossing any
sensitive analog areas or signals. No signal must
exceed the limit of –300mV with regard to the
respective ground plane. Figure 37 illustrates the
recommended layout of the ground and power-supply
connections.
Supply
The ADS7865 has two separate supplies: the BVDD
pin for the digital interface and the AVDD pin for all
remaining circuits.
BVDD can range from 2.7V to 5.5V, allowing the
ADS7865 to easily interface with processors and
controllers. To limit the injection of noise energy from
external digital circuitry, BVDD should be filtered
properly. Bypass capacitors of 0.1µF and 10µF
should be placed between the BVDD pin and the
ground plane.
With this possibility in mind, power to the ADS7865
should be clean and well-bypassed. A 0.1µF ceramic
bypass capacitor should be placed as close to the
device as possible. In addition, a 1µF to 10µF
capacitor is recommended. If needed, an even larger
capacitor and a 5Ω or 10Ω series resistor may be
used to low-pass filter a noisy supply.
AVDD supplies the internal analog circuitry. For
optimum performance,
a
linear regulator (for
If the reference voltage is external and originates
from an operational amplifier, be sure that it can drive
the reference capacitor without oscillation. The
connection between the output of the external
reference driver and REFIN should be of low
example, the UA7805 family) is recommended to
generate the analog supply voltage in the range of
2.7V to 5.5V for the ADS7865 and the necessary
analog front-end circuitry.
Bypass capacitors should be connected to the ground
plane such that the current is allowed to flow through
the pad of the capacitor (that is, the vias should be
placed on the opposite side of the connection
between the capacitor and the power-supply pin of
the ADC).
resistance
(10Ω
max)
to
minimize
any
code-dependent voltage drop on this path.
Grounding
All ground (AGND and BGND) pins should be
connected to a clean ground reference. These
connections should be kept as short as possible to
minimize the inductance of these paths. It is
recommended to use vias connecting the pads
directly to the ground plane. In designs without
ground planes, the ground trace should be kept as
wide as possible. Avoid connections that are too near
the grounding point of a microcontroller or digital
signal processor.
Digital Interface
To further optimize device performance, a series
resistor of 10Ω to 100Ω can be used on each digital
pin of the ADS7865. In this way, the slew rates of the
input and output signals are reduced, limiting the
noise injection from the digital interface.
Depending on the circuit density of the board,
placement of the analog and digital components, and
the related current loops, a single solid ground plane
for the entire printed circuit board (PCB) or a
dedicated analog ground area may be used. In an
24
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ADS7865
www.ti.com.............................................................................................................................................................................................. SBAS441–OCTOBER 2008
Top View
ADS7865I
32
31
30
29
28
27
26
25
REFIN
BVDD
BGND
22
470
nF
REFOUT
0.1
1
AGND
mF mF
to
1.0
mF
0.1
AVDD
21
BVDD
mF
to
5
6
7
8
20
AVDD
19
18
17
9
10
11
12
13
14
15
16
LEGEND
TOP layer; copper pour and traces
lower layer; AGND area
lower layer; BGND area
via
Figure 37. Optimized Layout Recommendation
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
TQFP
TQFP
Drawing
ADS7865IBPBSR
ADS7865IPBS
PREVIEW
ACTIVE
PBS
32
32
1000
TBD
Call TI
Call TI
PBS
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
ADS7865IPBSG4
ADS7865IPBSR
ACTIVE
ACTIVE
ACTIVE
TQFP
TQFP
TQFP
PBS
PBS
PBS
32
32
32
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
ADS7865IPBSRG4
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
ADS7865IPBSR
TQFP
PBS
32
1000
330.0
16.4
7.2
7.2
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Nov-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TQFP PBS 32
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 33.0
ADS7865IPBSR
1000
Pack Materials-Page 2
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