ADS7961SRHBT [TI]
12/10/8-Bit, 1 MSPS, 16/12/8/4-Channel, Single-Ended, MicroPower, Serial Interface ADCs; 12月10日/ 8-位， 1 MSPS的16 /12/ 8/4通道，单端，微功耗，串行接口的ADC
| 型号： | ADS7961SRHBT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12/10/8-Bit, 1 MSPS, 16/12/8/4-Channel, Single-Ended, MicroPower, Serial Interface ADCs |
| 文件： | 总65页 (文件大小：1898K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
12/10/8-Bit, 1 MSPS, 16/12/8/4-Channel, Single-Ended, MicroPower, Serial Interface ADCs
Check for Samples: ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955, ADS7956, ADS7957, ADS7958, ADS7959,
ADS7960, ADS7961
1
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
1-MHz Sample Rate Serial Devices
Product Family of 12/10/8-Bit Resolution
Zero Latency
The ADS79XX is
analog-to-digital converter family. The following table
shows all twelve devices from this product family.
a
12/10/8-bit multichannel
The devices include a capacitor based SAR A/D
converter with inherent sample and hold.
20-MHz Serial Interface
Analog Supply Range: 2.7 to 5.25V
I/O Supply Range: 1.7 to 5.25V
The devices accept a wide analog supply range from
2.7V to 5.25V. Very low power consumption makes
these devices suitable for battery-powered and
isolated power supply applications.
Two SW Selectable Unipolar, Input Ranges: 0
to 2.5V and 0 to 5V
•
•
Auto and Manual Modes for Channel Selection
A wide 1.7V to 5.25V I/O supply range facilitates a
glue-less interface with the most commonly used
CMOS digital hosts.
12,8,4-Channel Devices can Share 16 Channel
Device Footprint
•
•
Two Programmable Alarm Levels per Channel
The serial interface is controlled by CS and SCLK for
easy connection with microprocessors and DSP.
Four Individually Configurable GPIOs for
TSSOP package devices. One GPIO for QFN
devices
The input signal is sampled with the falling edge of
CS. It uses SCLK for conversion, serial data output,
and reading serial data in. The devices allow auto
sequencing of preselected channels or manual
selection of a channel for the next conversion cycle.
•
Typical Power Dissipation: 14.5 mW (+VA = 5V,
+VBD = 3V) at 1 MSPS
•
•
•
Power-Down Current (1 mA)
Input Bandwidth (47 MHz at 3dB)
There are two software selectable input ranges (0V -
2.5V and 0V - 5V), four individually configurable
GPIOs ( in case of TSSOP package devices), and
two programmable alarm thresholds per channel.
These features make the devices suitable for most
data acquisition applications.
38-,30-Pin TSSOP and 32-,24-Pin QFN
Packages
APPLICATIONS
•
•
•
•
•
•
•
PLC / IPC
The devices offer an attractive power-down feature.
This is extremely useful for power saving when the
device is operated at lower conversion speeds.
Battery Powered Systems
Medical Instrumentation
Digital Power Supplies
Touch Screen Controllers
High-Speed Data Acquisition Systems
High-Speed Closed-Loop Systems
The 16/12-channel devices from this family are
available in a 38-pin TSSOP and 32 pin QFN
package and the 4/8-channel devices are available in
a 30-pin TSSOP and 24 pin QFN packages.
MICROPOWER MULTI-CHANNEL ADS79XX FAMILY
RESOLUTION
NUMBER OF
CHANNELS
12 BIT
10 BIT
8 BIT
16
12
8
ADS7953
ADS7952
ADS7951
ADS7950
ADS7957
ADS7956
ADS7955
ADS7954
ADS7961
ADS7960
ADS7959
ADS7958
4
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2010, Texas Instruments Incorporated
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ADS79XX BLOCK DIAGRAM
MXO AINP
REF
+VA
AGND
Ch0
Ch1
Ch2
ADC
SDO
Compare
Alarm
Threshold
Control Logic
&
SDI
Ch n*
SCLK
Sequencing
CS
GPIO
BDGND
VBD
NOTE: n* is number of channels (16,12,8, or 4) depending on the device from the ADS79XX product family.
NOTE: 4 number of GPIO are available in TSSOP package devices only, QFN package devices offer only one GPIO.
2
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
ORDERING INFORMATION - 12-BIT
MAXIMUM
INTEGRAL
LINEARITY
(LSB)
MAXIMUM
DIFFERENTIAL
LINEARITY
(LSB)
NO MISSING
CODES AT
RESOLUTION
(BIT)
TRANSPORT
MEDIA
PACKAGE
TYPE
NUMBER OF
CHANNELS
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
ORDERING
INFORMATION
MODEL
QTY
ADS7953SBDBT
ADS7953SBDBTR
ADS7953SBRHBT
ADS7953SBRHBR
ADS7952SBDBT
ADS7952SBDBTR
ADS7952SBRHBT
ADS7952SBRHBR
ADS7951SBDBT
ADS7951SBDBTR
ADS7951SBRGET
ADS7951SBRGER
ADS7950SBDBT
ADS7950SBDBTR
ADS7950SBRGET
ADS7950SBRGER
ADS7953SDBT
Tube, 50
Reel, 2000
Tube, 250
Reel, 3000
Tube, 50
38 pin TSSOP
32 pin QFN
DBT
RHB
DBT
RHB
DBT
RGE
DBT
RGE
DBT
RHB
DBT
RHB
DBT
RGE
DBT
RGE
ADS7953 SB
16
12
8
38 pin TSSOP
32 pin QFN
Reel, 2000
Tube, 250
Reel, 3000
Tube, 50
ADS7952 SB
ADS7951 SB
ADS7950 SB
ADS7953 S
ADS7952 S
ADS7951S
±1
±1
12
–40°C to 125°C
30 pin TSSOP
24 pin QFN
Reel, 2000
Tube, 250
Reel, 3000
Tube, 50
30 pin TSSOP
24 pin QFN
Reel, 2000
Tube, 250
Reel, 3000
Tube, 50
4
38 pin TSSOP
32 pin QFN
ADS7953SDBTR
ADS7953SRHBT
ADS7953SRHBR
ADS7952SDBT
Reel, 2000
Tube, 250
Reel, 3000
Tube, 50
16
12
8
38 pin TSSOP
32 pin QFN
ADS7952SDBTR
ADS7952SRHBT
ADS7952SRHBR
ADS7951SDBT
Reel, 2000
Tube, 250
Reel, 3000
Tube, 50
±1.5
±2
11
–40°C to 125°C
30 pin TSSOP
24 pin QFN
ADS7951SDBTR
ADS7951SRGET
ADS7951SRGER
ADS7950SDBT
Reel, 2000
Tube, 250
Reel, 3000
Tube, 50
30 pin TSSOP
24 pin QFN
ADS7950SDBTR
ADS7950SRGET
ADS7950SRGER
Reel, 2000
Tube, 250
Reel, 3000
ADS7950 S
4
ORDERING INFORMATION - 10-BIT
MAXIMUM
INTEGRAL DIFFERENTIAL
LINEARITY
(LSB)
MAXIMUM
NO MISSING
NUMBER
OF
CHANNELS
TRANSPORT
MEDIA
PACKAGE
TYPE
CODES AT
RESOLUTION
(BIT)
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
ORDERING
INFORMATION
MODEL
LINEARITY
(LSB)
QTY
ADS7957SDBT
ADS7957SDBTR
ADS7957SRHBT
ADS7957SRHBR
ADS7956SDBT
ADS7956SDBTR
ADS7956SRHBT
ADS7956SRHBR
ADS7955SDBT
ADS7955SDBTR
ADS7955SRGET
ADS7955SRGER
ADS7954SDBT
ADS7954SDBTR
ADS7954SRGET
ADS7954SRGER
Tube, 50
Reel, 2000
Tube, 250
Reel, 3000
Tube, 50
38 pin TSSOP
32 pin QFN
DBT
RHB
DBT
RHB
DBT
RGE
DBT
RGE
ADS7957 S
16
12
8
38 pin TSSOP
32 pin QFN
Reel, 2000
Tube, 250
Reel, 3000
Tube, 50
ADS7956 S
ADS7955 S
ADS7954 S
±0.5
±0.5
10
–40°C to 125°C
30 pin TSSOP
24 pin QFN
Reel, 2000
Tube, 250
Reel, 3000
Tube, 50
30 pin TSSOP
24 pin QFN
Reel, 2000
Tube, 250
Reel, 3000
4
Copyright © 2008–2010, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
ORDERING INFORMATION - 8-BIT
MAXIMUM
INTEGRAL DIFFERENTIAL
LINEARITY
(LSB)
MAXIMUM
NO MISSING
TRANSPORT
MEDIA
PACKAGE
TYPE
CODES AT
RESOLUTION
(BIT)
NUMBER OF
CHANNELS
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
ORDERING
INFORMATION
MODEL
LINEARITY
(LSB)
QTY
ADS7961SDBT
ADS7961SDBTR
ADS7961SRHBT
ADS7961SRHBR
ADS7960SDBT
ADS7960SDBTR
ADS7960SRHBT
ADS7960SRHBR
ADS7959SDBT
ADS7959SDBTR
ADS7959SRGET
ADS7959SRGER
ADS7958SDBT
ADS7958SDBTR
ADS7958SRGET
ADS7958SRGER
Tube, 50
Reel, 2000
Tube, 250
Reel, 3000
Tube, 50
38 pin TSSOP
32 pin QFN
DBT
RHB
DBT
RHB
DBT
RGE
DBT
RGE
ADS7961 S
16
12
8
38 pin TSSOP
32 pin QFN
Reel, 2000
Tube, 250
Reel, 3000
Tube, 50
ADS7960 S
ADS7959 S
ADS7958 S
±0.3
±0.3
8
–40°C to 125°C
30 pin TSSOP
24 pin QFN
Reel, 2000
Tube, 250
Reel, 3000
Tube, 50
30 pin TSSOP
24 pin QFN
Reel, 2000
Tube, 250
Reel, 3000
4
ABSOLUTE MAXIMUM RATINGS(1)
VALUE
UNIT
V
AINP or CHn to AGND
–0.3 to +VA +0.3
–0.3 to +7.0
–0.3 to (7.0)
–0.3 to (+VA + 0.3)
–40 to 125
–65 to 150
150
+VA to AGND, +VBD to BDGND
Digital input voltage to BDGND
Digital output to BDGND
V
V
V
Operating temperature range
Storage temperature range
°C
°C
°C
Junction temperature (TJ Max)
Power dissipation
(TJ Max–TA)/qJA
100.6
qJA thermal impedance, DBT Package
qJA thermal impedance, RHB Package
qJA thermal impedance, RGE Package
°C/W
°C/W
°C/W
34
38
DBT packaged versions of ADS79XX family devices are rated for MSL2 260°C per
the JSTD-020 specifications and the RGE and RHB packaged versions of ADS79XX
family devices are rated for MSL3 260C per JSTD-020 specifications
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
4
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
ELECTRICAL CHARACTERISTICS, ADS7950/51/52/53
+VA = 2.7 V to 5.25 V, +VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA = -40°C to 125°C, fsample = 1 MHz (unless otherwise
noted)
PARAMETER
ANALOG INPUT
TEST CONDITIONS
MIN
TYP
MAX UNIT
Range 1
0
0
Vref
V
Full-scale input span(1)
Range 2 while 2Vref ≤ +VA
2*Vref
–0.20
VREF
+0.20
Range 1
Absolute input range
V
–0.20
2*VREF
+0.20
Range 2 while 2Vref ≤ +VA
Input capacitance
Input leakage current
SYSTEM PERFORMANCE
Resolution
15
61
rF
TA = 125°C
nA
12
Bits
Bits
(2)
ADS795XSB
12
11
No missing codes
Integral linearity
ADS795XS(2)
ADS795XSB(2)
ADS795XS(2)
ADS795XSB(2)
ADS795XS(2)
–1
±0.5
±0.75
±0.5
±0.75
±1.1
±0.2
±0.2
±2
1
LSB(3)
1.5
–1.5
–1
1
Differential linearity
Offset error(4)
Gain error
LSB
1.5
–2
–3.5
–2
3.5
2
LSB
LSB
LSB
Range 1
Range 2
Total unadjusted error (TUE)
SAMPLING DYNAMICS
Conversion time
20 MHz sclk
20 MHz sclk
800 nSec
nSec
Acquisition time
325
Maximum throughput rate
Aperture delay
1.0
MHz
nsec
nsec
nsec
5
150
150
Step response
Over voltage recovery
DYNAMIC CHARACTERISTICS
Total harmonic distortion(5)
Signal-to-noise ratio
100 kHz
–82
71.7
71.7
71.3
71.3
84
dB
dB
100 kHz, ADS795XSB(2)
100 kHz, ADS795XS(2)
100 kHz, ADS795XSB(2)
100 kHz, ADS795XS(2)
100 kHz
70
70
69
68
Signal-to-noise + distortion
dB
Spurious free dynamic range
Small signal bandwidth
dB
At –3 dB
47
MHz
Any off-channel with 100kHz, Full-scale input to
channel being sampled with DC input (isolation
crosstalk).
–95
–85
Channel-to-channel crosstalk
dB
From previously sampled to channel with 100kHz,
Full-scale input to channel being sampled with DC
input (memory crosstalk).
EXTERNAL REFERENCE INPUT
(1) Ideal input span; does not include gain or offset error.
(2) ADS795X, where X indicates 0, 1, 2, or 3
(3) LSB means Least Significant Bit.
(4) Measured relative to an ideal full-scale input
(5) Calculated on the first nine harmonics of the input frequency.
Copyright © 2008–2010, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
ELECTRICAL CHARACTERISTICS, ADS7950/51/52/53 (continued)
+VA = 2.7 V to 5.25 V, +VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA = -40°C to 125°C, fsample = 1 MHz (unless otherwise
noted)
PARAMETER
Vref reference voltage at REFP(6)
Reference resistance
ALARM SETTING
Higher threshold range
Lower threshold range
DIGITAL INPUT/OUTPUT
Logic family
TEST CONDITIONS
MIN
TYP
2.5
MAX UNIT
2.0
3.0
V
100
kΩ
0
0
FFC
FFC
Hex
Hex
CMOS
VIH
0.7*(+VBD)
VIL
+VBD = 5 V
+VBD = 3 V
0.8
0.4
Logic level
VIL
V
VOH
VOL
At Isource = 200 mA
At Isink = 200 mA
Vdd-0.2
0.4
Data format MSB first
MSB First
POWER SUPPLY REQUIREMENTS
+VA supply voltage
2.7
1.7
3.3
3.3
1.8
1.05
2.3
1.1
1
5.25
5.25
V
V
+VBD supply voltage
At +VA = 2.7 to 3.6 V and 1MHz throughput
At +VA = 2.7 to 3.6 V static state
mA
mA
mA
mA
mA
Supply current (normal mode)
At +VA = 4.7 to 5.25 V and 1 MHz throughput
At +VA = 4.7 to 5.25 V static state
3
1.5
Power-down state supply current
+VBD supply current
Power-up time
+VA = 5.25V, fs = 1MHz
1
mA
mSec
1
1
Invalid conversions after power up or
reset
Number
s
TEMPERATURE RANGE
Specified performance
–40
125
°C
(6) Device is designed to operate over Vref = 2.0 V to 3.0 V. However one can expect lower noise performance at Vref < 2.4 V. This is due to
SNR degradation resulting from lowered signal range.
ELECTRICAL CHARACTERISTICS, ADS7954/55/56/57
+VA = 2.7 V to 5.25 V, +VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA = -40°C to 125°C, fsample = 1 MHz (unless otherwise
noted)
PARAMETER
ANALOG INPUT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Range 1
0
0
Vref
Full-scale input span(1)
V
Range 2 while 2Vref ≤ +VA
2*Vref
VREF
+0.20
Range 1
–0.20
–0.20
Absolute input range
V
2*VREF
+0.20
Range 2 while 2Vref ≤ +VA
Input capacitance
Input leakage current
SYSTEM PERFORMANCE
Resolution
15
61
rF
TA = 125°C
nA
10
Bits
Bits
No missing codes
10
(1) Ideal input span; does not include gain or offset error.
Submit Documentation Feedback
6
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
ELECTRICAL CHARACTERISTICS, ADS7954/55/56/57 (continued)
+VA = 2.7 V to 5.25 V, +VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA = -40°C to 125°C, fsample = 1 MHz (unless otherwise
noted)
PARAMETER
Integral linearity
TEST CONDITIONS
MIN
–0.5
–0.5
–1.5
–1
TYP
±0.2
±0.2
±0.5
±0.1
±0.1
MAX
0.5 LSB(2)
UNIT
Differential linearity
Offset error(3)
0.5
1.5
1
LSB
LSB
Range 1
Range 2
Gain error
LSB
SAMPLING DYNAMICS
Conversion time
20 MHz SCLK
20 MHz SCLK
800
1.0
nSec
nSec
MHz
nsec
nsec
nsec
Acquisition time
325
Maximum throughput rate
Aperture delay
5
150
150
Step response
Over voltage recovery
DYNAMIC CHARACTERISTICS
Total harmonic distortion(4)
Signal-to-noise ratio
100 kHz
100 kHz
100 kHz
100 kHz
At –3 dB
–80
dB
dB
60
60
Signal-to-noise + distortion
Spurious free dynamic range
Full power bandwidth
82
47
dB
MHz
Any off-channel with 100kHz, Full-scale input to
channel being sampled with DC input.
–95
Channel-to-channel crosstalk
dB
From previously sampled to channel with 100kHz,
Full-scale input to channel being sampled with DC
input.
–85
EXTERNAL REFERENCE INPUT
Vref reference voltage at REFP
Reference resistance
ALARM SETTING
Higher threshold range
Lower threshold range
DIGITAL INPUT/OUTPUT
Logic family
2.0
2.5
3.0
V
100
kΩ
000
000
FFC
FFC
Hex
Hex
CMOS
VIH
0.7*(+VBD)
VIL
+VBD = 5 V
0.8
0.4
Logic level
VIL
+VBD = 3 V
V
VOH
VOL
At Isource = 200 mA
At Isink = 200 mA
Vdd-0.2
0.4
Data format MSB first
MSB First
POWER SUPPLY REQUIREMENTS
+VA supply voltage
2.7
1.7
3.3
3.3
5.25
5.25
V
+VBD supply voltage
V
At +VA = 2.7 to 3.6 V and 1MHz throughput
At +VA = 2.7 to 3.6 V static state
1.8
mA
mA
mA
mA
1.05
2.3
1
3
Supply current (normal mode)
At +VA = 4.7 to 5.25 V and 1 MHz throughput
At +VA = 4.7 to 5.25 V static state
1.1
1.5
(2) LSB means Least Significant Bit.
(3) Measured relative to an ideal full-scale input
(4) Calculated on the first nine harmonics of the input frequency.
Copyright © 2008–2010, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
ELECTRICAL CHARACTERISTICS, ADS7954/55/56/57 (continued)
+VA = 2.7 V to 5.25 V, +VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA = -40°C to 125°C, fsample = 1 MHz (unless otherwise
noted)
PARAMETER
Power-down state supply current
+VBD supply current
TEST CONDITIONS
MIN
TYP
1
MAX
UNIT
mA
+VA = 5.25V, fs = 1MHz
1
mA
Power-up time
1
1
mSec
Numbers
Invalid conversions after power up or
reset
TEMPERATURE RANGE
Specified performance
–40
125
°C
ELECTRICAL CHARACTERISTICS, ADS7958/59/60/61
+VA = 2.7 V to 5.25 V, +VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA = -40°C to 125°C, fsample = 1 MHz (unless otherwise
noted)
PARAMETER
ANALOG INPUT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Range 1
0
0
Vref
Full-scale input span(1)
V
Range 2 while 2Vref ≤ +VA
2*Vref
VREF
+0.20
Range 1
–0.20
–0.20
Absolute input range
V
2*VREF
+0.20
Range 2 while 2Vref ≤ +VA
Input capacitance
Input leakage current
SYSTEM PERFORMANCE
Resolution
15
61
rF
TA = 125°C
nA
8
Bits
Bits
0.3 LSB(2)
No missing codes
Integral linearity
8
–0.3
–0.3
–0.5
–0.6
±0.1
±0.1
±0.2
±0.1
±0.1
Differential linearity
Offset error(3)
0.3
0.5
0.6
LSB
LSB
Range 1
Range 2
Gain error
LSB
SAMPLING DYNAMICS
Conversion time
20 MHz SCLK
20 MHz SCLK
800
1.0
nSec
nSec
MHz
nsec
nsec
nsec
Acquisition time
325
Maximum throughput rate
Aperture delay
5
150
150
Step response
Over voltage recovery
DYNAMIC CHARACTERISTICS
Total harmonic distortion(4)
Signal-to-noise ratio
100 kHz
100 kHz
100 kHz
100 kHz
At –3 dB
–75
dB
dB
49
49
Signal-to-noise + distortion
Spurious free dynamic range
Full power bandwidth
–78
47
dB
MHz
(1) Ideal input span; does not include gain or offset error.
(2) LSB means Least Significant Bit.
(3) Measured relative to an ideal full-scale input
(4) Calculated on the first nine harmonics of the input frequency.
8
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
ELECTRICAL CHARACTERISTICS, ADS7958/59/60/61 (continued)
+VA = 2.7 V to 5.25 V, +VBD = 1.7 V to 5.25 V, Vref = 2.5 V ± 0.1 V, TA = -40°C to 125°C, fsample = 1 MHz (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Any off-channel with 100kHz, Full-scale input to
channel being sampled with DC input.
–95
Channel-to-channel crosstalk
dB
From previously sampled to channel with 100kHz,
Full-scale input to channel being sampled with DC
input.
–85
ETERNAL REFERENCE INPUT
Vref reference voltage at REFP
Reference resistance
ALARM SETTING
Higher threshold range
Lower threshold range
DIGITAL INPUT/OUTPUT
Logic family
2.0
2.5
3.0
V
100
kΩ
000
000
FF
FF
Hex
Hex
CMOS
VIH
0.7*(+VBD)
VIL
+VBD = 5 V
0.8
0.4
Logic level
VIL
+VBD = 3 V
V
VOH
VOL
At Isource = 200 mA
At Isink = 200 mA
Vdd-0.2
0.4
Data format
MSB First
POWER SUPPLY REQUIREMENTS
+VA supply voltage
2.7
3.3
3.3
1.8
1.05
2.3
1.1
1
5.25
5.25
V
V
+VBD supply voltage
1.7
At +VA = 2.7 to 3.6 V and 1MHz throughput
At +VA = 2.7 to 3.6 V static state
mA
mA
Supply current (normal mode)
At +VA = 4.7 to 5.25 V and 1 MHz throughput
At +VA = 4.7 to 5.25 V static state
3
mA
1.5
mA
Power-down state supply current
+VBD supply current
Power-up time
mA
+VA = 5.25V, fs = 1MHz
1
mA
1
1
mSec
Numbers
Invalid conversions after power up or
reset
TEMPERATURE RANGE
Specified performance
–40
125
°C
TIMING REQUIREMENTS (see Figure 45, Figure 46, Figure 47, and Figure 48)
All specifications typical at –40°C to 125°C, +VA = 2.7 V to 5.25 V (unless otherwise specified)
PARAMETER
TEST CONDITIONS(1) (2)
+VBD = 1.8 V
+VBD = 3 V
MIN
TYP
MAX
16
UNIT
tconv
Conversion time
16
SCLK
+VBD = 5 V
16
+VBD = 1.8 V
+VBD = 3 V
40
40
40
Minimum quiet sampling time needed from bus
3-state to start of next conversion
tq
ns
+VBD = 5 V
(1) 1.8V specifications apply from 1.7V to 1.9V, 3V specifications apply from 2.7V to 3.6V, 5V specifications apply from 4.75V to 5.25V.
(2) With 50-pF load
Copyright © 2008–2010, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
TIMING REQUIREMENTS (see Figure 45, Figure 46, Figure 47, and Figure 48) (continued)
All specifications typical at –40°C to 125°C, +VA = 2.7 V to 5.25 V (unless otherwise specified)
PARAMETER
TEST CONDITIONS(1) (2)
+VBD = 1.8 V
+VBD = 3 V
+VBD = 5 V
+VBD = 1.8 V
+VBD = 3 V
+VBD = 5 V
+VBD = 1.8 V
+VBD = 3 V
+VBD = 5 V
+VBD = 1.8 V
+VBD = 3 V
+VBD = 5 V
+VBD = 1.8 V
+VBD = 3 V
+VBD = 5 V
+VBD = 1.8 V
+VBD = 3 V
+VBD = 5 V
+VBD = 1.8 V
+VBD = 3 V
+VBD = 5 V
+VBD = 1.8 V
+VBD = 3 V
+VBD = 5 V
+VBD = 1.8 V
+VBD = 3 V
+VBD = 5 V
+VBD = 1.8 V
+VBD = 3 V
+VBD = 5 V
+VBD = 1.8 V
+VBD = 3 V
+VBD = 5 V
+VBD = 1.8 V
+VBD = 3 V
+VBD = 5 V
MIN
TYP
MAX
38
UNIT
td1
tsu1
td2
th1
td3
tsu2
th2
tw1
td4
twh
twl
Delay time, CS low to first data (DO–15) out
27
ns
17
8
6
4
Setup time, CS low to first rising edge of SCLK
Delay time, SCLK falling to SDO next data bit valid
Hold time, SCLK falling to SDO data bit valid
Delay time, 16th SCLK falling edge to SDO 3-state
Setup time, SDI valid to rising edge of SCLK
Hold time, rising edge of SCLK to SDI valid
Pulse duration CS high
ns
ns
35
27
17
7
5
3
ns
26
22
13
ns
2
3
ns
4
12
10
6
ns
20
20
20
ns
24
21
12
Delay time CS high to SDO 3-state
Pulse duration SCLK high
ns
20
20
20
20
20
20
ns
Pulse duration SCLK low
ns
20
20
20
Frequency SCLK
MHz
10
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
DEVICE INFORMATION
PIN CONFIGURATION (TOP VIEW)
1
30
29
GPIO2
GPIO1
GPIO0
1
30
29
GPIO2
GPIO3
GPIO1
GPIO0
2
GPIO3
2
REFM
REFP
3
28 +VBD
3
28 +VBD
REFM
REFP
4
27
26
25
BDGND
SDO
4
27
26
25
BDGND
SDO
5
+VA
AGND
MXO
+VA
AGND
MXO
5
6
SDI
6
SDI
7
24 SCLK
7
24 SCLK
AINP
AINM
8
ADS7950 23 CS
AINP
8
ADS7951 23 CS
ADS7954
ADS7958
ADS7955
9
22
21
20
19
AGND
+VA
9
22
21
20
19
AINM
AGND
+VA
ADS7959
10
AGND
10
AGND
NC 11
CH3 12
NC 13
CH0
NC
CH7 11
CH6 12
CH5 13
CH4 14
NC 15
CH0
CH1
18 CH1
17 NC
16 NC
18 CH2
17 CH3
16 NC
CH2 14
NC 15
1
38
1
38
GPIO2
GPIO1
GPIO2
GPIO1
2
3
4
5
6
7
8
9
37
36
35
34
33
32
31
30
2
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
GPIO3
REFM
REFP
+VA
GPIO0
+VBD
BDGND
SDO
GPIO3
REFM
REFP
+VA
GPIO0
+VBD
3
4
BDGND
SDO
SDI
5
6
AGND
MXO
AGND
MXO
SDI
7
SCLK
CS
SCLK
CS
8
AINP
AINP
AINM
9
AINM
AGND
NC
AGND
+VA
AGND
10 ADS7953 29
+VA
10
11
12
13
14
15
16
17
18
19
ADS7952
ADS7956
ADS7960
AGND
CH15
CH14
ADS7957
11
12
13
14
15
16
17
18
19
28
27
26
25
24
23
22
21
20
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AGND
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AGND
ADS7961
NC
NC
CH13
CH12
CH11
CH10
CH9
NC
CH11
CH10
CH9
CH8
CH8
AGND
AGND
32
25
24
AGND
SCLK
CS
1
MXO
AINP
AINM
CH15
CH14
CH13
CH12
AGND
ADS7953/
+VA
ADS7957/
ADS7961
CH0
CH1
CH2
17
16
CH3
8
9
Copyright © 2008–2010, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
32
25
24
AGND
MXO
AINP
AINM
NC
SCLK
CS
1
AGND
ADS7952/
ADS7956/
ADS7960
+VA
NC
NC
NC
CH11
CH10
CH0
CH1
17
16
8
9
24
19
18
SDI
+VA
1
SCLK
CS
AGND
MXO
AINP
AINM
CH7
ADS7951/
ADS7955/
ADS7959
AGND
+VA
13
12
6
CH0
7
24
19
18
SDI
+VA
AGND
MXO
AINP
AINM
NC
1
SCLK
CS
ADS7950/
ADS7954/
ADS7958
AGND
+VA
13
12
6
NC
7
TERMINAL FUNCTIONS - TSSOP PACKAGES
DEVICE NAME
ADS7953
ADS7957
ADS7961
ADS7952
ADS7956
ADS7960
ADS7951
ADS7955
ADS7959
ADS7950
ADS7954
ADS7958
PIN NAME
I/O
FUNCTION
PIN NO.
REFERENCE
4
3
4
3
4
3
4
3
REFP
REFM
I
I
Reference input
Reference ground
12
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
TERMINAL FUNCTIONS - TSSOP PACKAGES (continued)
DEVICE NAME
ADS7953
ADS7957
ADS7961
ADS7952
ADS7956
ADS7960
ADS7951
ADS7955
ADS7959
ADS7950
ADS7954
ADS7958
PIN NAME
I/O
FUNCTION
PIN NO.
ADC ANALOG INPUT
8
8
9
8
9
8
9
AINP
AINM
I
I
Signal input to ADC
ADC input ground
9
MULTIPLEXER
7
7
28
27
26
25
24
23
22
21
18
17
16
15
-
7
20
19
18
17
14
13
12
11
-
7
20
18
14
12
-
MXO
Ch0
O
I
Multiplexer output
28
27
26
25
24
23
22
21
18
17
16
15
14
13
12
11
Analog channels for multiplexer
Ch1
I
Ch2
I
Ch3
I
Ch4
I
-
Ch5
I
-
Ch6
I
-
Ch7
I
-
Ch8
I
-
-
Ch9
I
-
-
Ch10
Ch11
Ch12
Ch13
Ch14
Ch15
I
-
-
I
-
-
I
-
-
-
I
-
-
-
I
-
-
-
I
DIGITAL CONTROL SIGNALS
31
32
33
34
31
32
33
34
23
24
25
26
23
24
25
26
CS
SCLK
SDI
I
I
Chip select input
Serial clock input
Serial data input
Serial data output
I
SDO
O
GENERAL PURPOSE INPUTS / OUTPUTS: These pins have programmable dual functionality. Refer to Table 8 for functionality
programming
37
37
29
29
GPIO0
I/O
O
General purpose input or output
High alarm or
High/Low
alarm
Active high output indicating high alarm or high/low
alarm depending on programming
38
1
38
1
30
1
30
1
GPIO1
Low alarm
GPIO2
Range
GPIO3
PD
I/O
O
General purpose input or output
Active high output indicating low alarm
General purpose input or output
I/O
I
Selects range: High -> Range 2 / Low -> Range 1
General purpose input or output
2
2
2
2
I/O
I
Active low power down input
POWER SUPPLY AND GROUND
5, 29
5, 29
5, 21
5, 21
+VA
—
—
Analog power supply
Analog ground
6, 10, 19,
20, 30
6, 10, 19,
20, 30
6, 10, 22
6, 10, 22
AGND
36
35
36
35
28
27
28
27
+VBD
—
—
Digital I/O supply
Digital ground
BDGND
NC PINS
Copyright © 2008–2010, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
TERMINAL FUNCTIONS - TSSOP PACKAGES (continued)
DEVICE NAME
ADS7953
ADS7957
ADS7961
ADS7952
ADS7956
ADS7960
ADS7951
ADS7955
ADS7959
ADS7950
ADS7954
ADS7958
PIN NAME
I/O
FUNCTION
PIN NO.
—
11, 12, 13,
14
15, 16
11, 13, 15,
16, 17, 19
—
—
Pins internally not connected, do not float these pins
TERMINAL FUNCTIONS - QFN PACKAGES
DEVICE NAME
ADS7953
ADS7957
ADS7961
ADS7952
ADS7956
ADS7960
ADS7951
ADS7955
ADS7959
ADS7950
ADS7954
ADS7958
PIN NAME
I/O
FUNCTION
PIN NO.
REFERENCE
31
30
31
30
24
23
24
23
REFP
REFM
I
I
Reference input
Reference ground
ADC ANALOG INPUT
3
3
4
4
5
4
5
AINP
AINM
I
I
Signal input to ADC
ADC input ground
4
MULTIPLEXER
2
2
18
17
16
15
14
13
12
11
10
9
3
13
12
11
10
9
8
7
6
-
3
11
10
9
8
-
MXO
Ch0
O
I
Multiplexer output
20
19
18
17
16
15
14
13
12
11
10
9
Analog-input channels for multiplexer
Ch1
I
Ch2
I
Ch3
I
Ch4
I
-
Ch5
I
-
Ch6
I
-
Ch7
I
-
Ch8
I
-
-
Ch9
I
8
-
-
Ch10
Ch11
Ch12
Ch13
Ch14
Ch15
I
7
-
-
I
8
-
-
-
I
7
-
-
-
I
6
-
-
-
I
5
-
-
-
I
DIGITAL CONTROL SIGNALS
23
24
25
26
23
24
25
26
16
17
18
19
16
17
18
19
CS
SCLK
SDI
I
I
Chip select input
Serial clock input
Serial data input
Serial data output
I
SDO
O
GENERAL PURPOSE INPUT / OUTPUT: This pin has programmable dual functionality. Refer to Table 8 for functionality programming
29
29
22
22
GPIO0
I/O
O
General purpose input or output
High alarm or
High/Low
alarm
Active high output indicating high alarm or high/low
alarm depending on programming
POWER SUPPLY AND GROUND
21, 32 21, 32 1, 14
1, 14
+VA
—
Analog power supply
14
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
TERMINAL FUNCTIONS - QFN PACKAGES (continued)
DEVICE NAME
ADS7953
ADS7957
ADS7961
ADS7952
ADS7956
ADS7960
ADS7951
ADS7955
ADS7959
ADS7950
ADS7954
ADS7958
PIN NAME
I/O
FUNCTION
PIN NO.
1, 22
28
1, 22
28
2, 15
21
2, 15
21
AGND
+VBD
—
—
—
Analog ground
Digital I/O supply
Digital ground
27
27
20
20
BDGND
NC PINS
—
5, 6, 19,
20
—
6, 7, 12, 13
—
—
Pins internally not connected, do not float these pins
Copyright © 2008–2010, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
TYPICAL CHARATERISTICS (all ADS79XX Family Devices)
SUPPLY CURRENT
vs
STATIC SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
3.5
3
1.5
1.4
fS = 1 MSPS,
VDD = 5.5 V
3.4
3.2
fS = 1 MSPS,
TA = 25°C
TA = 25°C
3
1.3
1.2
1.1
1
2.5
2
2.8
2.6
2.4
1.5
1
2.2
2
0.9
-40
15
70
125
2.7
3.4
4.1
4.8
5.5
2.7
3.4
4.1
4.8
5.5
TA - Free-Air Temperature - °C
+VA - Supply Voltage - V
+VA - Supply Voltage - V
Figure 1.
Figure 2.
Figure 3.
STATIC SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
SAMPLE RATE
SAMPLE RATE
1.115
1.11
2.5
2
2.5
2
VDD = 5.5 V
No Powerdown,
TA = 25°C
With Powerdown,
TA = 25°C
5 V
1.105
1.1
5 V
2.7 V
1.5
1
1.5
1
1.095
1.09
1.085
1.08
2.7 V
0.5
0
0.5
0
1.075
1.07
0
100
200
300
400
500
-40
15
70
125
0
200
400
600
800
1000
fS - Sample Rate - KSPS
TA - Free-Air Temperature - °C
fS - Sample Rate - KSPS
Figure 4.
Figure 5.
Figure 6.
16
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
TYPICAL CHARACTERISTICS (12-Bit Devices Only)
Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves
DIFFERENTIAL NONLINEARITY
INTEGRAL NONLINEARITY
vs
DIFFERENTIAL NONLINEARITY
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
1
0.8
0.6
0.4
0.2
1
1
+VA = 5 V,
+VBD = 5 V,
fS = 1 MSPS
fS = 1 MSPS,
TA = 25°C
fS = 1 MSPS,
0.8
0.8
0.6
TA = 25°C
INL max
0.6
0.4
0.2
DNL max
DNL max
0.4
0.2
0
0
0
-0.2
-0.4
-0.2
-0.2
INL min
DNL min
DNL min
-0.4
-0.6
-0.4
-0.6
-0.6
-0.8
-1
-0.8
-1
-0.8
-1
5.5
-40
15
70
125
2.7
3.2
4.2
4.7
+VA - Supply Voltage - V
5.2
2.7
3.2
3.7
4.2
4.7
5.2
3.7
TA - Free-Air Temperature - °C
+VA - Supply Voltage - V
Figure 7.
Figure 8.
Figure 9.
INTEGRAL NONLINEARITY
vs
OFFSET ERROR
vs
OFFSET ERROR
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
INTERFACE SUPPLY VOLTAGE
1
2
2
1.8
1.6
+VA = 5 V,
+VBD = 5 V,
fS = 1 MSPS
+VA = 5.5 V,
fS = 1 MSPS,
+VBD = 1.8 V,
fS = 1 MSPS,
TA = 25°C
0.8
0.6
1.8
1.6
1.4
TA = 25°C
INL max
0.4
0.2
0
1.4
1.2
1.2
1
1
-0.2
-0.4
-0.6
0.8
0.6
0.4
0.2
0
0.8
INL min
0.6
0.4
0.2
0
-0.8
-1
-40
15
70
125
1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.5
2.7
3.4
4.1
4.8
5.5
TA - Free-Air Temperature - °C
+VA - Supply Voltage - V
+VBD - Interace Supply - V
Figure 10.
Figure 11.
Figure 12.
GAIN ERROR
vs
GAIN ERROR
vs
OFFSET ERROR
vs
SUPPLY VOLTAGE
INTERFACE SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
1
1
0.8
0.6
0.4
0.2
2
+VBD = 1.8 V,
fS = 1 MSPS,
+VA = 5.5 V,
fS = 1 MSPS,
TA = 25°C
+VA = 5.5 V,
+VBD = 1.8 V,
fS = 1 MSPS
0.8
1.8
TA = 25°C
0.6
0.4
0.2
1.6
1.4
1.2
1
0
0
-0.2
-0.4
-0.6
-0.2
-0.4
0.8
0.6
-0.6
-0.8
-1
0.4
0.2
0
-0.8
-1
1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.5
2.7
3.4
4.1
4.8
5.5
-40
15
70
125
+VBD - Interace Supply - V
+VA - Supply Voltage - V
TA - Free-Air Temperature - °C
Figure 13.
Figure 14.
Figure 15.
Copyright © 2008–2010, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
TYPICAL CHARACTERISTICS (12-Bit Devices Only) (continued)
Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves
GAIN ERROR
vs
SIGNAL-TO-NOISE RATIO
vs
SIGNAL-TO-NOISE + DISTORTION
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
SUPPLY VOLTAGE
1
0.9
0.8
0.7
0.6
0.5
72
71.5
71
72
71.5
71
+VA = 5.5 V,
+VBD = 1.8 V,
fS = 1 MSPS
70.5
70.5
0.4
0.3
0.2
+VBD = 3 V,
fS = 1 MSPS,
+VBD = 3 V,
70
70
fS = 1 MSPS,
fIN = 100 kHz
TA = 25°C
fIN = 100 kHz
TA = 25°C
69.5
69
69.5
69
0.1
0
2.7
3.4
4.1
4.8
5.5
-40
15 70
TA - Free-Air Temperature - °C
125
2.7
3.4
4.1
4.8
5.5
+VA - Supply Voltage - V
+VA - Supply Voltage - V
Figure 16.
Figure 17.
Figure 18.
TOTAL HARMONIC DISTORTION
SPURIOUS FREE DYNAMIC RANGE
SIGNAL-TO-NOISE RATIO
vs
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
-80
90
72
+VBD = 3 V,
89
-81
-82
fS = 1 MSPS,
71.5
fIN = 100 kHz
88
TA = 25°C
87
-83
-84
-85
71
70.5
70
86
85
84
83
82
81
80
-86
-87
-88
+VBD = 3 V,
fS = 1 MSPS,
+VA = 5 V
+VBD = 3 V,
fS = 1 MSPS,
fIN = 100 kHz
TA = 25°C
69.5
69
-89
-90
fIN = 100 kHz
2.7
3.4
4.1
4.8
5.5
-40
15
70
125
2.7
3.4
4.1
4.8
+VA - Supply Voltage - V
5.5
TA - Free-Air Temperature - °C
+VA - Supply Voltage - V
Figure 19.
Figure 20.
Figure 21.
SIGNAL-TO-NOISE + DISTORTION
vs
TOTAL HARMONIC DISTORTION
vs
SPURIOUS FREE DYNAMIC RANGE
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
72
-80
90
+VA = 5 V
+VBD = 3 V,
fS = 1 MSPS,
+VA = 5 V
89
+VBD = 3 V,
fS = 1 MSPS,
88
-81
71.5
-82
-83
fIN = 100 kHz
fIN = 100 kHz
87
71
-84
-85
86
85
84
83
82
70.5
70
-86
-87
+VA = 5 V
+VBD = 3 V,
fS = 1 MSPS,
-88
-89
-90
69.5
69
81
80
fIN = 100 kHz
-40
15
70
125
-40
15
70
TA - Free-Air Temperature - °C
125
-40
15
70
125
TA - Free-Air Temperature - °C
TA - Free-Air Temperature - °C
Figure 22.
Figure 23.
Figure 24.
18
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
TYPICAL CHARACTERISTICS (12-Bit Devices Only) (continued)
Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves
SIGNAL-TO-NOISE RATIO
vs
SIGNAL-TO-NOISE + DISTORTION
TOTAL HARMONIC DISTORTION
vs
vs
INPUT FREQUENCY
INPUT FREQUENCY
INPUT FREQUENCY
73
72.5
72
73
-70
+VA = 5 V
+VBD = 3 V,
fS = 1 MSPS,
+VA = 5 V
+VBD = 3 V,
fS = 1 MSPS,
-72
-74
72.5
72
TA = 25°C,
TA = 25°C,
-76
-78
-80
-82
-84
MXO Shorted to AINP
MXO Shorted to AINP
71.5
71.5
71
70.5
70
71
70.5
70
+VA = 5 V
+VBD = 3 V,
fS = 1 MSPS,
-86
-88
-90
TA = 25°C,
69.5
69
69.5
69
MXO Shorted to AINP
10
30
50
70
90
110 130 150
10
30
50
70
90
110 130 150
10
30
50
70
90
110 130 150
fIN - Input Frequency - KHz
fIN - Input Frequency - KHz
fIN - Input Frequency - KHz
Figure 25.
Figure 26.
Figure 27.
SIGNAL-TO-NOISE + DISTORTION
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY
(Across Different Source Resistance
Values)
vs
INPUT FREQUENCY
(Across Different Source Resistance
Values)
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY
72
100
-70
+VA = 5 V
+VBD = 5 V,
fS = 1 MSPS,
+VA = 5 V
+VBD = 3 V,
fS = 1 MSPS,
-72
500 W
71.5
71
95
1000 W
-74
TA = 25°C,
TA = 25°C,
Buffer Between MXO and AINP
-76
MXO Shorted to AINP
90
1000 W
-78
500 W
10 W
100 W
85
80
70.5
-80
-82
70
10 W
+VA = 5 V
+VBD = 5 V,
fS = 1 MSPS,
100 W
-84
-86
75
70
69.5
69
TA = 25°C,
-88
-90
Buffer Between MXO and AINP
10
30
50
70
90
110 130 150
20
40 60 80
fIN - Input Frequency - KHz
100
20
40
60
80
100
fIN - Input Frequency - KHz
fIN - Input Frequency - KHz
Figure 28.
Figure 29.
Figure 30.
Copyright © 2008–2010, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
TYPICAL CHARACTERISTICS (12-Bit Devices Only) (continued)
Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY
(Across Different Source Resistance
Values)
DIFFERENTIAL NONLINEARITY
VARIATION ACROSS CHANNELS
INTEGRAL NONLINEARITY VARIATION
ACROSS CHANNELS
1
90
1
+VA = 5 V,
+VBD = 5 V,
fS = 1 MSPS
0.8
0.6
0.4
0.2
0
88
0.8
INL max
DNL max
10 W
100 W
0.6
86
0.4
0.2
84
82
0
80
1000 W
500 W
-0.2
-0.4
-0.6
-0.8
-1
-0.2
78
INL min
DNL min
-0.4
76
74
72
70
+VA = 5 V
+VBD = 5 V,
fS = 1 MSPS,
-0.6
+VA = 5 V,
+VBD = 5 V,
fS = 1 MSPS
TA = 25°C,
-0.8
Buffer Between MXO and AINP
-1
0
5 10
Channel Number
15
0
5 10
Channel Number
15
20
40
60
80
100
fIN - Input Frequency - KHz
Figure 31.
Figure 32.
Figure 33.
OFFSET ERROR VARIATION ACROSS
CHANNELS
GAIN ERROR VARIATION ACROSS
CHANNELS
SIGNAL-TO-NOISE RATIO VARIATION
ACROSS CHANNELS
73
1.6
0.25
+VA = 5 V,
+VBD = 5 V,
+VA = 5 V,
+VBD = 5 V,
fS = 1 MSPS
0.2
1.4
fS = 1 MSPS
1.2
72.5
72
1
0.15
0.1
0.05
0
0.8
71.5
0.6
0.4
0.2
0
71
+VA = 5 V,
+VBD = 5 V,
fS = 1 MSPS
70.5
70
1
2
3
4
5
6
7 9 10 11 12 1314 15 16
Channel Number
8
0
5
10
Channel Number
15
20
0
5
10
Channel Number
15
20
Figure 34.
Figure 35.
Figure 36.
20
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
TYPICAL CHARACTERISTICS (12-Bit Devices Only) (continued)
Variations for 10-bit and 8-bit devices are too small to be illustrated through the characteristic curves
CROSSTALK
vs
INPUT FREQUENCY
INPUT LEAKAGE CURRENT
SIGNAL-TO-NOISE + DISTORTION
VARIATION ACROSS CHANNELS
vs
FREE-AIR TEMPERATURE
120
100
100
90
73
+VA = 5 V,
+VBD = 5 V,
fS = 1 MSPS
+VA = 5 V,
+VBD = 5 V
Isolation
72.5
72
80
70
60
80
60
40
Memory
71.5
71
50
40
VI = 0 V
VI = 1.25 V
30
20
10
0
+VA = 5 V,
+VBD = 5 V,
fS = 1 MSPS,
VI = 2.5 V
20
0
70.5
70
CH0, CH1
1
2
3
4
5
6
7
Channel Number
8
9 10 11 12 1314 15 16
0
50
100
150
200
250
-40 -25 -10
5
20 35 50 65 80 95 110 125
fIN - Input Frequency - KHz
TA - Free-Air Temperature - °C
Figure 37.
Figure 38.
Figure 39.
TOTAL UNADJUSTED ERROR (TUE Max)
25
TOTAL UNADJUSTED ERROR (TUE Min)
25
20
15
10
20
15
10
5
0
5
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
TUE Max - LSB
TUE Min- LSB
Figure 40.
Figure 41.
Copyright © 2008–2010, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
TYPICAL CHARACTERISTICS (12-Bit Devices Only)
DNL
1
+VA = 5 V
+VBD = 5 V,
fS = 1 MSPS,
0.8
0.6
0.4
TA = 25°C
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
1024
2048
3072
4096
Code
Figure 42.
INL
1
0.8
0.6
0.4
0.2
+VA = 5 V,
+VBD = 5 V,
fS = 1 MSPS
0
-0.2
-0.4
-0.6
-0.8
-1
4096
1024
2048
3072
0
Code
Figure 43.
FFT
0
-20
-40
+VA = 5 V
+VBD = 5 V,
fS = 1 MSPS,
fIN = 100 kHz
Npoints = 16384
-60
-80
-100
-120
-140
-160
500000
0
200000
300000
400000
100000
f - Frequency - Hz
Figure 44.
22
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
DETAILED DESCRIPTION
DEVICE OPERATION
The ADS7950 to ADS7961 are 12/10/8-bit multichannel devices. Figure 45, Figure 46, Figure 47, and Figure 48
show device operation timing. Device operation is controlled with CS, SCLK, and SDI. The device outputs its
data on SDO.
Frame n
9
Frame n+1
11
CS
13
1
3
1
3
5
7
11
15 16
5
7
9
13
15 16
SCLK
SDO
Top
4 bit
Top
4 bit
12 bit conversion result
16 bit i/p word
12 bit conversion result
16 bit i/p word
SDI
Mux chan change
Analog i/p settling after Chan change
Mux chan change
MUX
Sampling
instance
Acquisition phase
tacq
Acquisition
Conversion
Conversion phase
tcnv
Conversion phase
GPO
GPI
Data written(thr SDI) in frame n-1
Data written(thr SDI) in frame n
GPI status is latched in on CSfalling
edge and transferred to SDO frame n
Figure 45. Device Operation Timing Diagram
Each frame begins with the falling edge of CS. With the falling edge of CS, the input signal from the selected
channel is sampled, and the conversion process is initiated. The device outputs data while the conversion is in
progress. The 16-bit data word contains a 4-bit channel address, followed by a 12-bit conversion result in MSB
first format. There is an option to read the GPIO status instead of the channel address. (Refer to Table 1,
Table 2, and Table 5 for more details.)
The device selects a new multiplexer channel on the second SCLK falling edge. The acquisition phase starts on
the fourteenth SCLK rising edge. On the next CS falling edge the acquisition phase will end, and the device
starts a new frame.
The TSSOP packaged device has four General Purpose IO (GPIO) pins, QFN versions have only one GPIO.
These four pins can be individually programmed as GPO or GPI. It is also possible to use them for preassigned
functions, refer to Table 10. GPO data can be written into the device through the SDI line. The device refreshes
the GPO data on the CS falling edge as per the SDI data written in previous frame.
Similarly the device latches GPI status on the CS falling edge and outputs the GPI data on the SDO line (if GPI
read is enabled by writing DI04=1 in the previous frame) in the same frame starting with the CS falling edge.
Copyright © 2008–2010, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
a
1/t throughput (single frame)
CS
tw 1
tsu 1
3
4
15
16
SCLK
SDO
SDI
1
2
5
6
14
th 1
td 2
DO- DO-11
td 3
td 1
DO-
13
DO-10
MSB-1
DO-
15
DO-
14
DO-2 DO-1
LSB+2 LSB+1
DO-0
LSB
12
MSB
tq
tsu2
DI-10
DI-15
DI-14
DI-13
DI-12
DI-11
DI-2
DI-1
DI-0
th 2
Figure 46. Serial Interface Timing Diagram for 12-Bit Devices ( ADS7950/51/52/53)
a
1/t throughput (single frame)
CS
tw1
tsu1
td1
3
4
15
16
SCLK
SDO
SDI
1
2
5
6
14
th1
DO-
14
td2
DO- DO-11
td3
DO-
13
DO-10
MSB-1
DO-
15
DO-2
LSB
DO-1
-
DO-0
-
12
MSB
tq
tsu2
DI-10
DI-15
DI-14
DI-13
DI-12
DI-11
DI-2
DI-1
DI-0
th2
Figure 47. Serial Interface Timing Diagram for 10-Bit Devices (ADS7954/55/56/57)
a
1/t throughput (single frame)
CS
tw1
tsu1
td1
3
4
13
16
SCLK
SDO
SDI
1
2
5
6
12
th1
DO-
14
td2
DO- DO-11
td3
DO-
13
DO-10
MSB-1
DO-
15
DO-4
LSB
DO-3
-
DO-0
-
12
MSB
tq
tsu2
DI-10
DI-15
DI-14
DI-13
DI-12
DI-11
DI-4
DI-3
DI-0
th2
Figure 48. Serial Interface Timing Diagram for 8-Bit Devices (ADS7958/59/60/61)
The falling edge of CS clocks out DO-15 (first bit of the four bit channel address), and remaining address bits are
clocked out on every falling edge of SCLK until the third falling edge. The conversion result MSB is clocked out
on the 4th SCLK falling edge and LSB on the 15th/13th/11th falling edge respectively for 12/10/8-bit devices. On
the 16th falling edge of SCLK, SDO goes to the 3-state condition. The conversion ends on the 16th falling edge
of SCLK.
The device reads a sixteen bit word on the SDI pin while it outputs the data on the SDO pin. SDI data is latched
on every rising edge of SCLK starting with the 1st clock as shown in Figure 46, Figure 47, and Figure 48.
CS can be asserted (pulled high) only after 16 clocks have elapsed.
24
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
The device has two (high and low) programmable alarm thresholds per channel. If the input crosses these limits;
the device flags out an alarm on GPIO0/GPIO1 depending on the GPIO program register settings (refer to
Table 10). The alarm is asserted (under the alarm conditions) on the 12th falling edge of SCLK in the same
frame when a data conversion is in progress. The alarm output is reset on the 10th falling edge of SCLK in the
next frame.
The device offers a power-down feature to save power when not in use. There are two ways to powerdown the
device. It can be powered down by writing DI05 = 1 in the mode control register (refer to Table 1, Table 2, and
Table 5); in this case the device powers down on the 16th falling edge of SCLK in the next data frame. Another
way to powerdown the device is through GPIO in the case of the TSSOP packaged devices . GPIO3 can act as
the PD input (refer to Table 10, to assign this functionality to GPIO3). This is an asynchronous and active low
input. The device powers down instantaneously after GPIO3 (PD) = 0. The device will power up again on the CS
falling edge with DI05 = 0 in the mode control register and GPIO3 (PD) = 1.
CHANNEL SEQUENCING MODES
There are three modes for channel sequencing, namely Manual mode, Auto-1 mode, Auto-2 mode. Mode
selection is done by writing into the control register (refer to Table 1, Table 2, and Table 5). A new multiplexer
channel is selected on the second falling edge of SCLK (as shown in Figure 45) in all three modes.
Manual mode: When configured to operate in Manual mode, the next channel to be selected is programmed in
each frame and the device selects the programmed channel in the next frame. On powerup or after reset the
default channel is 'Channel-0' and the device is in Manual mode.
Auto-1 mode: In this mode the device scans pre-programmed channels in ascending order. A new multiplexer
channel is selected every frame on the second falling edge of SCLK. There is a separate ‘program register’ for
pre-programming the channel sequence. Table 3 and Table 4 show Auto-1 ‘program register’ settings.
Once programmed the device retains ‘program register’ settings until the device is powered down, reset, or
reprogrammed. It is allowed to exit and re-enter the Auto-1 mode any number of times without disturbing
‘program register’ settings.
The Auto-1 program register is reset to FFFF/FFF/FF/F hex for the 16/12/8/4 channel devices respectively upon
device powerup or reset; implying the device scans all channels in ascending order.
Auto-2 mode: In this mode the user can configure the program register to select the last channel in the scan
sequence. The device scans all channels from channel 0 up to and including the last channel in ascending order.
The multiplexer channel is selected every frame on the second falling edge of SCLK. There is a separate
‘program register’ for pre-programming of the last channel in the sequence (multiplexer depth). Table 6 lists the
‘Auto-2 prog’ register settings for selection of the last channel in the sequence.
Once programmed the device retains program register settings until the device is powered down, reset, or
reprogrammed. It is allowed to exit and re-enter Auto-2 mode any number of times, without disturbing the
‘program register’ settings.
On powerup or reset the bits D9-D6 of the Auto-2 program register are reset to F/B/7/3 hex for the 16/12/8/4
channel devices respectively; implying the device scans all channels in ascending order.
DEVICE PROGRAMMING AND MODE CONTROL
The following section describes device programming and mode control. These devices feature two types of
registers to configure and operate the devices in different modes. These registers are referred as ‘Configuration
Registers’. There are two types of ‘Configuration Registers’ namely ‘Mode control registers’ and ‘Program
registers’.
Mode Control Register
A ‘Mode control register’ is configured to operate the device in one of three channel sequencing modes, namely
Manual mode, Auto-1 Mode, Auto-2 Mode. It is also used to control user programmable features like range
selection, device power-down control, GPIO read control, and writing output data into the GPIO.
Copyright © 2008–2010, Texas Instruments Incorporated
Submit Documentation Feedback
25
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
Program Registers
The 'Program registers’ are used for device configuration settings and are typically programmed once on
powerup or after device reset. There are different program registers such as ‘Auto-1 mode programming’ for
pre-programming the channel sequence, ‘Auto-2 mode programming’ for selection of the last channel in the
sequence, ‘Alarm programming’ for all 16 channels (or 12,8,4 channels depending on the device) and GPIO for
individual pin configuration as GPI or GPO or a pre-assigned function.
DEVICE POWER-UP SEQUENCE
The device power-up sequence is shown in Figure 49. Manual mode is the default power-up channel sequencing
mode and Channel-0 is the first channel by default. As explained previously, these devices offer Program
Registers to configure user programmable features like GPIO, Alarm, and to pre-program the channel sequence
for Auto modes. At ‘powerup or on reset’ these registers are set to the default values listed in Table 1 to
Table 10. It is recommended to program these registers on powerup or after reset. Once configured; the device
is ready to use in any of the three channel sequencing modes namely Manual, Auto-1, and Auto-2.
26
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
Device power up or reset
Device operation in manual mode, Channel 0;
SDO Invalid in first frame
CS
First frame
CS
Auto 1 register program (note 1)
Auto 2 register program (note 1)
CS
CS
CS
Alarm register program (note 1)
GPIO register program (note 1)
Operation in manual mode
CS
Operation in Auto 1 mode
Operation in Auto 2 mode
CS
CS
(1) The device continues its operation in Manual mode channel 0 through out the programming sequence and outputs
valid conversion results. It is possible to change channel, range, GPIO by inserting extra frames in between two
programming blocks. It is also possible to bypass any programming block if the user does not intent to use that
feature.
(2) It is possible to reprogram the device at any time during operation, regardless of what mode the device is in. During
programming the device continues its operation in whatever mode it is in and outputs valid data.
Figure 49. Device Power-Up Sequence
OPERATING IN MANUAL MODE
The details regarding entering and running in Manual channel sequencing mode are illustrated in Figure 50.
Table 1 lists the Mode Control Register settings for Manual mode in detail. Note that there are no Program
Registers for manual mode.
Copyright © 2008–2010, Texas Instruments Incorporated
Submit Documentation Feedback
27
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
Device operation in Auto 1 or
Auto 2 mode
CS
Frame: n-1
No
Change to Manual mode?
Yes
* Sample: Samples and converts channel selected in ‘frame n-1’
* Mux : Selects channel incremented from previous frame as per auto sequence this channel will be
acquired in this frame and sampled at start of ‘frame n+1’
* Range: As programmed in ‘frame n-1’ . Applies to channel selected for acquisition in current fram.e
* SDI : Programming for ‘frame n +1’
DI15..12 = 0001binary …. Selects manual mode
DI11=1 enables programming of ‘range and GPIO’
DI10..7 = binary address of channel
CS
DI6.. As per required range for channel to be selected
DI5=0 .. No power down
DI4..0… as per GPIO settings
Frame: n
Request
for Manual
mode
*SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n-1’
* GPIO:
O/P: latched on CS falling edge as per DI3..0 written in frame n-1’
I/P: Input status latched on falling edge of CSand transferred serially on SDO in the same
frame
* Sample: Samples and converts channel selected in ‘frame n’
* Mux : Selects channel programmed in ‘frame n’(Manual mode) this channel will be acquired in this
frame and sampled at start of ‘frame n+2’
* Range: As programmed in ‘frame n’. Applies to channel selected for acquisition in current fram.e*
SDI : Programming for ‘frame n+2’
DI15..12 = 0001binary …. To continue in manual mode
DI11=1 enables programming of ‘range and GPIO’
DI10..7 = binary address of channel
CS
DI6.. As per required range for channel to be selected
DI5=0 .. No power down
DI4..0… as per GPIO settings
Frame:
n+1
Entry into
Manual
Mode
*SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n’
* GPIO:
O/P: latched on CS falling edge as per DI3..0 written in frame ‘n’
I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same
frame
* Sample: Samples and converts channel selected in ‘frame n+1’
* Mux : Selects channel programmed in ‘frame n+1’ (Manual mode), this channel will be acquired in
this frame and sampled at start of ‘frame n+3’
* Range: As programmed in ‘frame n+1’ . Applies to channel selected for acquisition in current frame.*
SDI : Programming for ‘frame n+3’
DI15..12 = 0001binary …. Selects manual mode
DI11=1 enables programming of ‘range and GPIO’
DI10..7 = binary address of channel
CS
DI6.. As per required range for channel to be selected
DI5=0 .. No power down
DI4..0… as per GPIO settings
Frame:
n+2
Operation
in Manual
mode
*SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n+1’
* GPIO:
O/P: latched on CS falling edge as per DI3..0 written in frame n+1’
I/P: Input status latched on falling edge of CSand transferred serially on SDO in the same
frame
CS
Continue operation in manual mode
Figure 50. Entering and Running in Manual Channel Sequencing Mode
28
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
Table 1. Mode Control Register Settings for Manual Mode
DESCRIPTION
RESET
STATE
BITS
LOGIC
STATE
FUNCTION
DI15-12
DI11
0001
0001
Selects Manual Mode
Enables programming of bits DI06-00.
Device retains values of DI06-00 from the previous frame.
0
1
0
DI10-07
DI06
0000
0
This four bit data represents the address of the next channel to be selected in the next frame. DI10: MSB and
DI07: LSB. e.g. 0000 represents channel- 0, 0001 represents channel-1 etc.
0
1
0
1
Selects 2.5V i/p range (Range 1)
Selects 5V i/p range (Range 2)
DI05
DI04
0
0
Device normal operation (no powerdown)
Device powers down on 16th SCLK falling edge
SDO outputs current channel address of the channel on DO15..12 followed by 12 bit conversion
result on DO11..00.
0
1
GPIO3-GPIO0 data (both input and output) is mapped onto DO15-DO12 in the order shown below.
Lower data bits DO11-DO00 represent 12-bit conversion result of the current channel.
DOI5
DOI4
DOI3
DOI2
GPIO3(1)
GPIO2(1)
GPIO1(1)
GPIO0(1)
DI03-00
0000
GPIO data for the channels configured as output. Device will ignore the data for the channel which is configured
as input. SDI bit and corresponding GPIO information is given below
DI03
DI02
DI01
DI00
GPIO3(2)
GPIO2(2)
GPIO1(2)
GPIO0(2)
(1) GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only.
(2) GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only.
Copyright © 2008–2010, Texas Instruments Incorporated
Submit Documentation Feedback
29
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
OPERATING IN AUTO-1 MODE
The details regarding entering and running in Auto-1 channel sequencing mode are illustrated in the flowchart in
Figure 51. Table 2 lists the Mode Control Register settings for Auto-1 mode in detail.
Device operation in Manual or
CS
Auto-2 mode
Frame: n-1
No
Change to Auto -1 mode?
Yes
* Sample: Samples and converts channel selected in ‘frame n-1’
* Mux : Selects channel incremented from previous frame as per Auto -2 sequence, or channel
programmed in previous frame in case of manual mode. This channel will be acquired in this frame
and sampled at start of ‘frame n+1’
* Range: As programmed in ‘frame n-1’ . Applies to channel selected for acquisition in current fram.e
* SDI : Programming for ‘frame n+1’
DI15..12 = 0010 binary …. Selects Auto-1 mode
DI11=1 enables programming of ‘range and GPIO’
DI10 = x, Device automatically resets channel to lowest number in Auto-1 sequence.
CS
DI6.. As per required range for channel to be selected
DI5=0 .. No power down
DI4..0… as per GPIO settings
*SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n-1’
* GPIO :
Frame: n
Request
for Auto-1
mode
O/P: latched on CS falling edge as per DI3..0 written in frame n-1’
I/P: Input status latched on falling edge of CSand transferred serially on SDO in the same
frame
* Sample: Samples and converts channel selected in ‘frame n’
* Mux : Selects lowest channel# in Auto-1 sequence; this channel will be acquired in this frame and
sampled at start of ‘frame n+2’
* Range: As programmed in ‘frame n’. Applies to channel selected for acquisition in current fram.e
* SDI : Programming for ‘frame n +2’
DI15..12 = 0010 binary …. To continue in Auto-1 mode
DI11=1 enables programming of ‘range and GPIO’
DI10 =0, not to reset channel sequence
CS
DI6.. As per required range for channel to be selected
DI5=0 .. No power down
DI4..0… as per GPIO settings
Frame:
n+1
Entry into
Auto-1
*SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n’
* GPIO :
O/P: latched on CS falling edge as per DI3..0 written in frame ‘n’
Mode
I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same
frame
* Sample: Samples and converts channel selected in ‘frame n+1’ (ie. Lowest channel# in Auto-1
sequence)
* Mux : Selects next higher channel in Auto-1 sequence, this channel will be acquired in this frame
and sampled at start of ‘frame n+3’
* Range: As programmed in ‘frame n+1’ . Applies to channel selected for acquisition in current frame.*
SDI : Programming for ‘frame n+3’
DI15..12 = 0010 binary …. To continue in Auto-1 mode
DI11=1 enables programming of ‘range and GPIO’
DI10 =0 not to reset channel sequence
DI6.. As per required range for channel to be selected
CS
Frame:
DI5=0 .. No power down
n+2
DI4..0… as per GPIO settings
*SDO : DO15..0 address (or GPIO data) & conversion data of channel selected in ‘frame n+1’
* GPIO :
Operation
in Auto-1
mode
O/P: latched on CS falling edge as per DI3..0 written in frame n+1’
I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same
frame
CS
Continue operation in Auto-1 mode
Figure 51. Entering and Running in Auto-1 Channel Sequencing Mode
30
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
Table 2. Mode Control Register Settings for Auto-1 Mode
DESCRIPTION
RESET
STATE
BITS
LOGIC
STATE
FUNCTION
DI15-12
DI11
0001
0010
Selects Auto-1 Mode
Enables programming of bits DI10-00.
0
1
0
Device retains values of DI10-00 from previous frame.
The channel counter is reset to the lowest programmed channel in the Auto-1 Program Register
The channel counter increments every conversion (No reset)
Do not care
DI10
0
1
0
DI09-07
DI06
000
0
xxx
0
Selects 2.5V i/p range (Range 1)
1
Selects 5V i/p range (Range 2)
DI05
DI04
0
0
0
Device normal operation (no powerdown)
1
Device powers down on the 16th SCLK falling edge
SDO outputs current channel address of the channel on DO15..12 followed by 12-bit conversion
result on DO11..00.
0
1
GPIO3-GPIO0 data (both input and output) is mapped onto DO15-DO12 in the order shown below.
Lower data bits DO11-DO00 represent 12-bit conversion result of the current channel.
DO15
DO14
DO13
DO12
GPIO3(1)
GPIO2(1)
GPIO1(1)
GPIO0(1)
DI03-00
0000
GPIO data for the channels configured as output. Device will ignore the data for the channel which is configured
as input. SDI bit and corresponding GPIO information is given below
DI03
DI02
DI01
DI00
GPIO3(2)
GPIO2(2)
GPIO1(2)
GPIO0(2)
(1) GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only.
(2) GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only.
Copyright © 2008–2010, Texas Instruments Incorporated
Submit Documentation Feedback
31
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
The Auto-1 Program Register is programmed (once on powerup or reset) to pre-select the channels for the
Auto-1 sequence. Auto-1 Program Register programming requires two CS frames for complete programming. In
the first CS frame the device enters the Auto-1 register programming sequence and in the second frame it
programs the Auto-1 Program Register. Refer to Table 2, Table 3, and Table 4 for complete details.
CS
Device in any operation mode
No
Program Auto 1 register?
Yes
SDI: DI15..12 = 1000
CS
(Device enters Auto 1 programming sequence)
Entry into Auto 1
register
programming
sequence
CS
SDI: DI15..0 as per tables 4,5
Auto 1 register
programming
End of Auto 1 register programming
NOTE: The device continues its operation in selected mode during programming. SDO is valid, however it is not possible to
change the range or write GPIO data into the device during programming.
Figure 52. Auto-1 Register Programming Flowchart
Table 3. Program Register Settings for Auto-1 Mode
DESCRIPTION
FUNCTION
RESET
STATE
BITS
LOGIC STATE
FRAME 1
DI15-12
DI11-00
FRAME 2
DI15-00
NA
1000
Device enters Auto-1 program sequence. Device programming is done in the next frame.
NA
Do not care
All 1s
1 (individual bit)
A particular channel is programmed to be selected in the channel scanning sequence. The
channel numbers are mapped one-to-one with respect to the SDI bits; e.g.
DI15 → Ch15, DI14 → Ch14 … DI00 → Ch00
A particular channel is programmed to be skipped in the channel scanning sequence. The
channel numbers are mapped one-to-one with respect to the SDI bits; e.g.
DI15 → Ch15, DI14 → Ch14 … DI00 → Ch00
0 (individual bit)
Table 4. Mapping of Channels to SDI Bits for 16,12,8,4 Channel Devices
Device(1)
SDI BITS
DI15 DI14 DI13 DI12
DI11
1/0
1/0
X
DI10
1/0
1/0
X
DI09
1/0
1/0
X
DI08
1/0
1/0
X
DI07
1/0
1/0
1/0
X
DI06
1/0
1/0
1/0
X
DI05
1/0
1/0
1/0
X
DI04
1/0
1/0
1/0
X
DI03
1/0
DI02
1/0
DI01
1/0
DI00
1/0
16 Chan
12 Chan
8 Chan
4 Chan
1/0
X
1/0
X
1/0
X
1/0
X
1/0
1/0
1/0
1/0
X
X
X
X
1/0
1/0
1/0
1/0
X
X
X
X
X
X
X
X
1/0
1/0
1/0
1/0
(1) When operating in Auto-1 mode, the device only scans the channels programmed to be selected.
32 Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
OPERATING IN AUTO-2 MODE
The details regarding entering and running in Auto-2 channel sequencing mode are illustrated in Figure 53.
Table 5 lists the Mode Control Register settings for Auto-2 mode in detail.
Device operation in Manual or
Auto -1 mode
CS
Frame: n-1
No
Change to Auto-2 mode?
Yes
* Sample: Samples and converts channel selected in ‘frame n-1’
* Mux : Selects channel incremented from previous frame as per Auto-1 sequence, or channel
programmed in previous frame in case of manual mod.e.This channel will be acquired in this frame
and sampled at start of ‘frame n+1’
* Range: As programmed in ‘frame n-1’. Applies to channel selected for acquisition in current fram.e
* SDI : Programming for ‘frame n+1’
DI15..12 = 0011 binary …. Selects Auto-2 mode
DI11=1 enables programming of ‘range and GPIO’
DI10 = x, Device automatically resets to channel0.
CS
DI6.. As per required range for channel to be selected
DI5=0 .. No power down
DI4..0… as per GPIO settings
*SDO : DO15..0 address(or GPIO data) & conversion data of channel selected in ‘frame n-1’
* GPIO :
Frame: n
Request
for Auto-2
mode
O/P: latched on CS falling edge as per DI3..0 written in frame n -1’
I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same
frame
* Sample: Samples and converts channel selected in ‘frame n’
* Mux : Selects channel0 (Auto-2 sequence always starts with Ch-0); this channel will be acquired
in this frame and sampled at start of ‘frame n+2’
* Range: As programmed in ‘frame n’. Applies to channel selected for acquisition in current fram.e
* SDI : Programming for ‘frame n +2’
DI15..12 = 0011 binary …. To continue in Auto-2 mode
DI11=1 enables programming of ‘range and GPIO’
DI10 =0, not to reset channel sequence
CS
DI6.. As per required range for channel to be selected
DI5=0 .. No power down
DI4..0… as per GPIO settings
*SDO : DO15..0 address(or GPIO data) & conversion data of channel selected in ‘frame n’
Frame:
n+1
Entry into
* GPIO :
Auto-2
O/P: latched on CS falling edge as per DI3..0 written in frame ‘n’
Mode
I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same
frame
* Sample: Samples and converts channel 0
* Mux : Selects next higher channel in Auto-2 sequence, this channel will be acquired in this frame
and sampled at start of ‘frame n+3’
* Range: As programmed in ‘frame n+1’. Applies to channel selected for acquisition in current frame.*
SDI : Programming for ‘frame n+3’
DI15..12 = 0011 binary …. To continue in Auto-2 mode
DI11=1 enables programming of ‘range and GPIO’
DI10 =0 not to reset channel sequence
CS
DI6.. As per required range for channel to be selected
DI5=0 .. No power down
DI4..0… as per GPIO settings
*SDO : DO15..0 address(or GPIO data) & conversion data of channel selected in ‘frame n+1’
* GPIO :
O/P: latched on CS falling edge as per DI3..0 written in frame n+1’
I/P: Input status latched on falling edge of CS and transferred serially on SDO in the same
frame
Frame:
n+2
Operation
in Auto-2
mode
CS
Continue operation in Auto-2 mode
Figure 53. Entering and Running in Auto-2 Channel Sequencing Mode
Copyright © 2008–2010, Texas Instruments Incorporated
Submit Documentation Feedback
33
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
Table 5. Mode Control Register Settings for Auto-2 Mode
DESCRIPTION
RESET
STATE
BITS
LOGIC
STATE
FUNCTION
DI15-12
DI11
0001
0011
Selects Auto-2 Mode
Enables programming of bits DI10-00.
0
1
0
Device retains values of DI10-00 from the previous frame.
Channel number is reset to Ch-00.
DI10
0
1
0
Channel counter increments every conversion.(No reset).
Do not care
DI09-07
DI06
000
0
xxx
0
Selects 2.5V i/p range (Range 1)
1
Selects 5V i/p range (Range 2)
DI05
DI04
0
0
0
Device normal operation (no powerdown)
Device powers down on the 16th SCLK falling edge
1
SDO outputs the current channel address of the channel on DO15..12 followed by the 12-bit
conversion result on DO11..00.
0
1
GPIO3-GPIO0 data (both input and output) is mapped onto DO15-DO12 in the order shown below.
Lower data bits DO11-DO00 represent the 12-bit conversion result of the current channel.
DO15
DO14
DO13
DO12
GPIO3(1)
GPIO2(1)
GPIO1(1)
GPIO0(1)
DI03-00
0000
GPIO data for the channels configured as output. Device ignores data for the channel which is configured as
input. SDI bit and corresponding GPIO information is given below
DI03
DI02
DI01
DI00
GPIO3(1)
GPIO2(1)
GPIO1(1)
GPIO0(1)
(1) GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only.
The Auto-2 Program Register is programmed (once on powerup or reset) to pre-select the last channel (or
sequence depth) in the Auto-2 sequence. Unlike Auto-1 Program Register programming, Auto-2 Program
Register programming requires only 1 CS frame for complete programming. See Figure 54 and Table 6 for
complete details.
CS
Device in any operation mode
No
Program Auto 2 register?
Yes
SDI: Di15..12 = 1001
DI9..6 = binary address of last channel in the sequence
refer tables 6
CS
Auto 2 register
programming
End of Auto 2 register programming
NOTE: The device continues its operation in the selected mode during programming. SDO is valid, however it is not possible
to change the range or write GPIO data into the device during programming.
Figure 54. Auto-2 Register Programming Flowchart
34
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
Table 6. Program Register Settings for Auto-2 Mode
DESCRIPTION
RESET
STATE
BITS
LOGIC
STATE
FUNCTION
DI15-12
DI11-10
DI09-06
NA
1001
Auto-2 program register is selected for programming
NA
NA
Do not care
aaaa
This 4-bit data represents the address of the last channel in the scanning sequence. During device
operation in Auto-2 mode, the channel counter starts at CH-00 and increments every frame until it
equals “aaaa”. The channel counter roles over to CH-00 in the next frame.
DI05-00
NA
Do not care
CONTINUED OPERATION IN A SELECTED MODE
Once a device is programmed to operate in one of the modes, the user may want to continue operating in the
same mode. Mode Control Register settings to continue operating in a selected mode are detailed in Table 7.
Table 7. Continued Operation in a Selected Mode
DESCRIPTION
RESET
STATE
BITS
LOGIC
STATE
FUNCTION
DI15-12
0001
0000
The device continues to operate in the selected mode. In Auto-1 and Auto-2 modes the channel
counter increments normally, whereas in the Manual mode it continues with the last selected
channel. The device ignores data on DI11-DI00 and continues operating as per the previous
settings. This feature is provided so that SDI can be held low when no changes are required in the
Mode Control Register settings.
DI11-00
All '0'
Device ignores these bits when DI15-12 is set to 0000 logic state
PROGRAMMING ALARM THRESHOLDS
There are two Alarm Program Registers per channel, one for setting the high alarm threshold and the other for
setting the low alarm threshold. For ease of programming, two alarm programming registers per channel,
corresponding to four consecutive channels, are assembled into one group (a total eight registers). There are
four such groups for 16 channel devices and 3/2/1 such groups for 12/8/4 channel devices respectively. The
grouping of the various channels for each device in the ADS79XX family is listed in Table 8. The details
regarding programming the alarm thresholds are illustrated in the flowchart in Figure 55. Table 9 lists the details
regarding the Alarm Program Register settings.
Table 8. Grouping of Alarm Program Registers
GROUP NO.
REGISTERS
APPLICABLE FOR DEVICE
ADS7953..50, ADS7957..54, ADS7961..58
ADS7953..51, ADS7957..55, ADS7961..59
ADS7953 and 52, ADS7957 and 56, ADS7961 and 60
ADS7953, ADS7957, ADS7961
0
1
2
3
High and low alarm for channel 0, 1, 2, and 3
High and low alarm for channel 4, 5, 6, and 7
High and low alarm for channel 8, 9, 10, and 11
High and low alarm for channel 12, 13, 14, and 15
Each alarm group requires 9 CS frames for programming their respective alarm thresholds. In the first frame the
device enters the programming sequence and in each subsequent frame it programs one of the registers from
the group. The device offers a feature to program less than eight registers in one programming sequence. The
device exits the alarm threshold programming sequence in the next frame after it encounters the first ‘Exit Alarm
Program’ bit high.
Copyright © 2008–2010, Texas Instruments Incorporated
Submit Documentation Feedback
35
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
CS
Device in any operation mode
No
Program alarm thresholds?
Yes
SDI: DI15..12 = 11XX
(xx indicates group of four channels; refer table 8)
Device enters alarm register programming sequence
CS
Entry into alarm
register
programming
sequence
CS
SDI: DI15..0 as per table 8 (program alarm thresholds)
Alarm register
programming
sequence
No
Yes
DI12 = 1?
Yes
Program another group of four channels?
No
End of alarm programing
NOTE: The device continues its operation in selected mode during programming. SDO is valid, however it is not possible to
change the range or write GPIO data into the device during programming.
Figure 55. Alarm Program Register Programming Flowchart
Table 9. Alarm Program Register Settings
DESCRIPTION
BITS
RESET STATE
LOGIC
STATE
FUNCTION
FRAME 1
DI15-12 NA
1100
1101
1110
1111
Device enters ‘alarm programming sequence’ for group 0
Device enters ‘alarm programming sequence’ for group 1
Device enters ‘alarm programming sequence’ for group 2
Device enters ‘alarm programming sequence’ for group 3
Note: DI15-12 = 11bb is the alarm programming request for group bb. Here ‘bb’ represents the alarm programming group number in binary
format.
DI11-14 NA
Do not care
FRAME 2 AND ONWARDS
36
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
Table 9. Alarm Program Register Settings (continued)
DESCRIPTION
BITS
RESET STATE
LOGIC
STATE
FUNCTION
DI15-14 NA
cc
Where “cc” represents the lower two bits of the channel number in binary format. The device
programs the alarm for the channel represented by the binary number “bbcc”. Note that “bb” is
programmed in the first frame.
DI13
DI12
NA
NA
1
0
0
1
High alarm register selection
Low alarm register selection
Continue alarm programming sequence in next frame
Exit Alarm Programming in the next frame. Note: If the alarm programming sequence is not
terminated using this feature then the device will remain in the alarm programming sequence
state and all SDI data will be treated as alarm thresholds.
DI11-10 NA
xx
Do not care
DI09-00 All ones for high
alarm register
This 10-bit data represents the alarm threshold. The 10-bit alarm threshold is compared with the upper 10-bit
word of the 12-bit conversion result. The device sets off an alarm when the conversion result is higher (High
Alarm) or lower (Low Alarm) than this number. For 10-bit devices, all 10 bits of the conversion result are
and all zeros for
low alarm register compared with the set threshold. For 8-bit devices, all 8 bits of the conversion result are compared with DI09
to DI02 and DI00, 01 are 'do not care'.
PROGRAMMING GPIO REGISTERS
NOTE
GPIO 1 to 3 are available only in TSSOP packaged devices. The QFN device offers
'GPIO 0' only. As a result, all references related to 'GPIO 0' only are valid in the case
of QFN package devices.
The device has four General Purpose Input and Output (GPIO) pins. Each of the four pins can be independently
programmed as General Purpose Output (GPO) or General Purpose Input (GPI). It is also possible to use the
GPIOs for some pre-assigned functions (refer to Table 10 for details). GPO data can be written into the device
through the SDI line. The device refreshes the GPO data on every CS falling edge as per the SDI data written in
the previous frame. Similarly, the device latches GPI status on the CS falling edge and outputs it on SDO (if GPI
is read enabled by writing DI04 = 1 during the previous frame) in the same frame starting on the CS falling edge.
The details regarding programming the GPIO registers are illustrated in the flowchart in Figure 56. Table 10 lists
the details regarding GPIO Register programming settings.
Copyright © 2008–2010, Texas Instruments Incorporated
Submit Documentation Feedback
37
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
CS
Device in any operation mode
No
Program GPIO register?
Yes
CS
SDI: DI15..12 = 0100
Refer table 9 for DI11..00 data
GPIO register
programming
End of GPIO register programming
NOTE: The device continues its operation in selected mode during programming. SDO is valid, however it is not possible to
change the range or write GPIO data into the device during programming.
Figure 56. GPIO Program Register Programming Flowchart
Table 10. GPIO Program Register Settings
DESCRIPTION
RESET
STATE
BITS
LOGIC
STATE
FUNCTION
DI15-12 NA
DI11-10 00
0100
00
Device selects GPIO Program Registers for programming.
Do not program these bits to any logic state other than ‘00’
DI09
0
1
Device resets all registers in the next CS frame to the reset state shown in the corresponding tables (it
also resets itself).
0
Device normal operation
DI08
DI07
0
0
1
Device configures GPIO3 as the device power-down input.
GPIO3 remains general purpose I or O. Program 0 for QFN packaged devices.
Device configures GPIO2 as device range input.
0
1
0
GPIO2 remains general purpose I or O. Program 0 for QFN packaged devices.
GPIO1 and GPIO0 remain general purpose I or O. Valid setting for QFN packaged devices.
DI06-04 000
000
xx1
Device configures GPIO0 as ‘high or low’ alarm output. This is an active high output. GPIO1 remains
general purpose I or O. Valid setting for QFN packaged devices.
010
100
110
Device configures GPIO0 as high alarm output. This is an active high output. GPIO1 remains general
purpose I or O. Valid setting for QFN packaged devices.
Device configures GPIO1 as low alarm output. This is an active high output. GPIO0 remains general
purpose I or O. Setting not allowed for QFN packaged devices.
Device configures GPIO1 as low alarm output and GPIO0 as a high alarm output. These are active high
outputs. Setting not allowed for QFN packaged devices.
Note: The following settings are valid for GPIO which are not assigned a specific function through bits DI08..04
DI03
DI02
DI01
DI00
0
0
0
0
1
0
1
0
1
0
1
GPIO3 pin is configured as general purpose output. Program 1 for QFN packaged devices.
GPIO3 pin is configured as general purpose input. Setting not allowed for QFN packaged devices.
GPIO2 pin is configured as general purpose output. Program 1 for QFN packaged devices.
GPIO2 pin is configured as general purpose input. Setting not allowed for QFN packaged devices.
GPIO1 pin is configured as general purpose output. Program 1 for QFN packaged devices.
GPIO1 pin is configured as general purpose input. Setting not allowed for QFN packaged devices.
GPIO0 pin is configured as general purpose output. Valid setting for QFN packaged devices.
38
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
Table 10. GPIO Program Register Settings (continued)
DESCRIPTION
FUNCTION
GPIO0 pin is configured as general purpose input. Valid setting for QFN packaged devices.
RESET
STATE
BITS
LOGIC
STATE
0
Copyright © 2008–2010, Texas Instruments Incorporated
Submit Documentation Feedback
39
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
APPLICATION INFORMATION
ANALOG INPUT
The ADS79XX device family offers 12/10/8-bit ADCSs with 16/12/8/4 channel multiplexers for analog input. The
multiplexer output is available on the MXO pin. AINP is the ADC input pin. The devices offers flexibility for a
system designer as both signals are accessible esternally.
Typically it is convenient to short MXO to the AINP pin so that signal input to each multiplexer channel can be
processed independently. In this condition it is recommended to limit source impedance to 50Ω or less. Higher
source impedance may affect the signal settling time after a multiplexer channel change. This condition can
affect linearity and total harmonic distortion.
MXO
AINP
GPIO 0, H Alarm
Ch0
Ch1
Ch2
GPIO 1, L Alarm
GPIO 2, Range
GPIO 3, PD
From sensors, INA etc.
There is a restriction on
source impedance.
To
Host
ADC
SDO
R
SOURCE £ 50 W
SDI
SCLK
CS
Chn*
REF
10 mF
REF5025
o/p
GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers 'GPIO 0' only. As a result all
references related to 'GPIO 0' only are valid in case of QFN package devices.
Figure 57. Typical Application Diagram Showing MXO Shorted to AINP
Another option is to add a common ADC driver buffer between the MXO and AINP pins. This relaxes the
restriction on source impedance to a large extent. Refer to the typical characteristics section for the effect of
source impedance on device performance. The typical characteristics show that the device has respectable
performance with up to 1kΩ source impedance. This topology (including a common ADC driver) is useful when
all channel signals are within the acceptable range of the ADC. In this case the user can save on signal
conditioning circuit for each channel.
40
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
High Input
impedance PGA
(or non inverting buffer
like THS4031)
PGA Gain
Control
GPIO
1, 2, 3
MXO
AINP
GPIO 0
H/L Alarm
Ch0
Ch1
Ch2
From sensors, INA etc.
Source impedance has very
little effect on performance.
Refer to Typical Characteristics
for details.
To
Host
ADC
SDO
SDI
SCLK
CS
Chn*
REF
10 mF
REF5025
o/p
GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers 'GPIO 0' only. As a result all
references related to 'GPIO 0' only are valid in case of QFN package devices.
Figure 58. Typical Application Diagram Showing Common Buffer/PGA for all Channels
When the converter samples an input, the voltage difference between AINP and AGND is captured on the
internal capacitor array. The (peak) input current through the analog inputs depends upon a number of factors:
sample rate, input voltage, and source impedance. The current into the ADS79XX charges the internal capacitor
array during the sample period. After this capacitance has been fully charged, there is no further input current.
When the converter goes into hold mode, the input impedance is greater than 1 GΩ.
Care must be taken regarding the absolute analog input voltage. To maintain linearity of the converter, the Ch0 ..
Chn and AINP inputs should be within the limits specified. Outside of these ranges, converter linearity may not
meet specifications.
Copyright © 2008–2010, Texas Instruments Incorporated
Submit Documentation Feedback
41
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
W
80
MXO
Ch0
W
200
AINP
3 pF
5 pF
7 pF
Chn
W
20M
3 pF
Ch0 assumed to be on
Chn assumed to be off
Figure 59. ADC and Mux Equivalent Circuit
REFERENCE
The ADS79XX can operate with an external 2.5V ± 10mV reference. A clean, low noise, well-decoupled
reference voltage on the REF pin is required to ensure good performance of the converter. A low noise band-gap
reference like the REF5025 can be used to drive this pin. A 10-mF ceramic decoupling capacitor is required
between the REF and GND pins of the converter. The capacitor should be placed as close as possible to the
pins of the device.
POWER SAVING
The ADS79XX devices offer a power-down feature to save power when not in use. There are two ways to
powerdown the device. It can be powered down by writing DI05 = 1 in the Mode Control register (refer to
Table 1, Table 2 and Table 5); in this case the device powers down on the 16th falling edge of SCLK in the next
data frame. Another way to powerdown the device is through GPIO. GPIO3 can act as a PD input (refer to
Table 10, for assigning this functionality to GPIO3). This is an asynchronous and active low input. The device
powers down instantaneously after GPIO3 (PD) = 0. The device will powerup again on the CS falling edge while
DI05 = 0 in the Mode Control register and GPIO3 (PD) = 1.
DIGITAL OUTPUT
As discussed previously in the Device Operation section, the digital output of the ADS79XX devices is SPI
compatible. The following table lists the output codes corresponding to various analog input voltages.
Table 11. Ideal Input Voltages and Output Codes for 12-Bit Devices (ADS7950/51/52/53)
DESCRIPTION
Full scale range
ANALOG VALUE
Range 2 → 2×Vref
DIGITAL OUTPUT
STRAIGHT BINARY
Range 1 → Vref
Vref/4096
Vref – 1 LSB
Vref/2
Least significant bit (LSB)
Full scale
2Vref/4096
2Vref – 1 LSB
Vref
BINARY CODE
1111 1111 1111
HEX CODE
FFF
Midscale
1000 0000 0000
0111 1111 1111
0000 0000 0000
800
7FF
000
Midscale – 1 LSB
Zero
Vref/2 – 1 LSB
0 V
Vref – 1 LSB
0 V
Table 12. Ideal Input Voltages and Output Codes for 10-Bit Devices (ADS7954/55/56/57)
DESCRIPTION
Full scale range
ANALOG VALUE
Range 2 → 2×Vref
DIGITAL OUTPUT
STRAIGHT BINARY
Range 1 → Vref
Vref/1024
Vref – 1 LSB
Vref/2
Least significant bit (LSB)
Full scale
2Vref/1024
2Vref – 1 LSB
Vref
BINARY CODE
11 1111 1111
HEX CODE
3FF
Midscale
10 0000 0000
01 1111 1111
00 0000 0000
200
1FF
000
Midscale – 1 LSB
Zero
Vref/2 – 1 LSB
0 V
Vref – 1 LSB
0 V
42
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
Table 13. Ideal Input Voltages and Output Codes for 8-Bit Devices (ADS7958/59/60/61)
DESCRIPTION
ANALOG VALUE
Range 2 → 2×Vref
DIGITAL OUTPUT
STRAIGHT BINARY
Full scale range
Least significant bit (LSB)
Full scale
Range 1 → Vref
Vref/256
2Vref/256
2Vref – 1 LSB
Vref
BINARY CODE
1111 1111
HEX CODE
FF
Vref – 1 LSB
Vref/2
Midscale
1000 0000
0111 1111
0000 0000
80
7F
00
Midscale – 1 LSB
Zero
Vref/2 – 1 LSB
0 V
Vref – 1 LSB
0 V
Copyright © 2008–2010, Texas Instruments Incorporated
Submit Documentation Feedback
43
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010
www.ti.com
REVISION HISTORY
Changes from Original (June 2008) to Revision A
Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Added QFN information to Features ..................................................................................................................................... 1
Added QFN information to Description ................................................................................................................................. 1
Added QFN information to 12-bit ordering information ......................................................................................................... 3
Added QFN information to 10-bit ordering information ......................................................................................................... 3
Added QFN information to 8-bit ordering information ........................................................................................................... 4
Changed thermal impedance for DBT package in absolute maximum ratings .................................................................... 4
Changed thermal impedance for RHB package in absolute maximum ratings .................................................................... 4
Changed thermal impedance for RGE package in absolute maximum ratings .................................................................... 4
Added Vref = 2.5 V ± 0.1 V to ELECTRICAL CHARACTERISTICS, ADS7950/51/52/53 ..................................................... 5
Added while 2Vref ≤ +VA to full-scale input span range 2 test conditions ........................................................................... 5
Added while 2Vref ≤ +VA to full-scale input span range 2 test conditions ........................................................................... 5
Added Total unadjusted error (TUE) specification ................................................................................................................ 5
Changed reference voltage at REFP min and max values .................................................................................................. 6
Added Vref = 2.5 V ± 0.1 V to ELECTRICAL CHARACTERISTICS, ADS7950/51/52/53 ..................................................... 6
Added Note to ELECTRICAL CHARACTERISTICS, ADS7950/51/52/53 ............................................................................ 6
Added Vref = 2.5 V ± 0.1 V to ELECTRICAL CHARACTERISTICS, ADS7954/55/56/57 test conditions ............................. 6
Added while 2Vref ≤ +VA to full-scale input span range 2 test conditions ........................................................................... 6
Added while 2Vref ≤ +VA to full-scale input span range 2 test conditions ........................................................................... 6
Added Vref = 2.5 V ± 0.1 V to ELECTRICAL CHARACTERISTICS, ADS7954/55/56/57 test conditions ............................. 7
Changed Vref reference voltage at REFP min value from 2.49 V to 2.0 V ........................................................................... 7
Changed Vref reference voltage at REFP max value from 2.51 V to 3.0 V .......................................................................... 7
Added Vref = 2.5 V ± 0.1 V to ELECTRICAL CHARACTERISTICS, ADS7954/55/56/57 test conditions ............................. 8
Added Vref = 2.5 V ± 0.1 V to ELECTRICAL CHARACTERISTICS, ADS7958/59/60/61 test conditions ............................. 8
Added while 2Vref ≤ +VA to full-scale input span range 2 test conditions ........................................................................... 8
Added while 2Vref ≤ +VA to full-scale input span range 2 test conditions ........................................................................... 8
Changed Vref reference voltage at REFP min value from 2.49 V to 2.0 V ........................................................................... 9
Changed Vref reference voltage at REFP max value from 2.51 V to 3.0 V .......................................................................... 9
Added Vref = 2.5 V ± 0.1 V to ELECTRICAL CHARACTERISTICS, ADS7958/59/60/61 test conditions ............................. 9
Changed tsu1 values from max to min ................................................................................................................................. 10
Changed tsu2 values from max to min ................................................................................................................................. 10
Changed VEE to AGND and VCC to +VA on 38-pin TSSOP pinout ................................................................................. 11
Added QFN pinout .............................................................................................................................................................. 11
Added QFN pinout .............................................................................................................................................................. 12
Added QFN pinout .............................................................................................................................................................. 12
Added QFN pinout .............................................................................................................................................................. 12
Added terminal functions for QFN packages ...................................................................................................................... 14
Changed ADS7950/4/8 QFN package MXO pin from 7 to 3 .............................................................................................. 14
Added TOTAL UNADJUSTED ERROR (TUE Max) graph ................................................................................................. 21
Added TOTAL UNADJUSTED ERROR (TUE Min) graph .................................................................................................. 21
Changed GPIO pins description ......................................................................................................................................... 23
Added device powerdown through GPIO in the case of the TSSOP packaged devices ................................................... 25
Added note to Table 1 ........................................................................................................................................................ 29
Added note to Table 1 ........................................................................................................................................................ 29
44
Submit Documentation Feedback
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
www.ti.com
SLAS605A –JUNE 2008–REVISED JANUARY 2010
•
•
•
•
•
•
•
•
Added note to Table 2 ........................................................................................................................................................ 31
Added note to Table 2 ........................................................................................................................................................ 31
Added note to Table 5 ........................................................................................................................................................ 34
Changed DI12 = 1? from No or No to Yes or No in Figure 55 ........................................................................................... 36
Added note to Programming GPIO Registers description .................................................................................................. 37
Added QFN information to Table 10 ................................................................................................................................... 38
Added note to Figure 57 ..................................................................................................................................................... 40
Added note to Figure 58 ..................................................................................................................................................... 41
Copyright © 2008–2010, Texas Instruments Incorporated
Submit Documentation Feedback
45
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jul-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
ADS7950SBDBT
ADS7950SBDBTG4
ADS7950SBDBTR
ADS7950SBDBTRG4
ADS7950SBRGER
ADS7950SBRGET
ADS7950SDBT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
VQFN
DBT
DBT
DBT
DBT
RGE
RGE
DBT
DBT
DBT
DBT
RGE
RGE
DBT
DBT
DBT
DBT
RGE
30
30
30
30
24
24
30
30
30
30
24
24
30
30
30
30
24
60
60
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Add to cart
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
2000
2000
3000
250
60
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
VQFN
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
VQFN
Green (RoHS
& no Sb/Br)
ADS7950SDBTG4
ADS7950SDBTR
ADS7950SDBTRG4
ADS7950SRGER
ADS7950SRGET
ADS7951SBDBT
60
Green (RoHS
& no Sb/Br)
2000
2000
3000
250
60
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
VQFN
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
VQFN
Green (RoHS
& no Sb/Br)
ADS7951SBDBTG4
ADS7951SBDBTR
ADS7951SBDBTRG4
ADS7951SBRGER
60
Green (RoHS
& no Sb/Br)
2000
2000
3000
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jul-2011
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
ADS7951SBRGET
ADS7951SDBT
VQFN
TSSOP
TSSOP
TSSOP
TSSOP
VQFN
RGE
DBT
DBT
DBT
DBT
RGE
RGE
DBT
DBT
DBT
DBT
RHB
RHB
DBT
DBT
DBT
DBT
RHB
24
30
30
30
30
24
24
38
38
38
38
32
32
38
38
38
38
32
250
60
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Add to cart
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-3-260C-168 HR
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
ADS7951SDBTG4
ADS7951SDBTR
ADS7951SDBTRG4
ADS7951SRGER
ADS7951SRGET
ADS7952SBDBT
ADS7952SBDBTG4
ADS7952SBDBTR
ADS7952SBDBTRG4
ADS7952SBRHBR
ADS7952SBRHBT
ADS7952SDBT
60
Green (RoHS
& no Sb/Br)
2000
2000
3000
250
50
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
VQFN
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
QFN
Green (RoHS
& no Sb/Br)
50
Green (RoHS
& no Sb/Br)
2000
2000
3000
250
50
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
QFN
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
QFN
Green (RoHS
& no Sb/Br)
ADS7952SDBTG4
ADS7952SDBTR
ADS7952SDBTRG4
ADS7952SRHBR
50
Green (RoHS
& no Sb/Br)
2000
2000
3000
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jul-2011
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
ADS7952SRHBT
ADS7953SBDBT
ADS7953SBDBTG4
ADS7953SBDBTR
ADS7953SBDBTRG4
ADS7953SBRHBR
ADS7953SBRHBT
ADS7953SDBT
QFN
RHB
DBT
DBT
DBT
DBT
RHB
RHB
DBT
DBT
DBT
DBT
RHB
RHB
DBT
DBT
DBT
DBT
RGE
32
38
38
38
38
32
32
38
38
38
38
32
32
30
30
30
30
24
250
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Add to cart
TSSOP
TSSOP
TSSOP
TSSOP
QFN
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-3-260C-168 HR
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
50
Green (RoHS
& no Sb/Br)
2000
2000
3000
250
50
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
QFN
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
QFN
Green (RoHS
& no Sb/Br)
ADS7953SDBTG4
ADS7953SDBTR
ADS7953SDBTRG4
ADS7953SRHBR
ADS7953SRHBT
ADS7954SDBT
50
Green (RoHS
& no Sb/Br)
2000
2000
3000
250
60
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
QFN
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
VQFN
Green (RoHS
& no Sb/Br)
ADS7954SDBTG4
ADS7954SDBTR
ADS7954SDBTRG4
ADS7954SRGER
60
Green (RoHS
& no Sb/Br)
2000
2000
3000
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jul-2011
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
ADS7954SRGET
ADS7955SDBT
VQFN
TSSOP
TSSOP
TSSOP
TSSOP
VQFN
RGE
DBT
DBT
DBT
DBT
RGE
RGE
DBT
DBT
DBT
DBT
RHB
RHB
DBT
DBT
DBT
DBT
RHB
24
30
30
30
30
24
24
38
38
38
38
32
32
38
38
38
38
32
250
60
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Add to cart
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-3-260C-168 HR
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
ADS7955SDBTG4
ADS7955SDBTR
ADS7955SDBTRG4
ADS7955SRGER
ADS7955SRGET
ADS7956SDBT
60
Green (RoHS
& no Sb/Br)
2000
2000
3000
250
50
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
VQFN
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
QFN
Green (RoHS
& no Sb/Br)
ADS7956SDBTG4
ADS7956SDBTR
ADS7956SDBTRG4
ADS7956SRHBR
ADS7956SRHBT
ADS7957SDBT
50
Green (RoHS
& no Sb/Br)
2000
2000
3000
250
50
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
QFN
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
QFN
Green (RoHS
& no Sb/Br)
ADS7957SDBTG4
ADS7957SDBTR
ADS7957SDBTRG4
ADS7957SRHBR
50
Green (RoHS
& no Sb/Br)
2000
2000
3000
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jul-2011
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
ADS7957SRHBT
ADS7958SDBT
QFN
RHB
DBT
DBT
DBT
DBT
RGE
RGE
DBT
DBT
DBT
DBT
RGE
RGE
DBT
DBT
DBT
DBT
RHB
32
30
30
30
30
24
24
30
30
30
30
24
24
38
38
38
38
32
250
60
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Add to cart
TSSOP
TSSOP
TSSOP
TSSOP
VQFN
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-3-260C-168 HR
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
ADS7958SDBTG4
ADS7958SDBTR
ADS7958SDBTRG4
ADS7958SRGER
ADS7958SRGET
ADS7959SDBT
60
Green (RoHS
& no Sb/Br)
2000
2000
3000
250
60
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
VQFN
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
VQFN
Green (RoHS
& no Sb/Br)
ADS7959SDBTG4
ADS7959SDBTR
ADS7959SDBTRG4
ADS7959SRGER
ADS7959SRGET
ADS7960SDBT
60
Green (RoHS
& no Sb/Br)
2000
2000
3000
250
50
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
VQFN
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
QFN
Green (RoHS
& no Sb/Br)
ADS7960SDBTG4
ADS7960SDBTR
ADS7960SDBTRG4
ADS7960SRHBR
50
Green (RoHS
& no Sb/Br)
2000
2000
3000
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Addendum-Page 5
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jul-2011
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
ADS7960SRHBT
ADS7961SDBT
QFN
TSSOP
TSSOP
TSSOP
TSSOP
QFN
RHB
DBT
DBT
DBT
DBT
RHB
RHB
32
38
38
38
38
32
32
250
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Add to cart
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
Add to cart
ADS7961SDBTG4
ADS7961SDBTR
ADS7961SDBTRG4
ADS7961SRHBR
ADS7961SRHBT
50
Green (RoHS
& no Sb/Br)
2000
2000
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
QFN
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 6
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jul-2011
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 7
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS7950SBDBTR
ADS7950SBRGER
ADS7950SBRGET
ADS7950SDBTR
ADS7950SRGER
ADS7950SRGET
ADS7951SBDBTR
ADS7951SBRGER
ADS7951SBRGET
ADS7951SDBTR
ADS7951SRGER
ADS7951SRGET
ADS7952SBDBTR
ADS7952SBRHBR
ADS7952SBRHBT
ADS7952SDBTR
ADS7952SRHBR
ADS7952SRHBT
TSSOP
VQFN
VQFN
TSSOP
VQFN
VQFN
TSSOP
VQFN
VQFN
TSSOP
VQFN
VQFN
TSSOP
QFN
DBT
RGE
RGE
DBT
RGE
RGE
DBT
RGE
RGE
DBT
RGE
RGE
DBT
RHB
RHB
DBT
RHB
RHB
30
24
24
30
24
24
30
24
24
30
24
24
38
32
32
38
32
32
2000
3000
250
330.0
330.0
180.0
330.0
330.0
180.0
330.0
330.0
180.0
330.0
330.0
180.0
330.0
330.0
180.0
330.0
330.0
180.0
16.4
12.4
12.4
16.4
12.4
12.4
16.4
12.4
12.4
16.4
12.4
12.4
16.4
12.4
12.4
16.4
12.4
12.4
6.95
4.25
4.25
6.95
4.25
4.25
6.95
4.25
4.25
6.95
4.25
4.25
6.9
8.3
4.25
4.25
8.3
1.6
1.15
1.15
1.6
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
8.0
8.0
12.0
8.0
8.0
16.0
12.0
12.0
16.0
12.0
12.0
16.0
12.0
12.0
16.0
12.0
12.0
16.0
12.0
12.0
16.0
12.0
12.0
Q1
Q2
Q2
Q1
Q2
Q2
Q1
Q2
Q2
Q1
Q2
Q2
Q1
Q2
Q2
Q1
Q2
Q2
2000
3000
250
4.25
4.25
8.3
1.15
1.15
1.6
2000
3000
250
4.25
4.25
8.3
1.15
1.15
1.6
2000
3000
250
4.25
4.25
10.2
5.3
1.15
1.15
1.8
2000
3000
250
5.3
1.5
QFN
5.3
5.3
1.5
TSSOP
QFN
2000
3000
250
6.9
10.2
5.3
1.8
5.3
1.5
QFN
5.3
5.3
1.5
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS7953SBDBTR
ADS7953SBRHBR
ADS7953SBRHBT
ADS7953SDBTR
ADS7953SRHBR
ADS7953SRHBT
ADS7954SDBTR
ADS7954SRGER
ADS7954SRGET
ADS7955SDBTR
ADS7955SRGER
ADS7955SRGET
ADS7956SDBTR
ADS7957SDBTR
ADS7958SDBTR
ADS7958SRGER
ADS7958SRGET
ADS7959SDBTR
ADS7959SRGER
ADS7959SRGET
ADS7960SDBTR
ADS7961SDBTR
TSSOP
QFN
DBT
RHB
RHB
DBT
RHB
RHB
DBT
RGE
RGE
DBT
RGE
RGE
DBT
DBT
DBT
RGE
RGE
DBT
RGE
RGE
DBT
DBT
38
32
32
38
32
32
30
24
24
30
24
24
38
38
30
24
24
30
24
24
38
38
2000
3000
250
330.0
330.0
180.0
330.0
330.0
180.0
330.0
330.0
180.0
330.0
330.0
180.0
330.0
330.0
330.0
330.0
180.0
330.0
330.0
180.0
330.0
330.0
16.4
12.4
12.4
16.4
12.4
12.4
16.4
12.4
12.4
16.4
12.4
12.4
16.4
16.4
16.4
12.4
12.4
16.4
12.4
12.4
16.4
16.4
6.9
5.3
10.2
5.3
1.8
1.5
12.0
8.0
16.0
12.0
12.0
16.0
12.0
12.0
16.0
12.0
12.0
16.0
12.0
12.0
16.0
16.0
16.0
12.0
12.0
16.0
12.0
12.0
16.0
16.0
Q1
Q2
Q2
Q1
Q2
Q2
Q1
Q2
Q2
Q1
Q2
Q2
Q1
Q1
Q1
Q2
Q2
Q1
Q2
Q2
Q1
Q1
QFN
5.3
5.3
1.5
8.0
TSSOP
QFN
2000
3000
250
6.9
10.2
5.3
1.8
12.0
8.0
5.3
1.5
QFN
5.3
5.3
1.5
8.0
TSSOP
VQFN
VQFN
TSSOP
VQFN
VQFN
TSSOP
TSSOP
TSSOP
VQFN
VQFN
TSSOP
VQFN
VQFN
TSSOP
TSSOP
2000
3000
250
6.95
4.25
4.25
6.95
4.25
4.25
6.9
8.3
1.6
8.0
4.25
4.25
8.3
1.15
1.15
1.6
8.0
8.0
2000
3000
250
8.0
4.25
4.25
10.2
10.2
8.3
1.15
1.15
1.8
8.0
8.0
2000
2000
2000
3000
250
12.0
12.0
8.0
6.9
1.8
6.95
4.25
4.25
6.95
4.25
4.25
6.9
1.6
4.25
4.25
8.3
1.15
1.15
1.6
8.0
8.0
2000
3000
250
8.0
4.25
4.25
10.2
10.2
1.15
1.15
1.8
8.0
8.0
2000
2000
12.0
12.0
6.9
1.8
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS7950SBDBTR
ADS7950SBRGER
ADS7950SBRGET
ADS7950SDBTR
ADS7950SRGER
ADS7950SRGET
ADS7951SBDBTR
ADS7951SBRGER
ADS7951SBRGET
ADS7951SDBTR
ADS7951SRGER
ADS7951SRGET
ADS7952SBDBTR
ADS7952SBRHBR
ADS7952SBRHBT
ADS7952SDBTR
ADS7952SRHBR
ADS7952SRHBT
ADS7953SBDBTR
ADS7953SBRHBR
TSSOP
VQFN
VQFN
TSSOP
VQFN
VQFN
TSSOP
VQFN
VQFN
TSSOP
VQFN
VQFN
TSSOP
QFN
DBT
RGE
RGE
DBT
RGE
RGE
DBT
RGE
RGE
DBT
RGE
RGE
DBT
RHB
RHB
DBT
RHB
RHB
DBT
RHB
30
24
24
30
24
24
30
24
24
30
24
24
38
32
32
38
32
32
38
32
2000
3000
250
367.0
367.0
210.0
367.0
367.0
210.0
367.0
367.0
210.0
367.0
367.0
210.0
367.0
367.0
210.0
367.0
367.0
210.0
367.0
367.0
367.0
367.0
185.0
367.0
367.0
185.0
367.0
367.0
185.0
367.0
367.0
185.0
367.0
367.0
185.0
367.0
367.0
185.0
367.0
367.0
38.0
35.0
35.0
38.0
35.0
35.0
38.0
35.0
35.0
38.0
35.0
35.0
38.0
35.0
35.0
38.0
35.0
35.0
38.0
35.0
2000
3000
250
2000
3000
250
2000
3000
250
2000
3000
250
QFN
TSSOP
QFN
2000
3000
250
QFN
TSSOP
QFN
2000
3000
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS7953SBRHBT
ADS7953SDBTR
ADS7953SRHBR
ADS7953SRHBT
ADS7954SDBTR
ADS7954SRGER
ADS7954SRGET
ADS7955SDBTR
ADS7955SRGER
ADS7955SRGET
ADS7956SDBTR
ADS7957SDBTR
ADS7958SDBTR
ADS7958SRGER
ADS7958SRGET
ADS7959SDBTR
ADS7959SRGER
ADS7959SRGET
ADS7960SDBTR
ADS7961SDBTR
QFN
TSSOP
QFN
RHB
DBT
RHB
RHB
DBT
RGE
RGE
DBT
RGE
RGE
DBT
DBT
DBT
RGE
RGE
DBT
RGE
RGE
DBT
DBT
32
38
32
32
30
24
24
30
24
24
38
38
30
24
24
30
24
24
38
38
250
2000
3000
250
210.0
367.0
367.0
210.0
367.0
367.0
210.0
367.0
367.0
210.0
367.0
367.0
367.0
367.0
210.0
367.0
367.0
210.0
367.0
367.0
185.0
367.0
367.0
185.0
367.0
367.0
185.0
367.0
367.0
185.0
367.0
367.0
367.0
367.0
185.0
367.0
367.0
185.0
367.0
367.0
35.0
38.0
35.0
35.0
38.0
35.0
35.0
38.0
35.0
35.0
38.0
38.0
38.0
35.0
35.0
38.0
35.0
35.0
38.0
38.0
QFN
TSSOP
VQFN
VQFN
TSSOP
VQFN
VQFN
TSSOP
TSSOP
TSSOP
VQFN
VQFN
TSSOP
VQFN
VQFN
TSSOP
TSSOP
2000
3000
250
2000
3000
250
2000
2000
2000
3000
250
2000
3000
250
2000
2000
Pack Materials-Page 4
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products
Audio
Applications
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
www.ti.com/security
Medical
Logic
Security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense www.ti.com/space-avionics-defense
microcontroller.ti.com
www.ti-rfid.com
Video and Imaging
www.ti.com/video
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community
e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
相关型号：
ADS800E
12-Bit, 40 MSPS ADC SE/Diff inputs. Internal References, pin compatible to ADS801/2 28-SSOP -40 to 85
TI
ADS800E/1K
12-Bit, 40 MSPS ADC SE/Diff inputs. Internal References, pin compatible to ADS801/2 28-SSOP -40 to 85
TI
©2020 ICPDF网 联系我们和版权申明