ADS800U [TI]
12-Bit, 40MHz Sampling ANALOG-TO-DIGITAL CONVERTER;
| 型号： | ADS800U |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12-Bit, 40MHz Sampling ANALOG-TO-DIGITAL CONVERTER 光电二极管 转换器 |
| 文件： | 总22页 (文件大小：952K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS800
A
D
S
8
0
0
U
SBAS035B – FEBRUARY 1995 – REVISED FEBRUARY 2005
12-Bit, 40MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
DESCRIPTION
FEATURES
The ADS800 is a low-power, monolithic 12-bit, 40MHz Ana-
log-to-Digital (A/D) converter utilizing a small geometry CMOS
process. This complete converter includes a 12-bit quantizer,
wideband track-and-hold, reference, and three-state outputs.
It operates from a single +5V power supply and can be
configured to accept either differential or single-ended input
signals.
ꢀ LOW POWER: 390mW
ꢀ INTERNAL REFERENCE
ꢀ WIDEBAND TRACK-AND-HOLD: 65MHz
ꢀ SINGLE +5V SUPPLY
APPLICATIONS
The ADS800 employs digital error correction to provide
excellent Nyquist differential linearity performance for de-
manding imaging applications. Its low distortion, high SNR,
and high oversampling capability give it the extra margin
needed for telecommunications, test instrumentation, and
video applications.
ꢀ IF AND BASEBAND DIGITIZATION
ꢀ DIGITAL COMMUNICATIONS
ꢀ ULTRASOUND IMAGING
ꢀ GAMMA CAMERAS
ꢀ TEST INSTRUMENTATION
This high-performance A/D converter is specified over tem-
perature for AC and DC performance at a 40MHz sampling
rate. The ADS800 is available in an SO-28 package.
ꢀ CCD IMAGING
Copiers
Scanners
Cameras
ꢀ VIDEO DIGITIZING
CLK
MSBI
OE
Timing
Circuitry
IN
Pipeline
A/D
Converter
12-Bit
Digital
Data
Error
Correction
Logic
3-State
Outputs
T/H
IN
+3.25V
REFT
CM
REFB
+1.25V
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1995-2005, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper han-
dling and installation procedures can cause damage.
+VS ....................................................................................................... +6V
Analog Input .............................................................. 0V to (+VS + 300mV)
Logic Input ................................................................ 0V to (+VS + 300mV)
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature ..................................................................... +125°C
External Top Reference Voltage (REFT) .................................. +3.4V Max
External Bottom Reference Voltage (REFB).............................. +1.1V Min
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
NOTE: (1) Stresses above these ratings may permanently damage the device.
PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
ADS800U
SO-28
DW
–40°C to +85°C
ADS800U
ADS800U
Rails, 28
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at
www.ti.com.
ELECTRICAL CHARACTERISTICS
At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.
ADS800U
PARAMETER
CONDITIONS
TEMP
MIN
TYP
MAX
UNITS
Resolution
Specified Temperature Range
Operating Temperature Range
12
Bits
°C
°C
TAMBIENT
TAMBIENT
0
–40
+70
+85
ANALOG INPUT
Differential Full-Scale Input Range
Both Inputs,
180° Out-of-Phase
+1.25
+3.25
V
V
Common-Mode Voltage
Analog Input Bandwidth (–3dB)
Small-Signal
+2.25
–20dBFS(1) Input
0dBFS Input
+25°C
+25°C
400
65
MHz
MHz
Full-Power
Input Impedance
1.25 || 4
MΩ || pF
DIGITAL INPUT
Logic Family
Convert Command
TTL/HCT Compatible CMOS
Falling Edge
Start Conversion
ACCURACY(2)
Gain Error
fS = 2.5MHz
+25°C
±0.4
±0.6
±95
0.01
±2.6
0.02
±1.5
±2.5
%
%
Full
Gain Drift
Power-Supply Rejection of Gain
Input Offset Error
ppm/°C
%FSR/%
%
∆ +VS = ±5%
∆ +VS = ±5%
+25°C
Full
+25°C
0.15
±3.5
0.15
Power-Supply Rejection of Offset
%FSR/%
CONVERSION CHARACTERISTICS
Sample Rate
10k
40M
Sample/s
Data Latency
6.5
Convert Cycle
DYNAMIC CHARACTERISTICS
Differential Linearity Error
f = 500kHz
tH = 13ns(3)
+25°C
Full
+25°C
Full
+25°C
Full
±0.6
±0.8
±0.4
±0.5
Tested
±1.9
±1.0
±1.0
LSB
LSB
LSB
LSB
LSB
LSB
f = 12MHz
No Missing Codes
tH = 13ns(3)
Integral Linearity Error at f = 500kHz
Spurious-Free Dynamic Range (SFDR)
f = 500kHz (–1dBFS input)
+25°C
Full
+25°C
Full
65
60
58
55
72
66
61
61
dBFS
dBFS
ꢀdBFS
dBFS
f = 12MHz (–1dBFS input)
NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) To assure
DNL and no missing code performance, see timing diagram footnote 2. (4) IMD is referred to the larger of the two input signals. If referred to the peak envelope
signal (≈0dB), the intermodulation products will be 7dB lower. (5) No “rollover” of bits.
ADS800
2
SBAS035B
www.ti.com
ELECTRICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.
ADS800U
PARAMETER
CONDITIONS
TEMP
MIN
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS (Cont.)
2-Tone Intermodulation Distortion (IMD)(4)
f = 4.4MHz and 4.5MHz (–7dBFS each tone)
+25°C
Full
–63
–62
dBc
dBc
Signal-to-Noise Ratio (SNR)
f = 500kHz (–1dBFS input)
+25°C
Full
+25°C
Full
61
57
61
56
64
63
62
62
dB
dB
dB
dB
f = 12MHz (–1dBFS input)
Signal-to-(Noise + Distortion) (SINAD)
f = 500kHz (–1dBFS input)
+25°C
Full
+25°C
Full
+25°C
+25°C
+25°C
+25°C
+25°C
59
54
56
51
63
64
58
57
0.5
0.1
2
dB
dB
dB
dB
%
degrees
ns
ps rms
ns
f = 12MHz (–1dBFS input)
Differential Gain Error
Differential Phase Error
Aperture Delay Time
Aperture Jitter
NTSC or PAL
NTSC or PAL
7
2
Over-Voltage Recovery Time(5)
1.5x Full-Scale Input
OUTPUTS
Logic Family
Logic Coding
Logic Levels
TTL/HCT Compatible CMOS
SOB or BTC
Logic Selectable
Full
Logic “LO”,
CL = 15pF max
Logic “HI”,
0
0.4
V
V
Full
Full
+2.5
+VS
CL = 15pF max
3-State Enable Time
3-State Disable Time
20
2
40
10
ns
ns
POWER-SUPPLY REQUIREMENTS
Supply Voltage: +VS
Supply Current: +IS
Operating
Operating
Operating
Operating
Operating
Full
+25°C
Full
+25°C
Full
+4.75
+5.0
78
78
390
390
+5.25
93
97
465
485
V
mA
mA
mW
mW
Power Consumption
Thermal Resistance, θJA
SO-28
75
°C/W
NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) To assure
DNL and no missing code performance, see timing diagram footnote 2. (4) IMD is referred to the larger of the two input signals. If referred to the peak envelope
signal (≈0dB), the intermodulation products will be 7dB lower. (5) No “rollover” of bits.
ADS800
SBAS035B
3
www.ti.com
PIN CONFIGURATION
PIN DESCRIPTIONS
PIN
DESIGNATOR DESCRIPTION
Top View
SO
1
2
GND
B1
Ground
Bit 1, Most Significant Bit
3
B2
Bit 2
4
B3
Bit 3
GND
B1
B2
B3
B4
B5
B6
B7
B8
1
2
3
4
5
6
7
8
9
28 GND
27 IN
5
6
7
8
B4
B5
B6
B7
B8
B9
B10
B11
B12
GND
+VS
CLK
+VS
OE
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
26 IN
9
10
11
12
13
14
15
16
17
18
25 GND
24 +VS
23 REFT
22 CM
21 REFB
20 +VS
19 MSBI
18 OE
Bit 12, Least Significant Bit
Ground
+5V Power Supply
Convert Clock Input, 50% Duty Cycle
+5V Power Supply
ADS800
HI: High Impedance State. LO or Floating: Nor-
mal Operation. Internal pull-down resistors.
Most Significant Bit Inversion, HI: MSB inverted
for complementary output. LO or Floating: Straight
output. Internal pull-down resistors.
+5V Power Supply
Bottom Reference Bypass. For external bypass-
ing of internal +1.25V reference.
Common-Mode Voltage. It is derived by (REFT +
REFB)/2.
Top Reference Bypass. For external bypassing
of internal +3.25V reference.
+5V Power Supply
Ground
Input
19
MSBI
B9 10
B10 11
B11 12
B12 13
GND 14
20
21
+VS
REFB
17 +VS
16 CLK
15 +VS
22
23
CM
REFT
24
25
26
27
28
+VS
GND
IN
IN
GND
Complementary Input
Ground
TIMING DIAGRAM
tCONV
tL
tH
Convert
Clock
tD
DATA LATENCY
(6.5 Clock Cycles)
(1)
Hold
“N”
Hold
“N + 1”
Hold
“N + 2”
Hold
“N + 3”
Hold
N + 4
Hold
N + 5
Hold
Track
N + 6”
Track
Track
Track
Track
Track
Track
Track
“
”
“
”
“
Internal
Track-and-Hold
t2
Output
Data
Data Valid
N – 8
Data Valid
N – 7
Data Valid
N – 6
N – 5
N – 4
N – 3
N – 2
N – 1
N
t1
Data Invalid
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tCONV
tL
tH
tD
t1
Convert Clock Period
Clock Pulse LOW
Clock Pulse HIGH
Aperture Delay
Data Hold Time, CL = 0pF
25
12
100µs
ns
ns
ns
ns
ns
ns
12.5
12.5
2
12(2)
3.9
t2
New Data Delay Time, CL = 15pF max
12.5
NOTES: (1) “ ” indicates the portion of the waveform that will stretch out at slower sample rates.
(2) tH must be 13ns minimum if no missing codes is desired only for the conditions of tCONV ≤ 28ns
and fIN < 2MHz.
ADS800
4
SBAS035B
www.ti.com
TYPICAL CHARACTERISTICS
At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
0
–20
–
–40
–
–60
–
–80
–
–100
–120
–1
–1
0
5
10
15
20
Frequency (MHz)
Frequency (MHz)
SPECTRAL PERFORMANCE
–2
–2
–4
–4
–6
–6
–8
–8
–10
–12
–10
–12
0
5
10
15
20
0
5
10
15
20
Frequency (MHz)
Frequency (MHz)
SPECTRAL PERFORMANCE
2-TONE INTERMODULATION
0
–20
0
–2
–40
–4
–60
–6
–80
–8
–100
–120
–10
–12
0
1
2
3
4
5
0
5
10
15
20
Frequency (MHz)
Frequency (MHz)
ADS800
SBAS035B
5
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.
DIFFERENTIAL LINEARITY ERROR
fIN = 500kHz
DIFFERENTIAL LINEARITY ERROR
fIN = 12MHz
2.0
1.0
2.0
1.0
0
–1.0
–2.0
–1.0
–2.0
0
1024
2048
Code
3072
4096
0
1024
2048
Code
3072
4096
SWEPT POWER SFDR
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
100
80
60
40
20
0
80
75
70
65
60
55
50
fIN = 12MHz
SFDR
SNR
–50
–40
–30
–20
–10
0
10
0.1
1
10
Frequency (MHz)
100
Input Amplitude (dBm)
SWEPT POWER SNR
INTEGRAL LINEARITY ERROR
80
60
40
20
0
4.0
fIN = 500kHz
fIN = 12MHz
–4.0
–50
–40
–30
–20
–10
0
10
0
1024
2048
Code
3072
4096
Input Amplitude (dBm)
ADS800
6
SBAS035B
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.
DYNAMIC PERFORMANCE
DYNAMIC PERFORMANCE
vs DIFFERENTIAL FULL-SCALE INPUT RANGE
vs SINGLE-ENDED FULL-SCALE INPUT RANGE
75
70
65
60
55
50
65
60
55
50
45
fIN = 12MHz
SFDR (fIN = 500kHz)
SFDR (fIN = 12MHz)
SNR (fIN = 500kHz)
SNR
SFDR
SNR (fIN = 12MHz)
NOTE: REFTEXT varied,
REFB is fixed at the internal value of +1.25V.
NOTE: REFTEXT varied,
REFB is fixed at the internal value of +1.25V.
2
3
4
1
2
3
4
5
Differential Full-Scale Input Range (Vp-p)
Single-Ended Full-Scale Range (Vp-p)
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
vs TEMPERATURE
SIGNAL-TO-NOISE RATIO vs TEMPERATURE
90
80
70
60
50
80
70
60
50
40
fIN = 500kHz
fIN = 500kHz
fIN = 12MHz
fIN = 12MHz
–25
0
25
50
75
–25
0
25
50
75
Temperature (°C)
Temperature (°C)
SIGNAL-TO-(NOISE + DISTORTION)
vs TEMPERATURE
SUPPLY CURRENT vs TEMPERATURE
70
65
60
55
50
85
80
75
70
fIN = 500kHz
fIN = 12MHz
–25
0
25
50
75
–25
0
25
50
75
Temperature (°C)
Temperature (°C)
ADS800
SBAS035B
7
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.
POWER DISSIPATION vs TEMPERATURE
GAIN ERROR vs TEMPERATURE
0.75
0.25
425
400
375
350
–0.25
–0.75
–1.25
–25
0
25
50
75
–25
0
25
50
75
Temperature (°C)
Temperature (°C)
TRACK-MODE SMALL-SIGNAL INPUT BANDWIDTH
OFFSET ERROR vs TEMPERATURE
1
0
–2.25
–1
–2
–3
–4
–5
–2.5
–2.75
–25
0
25
50
75
10k
100k
1M
10M
100M
1G
Ambient Temperature (°C)
Frequency (Hz)
OUTPUT NOISE HISTOGRAM (NO SIGNAL)
800k
600k
400k
200k
0.0
N – 2
N – 1
N
N + 1
N + 2
Code
ADS800
8
SBAS035B
www.ti.com
Op Amp
Bias
THEORY OF OPERATION
VCM
The ADS800 is a high-speed, sampling A/D converter with
pipelining. It uses a fully differential architecture and digital
error correction to ensure 12-bit resolution. The differential
track-and-hold circuit is shown in Figure 1. The switches are
controlled by an internal clock which has a non-overlapping
2-phase signal, φ1 and φ2. At the sampling time, the input
signal is sampled on the bottom plates of the input capaci-
tors. In the next clock phase, φ2, the bottom plates of the
input capacitors are connected together and the feedback
capacitors are switched to the op amp output. At this time,
the charge redistributes between CI and CH, completing one
track-and-hold cycle. The differential output is a held DC
representation of the analog input at the sample time. The
track-and-hold circuit can also convert a single-ended input
signal into a fully differential signal for the quantizer.
φ1
φ1
CH
φ2
φ2
CI
CI
IN
IN
OUT
OUT
φ1
φ1
φ2
φ1
CH
φ1
φ1
Input Clock (50%)
Op Amp
Bias
VCM
Internal Non-Overlapping Clock
φ1 φ2 φ1
The pipelined quantizer architecture has 11 stages with each
stage containing a 2-bit quantizer and a 2-bit Digital-to-
Analog Converter (DAC), as shown in Figure 2. Each 2-bit
quantizer stage converts on the edge of the sub-clock, which
is twice the frequency of the externally applied clock. The
output of each quantizer is fed into its own delay line to time-
FIGURE 1. Input Track-and-Hold Configuration with Timing
Signals.
IN
Digital Delay
Input
T/H
IN
2-Bit
Flash
2-Bit
DAC
+
STAGE 1
–
Σ
x2
B1 (MSB)
Digital Delay
B2
B3
B4
B5
B6
B7
B8
B9
B10
2-Bit
Flash
2-Bit
DAC
STAGE 2
+
–
Σ
x2
B11
Digital Delay
B12 (LSB)
2-Bit
Flash
2-Bit
DAC
STAGE 10
+
–
Σ
x2
2-Bit
Flash
Digital Delay
STAGE 11
FIGURE 2. Pipeline A/D Converter Architecture.
ADS800
SBAS035B
9
www.ti.com
align it with the data created from the following quantizer
stages. This aligned data is fed into a digital error correction
circuit which can adjust the output data based on the infor-
mation found on the redundant bits. This technique gives the
ADS800 excellent differential linearity and ensures no miss-
ing codes at the 12-bit level.
• For most applications, the clock duty should be set to
50%. However, for applications requiring no missing codes,
a slight skew in the duty cycle will improve DNL perfor-
mance for conversion rates > 35MHz and input frequen-
cies < 2MHz (see Timing Diagram) in the SO package.
For the best performance in the SSOP package, the clock
should be skewed under all input frequencies with conver-
sion rates > 35MHz. A possible method for skewing the
50% duty cycle source is shown in Figure 4.
Since there are two pipeline stages per external clock cycle,
there is a 6.5 clock cycle data latency from the start convert
signal to the valid output data. The output data is available in
Straight Offset Binary (SOB) or Binary Two’s Complement
(BTC) format.
VDD
VDD
IC1, IC2 = ACT04
RV
2kΩ
RV = 217Ω, typical
THE ANALOG INPUT AND INTERNAL REFERENCE
0.1µF
0.1µF
The analog input of the ADS800 can be configured in various
ways and driven with different circuits, depending on the
nature of the signal and the level of performance desired.
The ADS800 has an internal reference that sets the full-scale
input range of the A/D converter. The differential input range
has each input centered around the common-mode of +2.25V,
with each of the two inputs having a full-scale range of
+1.25V to +3.25V. Since each input is 2Vp-p and 180° out-
of-phase with the other, a 4V differential input signal to the
quantizer results. As shown in Figure 3, the positive full-scale
reference (REFT) and the negative full-scale (REFB) are
brought out for external bypassing. In addition, the common-
mode voltage (CM) may be used as a reference to provide
the appropriate offset for the driving circuitry. However, care
must be taken not to appreciably load this reference node.
For more information regarding external references, single-
ended input, and ADS800 drive circuits, refer to the applica-
tions section.
CLKIN
CLKOUT
IC1
IC2
FIGURE 4. Clock Skew Circuit.
DIGITAL OUTPUT DATA
The 12-bit output data is provided at CMOS logic levels. The
standard output coding is Straight Offset Binary (SOB) where
a full-scale input signal corresponds to all “1’s” at the output,
as shown in Table 1. This condition is met with pin 19 “LO”
or Floating due to an internal pull-down resistor. By applying
a logic “HI” voltage to this pin, a Binary Two’s Complement
(BTC) output will be provided where the most significant bit
is inverted. The digital outputs of the ADS800 can be set to
a high-impedance state by driving OE (pin 18) with a logic
“HI”. Normal operation is achieved with pin 18 “LO” or
Floating due to internal pull-down resistors. This function is
provided for testability purposes and is not meant to drive
digital buses directly or be dynamically changed during the
conversion process.
ADS800
+3.25V
REFT
23
0.1µF
2kΩ
To
Internal
CM
22
21
OUTPUT CODE
+2.25V
Comparators
2kΩ
SOB
PIN 19
BTC
PIN 19
HI
REFB
DIFFERENTIAL INPUT(1)
FLOATING or LO
0.1µF
+FS (IN = +3.25V, IN = +1.25V)
+FS – 1LSB
+FS – 2LSB
+3/4 Full-Scale
+1/2 Full-Scale
+1/4 Full-Scale
+1LSB
Bipolar Zero (IN = IN = +2.25V)
–1LSB
–1/4 Full-Scale
111111111111
111111111111
111111111110
111000000000
110000000000
101000000000
100000000001
100000000000
011111111111
011000000000
010000000000
001000000000
000000000001
000000000000
011111111111
011111111111
011111111110
011000000000
010000000000
001000000000
000000000001
000000000000
111111111111
111000000000
110000000000
101000000000
100000000001
100000000000
+1.25V
FIGURE 3. Internal Reference Structure.
CLOCK REQUIREMENTS
The CLK pin accepts a CMOS level clock input. Both the
rising and falling edges of the externally applied clock control
the various interstage conversions in the pipeline. Therefore,
the clock signal’s jitter, rise-and-fall times, and duty cycle can
affect conversion performance.
–1/2 Full-Scale
–3/4 Full-Scale
–FS + 1LSB
–FS (IN = +1.25V, IN = +3.25V)
NOTE: (1) In the single-ended input mode, +FS = +4.25V and –FS = +0.25V.
• Low clock jitter is critical to SNR performance in fre-
quency-domain signal environments.
TABLE I. Coding Table for the ADS800.
• Clock rise-and-fall times should be as short as possible
(< 2ns for best performance).
ADS800
10
SBAS035B
www.ti.com
product performance. The input capacitors, CIN, and the input
resistors, RIN, create a high-pass filter with the lower corner
frequency at fC = 1/(2pRINCIN). The corner frequency can be
reduced by either increasing the value of RIN or CIN. If the
circuit operates with a 50Ω or 75Ω impedance level, the
resistors are fixed and only the value of the capacitor can be
increased. Usually, AC-coupling capacitors are electrolytic or
tantalum capacitors with values of 1µF or higher. It should be
noted that these large capacitors become inductive with
increased input frequency, which could lead to signal ampli-
tude errors or oscillation. To maintain a low AC-coupling
impedance throughout the signal band, a small value (e.g.
1µF) ceramic capacitor could be added in parallel with the
polarized capacitor.
APPLICATIONS
DRIVING THE ADS800
The ADS800 has a differential input with a common-mode of
+2.25V. For AC-coupled applications, the simplest way to
create this differential input is to drive the primary winding of
a transformer with a single-ended input. A differential output
is created on the secondary if the center tap is tied to the
common-mode voltage of +2.25V, as per Figure 5. This
transformer-coupled input arrangement provides good high-
frequency AC performance. It is important to select a trans-
former that gives low distortion and does not exhibit core
saturation at full-scale voltage levels. Since the transformer
does not appreciably load the ladder, there is no need to
buffer the Common-Mode (CM) output in this instance. In
general, it is advisable to keep the current draw from the CM
output pin below 0.5µA to avoid nonlinearity in the internal
reference ladder. A FET input operational amplifier such as
the OPA130 can provide a buffered reference for driving
external circuitry. The analog IN and IN inputs should be
bypassed with 22pF capacitors to minimize track-and-hold
glitches and to improve high input frequency performance.
Capacitors CSH1 and CSH2 are used to minimize current
glitches resulting from the switching in the input track-and-
hold stage and to improve signal-to-noise performance. These
capacitors can also be used to establish a low-pass filter and
effectively reduce the noise bandwidth. In order to create a
real pole, resistors RSER1 and RSER2 were added in series
with each input. The cutoff frequency of the filter is deter-
mined by fC = 1/(2pRSER • (CSH + CADC)) where RSER is the
resistor in series with the input, CSH is the external capacitor
from the input to ground, and CADC is the internal input
capacitance of the A/D converter (typically 4pF).
Figure 6 illustrates another possible low-cost interface circuit
which utilizes resistors and capacitors in place of a trans-
former. Depending on the signal bandwidth, the component
values should be carefully selected in order to maintain the
Resistors R1 and R2 are used to derive the necessary
common-mode voltage from the buffered top and bottom
references. The total load of the resistor string should be
selected so that the current does not exceed 1mA. Although
the circuit in Figure 6 uses two resistors of equal value so
that the common-mode voltage is centered between the top
and bottom reference (+2.25V), it is not necessary to do so.
In all cases the center point, VCM, should be bypassed to
ground in order to provide a low-impedance AC ground.
22 CM
0.1µF
26
27
IN
IN
AC Input
Signal
ADS800
22pF
22pF
Mini-Circuits
TT1-6-KK81
or equivalent
If the signal needs to be DC coupled to the input of the
ADS800, an operational amplifier input circuit is required. In the
differential input mode, any single-ended signal must be modi-
fied to create a differential signal. This can be accomplished by
FIGURE 5. AC-Coupled Single-Ended to Differential Drive
Circuit Using a Transformer.
C1
0.1µF
R1
(6kΩ)
(1)
CIN
0.1µF
RSER1
+3.25V
Top Reference
49.9Ω
IN
CSH1
22pF
RIN1
25Ω
R3
1kΩ
ADS8xx
VCM
C2
RIN2
25Ω
0.1µF
IN
CSH2
(1)
+1.25V
Bottom Reference
RSER2
CIN
0.1µF
22pF
R2
(6kΩ)
49.9Ω
C3
0.1µF
NOTE: (1) Indicates optional component.
FIGURE 6. AC-Coupled Differential Input Circuit.
ADS800
SBAS035B
11
www.ti.com
using two operational amplifiers, one in the noninverting mode
for the input and the other amplifier in the inverting mode for the
complementary input. The low distortion circuit in Figure 7 will
provide the necessary input shifting required for signals cen-
tered around ground. It also employs a diode for output level
shifting to ensure a low distortion +3.25V output swing. Other
amplifiers can be used in place of the OPA842s if the lowest
distortion is not necessary. If output level shifting circuits are
not used, care must be taken to select operational amplifiers
that give the necessary performance when swinging to +3.25V
with a ±5V supply operational amplifier.
age, as shown in Figure 8. This configuration will result in
increased even-order harmonics, especially at higher input
frequencies. However, this tradeoff may be quite acceptable
for time-domain applications. The driving amplifier must give
adequate performance with a +0.25V to +4.25V output swing
in this case.
EXTERNAL REFERENCES AND ADJUSTMENT
OF FULL-SCALE RANGE
The internal reference buffers are limited to approximately
1mA of output current. As a result, these internal +1.25V and
+3.25V references may be overridden by external references
that have at least 18mA (at room temperature) of output drive
capability. In this instance, the common-mode voltage will be
The ADS800 can also be configured with a single-ended
input full-scale range of +0.25V to +4.25V by tying the
complementary input to the common-mode reference volt-
+5V
604Ω
+5V
301Ω
BAS16(1)
Optional
High Impedance
Input Amplifier
27 IN
301Ω
OPA842
301Ω
2.49kΩ
0.1µF
604Ω
22pF
+5V(2)
0.1µF
+5V
–5V
DC-Coupled
Input Signal
ADS800
OPA842
604Ω
49.9Ω
+2.25V
OPA130
2.49kΩ
22 CM
+5V
–5V
+5V
24.9Ω
301Ω
Input Level
Shift Buffer
301Ω
BAS16(1)
26 IN
OPA842
22pF
0.1µF
–5V
604Ω
NOTES: (1) A Philips BAS16 diode or equivalent
may be used. (2) Supply bypassing not shown.
301Ω
FIGURE 7. A Low Distortion DC-Coupled, Single-Ended to Differential Input Driver Circuit.
22 CM
0.1µF
ADS800
Single-Ended
Input Signal
26 IN
27 IN
22pF
Full Scale = +0.25V to +4.25V with internal references.
FIGURE 8. Single-Ended Input Connection.
ADS800
12
SBAS035B
www.ti.com
set halfway between the two references. This feature can be
used to adjust the gain error, improve gain drift, or to change
the full-scale input range of the ADS800. Changing the full-
scale range to a lower value has the benefit of easing the
swing requirements of external input drive amplifiers. The
external references can vary as long as the value of the
external top reference (REFTEXT) is less than or equal to
The circuit in Figure 10 works completely on a single +5V
supply. As a reference element, it uses the micro-power
reference REF1004-2.5, which is set to a quiescent current
of 0.1mA. Amplifier A2 is configured as a follower to buffer the
+1.25V generated from the resistor divider. To provide the
necessary current drive, a pull-down resistor, RP, is added.
Amplifier A1 is configured as an adjustable gain stage, with
a range of approximately 1 to 1.32. The pull-up resistor
again relieves the op amp from providing the full current
drive. The value of the pull-up/down resistors is not critical
and can be varied to optimize power consumption. The
need for pull-up, pull-down resistors depends only on the
drive capability of the selected drive amplifiers and thus can
be omitted.
+3.4V, the value of the external bottom reference (REFBEXT
)
is greater than or equal to +1.1V, and the difference between
the external references are greater than or equal to 1.5V.
For the differential configuration, the full-scale input
range will be set to the external reference values that are
selected. For the single-ended mode, the input range is
2 • (REFTEXT – REFBEXT), with the common-mode being
centered at (REFTEXT + REFBEXT)/2. Refer to the typical
characteristics for “Expected Performance vs Full-Scale In-
put Range”.
–541
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
+5V
0.1µF
0.1µF
+VS
GND
LSB
15
16
17
18
19
20
21
22
23
24
25
26
27
28
14
13
12
11
10
9
CLK
+VS
Ext
Clk
1
Dir
G+
R1
50Ω
19
OE
MSBI
+VS
–541
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
0.1µF
0.1µF
REFB
CM
8
ADS800
7
REFT
+VS
6
0.1µF
5
0.1µF
0.1µF
AC Input
Signal
GND
IN
4
3
R2
50Ω
IN
MSB
GND
2
(1)
GND
22pF
1
1
22pF
Mini-Circuits
TT1-6-KK81
or equivalent
Dir
G+
19
NOTE: (1) All capacitors should be located as close to the pins as the manufacturing
process will allow. Ceramic X7R surface-mount capacitors or equivalent are recommended.
FIGURE 9. ADS800 Interface Schematic with AC-Coupling and External Buffers.
ADS800
SBAS035B
13
www.ti.com
+5V
RP
220Ω
A
Top
1
1/2
OPA2234
Reference
+5V
+2.5V to +3.25V
2kΩ
10kΩ
6.2kΩ
10kΩ
REF1004
10kΩ(1)
A
+2.5V
0.1µF
2
+1.25V
1/2
OPA2234
Bottom
Reference
10kΩ
RP
10kΩ(1)
220Ω
NOTE: (1) Use parts alternatively for adjustment capability.
FIGURE 10. Optional External Reference to Set the Full-Scale Range Utilizing a Dual, Single-Supply Op Amp.
HP8022A pulse generator for the A/D converter clock, gives
PC BOARD LAYOUT AND BYPASSING
excellent results. Low-pass filtering (or bandpass filtering) of
test signals is absolutely necessary to test the low distortion of
the ADS800. Using a signal amplitude slightly lower than full-
scale will allow a small amount of “headroom” so that noise or
DC offset voltage will not over-range the A/D converter and
cause clipping on signal peaks.
A well-designed, clean PC board layout will assure proper
operation and clean spectral response. Proper grounding
and bypassing, short lead lengths, and the use of ground
planes are particularly important for high-frequency circuits.
Multilayer PC boards are recommended for best perfor-
mance but if carefully designed, a two-sided PC board with
large, heavy ground planes can give excellent results. It is
recommended that the analog and digital ground pins of the
ADS800 be connected directly to the analog ground plane.
In our experience, this gives the most consistent results. The
A/D converter power-supply commons should be tied to-
gether at the analog ground plane. Power supplies should
be bypassed with 0.1µF ceramic capacitors as close to the
pin as possible.
DYNAMIC PERFORMANCE DEFINITIONS
1.
2.
3.
Signal-to-Noise-and-Distortion Ratio (SINAD):
Sinewave SignalPower
10 log
Noise + Harmonic Power first 15 harmonics
(
)
Signal-to-Noise Ratio (SNR):
Sinewave SignalPower
10 log
NoisePower
Intermodulation Distortion (IMD):
DYNAMIC PERFORMANCE TESTING
The ADS800 is a high performance converter and careful
attention to test techniques is necessary to achieve accurate
results. Highly accurate phase-locked signal sources allow
high resolution FFT measurements to be made without using
data windowing functions. A low jitter signal generator such as
the HP8644A for the test signal, phase-locked with a low jitter
Highest IMDProduct Power to 5th − order
(
)
10 log
Sinewave SignalPower
IMD is referenced to the larger of the test signals, f1 or f2. Five
“bins” either side of peak are used for calculation of funda-
mental and harmonic power. The “0” frequency bin (DC) is
not included in these calculations as it is of little importance
in dynamic signal processing applications.
ADS800
14
SBAS035B
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ADS800E
ADS800E/1K
ADS800U
OBSOLETE
OBSOLETE
ACTIVE
SSOP
SSOP
SOIC
DB
28
28
28
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 85
-40 to 85
-40 to 85
DB
DW
20
1000
1000
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ADS800U
ADS800U/1K
ADS800U/1KG4
ADS800UG4
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
DW
DW
DW
28
28
28
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
ADS800U
ADS800U
ADS800U
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS800U/1K
SOIC
DW
28
1000
330.0
32.4
11.35 18.67
3.1
16.0
32.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 28
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 55.0
ADS800U/1K
1000
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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