ADS804 [TI]

12 位、10MSPS 模数转换器 (ADC);


型号：	ADS804
厂家：	TEXAS INSTRUMENTS
描述：	12 位、10MSPS 模数转换器 (ADC) 转换器模数转换器
文件：	总18页 (文件大小：913K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS804

ADS804E

SBAS068B – JANUARY 1997 – REVISED AUGUST 2002

12-Bit, 10MHz Sampling

ANALOG-TO-DIGITAL CONVERTER

FEATURES

APPLICATIONS

● HIGH SFDR: 80dB at NYQUIST

● IF AND BASEBAND DIGITIZATION

● HIGH SNR: 69dB

● CCD IMAGING

● LOW POWER: 180mW

● LOW DLE: ±0.3LSB

● SCANNERS

● TEST INSTRUMENTATION

● FLEXIBLE INPUT RANGE

● OVERRANGE INDICATOR

of 0.09LSBs rms giving superior imaging performance. There

is also a capability to set the input range in between the 2Vp-

p and 5Vp-p input ranges or to use external reference. The

ADS804 also provides an over-range indicator flag to indi-

cate an input range that exceeds the full-scale input range of

the converter. This flag can be used to reduce the gain of the

front end gain-ranging circuitry.

DESCRIPTION

The ADS804 is a high-speed, high dynamic range, 12-bit,

pipelined Analog-to-Digital (A/D) converter. This converter

includes a high-bandwidth track-and-hold that gives excel-

lent spurious performance up to and beyond the Nyquist

rate. This high-bandwidth, linear track-and-hold minimizes

harmonics and has low jitter, leading to excellent SNR

performance. The ADS804 is also pin-compatible with the

5MHz ADS803 and the 20MHz ADS805.

The ADS804 employs digital error correction techniques to

provide excellent differential linearity for demanding imaging

applications. Its low distortion and high SNR give the extra

margin needed for communications, medical imaging, video,

and test instrumentation applications. The ADS804 is avail-

able in a SSOP-28 package.

The ADS804 provides an internal reference and can be

programmed for a 2Vp-p input range for the best spurious

performance and ease of driving. Alternatively, the 5Vp-p

input range can be used for the lowest input referred noise

+V_S

CLK

VDRV

ADS804

Timing Circuitry

V_IN

12-Bit

Pipelined

A/D Converter Core

Error

Correction

Logic

3-State

Outputs

•

T&H

D11

(Opt.)

OVR

Reference Ladder

and Driver

Reference and

Mode Select

REFT

V_REF

SEL

REFB

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

www.ti.com

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-

ments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

+V_S, VDRV ........................................................................................... +6V

Analog Input .......................................................... (–0.3V) to (+V_S+ 0.3V)

Logic Input ............................................................ (–0.3V) to (+V_S+ 0.3V)

Case Temperature ......................................................................... +100°C

Junction Temperature .................................................................... +150°C

Storage Temperature ..................................................................... +150°C

NOTE: (1) Stresses above these ratings may cause permanent damage.

Exposure to absolute maximum conditions for extended periods may degrade

device reliability.

ESD damage can range from subtle performance degradation

tocompletedevicefailure. Precisionintegratedcircuitsmaybe

more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

PACKAGE/ORDERING INFORMATION

SPECIFIED

PACKAGE

DESIGNATOR⁽¹⁾

TEMPERATURE

RANGE

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

MEDIA, QUANTITY

PRODUCT

PACKAGE-LEAD

ADS804

SSOP-28

–40°C to +85°C

ADS804E

Rails, 48

ADS804E/1K

Tape and Reel, 1000

NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.

ELECTRICAL CHARACTERISTICS

At T_A= full specified temperature range, V_S= +5V, specified input range = 1.5V to 3.5V, single-ended input, and sampling rate = 5MHz, unless otherwise specified.

ADS804E

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

RESOLUTION

Bits

SPECIFIED TEMPERATURE RANGE

–40 to +85

°C

CONVERSION CHARACTERISTICS

Sample Rate

Data Latency

10k

10M

Samples/s

Clk Cycles

ANALOG INPUT

Single-Ended Input Range

Single-Ended Input Range (Optional)

Common-Mode Voltage

Input Impedance

1.5

3.5

+2.5

1.25 || 16

270

MΩ || pF

MHz

Track-Mode Input Bandwidth

–3dBFS Input

DYNAMIC CHARACTERISTICS

Differential Linearity Error (Largest Code Error)

f = 500kHz

±0.3

±0.75

LSB

No Missing Codes

Tested

Spurious-Free Dynamic Range⁽¹⁾

f = 4.8MHz

2-Tone Intermodulation Distortion⁽³⁾

f = 3.5MHz and 4.0MHz (–7dBFS each tone)

Signal-to-Noise Ratio (SNR)

f = 4.8MHz

Signal-to-(Noise + Distortion) (SINAD)

f = 4.8MHz

Effective Number of Bits at 4.8MHz⁽⁴⁾

Input Referred Noise

dBFS

dBc

66.5

dBFS

0.09

0.23

dBFS

Bits

LSBs rms

0V to 5V Input

1.5V to 3.5V Input

Integral Nonlinearity Error

f = 500kHz

Aperture Delay Time

Aperture Jitter

Over-Voltage Recovery Time

Full-Scale Step Acquisition Time

±1

±2

LSB

ps rms

1.5 • FS Input

ADS804

SBAS068B

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ELECTRICAL CHARACTERISTICS (Cont.)

At T_A= full specified temperature range, V_S= +5V, specified single-ended input range = 1.5V to 3.5V, and sampling rate = 10MHz, unless otherwise specified.

ADS804E

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

DIGITAL INPUTS

Logic Family

CMOS Compatible

Convert Command

Start Conversion

Rising Edge of Convert Clock

High Level Input Current (V_IN= 5V)⁽⁵⁾

Low Level Input Current (V_IN= 0V)

High Level Input Voltage

Low Level Input Voltage

Input Capacitance

100

µA

+3.5

+1.0

DIGITAL OUTPUTS

Logic Family

Convert Command

Output Voltages, V_DRV= +5V

Low Level

CMOS/TTL Compatible

Straight Offset Binary

I_OL= 50µA

+0.1

+0.4

High Level

Low Level

High Level

_OH= 50µA

±4.6

±2.4

I_OL= 1.6mA

I_OH= 0.5mA

Output Voltages, V_DRV= +3V

Low Level

High Level

I_OL= 50µA

+0.1

I_OH= 50µA

+2.5

3-State Enable Time

3-State Disable Time

Output Capacitance

OE = L

OE = H

ACCURACY (5Vp-p Input Range)

Zero Error (Referred to –FS)

Zero Error Drift

f_S= 2.5MHz

At 25°C

0.2

±5

±1.5

±2.0

±1.5

%FS

ppm/°C

%FS

ppm/°C

%FS

ppm/°C

kΩ

Gain Error⁽⁶⁾

At 25°C

Gain Error Drift⁽⁶⁾

±15

Gain Error⁽⁷⁾

Gain Error Drift⁽⁷⁾

±15

1.6

Power-Supply Rejection of Gain

Reference Input Resistance

Internal Voltage Reference Tolerance (V_REF= 2.5V)

Internal Voltage Reference Tolerance (V_REF= 1.0V)

∆V_S= ±5%

At 25°C

±35

±14

POWER-SUPPLY REQUIREMENTS

Supply Voltage: +V_S

Supply Current: +I_S

+4.7

+5.0

180

+5.3

200

Power Dissipation

Thermal Resistance, θ_JA

SSOP-28

°C/W

NOTES: (1) Spurious-Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to full-scale. (3) 2-tone intermodulation

distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the 2-tone fundamental envelope.

(4) Effective number of bits (ENOB) is defined by (SINAD – 1.76)/6.02. (5) Internal 50kΩ pull-down resistor. (6) Includes internal reference. (7) Excludes internal

reference.

ADS804

SBAS068B

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PIN DESCRIPTIONS

PIN CONFIGURATION

DESIGNATOR

DESCRIPTION

Top View

SSOP

OVR

Over-Range Indicator (See Application

Section)

Data Bit 1(D11) (MSB)

Data Bit 2 (D10)

Data Bit 3 (D9)

OVR

28 VDRV

27 +V_S

26 GND

25 IN

Data Bit 4 (D8)

Data Bit 5 (D7)

Data Bit 6 (D6)

Data Bit 7 (D5)

Data Bit 8 (D4)

Data Bit 9 (D3)

B10

B11

B12

CLK

Data Bit 10 (D2)

Data Bit 11 (D1)

Data Bit 12 (D0) (LSB)

24 GND

23 IN

Convert Clock Input

22 REFT

21 CM

Output Enable. H = High Impedance State.

L = Low or floating, normal operation

(Internal pull-down resistor).

+5V Supply

ADS804

20 REFB

19 V_REF

18 SEL

17 GND

16 +V_S

15 OE

+V_S

GND

SEL

Ground

B9 10

B10 11

B11 12

B12 13

CLK 14

Input Range Select (See Application

Section)

V_REF

REFB

Reference Voltage Select (I/O)

Bottom Reference

Common-Mode Voltage

Top Reference

Analog Input (–)

Ground

REFT

GND

Analog Input (+)

GND

+V_S

Ground

+5V Supply

VDRV

Output Driver Voltage (See Application

Section)

TIMING DIAGRAM

N + 2

N + 1

N + 4

N + 3

Analog In

N + 7

N + 5

N + 6

t_L

t_H

t_D

t_CONV

Clock

6 Clock Cycles

N – 4 N – 3

t₂

Data Out

N – 6

N – 5

N – 2

N – 1

N + 1

Data Invalid

t₁

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

t_CONV

t_L

t_H

t_D

t₁

Convert Clock Period

Clock Pulse LOW

Clock Pulse HIGH

100

100µs

Aperture Delay

Data Hold Time, C_L= 0pF

New Data Delay Time, C_L= 15pF max

3.9

t₂

ADS804

SBAS068B

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TYPICAL CHARACTERISTICS

At T_A= full specified temperature range, V_S= +5V, specified single-ended input range = 1.5V to 3.5V, and sampling rate = 10MHz, unless otherwise specified.

SPECTRAL PERFORMANCE

f_IN= 500kHz

SPECTRAL PERFORMANCE

f_IN= 4.8MHz

–20

–40

–60

–80

–100

–120

–100

–120

1.0

2.0

3.0

4.0

5.0

1.0

2.0

3.0

4.0

5.0

Frequency (MHz)

2-TONE INTERMODULATION

DIFFERENTIAL LINEARITY ERROR

f_IN= 4.8MHz

–20

1.0

0.5

f₁= 3.5MHz at –7dB

₂= 4MHz at –7dB

IMD (3) = –76dBc

–40

–60

–80

–0.5

–1.0

–100

–120

1.25

2.5

Frequency (MHz)

3.75

5.0

1024

2048

3072

4096

Output Code

INTEGRAL LINEARITY ERROR

SWEPT POWER SFDR

4.0

2.0

100

f_IN= 500kHz

f_IN= 4.8MHz

dBFS

dBc

–2.0

–4.0

1024

2048

3072

4096

–60

–50

–40

–30

–20

–10

Output Code

Input Amplitude (dBFS)

ADS804

SBAS068B

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TYPICAL CHARACTERISTICS (Cont.)

At T_A= full specified temperature range, V_S= +5V, specified single-ended input range = 1.5V to 3.5V, and sampling rate = 10MHz, unless otherwise specified.

DYNAMIC PERFORMANCE vs INPUT FREQUENCY

(Differential Input, V_IN= 5Vp-p)

DYNAMIC PERFORMANCE vs INPUT FREQUENCY

SFDR

SNR

0.1

–50

100

Frequency (MHz)

SPURIOUS-FREE DYNAMIC RANGE

vs TEMPERATURE

DIFFERENTIAL LINEARITY vs TEMPERATURE

f_IN= 4.8MHz

0.40

0.35

0.30

0.25

f_IN= 500kHz

f_IN= 4.8MHz

f_IN= 500kHz

–25

–50

–25

100

Temperature (°C)

SIGNAL-TO-(NOISE + DISTORTION)

vs TEMPERATURE

SIGNAL-TO-NOISE RATIO vs TEMPERATURE

f_IN= 500kHz

f_IN= 4.8MHz

–50

–25

100

–25

Temperature (°C)

ADS804

SBAS068B

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TYPICAL CHARACTERISTICS (Cont.)

At T_A= full specified temperature range, V_S= +5V, specified single-ended input range = 1.5V to 3.5V, and sampling rate = 10MHz, unless otherwise specified.

POWER DISSIPATION vs TEMPERATURE

OUTPUT NOISE HISTOGRAM (DC INPUT)

185

180

175

170

800

600

400

200

–50

–25

100

N – 2

N – 1

N + 1

N + 2

Temperature (°C)

Code

OUTPUT NOISE HISTOGRAM

(DC Input, V_IN= 5Vp-p Range)

800

600

400

200

N – 2

N – 1

N + 1

N + 2

Code

ADS804

SBAS068B

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configurations. This will decouple the op amp’s output from

the capacitive load and avoid gain peaking, which can result

in increased noise. For best spurious and distortion perfor-

mance, the resistor value should be kept below 100Ω.

Furthermore, the series resistor together with the 100pF

capacitor establish a passive low-pass filter, limiting the

bandwidth for the wideband noise thus, help improving the

SNR performance.

APPLICATION INFORMATION

DRIVING THE ANALOG INPUT

The ADS804 allows its analog inputs to be driven either

single-ended or differentially. The focus of the following

discussion is on the single-ended configuration. Typically, its

implementation is easier to achieve, and the rated specifica-

tions for the ADS804 are characterized using the single-

ended mode of operation.

DC-COUPLED WITHOUT LEVEL SHIFT

AC-COUPLED INPUT CONFIGURATION

In some applications the analog input signal may already be

biased at a level which complies with the selected input

range and reference level of the ADS804. In this case, it is

only necessary to provide an adequately low source imped-

ance to the selected input, IN or IN. Always consider wideband

op amps since their output impedance will stay low over a

wide range of frequencies. For those applications requiring

the driving amplifier to provide a signal amplification, with a

gain ≥ 3, consider using the decompensated voltage feed-

back op amp OPA643.

Given in Figure 1 is the circuit example of the most common

interface configuration for the ADS804. With the V_REFpin

connected to the SEL pin, the full-scale input range is defined

to be 2Vp-p. This signal is ac-coupled in single-ended form

to the ADS804 using the low distortion voltage- feedback

amplifier OPA642. As is generally necessary for single-

supply components, operating the ADS804 with a full-scale

input signal swing requires a level-shift of the amplifier’s

zero-centered analog signal to comply with the A/D convert-

ers input range requirements. Using a DC blocking capacitor

between the output of the driving amplifier and the converter’s

input, a simple level-shifting scheme can be implemented. In

this configuration, the top and bottom references (REFT,

REFB) provide an output voltage of +3V and +2V, respec-

tively. Here, two resistor pairs (2 • 2kΩ) are used to create a

common-mode voltage of approximately +2.5V to bias the

inputs of the ADS804 (IN, IN) to the required DC voltage.

DC-COUPLED WITH LEVEL SHIFT

Several applications may require that the bandwidth of the

signal path include DC, in which case the signal has to be

DC-coupled to the A/D converter. In order to accomplish this,

the interface circuit has to provide a DC-level shift. See the

circuit of Figure 2 which employs an op amp, to sum the

ground-centered input signal with a required DC offset. The

ADS804 typically operates with a +2.5V common-mode volt-

age, which is established at the center tap of the ladder and

connected to the IN input of the converter. Amplifier A1

operates in inverting configuration. Here resistors R₁and

R₂set the DC-bias level for A1. Because of the op amp’s

noise gain of +2V/V, assuming R_F= R_IN, the DC offset

voltage applied to its noninverting input has to be divided

down to +1.25V, resulting in a DC output voltage of +2.5V.

An advantage of ac-coupling is that the driving amplifier still

operates with a ground-based signal swing. This will keep

the distortion performance at its optimum since the signal

swing stays within the linear region of the op amp and

sufficient headroom to the supply rails can be maintained.

Consider using the inverting gain configuration to eliminate

CMR induced errors of the amplifier. The addition of a small

series resistor (R_S) between the output of the op amp and the

input of the ADS804 will be beneficial in almost all interface

+5V –5V

REFT

(+3V)

2kΩ

R_S

24.9Ω

2Vp-p 0.1µF

V_IN

+V_IN

OPA642

100pF

–V_IN

R_F

402Ω

ADS804

R_G

402Ω

+2.5V_DC

0.1µF

(+2V) (+1V)

2kΩ

SEL

REFB VREF

FIGURE 1. AC-Coupled Input Configuration for 2Vp-p Input Swing and Common-Mode Voltage at +2.5V Derived from Internal

Top and Bottom Reference.

ADS804

SBAS068B

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R_F

REFT

R_IN

+1V

2kΩ

+V_S

R_S

24.9Ω

V_IN

OPA691

–1V

2Vp-p

100pF

ADS804

R₁

R₂

+V_S

+2.5V

0.1µF

10µF

0.1µF

(+1V)

REFB

V_REF

SEL

2kΩ

NOTE: R_F= R_IN, G = –1

FIGURE 2. DC-Coupled, Single-Ended Input Configuration with DC-Level Shift.

DC voltage differences between the IN and IN inputs of the

ADS804 effectively will produce an offset, which can be

corrected for by adjusting the values of resistors R₁and R₂.

The bias current of the op amp may also result in an

R_G

0.1µF

22Ω

undesired offset. The selection criteria of the appropriate op

amp should include the input bias current, output voltage

1:n

V_IN

100pF

swing, distortion, and noise specification. Note that in this

example the overall signal phase is inverted. To re-establish

the original signal polarity it is always possible to interchange

the IN and IN connections.

R_T

ADS804

22Ω

100pF

SINGLE-ENDED-TO-DIFFERENTIAL

CONFIGURATION (TRANSFORMER COUPLED)

4.7µF

0.1µF

In order to select the best suited interface circuit for the

ADS804, the performance requirements must be known. If

an ac-coupled input is needed for a particular application, the

next step is to determine the method of applying the signal;

FIGURE 3. Transformer-Coupled Input.

either single-ended or differentially. The differential input

configuration may provide a noticeable advantage of achiev-

ing good SFDR performance based on the fact that in the

differential mode, the signal swing can be reduced to half of

the swing required for single-ended drive. Secondly, by

driving the ADS804 differentially, the even-order harmonics

will be reduced. Figure 3 shows the schematic for the

suggested transformer-coupled interface circuit. The resistor

across the secondary side (R_T) should be set to get an input

impedance match (e.g., R_T= n²• R_G).

gain for the internal reference buffer. For more design flexibil-

ity, the internal reference can be shut off and an external

reference voltage used. Table I provides an overview of the

possible reference options and pin configurations.

INPUT

FULL-SCALE

RANGE

REQUIRED

V_REF

MODE

CONNECT

Internal

2Vp-p

5Vp-p

+1V

SEL

V_REF

GND

+2.5V

REFERENCE OPERATION

2V ≤ FSR < 5V

FSR = 2 • V_REF

1V < V_REF< 2.5V

V_REF= 1 + (R₁/R₂)

R₁

R₂

V_REFand SEL

SEL and Gnd

Integrated into the ADS804 is a bandgap reference circuit

including logic that provides either a +1V or +2.5V reference

output, by simply selecting the corresponding pin-strap con-

figuration. Different reference voltages can be generated by

the use of two external resistors, which will set a different

External

1V < FSR < 5V

0.5V < V_REF< 2.5V

SEL

+V_S

V_REF

Ext. V_REF

TABLE I. Selected Reference Configuration Examples.

ADS804

SBAS068B

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A simple model of the internal reference circuit is shown in

Figure 4. The internal blocks are a 1V-bandgap voltage

reference, buffer, the resistive reference ladder, and the

drivers for the top and bottom reference which supply the

necessary current to the internal nodes. As shown, the

output of the buffer appears at the V_REFpin. The full-scale

input span of the ADS804 is determined by the voltage at

ADS804

REFT

REFB

VREF

0.1µF

_REF, according to equation (1):

10µF

Full-Scale Input Span = 2 • V_REF

(1)

0.1µF

Note that the current drive capability of this amplifier is limited

to about 1mA and should not be used to drive low loads. The

programmable reference circuit is controlled by the voltage

applied to the select pin (SEL). Refer to Table I for an

overview.

FIGURE 5. Recommended Reference Bypassing Scheme.

The top reference (REFT) and the bottom reference (REFB)

are brought out mainly for external bypassing. For proper

operation with all reference configurations, it is necessary to

provide solid bypassing to the reference pins in order to keep

the clock feedthrough to a minimum. Figure 5 shows the

recommended decoupling network.

REFT

0.1µF

R₁

In addition, the common-mode voltage (CMV) may be used

as a reference level to provide the appropriate offset for the

driving circuitry. However, care must be taken not to appre-

ciably load this node, which is not buffered and has a high

impedance. An alternate method of generating a common-

mode voltage is given in Figure 6. Here, two external preci-

sion resistors (tolerance 1% or better) are located between

the top and bottom reference pins. The common-mode level

will appear at the midpoint. The output buffers of the top and

bottom reference are designed to supply approximately 2mA

of output current.

CMV

ADS804

R₂

REFB

0.1µF

FIGURE 6. Alternative Circuit to Generate Common-Mode

Voltage.

Disable

Switch

SEL

V_REF

1V_DC

to A/D

Converter

REFT

Resistor Network

and Switches

800Ω

Bandgap

and Logic

Reference

Driver

800Ω

REFB

to A/D

Converter

ADS804

FIGURE 4. Equivalent Reference Circuit.

ADS804

SBAS068B

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EXTERNAL REFERENCE OPERATION

SELECTING THE INPUT RANGE AND

REFERENCE

Depending on the application requirements, it might be

advantageous to operate the ADS804 with an external refer-

ence. This may improve the DC accuracy if the external

reference circuitry is superior in its drift and accuracy. To use

the ADS804 with an external reference, the user must

disable the internal reference (as shown in Figure 10). By

connecting the SEL pin to +V_S, the internal logic will shut

down the internal reference. At the same time, the output of

the internal reference buffer is disconnected from the V_REF

pin, which now must be driven with the external reference.

Note that a similar bypassing scheme should be maintained

Figures 7 through 9 show a selection of circuits for the most

common input ranges when using the internal reference of

the ADS804. All examples are for single-ended input and

operate with a nominal common-mode voltage of +2.5V.

V_IN

as described for the internal reference operation.

ADS804

V_REF

SEL

4.5V

+2.5V

V_IN

0.5V

ADS804

+2.5V ext.

0.1µF

FIGURE 7. Internal Reference with 0V to 5V Input Range.

REF1004

+2.5V

V_REF

SEL

+5V

10µF

1.24kΩ

+2V_DC

3.5V

V_IN

4.99kΩ

1.5V

ADS804

+2.5V Ext.

FIGURE 10. External Reference, Input Range 0.5V to 4.5V

(4Vp-p), with +2.5V Common-Mode Voltage.

V_REF

+1V

SEL

DIGITAL INPUTS AND OUTPUTS

Over-Range (OVR)

FIGURE 8. Internal Reference with 1.5V to 3.5V Input Range.

One feature of the ADS804 is its ‘Over-Range’ digital output

(OVR). This pin can be used to monitor any out-of-range

condition, which occurs every time the applied analog input

voltage exceeds the input range (set by V_REF). The OVR

output is LO when the input voltage is within the defined input

range. It becomes HI when the input voltage is beyond the

input range. This is the case when the input voltage is either

below the bottom reference voltage or above the top refer-

ence voltage. OVR will remain active until the analog input

returns to its normal signal range and another conversion is

completed. Using the MSB and its complement in conjunc-

tion with OVR a simple clue logic can be built that detects the

over-range and under-range conditions, (see Figure 11). It

should be noted that OVR is a digital output which is updated

along with the bit information corresponding to the particular

sampling incidence of the analog signal. Therefore, the OVR

data is subject to the same pipeline delay (latency) as the

digital data.

V_IN

ADS804

+2.5V Ext.

V_REF

SEL

R₁

5kΩ

R₁

R₂

+1.5V

_REF= 1V 1 +

R₂

10kΩ

FSR = 2 • V_REF

FIGURE 9. Internal Reference with 1V to 4V Input Range.

ADS804

SBAS068B

www.ti.com

provide the added benefit of isolating the ADS804 from any

digital noise activities on the bus coupling back high fre-

quency noise. In addition, resistors in series with each data

line may help maintain the ac performance of the ADS804.

Their use depends on the capacitive loading seen by the

converter. Values in the range of 100Ω to 200Ω will limit the

instantaneous current the output stage has to provide for

recharging the parasitic capacitances, as the output levels

change from LO-to-HI or HI-to-LO.

MSB

OVR

Over = HI

Under = HI

GROUNDING AND DECOUPLING

Proper grounding and bypassing, short lead length, and the

use of ground planes are particularly important for high-

frequency designs. Multi-layer PC boards are recommended

for best performance since they offer distinct advantages like

minimizing ground impedance, separation of signal layers by

ground layers, etc. It is recommended that the analog and

digital ground pins of the ADS804 be joined together at the

IC and be connected only to the analog ground of the

system.

FIGURE 11. External Logic for Decoding Under- and Over-

range Conditions.

CLOCK INPUT REQUIREMENTS

Clock jitter is critical to the SNR performance of high speed,

high resolution A/D converters. It leads to aperture jitter (t_A)

which adds noise to the signal being converted. The ADS804

samples the input signal on the rising edge of the CLK input.

Therefore, this edge should have the lowest possible jitter.

The jitter noise contribution to total SNR is given by the

following equation. If this value is near your system require-

The ADS804 has analog and digital supply pins, however,

the converter should be treated as an analog component and

all supply pins should be powered by the analog supply. This

will ensure the most consistent results, since digital supply

lines often carry high levels of noise that would otherwise be

coupled into the converter and degrade the achievable per-

formance.

ments, input clock jitter must be reduced.

JitterSNR = 20log

rmssignaltormsnoise

2πƒ_{IN A}

Where: ƒ_INis Input Signal Frequency

t_Ais rms Clock Jitter

Because of the pipeline architecture, the converter also

generates high-frequency current transients and noise that

are fed back into the supply and reference lines. This

requires that the supply and reference pins be sufficiently

bypassed. Figure 12 shows the recommended decoupling

scheme for the analog supplies. In most cases, 0.1µF ce-

ramic chip capacitors are adequate to keep the impedance

low over a wide frequency range. Their effectiveness largely

depends on the proximity to the individual supply pin. There-

fore, they should be located as close to the supply pins as

possible. In addition, a larger size bipolar capacitor (1µF to

22µF) should be placed on the PC board in close proximity

to the converter circuit.

Particularly in undersampling applications, special consider-

ation should be given to clock jitter. The clock input should be

treated as an analog input in order to achieve the highest

level of performance. Any overshoot or undershoot of the

clock signal may cause degradation of the performance.

When digitizing at high sampling rates, the clock should have

a 50% duty cycle (t_H= t_L), along with fast rise and fall times

of 2ns or less.

DIGITAL OUTPUTS

The digital outputs of the ADS804 are designed to be

compatible with both high-speed TTL and CMOS logic fami-

lies. The driver stage for the digital outputs is supplied

through a separate supply pin, VDRV, which is not con-

nected to the analog supply pins. By adjusting the voltage on

VDRV, the digital output levels will vary respectively. There-

fore, it is possible to operate the ADS804 on a +5V analog

supply while interfacing the digital outputs to 3V logic.

ADS804

+V_S

GND

+V_S

GND

VDRV

0.1µF

It is recommended to keep the capacitive loading on the data

lines as low as possible (≤ 15pF). Larger capacitive loads

demand higher charging currents as the outputs are chang-

ing. Those high current surges can feed back to the analog

portion of the ADS804 and influence the performance. If

necessary, external buffers or latches may be used which

2.2µF

+5V

+5V/+3V

FIGURE 12. Recommended Bypassing for Analog Supply

Pins.

ADS804

SBAS068B

www.ti.com

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

ADS804E

ACTIVE

SSOP

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

ADS804E

ADS804E/1K

1000 RoHS & Green

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADS804E/1K

SSOP

1000

330.0

16.4

8.1

10.4

2.5

12.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SSOP DB 28

SPQ

Length (mm) Width (mm) Height (mm)

350.0 350.0 43.0

ADS804E/1K

1000

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TUBE

*All dimensions are nominal

Device

Package Name Package Type

DB SSOP

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

ADS804E

530

10.5

4000

4.1

Pack Materials-Page 3

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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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