ADS8167IRHBT [TI]
具有基准电压、基准电压缓冲器和直接传感器接口的 16 位、500kSPS、8 通道 SAR ADC | RHB | 32 | -40 to 125;
| 型号： | ADS8167IRHBT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有基准电压、基准电压缓冲器和直接传感器接口的 16 位、500kSPS、8 通道 SAR ADC | RHB | 32 | -40 to 125 传感器 转换器 |
| 文件： | 总93页 (文件大小：2300K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADS8166, ADS8167, ADS8168
ZHCSIK6C –NOVEMBER 2017–REVISED NOVEMBER 2019
具有直接传感器接口的 ADS816x 8 通道、16 位 1MSPS SAR ADC
1 特性
2 应用
1
•
紧凑的低功耗数据采集系统：
•
•
•
•
•
•
模拟输入模块
多参数患者监视器
麻醉给药系统
–
–
–
–
多路复用器输出引脚支持单个外部驱动器放大器
16 位 SAR ADC
LCD 测试
低漂移集成基准和缓冲器
数据中心内部互联（地铁）
光学模块
适用于模拟输入直流偏置的 0.5 × VREF 输出
•
•
出色的交流和直流性能：
–
–
SNR：92dB，THD：–110dB
3 说明
INL：±0.3LSB，16 位，无丢失码
ADS816x 是一系列 16 位、8 通道、高精度逐次逼近
型寄存器 (SAR) 模数转换器 (ADC)，该器件由 5V 单
电源供电，具有 (ADS8168)
具有通道序列发生器的多路复用器：
–
多通道定序选项：
–
手动模式、动态模式、自动序列模式、自定
义通道定序
500kSPS (ADS8166) 和 250kSPS (ADS8166)的总吞
吐量。
–
–
早期开关可实现直接传感器接口
动态模式可缩短响应时间
输入多路复用器支持更长的建立时间，这使得驱动模拟
输入更加容易。多路复用器和 ADC 模拟输入的输出可
作为器件引脚提供。该配置使一个 ADC 驱动器运算放
大器可用于多路复用器的全部八路模拟输入。
•
•
•
系统监测 功能：
–
–
每通道可编程窗口比较器
通过可编程迟滞避免错误触发
增强型 SPI 数字接口：
ADS816x 具有 一个数字窗口比较器，其中每个模拟输
入通道具有可编程高低警报阈值。具有可编程警报阈值
的单运算放大器解决方案可实现低功耗、低成本且具有
最小外形尺寸的 应用。
–
–
在 16MHz SCLK 下具有 1MSPS 的吞吐量
70MHz 高速数字接口
宽工作范围：
–
–
–
–
外部 VREF 输入范围：2.5V 至 5V
AVDD 范围：3V 至 5.5V
器件信息
器件型号
ADS816x
封装
VQFN (32)
封装尺寸（标称值）
DVDD 范围：1.65V 至 5.5V
温度范围：–40°C 至 +125°C
5.00mm × 5.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
ADS816x 方框图
Single external op-amp
(optional)
AVDD
DVDD
Channel
Sequencer
HI threshold
+
+
œ
ALERT
AINX Data
LO threshold
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
16-bit
ADC
Enhanced-SPI
SPI
MUX
REFIO
÷2
4.096V
REFby2
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBAS817
ADS8166, ADS8167, ADS8168
ZHCSIK6C –NOVEMBER 2017–REVISED NOVEMBER 2019
www.ti.com.cn
目录
7.5 Programming........................................................... 38
7.6 Register Maps......................................................... 44
Application and Implementation ........................ 72
8.1 Application Information............................................ 72
8.2 Typical Applications ................................................ 75
Power Supply Recommendations...................... 80
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information.................................................. 7
6.5 Electrical Characteristics........................................... 8
6.6 Timing Requirements.............................................. 10
6.7 Switching Characteristics........................................ 11
6.8 Typical Characteristics............................................ 14
Detailed Description ............................................ 19
7.1 Overview ................................................................. 19
7.2 Functional Block Diagram ....................................... 19
7.3 Feature Description................................................. 20
7.4 Device Functional Modes........................................ 30
8
9
10 Layout................................................................... 81
10.1 Layout Guidelines ................................................. 81
10.2 Layout Example .................................................... 83
11 器件和文档支持 ..................................................... 84
11.1 文档支持................................................................ 84
11.2 相关链接................................................................ 84
11.3 接收文档更新通知 ................................................. 84
11.4 社区资源................................................................ 84
11.5 商标....................................................................... 84
11.6 静电放电警告......................................................... 84
11.7 Glossary................................................................ 84
12 机械、封装和可订购信息....................................... 85
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (December 2018) to Revision C
Page
•
已更改 将文档标题从具有易于驱动的模拟输入的 ADS816x 8 通道、16 位 1MSPS SAR ADC 更改为具有直接传感器
接口的 ADS816x 8 通道、16 位 1MSPS SAR ADC............................................................................................................... 1
•
•
•
•
•
•
已更改 将具有序列发生器的低泄漏多路复用器 更改为具有通道序列发生器的多路复用器（位于特性 部分） ....................... 1
已更改 将宽输入范围 更改为宽工作范围（位于特性 部分），更改了并将子项目符号添加至此 “特性” 项目符号................... 1
已删除 删除了警报阈值论述中的迟滞（位于说明 部分） ....................................................................................................... 1
已更改 更改了 ADS816x 方框图 的标题 ................................................................................................................................. 1
已更改 AUTO_SEQ_CFG1 = 0x84 to AUTO_SEQ_CFG1 = 0x44 in Auto Sequence Mode section .................................. 34
已更改 default settings from 1 to 0xFF in Channel Sample Count column of Custom Channel Sequencing
Configuration Space table .................................................................................................................................................... 36
•
•
已更改 reset value from R/W-0000 0001b to R/W-1111 1111b in REPEAT_INDEX_m Registers section ......................... 60
已更改 description of registers 78h, 7Ah, 7Ch, and 7Eh in Digital Window Comparator Configuration Registers
Mapping table ...................................................................................................................................................................... 61
•
•
•
•
已更改 ALERT_LO_STATUS Register section and name .................................................................................................. 66
已更改 ALERT_STATUS Register section and name ......................................................................................................... 68
已更改 CURR_ALERT_LO_STATUS Register section and name ...................................................................................... 69
已更改 CURR_ALERT_STATUS Register section and name ............................................................................................. 71
Changes from Revision A (July 2018) to Revision B
Page
•
已更改 将文档状态从“预告信息”更改为“生产数据”.................................................................................................................. 1
2
Copyright © 2017–2019, Texas Instruments Incorporated
ADS8166, ADS8167, ADS8168
www.ti.com.cn
ZHCSIK6C –NOVEMBER 2017–REVISED NOVEMBER 2019
5 Pin Configuration and Functions
RHB Package
32-Pin VQFN
Top View
GND
DECAP
REFIO
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
SDI
CS
ALERT
GND
REFM
Thermal
Pad
REFP
ADC-INM
MUXOUT-M
MUXOUT-P
ADC-INP
REFP
REFby2
AIN-COM
Not to scale
Pin Functions
PIN
NAME
ADC-INM
ADC-INP
AIN0
NO.
20
17
9
FUNCTION
DESCRIPTION
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Negative ADC analog input
Positive ADC analog input
Analog input channel 0
Analog input channel 1
Analog input channel 2
Analog input channel 3
Analog input channel 4
Analog input channel 5
Analog input channel 6
Analog input channel 7
Common analog input
AIN1
10
11
12
13
14
15
16
8
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN-COM
Digital ALERT output; active high.
This pin is the output of the logical OR of the enabled channel ALERTs.
ALERT
AVDD
22
32
Digital output
Power supply
Analog power-supply pin. Connect a 1-µF capacitor from this pin to GND.
Chip-select input pin; active low.
The device starts converting the active input channel on the rising edge of CS.
The device takes control of the data bus when CS is low.
The SDO-x pins go Hi-Z when CS is high.
CS
23
Digital input
DECAP
DVDD
2
Power supply
Power supply
Connect a 1-µF capacitor to GND for the internal power supply.
30
Interface power-supply pin. Connect a 1-µF capacitor from this pin to GND.
Copyright © 2017–2019, Texas Instruments Incorporated
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Pin Functions (continued)
PIN
NAME
GND
NO.
1, 21, 31
19
FUNCTION
Power supply
Analog output
Analog output
DESCRIPTION
Ground
MUXOUT-M
MUXOUT-P
MUX negative analog output
MUX positive analog output
Multifunction output pin.
18
When CS is held high, READY reflects the device conversion status. READY is low when
a conversion is in process.
When CS is low, the status of READY depends on the output protocol selection.
READY
28
Digital output
Analog output
The output voltage on this pin is equal to half the voltage on the REFP pin.
Connect a 1-µF capacitor from this pin to GND.
REFby2
REFIO
7
3
Reference voltage input; internal reference is a 4.096-V output.
Connect a 1-µF capacitor from this pin to GND.
Analog input/output
Analog input
REFM
REFP
4
Reference ground potential; short this pin to GND externally.
5, 6
Analog input/output Reference buffer output, ADC reference input. Short pins 5 and 6 together.
Asynchronous reset input pin.
Digital input
RST
29
25
A low pulse on the RST pin resets the device. All register bits return to their default states.
Clock input pin for the serial interface.
Digital input
SCLK
All system-synchronous data transfer protocols are timed with respect to the SCLK signal.
Serial data input pin.
Digital input
SDI
24
26
This pin is used to transfer data or commands into the device.
SDO-0
Digital output
Digital output
Supply
Serial communication pin: data output 0.
Multifunction output pin. By default, this pin indicates the channel scanning status in the
auto and custom channel sequence modes.
In dual SDO data transfer mode this pin functions as a serial communication pin: data
output 1.
SDO-1/
SEQSTS
27
Thermal pad
Exposed thermal pad; connect to GND.
4
Copyright © 2017–2019, Texas Instruments Incorporated
ADS8166, ADS8167, ADS8168
www.ti.com.cn
ZHCSIK6C –NOVEMBER 2017–REVISED NOVEMBER 2019
6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN
–0.3
MAX
7
UNIT
V
AVDD to GND
DVDD to GND
–0.3
7
V
AINx(2), AIN-COM, MUXOUT-P, MUXOUT-M, ADC-INP, ADC-INM
GND – 0.3
REFM – 0.3
REFM – 0.3
GND – 0.1
GND – 0.3
GND – 0.3
–10
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
GND + 0.1
DVDD + 0.3
DVDD + 0.3
10
V
REFP
V
REFIO
V
REFM
V
Digital input pins
V
Digital output pins
Input current to any pin except supply pins
Junction temperature, TJ
Storage temperature, Tstg
V
mA
°C
°C
–40
125
–65
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) AINx refers to AIN0, AIN1, AIN2, AIN3, AIN4, AIN5, AIN6, and AIN7 pins.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per
±2000
ANSI/ESDA/JEDEC JS-001, all pins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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ZHCSIK6C –NOVEMBER 2017–REVISED NOVEMBER 2019
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MAX UNIT
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
POWER SUPPLY
TEST CONDITIONS
MIN
TYP
Internal reference
External reference
Operating
4.5
3
5
5
3
3
5.5
V
AVDD
DVDD
5.5
1.65
2.35
5.5
V
Specified throughput
5.5
ANALOG INPUTS - SINGLE ENDED CONFIGURATION
FSR
Full-scale input range
0
–0.1
–0.1
–0.1
VREF
VREF + 0.1
0.1
V
V
V
AINx(1) to REFM and CHx_CHy_CFG(2) = 00b
AINy(3) to REFM and CHx_CHy_CFG = 01b
VIN
Absolute input voltage
VIN
Absolute input voltage AIN-COM
0.1
ANALOG INPUTS - PSEUDO-DIFFERENTIAL CONFIGURATION
FSR
Full-scale input range
–VREF/2
–0.1
VREF/2
VREF + 0.1
V
V
V
AINx to REFM and CHx_CHy_CFG = 00b
AINy to REFM and CHx_CHy_CFG = 10b
VIN
Absolute input voltage
VREF/2 – 0.1
VREF/2 – 0.1
VREF/2 + 0.1
VREF/2 + 0.1
VIN
Absolute input voltage AIN-COM
EXTERNAL REFERENCE INPUT
VREFIO REFIO input voltage
TEMPERATURE RANGE
TA Ambient temperature
(1) AINx refers to analog inputs AIN0, AIN1, AIN2, AIN3, AIN4, AIN5, AIN6, and AIN7.
REFIO configured as input pin
2.5
AVDD – 0.3
125
V
–40
25
°C
(2) CHx_CHy_CFG bits set the analog input configuration as single-ended or pseudo-differential pair. See the AIN_CFG register for more
details.
(3) AINy refers to analog inputs AIN1, AIN3, AIN5, and AIN7 when CHx_CHy_CFG = 01b or 10b. See the Multiplexer
Configurations section for more details.
6
版权 © 2017–2019, Texas Instruments Incorporated
ADS8166, ADS8167, ADS8168
www.ti.com.cn
ZHCSIK6C –NOVEMBER 2017–REVISED NOVEMBER 2019
6.4 Thermal Information
ADS816x
THERMAL METRIC(1)
RHB (VQFN)
32 PINS
29.5
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
18.6
10.2
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ΨJB
10.2
RθJC(bot)
1.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
版权 © 2017–2019, Texas Instruments Incorporated
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ADS8166, ADS8167, ADS8168
ZHCSIK6C –NOVEMBER 2017–REVISED NOVEMBER 2019
www.ti.com.cn
6.5 Electrical Characteristics
at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, REFIO configured as output pin, and maximum throughput (unless otherwise
noted); minimum and maximum values at TA = –40°C to +125°C; typical values at TA = 25°C
PARAMETER
ANALOG INPUTS
TEST CONDITIONS
MIN
TYP
MAX UNIT
CSH
ADC Input capacitance
MUX Input capacitance
60
13
pF
pF
CINMUX
MUX input on-channel leakage
current
ILMUX_ON
REFM < VIN < REFP
–750
±10
750
nA
DC PERFORMANCE
Resolution
16
Bits
NMC
INL
No missing codes
Integral nonlinearity
Differential nonlinearity
Input offset error
16
–0.8
–0.5
–10
–1
±0.35
±0.2
0.8
0.5
10
1
LSB
LSB
DNL
VOS
±0.5
LSB
Input offset error match
Input offset thermal drift
Gain error
±0.5
LSB
dVOS/dT
GE
0.25
µV/°C
Referred to REFIO
Referred to REFIO
Referred to REFIO
VIN = VREF/2
–0.06
±0.002
±0.0025
±1
0.06 %FSR
0.005 %FSR
ppm/°C
Gain error match
–0.005
dGE/dT
TNS
Gain error thermal drift
Transition noise
0.6
LSB
AC PERFORMANCE
SINAD
SNR
Signal-to-noise + distortion
fIN = 2 kHz
fIN = 2 kHz
fIN = 2 kHz
fIN = 2 kHz
fIN = 100 kHz
91.6
91.8
93.5
93.6
-110
112
dB
dB
dB
dB
dB
Signal-to-noise-ratio
THD
Total harmonic distortion
Spurious-free dynamic range
Isolation crosstalk
SFDR
-115
REFERENCE BUFFER
VRO = VREFP - VREFIO, TA
25°C
=
VRO
Reference buffer offset voltage
–250
0
250
1.3
µV
CREFP
RESR
Decoupling capacitor on REFP
External series resistance
22
µF
Ω
REFby2 BUFFER
VREFby2 REFby2 output voltage
VREFP/2
V
DC Sourcing current from
REFby2
IREFby2
2
mA
Decoupling capacitor on
REFby2
CREFby2
1
µF
V
INTERNAL REFERENCE OUTPUT
TA = 25°C, REFIO configured
as output pin
VREFIO
REFIO output voltage(1)
4.091
4.096
4
4.101
Internal reference temperature
drift
dVREFIO/dT
CREFIO
18 ppm/°C
µF
Decoupling capacitor on REFIO REFIO configured as output
1
EXTERNAL REFERENCE INPUT
IREFIO
REFIO input current
REFIO configured as input pin
REFIO configured as input pin
0.1
10
1
µA
pF
Internal capacitance on REFIO
pin
CREF
SAMPLING DYNAMICS
Aperture delay
Aperture jitter
4
2
ns
tj-RMS
ps RMS
(1) Does not include the variation in voltage resulting from solder effects.
8
Copyright © 2017–2019, Texas Instruments Incorporated
ADS8166, ADS8167, ADS8168
www.ti.com.cn
ZHCSIK6C –NOVEMBER 2017–REVISED NOVEMBER 2019
Electrical Characteristics (continued)
at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, REFIO configured as output pin, and maximum throughput (unless otherwise
noted); minimum and maximum values at TA = –40°C to +125°C; typical values at TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
f-3-dB(small)
Small-signal bandwidth
Measured at ADC inputs
23
MHz
POWER SUPPLY CURRENTS
ADS8168, AVDD = 5 V
ADS8167, AVDD = 5 V
ADS8166, AVDD = 5 V
Static, no conversion
Static, PD_REFBUF = 1
Static, PD_REF = 1
5.3
3.9
3
6.4
5
4.1
mA
2.3
1.6
800
IAVDD
Analog supply current
Digital supply current
µA
µA
Static, PD_REFBUF, PD_REF
and PD_REFby2 = 1
180
DVDD = 3 V, CLOAD = 10 pF,
no conversion
IDVDD
0.45
µA
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www.ti.com.cn
6.6 Timing Requirements
at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values
at TA = –40°C to +125°C; typical values at TA = 25°C
MIN
NOM
MAX
UNIT
kHz
µs
CONVERSION CYCLE
ADS8168
ADS8167
ADS8166
ADS8168
ADS8167
ADS8166
1000
500
fCYCLE
Sampling frequency
250
1
2
tCYCLE
ADC cycle-time period
4
twh_CSZ
twl_CSZ
tACQ
Pulse duration: CS high
Pulse duration: CS low
Acquisition time
30
30
300
30
20
ns
ns
ns
ns
ns
tqt_ACQ
td_CNVCAP
Quite acquisition time
Quiet aperture time
ASYNCHRONOUS RESET AND LOW POWER MODES
twl_RST Pulse duration: RST low
SPI-COMPATIBLE SERIAL INTERFACE
100
ns
2.35 V ≤ DVDD ≤ 5.5 V,
VIH > 0.7 DVDD, VIL < 0.3 DVDD
70
20
68
1.65 V ≤ DVDD < 2.35 V,
VIH ≥ 0.8 DVDD, VIL ≤ 0.2 DVDD
fCLK
Serial clock frequency
MHz
1.65 V ≤ DVDD < 2.35 V,
VIH ≥ 0.9 DVDD, VIL ≤ 0.1 DVDD
tCLK
Serial clock time period
SCLK high time
1/fCLK
0.45
0.45
15
ns
tCLK
tCLK
ns
tph_CK
0.55
0.55
tpl_CK
SCLK low time
tph_CSCK
tsu_CKDI
tht_CKDI
tht_CKCS
Setup time: CS falling to the first SCLK capture edge
Setup time: SDI data valid to the SCLK capture edge
Hold time: SCLK capture edge to (previous) data valid on SDI
Delay time: last SCLK falling to CS rising
3
ns
4
ns
7.5
ns
SOURCE-SYNCHRONOUS SERIAL INTERFACE
2.35 V ≤ DVDD ≤ 5.5 V, SDR
(DATA_RATE = 0b)
70
35
fCLK
Serial clock frequency
Serial clock time period
MHz
ns
2.35 V ≤ DVDD ≤ 5.5 V, DDR
(DATA_RATE = 1b)
tCLK
1/fCLK
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6.7 Switching Characteristics
at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values
at TA = –40°C to +125°C; typical values at TA= 25°C
PARAMETER
CONVERSION CYCLE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADS8168
660
1200
2500
tCONV
Conversion time
ADS8167
ADS8166
ns
ASYNCHRONOUS RESET, AND LOW POWER MODES
td_RST
Delay time: RST rising to READY rising
Power-up time for converter module
Power-up time for internal reference
4
ms
ms
ms
tPU_ADC
tPU_REFIO
Change PD_ADC = 1b to 0b
Change PD_REF = 1b to 0b
1
5
Power-up time for internal reference
buffer
tPU_REFBUF
Change PD_REFBUF = 1b to 0b
10
10
ms
ms
tPU_Device
Power-up time for device
SPI-COMPATIBLE SERIAL INTERFACE
tden_CSDO Delay time: CS falling to data enable
15
15
ns
ns
Delay time: CS rising to SDO going to
Hi-Z
tdz_CSDO
Delay time: SCLK launch edge to (next)
data valid on SDO
td_CKDO
19
15
ns
ns
td_CSRDY_t
Delay time: CS falling to READY falling
SOURCE-SYNCHRONOUS SERIAL INTERFACE (External Clock)
Delay time: SCLK launch edge to
READY rising
td_CKSTR_r
23
23
2
ns
ns
ns
ns
Delay time: SCLK launch edge to
READY falling
td_CKSTR_f
Time offset: READY falling to (next) data
valid on SDO
toff_STRDO_f
–2
–2
Time offset: READY rising to (next) data
valid on SDO
toff_STRDO_r
2
tph_STR
tpl_STR
Strobe output high time
Strobe output low time
2.35 V ≤ DVDD ≤ 5.5 V
2.35 V ≤ DVDD ≤ 5.5 V
0.45
0.45
0.55
0.55
tSTR
tSTR
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Sample
S
Sample
S + 1
CS
ADCST (Internal)
READY
tcycle
tconv_max
tconv
tconv_min
tacq
CNV (S)
ACQ (S + 1)
图 1. Conversion Cycle Timing
twl_RST
RST
CS
td_rst
SCLK
READY
SDO-x
图 2. Asynchronous Reset Timing
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tCLK
tph_CK
tpl_CK
SCLK(1)
CS
tsu_CKDI
tht_CKDI
tsu_CSCK
tht_CKCS
SCLK(1)
SDI
tden_CSDO
tdz_CSDO
td_CKDO
SDO-x
SDO-x
(1) The SCLK polarity, launch edge, and capture edge depend on the SPI protocol selected.
图 3. SPI-Compatible Serial Interface Timing
tCLK
tph_CK
tpl_CK
CS
SCLK
td_CKSTR_f
tsu_CSCK
tht_CKCS
td_CKSTR_r
SCLK
SDO-x
READY
READY
tden_CSDO
tdz_CSDO
toff_STRDO_r
toff_STRDO_f
SDO-x
(DDR)
td_CSRDY_f
td_CSRDY_r
toff_STRDO_r
SDO-x
(SDR)
图 4. Source-Synchronous Serial Interface Timing
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6.8 Typical Characteristics
at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, REFIO configured as output pin, and maximum throughput (unless otherwise noted)
0.3
0.18
0.06
-0.06
-0.18
-0.3
0.5
0.3
0.1
-0.1
-0.3
-0.5
0
13107
26214 39321
ADC Output Code
52428
65535
0
13107
26214 39321
ADC Output Code
52428
65535
ADD0S048
D007
Typical DNL = ±0.15 LSB
Typical INL = ±0.3 LSB
图 5. Typical DNL
图 6. Typical INL
0.3
0.18
0.06
-0.06
-0.18
-0.3
1800
1600
1400
1200
1000
800
600
400
200
0
1647
Maximum
Minimum
1004
952
319
278
223
50
21
6
0
0
0
0
-40
-7
26
59
92
125
Free-Air Temperature (èC)
D005
ADD0S583
2250 devices
图 7. Typical INL Distribution (LSB)
图 8. DNL vs Temperature
1
0.6
0.2
-0.2
-0.6
-1
0.5
0.3
Maximum
Minimum
0.1
-0.1
-0.3
-0.5
Maximum
-7
Minimum
26
2.5
3
3.5 4
Reference Voltage (V)
4.5
5
-40
59
92
125
Free-Air Temperature (èC)
D050
D008
图 10. DNL vs Reference Voltage
图 9. INL vs Temperature
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Typical Characteristics (接下页)
at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, REFIO configured as output pin, and maximum throughput (unless otherwise noted)
700
650
600
550
500
450
400
350
300
250
200
150
100
50
1
0.6
0.2
-0.2
-0.6
-1
Maximum
Minimum
505
441
249
209
81
62
11
4
0
0
0
2.5
3
3.5 4
Reference Voltage (V)
4.5
5
D054
D051
2250 devices
图 12. Typical Offset Distribution (LSB)
图 11. INL vs Reference Voltage
1200
1000
800
600
400
200
0
10
0
1101
-10
-20
-30
-40
-50
722
322
84
20
0
0
1
0
-40
-7
26 59
Temperature (°C)
92
125
D055
D052
REF_SEL[2:0] = 000b
2250 devices
图 14. Offset Error vs Temperature
图 13. Typical Gain Error Distribution (%FSR)
50
40
0.004
0.003
0.002
0.001
0
30
20
10
0
-10
-20
-30
-40
-50
-0.001
-0.002
-0.003
2.5
3
3.5
Reference Voltage (V)
4
4.5
5
-40
-7
26
59
92
125
Free-Air Temperature (èC)
D011
D013
With the appropriate REF_SEL[2:0]; see the OFST_CAL register
EN_MARG = 0b
图 15. Offset Error vs Reference Voltage
图 16. Gain Error (ADC + REFBUF) vs Temperature
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Typical Characteristics (接下页)
at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, REFIO configured as output pin, and maximum throughput (unless otherwise noted)
0.01
0.008
0.006
0.004
0.002
0
40000
35000
30000
25000
20000
15000
10000
5000
27043
467
183
0
2.5
3
3.5 4
Reference Voltage (V)
4.5
5
D014
D002
EN_MARG = 0b
Standard deviation = 0.51 LSB
图 17. Gain Error (ADC + REFBUF) vs Reference Voltage
图 18. DC Input Histogram
0
0
-40
-40
-80
-80
-120
-120
-160
-200
-160
-200
0
100
200 300
fIN, Input Frequency (kHz)
400
500
0
50
100 150
fIN, Input Frequency (kHz)
200
250
D018
D019
fIN = 2 kHz, SNR = 93.8 dB, THD = –112.7 dB
fIN = 2 kHz, SNR = 93.8 dB, THD = –112.4 dB
图 19. Typical FFT, ADS8168
图 20. Typical FFT, ADS8167
0
-40
94.8
94.4
94
16
SNR
SINAD
ENOB
15.6
15.2
14.8
14.4
14
-80
-120
-160
-200
93.6
93.2
92.8
-40
0
25
50 75
fIN, Input Frequency (kHz)
100
125
-7
26
59
92
125
Free-Air Temperature (èC)
D020
D028
fIN = 2 kHz, SNR = 93.8 dB, THD = –111.4 dB
fIN = 2 kHz
图 21. Typical FFT, ADS8166
图 22. Noise Performance vs Temperature
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Typical Characteristics (接下页)
at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, REFIO configured as output pin, and maximum throughput (unless otherwise noted)
-106
-107
-108
-109
-110
-111
-112
-113
120
118
116
114
112
110
108
106
95
94.5
94
15.6
15.5
15.4
15.3
15.2
15.1
15
THD
SFDR
SNR
SINAD
ENOB
93.5
93
92.5
92
91.5
91
14.9
14.8
14.7
90.5
-40
-7
26
59
92
125
2.5
3
3.5
Reference Voltage (V)
4
4.5
5
Free-Air Temperature (èC)
D031
D029
fIN = 2 kHz
fIN = 2 kHz
图 23. Distortion Performance vs Temperature
图 24. Noise Performance vs Reference Voltage
94
92
90
88
86
84
15.6
-112
-111.5
-111
111
112
113
114
115
116
SNR
SINAD
ENOB
THD
SFDR
15.2
14.8
14.4
14
-110.5
-110
13.6
-109.5
0
20000
40000 60000
fIN, Input Frequency (Hz)
80000
100000
2.5
3
3.5 4
Reference Voltage (V)
4.5
5
ADD0S285
D032
fIN = 2 kHz
图 26. Noise Performance vs Input Frequency
图 25. Distortion Performance vs Reference Voltage
7
-70
-80
120
THD
SFDR
1000 kSPS
500 kSPS
250 kSPS
6.5
6
110
100
90
5.5
5
-90
4.5
4
-100
-110
-120
3.5
3
80
2.5
2
70
100000
0
20000
40000 60000
fIN, Input Frequency (Hz)
80000
4.5
4.7
4.9
5.1
5.3
5.5
AVDD (V)
D026
D043
图 27. Distortion Performance vs Input Frequency
图 28. Analog Supply Current vs Supply Voltage
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Typical Characteristics (接下页)
at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, REFIO configured as output pin, and maximum throughput (unless otherwise noted)
7
1000 kSPS
500 kSPS
250 kSPS
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
-40
-7
26
59
92
125
Free-Air Temperature (èC)
D037
AVDD = 5 V
图 29. Analog Supply Current vs Temperature
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7 Detailed Description
7.1 Overview
The ADS816x is a 16-bit, successive approximation register (SAR) analog-to-digital converter (ADC) with an
analog multiplexer. This device integrates a reference, reference buffer, REFby2 buffer, low-dropout regulator
(LDO), and features high performance at full throughput and low power consumption.
The ADS816x supports unipolar, single-ended and pseudo-differential analog input signals. The analog
multiplexer is optimized for low distortion and extended settling time. The internal reference generates a low-drift,
4.096-V reference output. The integrated reference buffer supports burst mode for data acquisition of external
reference voltages in the range 2.5 V to 5 V. For DC level shifting of the analog input signals, the device has a
REFby2 output. The REFby2 output is derived from the output of the integrated reference buffer (the REFP pin).
When a conversion is initiated, the differential input between the ADC-INP and ADC-INM pins is sampled on the
internal capacitor array. The device uses an internal clock to perform conversions. During the conversion
process, both analog inputs of the ADC are disconnected from the internal circuit. At the end of conversion
process, the device reconnects the sampling capacitors to the ADC-INP and ADC-INM pins and enters an
acquisition phase.
The integrated LDO allows the device to operate on a single supply, AVDD. The device consumes only
26.5 mW, 19.5 mW, and 15 mW of power when operating at 1 MSPS (ADS8168), 500 kSPS (ADS8167), and
250 kSPS (ADS8166), respectively, with the internal reference, reference buffer, REFby2 buffer, and LDO
enabled.
The enhanced-SPI digital interface is backward-compatible with traditional SPI protocols. Configurable features
boost analog performance and simplify board layout, timing, firmware, and support full throughput at lower clock
speeds. These features enable a variety of microcontrollers, digital signal processors (DSPs), and field-
programmable gate arrays (FPGAs) to be used.
The ADS816x enables optical line cards, test and measurement, medical, and industrial applications to achieve
fast, low-noise, low-distortion, and low-power data acquisition in a small form-factor.
7.2 Functional Block Diagram
MUXOUT-P ADC-INP AVDD
DECAP
LDO
Channel
Sequencer
DVDD
ALERT
READY
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
SDO-1/SEQSTS
4-WIRE SPI
RST
Digital
ADC
MUX
4.096-V
÷2
AIN-COM MUXOUT-N ADC-INM REFP REFby2
REFIO
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7.3 Feature Description
The ADS816x is comprised of five modules: the converter (SAR ADC), multiplexer (MUX), the reference module,
the enhanced-SPI interface, and the low-dropout regulator (LDO); see the Functional Block Diagram section.
The LDO module is powered by the AVDD supply, and generates the bias voltage for the internal circuit blocks of
the device. The reference buffer drives the capacitive switching load present at the reference pins during the
conversion process. The multiplexer selects among eight analog input channels as the input for the converter
module. The converter module samples and converts the analog input into an equivalent digital output code. The
enhanced-SPI interface module facilitates communication and data transfer between the device and the host
controller.
7.3.1 Analog Multiplexer
图 30 shows the small-signal equivalent circuit of the sample-and-hold circuit. Each sampling switch is
represented by resistance (RS1 and RS2, typically 50 Ω) in series with an ideal switch (SW). The sampling
capacitors, CS1 and CS2, are typically 60 pF.
The multiplexer on-resistance (RMUX), is typically a 40-Ω resistor in series between the ON channel and the
MUXOUT-P or MUXOUT-M pins. The multiplexer analog input typically has a 13-pF on-channel capacitance
(CMUX).
AVDD
AVDD
MUX
ADC
RMUX
40ꢀ
RS1
50ꢀ
SW
SW
OR
AINx
MUXOUT-P
ADC-INP
CMUX
13pF
CS1
60pF
AVDD
AVDD
CS2
60pF
RMUX
40ꢀ
RS2
50ꢀ
SW
SW
AINy,
AIN-COM
OR
MUXOUT-M
ADC-INM
CMUX
13pF
图 30. Input Sampling Stage Equivalent Circuit
During the input signal acquisition phase, the ADC-INP and ADC-INM inputs are individually sampled on CS1 and
CS2, respectively. During the conversion process, the device converts for the voltage difference between the two
sampled values: VADC-INP – VADC-INM
.
Each analog input pin has electrostatic discharge (ESD) protection diodes to AVDD and GND. Keep the analog
inputs within the specified range to avoid turning the diodes on.
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Feature Description (接下页)
7.3.1.1 Multiplexer Configurations
The ADS816x supports single-ended and pseudo-differential analog input signals. The flexible analog input
channel configuration supports interfacing various types of sensors. 图 31 shows how the analog inputs can be
configured.
8-channel MUX
4-channel MUX
CHx_CHy_CFG = 00b
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
Input Pair 1
Input Pair 2
Input Pair 3
Input Pair 4
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
Pseudo-differential
AIN-COM = REFby2
COM_CFG bit = 1
REFby2
REFby2
AIN-COM
AIN-COM
AIN-COM not used
Single-ended
CHx_CHy_CFG = 01b
Pseudo-differential
CHx_CHy_CFG = 10b
Single-ended
AIN-COM = GND
AINX
AINY
COM_CFG bit = 0
GND or REFby2
Configuration - 1
Configuration - 2
6-channel MUX
Single-ended
CHx_CHy_CFG = 01b
Pseudo-differential
CHx_CHy_CFG = 10b
AIN0
Input Pair 1
Input Pair 2
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AINX
AINY
Pseudo-differential
AIN-COM = REFby2
GND or REFby2
4 single inputs
referred to AIN-COM
Selectable Channel Configuration
REFby2
Channels
Input Pairs
Single Inputs
AIN-COM
8
6
4
2
0
0
1
2
3
4
8
7
6
5
4
CHx_CHy_CFG = 00b
Single-ended
AIN-COM = GND
Configuration - 3
图 31. Analog Input Configurations
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Feature Description (接下页)
The analog inputs can be configured as:
•
Configuration 1: Eight-channel MUX with the AIN_CFG register set to 00h. The AIN-COM input range is
decided by the COM_CFG register.
–
–
Single-ended inputs with the AIN-COM input set to GND (set the COM_CFG register to 00h).
Pseudo-differential inputs with the AIN-COM input set to VREF / 2 (set the COM_CFG register to 01h).
•
•
Configuration 2: Four-channel MUX.
As shown in 表 1, the AIN_CFG register selects the analog input range of individual pairs.
Configuration 3: Single-ended and pseudo-differential inputs.
–
–
–
–
Among the eight analog inputs of the MUX, some inputs can be configured as pairs and some inputs are
configured as individual channels. 表 1 lists options for channel configuration.
For channels configured as pairs, the AIN_CFG register selects the single-ended or pseudo-differential
configuration for individual pairs.
For individual channels, the COM_CFG register decides the single-ended or pseudo-differential
configuration.
表 1. Channel Configuration Options(1)(2)
SERIAL NUMBER
TOTAL CHANNELS
INPUT PAIRS
INDIVIDUAL CHANNELS
1
2
3
4
5
8
7
6
5
4
0
1
2
3
4
8
6
4
2
0
(1) Channel pairs can be formed as [AIN0 - AIN1], [AIN2 - AIN3], [AIN4 - AIN5], and [AIN6 - AIN7].
(2) When channels are configured as pairs, AIN0, AIN2, AIN4, and AIN6 are positive inputs.
注
The COM_CFG register sets the input voltage range of the AIN-COM pin. AIN-COM pin
must be connected to GND (set the COM_CFG register to 0b) or REFby2 (set the
COM_CFG register to 1b) externally. When using the MUX in a four-channel configuration,
the COM_CFG register has no effect; connect the AIN-COM pin to GND to avoid noise
coupling.
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7.3.1.2 Multiplexer With Minimum Crosstalk
For precision measurement in a multichannel system, coupling (such as crosstalk) from one channel to another
can distort the measurement. In conventional multiplexers, as shown in 图 32, the off channel parasitic
capacitance between the drain and the source of the switch (CDSY) couples the off channel signal to the on
channel.
图 32 shows that the ADS816x uses a T-switch structure. In this switch architecture, the off channel parasitic
capacitance is connected to ground, which significantly reduces coupling. Care must be taken to avoid signal
coupling on the printed circuit board (PCB), as described in the Layout section.
Conventional MUX
ADS816x MUX
CHX
MUXOUT
CHX
MUXOUT
SW
SW
SW
CS
CD
CS
CD
CHY
CHY
SW
SW
SW
CS
CD
CS
CD
图 32. Isolation Crosstalk in a Conventional MUX versus the ADS816x
7.3.1.3 Early Switching for Direct Sensor Interface
图 33 shows the small-signal equivalent model of the ADS816x analog inputs. The multiplexer input has a switch
resistance (RMUX) and parasitic capacitance (CMUX). The parasitic capacitance causes a charge kickback on the
MUX analog input at the same time as the ADC sampling capacitor causes a charge kickback on ADC inputs.
RS1
50ꢀ
RMUX
40ꢀ
CMUX
13pF
SWMUX
SWADC
OR
CS1
60pF
AINx
ADC-AINP
MUXOUT-P
RMUX
40ꢀ
RS2
50ꢀ
SWMUX
SWADC
AINy,
AIN-COM
CS2
60pF
MUXOUT-M
ADC-AINM
OR
CMUX
13pF
ADC
MUX
图 33. Synchronous and Timed Switching of the MUX and ADC Input Switches
In conventional multichannel SAR ADCs, the acquisition time of the ADC is also the settling time available at the
analog inputs of the multiplexer because these times are internally connected. Thus, high-bandwidth op amps
are required at the analog inputs of the multiplexer to settle the charge kickback. However, multiple high-
bandwidth op amps significantly increase power dissipation, cost, and size of the solution.
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The analog inputs of the ADS816x provide a long settling time (tCYCLE – 100 ns), resulting in long acquisition time
at the MUX inputs when using a driver amplifier between the MUX outputs and the ADC inputs. 图 34 shows a
timing diagram of this long acquisition phase. The low parasitic capacitance together with the enhanced settling
time eliminate the need to use an op amp at the multiplexer input in most applications.
tCYCLE
CS
SWADC
100-ns
tACQ
SWMUX
CHX Input Settling Time
图 34. Early Switching of the MUX Enables a Long Acquisition Phase
Averaging several output codes of a particular MUX input channel without switching the MUX achieves better
accuracy and noise performance. The output of the multiplexer does not create a charge kickback as long as SDI
is set to 0 (that is, as long as SDI returns the NOP command); see 图 43 and 图 45. The multiplexer does not
switch during subsequent conversions except for the first time when a channel is selected. Thus high-impedance
sources (such as the voltage from the resistor dividers) can be connected to the analog inputs of the multiplexer
without an op amp.
7.3.2 Reference
The ADS816x has a precision, low-drift reference internal to the device. See the Internal Reference section for
details about using the internal reference.
For best SNR performance, the input signal range must be equal to the full-scale input range of the ADC. To
maximize ENOB, an external reference voltage source can be used as described in the External Reference
section.
7.3.2.1 Internal Reference
The device features an internal reference source with a nominal output value of 4.096 V. On power-up, the
internal reference is enabled by default. A minimum 1-µF decoupling capacitor, as illustrated in 图 35, is
recommended to be placed between the REFIO and REFM pins. The capacitor must be placed as close to the
REFIO pin as possible. The output impedance of the internal band-gap circuit creates a low-pass filter with this
capacitor to band-limit the noise of the reference. The internal reference is also temperature compensated to
provide excellent temperature drift over an extended industrial temperature range of –40°C to +125°C. By default
the internal reference is on and the voltage at REFIO is 4.096 V. The REFIO pin has ESD protection diodes to
the AVDD and GND pins.
The initial accuracy specification for the internal reference can be degraded if the die is exposed to any
mechanical or thermal stress. Heating the device when being soldered to a PCB and any subsequent solder
reflow is a primary cause for shifts in the internal reference voltage output. The main cause of thermal hysteresis
is a change in die stress and is therefore a function of the package, die-attach material, and molding compound,
as well as the layout of the device itself.
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5-V
1-kꢁ
4.096-V
AVDD
PD_CNTL[3] = 0
(PD_REF)
REFIO
1 ꢀF
REFP
10 ꢀF
10 ꢀF
REFM
GND
ADS816x
ADC
图 35. Device Connections for Using an Internal 4.096-V Reference
7.3.2.2 External Reference
图 36 shows the connections for using the device with an external reference. A reference without a low-
impedance output buffer can be used because the input leakage current of the internal reference buffer is less
than 1 µA.
5-V
1-kꢀ
4.096-V
AVDD
AVDD
PD_CNTL[3] = 1
(PD_REF)
OUT
REF5040
REFIO
REFP
1 …F
10 …F
10 …F
REFM
GND
ADC
ADS816x
图 36. Device Connections for Using an External Reference
7.3.3 Reference Buffer
The ADC starts converting the sampled analog input channel on the CS rising edge and the internal capacitors
are switched to the REFP pins as per the successive approximation algorithm. Most of the switching charge
required during the conversion process is provided by an external decoupling capacitor CREFP. If the charge lost
from CREFP is not replenished before the next CS rising edge, the voltage on the REFP pins is less than VREFP
.
The subsequent conversion occurs with this different reference voltage, and causes a proportional error in the
output code. The internal reference buffer of the device maintains the voltage on the REFP pins within 0.5 LSB of
VREFP. All typical characteristics of the device are specified with the internal reference buffer and the specified
value of CREFP
.
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In burst-mode operation, the ADC samples the selected analog input channel for a long duration of time and then
performs a burst of conversions. During the sampling time, the sampling capacitor (CS) is connected to the
differential input pins and no charge is drawn from the REFP pins. However, during the very first conversion
cycle, there is a step change in the current drawn from the REFP pins. This sudden change in load triggers a
transient settling response in the reference buffer. For a fixed input voltage, any transient settling error at the end
of the conversion cycle results in a change in output codes over the subsequent conversions. The internal
reference buffer of the ADS816x, when used with the recommended value of CREFP, keeps the transient settling
error at the end of each conversion cycle within 0.5 LSB. Therefore, the device supports burst-mode operation
with every conversion result as per the data sheet specifications.
图 37 shows the block diagram of the internal reference and reference buffer.
ADS816x
AVDD
Margin
œ
BUF
REFP
REFP
REFIO
+
PD_REF
4.096-V
GND
REFM
图 37. Internal Reference and Reference Buffer Block Diagram
For the minimum ADC input offset error (VOS), set the REF_SEL[2:0] bits to the value closest to VREF (see the
OFST_CAL register). The internal reference buffer has a typical gain of 1 V/V with a minimal offset error (V(RO)),
and the output of the buffer is available between the REFP and the REFM pins. Set the REF_OFST[4:0] (see the
REF_MRG1 register) bits to add or subtract an intentional offset voltage as described in 表 22.
Short the two REFP pins externally. Short the REFM pin to GND externally. Place a decoupling capacitor CREFP
between the REFP and the REFM pins as close to the device as possible; see 图 36. See the Layout section for
layout recommendations.
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7.3.4 REFby2 Buffer
To use the maximum dynamic range of the ADC, the input signal must be biased around the mid-scale of the
ADC input range. In the ADS816x, where the absolute input range is 0 V to the reference voltage (VREF), mid-
scale is VREF / 2. The REFby2 buffer generates the VREF / 2 signal for mid-scale shifting of the input signal. 图 38
shows that REFBy2 can be used in various types of sensor signal conditioning circuits.
VCC
VCC
Current Sense Amplifier
AC coupled
sensor
VLOAD
ADS816x
ADC
ADS816x
ADC
-
-
INA Ref
+
+
Load
REFby2
REFby2
REF
REF
Configuration 1: High-side / Low-side Current sensing
Configuration 2: AC Coupled Sensor Interface
VCC
VCC
VBRIDGE
R
INA
ADS816x
ADC
ADS816x
R
-
-
ADC
Ref
+
+
REFby2
REFby2
REF
REF
R
R
Configuration 4: High Impedance Sensor Interface with INA
Configuration 3:Unity Gain Sensor Interface
图 38. Signal Conditioning With the REFby2 Buffer
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A resistor divider at the output of the reference buffer, as shown in 图 39, generates the VREF / 2 signal. When
not using the internal reference buffer (see the PD_CNTL register), any voltage applied at the REFP pin is
applied to the resistor divider. The output of the resistor divider is buffered and available at the REFby2 pin.
REFP
ADS816x
AVDD
ADC
Reference
œ
œ
REFby2
BUF
BUF
+
+
REFIO
100-kꢀ
100-kꢀ
Margin
GND
图 39. REFby2 Buffer Model
The REFby2 buffer is capable of sourcing up to 2 mA of DC current. The REFby2 pin has ESD diode
connections to AVDD and GND.
7.3.5 Converter Module
The converter module samples the analog input signal (provided between the ADC-INP and ADC-INM pins),
compares this signal with the reference voltage (between the REFP pins and REFM pin), and generates an
equivalent digital output code.
The converter module receives the RST and CS inputs from the interface module, and outputs the conversion
result back to the interface module.
7.3.5.1 Internal Oscillator
The device features an internal oscillator (OSC) that provides the conversion clock. Conversion duration varies,
but is bounded by the minimum and maximum value of tconv
.
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7.3.5.2 ADC Transfer Function
The device supports single-ended and pseudo-differential analog inputs. The device output is in straight binary
format. 图 40 and 表 2 show the ideal transfer characteristics for a 16-bit ADC with unipolar inputs.
公式 1 gives the least significant bit (LSB) for the ADC:
1 LSB = VREF / 216
(1)
FFFF
8000
7FFF
1
0
-FSR
VIN
MID œ 1 LSB
-FSR + 1 LSB
MID
FSR œ 1 LSB
Analog Input
(AINP - AINM)
图 40. Converter Transfer Characteristics
表 2. Transfer Characteristics
PSEUDO-DIFFERENTIAL INPUT
SINGLE-ENDED INPUT VOLTAGE
OUTPUT CODE
(HEX)
DESCRIPTION
VOLTAGE
(VREF = 4.096 V)
(VREF = 4.096 V)
FSR – 1 LSB
MID + 1 LSB
MID
4.0959375 V
2.0480625 V
2.048 V
2.0479375 V
0.0000625 V
0 V
FFFF
8001
8000
7FFF
0001
0000
MID – 1 LSB
–FSR + 1 LSB
–FSR
2.0479375 V
0.0000625 V
0 V
–0.0000625 V
–2.0479375 V
–2.048 V
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7.3.6 Low-Dropout Regulator (LDO)
To enable single-supply operation, the device features an internal low-dropout regulator (LDO). The LDO is
powered by the AVDD supply, and the 2.85-V (nominal) output is available on the DECAP pin. This LDO output
powers the critical analog blocks within the device, and must not be used for any other external purposes.
Decouple the DECAP pin with the GND pin, as shown in 图 41, by placing a 1-µF, X7R-grade, ceramic capacitor
with a 6.3-V rating from DECAP to GND. There is no upper limit on the value of the decoupling capacitor;
however, a larger decoupling capacitor results in higher power-up time for the device. See the Layout section for
layout recommendations.
AVDD
DECAP
LDO
CLDO
1 ꢀF
GND
图 41. Internal LDO Connections
7.4 Device Functional Modes
The multiplexer includes a sequence control logic that supports various features as described in the Channel
Selection Using Internal Multiplexer section.
7.4.1 Channel Selection Using Internal Multiplexer
The ADS816x includes an 8-channel, linear, and low-leakage current analog multiplexer. The multiplexer
performs a break-before-make operation when switching channels. There are four modes of switching the
multiplexer input channels: manual mode, on-the-fly mode, auto sequence mode, and custom channel
sequencing mode.
These modes can be selected by configuring the SEQ_MODE[1:0] bits in the DEVICE_CFG register. On power-
up the default mode is manual mode, SEQ_MODE[1:0] = 00b, and the default input channel is AIN0. The
multiplexer configuration registers can be accessed over the SPI; see 图 50. The SPI interface eliminates the
need for separate MUX control lines.
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Device Functional Modes (接下页)
7.4.1.1 Manual Mode
In manual mode, the channel ID of the desired analog input is configured in the CHANNEL_ID register. On
power-up or after device reset, AIN0 is selected and CHANNEL_ID[2:0] = 000b. Manual mode can be enabled
from any other sequencing mode by programming the SEQ_MODE[1:0] bits to 00b in the DEVICE_CFG register.
图 42 shows the timing information for changing channels in manual mode.
The channel information can be updated in a microcontroller (MCU)-friendly 3-byte access. As the 24-bits of
channel configuration are sent over SDI, conversion data are clocked out over SDO. The data on SDO are MSB
aligned and the first 16 clocks correspond to 16 bits of conversion data. The last eight bits of the SDO can be
ignored by the MCU.
As shown in 图 42, the command to switch to AINy is sent in the Nth cycle and the data corresponding to
channel AINy is available in the (N + 2)th cycle. This switch occurs because the SDI commands are processed
and the ADC starts conversions on the rising edge of CS. Thus, the conversion is processed on the previous
channel (AINx) and not on the updated channel ID (AINy).
Sample
AINx
Sample
AINx
Sample
AINy
Sample
AINz
tCONV
tCYCLE
CS
SCLK
SDI
Switch to AINy
Switch to AINz
Switch to AINx
Data AINy
SDO
Data AINx
24 clocks
Data AINx
100-ns
MUX OUT = AINx
MUX OUT = AINy
MUX OUT = AINz
MUX
Cycle N
Cycle (N + 1)
Cycle (N + 2)
图 42. Manual Mode Timing Diagram
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Device Functional Modes (接下页)
As shown in 图 43, after selecting AINy the output of the multiplexer does not create a charge kickback as long
as SDI is set to 0 (that is, as long as SDI returns the NOP command). Therefore, high-impedance sources such
as the voltage from resistor dividers can be connected to the analog inputs of the multiplexer without an op amp.
Sample
AINx
Sample
AINy
Sample
AINy
Sample
AINy
Sample
AINy
tCONV
tCYCLE
CS
SCLK
SDI
Switch to AINy
SDO
Data AINx
24 clocks
Data AINy
16 clocks
Data AINy
Data AINy
MUX OUT = AINx
MUX OUT = AINx
MUX
100-ns
No MUX switching with SDI = 0 (NOP)
图 43. Manual Mode With No Channel Switching Timing Diagram
7.4.1.2 On-The-Fly Mode
There is a latency of one cycle when switching channels using the register access, just as in manual mode. The
newly selected channel data are available two cycles after selecting the desired channel. The ADS816x supports
on-the-fly switching of the analog input channels of the multiplexer. This mode can be enabled by programming
the SEQ_MODE[1:0] bits to 01b in the DEVICE_CFG register. When enabled, the analog input channel for the
next conversion is determined by the first five bits sent over SDI. The desired analog input channel can be
selected by setting the MSB to 1 and the following four bits as the channel ID. If the MSB is 0 then the SDI
bitstream is decoded as a normal frame on the rising edge of CS. 表 3 lists the channel selection commands for
this mode.
表 3. On-the-Fly Mode Channel Selection Commands
SDI BITS [15:11]
1 0000
SDI BITS [10:0]
Don't care
Don't care
Don't care
Don't care
Don't care
Don't care
Don't care
Don't care
Don't care
DESCRIPTION
Select analog input 0
Select analog input 1
Select analog input 2
Select analog input 3
Select analog input 4
Select analog input 5
Select analog input 6
Select analog input 7
Error bit is set; select analog input 0
1 0001
1 0010
1 0011
1 0100
1 0101
1 0110
1 0111
1 1000 to 1 1111
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To set the device in on-the-fly mode, configure EN_ON_THE_FLY to 1b in the ON_THE_FLY_CFG register as
shown in 图 44 using a 3-byte register access. When in this mode, the 16-bit data transfer can be used to reduce
the required clock speed for operating at full throughput.
Sample
AINx
Sample
AINx
Sample
AINy
Sample
AINz
tCONV
tCYCLE
CS
SCLK
SDI
2
2
1
24
1
3
4
5
16
1
3
4
5
16
5 clocks
Set MODE = 1
4-bit AINy ID
1
4-bit AINz ID
1
16 clocks
Data AINx
16 clocks
SDO
Data AINx
24 clocks
Data AINy
MUX OUT = AINz
MUX OUT = AINx
100-ns
MUX OUT = AINx
MUX OUT = AINy
MUX
No Cycle Latency
图 44. On-the-Fly Mode With No MUX Channel Selection Latency
After selecting AINy, as shown in 图 45, the output of the multiplexer does not create a charge kickback as long
as SDI is set to 0 (that is, as long as SDI returns the NOP command). Thus, high-impedance sources such as
the voltage from resistor dividers can be connected to the analog inputs of the multiplexer without an op amp.
Sample
AINx
Sample
AINx
Sample
AINy
Sample
AINy
tCONV
tCYCLE
CS
SCLK
SDI
2
2
1
24
1
3
4
5
16
1
3
4
5
16
5 clocks
Set MODE = 1
4-bit AINy ID
1
16 clocks
Data AINx
16 clocks
Data AINy
SDO
Data AINx
24 clocks
MUX OUT = AINy
MUX OUT = AINx
100-ns
MUX OUT = AINx
MUX
No MUX switching with SDI = 0 (NOP)
图 45. On-the-Fly Mode With No Channel Switching Timing Diagram
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7.4.1.3 Auto Sequence Mode
In auto sequence mode, the internal channel sequencer can selectively scan channels from AIN0 through AIN7
in ascending order. To select auto sequence mode, configure SEQ_MODE to 10b in the DEVICE_CFG register
using a 3-byte register access. One or more channels among AIN[7:0] can be enabled by configuring the
AUTO_SEQ_CFG1 register. By default all analog input channels are enabled. After enabling the desired
channels, the sequence can be started by setting SEQ_START to 1b. The ADC auto-increments through the
enabled channels after every CS rising edge. When SEQ_START is set to 1b, the SDO-1/SEQSTS pin is at logic
1 as shown in 图 46 until the last channel conversion frame is complete. After the last enabled channel
conversion is complete, channel AIN0 is selected and SDO-1/SEQSTS is in a high-impedance state.
Sample
AINx
Sample
AINx
Sample
AINx
Sample
AIN0
Sample
AIN0
tCONV
tCYCLE
CS
SCLK
SDI
AUTO_SEQ_CH
SEQ_START
SDO
Data AINx
24 clocks
Data AINx
24 clocks
Data AINx
16 clocks
Data AIN0
Data CH7
MUX OUT = AINx
MUX OUT = AIN0
MUX OUT = AIN1
MUX
MUX OUT = AIN0
Scan channels AIN0 to AIN7
SEQSTS
图 46. Starting a Sequence in Auto Sequence Mode
As an example, 图 47 depicts a timing diagram for when the device is scanning AIN2 and AIN6 in auto sequence
mode. When AIN6 is converted, SDO-1/SEQSTS is Hi-Z and AIN0 is selected as the active channel. At the end
of sequence, if more conversion frames are launched the device returns valid data corresponding to AIN0.
To use the device in auto sequence mode follow these steps:
•
•
•
Set the SEQ_MODE[1:0] bits in the DEVICE_CFG register to 10b.
Configure the AUTO_SEQ_CFG1 register. In 图 47, AUTO_SEQ_CFG1 = 0x44.
Set the SEQ_START bits in the SEQ_START register to 1b to start executing the sequence.
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Sample
AINx
Sample
AIN2
Sample
AIN6
Sample
AIN0
tCYCLE
CS
SCLK
SDI
SEQ_START
SDO
Data AIN6
16 clocks
Data AINx
24 clocks
Data AINx
Data AIN2
16 clocks
16 clocks
MUX OUT = AIN0
MUX OUT = AIN0
MUX OUT = AIN6
MUX OUT = AINx
MUX OUT = AIN2
MUX
SEQSTS
Scan channels AIN2 and AIN6
图 47. Example: Scanning Channels 2 and 6 in Auto Sequence Mode
To repeat a channel sequence indefinitely, set the AUTO_REPEAT bit in the AUTO_SEQ_CFG2 register to 1b.
图 48 shows that when the AUTO_REPEAT bit is enabled, the MUX scans through the channels enabled in the
AUTO_SEQ_CFG1 register and repeats the sequence after the last channel data are converted.
Sample
AINx
Sample
AIN2
Sample
AIN6
Sample
AIN2
Sample
AIN6
tCYCLE
CS
SCLK
SDI
SEQ_START
SDO
Data AIN6
16 clocks
Data AIN2
16 clocks
Data AINx
24 clocks
Data AINx
16 clocks
Data AIN2
16 clocks
MUX OUT = AIN2
MUX OUT = AIN6
MUX OUT = AIN2
MUX OUT = AIN6
MUX OUT = AINx
MUX
SEQSTS
Scan channels AIN2 and AIN6and repeat
图 48. Example: Scanning Channels 2 and 6 in Auto Sequence Mode With AUTO_REPEAT = 1
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图 48 provides a timing diagram for when the device is scanning AIN2 and AIN6 in auto sequence mode with
AUTO_REPEAT = 1b. When AIN6 is converted, AIN2 is selected as the active channel and the device continues
scanning through the enabled channels again.
To use the device in auto sequence with the repeat mode enabled follow these steps:
•
•
•
•
Set the SEQ_MODE[1:0] bits in the DEVICE_CFG register to 10b.
Configure the AUTO_SEQ_CFG1 register. In 图 47, AUTO_SEQ_CFG1 = 0x44.
Set AUTO_REPEAT to 1b.
Set the SEQ_START bit in the SEQ_START register to 1b to start executing the sequence.
To terminate an ongoing channel sequence set the SEQ_ABORT bit in the SEQ_ABORT register 1. When
SEQ_ABORT is set, the auto sequence stops and AIN0 is selected as the active input channel.
7.4.1.4 Custom Channel Sequencing Mode
In this mode the internal channel sequencer can selectively scan channels from AIN0 through AIN7 in any order
as defined by a user-programmable lookup table. 表 4 describes the configurability of this lookup table. The
device can be configured in custom channel sequencing mode by programming the SEQ_MODE[1:0] bits to 11b
in the DEVICE_CFG register using a 3-byte register access. 表 4 shows that the channel scanning sequence is
programmed by configuring the channel IDs in the register as space. A channel sample count can also be
programmed and associated with every channel ID. By default the channel sample count is 1, which means the
sequence executes in the order of programmed channel IDs. If the channel sample count is greater than 1 then
the corresponding channel is sampled and converted for a programmed number of times before switching to the
next channel.
表 4. Custom Channel Sequencing Configuration Space
REGISTER
ADDRESS
REGISTER
ADDRESS
CHANNEL ID[2:0]
CHANNEL SAMPLE COUNT[7:0]
0x8C
0x8E
0x90
0x92
0x94
0x96
0x98
0x9A
0x9C
0x9E
Index 0 : 3-bit channel ID (default = 0)
Index 1 : 3-bit channel ID (default = 0)
Index 2 : 3-bit channel ID (default = 0)
Index 3 : 3-bit channel ID (default = 0)
Index 4 : 3-bit channel ID (default = 0)
Index 5 : 3-bit channel ID (default = 0)
Index 6 : 3-bit channel ID (default = 0)
Index 7 : 3-bit channel ID (default = 0)
Index 8 : 3-bit channel ID (default = 0)
Index 9 : 3-bit channel ID (default = 0)
0x8D
0x8F
0x91
0x93
0x95
0x97
0x99
0x9B
0x9D
0x9F
Index 0 : 8-bit sample count (default = 0xFF)
Index 1 : 8-bit sample count (default = 0xFF)
Index 2 : 8-bit sample count (default = 0xFF)
Index 3 : 8-bit sample count (default = 0xFF)
Index 4 : 8-bit sample count (default = 0xFF)
Index 5 : 8-bit sample count (default = 0xFF)
Index 6 : 8-bit sample count (default = 0xFF)
Index 7 : 8-bit sample count (default = 0xFF)
Index 8 : 8-bit sample count (default = 0xFF)
Index 9 : 8-bit sample count (default = 0xFF)
Index 10 : 8-bit sample count (default =
0xFF)
0xA0
0xA2
0xA4
0xA6
0xA8
0xAA
Index 10 : 3-bit channel ID (default = 0)
Index 11 : 3-bit channel ID (default = 0)
Index 12 : 3-bit channel ID (default = 0)
Index 13 : 3-bit channel ID (default = 0)
Index 14 : 3-bit channel ID (default = 0)
Index 15: 3-bit channel ID (default = 0)
0xA1
0xA3
0xA5
0xA7
0xA9
0xAB
Index 11 : 8-bit sample count (default =
0xFF)
Index 12 : 8-bit sample count (default =
0xFF)
Index 13: 8-bit sample count (default =
0xFF)
Index 14 : 8-bit sample count (default =
0xFF)
Index 15 : 8-bit sample count (default =
0xFF)
For application-specific scanning requirements, start and stop pointers can be used to define the channel
scanning sequence. The start index can be programmed in the CCS_START_INDEX register and the stop index
can be programmed in the CCS_END_INDEX register. 表 4 shows that the 4-bit index corresponds to the
configuration index. The sequence starts executing from the index programmed in CCS_START_INDEX (default
0) and stop or loop-back from CCS_STOP_INDEX (default 15). The channel scanning sequence can be looped-
back to the start index from the stop index by setting the CCS_SEQ_LOOP register to 1b.
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After configuring the channel scanning order, start index, and stop index the scanning can be initiated by setting
the SEQ_START bit to 1b. The ADC scans through the enabled channels after every CS rising edge as defined
by the channel scanning order. When SEQ_START is set to 1b, the SDO-1/SEQSTS pin is pulled high until the
last channel conversion frame is complete, as described in 图 46. As illustrated in 图 47, channel AIN0 is
selected and SEQSTS/SDO-1 goes to Hi-Z after the last enabled channel conversion is complete.
As an example, 图 47 provides a timing diagram for when the channel configuration is set as in 表 5. When AIN6
is converted, SEQSTS/SDO-1 goes to Hi-Z and AIN0 is selected as the active channel. If more conversion
frames are launched at the end of the sequence, the device returns valid data corresponding to AIN0.
To use the device in easy capture mode follow these steps:
•
•
•
Set the SEQ_MODE[1:0] bits in the DEVICE_CFG register to 3.
Configure the channel sequence by setting registers 0x000C to 0x002B.
Configure the CCS_START_INDEX and the CCS_END_INDEX registers. In 图 47, CCS_START_INDEX = 0
and CCS_STOP_INDEX = 1.
•
•
Configure the CCS_SEQ_LOOP register to 1 to indefinitely loop the sequence. In
CCS_SEQ_LOOP register = 0b.
Set the SEQ_START register to 1b to start executing the sequence.
图 47, the
表 5. Custom Channel Sequencing Configuration Example
REGISTER
ADDRESS
REGISTER
ADDRESS
CHANNEL ID[2:0]
CHANNEL SAMPLE COUNT[7:0]
0x8C
0x8E
010b (Channel 2)
110b (Channel 6)
0x8D
0x8F
1
1
7.4.2 Digital Window Comparator
The ADS816x has a programmable digital window comparator for every analog input channel. The integrated
digital window comparator allows the host to not read ADC data over the serial interface for comparison
purposes. In monitoring applications, the ADC can compare channel data with the set thresholds and alert the
system host using the ALERT pin. Furthermore, the digital window comparator does not require software high
and low comparisons and thus saves processing cycles.
Window comparison is achieved by comparing the channel output code with a programmable high and low digital
threshold. As shown in 图 49, each analog input channel has a programable hysteresis that is applicable to both
the high and low thresholds of the corresponding channel. Thus, low threshold, high threshold, and hysteresis
configurations are available for each analog input channel.
AIN7
AIN1
AIN0
High Th + Hysteresis
AIN7
Alert
+
AIN0
Latch
Logical OR of All
Analog Input Alerts
Low Th - Hysteresis
VIN
ADC Data
ADC
图 49. Digital Window Comparator
The thresholds and hysteresis can be configured independently for each analog input channel. The ALERT
output of the device is a logical OR of all enabled alert outputs corresponding to the analog inputs. The window
comparator can be selectively enabled for the analog inputs by configuring the ALERT_CFG register.
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The alert status of an individual analog input channel can be read from the ALERT_STATUS register. See the
ALERT_HI_STATUS and ALERT_LO_STATUS registers for further information on the high or low threshold
ALERT, respectively. When monitoring only a low threshold, the high threshold can be set to the ADC positive
full-scale code. Similarly, when monitoring only a high threshold, the low threshold can be set to the negative full-
scale code.
7.5 Programming
7.5.1 Data Transfer Protocols
7.5.1.1 Enhanced-SPI Interface
The device features an enhanced-SPI interface that allows the host controller to operate at slower SCLK speeds
and still achieve the required cycle time with a faster response time. 图 50 shows the ADS816x Interface
connections for the minimum number of pins required by the enhanced-SPI interface.
For any data write operation, the host controller can use any of the four legacy, SPI-compatible protocols to
configure the device, as described in the Protocols for Configuring the Device section. See the Register
Read/Write Operation section for details about the register read or write operation.
For reading ADC conversion data or register data from the device, the enhanced-SPI interface module offers the
following options:
•
•
•
SPI protocol with a single data output line: SDO-0 (see the SPI Protocols With a Single SDO section)
SPI protocol with dual data output lines: SDO-1 and SDO-0 (see the SPI Protocols With Dual SDO section)
Clock re-timer data transfer (see the Clock Re-Timer Data Transfer section)
5-V
VDD
AVDD
DVDD
CS
SDI
CS
MOSI
MISO
SCK
ADS816x
MCU
SDO
SCLK
GND
GND
GND
GND
图 50. 4-Wire SPI Interface Connection Diagram
7.5.1.1.1 Protocols for Configuring the Device
As described in 表 6, the host controller can use any of the four SPI protocols (SPI-00, SPI-01, SPI-10, or SPI-
11) to write data into the device.
表 6. SPI Protocols for Configuring the Device
SCLK POLARITY
(At the CS Falling
Edge)
SCLK PHASE
(Capture Edge)
SDI_MODE[1:0]
BITS(1)
SDO_MODE[1:0]
BITS(2)
PROTOCOL
DIAGRAM
SPI-00
SPI-01
SPI-10
SPI-11
Low
Low
High
High
Rising
Falling
Falling
Rising
00h
01h
02h
03h
00h
00h
00h
00h
图 51
图 51
图 52
图 52
(1) See the SDI_CNTL register.
(2) See the SDO_CNTL1 register.
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On power-up or after coming out of any asynchronous reset, the device supports the SPI-00-S protocol for data
read and data write operations. To select a different SPI-compatible protocol, program the SDI_MODE[1:0] bits in
the SDI_CNTL register. This first write operation must adhere to the SPI-00-S protocol. Any subsequent data
transfer frames must adhere to the newly-selected protocol. The SPI protocol selected by the SDI_MODE[1:0]
configuration is applicable to both read and write operations.
图 51 and 图 52 detail the four protocols using an optimal data frame.
CS
CS
READY
READY
CPOL = 0
CPOL = 0
SCLK
SCLK
CPOL = 1
CPOL = 1
MSB
MSB-1
LSB+1
LSB
SDI
SDI
MSB
MSB-1
LSB+1
LSB
图 51. Standard SPI Timing Protocol
图 52. Standard SPI Timing Protocol
(CPHA = 0)
(CPHA = 1)
注
As explained in the Register Read/Write Operation section, a valid register read or write
operation to the device requires 24 SCLKs to be provided within a data transfer frame.
When reading ADC conversion data, a minimum 16 SCLKs are required within a data
transfer frame.
7.5.1.1.2 Protocols for Reading From the Device
The protocols for the data read operation can be broadly classified into three categories:
1. SPI protocols (SPI-00, SPI-01, SPI-10, and SPI-11) with a single SDO (see the SPI Protocols With a Single
SDO section); for example, SDO-0
2. SPI protocols (SPI-00, SPI-01, SPI-10, and SPI-11) with dual SDOs (see the SPI Protocols With Dual SDO
section); for example, SDO-1 and SDO-0
3. Source-synchronous protocol for data transfer
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7.5.1.1.2.1 SPI Protocols With a Single SDO
As shown in 表 7, 图 53, and 图 54, the host controller can use any of the four legacy, SPI-compatible protocols
(SPI-00, SPI-01, SPI-10, or SPI-11) to read data from the device.
表 7. SPI Protocols for Reading From the Device
SCLK POLARITY
(At the CS
Falling Edge)
SCLK PHASE
(Capture Edge)
MSB BIT
LAUNCH EDGE
SDI_MODE[1:0] SDO_MODE[1:0]
PROTOCOL
DIAGRAM
BITS
BITS
SPI-00
SPI-01
SPI-10
SPI-11
Low
Low
High
High
Rising
Falling
Falling
Rising
CS falling
1st SCLK rising
CS falling
00h
01h
02h
03h
00h
00h
00h
00h
图 53
图 53
图 54
图 54
1st SCLK falling
CS
CS
READY
READY
CPOL = 0
CPOL = 1
CPOL = 0
CPOL = 1
SCLK
SCLK
MSB
MSB-1
LSB+1
LSB
SDO-0
MSB-2
SDO-0
0
MSB
MSB-1
LSB+1
LSB
图 53. Standard SPI Timing Protocol
图 54. Standard SPI Timing Protocol
(CPHA = 0, Single SDO-0)
(CPHA = 1, Single SDO-0)
On power-up or after coming out of any asynchronous reset, the device supports the SPI-00 protocol for data
read and data write operations. To select a different SPI-compatible protocol for both of the data transfer
operations:
1. Program the SDI_MODE[1:0] bits in the SDI_CNTL register. This first write operation must adhere to the SPI-
00 protocol. Any subsequent data transfer frames must adhere to the newly-selected protocol.
2. Set the SDO_MODE[1:0] bits = 00b in the SDO_CNTL1 register.
注
The SPI transfer protocol selected by configuring the SDI_MODE[1:0] bits in the
SDI_CNTL register determines the data transfer protocol for both write and read
operations.
When using any of the SPI-compatible protocols, the READY output remains low throughout the data transfer
frame.
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7.5.1.1.2.2 SPI Protocols With Dual SDO
The device provides an option to increase the SDO bus width from one bit (default, single SDO-0) to two bits
(dual SDO) when operating with any of the data transfer protocols. In order to operate the device in dual SDO
mode, the SDO_WIDTH bit in the SDO_CNTL1 register must be set to 1b. In this mode, the SDO-1/SEQSTS pin
functions as SDO-1.
As shown in 图 55 and 图 56, two bits of data are launched on the two SDO pins (SDO-0 and SDO-1) on every
SCLK launch edge in dual SDO mode.
CS
CS
READY
READY
CPOL = 0
CPOL = 1
CPOL = 0
CPOL = 1
SCLK
SCLK
MSB
MSB-2
MSB-3
LSB+3
LSB+2
LSB+1
SDO-1
SDO-0
MSB-4
MSB-5
SDO-1
SDO-0
0
0
MSB
MSB-2
MSB-3
LSB+3
LSB+2
LSB+1
MSB-1
LSB
MSB-1
LSB
图 55. Standard SPI Timing Protocol
图 56. Standard SPI Timing Protocol
(CPHA = 0, Dual SDO)
(CPHA = 1, Dual SDO)
7.5.1.1.2.3 Clock Re-Timer Data Transfer
In clock re-timer data transfer mode, the device provides an output clock that is synchronous with the output
data. Furthermore, the host controller can also select the data bus width in this mode of operation. In all modes
of operation, the READY pin provides the output clock, synchronous to the device data output.
The clock re-timer data transfer allows the width of the output bus to be configured, similar to the SPI protocols
SPI protocols described in 表 6.
7.5.1.1.2.3.1 Output Bus Width Options
The device provides an option to increase the SDO-x bus width from one bit (default, single SDO-x) to two bits
(dual SDO-x) when operating with clock re-timer data transfer. In order to operate the device in dual SDO mode,
the SDO_WIDTH bit in the SDO_CNTL1 register must be set to 1b. In this mode, the SDO-1/SEQSTS pin
functions as SDO-1.
注
For any particular data transfer, SPI or clock re-timer, the device follows the same timing
specifications for single and dual SDO modes. The only difference is that in the dual SDO
mode the device requires half as many clock cycles to output the same number of bits
when in single SDO mode, thus reducing the minimum required clock frequency for a
certain sampling rate of the ADC.
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7.5.2 Register Read/Write Operation
This device features configuration registers (as described in the Interface and Hardware Configuration Registers
section). These devices support the commands listed in 表 8 to access the internal configuration registers.
表 8. Supported Commands
COMMAND
ACRONYM
B[23:19]
B[18:8]
B[7:0]
COMMAND DESCRIPTION
00000
00001
00010
00011
00100
00000000000
<11-bit address>
<11-bit address>
<11-bit address>
<11-bit address>
00000000
<8-bit data>
NOP
No operation
WR_REG Write <8-bit data> to the <11-bit address>
RD_REG Read contents from the <11-bit address>
SET_BITS Set <8-bit unmasked bits> from <11-bit address>
CLR_BITS Clear <8-bit unmasked bits> from <11-bit address>
00000000
<8-bit unmasked bits>
<8-bit unmasked bits>
Remaining
combinations
These commands are reserved and treated by the
device as no operation
xxxxxxxxx
xxxxxxxx
Reserved
The ADS816x supports two types of data transfer operations: data write (the host controller configures the
device), and data read (the host controller reads data from the device).
Any data write to the device is always synchronous to the external clock provided on the SCLK pin. The
WR_REG command writes the 8-bit data into the 11-bit address specified in the command string. The CLR_BITS
command clears the specified bits (identified by 1) at the 11-bit address (without affecting the other bits), and the
SET_BITS command sets the specified bits (identified by 1) at the 11-bit address (without affecting the other
bits).
图 57 shows the digital waveform for register read operation. Register read operation consists of two frames: one
frame to initiate a register read and a second frame to read data from the register address provided in the first
frame. As shown in 图 57, the 11-bit register address and the 8-bit dummy data are sent over the SDI pin during
the first 24-bit frame with the read command (00010b). When CS goes from low to high, this read command is
decoded and the requested register data are available for reading during the next frame. During the second
frame, the first eight bits on SDO correspond to the requested register read. During the second frame SDI can be
used to initiate another operation or can be set to 0.
CS
SCLK
18
18
1
2
5
6
7
16
17
24
1
2
5
6
7
16
17
24
0 0010b
(RD_REG)
SDI
11-bit Address
0000 0000b
Command
11-bit Address
Optional; Can set SDI = 0
8-bit Data
SDO
8-bit Register Data
图 57. Register Read Operation
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图 58 shows that for writing data to the register, one 24-bit frame is required. The 24-bit data on SDI consists of a
5-bit write command (00001b), an 11-bit register address, and 8-bit data. The write command is decoded on the
CS rising edge and the specified register is updated with the 8-bit data specified during register write operation.
CS
SCLK
18
1
2
5
6
7
16
17
24
0 0001b
(WR_REG)
SDI
11-bit Address
8-bit Data
图 58. Register Write Operation
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7.6 Register Maps
表 9 lists the access codes for the ADS816x registers.
表 9. ADS816x Access Type Codes
Access Type
Code
Description
Read Type
R
R
Read
R-W
R/W
Read or write
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default value
7.6.1 Interface and Hardware Configuration Registers
表 10 maps the device features following a hardware configuration of the registers.
表 10. Configuration Registers Mapping
ADDRESS
REGISTER NAME
REGISTER DESCRIPTION
Enables read/write access to the device configuration registers specified in
Interface and Hardware Configuration Registers
00h
REG_ACCESS
Enable/disable control for reference, reference buffer, REFby2 buffer, and
the ADC
04h
PD_CNTL
08h
0Ch
0Dh
0Eh
0Fh
10h
11h
SDI_CNTL
SDO_CNTL1
SDO_CNTL2
SDO_CNTL3
SDO_CNTL4
DATA_CNTL
PARITY_CNTL
SPI-00, SPI-01, SPI-10, or SPI-11 protocol selection.
SDO output protocol selection
Output data rate selection
Reserved
Configuration for the SEQSTS pin when not using SDO-1 for data transfer.
Output data word configuration
Parity configuration register
7.6.1.1 REG_ACCESS Register (address = 00h) [reset = 00h]
This register enables or disables write access to the device configuration registers specified in 表 10.
图 59. REG_ACCESS Register
7
6
5
4
3
2
1
0
REG_ACCESS_BITS
R/W-0000 0000b
表 11. REG_ACCESS Register Field Descriptions
Bit
Field
REG_ACCESS_BITS
Type
Reset
Description
7-0
R/W
0000
0000b
Enables or disables write access to the device configuration
registers specified in 表 10.
Write 1010 1010b to this register to enable write access.
Write access is disabled for all values other than
REG_ACCESS_BITS = 1010 1010b.
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7.6.1.2 PD_CNTL Register (address = 04h) [reset = 00h]
This register controls the low-power modes offered by the device. Write access to this register is disabled on
power-up. To enable write access, configure the REG_ACCESS register.
图 60. PD_CNTL Register
7
0
6
0
5
0
4
3
2
1
0
0
PD_REFby2
R/W-0b
PD_REF
R/W-0b
PD_REFBUF
R/W-0b
PD_ADC
R/W-0b
R-0b
R-0b
R-0b
R-0b
表 12. PD_CNTL Register Field Descriptions
Bit
Field
Type
R
Reset
000b
0b
Description
7-5
4
0
Reserved bits. Reads return 000b.
PD_REFby2
PD_REF
PD_REFBUF
PD_ADC
0
R/W
This bit powers down the internal REFby2 buffer.
0b = REFby2 buffer is powered up
1b = REFby2 buffer is powered down
3
2
1
0
R/W
R/W
R/W
R
0b
0b
0b
0b
This bit powers down the internal reference.
0b = Internal reference is powered up
1b = Internal reference is powered down
This bit powers down the internal reference buffer.
0b = Internal reference buffer is powered up
1b = Internal reference buffer is powered down
This bit powers down the converter module.
0b = Converter module is powered up
1b = Converter module is powered down
Reserved bits. Do not write. Reads return 0b.
To power-down the converter module, set the PD_ADC bit in the PD_CNTL register. The converter module
powers down on the rising edge of CS. To power-up the converter module, reset the PD_ADC bit in the
PD_CNTL register. The converter module starts to power-up on the rising edge of CS. Wait for tPU_ADC before
initiating any conversion or data transfer operation.
To power-down the internal reference buffer, set the PD_REFBUF bit in the PD_CNTL register. The internal
reference buffer powers down on the rising edge of CS.
To power-down the internal reference, set the PD_REF bit in the PD_CNTL register. The internal reference
powers down on the rising edge of CS.
7.6.1.3 SDI_CNTL Register (address = 008h) [reset = 00h]
This register selects the SPI protocol for writing data to the device. Write access to this register is disabled on
power-up. To enable write access, configure the REG_ACCESS register.
图 61. SDI_CNTL Register
7
0
6
0
5
0
4
0
3
0
2
0
1
0
SDI_MODE[1:0]
R/W-00b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
表 13. SDI_CNTL Register Field Descriptions
Bit
Field
Type
R
Reset
Description
7-2
1-0
0
000000b Reserved bits. Do not write. Reads return 000000b.
SDI_MODE[1:0]
R/W
00b
These bits select the protocol for writing data into the device.
00b = Standard SPI with CPOL = 0 and CPHASE = 0
01b = Standard SPI with CPOL = 0 and CPHASE = 1
10b = Standard SPI with CPOL = 1 and CPHASE = 0
11b = Standard SPI with CPOL = 1 and CPHASE = 1
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7.6.1.4 SDO_CNTL1 Register (address = 0Ch) [reset = 00h]
This register configures the protocol for reading data from the device. Write access to this register is disabled on
power-up. To enable write access, configure the REG_ACCESS register.
图 62. SDO_CNTL1 Register
7
0
6
5
4
3
0
2
1
0
OUTDATA_uC DATA_RIGHT_
BYTE_
INTERLEAVE
SDO_WIDTH
R/W-0b
SDO_MODE[1:0]
R/W-00b
_MODE
ALIGNED
R-0b
R/W-0b
R/W-0b
R/W-0b
R-0b
表 14. SDO_CNTL1 Register Field Descriptions
Bit
Field
Type
R
Reset
0b
Description
7
6
0
Reserved bit. Do not write. Read returns 0b.
OUTDATA_uC_MODE
DATA_RIGHT_ALIGNED
BYTE_INTERLEAVE
R/W
0b
Enables the MCU or processor-friendly data interface.
0b = Length of output data is determined by the DATA_OUT_FORMAT
field in the DATA_CNTL register.
1b = Length of output data is fixed to 16-bits when the length based on
DATA_OUT_FORMAT is ≤ 16 or 32-bits when the length based on
DATA_OUT_FORMAT is > 16.
5
4
R/W
R/W
0b
0b
This bit is ignored if OUTDATA_uC_MODE = 0b. When
OUTDATA_uC_MODE = 1b:
0b = Data frame is left aligned. The SDOs output the device data bits
followed by 0s in a 32-bit output frame.
1b = Data frame is right aligned. The SDOs output 0s followed by device
data bits in a 32-bit output frame.
This bit is ignored if OUTDATA_uC_MODE = 0b or SDO_WIDTH = 0b.
When OUTDATA_uC_MODE = 1b and SDO_WIDTH = 1b:
0b = Bit mode. SDO-1 outputs (MSB, MSB - 2 ..., LSB + 1) and SDO-0
outputs (MSB - 1, MSB - 3, ..., LSB).
1b = Byte mode. If the total number of bits to be read from the device is N
(conversion result, parity, channel ID, and so forth) then SDO-1 outputs 8
MSB bits and SDO-0 outputs (N-8) bits when N ≤16 and SDO-1 outputs
16 MSB bits and SDO-0 outputs (N-16) bits when 16 < N ≤ 32.
3
2
0
R
0b
0b
Reserved bit. Do not write. Read returns 0b.
SDO_WIDTH
R/W
This bit sets the width of the output bus.
0b = Data bits are output only on SDO-0
1b = Data bits are output on SDO-0 (MSB - 1, MSB - 3 ..., LSB) and
SDO-1 (MSB, MSB - 2 ..., LSB + 1)
1-0
SDO_MODE[1:0]
R/W
00b
These bits select the protocol for reading data from the device.
00b = SDO follows the SPI protocol selected in the SDI_CNTL register
01b = Invalid configuration, not supported by the device
10b = Invalid configuration, not supported by the device
11b = SDO follows the Clock Re-Timer Data Transfer section
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7.6.1.5 SDO_CNTL2 Register (address = 0Dh) [reset = 00h]
This register configures the output data rates, SDR or DDR, when using the clock re-timer data transfer. Write
access to this register is disabled on power-up. To enable write access, configure the REG_ACCESS register.
图 63. SDO_CNTL2 Register
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
DATA_RATE
R/W-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
表 15. SDO_CNTL2 Register Field Descriptions
Bit
Field
Type
Reset
Description
Reserved bit. Do not write. Reads return 000 0000b.
7-1
000 0000
R
000
0000b
0
DATA_RATE
R/W
0b
This bit is ignored if SDO_MODE[1:0] = 0xb. When SDO_MODE[1:0] =
11b:
0b = SDOs are updated at a single data rate (SDR) with respect to the
output clock
1b = SDOs are updated at double data rate (DDR) with respect to the
output clock
7.6.1.6 SDO_CNTL3 Register (address = 0Eh) [reset = 00h]
The bits in this register are reserved.
图 64. SDO_CNTL3 Register
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
表 16. SDO_CNTL3 Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
Reserved bits. Do not write. Reads return 0000 0000b.
0000 0000
R
0000
0000b
7.6.1.7 SDO_CNTL4 Register (address = 0Fh) [reset = 00h]
This register configures the behaviour of the SEQ_STS pin when not using dual SDO mode (SDO_WIDTH = 0b).
Write access to this register is disabled on power-up. To enable write access, configure the REG_ACCESS
register.
图 65. SDO_CNTL4 Register
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
SEQSTS_CFG
R/W-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
表 17. SDO_CNTL4 Register Field Descriptions
Bit
Field
Type
Reset
Description
Reserved bits. Do not write. Reads return 000 0000b.
7-1
000 0000
R
000
0000b
0
SEQSTS_CFG
R/W
0b
This pin decides the behaviour of SDO-1 when SDO_WIDTH = 0b.
0b = SDO-1 is Hi-Z
1b = SDO-1 indicates the sequence of the active status
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7.6.1.8 DATA_CNTL Register (address = 10h) [reset = 00h]
This register configures the contents of the output data word. Write access to this register is disabled on power-
up. To enable write access, configure the REG_ACCESS register.
图 66. DATA_CNTL Register
7
0
6
0
5
4
3
0
2
0
1
0
0
DATA_OUT_FORMAT[1:0]
R/W-00b
DATA_VAL
R/W-0b
R-0b
R-0b
R-0b
R-0b
R-0b
表 18. DATA_CNTL Register Field Descriptions
Bit
Field
Type
R
Reset
000b
00b
Description
7-6
5-4
00
Reserved bits. Reads return 00b.
DATA_OUT_FORMAT[1:0]
R/W
These bits control the composition of the output data frame.
00b = ADC conversion result
01b = ADC conversion result + 4-bit channel ID
10b = ADC conversion result + 4-bit channel ID + 4-bit device status (see
表 32) + 2-bit channel configuration
11b = Reserved
Parity bits can be appended to the data output frame. See the
PARITY_CNTL register for details.
3-1
0
000
R
000b
0b
Reserved bits. Reads return 00b.
DATA_VAL
R/W
Setting this bit enables debug mode for SDO capture.
0b = Normal operation; device data are output on SDO
1b = The device outputs a fixed 1010 0110 patten that is useful for
debugging data capture from the device
7.6.1.9 PARITY_CNTL Register (address = 11h) [reset = 00h]
This register enables or disables the computing parity status for the output from the device. Write access to this
register is disabled on power-up. To enable write access, configure the REG_ACCESS register.
图 67. PARITY_CNTL Register
7
0
6
0
5
0
4
0
3
0
2
1
0
0
0
PARITY_EN
R/W-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
表 19. PARITY_CNTL Register Field Descriptions
Bit
Field
Type
R
Reset
Description
7-3
2
0 0000
0 0000b Reserved bits. Do not write. Reads return 0 0000b.
PARITY_EN
R/W
0b
Enables the parity computation on the data output bits.
0b = Parity disabled
1b = A 1-bit parity is appended to the data output frame. Data length is 1-
bit more than the length specified by DATA_OUT_FORMAT in the
DATA_CNTL register.
1-0
00
R
00b
Reserved bits. Do not write. Reads return 00b.
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7.6.2 Device Calibration Registers
表 20 maps the device features following register calibration.
表 20. Calibration Registers Mapping
ADDRESS
REGISTER NAME
REGISTER DESCRIPTION
Setting for optimum ADC offset calibration when using an external
reference input
18h
OFST_CAL
Margin setting for the reference buffer to compensate for initial accuracy of
the reference voltage
19h
REF_MRG1
Enable margin setting of the reference buffer as configured in the
REF_MRG1 register
1Ah
1Bh
REF_MRG2
REFby2_MRG
REFby2 buffer margin configuration
7.6.2.1 OFST_CAL Register (address = 18h) [reset = 00h]
This register selects the optimal offset calibration when using an external reference input. When using an internal
reference, do not write to this register. See the Reference Buffer section for more details.
图 68. OFST_CAL Register
7
0
6
0
5
0
4
0
3
0
2
1
0
REF_SEL[2:0]
R/W-000b
R-0b
R-0b
R-0b
R-0b
R-0b
表 21. OFST_CAL Register Field Descriptions
Bit
Field
Type
R
Reset
Description
7-3
2-0
0
0 0000b Reserved bits. Reads return 0 0000b.
REF_SEL[2:0]
R/W
000b
These bits select the external reference range for optimal offset.
000b = Optimum offset calibration for VREF = 5.0 V
001b = Optimum offset calibration for VREF = 4.5 V
010b = Optimum offset calibration for VREF = 4.096 V
011b = Optimum offset calibration for VREF = 3.3 V
100b = Optimum offset calibration for VREF = 3.0 V
101b = Optimum offset calibration for VREF = 2.5 V
110b = Optimum offset calibration for VREF = 5.0 V
111b = Optimum offset calibration for VREF = 5.0 V
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7.6.2.2 REF_MRG1 Register (address = 19h) [reset = 00h]
This register selects the margining to be added to or subtracted from the reference buffer output; see the
Reference Buffer section.
图 69. REF_MRG1 Register
7
0
6
0
5
0
4
3
2
1
0
REF_OFST[4:0]
R/W-00000b
R-0b
R-0b
R-0b
表 22. REF_MRG1 Register Field Descriptions
Bit
Field
Type
R
Reset
000b
Description
7-5
4-0
0
Reserved bits. Reads return 000b.
REF_OFST[4:0]
R/W
00000b
These bits select the reference offset value as per 表 23.
表 23. REF_OFST[4:0] Settings
(1)
(1)
REF_OFST[4:0]
00000b
00001b
00010b
00011b
00100b
00101b
00110b
00111b
01000b
01001b
01010b
01011b
01100b
01101b
01110b
01111b
ΔVREFBUFOUT
REF_OFST[4:0]
ΔVREFBUFOUT
–4.5 mV
0 mV
10000b
10001b
10010b
10011b
10100b
10101b
10110b
10111b
11000b
11001b
11010b
11011b
11100b
11101b
11110b
11111b
280 µV
580 µV
840 µV
–4.22 mV
–3.94 mV
–3.66 mV
–3.38 mV
–3.1 mV
1.12 mV
1.4 mV
1.68 mV
1.96 mV
2.24 mV
2.52 mV
2.8 mV
–2.82 mV
–2.54 mV
–2.26 mV
–1.98 mV
–1.70 mV
–1.42 mV
–1.14 mV
–860 µV
3.08 mV
3.36 mV
3.64 mV
3.92 mV
4.2 mV
–580 µV
–280 µV
(1) The actual VREFBUFOUT value may vary by ±10% from 表 23.
7.6.2.3 REF_MRG2 Register (address = 1Ah) [reset = 00h]
This register enables or disables the reference buffer margin configuration in the REF_MRG1 register.
图 70. REF_MRG2 Register
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
EN_MARG
R/W-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
表 24. REF_MRG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
R
000
Reserved bits. Reads return 000 0000b.
0000b
0
EN_MARG
R/W
0b
This bit enables the reference buffer margining feature.
0b = Margining is disabled
1b = Margining is enabled
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7.6.2.4 REFby2_MRG Register (address = 1Bh) [reset = 00h]
This register selects the margining to be added to or subtracted from the REFFby2 buffer output; see the
REFby2 Buffer section.
图 71. REFby2_MRG Register
7
0
6
5
4
3
0
2
0
1
0
0
REFby2_OFST[2:0]
R/W-000b
EN_REFby2_MARG
R/W-0b
R-0b
R-0b
R-0b
R-0b
表 25. REFby2_MRG Register Field Descriptions
Bit
Field
Type
R
Reset
0b
Description
7
0
Reserved bit. Do not write. Reads return 0b.
6-4
3-1
0
REFBY2_OFST[2:0]
0
R/W
R
000b
000b
0b
These bits select the REFby2 offset value as per 表 26.
Reserved bits. Do not write. Reads return 000b.
EN_REFby2_MARG
R/W
This bit enables the REFby2 buffer margining feature.
0b = Margining is disabled
1b = Margining is enabled
表 26. REFby2_OFST[2:0] Settings
(1)
(1)
VREFby2
VREFby2
REFby2_OFST[2:0]
(VREF = 4.096 V)
(VREF = 5 V)
EN_REFby2_MARG = 0b
2.04800 V
2.12611 V
2.13008 V
2.13406 V
2.13804 V
2.14203 V
2.14602 V
2.14999 V
2.15397 V
2.50000 V
2.59155 V
2.59640 V
2.60124 V
2.60610 V
2.61096 V
2.61581 V
2.62065 V
2.62550 V
000b
001b
010b
011b
100b
101b
110b
111b
(1) The actual VREFby2 value may vary by ±10% from 表 26.
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7.6.3 Analog Input Configuration Registers
表 27 maps the device features following channel configuration of the registers.
表 27. Analog Input Configuration Registers Mapping
ADDRESS
24h
REGISTER NAME
AIN_CFG
REGISTER DESCRIPTION
Analog input signal configuration selection
AIN-COM pin configuration
27h
COM_CFG
7.6.3.1 AIN_CFG Register (address = 24h) [reset = 00h]
This register configures the analog inputs as single-ended or pseudo-differential with or without a common input.
图 72. AIN_CFG Register
7
6
5
4
3
2
1
0
CH7_CH6_CFG[1:0]
R/W-00b
CH5_CH4_CFG[1:0]
R/W-00b
CH3_CH2_CFG[1:0]
R/W-00b
CH1_CH0_CFG[1:0]
R/W-00b
表 28. AIN_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
CH1_CH0_CFG[1:0]
R/W
00b
00b = AIN0 and AIN1 are two separate channels. The MUXOUT-M pin is
connected to the AIN-COM pin. See the COM_CFG register for selecting
single-ended or pseudo-differential operation.
01b = AIN0 and AIN1 are a single-ended pair. AIN0 connects to
MUXOUT-P and AIN1 connects to MUXOUT-M.
10b = AIN0 and AIN1 are a pseudo-differential pair. AIN0 connects to
MUXOUT-P and AIN1 connects to MUXOUT-M.
11b = Same as 00b
5-4
3-2
1-0
CH3_CH2_CFG[1:0]
CH5_CH4_CFG[1:0]
CH7_CH6_CFG[1:0]
R/W
R/W
R/W
00b
00b
00b
00b = AIN2 and AIN3 are two separate channels. The MUXOUT-M pin is
connected to the AIN-COM pin. See the COM_CFG register for selecting
single-ended or pseudo-differential operation.
01b = AIN2 and AIN3 are a single-ended pair. AIN2 connects to
MUXOUT-P and AIN3 connects to MUXOUT-M.
10b = AIN2 and AIN3 are a pseudo-differential pair. AIN2 connects to
MUXOUT-P and AIN3 connects to MUXOUT-M.
11b = Same as 00b
00b = AIN4 and AIN5 are two separate channels. The MUXOUT-M pin is
connected to the AIN-COM pin. See the COM_CFG register for selecting
single-ended or pseudo-differential operation.
01b = AIN4 and AIN5 are a single-ended pair. AIN4 connects to
MUXOUT-P and AIN5 connects to MUXOUT-M.
10b = AIN4 and AIN5 are a pseudo-differential pair. AIN4 connects to
MUXOUT-P and AIN5 connects to MUXOUT-M.
11b = Same as 00b
00b = AIN6 and AIN7 are two separate channels. MUXOUT-M pin
connected to AIN-COM pin. See the COM_CFG register for selecting
single-ended or pseudo-differential operation.
01b = AIN6 and AIN7 are a single-ended pair. AIN6 connects to
MUXOUT-P and AIN7 connects to MUXOUT-M.
10b = AIN6 and AIN7 are a pseudo-differential pair. AIN6 connects to
MUXOUT-P and AIN7 connects to MUXOUT-M.
11b = Same as 00b
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7.6.3.2 COM_CFG Register (address = 27h) [reset = 00h]
This register selects single-ended or pseudo-differential operation for any analog input channels that are not
configured as pairs (see the AIN_CFG register). Depending on the contents of this register, AIN-COM must be
connected to either GND or REFby2 on the PCB.
图 73. COM_CFG Register
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
COM_CFG
R/W-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
表 29. COM_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
R
000
Reserved bits. Reads return 000 0000b.
0000b
0
COM_CFG
R/W
0b
This bit selects the analog input channel configuration when = 00b or 11b
in the AIN_CFG register:
0b = All individual channels are single-ended inputs; connect the AIN-
COM pin to GND
1b = All individual channels are pseudo-differential inputs; connect the
AIN-COM pin to REFby2
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7.6.4 Channel Sequence Configuration Registers Map
表 30 maps the device features following channel configuration of the registers.
表 30. Channel Sequence Configuration Registers Mapping
ADDRESS
REGISTER NAME
REGISTER DESCRIPTION
1Ch
DEVICE_CFG
MUX sequence configuration and device status bits
Analog input channel selection in manual mode (see the Manual Mode
section)
1Dh
CHANNEL_ID
1Eh
1Fh
2Ah
SEQ_START
SEQ_STOP
Control for starting the multiplexer sequence
Control for aborting the multiplexer sequence
ON_THE_FLY_CFG
Enables or disables on-the-fly mode (see the On-The-Fly Mode section)
Channel selection register for auto sequence mode (see the Auto Sequence
Mode section)
80h
82h
AUTO_SEQ_CFG1
AUTO_SEQ_CFG2
Control for repeating the channels in auto sequence mode
7.6.4.1 DEVICE_CFG Register (address = 1Ch) [reset = 00h]
This register selects the mode of channel sequencing and reading this register returns device status information.
图 74. DEVICE_CFG Register
7
0
6
0
5
0
4
0
3
2
1
0
ALERT_STATUS
R-0b
ERROR_STATUS
R-0b
SEQ_MODE[1:0]
R/W-00b
R-0b
R-0b
R-0b
R-0b
表 31. DEVICE_CFG Register Field Descriptions
Bit
7-4
3
Field
Type
R
Reset
0000b
0b
Description
0
Reserved bits. Do not write. Reads return 0000b.
ALERT_STATUS
ERROR_STATUS
R
Read only. This bit reflects the ALERT pin logic level.
2
R
0b
Read only. This bit indicates a device configuration error:
0b = No error
1b = Error in configuration
1-0
SEQ_MODE[1:0]
R/W
00b
Sets the MUX channel selection operation:
00b = Manual mode
01b = On-the-fly mode
10b = Auto sequence mode
11b = Custom channel sequencing mode (see the Custom Channel
Sequencing Mode section)
表 32 describes how the ALERT_STATUS, ERROR_STATUS, and SEQ_MODE[1:0] bits can be collectively
decoded to indicate events.
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表 32. Decoding the DEVICE_CFG Read Value
ALERT_STATUS
ERROR_STATUS
SEQ_MODE[1:0]
EVENT DESCRIPTION
0
0
0
0
0
0
00
01
10
No ALERT, no error, manual mode
No ALERT, no error, on-the-fly mode
No ALERT, no error, auto sequence mode
No ALERT, no error, custom channel sequencing
mode
0
0
11
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
00
01
10
11
00
01
10
11
00
01
10
11
No ALERT, error, manual mode
No ALERT, error, on-the-fly mode
No ALERT, error, auto sequence mode
No ALERT, error, custom channel sequencing mode
ALERT, no error, manual mode
ALERT, no error, on-the-fly mode
ALERT, no error, auto sequence mode
ALERT, no error, custom channel sequencing mode
ALERT, error, manual mode
ALERT, error, on-the-fly mode
ALERT, error, auto sequence mode
ALERT, error, custom channel sequencing mode
7.6.4.2 CHANNEL_ID Register (address = 1Dh) [reset = 00h]
This register selects the analog input channel; see the Manual Mode section.
图 75. CHANNEL_ID Register
7
0
6
0
5
0
4
0
3
0
2
1
0
CHANNEL_ID[2:0]
R/W-000b
R-0b
R-0b
R-0b
R-0b
R-0b
表 33. CHANNEL_ID Register Field Descriptions
Bit
Field
Type
R
Reset
0 0000b Reserved bits. Reads return 0 0000b.
000b These bits select the analog input channel as per 表 34.
Description
7-3
2-0
0
CHANNEL_ID[2:0]
R/W
表 34. Analog Input Channel Selection Settings
CHANNEL_ID[2:0]
ANALOG INPUT SELECTED
000b
001b
010b
011b
100b
101b
110b
111b
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
注
Writing to the CHANNEL_ID register when the device is actively operating in auto
sequence mode or custom channel sequencing mode aborts the on-going sequence and
the DEVICE_CFG register is set to manual mode.
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7.6.4.3 SEQ_START Register (address = 1Eh) [reset = 00h]
This register starts the channel selection sequence when in auto sequence mode or custom channel sequencing
mode. Writing to this register has no effect when in manual mode or on-the-fly mode.
图 76. SEQ_START Register
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
SEQ_START
W-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
表 35. SEQ_START Register Field Descriptions
Bit
Field
Type
R
Reset
0b
Description
7-1
0
0
Reserved bits. Do not write.
SEQ_START
W
0b
This bit starts the channel scanning sequence when SEQ_MODE[1:0] =
auto sequence mode or custom channel sequencing mode.
0b = No effect; any on-going sequence is not stopped
1b = Start channel sequence
7.6.4.4 SEQ_ABORT Register (address = 1Fh) [reset = 00h]
This register stops the channel selection sequence when in auto channel sequence mode or custom channel
sequencing mode. Writing to this register has no effect when in manual mode or on-the-fly mode.
图 77. SEQ_ABORT Register
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
SEQ_ABORT
W-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
表 36. SEQ_ABORT Register Field Descriptions
Bit
Field
Type
R
Reset
0b
Description
7-1
0
0
Reserved bits. Do not write.
SEQ_ABORT
W
0b
This bit stops the channel scanning sequence when SEQ_MODE[1:0] =
auto sequence mode or custom channel sequencing mode.
0b = No effect
1b = Stop channel sequence
7.6.4.5 ON_THE_FLY_CFG Register (address = 2Ah) [reset = 00h]
This register enables on-the-fly mode of operation. This mode of operation helps select analog input channels
without having to write to device configuration registers.
图 78. ON_THE_FLY_CFG Register
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
EN_ON_THE_FLY
R/W-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
表 37. ON_THE_FLY_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
R
000
Reserved bits. Reads return 000 0000b.
0000b
0
EN_ON_THE_FLY
R/W
0b
This bit enables on-the-fly mode.
0b = On-the-fly mode disabled
1b = On-the-fly mode enabled; the first five bits on SDI select the analog
input channel for next conversion (see 图 44)
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7.6.4.6 AUTO_SEQ_CFG1 Register (address = 80h) [reset = 00h]
This register selects the channels enabled for auto sequence mode.
图 79. AUTO_SEQ_CFG1 Register
7
6
5
4
3
2
1
0
EN_AIN7
R/W-0b
EN_AIN6
R/W-0b
EN_AIN5
R/W-0b
EN_AIN4
R/W-0b
EN_AIN3
R/W-0b
EN_AIN2
R/W-0b
EN_AIN1
R/W-0b
EN_AIN0
R/W-0b
表 38. AUTO_SEQ_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
EN_AIN7
R/W
0b
This bit enables analog input channel 7 in the auto channel sequence
mode; see the Auto Sequence Mode section.
0b = AIN7 is not enabled in the scanning sequence
1b = AIN7 is enabled in the scanning sequence
6
5
4
3
2
1
0
EN_AIN6
EN_AIN5
EN_AIN4
EN_AIN3
EN_AIN2
EN_AIN1
EN_AIN0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b
0b
0b
This bit enables analog input channel 6 in the auto sequence mode.
0b = AIN6 is not enabled in the scanning sequence
1b = AIN6 is enabled in the scanning sequence
This bit enables analog input channel 5 in the auto sequence mode.
0b = AIN5 is not enabled in the scanning sequence
1b = AIN5 is enabled in the scanning sequence
This bit enables analog input channel 4 in the auto sequence mode.
0b = AIN4 is not enabled in the scanning sequence
1b = AIN4 is enabled in the scanning sequence
This bit enables analog input channel 3 in the auto sequence mode.
0b = AIN3 is not enabled in the scanning sequence
1b = AIN3 is enabled in the scanning sequence
This bit enables analog input channel 2 in the auto sequence mode.
0b = AIN2 is not enabled in the scanning sequence
1b = AIN2 is enabled in the scanning sequence
This bit enables analog input channel 1 in the auto sequence mode.
0b = AIN1 is not enabled in the scanning sequence
1b = AIN1 is enabled in the scanning sequence
This bit enables analog input channel 0 in the auto sequence mode.
0b = AIN0 is not enabled in the scanning sequence
1b = AIN0 is enabled in the scanning sequence
7.6.4.7 AUTO_SEQ_CFG2 Register (address = 82h) [reset = 00h]
This register enables the sequence loop for auto sequence mode.
图 80. AUTO_SEQ_CFG2 Register
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
AUTO_REPEAT
R/W-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
表 39. AUTO_SEQ_CFG2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
R
000
Reserved bits. Reads return 000 0000b.
0000b
0
AUTO_REPEAT
R/W
0b
This bit enables looping the sequence indefinitely in auto sequence
mode.
0b = Sequence terminates after all enabled channels are scanned
1b = Sequence repeats after scanning all enabled channels
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7.6.4.8 Custom Channel Sequencing Mode Registers
表 20 maps the device features for the custom channel sequencing mode registers; see the Custom Channel
Sequencing Mode section for mode details.
表 40. Custom Channel Sequencing Registers
ADDRESS
88h
REGISTER NAME
CCS_START_INDEX
CCS_END_INDEX
REGISTER DESCRIPTION
Start index for the custom channel sequencing mode sequence
End index for the custom channel sequencing mode sequence
Custom channel sequencing mode loop control
Channel ID configuration register index 0
Repeat count register index 0
89h
8Ah
8Ch
8Dh
8Eh
8Fh
90h
CCS_SEQ_LOOP
CCS_CHID_INDEX_0
REPEAT_INDEX_0
CCS_CHID_INDEX_1
REPEAT_INDEX_1
CCS_CHID_INDEX_2
REPEAT_INDEX_2
CCS_CHID_INDEX_3
REPEAT_INDEX_3
CCS_CHID_INDEX_4
REPEAT_INDEX_4
CCS_CHID_INDEX_5
REPEAT_INDEX_5
CCS_CHID_INDEX_6
REPEAT_INDEX_6
CCS_CHID_INDEX_7
REPEAT_INDEX_7
CCS_CHID_INDEX_8
REPEAT_INDEX_8
CCS_CHID_INDEX_9
REPEAT_INDEX_9
CCS_CHID_INDEX_10
REPEAT_INDEX_10
CCS_CHID_INDEX_11
REPEAT_INDEX_11
CCS_CHID_INDEX_12
REPEAT_INDEX_12
CCS_CHID_INDEX_13
REPEAT_INDEX_13
CCS_CHID_INDEX_14
REPEAT_INDEX_14
CCS_CHID_INDEX_15
REPEAT_INDEX_15
Channel ID configuration register index 1
Repeat count register index 1
Channel ID configuration register index 2
Repeat count register index 2
91h
92h
Channel ID configuration register index 3
Repeat count register index 3
93h
94h
Channel ID configuration register index 4
Repeat count register index 4
95h
96h
Channel ID configuration register index 5
Repeat count register index 5
97h
98h
Channel ID configuration register index 6
Repeat count register index 6
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
A1h
A2h
A3h
A4h
A5h
A6h
A7h
A8h
A9h
AAh
ABh
Channel ID configuration register index 7
Repeat count register index 7
Channel ID configuration register index 8
Repeat count register index 8
Channel ID configuration register index 9
Repeat count register index 9
Channel ID configuration register index 10
Repeat count register index 10
Channel ID configuration register index 11
Repeat count register index 11
Channel ID configuration register index 12
Repeat count register index 12
Channel ID configuration register index 13
Repeat count register index 13
Channel ID configuration register index 14
Repeat count register index 14
Channel ID configuration register index 15
Repeat count register index 15
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7.6.4.8.1 CCS_START_INDEX Register (address = 88h) [reset = 00h]
This register sets the relative sequence index where the custom channel sequencing mode starts execution from.
图 81. CCS_START_INDEX Register
7
0
6
0
5
0
4
0
3
2
1
0
SEQ_START_INDEX[3:0]
R/W-0000b
R-0b
R-0b
R-0b
R-0b
表 41. CCS_START_INDEX Register Field Descriptions
Bit
Field
Type
R
Reset
0000b
0000b
Description
7-4
3-0
0
Reserved bits. Reads return 0000b.
SEQ_START_INDEX[3:0]
R/W
Relative pointer to the index for the start of the sequence in custom
channel sequencing mode.
7.6.4.8.2 CCS_END_INDEX Register (address = 89h) [reset = 00h]
This register sets the relative sequence index where the custom channel sequencing mode stops execution at.
The value in the CCS_END_INDEX register must not be less than the value in the CCS_START_INDEX register.
图 82. CCS_END_INDEX Register
7
0
6
0
5
0
4
0
3
2
1
0
SEQ_END_INDEX[3:0]
R/W-0000b
R-0b
R-0b
R-0b
R-0b
表 42. CCS_END_INDEX Register Field Descriptions
Bit
Field
Type
R
Reset
0000b
0000b
Description
7-4
3-0
0
Reserved bits. Reads return 0000b.
SEQ_END_INDEX[3:0]
R/W
Relative pointer to the index for the end of the sequence in custom
channel sequencing mode.
7.6.4.8.3 CCS_SEQ_LOOP Register (address = 8Bh) [reset = 00h]
This register controls the looping of the sequence in custom channel sequencing mode.
图 83. CCS_SEQ_LOOP Register
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
SEQ_LOOP
R/W-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
表 43. CCS_SEQ_LOOP Register Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
R
000
Reserved bits. Reads return 000 0000b.
0000b
0
SEQ_LOOP
R/W
0b
Configures the looping of sequence in custom channel sequencing mode.
0b = Sequence ends at the index location configured in the
CCS_END_INDEX[3:0] bits; see the CCS_END_INDEX register
1b = Sequence resumes from the CCS_START_INDEX[3:0] bits (see the
CCS_START_INDEX register) after executing the CCS_END_INDEX[3:0]
bits.
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7.6.4.8.4 CCS_CHID_INDEX_m Registers (address = 8C, 8E, 90, 92, 94, 96, 98, 9A, 9C, 9E, A0, A2, A4, A6, A8, and
AAh) [reset = 00h]
In custom channel sequencing mode, the intended sequence of the analog input channels can be programmed in
these 16 registers. See the REPEAT_INDEX_m registers for details about repeating a particular channel before
switching to the next index.
图 84. CCS_CHID_INDEX_m Register
7
0
6
0
5
0
4
0
3
0
2
1
0
CHID[2:0]
R/W-000b
R-0b
R-0b
R-0b
R-0b
R-0b
表 44. CCS_CHID_INDEX_m Register Field Descriptions
Bit
Field
0
Type
R
Reset
Description
7-3
2-0
0 0000b Reserved bits. Reads return 0 0000b.
CHID[2:0]
R/W
000b
These bits configure the analog input channel associated with the index in
custom channel sequencing mode.
000b = AIN0
001b = AIN1
010b = AIN2
011b = AIN3
100b = AIN4
101b = AIN5
110b = AIN6
111b = AIN7
7.6.4.8.5 REPEAT_INDEX_m Registers (address = 8D, 8F, 91, 93, 95, 97, 99, 9B, 9D, 9F, A1, A3, A5, A7, A9, and ABh)
[reset = 00h]
In custom channel sequencing mode, the analog input selected in the corresponding CCS_CHID_INDEX register
can be repeated by configuring the respective register.
图 85. REPEAT_INDEX_m Register
7
6
5
4
3
2
1
0
REPEAT[7:0]
R/W-1111 1111b
表 45. REPEAT_INDEX_m Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
REPEAT[7:0]
R/W
1111
1111b
These bits configure the number of times the analog input configured in
the corresponding CCS_CHID_INDEX register is repeated. Configuring
0000 0000b in this register results in an error.
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7.6.5 Digital Window Comparator Configuration Registers Map
表 46 maps the device features for the digital window comparator; see the Digital Window Comparator section.
表 46. Digital Window Comparator Configuration Registers Mapping
ADDRESS
2Eh
REGISTER NAME
ALERT_CFG
REGISTER DESCRIPTION
ALERT enable control for individual analog input channels
High threshold input for the AIN7 digital window comparator
High threshold input for the AIN6 digital window comparator
High threshold input for AIN5 digital window comparator
High threshold input for the AIN4 digital window comparator
High threshold input for the AIN3 digital window comparator
High threshold input for the AIN2 digital window comparator
High threshold input for the AIN1 digital window comparator
High threshold input for the AIN0 digital window comparator
Low threshold input for the AIN7 digital window comparator
Low threshold input for the AIN6 digital window comparator
Low threshold input for the AIN5 digital window comparator
Low threshold input for the AIN4 digital window comparator
Low threshold input for the AIN3 digital window comparator
Low threshold input for the AIN2 digital window comparator
Low threshold input for the AIN1 digital window comparator
Low threshold input for the AIN0 digital window comparator
Threshold hysteresis for the AIN7 digital window comparator
Threshold hysteresis for the AIN6 digital window comparator
Threshold hysteresis for the AIN5 digital window comparator
Threshold hysteresis for the AIN4 digital window comparator
Threshold hysteresis for the AIN3 digital window comparator
Threshold hysteresis for the AIN2 digital window comparator
Threshold hysteresis for the AIN1 digital window comparator
Threshold hysteresis for the AIN0 digital window comparator
31h and 30h
35h and 34h
39h and 38h
3Dh and 3Ch
41h and 40h
45h and 44h
49h and 48h
4Dh and 4Ch
55h and 54h
59h and 58h
5Dh and 5Ch
61h and 60h
65h and 64h
69h and 68h
6Dh and 6Ch
71h and 70h
33h
HI_TRIG_AIN7
HI_TRIG_AIN6
HI_TRIG_AIN5
HI_TRIG_AIN4
HI_TRIG_AIN3
HI_TRIG_AIN2
HI_TRIG_AIN1
HI_TRIG_AIN0
LO_TRIG_AIN7
LO_TRIG_AIN6
LO_TRIG_AIN5
LO_TRIG_AIN4
LO_TRIG_AIN3
LO_TRIG_AIN2
LO_TRIG_AIN1
LO_TRIG_AIN0
HYSTERESIS_AIN7
HYSTERESIS_AIN6
HYSTERESIS_AIN5
HYSTERESIS_AIN4
HYSTERESIS_AIN3
HYSTERESIS_AIN2
HYSTERESIS_AIN1
HYSTERESIS_AIN0
37h
3Bh
3Fh
43h
47h
4Bh
4Fh
Indicates the analog input channel-wise ALERT resulting from a low
threshold
78h
ALERT_LO_STATUS
Indicates the analog input channel-wise ALERT resulting from a high
threshold
79h
7Ah
7Ch
ALERT_HI_STATUS
ALERT_STATUS
Indicates the analog input channel-wise ALERT status
Indicates the analog input channel-wise ALERT resulting from a low
threshold for the last conversion data
CURR_ALERT_LO_STATUS
Indicates the analog input channel-wise ALERT resulting from a high
threshold for the last conversion data
7Dh
7Eh
CURR_ALERT_HI_STATUS
CURR_ALERT_STATUS
Indicates the analog input channel-wise ALERT status for the last
conversion data
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7.6.5.1 ALERT_CFG Register (address = 2Eh) [reset = 00h]
This register enables or disables the digital window comparator for the individual analog input channels.
图 86. ALERT_CFG Register
7
6
5
4
3
2
1
0
ALERT_EN_
AIN7
ALERT_EN_
AIN6
ALERT_EN_
AIN5
ALERT_EN_
AIN4
ALERT_EN_
AIN3
ALERT_EN_
AIN2
ALERT_EN_
AIN1
ALERT_EN_
AIN0
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
表 47. ALERT_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
ALERT_EN_AIN7
ALERT_EN_AIN6
ALERT_EN_AIN5
ALERT_EN_AIN4
ALERT_EN_AIN3
ALERT_EN_AIN2
ALERT_EN_AIN1
ALERT_EN_AIN0
R/W
0b
Digital window comparator control for AIN7.
0b = Digital window comparator disabled
1b = Digital window comparator enabled
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b
0b
0b
Digital window comparator control for AIN6.
0b = Digital window comparator disabled
1b = Digital window comparator enabled
Digital window comparator control for AIN5.
0b = Digital window comparator disabled
1b = Digital window comparator enabled
Digital window comparator control for AIN4.
0b = Digital window comparator disabled
1b = Digital window comparator enabled
Digital window comparator control for AIN3.
0b = Digital window comparator disabled
1b = Digital window comparator enabled
Digital window comparator control for AIN2.
0b = Digital window comparator disabled
1b = Digital window comparator enabled
Digital window comparator control for AIN1.
0b = Digital window comparator disabled
1b = Digital window comparator enabled
Digital window comparator control for AIN0.
0b = Digital window comparator disabled
1b = Digital window comparator enabled
When the digital window comparator is disabled, the bits corresponding to the disabled digital window
comparator are not updated in the ALERT_STATUS, ALERT_HI_STATUS, ALERT_LO_STATUS,
CURR_ALERT_STATUS, CURR_ALERT_HI_STATUS, or CURR_ALERT_LO_STATUS registers.
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7.6.5.2 HI_TRIG_AINx[15:0] Register (address = 4Dh to 30h) [reset = 0000h]
This bank of registers configures the high threshold for the digital window comparator. For 16-bit ADC data
output, the comparator thresholds are 16-bits wide and are spread over two 8-bit registers. Use the registers
listed in 表 48 to configure the high threshold for the individual analog input channels.
表 48. HI_TRIG_AINx[15:0] Register Address Map(1)
ANALOG INPUT
AIN7
REGISTER ADDRESS FOR HI_TRIG_AINx[15:8]
REGISTER ADDRESS FOR HI_TRIG_AINx[7:0]
031h
035h
039h
03Dh
041h
045h
049h
04Dh
030h
034h
038h
03Ch
040h
044h
048h
04Ch
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
AIN0
(1) AINx refers to analog inputs channels AIN0, AIN1, AIN2, AIN3, AIN4, AIN5, AIN6, and AIN7.
图 87. MSB Byte Register for HI_TRIG_AINx[15:8]
7
6
5
4
3
2
1
1
0
0
HI_TRIG[15:8]
R/W-0000 0000b
图 88. LSB Byte Register for HI_TRIG_AINx[7:0]
7
6
5
4
3
2
HI_TRIG[7:0]
R/W-0000 0000b
表 49. HI_TRIG_AINx[15:0] Registers Field Descriptions
Bit
Field
HI_TRIG[15:0]
Type
Reset
Description
High threshold for the digital window comparator
15:0
R/W
0000
0000
0000
0000b
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7.6.5.3 LO_TRIG_AINx[15:0] Register (address = 71h to 54h) [reset = 0000h]
This bank of registers configures the low threshold for the digital window comparator. For 16-bit ADC data output,
the comparator thresholds are 16-bits wide and are spread over two 8-bit registers. Use the registers listed in 表
50 to configure the low threshold for the individual analog input channels
表 50. LO_TRIG_AINx[15:0] Register Address Map(1)
ANALOG INPUT
AIN7
REGISTER ADDRESS FOR LO_TRIG_AINx[15:8]
REGISTER ADDRESS FOR LO_TRIG_AINx[7:0]
051h
059h
05Dh
061h
065h
069h
06Dh
071h
054h
058h
05Ch
060h
064h
068h
06Ch
070h
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
AIN0
(1) AINx refers to analog inputs channels AIN0, AIN1, AIN2, AIN3, AIN4, AIN5, AIN6, and AIN7.
图 89. MSB Byte Register for LO_TRIG_AINx[15:8]
7
6
5
4
3
2
1
1
0
0
LO_TRIG[15:8]
R/W-0000 0000b
图 90. LSB Byte Register for LO_TRIG_AINx[7:0]
7
6
5
4
3
2
LO_TRIG[7:0]
R/W-0000 0000b
表 51. LO_TRIG_AINx[15:0] Registers Field Descriptions
Bit
Field
LO_TRIG[15:0]
Type
Reset
Description
Low threshold for the digital window comparator
15:0
R/W
0000
0000
0000
0000b
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7.6.5.4 HYSTERESIS_AINx[7:0] Register (address = 4Fh to 33h) [reset = 00h]
This bank of registers configures the hysteresis around the high and low thresholds for the digital window
comparator. For 16-bit ADC data output, the hysteresis is six bits wide.
图 91. HYSTERESIS_AINx[7:0] Registers
7
6
5
4
3
2
1
0
0
0
HYSTERESIS[5:0]
R/W-00 0000b
R-0b
R-0b
表 52. HYSTERESIS_AINx[7:0](1) Register Field Descriptions
Bit
Field
HYSTERESIS[5:0]
Type
Reset
Description
Low threshold for the digital window comparator
7:2
R/W
000
0000b
(1) AINx refers to analog inputs channels AIN0, AIN1, AIN2, AIN3, AIN4, AIN5, AIN6, and AIN7.
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7.6.5.5 ALERT_LO_STATUS Register (address = 78h) [reset = 00h]
This register reflects the status of the ALERT pin resulting from the low thresholds of the respective analog input
channels.
图 92. ALERT_LO_STATUS Register
7
6
5
4
3
2
1
0
ALERT_LO_
AIN7
ALERT_LO_
AIN6
ALERT_LO_
AIN5
ALERT_LO_
AIN4
ALERT_LO_
AIN3
ALERT_LO_
AIN2
ALERT_LO_
AIN1
ALERT_LO_
AIN0
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
表 53. ALERT_LO_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7
ALERT_LO_AIN7
ALERT_LO_AIN6
ALERT_LO_AIN5
ALERT_LO_AIN4
ALERT_LO_AIN3
ALERT_LO_AIN2
ALERT_LO_AIN1
ALERT_LO_AIN0
R/W
0b
This bit indicates that the low threshold for AIN7 has been exceeded.
0b = Low threshold is not exceeded
1b = Low threshold has been exceeded; clear this bit by writing 1b
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b
0b
0b
This bit indicates that the low threshold for AIN6 has been exceeded.
0b = Low threshold is not exceeded
1b = Low threshold has been exceeded; clear this bit by writing 1b
This bit indicates that the low threshold for AIN5 has been exceeded.
0b = Low threshold is not exceeded
1b = Low threshold has been exceeded; clear this bit by writing 1b
This bit indicates that the low threshold for AIN4 has been exceeded.
0b = Low threshold is not exceeded
1b = Low threshold has been exceeded; clear this bit by writing 1b
This bit indicates that the low threshold for AIN3 has been exceeded.
0b = Low threshold is not exceeded
1b = Low threshold has been exceeded; clear this bit by writing 1b
This bit indicates that the low threshold for AIN2 has been exceeded.
0b = Low threshold is not exceeded
1b = Low threshold has been exceeded; clear this bit by writing 1b
This bit indicates that the low threshold for AIN1 has been exceeded.
0b = Low threshold is not exceeded
1b = Low threshold has been exceeded; clear this bit by writing 1b
This bit indicates that the low threshold for AIN0 has been exceeded.
0b = Low threshold is not exceeded
1b = Low threshold has been exceeded; clear this bit by writing 1b
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7.6.5.6 ALERT_HI_STATUS Register (address = 79h) [reset = 00h]
This register reflects the status of the ALERT pin resulting from the high thresholds of the respective analog input
channels.
图 93. ALERT_HI_STATUS Register
7
6
5
4
3
2
1
0
ALERT_HI_
AIN7
ALERT_HI_
AIN6
ALERT_HI_
AIN5
ALERT_HI_
AIN4
ALERT_HI_
AIN3
ALERT_HI_
AIN2
ALERT_HI_
AIN1
ALERT_HI_
AIN0
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
表 54. ALERT_HI_STATUS Register Field Descriptions
Bit
Field
ALERT_HI_AIN7
Type
Reset
Description
7
R/W
0b
This bit indicates that the high threshold for AIN7 has been exceeded.
0b = High threshold is not exceeded
1b = High threshold has been exceeded; clear this bit by writing 1b
6
5
4
3
2
1
0
ALERT_HI_AIN6
ALERT_HI_AIN5
ALERT_HI_AIN4
ALERT_HI_AIN3
ALERT_HI_AIN2
ALERT_HI_AIN1
ALERT_HI_AIN0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b
0b
0b
This bit indicates that the high threshold for AIN6 has been exceeded.
0b = High threshold is not exceeded
1b = High threshold has been exceeded; clear this bit by writing 1b
This bit indicates that the high threshold for AIN5 has been exceeded.
0b = High threshold is not exceeded
1b = High threshold has been exceeded; clear this bit by writing 1b
This bit indicates that the high threshold for AIN4 has been exceeded.
0b = High threshold is not exceeded
1b = High threshold has been exceeded; clear this bit by writing 1b
This bit indicates that the high threshold for AIN3 has been exceeded.
0b = High threshold is not exceeded
1b = High threshold has been exceeded; clear this bit by writing 1b
This bit indicates that the high threshold for AIN2 has been exceeded.
0b = High threshold is not exceeded
1b = High threshold has been exceeded; clear this bit by writing 1b
This bit indicates that the high threshold for AIN1 has been exceeded.
0b = High threshold is not exceeded
1b = High threshold has been exceeded; clear this bit by writing 1b
This bit indicates that the high threshold for AIN0 has been exceeded.
0b = High threshold is not exceeded
1b = High threshold has been exceeded; clear this bit by writing 1b
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7.6.5.7 ALERT_STATUS Register (address = 7Ah) [reset = 00h]
This register reflects the ALERT status for the analog input channels.
图 94. ALERT_STATUS Register
7
6
5
4
3
2
1
0
ALERT_AIN7
R-0b
ALERT_AIN6
R-0b
ALERT_AIN5
R-0b
ALERT_AIN4
R-0b
ALERT_AIN3
R-0b
ALERT_AIN2
R-0b
ALERT_AIN1
R-0b
ALERT_AIN0
R-0b
表 55. ALERT_STATUS Register Field Descriptions
Bit
Field
ALERT_AIN7
Type
Reset
Description
7
R
0b
This bit indicates if either the high or low threshold for AIN7 has been
exceeded.
0b = Neither the high are low threshold have been exceeded
1b = Either the high threshold, the low threshold, or both thresholds have
been exceeded
6
5
4
3
2
1
0
ALERT_AIN6
ALERT_AIN5
ALERT_AIN4
ALERT_AIN3
ALERT_AIN2
ALERT_AIN1
ALERT_AIN0
R
R
R
R
R
R
R
0b
0b
0b
0b
0b
0b
0b
This bit indicates if either the high or low threshold for AIN6 has been
exceeded.
0b = Neither the high are low threshold have been exceeded
1b = Either the high threshold, the low threshold, or both thresholds have
been exceeded
This bit indicates if either the high or low threshold for AIN5 has been
exceeded.
0b = Neither the high are low threshold have been exceeded
1b = Either the high threshold, the low threshold, or both thresholds have
been exceeded
This bit indicates if either the high or low threshold for AIN4 has been
exceeded.
0b = Neither the high are low threshold have been exceeded
1b = Either the high threshold, the low threshold, or both thresholds have
been exceeded
This bit indicates if either the high or low threshold for AIN3 has been
exceeded.
0b = Neither the high are low threshold have been exceeded
1b = Either the high threshold, the low threshold, or both thresholds have
been exceeded
This bit indicates if either the high or low threshold for AIN2 has been
exceeded.
0b = Neither the high are low threshold have been exceeded
1b = Either the high threshold, the low threshold, or both thresholds have
been exceeded
This bit indicates if either the high or low threshold for AIN1 has been
exceeded.
0b = Neither the high are low threshold have been exceeded
1b = Either the high threshold, the low threshold, or both thresholds have
been exceeded
This bit indicates if either the high or low threshold for AIN0 has been
exceeded.
0b = Neither the high are low threshold have been exceeded
1b = Either the high threshold, the low threshold, or both thresholds have
been exceeded
If the ALERT bit for a particular channel is set in the ALERT_STATUS register, then the ALERT bit can be
cleared by writing 1b to the corresponding bit in the ALERT_HI_STATUS or ALERT_LO_STATUS registers. If
both the high and low thresholds have been exceeded for a particular analog input channel, then the
corresponding ALERT bit in both the ALERT_HI_STATUS or ALERT_LO_STATUS registers must be set to 1b to
clear the ALERT bit.
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7.6.5.8 CURR_ALERT_LO_STATUS Register (address = 7Ch) [reset = 00h]
This register reflects the low threshold ALERT status for the analog input channels. The bits in this register are
updated after every conversion.
图 95. CURR_ALERT_LO_STATUS Register
7
6
5
4
3
2
1
0
ALERT_LO_
AIN7
ALERT_LO_
AIN6
ALERT_LO_
AIN5
ALERT_LO_
AIN4
ALERT_LO_
AIN3
ALERT_LO_
AIN2
ALERT_LO_
AIN1
ALERT_LO_
AIN0
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
表 56. CURR_ALERT_LO_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7
ALERT_LO_AIN7
ALERT_LO_AIN6
ALERT_LO_AIN5
ALERT_LO_AIN4
ALERT_LO_AIN3
ALERT_LO_AIN2
ALERT_LO_AIN1
ALERT_LO_AIN0
R
0b
This bit indicates if the low threshold for AIN7 has been exceeded by the
last converted data from channel AIN7.
0b = High threshold is not exceeded
1b = Low threshold has been exceeded
6
5
4
3
2
1
0
R
R
R
R
R
R
R
0b
0b
0b
0b
0b
0b
0b
This bit indicates if the low threshold for AIN6 has been exceeded by the
last converted data from channel AIN7.
0b = High threshold is not exceeded
1b = Low threshold has been exceeded
This bit indicates if the low threshold for AIN5 has been exceeded by the
last converted data from channel AIN7.
0b = High threshold is not exceeded
1b = Low threshold has been exceeded
This bit indicates if the low threshold for AIN4 has been exceeded by the
last converted data from channel AIN7.
0b = High threshold is not exceeded
1b = Low threshold has been exceeded
This bit indicates if the low threshold for AIN3 has been exceeded by the
last converted data from channel AIN7.
0b = High threshold is not exceeded
1b = Low threshold has been exceeded
This bit indicates if the low threshold for AIN2 has been exceeded by the
last converted data from channel AIN7.
0b = High threshold is not exceeded
1b = Low threshold has been exceeded
This bit indicates if the low threshold for AIN1 has been exceeded by the
last converted data from channel AIN7.
0b = High threshold is not exceeded
1b = Low threshold has been exceeded
This bit indicates if the low threshold for AIN0 has been exceeded by the
last converted data from channel AIN7.
0b = High threshold is not exceeded
1b = Low threshold has been exceeded
The status of the individual bits in this register is evaluated after every conversion. The contents of this register
can be used to ascertain if the last output data are within the specified high threshold for the respective analog
input channels.
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7.6.5.9 CURR_ALERT_HI_STATUS Register (address = 7Dh) [reset = 00h]
This register reflects the high threshold ALERT status for the analog input channels. The bits in this register are
updated after every conversion.
图 96. CURR_ALERT_HI_STATUS Register
7
6
5
4
3
2
1
0
ALERT_HI_
AIN7
ALERT_HI_
AIN6
ALERT_HI_
AIN5
ALERT_HI_
AIN4
ALERT_HI_
AIN3
ALERT_HI_
AIN2
ALERT_HI_
AIN1
ALERT_HI_
AIN0
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
表 57. CURR_ALERT_HI_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7
ALERT_HI_AIN7
ALERT_HI_AIN6
ALERT_HI_AIN5
ALERT_HI_AIN4
ALERT_HI_AIN3
ALERT_HI_AIN2
ALERT_HI_AIN1
ALERT_HI_AIN0
R
0b
This bit indicates if the high threshold for AIN7 has been exceeded by the
last converted data from channel AIN7.
0b = High threshold is not exceeded
1b = High threshold has been exceeded
6
5
4
3
2
1
0
R
R
R
R
R
R
R
0b
0b
0b
0b
0b
0b
0b
This bit indicates if the high threshold for AIN6 has been exceeded by the
last converted data from channel AIN7.
0b = High threshold is not exceeded
1b = High threshold has been exceeded
This bit indicates if the high threshold for AIN5 has been exceeded by the
last converted data from channel AIN7.
0b = High threshold is not exceeded
1b = High threshold has been exceeded
This bit indicates if the high threshold for AIN4 has been exceeded by the
last converted data from channel AIN7.
0b = High threshold is not exceeded
1b = High threshold has been exceeded
This bit indicates if the high threshold for AIN3 has been exceeded by the
last converted data from channel AIN7.
0b = High threshold is not exceeded
1b = High threshold has been exceeded
This bit indicates if the high threshold for AIN2 has been exceeded by the
last converted data from channel AIN7.
0b = High threshold is not exceeded
1b = High threshold has been exceeded
This bit indicates if the high threshold for AIN1 has been exceeded by the
last converted data from channel AIN7.
0b = High threshold is not exceeded
1b = High threshold has been exceeded
This bit indicates if the high threshold for AIN0 has been exceeded by the
last converted data from channel AIN7.
0b = High threshold is not exceeded
1b = High threshold has been exceeded
The status of the individual bits in this register is evaluated after every conversion. The contents of this register
can be used to ascertain if the last output data are within the specified high threshold for the respective analog
input channels.
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7.6.5.10 CURR_ALERT_STATUS Register (address = 7Eh) [reset = 00h]
This register reflects the ALERT pin status for the analog input channels. The bits in this register are updated
after every conversion.
图 97. CURR_ALERT_STATUS Register
7
6
5
4
3
2
1
0
ALERT_AIN7
R-0b
ALERT_AIN6
R-0b
ALERT_AIN5
R-0b
ALERT_AIN4
R-0b
ALERT_AIN3
R-0b
ALERT_AIN2
R-0b
ALERT_AIN1
R-0b
ALERT_AIN0
R-0b
表 58. CURR_ALERT_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7
ALERT_AIN7
ALERT_AIN6
ALERT_AIN5
ALERT_AIN4
ALERT_AIN3
ALERT_AIN2
ALERT_AIN1
ALERT_AIN0
R
0b
This bit indicates that either the high or low threshold for AIN7 has been
exceeded by the last converted data from channel AIN7.
0b = Neither the high or low threshold have been exceeded
1b = Either the high threshold, the low threshold, or both thresholds have
been exceeded
6
5
4
3
2
1
0
R
R
R
R
R
R
R
0b
0b
0b
0b
0b
0b
0b
This bit indicates that either the high or low threshold for AIN6 has been
exceeded by the last converted data from channel AIN7.
0b = Neither the high or low threshold have been exceeded
1b = Either the high threshold, the low threshold, or both thresholds have
been exceeded
This bit indicates that either the high or low threshold for AIN5 has been
exceeded by the last converted data from channel AIN7.
0b = Neither the high or low threshold have been exceeded
1b = Either the high threshold, the low threshold, or both thresholds have
been exceeded
This bit indicates that either the high or low threshold for AIN4 has been
exceeded by the last converted data from channel AIN7.
0b = Neither the high or low threshold have been exceeded
1b = Either the high threshold, the low threshold, or both thresholds have
been exceeded
This bit indicates that either the high or low threshold for AIN3 has been
exceeded by the last converted data from channel AIN7.
0b = Neither the high or low threshold have been exceeded
1b = Either the high threshold, the low threshold, or both thresholds have
been exceeded
This bit indicates that either the high or low threshold for AIN2 has been
exceeded by the last converted data from channel AIN7.
0b = Neither the high or low threshold have been exceeded
1b = Either the high threshold, the low threshold, or both thresholds have
been exceeded
This bit indicates that either the high or low threshold for AIN1 has been
exceeded by the last converted data from channel AIN7.
0b = Neither the high or low threshold have been exceeded
1b = Either the high threshold, the low threshold, or both thresholds have
been exceeded
This bit indicates that either the high or low threshold for AIN0 has been
exceeded by the last converted data from channel AIN7.
0b = Neither the high or low threshold have been exceeded
1b = Either the high threshold, the low threshold, or both thresholds have
been exceeded
Bits in this register reflect the result of the logical OR of the corresponding channel bits in the
CURR_ALERT_HI_STATUS and CURR_ALERT_LO_STATUS registers. The status of the individual bits in this
register is evaluated after every conversion. The contents of this register can be used to ascertain if the last
output data are within the specified high and low thresholds for the respective analog input channels.
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Multiplexer Input Connection
Conventional multichannel ADC solutions internally connect the multiplexer output directly to the switched
capacitor input of the ADC. Conventionally, a wide bandwidth amplifier is required for each channel. For the
ADS816x, only one amplifier is required for many applications. The ADS816x solution shown in 图 98 has lower
power, a smaller PCB area, and lower cost compared to the comparative solution. Furthermore, from a
calibration perspective, the offset error in the ADS816x solution is the same in each channel and is set by the
multiplexer output amplifier. The offset error in the conventional solution, on the other hand, is different for each
channel. Calibrating the offset error for the conventional solution also requires a separate calibration for each
channel.
High Bandwidth Amplifier
OPA320
VIN0
AIN0
ADC-INP
AIN0
VIN1
VIN2
AIN1
AIN2
VIN0
+
+
ADC
AIN1
AIN2
+
ADC
MUXOUT-P
VIN7
AIN7
AIN7
VIN7
Sequencer
ADS8168 Solution œ Single Wide Bandwidth Amplifier
Conventional Solution œ Eight Wide Bandwidth Amplifiers
图 98. Small-Size and Low-Power 8-Channel DAQ System Using the ADS816x
When connecting the sensor directly to the input of the ADS816x, the maximum switching speed of the
multiplexer is limited by multiplexer on-resistance and parasitic capacitance. 图 99 illustrates the source
resistance (RS0, RS1…), multiplexer impedance (RMUX), multiplexer capacitance (CMUX), op amp input
capacitance (COPA), and the stray PCB capacitance at the output of the multiplexer (CSTRAY). In this example, the
total output capacitance is the combination of the multiplexer output capacitance, the op amp input capacitance,
and the stray capacitance (CMUX + COPA + CSTRAY) = 15 pF. When switching to a channel, this capacitance must
be charged to the sensor output voltage via the source resistance and the multiplexer resistance (RS0 + RMUX).
公式 2 can be used to estimate the number of time constants required for N bits of settling. For this example, to
achieve 16-bit settling, 11.09 time constants are required. Thus, as computed in 公式 3 and 公式 4, for channel 0
the required settling time is 167 ns.
NTC = ln (216) = 11.09
(2)
(3)
(4)
Settling Time Required = (RS0 + RMUX) × (CMUX + COPA + CSTRAY) × NTC
Settling Time Required = (1 kΩ) × (15 pF) × 11.09 = 167 ns
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Application Information (接下页)
OPA320
RFLT
50ꢀ
RS1
50ꢀ
ADC-INP
SW
RMUX
40ꢀ
RS0
1000ꢀ
MUXOUT-P
AIN0
SW
+
CMUX
13pF
CFLT
1.2nF
CS1
60pF
AIN1
AIN2
SW
SW
COPA + CSTRAY
Sensor 0
CS2
60pF
RS7
1000ꢀ
RS2
50ꢀ
AIN7
SW
SW
ADC-INM
MUXOUT-M
RFLT
50ꢀ
CFLT
1.2nF
MUX
ADC
AIN-COM
Sensor 7
图 99. Direct Sensor Interface With the ADS816x in an 8-Channel, Single-Ended Configuration
When operating at 1 MSPS in either manual mode, auto sequence mode, or custom channel sequencing mode,
a 900-ns settling time is available at the analog inputs of the multiplexer; see the Early Switching for Direct
Sensor Interface section. Using 公式 4, the maximum sensor output impedance for a direct connection is 5.4 kΩ.
In some applications, such as temperature sensing, the sensor output impedance can be greater than 10 kΩ.
When scanning the multiplexer channels at high throughput, the relatively higher driving impedance results in a
settling error. In such cases, 图 100 shows that the multiplexer inputs can be driven using an amplifier. The
multiplexer outputs can be connected to the ADC inputs directly. For best distortion performance, an amplifier
can be used between the multiplexer and the ADC as described in the Selecting an ADC Input Buffer section.
MUXOUT-P
ADC-INP
RFLT_MUX
55 ꢀ
RS0
>10 kꢀ
AIN0
ADS816x
+
AIN1
AIN2
OPA320
CFLT_MUX
1 nF
ADC
Sensor 0
RFLT_MUX
55 ꢀ
RS7
>10 kꢀ
AIN7
+
OPA320
CFLT_MUX
1 nF
ADC-INM
MUXOUT-M
Sensor 7
图 100. High Output Impedance Sensor Interface
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Application Information (接下页)
8.1.2 Selecting an ADC Input Buffer
图 101 shows the external amplifier, charge bucket filter, and sample-and-hold circuit at the ADC input for the
ADS816x. Having a short background on the conversion process helps to understand the design procedure for
selecting the amplifier and RC filter. The conversion process is broken up into two phases: the acquisition phase
and the conversion phase. During the acquisition phase the SW switches are closed, and the input signal is
stored on the sample-and-hold capacitors, CS1 and CS2. After the acquisition phase, the switches opens and the
voltage stored on the capacitors is converted to a digital code by the SAR algorithm. This conversion process
depletes the charge on the sample-and-hold capacitors.
OPA320
RFLT
50ꢀ
RS1
50ꢀ
ADC-INP
SW
MUXOUT-P
+
CFLT
1.2nF
CS1
60pF
CS2
60pF
RS2
50ꢀ
SW
ADC-INM
MUXOUT-M
RFLT
50ꢀ
CFLT
1.2nF
ADC
图 101. Driving the ADC Inputs (ADC-INP and ADC-INM)
During subsequent acquisition cycles, the sample-and-hold capacitor must be charged to the ADC input voltage
that can make step changes in the value because each input may be from a different multiplexer channel. For
example, if AIN0 is connected to 4 V and AIN1 is connected to 0.5 V, the sample-and-hold capacitor must charge
to 4 V for the first acquisition cycle and then must charge to 0.5 V for the second acquisition cycle. When running
at high throughput, the acquisition time is small and a wide bandwidth amplifier is required for proper settling at
the ADC inputs (minimum acquisition time for the ADS816x is tACQ = 330 ns). The RC filter (RFLT and CFLT) is
designed to provide a reservoir of charge that helps rapidly charge the internal sample-and-hold capacitor at the
start of the acquisition period. For this reason, the RC filter is sometimes called a charge bucket or charge
kickback filter. A method for determining the required amplifier bandwidth and the values of the RC charge
bucket filter is provided in this section.
A summary of the equations and an example calculation is provided to determine the amplifier bandwidth and RC
charge bucket circuit for the ADS816x assuming a minimum ADC acquisition time is used. 公式 5 finds the
amplifier time constant and 公式 6 uses this to computer the amplifiers required unity-gain bandwidth.
tC
40.9ns
tAMP
=
=
= 9.917ns
17
17
(5)
(6)
1
1
UGBW =
=
= 16MHz
2pì tAMP 2pì(9.917ns)
公式 7, 公式 8, and 公式 9 calculate CSH, the LSB value, and τC, respectively.
CSH = 60pF,tACQ = 330ns,N = 16bits,VREF = 4.096V
(7)
(8)
VREF
4.096V
216
LSB =
=
= 62.5mV
2N
-tACQ
-330ns
tC
=
=
= 40.9ns
0.5ìLSB
100mV
0.5ì(62.5mV)
100mV
≈
’
≈
’
In
In
∆
«
÷
◊
∆
«
÷
◊
(9)
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Application Information (接下页)
The value of CFLT is computed in 公式 10 by taking 20 times the internal sample-and-hold capacitance. The
factor of 20 is a rule of thumb that is intended to minimize the droop in voltage on the charge bucket capacitor,
CFLT, after the start of the acquisition period. The filter resistor, RFLT, is computed in 公式 11 using the op amp
time constant and CFLT. These equations model the system as a first-order system, but in reality the system is a
higher order. Consequently, the values may need to be adjusted to optimize performance. This optimization and
more details on the math behind the component selection are covered in the ADC Precision Labs training videos.
CFLT = 20ìCFLT = 20ì(60pF) = 1.2nF
(10)
4ì tAMP
CFLT
4ì(9.917ns)
1.2nF
RFLT
=
=
= 33.05W
(11)
8.2 Typical Applications
8.2.1 1-MSPS DAQ Circuit With Lowest Distortion and Noise Performance
图 102 shows an 8-channel and 1-MSPS solution with minimum external components. This solution significantly
reduces solution size and power by not requiring amplifiers on every analog input.
IO Supply
5-V
1.2 …F
49.9 ꢀ
1 …F
1 …F
1 …F
+
OPA320
DECAP DVDD
AVDD
ADS816x
107 ꢀ
AIN0
AIN1
AIN2
ADC-INP
Interface
ADC
560 pF
ADC-INM
1 …F
REFIO
REFP
AIN7
22 …F
1 …F
107 ꢀ
AIN-COM
REFby2
÷2
4.096 V
560 pF
49.9 ꢀ
1.2 …F
图 102. 1-MSPS DAQ Circuit With Lowest Distortion and Noise Performance
8.2.1.1 Design Requirements
表 59 lists the design parameters for this example.
表 59. Design Parameters
DESIGN PARAMETER
SNR
EXAMPLE VALUE
≥ 92 dB
THD
≤ –108 dB
Throughput
1 MSPS
Input signal frequency
≤100 kSPS
8.2.1.2 Detailed Design Procedure
The procedure discussed in this section can be used for any ADS816x application circuit. See the Example
Schematic section for the final design for this example.
•
All ADS816x applications require the supply and reference decoupling as given in the Example Schematic
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and Layout sections.
•
•
Select the buffer amplifier and associated charge bucket filter between the multiplexer output and the ADC
input using the method described in the Selecting an ADC Input Buffer section. The values given in this
section meet the maximum throughput and input signal frequency design requirements given. A lower
bandwidth solution can be used in cases where lower power is required.
Select an input amplifier for rapid settling when the multiplexer switches channels. This selection is covered in
the Multiplexer Input Connection section. The OPA320 buffer and associated RC filter illustrated in 图 100
meet these requirements.
8.2.1.3 Application Curve
0
-36
-72
-108
-144
-180
0
100
200 300
fIN, Input Frequency (kHz)
400
500
D001
fIN = 2 kHz, SNR = 92 dB, THD = –109 dB
图 103. FFT Plot: ADS8168
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8.2.2 8-Channel Photodiode Detector With Smallest Size and Lowest Number of Components
The circuit in 图 104 shows an 8-channel photodiode detector using the ADS816x. In this example, one common
amplifier is used for eight photodiodes. See the 1 MHz, Single-Supply, Photodiode Amplifier Reference Design
reference guide for a detailed description of the transimpedance amplifier.
3.6 pF
43.2 kꢀ
5V
0 µA to 90 µA
49.9 ꢀ
+
VB = 0.1V
OPA320
3.6 pF
0 µA to 90 µA
ADC-INP
AIN0
AIN0
ADC
AIN1
AIN1
MUXOUT-P
VREF
VB = 0.1V
AIN7
AIN7
10 kꢀ
4.096V
÷2
SFH213
REFby2
Sequencer
500 ꢀ
ADS816x
ADS816x Solution œ Single Wide Bandwidth Amplifier
图 104. Small Size, 8-Channel Photodetector
8.2.2.1 Design Requirements
The objective of this design is to achieve:
•
•
•
Smallest solution size
Transimpedance output of 0.1 V to 4 V for a 0-µA to 90-µA input with a bandwidth of 1 MHz
The voltage divider is designed to provide a minimum amplifier output of 0.1 V when the photodiode
current is zero (dark current) to prevent the amplifier from saturating to the negative rail
8.2.2.2 Detailed Design Procedure
In 图 104, the photodiodes are connected to the multiplexer input in photovoltaic mode. Depending on the
application requirements, either photovoltaic mode or photoconductive mode can be used. The multiplexer in the
ADS816x is used as a current multiplexer in this example. One common amplifier for all photodiodes reduces
cost, complexity, PCB area, and power consumption. This common amplifier also simplifies system calibration
because the gain and offset error are the same for all channels. Finally, the low leakage current of the
multiplexer is ideal for photodiode applications.
The OPA320 is used as a transimpedance amplifier that can also drive the ADC inputs. In order to set the output
voltage of the OPA320 to 0.1 V in dark conditions, an equivalent bias voltage (VB) is applied at the noninverting
terminal. 公式 12 shows that this bias voltage is derived using a resistive voltage divider on the REFby2 output
(2.048V).
500W
10kW + 500W
≈
’
VB = (VREFby2V)ì
= 97.5mV
∆
«
÷
◊
(12)
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公式 13 shows that the feedback resistor for the transimpedance amplifier can be selected by designing for a 4-V
output for a 90-µA input.
VOUT _MAX - VOUT _MIN
4V - 0.1V
90mA
RF =
=
= 43.3kW
I
IN_MAX
(13)
公式 14 computes the value of the feedback capacitance to limit the bandwidth of the transimpedance circuit to 1
MHz.
1
1
CF =
=
= 3.6pF
2pì fC ìRF 2pì(1MHz)ì(43.3kW)
(14)
Transimpedance amplifiers can have potential stability concerns. Stability is a function of the feedback
capacitance, the capacitance on the inverting input of the amplifier, and the amplifier gain bandwidth. In this case
the capacitance on the inverting amplifier input (CIN, as calculated by 公式 15 and 公式 16) includes the
photodiode junction capacitance (CJ), the multiplexer capacitance (CMUX), the trace capacitance, and the op amp
input differential (CD) and common-mode (CCM2) capacitances. 公式 17 and 公式 18 compute the minimum gain
bandwidth of the amplifier for stability for a given CIN. The minimum required gain bandwidth is 10.9 MHz and the
gain bandwidth for the OPA320 is 20 MHz, so the stability test passes.
CIN = CJ + CD + CCM2 + CMUX
CIN = 11pF + 5pF + 4pF +15pF = 35pF
CIN + CF
(15)
(16)
FGBW
>
2pìRF ì(CF )2
(17)
(18)
35pF + 3.6pF
2pì 43.3kWì(3.6pF)2
FGBW
>
= 10.9MHz
78
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8.2.3 1-MSPS DAQ Circuit for Factory Automation
The circuit in 图 105 shows an example of how the ADS816x can be used for a factory automation application.
AVDD +5V
Supply Current
Sensor 1
Supply
Wiring Impedance
VSUP_DROP
T
GND1 -80mV
VGND_DROP
AVDD
Sensor 2
AIN0
ADS816x
AIN1
VSUP_DROP
AIN2
AIN3
T
ADC
GND2 -60mV
AIN4
AIN5
AIN6
AIN7
VGND_DROP
Sensor 3
VSUP_DROP
GND
Ground
Wiring Impedance
T
GND3 -40mV
VGND_DROP
ADC GND
0V
Sensor 4
T
GND4 -20mV
VGND_DROP
Ground return current
图 105. Remote Ground Sense With the ADS816x in Factory Automation
8.2.3.1 Design Requirements
The goal of this design to sense outputs from four sensors, with each sensor being at a different ground
potential.
8.2.3.2 Detailed Design Procedure
In 图 105, the sensors are connected over long leads to the supply, ground, and ADC inputs. Voltage drop
resulting from ground wiring impedance causes the ground connections to be at different potentials for each
sensor. The ADS816x can be configured into four single-ended pairs with a remote ground sense; see the
Multiplexer Configurations section. In this input configuration, the error in ground potential is sensed and
accounted for in the measurement.
The ADC negative input can sense ground voltages of ±100 mV. The ADC has digital window comparators that
can be programed to set an alarm if the sensor output is out of range. Many industrial applications require
isolation. When scanning all the channels at 1 MSPS, the serial clock rate can be as low as 16 MHz. This clock
rate is suitable for most isolators. Using a common amplifier to drive the ADC input simplifies calibration because
all channels have a common error.
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9 Power Supply Recommendations
The ADS816x has two separate power supplies: AVDD and DVDD. The internal reference, reference buffer,
multiplexer, and the internal LDO operate on AVDD. The ADC core operates on the LDO output (available on the
DECAP pin). DVDD is used for setting the logic levels on the digital interface. AVDD and DVDD can be
independently set to any value within their permissible ranges. During normal operation, if any voltage on the
AVDD supply drops below the AVDD minimum specification, then the AVDD supply is recommended to be
ramped down to ≤ 0.7 V before power-up. Also during power-up, AVDD must monotonously rise to the desired
operating voltage above the minimum AVDD specification.
When using an internal reference, set AVDD so that 4.5 V ≤ AVDD ≤ 5.5 V.
The AVDD supply voltage value defines the permissible range for the external reference voltage, VREF, on the
REFIO pin. To use the external reference voltage (VREF), set AVDD such that 3 V ≤ AVDD ≤ (AVDD + 0.3) V.
As shown in 图 106, place a minimum 1-µF decoupling capacitor between the AVDD and GND pins and between
the DVDD and GND pins. Use a minimum 1-µF decoupling capacitor between the DECAP and GND pins.
There are no specific requirements with regard to the power-supply sequencing of the device. However, issue a
reset after the supplies are powered and stable to ensure the device is properly configured.
AVDD
1 …F
1 …F
AVDD
DECAP
DVDD
DVDD
MUX Control
LDO
1 …F
ALERT
READY
Digital
GND
Interface
RST
ADC
MUX
4.096-V
÷2
图 106. Power-Supply Decoupling
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10 Layout
10.1 Layout Guidelines
This section provides some layout guidelines for achieving optimum performance with the ADS816x.
10.1.1 Analog Signal Path
As illustrated in 图 108, the analog input signals are routed in opposite directions to the digital connections. The
reference decoupling components are kept away from the switching digital signals. This arrangement prevents
noise generated by digital switching activity from coupling to sensitive analog signals.
10.1.2 Grounding and PCB Stack-Up
Low inductance grounding is critical for achieving optimum performance. Place all critical components of the
signal chain on the same PCB layer as the ADS816x.
For lowest inductance grounding, connect the GND pins of the ADS816x (pins 1, 21, and 31) and reference
ground REFM (pin 4) directly to the device thermal pad. Connect the device thermal pad to the PCB ground
using four vias; see 图 108.
10.1.3 Decoupling of Power Supplies
Use wide traces or a dedicated power-supply plane to minimize trace inductance. Place 1-µF, X7R-grade,
ceramic decoupling capacitors in close proximity on AVDD (pin 32), DECAP (pin 2), DVDD (pin 30), and REFby2
(pin 7). Avoid placing vias between any supply pin and the respective decoupling capacitor.
10.1.4 Reference Decoupling
When using the internal reference (see the External Reference section), REFIO (pin 3) must have a 1-µF, X7R-
grade, ceramic capacitor with at least a 10-V rating. This capacitor must be placed close to the REFIO pin, as
illustrated in 图 108. In cases where an external reference is used, refer to the reference component data sheet
for filtering capacitor requirements.
10.1.5 Reference Buffer Decoupling
Dynamic currents are present at the REFP and REFM pins during the conversion phase, and excellent
decoupling is required to achieve optimum performance. Place a 22-µF, X7R-grade, ceramic capacitor with at
least a 10-V rating between the REFP and the REFM pins, as illustrated in 图 108. Select 0603- or 0805-size
capacitors to keep the equivalent series inductance (ESL) low. Connect the REFM pin to the decoupling
capacitor before connecting to a ground via.
10.1.6 Multiplexer Input Decoupling
Minimizing channel-to-channel parasitic capacitance reduces the crosstalk induced on the PCB. This lower
capacitance can be achieved by increasing the spacing between the analog traces to the multiplexer input.
In 图 108, each multiplexer input has an RC filter. Use C0G- or NPO-type capacitors in the RC filter to help
reduce settling when switching between multiplexer channels. When not switching the multiplexer, as discussed
in 图 43 and 图 44, the RC filter can be omitted.
10.1.7 ADC Input Decoupling
Dynamic currents are also present at the ADC analog inputs (pins 18 and 19) of the ADS816x. Use C0G- or
NPO-type capacitors to decouple these inputs. With these type of capacitors, capacitance remains almost
constant over the full input voltage range. Lower-quality capacitors (such as X5R and X7R) have large
capacitance changes over the full input voltage range that may cause degradation in device performance.
In 图 108, each multiplexer input has an RC filter that helps reduce settling when switching between multiplexer
channels. When not switching the multiplexer, as discussed in 图 43 and 图 44, the RC filter can be omitted.
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Layout Guidelines (接下页)
10.1.8 Example Schematic
图 107 shows the schematic used for 图 108.
DVDD
AVDD
DECAP
REFP
REFby2
REFIO
1 …F
10 …F
10 …F
1 …F
1 …F
1 …F
1 …F
30
32
2
3
7
5
Reference
4.096V
LDO
107 ꢀ
÷2
AIN0
9
REFP
ALARM
READY
560 pF
INP
ADC
Analog In
SDO-1
4-wire SPI
INM
RST
107 ꢀ
AIN7
16
560 pF
107 ꢀ
19
18
17
20
8
OPA320
1.2 nF
560 pF
49.9 ꢀ
+
1.2 …F
5.5V
0.1 …F
49.9 ꢀ
图 107. Example Schematic for 图 108
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10.2 Layout Example
GND
REFby2
GND
CREF1
CREFby2
R
C
GND
CREFIO
CREF2
CDECAP
AVDD
GND
1
CAVDD
8
DVDD
GND
9
32
CDVDD
ADS8168
16
25
CFLT+
CFLT-
RFLT+
RFLT-
ADC-INM
ADC-INP
GND
MUXOUT-P
图 108. Recommended Layout
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11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档：
•
•
•
•
德州仪器 (TI)，适用于单端多路复用器应用的 16 位 1MSPS 数据采集参考 设计设计指南
德州仪器 (TI)，OPAx625 高带宽、高精度、低 THD+N、16 位和 18 位模数转换器 (ADC) 驱动器产品说明书
德州仪器 (TI)，THS4551 低噪声、高精度的 150MHz 全差分放大器产品说明书
德州仪器 (TI)，具有关断功能的 OPAx320x 高精度 20MHz、0.9pA、低噪声、RRIO、CMOS 运算放大器产品
说明书
•
•
德州仪器 (TI)，1MHz 单电源光电二极管放大器参考设计参考指南
德州仪器 (TI)，具有精密多通道 ADC 应用的简化系统设计概要
11.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。
表 60. 相关链接
器件
产品文件夹
单击此处
单击此处
单击此处
立即订购
单击此处
单击此处
单击此处
技术文档
单击此处
单击此处
单击此处
工具与软件
单击此处
单击此处
单击此处
支持和社区
单击此处
单击此处
单击此处
ADS8166
ADS8167
ADS8168
11.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
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PACKAGE OUTLINE
RHB0032E
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
5.1
4.9
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
2X
SYMM
33
3.5
0.3
32X
0.2
24
0.1
C A B
1
0.05
C
32
25
PIN 1 ID
(OPTIONAL)
SYMM
0.5
0.3
32X
4223442/A 11/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
(
0.2) TYP
VIA
8
17
(R0.05)
TYP
9
16
(1.475)
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223442/A 11/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223442/A 11/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS8166IRHBR
ADS8166IRHBT
ADS8167IRHBR
ADS8167IRHBT
ADS8168IRHBR
ADS8168IRHBT
ACTIVE
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RHB
32
32
32
32
32
32
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
ADS
8166
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
RHB
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
ADS
8166
RHB
ADS
8167
RHB
ADS
8167
RHB
ADS
8168
RHB
ADS
8168
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS8166IRHBR
ADS8166IRHBT
ADS8167IRHBR
ADS8167IRHBT
ADS8168IRHBR
ADS8168IRHBT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RHB
RHB
RHB
RHB
RHB
RHB
32
32
32
32
32
32
3000
250
330.0
180.0
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
1.1
1.1
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS8166IRHBR
ADS8166IRHBT
ADS8167IRHBR
ADS8167IRHBT
ADS8168IRHBR
ADS8168IRHBT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RHB
RHB
RHB
RHB
RHB
RHB
32
32
32
32
32
32
3000
250
367.0
210.0
367.0
210.0
367.0
210.0
367.0
185.0
367.0
185.0
367.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
250
3000
250
Pack Materials-Page 2
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
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