ADS8321EB/2K5 [TI]

16 位高速微功耗采样模数转换器 (ADC) | DGK | 8 | -40 to 85;


型号：	ADS8321EB/2K5
厂家：	TEXAS INSTRUMENTS
描述：	16 位高速微功耗采样模数转换器 (ADC) \| DGK \| 8 \| -40 to 85 光电二极管转换器模数转换器
文件：	总17页 (文件大小：404K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS8321

SBAS123B – SEPTEMBER 1999 – REVISED SEPTEMBER 2004

16-Bit, High Speed, MicroPower Sampling

ANALOG-TO-DIGITAL CONVERTER

FEATURES

DESCRIPTION

ꢀ BIPOLAR INPUT RANGE

The ADS8321 is a 16-bit sampling analog-to-digital con-

verter (ADC) with tested specifications over a 4.75V to

5.25V supply range. It requires very little power even when

operating at the full 100kHz data rate. At lower data rates,

the high speed of the device enables it to spend most of its

time in the power-down mode—the average power dissipa-

tion is less than 1mW at 10kHz data rate.

ꢀ 100kHz SAMPLING RATE

ꢀ MICRO POWER:

4.5mW at 100kHz

1mW at 10kHz

ꢀ POWER DOWN: 3µA max

ꢀ MSOP-8 PACKAGE

The ADS8321 also features a synchronous serial (SPI/SSI

compatible) interface, and a differential input. The refer-

ence voltage can be set to any level within the range of

500mV to V_CC/2.

ꢀ PIN-COMPATIBLE TO ADS7816 AND ADS7822

ꢀ SERIAL (SPI/SSI) INTERFACE

Ultra-low power and small size make the ADS8321 ideal

for portable and battery-operated systems. It is also a

perfect fit for remote data acquisition modules, simulta-

neous multi-channel systems, and isolated data acquisi-

tion. The ADS8321 is available in an MSOP-8 package.

APPLICATIONS

ꢀ BATTERY OPERATED SYSTEMS

ꢀ REMOTE DATA ACQUISITION

ꢀ ISOLATED DATA ACQUISITION

ꢀ SIMULTANEOUS SAMPLING,

MULTI-CHANNEL SYSTEMS

ꢀ INDUSTRIAL CONTROLS

ꢀ ROBOTICS

ꢀ VIBRATION ANALYSIS

SAR

V_REF

ADS8321

D_OUT

+In

–In

CDAC

Serial

Interface

DCLOCK

CS/SHDN

S/H Amp

Comparator

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

www.ti.com

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instruments

recommends that all integrated circuits be handled with appropriate

precautions. Failure to observe proper handling and installation proce-

dures can cause damage.

V_CC....................................................................................................... +6V

Analog Input ............................................................. –0.3V to (V_CC+ 0.3V)

Logic Input ...............................................................................–0.3V to 6V

Case Temperature ......................................................................... +100°C

Junction Temperature .................................................................... +150°C

Storage Temperature ..................................................................... +125°C

External Reference Voltage .............................................................. +5.5V

ESD damage can range from subtle performance degradation to

complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could

cause the device not to meet its published specifications.

NOTE: (1) Stresses above these ratings may permanently damage the device.

PACKAGE/ORDERING INFORMATION⁽¹⁾

MAXIMUM

INTEGRAL

LINEARITY

ERROR

MISSING

CODE

ERROR

(LSB)

SPECIFICATION

TEMPERATURE

RANGE

PACKAGE

DESIGNATOR⁽¹⁾

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

MEDIA, QUANTITY

PRODUCT

(%)

PACKAGE-LEAD

ADS8321E

0.018

MSOP-8

DGK

–40°C to +85°C

A21

ADS8321E/250

ADS8321E/2K5

ADS8321EB/250

ADS8321EB/2K5

Tape and Reel, 250

Tape and Reel, 2500

Tape and Reel, 250

Tape and Reel, 2500

0.012

MSOP-8

DGK

ADS8321EB

–40°C to +85°C

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.

PIN CONFIGURATION

PIN ASSIGNMENTS

NAME

DESCRIPTION

Top View

MSOP

V_REF

+In

Reference Input

Non Inverting Input

Inverting Input

Ground

–In

GND

V_REF

+In

+V_CC

CS/SHDN

Chip Select when LOW, Shutdown Mode when

HIGH.

DCLOCK

D_OUT

ADS8321

D_OUT

The serial output data word is comprised of 16

bits of data. In operation the data is valid on the

falling edge of DCLOCK. The second clock

pulse after the falling edge of CS enables the

serial output. After one null bit, data is valid for

the next 16 edges.

–In

GND

CS/SHDN

DCLOCK

+V_CC

Data Clock synchronizes the serial data transfer

and determines conversion speed.

Power Supply.

ADS8321

SBAS123B

www.ti.com

SPECIFICATIONS: +V_CC= +5V

At –40°C to +85°C, V_REF= +2.5V, –In = 2.5V, f_SAMPLE= 100kHz, and f_CLK= 24 • f_SAMPLE, unless otherwise specified.

ADS8321E

ADS8321EB

TYP

PARAMETER

RESOLUTION

CONDITIONS

MIN

TYP

MAX

MIN

MAX

UNITS

ꢀ

Bits

ANALOG INPUT

Full-Scale Input Span

Absolute Input Range

+In – (–In)

+In

–V_REF

–0.1

+V_REF

V_CC+ 0.1

+4.0

ꢀ

–In

–0.1

Capacitance

ꢀ

Leakage Current

SYSTEM PERFORMANCE

No Missing Codes

Bits

Integral Linearity Error

Offset Error

±0.008 ±0.018

±0.006

±0.2

ꢀ

±0.012 % of FSR

±0.4

±1

±2

±1

µV/°C

Offset Temperature Drift

Gain Error, Positive

Negative

±0.05

±0.024

Gain Temperature Drift

Noise

±0.3

ꢀ

ppm/°C

µVrms

Common-Mode Rejection Ratio

Power Supply Rejection Ratio

+4.7V < V_CC< 5.25V

LSB⁽¹⁾

SAMPLING DYNAMICS

Conversion Time

ꢀ

Clk Cycles

kHz

Acquisition Time

4.5

ꢀ

Throughput Rate

100

2.9

ꢀ

Clock Frequency Range

0.024

MHz

DYNAMIC CHARACTERISTICS

Total Harmonic Distortion

SINAD

V_IN= 5Vp-p at 10kHz

–84

–86

Spurious Free Dynamic Range

SNR

REFERENCE INPUT

Voltage Range

Resistance

0.5

V_CC/2

ꢀ

CS = GND, f_SAMPLE= 0Hz

CS = V_CC

ꢀ

GΩ

µA

Current Drain

0.8

0.1

f_SAMPLE= 10kHz

CS = V_CC

DIGITAL INPUT/OUTPUT

Logic Family

Logic Levels:

V_IH

CMOS

ꢀ

I_IH= +5µA

I_IL= +5µA

3.0

–0.3

4.0

V_CC+ 0.3

0.8

ꢀ

V_IL

V_OH

I_OH= –250µA

I_OL= 250µA

V_OL

0.4

ꢀ

Binary Two’s Complement

Data Format

ꢀ

POWER SUPPLY REQUIREMENTS

V_CC

V_CCRange⁽²⁾

Specified Performance

4.75

2.7

5.25

1700

ꢀ

Quiescent Current

1100

250

5.5

ꢀ

µA

f_SAMPLE= 10kHz^{(3, 4)}

CS = V_CC

Power Dissipation

Power Down

8.5

ꢀ

0.3

TEMPERATURE RANGE

Specified Performance

–40

+85

ꢀ

°C

ꢀ Specifications same as ADS8321E.

NOTES: (1) LSB means Least Significant Bit. (2) See Typical Performance Curves for more information. (3) f_CLK= 2.4MHz, CS = V_CCfor 216 clock cycles out

of every 240. (4) See the Power Dissipation section for more information regarding lower sample rates.

ADS8321

SBAS123B

www.ti.com

TYPICAL PERFORMANCE CURVES

At T_A= +25°C, V_CC= +5V, V_REF= +2.5V, f_SAMPLE= 100kHz, f_CLK= 24 • f_SAMPLE, unless otherwise specified.

FREQUENCY SPECTRUM

INTEGRAL LINEARITY ERROR vs CODE (+25°C)

(8192 Point FFT, f_IN= 10.03kHz, –0.3dB)

–20

–40

–60

–80

–1

–2

–3

–4

–5

–6

–100

–120

–140

–160

–180

0000_H

4000_H

7FF9_H

C000_H

FFFD_H

Frequency (kHz)

Hex Code

DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C)

SUPPLY CURRENT vs TEMPERATURE

3.0

2.5

2.0

1.5

1.0

0.5

1400

1200

1000

800

600

400

200

–0.5

–1.0

–1.5

–50

Temperature (°C)

100

0000_H

3FFF_H

7FFC_H

C000_H

FFFD_H

Hex Code

POWER-DOWN SUPPLY CURRENT

vs TEMPERATURE

QUIESCENT CURRENT vs V_CC

600

1.20

1.10

1.00

0.90

0.80

0.70

0.60

500

400

300

200

100

–50

–25

100

2.0

2.5

3.0

3.5

4.0

_CC(V)

4.5

5.0

5.5

Temperature (°C)

ADS8321

SBAS123B

www.ti.com

TYPICAL PERFORMANCE CURVES (Cont.)

At T_A= +25°C, V_CC= +5V, V_REF= +2.5V, f_SAMPLE= 100kHz, f_CLK= 24 • f_SAMPLE, unless otherwise specified.

SIGNAL-TO-NOISE AND SIGNAL-TO-(NOISE + DISTORTION)

vs INPUT FREQUENCY

MAXIMUM SAMPLE RATE vs V_CC

1000

100

SNR

SINAD

0.1

100

V_CC(V)

Input Frequency (kHz)

SPURIOUS FREE DYNAMIC RANGE AND

TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY

REFERENCE CURRENT vs SAMPLE RATE

2.5V

SFDR

THD

1.25V

100

120

140

0.1

100

Sample Rate (kHz)

Input Frequency (kHz)

CHANGE IN GAIN vs REFERENCE VOLTAGE

NOISE vs REFERENCE VOLTAGE

–5

–10

–15

0.1

0.5

1.0

1.5

2.0

2.5

3.0

Reference Voltage (V)

ADS8321

SBAS123B

www.ti.com

TYPICAL PERFORMANCE CURVES (Cont.)

At T_A= +25°C, V_CC= +5V, V_REF= +2.5V, f_SAMPLE= 100kHz, f_CLK= 24 • f_SAMPLE, unless otherwise specified.

CHANGE IN BIPOLAR ZERO vs REFERENCE VOLTAGE

CHANGE IN OFFSET vs TEMPERATURE

6.0

5.0

4.0

3.0

2.0

1.0

5.0

4.0

3.0

2.0

1.0

–1.0

–2.0

–3.0

–4.0

–5.0

–1.0

–2.0

–3.0

0.5

1.0

1.5

2.0

2.5

3.0

–50

Temperature (°C)

100

Reference Voltage (V)

COMMON-MODE REJECTION RATIO vs FREQUENCY

CHANGE IN GAIN vs TEMPERATURE

5.0

4.0

3.0

2.0

1.0

–1.0

–2.0

–3.0

–4.0

–5.0

V_CM= 1Vp-p Sinewave

–50

Temperature (°C)

100

10k

100k

Frequency (Hz)

REFERENCE CURRENT vs TEMPERATURE

–50

–25

100

Temperature (°C)

ADS8321

SBAS123B

www.ti.com

THEORY OF OPERATION

2 • V_REF

peak-to-peak

The ADS8321 is a classic Successive Approximation Reg-

ister (SAR) analog-to-digital converter (ADC). The archi-

tecture is based on capacitive redistribution which inherently

includes a sample/hold function. The converter is fabricated

on a 0.6µ CMOS process. The architecture and process

allow the ADS8321 to acquire and convert an analog signal

at up to 100,000 conversions per second while consuming

ADS8321

Common

Voltage

Single-Ended Input

V_REF

peak-to-peak

less than 5.5mW from +V_CC

The ADS8321 requires an external reference, an external

clock, and a single power source (V_CC). The external refer-

ence can be any voltage between 500mV and V_CC/2. The

value of the reference voltage directly sets the range of the

analog input. The reference input current depends on the

conversion rate of the ADS8321.

ADS821

Common

Voltage

V_REF

peak-to-peak

Differential Input

FIGURE 1. Methods of Driving the ADS8321—Single-Ended

or Differential.

The external clock can vary between 24kHz (1kHz through-

put) and 2.4MHz (100kHz throughput). The duty cycle of

the clock is essentially unimportant as long as the minimum

high and low times are at least 200ns (4.75V or greater). The

minimum clock frequency is set by the leakage on the

capacitors internal to the ADS8321.

V_CC= 5V

4.0

The analog input is provided to two input pins: +In and –In.

When a conversion is initiated, the differential input on these

pins is sampled on the internal capacitor array. While a

conversion is in progress, both inputs are disconnected from

any internal function.

Single-Ended Input

2.8

2.2

The digital result of the conversion is clocked out by the

DCLOCK input and is provided serially, most significant bit

first, on the D_OUTpin. The digital data that is provided on the

D_OUTpin is for the conversion currently in progress—there

is no pipeline delay. It is possible to continue to clock the

ADS8321 after the conversion is complete and to obtain the

serial data least significant bit first. See the digital timing

section for more information.

–0.3

–1

0.0

0.5

1.0

1.5

2.0

2.5

_REF(V)

FIGURE 2. Single-Ended Input—Common Voltage Range

vs V_REF

ANALOG INPUT

The analog input is bipolar and fully differential. There are

two general methods of driving the analog input of the

ADS8321: single-ended or differential (see Figure 1). When

the input is single-ended, the –In input is held at a fixed

voltage. The +In input swings around the same voltage and

the peak-to-peak amplitude is 2 • V_REF. The value of V_REF

determines the range over which the common voltage may

vary (see Figure 2).

V_CC= 5V

4.0

Differential Input

2.75

1.95

When the input is differential, the amplitude of the input is

the difference between the +In and –In input, or; +In – (–In).

A voltage or signal is common to both of these inputs. The

peak-to-peak amplitude of each input is V_REFabout this

common voltage. However, since the inputs are 180°C out-

of-phase, the peak-to-peak amplitude of the difference volt-

age is 2 • V_REF. The value of V_REFalso determines the range

of the voltage that may be common to both inputs (see

Figure 3).

–0.3

–1

0.0

0.5

1.0

1.5

2.0

2.5

V_REF(V)

In each case, care should be taken to ensure that the output

impedance of the sources driving the +In and –In inputs are

matched. If this is not observed, the two inputs could have

FIGURE 3. Differential Input—Common Voltage Range vs

V_REF.

ADS8321

SBAS123B

www.ti.com

NOISE

different settling times. This may result in offset error, gain

error, and linearity error which change with both tempera-

ture and input voltage. If the impedance cannot be matched,

the errors can be lessened by giving the ADS8321 additional

acquisition time.

The noise floor of the ADS8321 itself is extremely low, as

can be seen from Figures 4 and 5, and is much lower than

competing A/D converters. It was tested by applying a low

noise DC input and a 2.5V reference to the ADS8321 and

initiating 5,000 conversions. The digital output of the ADC

will vary in output code due to the internal noise of the

ADS8321. This is true for all 16-bit SAR-type ADCs. Using

a histogram to plot the output codes, the distribution should

appear bell-shaped with the peak of the bell curve represent-

ing the nominal code for the input value. The ±1σ, ±2σ, and

±3σ distributions will represent the 68.3%, 95.5%, and

99.7%, respectively, of all codes. The transition noise can be

calculated by dividing the number of codes measured by 6

and this will yield the ±3σ distribution or 99.7% of all

codes. Statistically, up to 3 codes could fall outside the

distribution when executing 1000 conversions. The

ADS8321, with five output codes for the ±3σ distribution,

will yield a ±0.8LSB transition noise. Remember, to achieve

this low noise performance, the peak-to-peak noise of the

input signal and reference must be < 50µV.

The input current on the analog inputs depends on a number

of factors: sample rate, input voltage, and source impedance.

Essentially, the current into the ADS8321 charges the inter-

nal capacitor array during the sample period. After this

capacitance has been fully charged, there is no further input

current. The source of the analog input voltage must be able

to charge the input capacitance (25pF) to 16-bit settling level

within 4.5 clock cycles. When the converter goes into the

hold mode or while it is in the power-down mode, the input

impedance is greater than 1GΩ.

Care must be taken regarding the absolute analog input

voltage. The +In input should always remain within the

range of GND – 300mV to V_CC+ 300mW. The –In input

should always remain within the range of GND – 300mV to

4V. Outside of these ranges, the converter’s linearity may

not meet specifications.

REFERENCE INPUT

1639

The external reference sets the analog input range. The

ADS8321 will operate with a reference in the range of

500mV to 2.5V. There are several important implications of

this. As the reference voltage is reduced, the analog voltage

weight of each digital output code is reduced. This is often

referred to as the Least Significant Bit (LSB) size and is

equal to 2 • V_REFdivided by 65,535. This means that any

offset or gain error inherent in the ADC will appear to

increase, in terms of LSB size, as the reference voltage is

reduced.

1260

981

192

Code

The noise inherent in the converter will also appear to

increase with lower LSB size. With a +2.5V reference, the

internal noise of the converter typically contributes only 5

LSB peak-to-peak of potential error to the output code. When

the external reference is 500mV, the potential error contribu-

tion from the internal noise will be 10 times larger—15 LSBs.

The errors due to the internal noise are gaussian in nature and

can be reduced by averaging consecutive conversion results.

FIGURE 4. Histogram of 5,000 Conversions of a DC Input

at the Code Transition.

2318

For more information regarding noise, consult the typical

performance curve “Noise vs Reference Voltage.” Note that

the Effective Number of Bits (ENOB) figure is calculated

based on the converter’s signal-to-(noise + distortion) ratio

with a 1kHz, 0dB input signal. SINAD is related to ENOB

as follows:

836

SINAD = 6.02 • ENOB + 1.76

696

With lower reference voltages, extra care should be taken to

provide a clean layout including adequate bypassing, a clean

power supply, a low-noise reference, and a low-noise input

signal. Because the LSB size is lower, the converter will also

be more sensitive to external sources of error such as nearby

digital signals and electromagnetic interference.

244

Code

FIGURE 5. Histogram of 5,000 Conversions of a DC Input

at the Code Center.

ADS8321

SBAS123B

www.ti.com

AVERAGING

SYMBOL

t_SMPL

DESCRIPTION

Analog Input Sample Time

Conversion Time

Throughput Rate

CS Falling to

MIN

TYP MAX

UNITS

4.5

5.0

Clk Cycles

kHz

The noise of the ADC can be compensated by averaging the

digital codes. By averaging conversion results, transition

noise will be reduced by a factor of 1/√n, where n is the

number of averages. For example, averaging 4 conversion

results will reduce the transition noise by 1/2 to ±0.25 LSBs.

Averaging should only be used for input signals with fre-

quencies near DC.

t_CONV

t_CYC

100

t_CSD

DCLOCK LOW

t_SUCS

CS Falling to

DCLOCK Rising

t_hDO

t_dDO

DCLOCK Falling to

Current D_OUTNot Valid

For AC signals, a digital filter can be used to low pass filter

and decimate the output codes. This works in a similar

manner to averaging; for every decimation by 2, the signal-

to-noise ratio will improve 3dB.

DCLOCK Falling to Next

D_OUTValid

t_dis

t_en

CS Rising to D_OUTTri-State

100

DCLOCK Falling to D_OUT

Enabled

DIGITAL INTERFACE

SIGNAL LEVELS

t_f

t_r

D_OUTFall Time

D_OUTRise Time

The digital inputs of the ADS8321 can accommodate logic

TABLE I. Timing Specifications (V_CC= 5V) –40°C to +85°C.

levels up to 5.5V regardless of the value of V_CC

The CMOS digital output (D_OUT) will swing 0V to V_CC. If

V_CCis 3V and this output is connected to a 5V CMOS logic

input, then that IC may require more supply current than

normal and may have a slightly longer propagation delay.

A falling CS signal initiates the conversion and data transfer.

The first 4.5 to 5.0 clock periods of the conversion cycle are

used to sample the input signal. After the fifth falling

DCLOCK edge, D_OUTis enabled and will output a LOW

value for one clock period. For the next 16 DCLOCK

periods, D_OUTwill output the conversion result, most signifi-

cant bit first. After the least significant bit (B0) has been

output, subsequent clocks will repeat the output data but in

a least significant bit first format.

SERIAL INTERFACE

The ADS8321 communicates with microprocessors and

other digital systems via a synchronous 3-wire serial inter-

face as shown in Figure 6 and Table I. The DCLOCK signal

synchronizes the data transfer with each bit being transmit-

ted on the falling edge of DCLOCK. Most receiving systems

will capture the bitstream on the rising edge of DCLOCK.

However, if the minimum hold time for D_OUTis acceptable,

the system can use the falling edge of DCLOCK to capture

each bit.

After the most significant bit (B15) has been repeated, D_OUT

will tri-state. Subsequent clocks will have no effect on the

converter. A new conversion is initiated only when CS has

been taken HIGH and returned LOW.

Complete Cycle

CS/SHDN

t_SUCS

Power Down

Sample

Conversion

DCLOCK

D_OUT

t_CSD

Use positive clock edge for data transfer

Hi-Z

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

(MSB) (LSB)

t_SMPL

t_CONV

NOTE: Minimum 22 clock cycles required for 16-bit conversion. Shown are 24 clock cycles.

If CS remains LOW at the end of conversion, a new datastream with LSB-first is shifted out again.

FIGURE 6. ADS8321 Basic Timing Diagrams.

ADS8321

SBAS123B

www.ti.com

DATA FORMAT

POWER DISSIPATION

The output data from the ADS8321 is in Binary Two’s

Complement format as shown in Table II. This table repre-

sents the ideal output code for the given input voltage and

does not include the effects of offset, gain error, or noise.

The architecture of the converter, the semiconductor fabrica-

tion process, and a careful design allow the ADS8321 to

convert at up to a 100kHz rate while requiring very little

power. Still, for the absolute lowest power dissipation, there

are several things to keep in mind.

DESCRIPTION

ANALOG VALUE

2 • V_REF

DIGITAL OUTPUT

The power dissipation of the ADS8321 scales directly with

conversion rate. Therefore, the first step to achieving the

lowest power dissipation is to find the lowest conversion rate

that will satisfy the requirements of the system.

Full-Scale Range

BINARY TWO’S COMPLEMENT

Least Significant

Bit (LSB)

2 • V_REF/65536

BINARY CODE

HEX CODE

7FFF

+Full Scale

Midscale

+V_REF– 1 LSB

0111 1111 1111 1111

0000 0000 0000 0000

1111 1111 1111 1111

1000 0000 0000 0000

In addition, the ADS8321 is in power-down mode under two

conditions: when the conversion is complete and whenever

CS is HIGH (see Figure 6). Ideally, each conversion should

occur as quickly as possible, preferably at a 2.4MHz clock

rate. This way, the converter spends the longest possible time

in the power-down mode. This is very important as the

converter not only uses power on each DCLOCK transition

(as is typical for digital CMOS components) but also uses

some current for the analog circuitry, such as the comparator.

The analog section dissipates power continuously, until the

power down mode is entered.

0000

Midscale – 1LSB

–Full Scale

0V – 1 LSB

–V_REF

FFFF

8000

TABLE II. Ideal Input Voltages and Output Codes.

1.4V

V_OH

3kΩ

D_OUT

V_OL

D_OUT

Test Point

t_r

t_f

100pF

C_LOAD

Voltage Waveforms for D_OUTRise and Fall Times, t_r, t_f

Load Circuit for t_dDO, t_r, and t_f

Test Point

DCLOCK

V_IL

V_CC

t_disWaveform 2, t_en

3kΩ

D_OUT

t_dDO

V_OH

V_OL

t_disWaveform 1

100pF

C_LOAD

D_OUT

t_hDO

Load Circuit for t_disand t_en

Voltage Waveforms for D_OUTDelay Times, t_dDO

V_IH

CS/SHDN

DCLOCK

D_OUT

Waveform 1⁽¹⁾

90%

10%

t_dis

V_OL

D_OUT

B11

D_OUT

Waveform 2⁽²⁾

t_en

Voltage Waveforms for t_en

Voltage Waveforms for t_dis

NOTES: (1) Waveform 1 is for an output with internal conditions such that the output

is HIGH unless disabled by the output control. (2) Waveform 2 is for an output with

internal conditions such that the output is LOW unless disabled by the output control.

FIGURE 7. Timing Diagrams and Test Circuits for the Parameters in Table I.

ADS8321

SBAS123B

www.ti.com

Figure 8 shows the current consumption of the ADS8321

versus sample rate. For this graph, the converter is clocked

at 2.4MHz regardless of the sample rate—CS is HIGH for

the remaining sample period. Figure 9 also shows current

consumption versus sample rate. However, in this case, the

DCLOCK period is 1/24th of the sample period—CS is

HIGH for one DCLOCK cycle out of every 16.

1000

100

T_A= 25°C

_CC= 5.0V

_REF= 2.5V

_CLK= 2.4MHz

There is an important distinction between the power-down

mode that is entered after a conversion is complete and the

full power-down mode which is enabled when CS is HIGH.

CS LOW will shut down only the analog section. The digital

section is completely shutdown only when CS is HIGH.

Thus, if CS is left LOW at the end of a conversion and the

converter is continually clocked, the power consumption

will not be as low as when CS is HIGH. See Figure 10 for

more information.

0.1

100

Sample Rate (kHz)

FIGURE 8. Maintaining f_CLKat the Highest Possible Rate

Allows Supply Current to Drop Linearly with

Sample Rate.

SHORT CYCLING

Another way of saving power is to utilize the CS signal to

short cycle the conversion. Because the ADS8321 places the

latest data bit on the D_OUTline as it is generated, the

converter can easily be short cycled. This term means that

the conversion can be terminated at any time. For example,

if only 14 bits of the conversion result are needed, then the

conversion can be terminated (by pulling CS HIGH) after

the 14th bit has been clocked out.

1000

100

This technique can be used to lower the power dissipation

(or to increase the conversion rate) in those applications

where an analog signal is being monitored until some con-

dition becomes true. For example, if the signal is outside a

predetermined range, the full 16-bit conversion result may

not be needed. If so, the conversion can be terminated after

the first n bits, where n might be as low as 3 or 4. This results

in lower power dissipation in both the converter and the rest

of the system, as they spend more time in the power-down

mode.

T_A= 25°C

_CC= 5.0V

_REF= 2.5V

_CLK= 24 • f_SAMPLE

0.1

100

Sample Rate (kHz)

FIGURE 9. Scaling f_CLKReduces Supply Current Only

Slightly with Sample Rate.

LAYOUT

1000

For optimum performance, care should be taken with the

physical layout of the ADS8321 circuitry. This will be

particularly true if the reference voltage is low and/or the

conversion rate is high. At a 100kHz conversion rate, the

ADS8321 makes a bit decision every 416ns. That is, for each

subsequent bit decision, the digital output must be updated

with the results of the last bit decision, the capacitor array

appropriately switched and charged, and the input to the

comparator settled to a 16-bit level all within one clock

cycle.

T_A= 25°C

_CC= 5.0V

_REF= 2.5V

800

600

_CLK= 24 • f_SAMPLE

CS LOW (GND)

400

200

0.250

0.00

CS HIGH (V_CC

)

The basic SAR architecture is sensitive to spikes on the

power supply, reference, and ground connections that occur

just prior to latching the comparator output. Thus, during

any single conversion for an n-bit SAR converter, there are

n “windows” in which large external transient voltages can

easily affect the conversion result. Such spikes might origi-

nate from switching power supplies, digital logic, and high

0.1

100

Sample Rate (kHz)

FIGURE 10. Shutdown Current with CS HIGH is 50nA

Typically, Regardless of the Clock. Shutdown

Current with CS LOW Varies with Sample

Rate.

ADS8321

SBAS123B

www.ti.com

reference input. This is of particular concern when the

reference input is tied to the power supply. Any noise and

ripple from the supply will appear directly in the digital

results. While high frequency noise can be filtered out as

described in the previous paragraph, voltage variation due to

the line frequency (50Hz or 60Hz), can be difficult to

remove.

power devices, to name a few. This particular source of error

can be very difficult to track down if the glitch is almost

synchronous to the converter’s DCLOCK signal—as the

phase difference between the two changes with time and

temperature, causing sporadic misoperation.

With this in mind, power to the ADS8321 should be clean

and well bypassed. A 0.1µF ceramic bypass capacitor should

be placed as close to the ADS8321 package as possible. In

addition, a 1µF to 10µF capacitor and a 5Ω or 10Ω series

resistor may be used to lowpass filter a noisy supply.

The GND pin on the ADS8321 should be placed on a clean

ground point. In many cases, this will be the “analog”

ground. Avoid connecting the GND pin too close to the

grounding point for a microprocessor, microcontroller, or

digital signal processor. If needed, run a ground trace di-

rectly from the converter to the power supply connection

point. The ideal layout will include an analog ground plane

for the converter and associated analog circuitry.

The reference should be similarly bypassed with a 0.1µF

capacitor. Again, a series resistor and large capacitor can be

used to lowpass filter the reference voltage. If the reference

voltage originates from an op amp, be careful that the op

amp can drive the bypass capacitor without oscillation (the

series resistor can help in this case). Keep in mind that while

the ADS8321 draws very little current from the reference on

average, there are still instantaneous current demands placed

on the external input and reference circuitry.

APPLICATION CIRCUITS

Figure 11 shows a basic data acquisition system. The

ADS8321 input range is 0V to V_CC, as the reference input is

connected directly to the power supply. The 5Ω resistor and

1µF to 10µF capacitor filter the microcontroller “noise” on

the supply, as well as any high-frequency noise from the

supply itself. The exact values should be picked such that the

filter provides adequate rejection of the noise.

Texas Instruments OPA627 op amp provides optimum per-

formance for buffering both the signal and reference inputs.

For low cost, low voltage, single-supply applications, the

OPA2350 or OPA2340 dual op amps are recommended.

Also, keep in mind that the ADS8321 offers no inherent

rejection of noise or voltage variation in regards to the

5Ω

1µF to 10µF

ADS8321

+2.5V

Reference

V_REF

V_CC

1µF to

10µF

0.1µF

Microcontroller

+In

D_OUT

0V to 5V

–In

GND

DCLOCK

FIGURE 11. Basic Data Acquisition System.

ADS8321

SBAS123B

www.ti.com

PACKAGE OPTION ADDENDUM

www.ti.com

7-Oct-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

ADS8321E/250

ADS8321E/250G4

ADS8321E/2K5

ACTIVE

VSSOP

DGK

250

RoHS & Green

Call TI

Level-2-260C-1 YEAR

-40 to 85

A21

Call TI

2500 RoHS & Green

ADS8321E/2K5G4

ADS8321EB/250

ADS8321EB/250G4

ADS8321EB/2K5

ADS8321EB/2K5G4

250

RoHS & Green

2500 RoHS & Green

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

7-Oct-2021

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

IMPORTANT NOTICE AND DISCLAIMER

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

ADS8321EB/2K5 [TI]

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