ADS8342_14_技术文档

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SBAS277 – MAY 2003

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FEATURES

DESCRIPTION

D

True Bipolar Input

Input Signal Range: ±2.5V

4-Channel Input Multiplexer

Up to 250kSPS Sampling Rate

Selectable 8-Bit or 16-Bit Parallel Interface

16-Bit Ensured No Missing Codes

Offset: 1mV max

Low Power: 200mW

TQFP-48 Package

Operating Temperature Range: –40°C to +85°C

The ADS8342 is a 4-channel, 16-bit analog-to-digital

converter (ADC). It contains 16-bit succesive

a

approximation register (SAR), a capacitor-based ADC with

an inherent sample-and-hold circuit, an interface for

microprocessor use, and parallel 3-state output drivers. The

ADS8342 is specified at a 250kHz sampling rate while

dissipating only 200mW of power using a ±5V power supply.

The ADS8342 is available in a TQFP-48 package and is

ensured over the –40°C to +85°C temperature range.

APPLICATIONS

D

Data Acquisition

Test and Measurement

Industrial Process Control

Medical Instruments

Laboratory Equipment

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

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SBAS277 – MAY 2003

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated

circuits be handled with appropriate precautions. Failure to observe proper handling and installation

procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small parametric changes could cause the device not to meet

its published specifications.

ORDERING INFORMATION

MAXIMUM

NO

INTEGRAL

LINEARITY

ERROR

SPECIFIED

TEMPERATURE

RANGE

TRANSPORT

MEDIA,

QUANTITY

PACKAGE–

PACKAGE

DESIGNATOR

ORDERING

NUMBER

MISSING

CODES

(Bits)

PRODUCT

(1)

LEAD

(LSB)

Tape and Reel,

250

ADS8342IPFBT

ADS8342IPFBR

ADS8342IBPFBT

ADS8342IBPFBR

ADS8342

±6

±4

15

16

TQFP-48

PFB

–40°C to +85°C

Tape and Reel,

2000

Tape and Reel,

250

Tape and Reel,

2000

(1)

For the most current specification and package information, refer to our web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

(1)

ADS8342I

UNIT

V

Supply voltage, +AV

to AGND and +DV

to DGND

–0.3 to 6

–6 to 0.3

DD

Supply voltage, –AV

to AGND and –DV

V

DD

Supply voltage, BV

to BGND

Analog input voltage to AGND

–0.3 to 6

V

DD

–AV

DD

– 0.3 to +AV

+ 0.3

DD

+ 0.3

V

Reference voltage, REF to AGND

IN

–0.3 to +AV

DD

V

Common voltage to AGND

Digital input voltage to BGND

–0.3 to +0.3

BGND – 0.3 to BV

V

+ 0.3

V

DD

Ground voltage differences, AGND to REFGND or BGND or DGND

Voltage differences, BVDD or +DVDD to AGND

–0.3 to 0.3

–0.3 to 6

V

Voltage differences, +DV

DD

to +AV

DD

and –DV

DD

to –AV

DD

–0.3 to 0.3

V

Voltage differences, BV

DD

to DV

DD

–(+DV ) to 0.3

V

DD

Input current to any pin except supply

Power dissipation

–20 to 20

mA

see Package Dissipation Ratings table

Operating virtual junction temperature range, T

–40 to +150

–40 to +85

–65 to +150

+300

°C

J

Operating free-air temperature range, T

A

Storage temperature range, T

STG

Lead temperature 1.6mm (1/16 inch) from case for 10 seconds

(1)

Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade

device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is

not implied.

2

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PACKAGE DISSIPATION RATINGS

DERATING FACTOR

T

≤ +25°C

T

≤ +70°C

T = +85°C

A

R

ΘJA

ΘJC

BOARD

PACKAGE

ABOVE T ≤ +25°C

POWER RATING POWER RATING POWER RATING

A

(°C/W)

(mW/°C)

10.256

15.698

(mW)

1282

1962

(mW)

Low K

High K

PFB

19.6

97.5

63.7

820

666

1255

1020

(1)

(2)

The JEDEC Low K(1s) board design used to derive this data was a 3 inch x 3 inch, 2-layer board with 2-ounce copper traces on top of the board.

The JEDEC High K(2s2p) board design used to derive this data was a 3 inch x 3 inch, multilayer board with 1-ounce internal power and ground

planes and 2-ounce copper traces on the top and bottom of the board.

RECOMMENDED OPERATING CONDITIONS

MIN

4.75

NOM

5

MAX UNIT

Supply voltage, +AV

to AGND

5.25

–4.75

3.6

V

DD

Supply voltage, –AV

–5.25

–5

DD

Low-voltage levels

5V logic levels

2.7

4.5

V

Supply voltage, BV

DD

to BGND

+DV

DD

Supply voltage, +DV

to DGND

4.75

5

–5

5.25

DD

Supply voltage, –DV

–5.25

–4.75

V

DD

Reference input voltage

Analog input voltage

Common voltage

2.0

2.5

2.55

–REF

+REF

IN

–0.3

0

+0.3

Ground differences, AGND to REFGND or BGND or DGND

Voltage differences, +DV to +AV and –DV to –AV

–0.01

0.01

DD DD DD DD

EQUIVALENT INPUT CIRCUIT

3

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SBAS277 – MAY 2003

ELECTRICAL CHARACTERISTICS

Over recommended operating free-air temperature range at –40°C to +85°C, ±AV

= ±DV

DD

= ±5V, BV

= +5V, V

REF

= +2.5V, f

CLK

= 5MHz, and

DD

f

= 250kSPS, unless otherwise noted.

SAMPLE

ADS8342I

(1)

ADS8342IB

(1)

MAX

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

MIN TYP

Analog Input

Full-scale range (FSR)

Input MUX on-resistance

Input capacitance

Input leakage current

Full power bandwidth

Voltage Accuracy

Resolution

AIN to Common

–V

REF

+V

REF

:

V

Ω

Common = AGND

FS sinewave, –3dB

500

20

:

pF

±0.3

16

µA

MHz

16

15

:

Bits

No missing code

(NMC)

16

Integral linearity error (INL)

Differential nonlinearity (DNL)

–6

–2

±3

±1

+6

+2

–4

–1

±2

+4

+1.5

+1

LSB

±0.6

Bipolar zero (offset) error (V

)

AIN = Common = 0V

mV

OS

Bipolar zero (offset) error drift (TCV

Bipolar zero (offset) error match

)

1

:

ppm/°C

mV

OS

0.150

1

:

Positive gain error (PG

)

AIN = V

, Common = 0V

–0.25

+0.25

:

% FSR

ppm/°C

% FSR

ppm/°C

% FSR

ERR

REF

Positive gain error drift (TCPG

Positive gain error match

)

, Common = 0V

REF

1.5

:

ERR

, Common = 0V

REF

0.003

0.01

:

Negative gain error (NG

)

AIN = –V

, Common = 0V

+0.25

ERR

REF

Negative gain error drift (TCNG

Negative gain error match

Sampling Dynamics

)

, Common = 0V

REF

1.5

:

ERR

, Common = 0V

REF

0.003

0.01

34

:

Conversion time (t

Acquisition time (t

)

500kHz ≤ f

CLK

≤ 5MHz

3.4

0.6

:

µs

CONV

)

f

= 5MHz

ACQ

CLK

Throughput rate

250

kHz

ns

Multiplexer settling time

Aperture delay

150

8

:

ns

Aperture jitter

50

ps

AC Accuracy

Total haromonic distortion (THD)

V

IN

V

IN

V

IN

V

IN

V

IN

= ±2.5Vp–p at 10kHz

= ±2.5Vp–p at 50kHz

–89

92

:

dB

Bits

Spurious-free dynamic range (SFDR)

Signal-to-noise ratio (SNR)

86

Signal-to-noise + distortion (SINAD)

84.6

(2)

Channel-to-channel isolation

95

:

Effective number of bits (ENOB)

14

:

: Indicates the same specifications as the ADS8342I.

(1)

(2)

(3)

(4)

All typical values are at T = +25°C.

Ensured by design.

A

Applies for 5.0V nominal supply: BV

Applies for 3.0V nominal supply: BV

(min) = 4.5V and BV

(min) = 2.7V and BV

(max) = 5.5V.

(max) = 3.6V.

DD

4

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SBAS277 – MAY 2003

ELECTRICAL CHARACTERISTICS (continued)

Over recommended operating free-air temperature range at –40°C to +85°C, ±AV

= ±DV

DD

= ±5V, BV

= +5V, V

REF

= +2.5V, f

CLK

= 5MHz, and

DD

f

= 250kSPS, unless otherwise noted.

SAMPLE

ADS8342I

(1)

ADS8342IB

(1)

MAX

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

MIN TYP

Voltage Reference Input

Reference voltage

2.0

2.5

100

5

2.55

:

V

Reference input resistance

Reference input capacitance

Reference input current

:

MΩ

pF

nA

25

(3)

5V Digital Inputs

Logic family

CMOS

High-level input voltage (V

)

0.7× BV

–0.3

BV

+ 0.3

V

IH

DD

Low-level input voltage (V

)

0.3× BV

IL

DD

Input leakage current (I

)

IN

V = BV

I DD

or GND

±50

nA

pF

Input capacitance (C )

5

I

(3)

5V Digital Outputs

Logic family

CMOS

High-level output voltage (V

)

I

= –100µA

= +100µA

4.4

V

OH

Low-level output voltage (V

)

0.5

20

OL

High-impeadance-state output current

(I

CS = BV , V = BV

GND

or

DD

O

DD

±50

nA

)

OZ

Output capacitance (C

)

5

pF

O

Load capacitance (C )

L

Data format

Binary Two’s Complement

(4)

3V Digital Inputs

Logic family

LVCMOS

High-level input voltage (V

)

BV

= 3.6V

= 2.7V

2

BV

DD

+ 0.3

V

IH

DD

Low-level input voltage (V

)

–0.3

0.8

IL

DD

Input leakage current (I

)

IN

V = BV

I DD

or GND

±50

nA

pF

Input capacitance (C )

5

I

(4)

3V Digital Outputs

Logic family

LVCMOS

High-level output voltage (V

)

BV

= 2.7V, I

OH

= –100µA BV

– 0.3

DD

V

OH

DD

Low-level output voltage (V

)

= 2.7V, I

OL

= +100µA

0.2

20

OL

DD

High-impeadance-state output current

(I

CS = BV , V = BV

GND

or

DD

O

DD

±50

nA

)

OZ

Output capacitance (C

)

5

pF

O

Load capacitance (C )

L

Data format

Binary Two’s Complement

: Indicates the same specifications as the ADS8342I.

(1)

(2)

(3)

(4)

All typical values are at T = +25°C.

Ensured by design.

A

Applies for 5.0V nominal supply: BV

Applies for 3.0V nominal supply: BV

(min) = 4.5V and BV

(min) = 2.7V and BV

(max) = 5.5V.

(max) = 3.6V.

DD

5

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SBAS277 – MAY 2003

ELECTRICAL CHARACTERISTICS (continued)

Over recommended operating free-air temperature range at –40°C to +85°C, ±AV

= ±DV

DD

= ±5V, BV

= +5V, V

REF

= +2.5V, f

CLK

= 5MHz, and

DD

f

= 250kSPS, unless otherwise noted.

SAMPLE

ADS8342I

(1)

ADS8342IB

(1)

MAX

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

MIN TYP

Power-Supply Requirements

Negative analog power supply (–AV

Positive analog power supply (+AV

)

–5.25

4.75

–5.25

4.75

2.7

–4.75

5.25

–4.75

5.25

3.6

:

V

DD

)

DD

Negative digital power supply (–DV

)

DD

)

Positive digital power supply (+DV

DD

Low-voltage levels

5V logic levels

I/O buffer power supply (BV

)

DD

4.5

+DV

DD

Negative analog operating supply

current (–AI

11.5

13.8

16.8

9.9

:

mA

)

DD

Positive analog operating supply current

(+AI

14

8.3

7.1

:

)

DD

Negative digital operating supply

current (–DI

)

DD

Positive digital operating supply current

(+DI

8.5

)

DD

I/O buffer operating supply current

(BI

BV

= 3V

= 5V

= 3V

0.65

1

0.81

1.25

250

:

mA

mW

DD

)

DD

Power Dissipation

208

: Indicates the same specifications as the ADS8342I.

(1)

(2)

(3)

(4)

All typical values are at T = +25°C.

Ensured by design.

A

Applies for 5.0V nominal supply: BV

Applies for 3.0V nominal supply: BV

(min) = 4.5V and BV

(min) = 2.7V and BV

(max) = 5.5V.

(max) = 3.6V.

DD

6

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SBAS277 – MAY 2003

APPLICATION BLOCK DIAGRAM

Figure 1. ADS8342 Typical Connection Diagram

7

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TQFP PACKAGE

(TOP VIEW)

PIN ASSIGNMENTS—NUMERICAL LISTING

PIN NO.

PIN NAME

PIN NO.

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

PIN NAME

(1)

NC

1

2

BGND

DB8

(1)

NC

3

CLKDIV0

CLKDIV1

A0

DB9

4

DB10

5

DB11

6

A1

DB12

7

BYTE

CONV

RD

DB13

8

DB14

9

DB15 (MSB)

(1)

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

CS

NC

(1)

CLK

+DV

DD

DGND

AGND

–AVDD

AGND

+AVDD

–DV

DD

BUSY

DB0 (LSB)

DB1

(1)

NC

REFIN

DB2

REFGND

(1)

NC

DB3

DB4

COMMON

AIN0

DB5

DB6

AIN1

DB7

AIN2

BV

DD

AIN3

(1)

NC = no connection. These pins should be left unconnected.

8

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Terminal Functions

(1)

TERMINAL

TYPE

NAME

NO.

DESCRIPTION

Analog Input Signals

AIN0

45

AI

Analog input 0

AIN1

46

47

48

44

41

Analog input 1

AIN2

Analog input 2

AIN3

Analog input 3

COMMON

REFIN

Analog input common signal

Reference voltage input pin for external reference voltage. Decouple to reference ground with a 0.1µF

ceramic capacitor.

REFGND

42

AI

Reference ground. Connected to the ground of the external reference voltage.

Digital Interface Signals

A(x)

5, 6

DI

Address decode input, select analog input.

DB(x)

16–23,

26–33

DO

Output 3-state data bus. DB15 (MSB) to DB0 (LSB). Data lines are 3-state during conversion.

RD should be asserted only when the part is not converting.

CS

10

9

DI

Active low chip select signal

RD

Active low read signal

CLK

11

3, 4

8

System clock

CLKDIV(x)

CONV

Select clock divider ratio. Internally divides external clock (pin 11) by 1, 2, 4, or 8.

Convert start. When CONV switches from high to low, the device switches from sample mode to hold

mode, independent of the external clock status. The address for the next conversion will be latched on

low-to-high transition.

BUSY

15

7

DO

DI

BUSY goes high during a conversion and returns low at the end when data is available for reading.

Active high bus width is 8 bits. When BYTE is low, the bus width is 16 bits.

BYTE

Power Supply

+AVDD

39

37

24

12

14

P

Positive analog power supply, +5V . Decouple to analog ground with a 0.1µF ceramic capacitor and a

DC

4.7µF tantalum capacitor. Referenced to the same power supply as +DV

(pin 12).

DD

–AVDD

BVDD

Negative analog power supply –5V . Decouple to analog ground with a 0.1µF ceramic capacitor and

DC

a 4.7µF tantalum capacitor. Referenced to the same power supply as –DV

(pin 14).

DD

Digital I/O power supply in the range 2.7V to DV . Decouple to digital I/O ground with a 0.1µF

DD

ceramic capacitor and a 4.7µF tantalum capacitor.

+DVDD

–DVDD

Positive digital power supply +5V . Decouple to digital ground with a 0.1µF ceramic capacitor and a

DC

4.7µF tantalum capacitor. Referenced to the same power supply as +AV

(pin 39).

DD

Negative digital power supply –5V . Decouple to digital ground with a 0.1µF ceramic capacitor and a

DC

4.7µF tantalum capacitor. Referenced to the same power supply as –AV

(pin 37).

DD

AGND

BGND

DGND

36, 38

25

P

Analog ground. Connected directly to digital ground (pin 13) and digital I/O ground (pin 25).

Digital I/O ground. Connected directly to analog ground (pins 36 and 38) and digital ground (pin 13).

Digital ground. Connected directly to analog ground (pins 36 and 38) and digital I/O ground (pin 25).

13

(1)

AI is analog input, AO is analog output, DI is digital input, DO is digital output, and P is power-supply connection.

9

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SBAS277 – MAY 2003

Figure 2. Timing Diagram

10

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SBAS277 – MAY 2003

(1)(2)

TIMING REQUIREMENTS

Over recommended operating free-air temperature range at –40°C to +85°C, and BV

= +5V, unless otherwise noted.

DD

ADS8342I

ADS8342IB

MIN

17

3

MAX

MIN

MAX

PARAMETER

SYMBOL

UNIT

Conversion time

t

:

t

CONV

C1

Acquisition time

t

:

t

ACQ

C1

CLK period

t

0.2

25

40

0

2

:

µs

ns

C1

CLK high time (for 5MHz clock frequency)

CLK low time (for 5MHz clock frequency)

CONV low to CLK high

CONV low time

t

:

W1

t

:

W2

t

:

D1

t

:

W3

CS low to CONV low

CONV low to BUSY high

t

:

D2

t

70

60

:

D3

(3)

CONV and CS high to 2nd CLK high

t

80

:

D4

18 CLK high to BUSY low

18 CLK low to CS low

CS low to RD low

CS high time

t

D5

t

0

:

D6

t

D7

t

40

25

:

W4

RD low time

t

40

:

W5

RD low to data valid

RD high to CS high

Data hold from RD high

RD high to CONV low

RD high time

t

D8

t

0

5

:

D9

t

D10

t

1.5

40

20

40

10

t

D11

C1

t

ns

W6

(4)

BYTE change to RD low

t

D12

A0 and A1 to CONV low

t

D13

A0 and A1 hold to CONV high

t

D14

: Indicates the same specifications as the ADS8342I.

(1)

(2)

(3)

(4)

All input signals are specified with rise and fall times of 5ns, t = t = 5ns (10% to 90% of BV ), and timed from a voltage level of (V + V )/2.

DD IL IH

See timing diagram in Figure 2.

R

F

CS can stay low during conversion. If it is not held low, then CS high to 2nd CS high must be > 80ns (t

)

D4

BYTE is asynchronous. When BYTE is 0, bits 15 through 0 appear at DB15–DB0. When BYTE is 1, bits 15 through 8 appear on DB7–DB0.

RD may remain low between changes in BYTE.

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TYPICAL CHARACTERISTICS

At T = +25°C, +AV

= +DV

DD DD

= +5V, BV

DD

= 5V, V

REF

= +2.5V, f

CLK

= 5MHz, and f = 250kHz, unless otherwise noted.

SAMPLE

A

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

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TYPICAL CHARACTERISTICS (continued)

At T = +25°C, +AV

DD

= +DV

DD

= +5V, BV

DD

= 5V, V

REF

= +2.5V, f

CLK

= 5MHz, and f = 250kHz, unless otherwise noted.

SAMPLE

A

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

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TYPICAL CHARACTERISTICS (continued)

At T = +25°C, +AV

= +DV

DD DD

= +5V, BV

DD

= 5V, V

REF

= +2.5V, f

CLK

= 5MHz, and f = 250kHz, unless otherwise noted.

SAMPLE

A

Figure 15

Figure 17

Figure 19

Figure 16

Figure 18

Figure 20

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THEORY OF OPERATION

The ADS8342 is a classic successive approximation

register (SAR) analog–to–digital converter (ADC). The

architecture is based on capacitive charge redistribution

that inherently includes a sample–and–hold function. The

converter is fabricated on a 0.5µm CMOS process. The

architecture and process allow the ADS8342 to acquire

and convert an analog signal at up to 250,000 conversions

per second, while consuming less than 200mW.

Figure 21. Simplified Diagram of the Analog Input

Table 1. Input Channel Selection

The ADS8342 requires an external reference, an external

clock, and a dual power source (±5V). When a digital

interface voltage (BV^DD) different from +5V is desired, a

triple power source is required (±5V and BVDD). The

external reference can be between 2V and 2.55V. The

value of the reference voltage directly sets the range of the

analog input.

A1

0

A0

0

AIN0

+IN

—

AIN1

—

AIN2

—

AIN3 COMMON

—

–IN

0

1

+IN

—

1

0

—

+IN

—

The external clock can vary between 500kHz (25kHz

throughput) and 5MHz (250kHz throughput). The

minimum clock frequency is set by the leakage on the

internal capacitors to the ADS8342.

1

—

+IN

When the converter enters the hold mode, the voltage

difference between the +IN and –IN inputs (Figure 21) is

captured on the internal capacitor array.

The analog inputs to the ADC consists of two input pins:

AINx and COMMON. The positive input to the ADC, AINx,

is one of four analog channels (AIN0 to AIN3) and is

selected by the front-end multiplexer. When a conversion

is initiated, the differential input on these pins is sampled

on to the internal capacitor array. While a conversion is in

progress, both inputs are disconnected from any internal

function.

SAMPLE-AND-HOLD CIRCUIT

The sample-and-hold circuit on the ADS8342 allows the

ADC to accurately convert an input sine wave of full-scale

amplitude to 16-bit accuracy. The input bandwidth of the

sample-and-hold circuit is greater than the Nyquist rate

(Nyquist equals one-half of the sampling rate) of the ADC

even when the ADC is operated at its maximum

throughput rate of 250kHz.

MULTIPLEXER

Typical aperture delay time, or the time it takes for the

ADS8342 to switch from sample mode to hold mode

following the start of conversion, is 8ns. The average delta

of repeated aperture delay values (also known as aperture

jitter) is typically 50ps. These specifications reflect the

ability of the ADS8342 to capture AC input signals

accurately.

The ADS8342 has an input multiplexer (MUX) that is used

to select the desired positive analog input, and connect the

sample-and-hold circuit and ADC to it. MUX address pins

A0 and A1 are decoded to select the MUX channel; Table 1

shows information on selecting the input channel. Both the

AINx and COMMON input signal voltages are sampled

and held simultaneously to provide the best possible noise

rejection.

ANALOG INPUT

Figure 21 shows a block diagram of the input multiplexer

on the ADS8342. The differential input of the converter is

derived from one of the four inputs in reference to the

COMMON pin. Table 1 shows the relationship between

the A1 and A0 control bits and the selection of the analog

multiplexer. The control bits are provided via input pins;

see the Digital Interface section of this data sheet for more

details.

The analog input of ADS8342 is bipolar and

pseudo-differential, as shown in Figure 22. The AIN0 to

AIN3 and COMMON input pins allow for a differential input

signal. The amplitude of the input is the difference between

the AINx and COMMON inputs, or AINx – COMMON.

Unlike some converters of this type, the COMMON input

is not resampled later in the conversion cycle. When the

converter goes into hold mode, the voltage difference

between AINx and COMMON is captured on the internal

capacitor array.

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±

Figure 22. Pseudo-Differential Input Mode of the ADS8342

The range of the COMMON input is limited to –0.1V to

+0.1V. Due to this, the differential input can be used to

reject signals that are common to both inputs in the

specified range. Thus, the COMMON input is best used to

sense a remote signal ground that may move slightly with

respect to the local ground potential.

Often, a small capacitor (100pF) between the positive and

negative inputs helps to match their impedance. To obtain

good performance from the ADS8342, the input circuit

from Figure 24 is recommended.

The general method for driving the analog input of the

ADS8342 is shown in Figure 23 and Figure 24. The

COMMON input is held at the common-mode voltage. The

AINx input swings from COMMON – V^REFto COMMON +

V^REF, and the peak-to-peak amplitude is 2 x VREF.

Figure 23. Method for Driving the ADS8342

The input current required by the analog inputs depends

on a number of factors, such as sample rate, input voltage,

and source impedance. Essentially, the current into the

ADS8342 analog inputs charges the internal capacitor

array during the sample period. After this capacitance has

been fully charged, there is no further input current. The

source of the analog input voltage must be able to charge

the input capacitance (20pF) to a 16-bit settling level within

3 clock cycles (600ns). When the converter goes into hold

mode, the input impedance is greater than 1GΩ.

Figure 24. Single-Ended Method of Interfacing

the ADS8342

REFERENCE AND REFGND INPUTS

The reference input of the ADS8342, REFIN, is buffered

with an internal reference amplifier. The reference

amplifier buffers the reference input from the switching

currents needed to charge and discharge the internal

capacitor DAC (CDAC), and therefore, the need to provide

an external reference capable of supplying these

switching currents is eliminated.

Care must be taken regarding the absolute analog input

voltage. To maintain the linearity of the converter, the

COMMON input should not drop below AGND – 0.1V, or

exceed AGND + 0.1V. The AINx input must always remain

within the range of COMMON – V^REFto COMMON + VREF.

The reference ground input, REFGND, is connected directly

to the CDAC. During the conversion, currents to charge and

discharge the CDAC flow through the REFGND pin. For that

reason, it is important that REFGND has a low-impedance

connection to ground.

To minimize noise, low bandwidth input signals or

low-pass filters must be used. In each case, care must be

taken to ensure that the output impedance of the sources

driving the AINx and COMMON inputs are matched.

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The external reference voltage sets the analog input

voltage range. The ADS8342 can operate with a reference

between 2.0V and 2.55V. There are several important

implications to this.

As the reference voltage is reduced, the analog voltage

weight of each digital output code is reduced. This is often

referred to as the least significant bit (LSB) size and is

equal to the reference voltage divided by 32,768. This

means that any offset or gain error inherent in the ADC

appears to increase (in terms of LSB size) as the reference

voltage is reduced. For a reference voltage of 2V, the value

of the LSB is 61.035µV. For a reference voltage of 2.5V, the

LSB is 76.294µV.

The noise inherent in the converter also appears to

increase with a lower LSB size. With a 2.5V reference, the

internal noise of the converter typically contributes only

1.5LSBs peak-to-peak of potential error to the output code.

When the external reference is 2.0V, the potential error

contribution from the internal noise is larger (2LSBs). The

errors due to the internal noise are Gaussian in nature and

can be reduced by averaging consecutive conversion

results.

Figure 25. Histogram of 8192 Conversions of a

DC Input at Code Transition

To obtain optimum performance from the ADS8342, a

0.22µF ceramic capacitor must be connected as close as

possible to the REFIN pin, to reduce noise coupling into

this high impedance input. Because the reference voltage

is internally buffered, a high output impedance reference

source can be used without the need for an additional

operational amplifier to drive the REFIN pin.

Figure 26. Histogram of 8192 Conversions of a

DC Input at Code Center

NOISE

The transition noise of the ADS8342 is extremely low, as

shown in Figure 25 and Figure 26. These histograms were

generated by applying a low-noise dc input and initiating

8192 conversions. The digital output of the ADC varies in

output code due to the internal noise of the ADS8342. This

is true for all 16-bit, SAR-type ADCs. Using a histogram to

plot the output codes, the distribution should appear

bell–shaped with the peak of the bell curve representing

the nominal code for the input value. The ±1σ, ±2σ, and

±3σ distributions will represent the 68.3%, 95.5%, and

99.7%, respectively, of all codes. The transition noise is

calculated by dividing the number of codes measured by

6, and yields the ±3σ distribution, or 99.7%, of all codes.

Statistically, up to three codes could fall outside the

distribution when executing 1000 conversions. The

ADS8342, with less than three output codes for the ±3σ

distribution, will yield < ±0.5LSBs of transition noise.

Remember, to achieve this low-noise performance, the

peak-to-peak noise of the input signal and reference must

be < 50µV.

Note that the effective number of bits (ENOB) figure is

calculated based on the ADC signal-to-noise (SNR) ratio

with a 10kHz, –0.2dB input signal. SNR is related to ENOB

as follows:

SNR = 6.02 × ENOB + 1.76

AVERAGING

The noise of the ADC can be compensated by averaging

the digital codes. By averaging conversion results,

transition noise is reduced by a factor of 1/ √n, where n is

the number of averages. For example, averaging four

conversion results will reduce the transition noise from

±0.5LSB to ±0.25LSB. Averaging should only be used for

input signals with frequencies near DC.

For AC signals, a digital filter can be used to low-pass filter

and decimate the output codes. This works in a similar

manner to averaging; for every decimation by 2, the

signal-to-noise ratio will improve by 3dB.

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5MHz is available. For example, if a digital signal processor

(DSP) uses a 20MHz clock, it is possible to set up the internal

clock divider of the ADS8342 to divide the input clock

frequency by four, to provide an internal clock speed of 5MHz.

Table 2 shows the maximum applicable external clock

frequency as a function of the CLKDIV0 and CLKDIV1 signals.

DIGITAL INTERFACE

SIGNAL LEVELS

The ADS8342 digital interface accommodates different

logic levels. The digital interface circuit is designed to

operate using 2.7V to 5.5V logic levels. When the

ADS8342 interface power-supply voltage is in the range of

4.5V to 5.5V (5V logic level), the ADS8342 can be

connected directly to another 5V CMOS integrated circuit.

If the ADS8342 interface power-supply voltage is in the

range of 2.7V to 3.6V, the ADS8342 can be connected

directly to another 3.3V LVCMOS integrated circuit. Note

that digital inputs must not exceed BVDD by more than

+0.3V.

Table 2. Clock Divider Selection

CLOCK MAX INPUT

INTERNAL

RATIO FREQUENCY FREQUENCY

CLKDIV1 CLKDIV0

(1:n)

(MHz)

5

(MHz)

0

1

0

1

0

1

2

4

8

5

10

20

5

20

2.5

TIMING AND CONTROL

The ADS8342 uses a parallel control interface consisting

of the following digital input pins: CS, RD, CONV, CLK,

BYTE, A0, A1, CLKDIV0, and CLKDIV1. The following

pins are digital outputs: BUSY, and DB1 to DB15. See

Figure 2 (page 10) for a typical timing diagram.

Note that all timing diagrams and specifications are

referenced to a clock divider ratio of 1:1 and an external

clock frequency of 5MHz. For higher clock input

frequencies, there will be a minor increase in power

consumption and a possible increase in noise.

BUSY—The digital output signal, BUSY, provides an external

indication that a conversion is taking place. BUSY goes high a

maximum of 70ns after a conversion is initiated (see Figure 2,

tD3) and remains high until the end of the conversion. When

BUSY goes low at the end of the conversion, the data from the

conversion in progress is latched into the ADC output registers

and is ready to be read. The BUSY signal remains low until

another conversion is started by bringing CS and CONV low.

The CS input enables the digital interface of the ADS8342.

CS and CONV start a conversion and CS and RD allow the

output data to be read.

BYTE controls the data output bus width. A0 and A1 select

the input MUX channel and CLKDIV0 and CLKDIV1 select

the internal clock divider ratio.

The ADS8342 needs an external clock, CLK ( pin 11), that

controls the conversion rate of the ADC. A typical conversion

cycle takes 20 clock cycles: 17 for conversion and 3 for signal

acquisition. A 250kHz sample rate can be achieved with a

5MHz external clock and a clock divider ratio of 1. This

corresponds to a 4µs maximum throughput period.

A0 AND A1—The digital inputs, A0 and A1, are MUX address

lines used to select the positive analog input MUX channel to

use for conversion. When a conversion is started with CS and

CONV, the Ax inputs are latched into registers on the rising

edge of CS or CONV. The latched MUX inputs control the state

of the MUX for the next conversion following the current

conversion. At the end of the conversion, the analog input

returns to the sampling mode and samples the MUX channel

that was latched during the previous conversion start.

The following list describes some of the pins used:

CLK—An external clock must be provided to the ADS8342 via

the digital input pin CLK. The frequency of the externally

provided clock can be divided down inside the ADS8342 to

provide a slower internal clock frequency for the ADS8342.

The maximum internal clock frequency is 5MHz. The

minimum internal clock period is 200ns (see Figure 2, t^C1).

The clock duty cycle (HIGH/LOW) for an external clock of

5MHz can range up to 40/60 to 60/40.

BYTE—The BYTE signal can be used in conjunction with the

RD signal to control the output data bus width. If BYTE is

held low, the ADS8342 operates in 16-bit output mode and

the output data is read on pins DB15 to DB0. When an 8-bit

bus interface is required, the 16-bit output word can be

read using eight data lines by toggling the RD and BYTE

signals. The lower eight data output bits are read on output

pins D7 to D0 when BYTE is low. The higher eight data

output bits are read on the same output pins, D7 to D0,

when BYTE is high (see Figure 2).

CLKDIVx—The CLKDIVx digital input pins are decoded to

select the clock frequency divider ratio that divides the

external clock frequency for use internal to the ADS8342. This

feature is useful for systems where a clock rate higher than

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For best performance, none of the input control lines

should change state after 80ns prior to the rising edge of

the second clock in the conversion, as previously

described.

START OF A CONVERSION (CS AND CONV)

CS and CONV are NORed together internally and must

both be low to start a conversion. Bringing both the CS and

CONV signals low for 40ns will start a conversion.

Immediately after a conversion is started, the analog

inputs, the selected MUX channel input, and the

COMMON input are held by the sample–and–hold circuit

(8ns).

READING DATA (RD, CS)—CS and RD are NORed

together internally and both must be low to enable the data

outputs. During the conversion, the data outputs are tri-state

and cannot be read. After a conversion has completed, both

CS and RD must be low for at least 40ns (see Figure 2, tW5)

to enable the outputs. The output data can be latched into

external registers using the rising edge of RD and another

conversion can be started 1.5 clocks following the rising edge

of RD. Before bringing RD back low for a subsequent read

command, it must remain high for at least 40ns (see Figure 2,

tW6)

The conversion starts on the next rising edge of the clock

signal following the conversion start signal, if the

conversion is started at least 40ns before the rising edge

of the next clock (see Figure 2, tD1). The CONV

signal—and CS if it is not always held low—needs to go

high 80ns before the rising edge of the second clock cycle

of the conversion in order to reduce noise caused by bus

activity on the control interface, which can disturb critical

comparator decisions made during the conversion. Once

CONV goes high, it has to stay high during the entire

conversion period (see Figure 2).

When BUSY rises after a conversion is initiated, the data

outputs will become tri-state regardless of the state of RD.

Noise will be generated when the enabled outputs

transition to tri–state, which can affect the results of the

conversion. To obtain best performance, it is

recommended to read the output data immediately after

the BUSY signal goes low at the end of conversion and to

bring RD high prior to starting the next conversion.

After a conversion has been started, the rising edge of

either CS or CONV, whichever is first, latches the MUX

address on pins A0 and A1 in a register. This address is

used to select the channel that will be converted upon the

next conversion start. After a conversion is finished (17

clock cycles), the sample-and-hold circuit switches from

hold mode to sample mode in order to sample the MUX

channel address that was latched during the previous

conversion start. The start of the next conversion can be

initiated after the input capacitor of the ADS8342 is fully

charged. This signal acquisition time depends on the

driving amplifier, but should be at least 600ns.

DATA FORMAT

The output data from the ADS8342 is in binary two’s

complement (BTC) format (see Figure 27). This figure

represents the ideal output code for a given input voltage and

does not include the effects of offset, gain error, or noise.

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Figure 27. Ideal Conversion Characteristics (V

= 0V and V

= 2.5V)

CM

REF

LAYOUT

For optimum performance, care should be taken with the

physical layout of the ADS8342 circuitry. This is

particularly true if the ADC is approaching the maximum

throughput rate.

addition, a 1µF to 4.7µF capacitor is recommended. If

needed, an even larger capacitor and a 5Ω or 10Ω series

resistor can be used to low-pass filter a noisy supply.

The ADS8342 draws very little current from an external

reference because the reference voltage is internally

buffered. The V^REFpin should be bypassed with a 0.22µF

capacitor. An additional larger capacitor can also be used,

if desired. If the reference voltage originates from an op

amp, make sure that it can drive the bypass capacitor or

capacitors without oscillation.

During the ADC conversion, the basic SAR architecture is

sensitive to glitches or sudden changes in the power

supply, reference, ground connections, and digital inputs.

Such glitches might originate from switching power

supplies, nearby digital logic, or high power devices. The

degree of error in the digital output depends on the

reference voltage, layout, and the exact timing of the

external event. The digital output error can change if the

external event changes in time with respect to the CLK

input.

The REFGND and GND pins should be connected to a

quiet ground. In many cases, this will be the analog

ground. Avoid connections that are too near to the

grounding point of a microcontroller or DSP. The ideal

layout should include an analog ground plane dedicated to

the converter and associated analog circuitry.

With this in mind, power to the ADS8342 must be quiet and

well bypassed. The 0.1µF ceramic bypass capacitors

should be placed as close to the device as possible.In

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APPLICATION INFORMATION

Figure 1 shows a typical connection diagram. Different connection diagrams to DSPs or microcontrollers are shown in

Figure 28 thru Figure 31.

Figure 28.

Figure 30.

Figure 29.

Figure 31.

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PFB (S-PQFP-G48)

PLASTIC QUAD FLATPACK

0,27

0,17

M

0,50

0,08

36

25

37

24

48

13

0,13 NOM

1

12

5,50 TYP

7,20

SQ

Gage Plane

6,80

9,20

SQ

8,80

0,25

0,05 MIN

0°–7°

ā

1,05

0,95

0,75

0,45

Seating Plane

0,08

1,20 MAX

4073176/B 10/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

22

PACKAGE OPTION ADDENDUM

www.ti.com

3-Oct-2003

PACKAGING INFORMATION

ORDERABLE DEVICE

STATUS(1)

PACKAGE TYPE

PACKAGE DRAWING

PINS

PACKAGE QTY

ADS8342IBPFBR

ADS8342IBPFBT

ADS8342IPFBR

ADS8342IPFBT

ACTIVE

TQFP

PFB

48

2000

250

2000

250

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

IMPORTANT NOTICE

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enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

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and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

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型号：	ADS8342_14
厂家：	TEXAS INSTRUMENTS
描述：	True Bipolar Input Input Signal Range: Â±2.5V
文件：	总24页 (文件大小：815K)
中文：	中文翻译
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ADS8342_14 [TI]

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