ADS8343 [TI]

16 位 4 通道串行输出采样模数转换器;


型号：	ADS8343
厂家：	TEXAS INSTRUMENTS
描述：	16 位 4 通道串行输出采样模数转换器转换器模数转换器
文件：	总25页 (文件大小：1421K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS8343

343

SBAS183C – JANUARY 2001 – REVISED APRIL 2003

16-Bit, 4-Channel Serial Output Sampling

ANALOG-TO-DIGITAL CONVERTER

DESCRIPTION

FEATURES

ꢀ BIPOLAR INPUT RANGE

The ADS8343 is a 4-channel, 16-bit sampling Analog-to-

Digital (A/D) converter with a synchronous serial interface.

Typical power dissipation is 8mW at a 100kHz throughput

rate and a +5V supply. The reference voltage (V_REF) can be

varied between 500mV and V_CC/2, providing a corresponding

input voltage range of ±V_REF. The device includes a shut-

down mode which reduces power dissipation to under 15µW.

The ADS8343 is ensured down to 2.7V operation.

ꢀ PIN-FOR-PIN COMPATIBLE WITH THE

ADS7841 AND ADS8341

ꢀ SINGLE SUPPLY: 2.7V to 5V

ꢀ 4-CHANNEL SINGLE-ENDED OR

2-CHANNEL DIFFERENTIAL INPUT

ꢀ UP TO 100kHz CONVERSION RATE

ꢀ 86dB SINAD

Low power, high speed, and an onboard multiplexer make

the ADS8343 ideal for battery-operated systems such as

personal digital assistants, portable multi-channel data log-

gers, and measurement equipment. The serial interface also

provides low-cost isolation for remote data acquisition. The

ADS8343 is available in an SSOP-16 package and is en-

sured over the –40°C to +85°C temperature range.

ꢀ SERIAL INTERFACE

ꢀ SSOP-16 PACKAGE

APPLICATIONS

ꢀ DATA ACQUISITION

ꢀ TEST AND MEASUREMENT

ꢀ INDUSTRIAL PROCESS CONTROL

ꢀ PERSONAL DIGITAL ASSISTANTS

ꢀ BATTERY-POWERED SYSTEMS

SAR

DCLK

CH0

Comparator

SHDN

Serial

Interface

and

Four

Channel

Multiplexer

CH1

DIN

CDAC

CH2

DOUT

BUSY

Control

CH3

COM

V_REF

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

www.ti.com

PACKAGE/ORDERING INFORMATION

MAXIMUM

INTEGRAL

LINEARITY

ERROR (LSB)

MISSING

CODES

SPECIFIED

TEMPERATURE

RANGE

PACKAGE

DESIGNATOR⁽¹⁾

ORDERING

NUMBER

TRANSPORT

MEDIA, QUANTITY

PRODUCT

ERROR (LSB)

PACKAGE-LEAD

ADS8343E

SSOP-16

DBQ

–40°C to +85°C

ADS8343E

ADS8343E/2K5

ADS8343EB

Rails, 100

Tape and Reel, 2500

Rails, 100

DBQ

ADS8343EB

SSOP-16

–40°C to +85°C

ADS8343EB/2K5 Tape and Reel, 2500

NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

PIN CONFIGURATIONS

+V_CCto GND ........................................................................ –0.3V to +6V

Analog Inputs to GND ............................................ –0.3V to +V_CC+ 0.3V

Digital Inputs to GND ........................................................... –0.3V to +6V

Power Dissipation .......................................................................... 250mW

Maximum Junction Temperature ................................................... +150°C

Operating Temperature Range ........................................–40°C to +85°C

Storage Temperature Range .........................................–65°C to +150°C

Lead Temperature (soldering, 10s)............................................... +300°C

Top View

SSOP

+V_CC

CH0

16 DCLK

15 CS

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”

may cause permanent damage to the device. Exposure to absolute maximum

conditions for extended periods may affect device reliability.

CH1

14 DIN

CH2

13 BUSY

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-

ments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

ADS8343

CH3

12 DOUT

11 GND

10 GND

COM

SHDN

V_REF

+V_CC

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet its

published specifications.

PIN DESCRIPTIONS

NAME

DESCRIPTION

+V_CC

CH0

Power Supply, 2.7V to 5V

Analog Input Channel 0

Analog Input Channel 1

Analog Input Channel 2

Analog Input Channel 3

CH1

CH2

CH3

COM

SHDN

V_REF

+V_CC

GND

DOUT

BUSY

DIN

Common reference for analog inputs. This pin is typically connected to V_REF.

Shutdown. When LOW, the device enters a very low power shutdown mode.

Voltage Reference Input. See Electrical Characteristic Table for ranges.

Power Supply, 2.7V to 5V

Ground

Serial Data Output. Data is shifted on the falling edge of DCLK. This output is high impedance when CS is HIGH.

Busy Output. This output is high impedance when CS is HIGH.

Serial Data Input. If CS is LOW, data is latched on rising edge of DCLK.

Chip Select Input. Controls conversion timing and enables the serial input/output register.

DCLK

External Clock Input. This clock runs the SAR conversion process and synchronizes serial data I/O. Maximum input clock frequency

equals 2.4MHz to achieve 100kHz sampling rate.

ADS8343

SBAS183C

www.ti.com

ELECTRICAL CHARACTERISTICS: +5V

At T_A= –40°C to +85°C, +V_CC= +5V, V_REF= +2.5V, f_SAMPLE= 100kHz, and f_CLK= 24 • f_SAMPLE= 2.4MHz, unless otherwise noted.

ADS8343E

TYP

ADS8343EB

PARAMETER

RESOLUTION

CONDITIONS

MIN

MAX

MIN

TYP

MAX

UNITS

ꢀ

Bits

ANALOG INPUT

Full-Scale Input Span

Absolute Input Range

Positive Input-Negative Input

Positive Input

–V_REF

–0.2

+V_REF

+V_CC+ 0.2

ꢀ

Negative Input

Capacitance

Leakage Current

±1

ꢀ

µA

SYSTEM PERFORMANCE

No Missing Codes

Integral Linearity Error

Bipolar Error

Bipolar Error Match

Gain Error

Gain Error Match

Noise

Power-Supply Rejection

Bits

LSB

LSB⁽¹⁾

LSB

±8

±2

8.0

±0.05

4.0

±6

±1

ꢀ

±0.024

ꢀ

2.3

ꢀ

1.0

ꢀ

µVrms

LSB⁽¹⁾

+4.75V < V_CC< 5.25V

SAMPLING DYNAMICS

Conversion Time

Acquisition Time

ꢀ

Clk Cycles

kHz

4.5

ꢀ

Throughput Rate

100

Multiplexer Settling Time

Aperture Delay

Aperture Jitter

Internal Clock Frequency

External Clock Frequency

500

100

2.4

ꢀ

MHz

SHDN = V_DD

0.024

2.4

ꢀ

Data Transfer Only

DYNAMIC CHARACTERISTICS

Total Harmonic Distortion⁽²⁾

Signal-to-(Noise + Distortion)

Spurious-Free Dynamic Range

Channel-to-Channel Isolation

V_IN= 5Vp-p at 10kHz

V_IN= 5Vp-p at 50kHz

–95

ꢀ

100

REFERENCE INPUT

Range

Resistance

0.5

+V_CC/2

100

ꢀ

DCLK Static

2.5

ꢀ

GΩ

µA

Input Current

f_SAMPLE= 12.5kHz

DCLK Static

0.001

DIGITAL INPUT/OUTPUT

Logic Family

Logic Levels

V_IH

V_IL

V_OH

CMOS

ꢀ

| I_IH| ≤ +5µA

| I_IL| ≤ +5µA

I_OH= –250µA

I_OL= 250µA

3.0

–0.3

3.5

5.5

+0.8

ꢀ

V_OL

Data Format

0.4

ꢀ

Binary Two’s Complement

POWER-SUPPLY REQUIREMENTS

+V_CC

Quiescent Current

Specified Performance

f_SAMPLE= 10kHz

4.75

5.25

2.0

ꢀ

µA

1.5

150

ꢀ

Power-Down Mode^{(3, 4)}

CS = +V_CC

ꢀ

Power Dissipation

7.5

TEMPERATURE RANGE

Specified Performance

–40

+85

ꢀ

°C

ꢀ Same specifications as ADS8343E.

NOTES: (1) LSB means Least Significant Bit. With V_REFequal to +2.5V, one LSB is 76µV. (2) First nine harmonics of the test frequency. (3) Auto power-down mode

(PD1 = PD0 = 0) active or SHDN = GND. (4) Power-down after conversion mode with external clock gated ‘HIGH’.

ADS8343

SBAS183C

www.ti.com

ELECTRICAL CHARACTERISTICS: +2.7V

At T_A= –40°C to +85°C, +V_CC= +2.7V, V_REF= +1.25V, f_SAMPLE= 100kHz, and f_CLK= 24 • f_SAMPLE= 2.4MHz, unless otherwise noted.

ADS8343E

TYP

ADS8343EB

TYP

PARAMETER

RESOLUTION

CONDITIONS

MIN

MAX

MIN

MAX

UNITS

BITS

ꢀ

ANALOG INPUT

Full-Scale Input Span

Absolute Input Range

Positive Input-Negative Input

Positive Input

–V_REF

–0.2

+V_REF

+V_CC+ 0.2

ꢀ

Negative Input

Capacitance

Leakage Current

±1

ꢀ

µA

SYSTEM PERFORMANCE

No Missing Codes

Integral Linearity Error

Bipolar Error

Bipolar Error Match

Gain Error

Gain Error Match

Noise

Power-Supply Rejection

Bits

LSB

% of FSR

LSB

±12

±1

4.0

±0.05

4.0

±8

±0.5

ꢀ

±0.0024

ꢀ

1.2

ꢀ

1.0

ꢀ

µVrms

LSB⁽¹⁾

+2.7 < V_CC< +3.3V

SAMPLING DYNAMICS

Conversion Time

Acquisition Time

ꢀ

Clk Cycles

kHz

4.5

ꢀ

Throughput Rate

100

Multiplexer Settling Time

Aperture Delay

Aperture Jitter

Internal Clock Frequency

External Clock Frequency

500

100

2.4

ꢀ

MHz

SHDN = V_DD

0.024

2.4

2.0

2.4

ꢀ

When Used with Internal Clock

Data Transfer Only

DYNAMIC CHARACTERISTICS

Total Harmonic Distortion⁽²⁾

Signal-to-(Noise + Distortion)

Spurious-Free Dynamic Range

Channel-to-Channel Isolation

V_IN= 2.5Vp-p at 1kHz

–94

ꢀ

_IN= 2.5Vp-p at 1kHz

V_IN= 2.5Vp-p at 10kHz

100

REFERENCE INPUT

Range

Resistance

0.5

+V_CC/2

ꢀ

DCLK Static

2.5

ꢀ

GΩ

µA

Input Current

f_SAMPLE= 12.5kHz

DCLK Static

0.001

DIGITAL INPUT/OUTPUT

Logic Family

Logic Levels

V_IH

V_IL

V_OH

CMOS

ꢀ

| I_IH| ≤ +5µA

| I_IL| ≤ +5µA

I_OH= –250µA

I_OL= 250µA

+V_CC• 0.7

–0.3

+V_CC• 0.8

5.5

+0.8

ꢀ

V_OL

Data Format

0.4

ꢀ

Binary Two’s Complement

POWER-SUPPLY REQUIREMENTS

+V_CC

Quiescent Current

Specified Performance

f_SAMPLE= 10kHz

2.7

3.6

1.85

ꢀ

µA

1.2

105

ꢀ

Power-Down Mode^{(3, 4)}

CS = +V_CC

ꢀ

Power Dissipation

3.2

TEMPERATURE RANGE

Specified Performance

–40

+85

ꢀ

°C

ꢀ Same specifications as ADS8343E.

NOTES: (1) LSB means Least Significant Bit. With V_REFequal to +1.25V, one LSB is 38µV. (2) First nine harmonics of the test frequency. (3) Auto power-down mode

(PD1 = PD0 = 0) active or SHDN = GND. (4) Power-down after conversion mode with external clock gated ‘HIGH’.

ADS8343

SBAS183C

www.ti.com

TYPICAL CHARACTERISTICS: +5V

At T_A= +25°C, +V_CC= +5V, V_REF= +2.5V, f_SAMPLE= 100kHz, and f_CLK= 24 • f_SAMPLE= 2.4MHz, unless otherwise noted.

FREQUENCY SPECTRUM

(4096 Point FFT; f_IN= 1.001kHz, –0.2dB)

FREQUENCY SPECTRUM

(4096 Point FFT; f_IN= 9.985kHz, –0.2dB)

–20

–40

–60

–80

–100

–120

–140

–100

–120

–140

Frequency (kHz)

SIGNAL-TO-NOISE RATIO AND

SIGNAL-TO-(NOISE + DISTORTION)

vs INPUT FREQUENCY

SPURIOUS-FREE DYNAMIC RANGE AND

TOTAL HARMONIC DISTORTION

vs INPUT FREQUENCY

100

110

100

–110

–100

–90

SFDR

SNR

THD⁽¹⁾

–80

SINAD

–70

NOTE: (1) First nine harmonics of the input frequency.

–60

100

Frequency (kHz)

EFFECTIVE NUMBER OF BITS

vs INPUT FREQUENCY

CHANGE IN SIGNAL-TO-(NOISE + DISTORTION)

vs TEMPERATURE

0.1

15.0

14.5

14.0

13.5

13.0

12.5

12.0

11.5

11.0

f_IN= 4.956kHz, –0.2dB

–0.1

–0.2

–0.3

100

–50

–25

100

Frequency (kHz)

Temperature (°C)

ADS8343

SBAS183C

www.ti.com

TYPICAL CHARACTERISTICS: +5V (Cont.)

At T_A= +25°C, +V_CC= +5V, V_REF= +2.5V, f_SAMPLE= 100kHz, and f_CLK= 24 • f_SAMPLE= 2.4MHz, unless otherwise noted.

INTEGRAL LINEARITY ERROR vs CODE

DIFFERENTIAL LINEARITY ERROR vs CODE

–1

–2

–3

–4

–1

–2

–3

8000_H

C000_H

0000_H

4000_H

7FFF_H

8000_H

C000_H

0000_H

4000_H

7FFF_H

Output Code

SUPPLY CURRENT vs TEMPERATURE

CHANGE IN BPZ vs TEMPERATURE

1.6

1.5

1.4

1.3

1.2

–1

–2

–3

–4

–50

–25

100

–50

–25

100

Temperature (°C)

WORST-CASE CHANNEL-TO-CHANNEL

BPZ MATCH vs TEMPERATURE

CHANGE IN GAIN vs TEMPERATURE

1.0

0.5

4.5

4.0

3.5

3.0

–0.5

–50

–25

100

–50

–25

100

Temperature (°C)

ADS8343

SBAS183C

www.ti.com

TYPICAL CHARACTERISTICS: +5V (Cont.)

At T_A= +25°C, +V_CC= +5V, V_REF= +2.5V, f_SAMPLE= 100kHz, and f_CLK= 24 • f_SAMPLE= 2.4MHz, unless otherwise noted.

WORST CASE CHANNEL-TO-CHANNEL

GAIN MATCH vs TEMPERATURE

COMMON-MODE REJECTION vs FREQUENCY

0.4

0.3

0.2

0.1

100

V_CM= 2Vp-p Sinewave

Centered Around V_REF

–0.1

–50

–25

100

0.1

100

Temperature (°C)

Frequency (kHz)

TYPICAL CHARACTERISTICS: +2.7V

At T_A= +25°C, +V_CC= +2.7V, V_REF= +1.25V, f_SAMPLE= 100kHz, and f_CLK= 24 • f_SAMPLE= 2.4MHz, unless otherwise noted.

FREQUENCY SPECTRUM

(4096 Point FFT; f_IN= 1.001kHz, –0.2dB)

(4096 Point FFT; f_IN= 9.985kHz, –0.2dB)

–20

–40

–60

–80

–100

–120

–140

–100

–120

–140

Frequency (kHz)

SIGNAL-TO-NOISE RATIO AND

SIGNAL-TO-(NOISE + DISTORTION)

vs INPUT FREQUENCY

SPURIOUS-FREE DYNAMIC RANGE AND

TOTAL HARMONIC DISTORTION

vs INPUT FREQUENCY

100

–100

–90

–80

–70

–60

–50

SNR

SFDR

SINAD

THD⁽¹⁾

NOTE: (1) First nine harmonics of the input frequency.

500

100

Frequency (kHz)

ADS8343

SBAS183C

www.ti.com

TYPICAL CHARACTERISTICS: +2.7V (Cont.)

At T_A= +25°C, +V_CC= +2.7V, V_REF= +1.25V, f_SAMPLE= 100kHz, and f_CLK= 24 • f_SAMPLE= 2.4MHz, unless otherwise noted.

EFFECTIVE NUMBER OF BITS

vs INPUT FREQUENCY

CHANGE IN SIGNAL-TO-(NOISE + DISTORTION)

vs TEMPERATURE

0.4

0.2

14.0

13.5

13.0

12.5

12.0

11.5

11.0

10.5

10.0

9.5

f_IN= 4.956kHz, –0.2dB

–0.2

–0.4

–0.6

–0.8

9.0

100

7FFF_H

100

–50

–25

100

7FFF_H

100

Frequency (kHz)

Temperature (°C)

INTEGRAL LINEARITY ERROR vs CODE

DIFFERENTIAL LINEARITY ERROR vs CODE

–1

–2

–3

–1

–2

–3

8000_H

C000_H

0000_H

4000_H

8000_H

C000_H

0000_H

4000_H

Output Code

SUPPLY CURRENT vs TEMPERATURE

CHANGE IN BPZ vs TEMPERATURE

1.2

1.0

0.5

1.1

1.0

0.9

–0.5

–1.0

–50

–25

–50

–25

Temperature (°C)

ADS8343

SBAS183C

www.ti.com

TYPICAL CHARACTERISTICS: +2.7V (Cont.)

At T_A= +25°C, +V_CC= +2.7V, V_REF= +1.25V, f_SAMPLE= 100kHz, and f_CLK= 24 • f_SAMPLE= 2.4MHz, unless otherwise noted.

WORST-CASE CHANNEL-TO-CHANNEL

BPZ MATCH vs TEMPERATURE

CHANGE IN GAIN vs TEMPERATURE

0.5

1.5

1.0

0.5

–0.5

–1.0

–50

–25

100

–50

–25

100

Temperature (°C)

WORST-CASE CHANNEL-TO-CHANNEL

GAIN MATCH vs TEMPERATURE

COMMON-MODE REJECTION vs FREQUENCY

0.16

0.15

0.14

0.13

0.12

V_CM= 1Vp-p Sinewave

Centered Around V_REF

–50

–25

100

0.1

100

Temperature (°C)

Frequency (kHz)

POWER-DOWN SUPPLY CURRENT

vs TEMPERATURE

SUPPLY CURRENT vs +V_SS

140

120

100

1.4

1.3

1.2

1.1

1.0

External Clock Disabled

f_SAMPLE= 100kHz

–50

–25

100

2.5

3.0

3.5

4.0

4.5

5.0

Temperature (°C)

+V_SS(V)

ADS8343

SBAS183C

www.ti.com

TYPICAL CHARACTERISTICS: +2.7V (Cont.)

At T_A= +25°C, +V_CC= +2.7V, V_REF= +1.25V, f_SAMPLE= 100kHz, and f_CLK= 24 • f_SAMPLE= 2.4MHz, unless otherwise noted.

SUPPLY CURRENT vs SAMPLING FREQUENCY

1.4

f_CLK= 2.4MHz

1.2

1.0

V_SS= 5.0V

0.8

0.6

V_SS= 2.7V

0.4

0.2

Power-Down After Conversion Mode.

External Clock Gated HIGH After Conversion.

100

Sampling Frequency (kHz)

The analog input to the converter is differential and is

provided via a 4-channel multiplexer. The input can be

provided in reference to a voltage on the COM pin (which is

generally V_REF) or differentially by using two of the four input

channels (CH0-CH3). The particular configuration is select-

able via the digital interface.

THEORY OF OPERATION

The ADS8343 is a classic Successive Approximation Register

(SAR) A/D converter. The architecture is based on capacitive

redistribution which inherently includes a sample-and-hold func-

tion. The converter is fabricated on a 0.6µm CMOS process.

The basic operation of the ADS8343 is shown in Figure 1.

The device requires an external reference and an external

clock. It operates from a single supply of 2.7V to 5.25V. The

external reference can be any voltage between 500mV and

+V_CC/2. The value of the reference voltage directly sets the

input range of the converter. The average reference input

current depends on the conversion rate of the ADS8343.

ANALOG INPUT

The analog input is bipolar and fully differential. There are

two general methods of driving the analog input of the

ADS8343: single-ended or differential, as shown in Figure 2.

CHX

(1)

+2.7V to +5V

±V_REF

ADS8343

COM

1µF

10µF

Serial/Conversion

Clock

Common-Mode

Voltage

0.1µF

+V_CC

CH0

CH1

CH2

CH3

COM

SHDN

V_REF

DCLK 16

CS 15

(typically V_REF

)

Chip Select

Single-Ended Input

Serial Data In

Single-ended

or differential

analog inputs.

DIN 14

(1)

V_REF

BUSY 13

DOUT 12

GND 11

GND 10

CHX+

ADS8343

CHX–

Serial Data Out

(1)

Common-Mode

Voltage

V_REF

Differential Input

NOTE: (1) Relative to common-mode voltage.

V_REF

+V_CC

1µF

FIGURE 1. Basic Operation of the ADS8343.

FIGURE 2. Methods of Driving the ADS8343—Single-Ended

or Differential.

ADS8343

SBAS183C

www.ti.com

When the input is single-ended, the COM input is held at a

fixed voltage. The CHX input swings around the same

voltage and the peak-to-peak amplitude is 2 • V_REF. The

value of V_REFdetermines the range over which the common

voltage may vary, as shown in Figure 3.

In each case, care should be taken to ensure that the output

impedance of the sources driving the CHX and COM inputs

are matched. If this is not observed, the two inputs could

have different settling times. This may result in offset error,

gain error, and linearity error which change with both tem-

perature and input voltage. If the impedance cannot be

matched, the errors can be lessened by giving the ADS8343

additional acquisition time.

V_CC= 5V

4.9

The input current on the analog inputs depends on a number

of factors: sample rate, input voltage, and source impedance.

Essentially, the current into the ADS8343 charges the inter-

nal capacitor array during the sample period. After this

capacitance has been fully charged, there is no further input

current.

Single-Ended Input

2.8

2.1

Care must be taken regarding the absolute analog input

voltage. Outside of these ranges, the converter’s linearity

may not meet specifications. Please refer to the electrical

characteristics table for min/max ratings.

0.1

REFERENCE INPUT

The external reference sets the analog input range. The

ADS8343 will operate with a reference in the range of 500mV

to +V_CC/2. Keep in mind that the analog input is the differ-

ence between the CHX input and the COM input, as shown

in Figure 5. For example, in the single-ended mode, with

V_REFand COM pin set to 1.25V, the selected input channel

(CH0-CH3) will properly digitize a signal in the range of 0V to

2.50V relative to GND. If the COM pin is connected to 2.0V,

the input range on the selected channel is 0.75V to 3.25V.

–1

0.5

1.0

1.5

2.0

2.5

_REF(V)

FIGURE 3. Single-Ended Input—Common Voltage Range vs V_REF

When the input is differential, the amplitude of the input is the

difference between the CHX and COM input. A voltage or

signal is common to both of these inputs. The peak-to-peak

amplitude of each input is V_REFabout this common voltage.

However, since the inputs are 180° out-of-phase, the peak-

to-peak amplitude of the difference voltage is 2 • V_REF. The

value of V_REFalso determines the range of the voltage that

may be common to both inputs, as shown in Figure 4.

A2-A0

(Shown 001_B)

CH0

CH1

CH2

+IN

CH3

5.2

Converter

–IN

V_CC= 5V

4.2

COM

Differential Input

SGL/DIF

(Shown HIGH)

FIGURE 5. Simplified Diagram of the Analog Input.

0.8

There are several critical items concerning the reference

input and its wide voltage range. As the reference voltage is

reduced, the analog voltage weight of each digital output

code is also reduced. This is often referred to as the LSB

(Least Significant Bit) size and is equal to the reference

voltage divided by 65,536. Any offset or gain error inherent

in the A/D converter will appear to increase, in terms of LSB

0.2

0.0

1.0

1.5

2.0

2.5

_REF(V)

FIGURE 4. Differential Input—Common Voltage Range vs V_REF.

ADS8343

SBAS183C

www.ti.com

converter enters the conversion mode. At this point, the input

sample-and-hold goes into the hold mode. The next 16 clock

cycles accomplish the actual A/D conversion.

size, as the reference voltage is reduced. For example, if the

offset of a given converter is 2LSBs with a 2.5V reference,

then it will typically be 10LSBs with a 0.5V reference. In each

case, the actual offset of the device is the same, 76µV.

Control Byte

The noise or uncertainty of the digitized output will increase

with lower LSB size. With a reference voltage of 500mV, the

LSB size is 7.6µV. This level is below the internal noise of the

device. As a result, the digital output code will not be stable

and vary around a mean value by a number of LSBs. The

distribution of output codes will be gaussian and the noise

can be reduced by simply averaging consecutive conversion

results or applying a digital filter.

Also shown in Figure 6 is the placement and order of the

control bits within the control byte. Tables I and II give

detailed information about these bits. The first bit, the ‘S’ bit,

must always be HIGH and indicates the start of the control

byte. The ADS8343 will ignore inputs on the DIN pin until the

start bit is detected. The next three bits (A2-A0) select the

active input channel or channels of the input multiplexer, as

shown in Tables III and IV and Figure 5.

With a lower reference voltage, care should be taken to

provide a clean layout including adequate bypassing, a clean

(low-noise, low-ripple) power supply, a low-noise reference,

and a low-noise input signal. Because the LSB size is lower,

the converter will also be more sensitive to nearby digital

signals and electromagnetic interference.

Bit 7

(MSB)

Bit 0

(LSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

—

PD1

PD0

SGL/DIF

TABLE I. Order of the Control Bits in the Control Byte.

The voltage into the V_REFinput is not buffered and directly

drives the Capacitor Digital-to-Analog Converter (CDAC)

portion of the ADS8343. Typically, the input current is 13µA

with a 2.5V reference. This value will vary by microamps

depending on the result of the conversion. The reference

current diminishes directly with both conversion rate and

reference voltage. As the current from the reference is drawn

on each bit decision, clocking the converter more quickly

during a given conversion period will not reduce overall

current drain from the reference.

BIT

NAME

DESCRIPTION

Start Bit. Control byte starts with first HIGH bit on

DIN.

6-4

A2-A0

Channel Select Bits. Along with the

these bits control the setting of the multiplexer input.

bit,

SGL/DIF

Single-Ended/Differential Select Bit. Along with bits

A2-A0, this bit controls the setting of the multiplexer

input.

SGL/DIF

1-0

PD1-PD0 Power-Down Mode Select Bits. See Table V for

details.

TABLE II. Descriptions of the Control Bits within the Control Byte.

DIGITAL INTERFACE

Figure 6 shows the typical operation of the ADS8343’s digital

interface. This diagram assumes that the source of the digital

signals is a microcontroller or digital signal processor with a

basic serial interface (note that the digital inputs are over-

voltage tolerant up to 5.5V, regardless of +V_CC). Each com-

munication between the processor and the converter con-

sists of eight clock cycles. One complete conversion can be

accomplished with three serial communications, for a total of

24 clock cycles on the DCLK input.

CH0

CH1

CH2

CH3

COM

+IN

–IN

+IN

TABLE III. Single-Ended Channel Selection (SGL/DIF HIGH).

CH0

CH1

CH2

CH3

COM

+IN

–IN

The first eight cycles are used to provide the control byte via

the DIN pin. When the converter has enough information

about the following conversion to set the input multiplexer

appropriately, it enters the acquisition (sample) mode. After

three more clock cycles, the control byte is complete and the

–IN

+IN

–IN

+IN

TABLE IV. Differential Channel Control (SGL/DIF LOW).

t_ACQ

DCLK

DIN

Idle

Acquire

Conversion

Idle

Acquire

Conversion

SGL/

DIF

SGL/

DIF

A2 A1 A0

PD1 PD0

A2 A1 A0

PD1 PD0

(START)

BUSY

DOUT

14 13 12 11 10

Zero Filled...

15 14

(MSB)

(LSB)

FIGURE 6. Conversion Timing, 24-Clocks per Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated serial port.

ADS8343

SBAS183C

www.ti.com

The SGL/DIF bit controls the multiplexer input mode: either

single-ended (HIGH) or differential (LOW). In single-ended

mode, the selected input channel is referenced to the COM

pin. In differential mode, the two selected inputs provide a

differential input. See Tables III and IV and Figure 5 for more

information. The last two bits (PD1-PD0) select the power-

down mode as shown in Table V. If both inputs are HIGH, the

device is always powered up. If both inputs are LOW, the

device enters a power-down mode between conversions.

When a new conversion is initiated, the device will resume

normal operation instantly—no delay is needed to allow the

device to power up and the very first conversion will be valid.

ADS8343 can switch to the new mode. The extra cycle is

required because the PD0 and PD1 control bits need to be

written to the ADS8343 prior to the change in clock modes.

When power is first applied to the ADS8343, the user must

set the desired clock mode. It can be set by writing PD1 = 1

and PD0 = 0 for internal clock mode or PD1 = 1 and PD0

= 1 for external clock mode. After enabling the required clock

mode, only then should the ADS8343 be set to power-down

between conversions (i.e., PD1 = PD0 = 0). The ADS8343

maintains the clock mode it was in prior to entering the

power-down modes.

External Clock Mode

In external clock mode, the external clock not only shifts data

in and out of the ADS8343, it also controls the A/D conver-

sion steps. BUSY will go HIGH for one clock period after the

last bit of the control byte is shifted in. Successive-approxi-

mation bit decisions are made and appear at DOUT on each

of the next 16 DCLK falling edges, see Figure 6. Figure 7

shows the BUSY timing in external clock mode.

PD1

PD0

DESCRIPTION

Power-down between conversions. When each

conversion is finished, the converter enters a low-

power mode. At the start of the next conversion,

the device instantly powers up to full power. There

is no need for additional delays to assure full

operation and the very first conversion is valid.

Selects internal clock mode.

Reserved for future use.

Since one clock cycle of the serial clock is consumed with

BUSY going HIGH (while the MSB decision is being made),

16 additional clocks must be given to clock out all 16 bits of

data; thus, one conversion takes a minimum of 25 clock

cycles to fully read the data. Since most microprocessors

communicate in 8-bit transfers, this means that an additional

transfer must be made to capture the LSB.

No power-down between conversions, device al-

ways powered. Selects external clock mode.

TABLE V. Power-Down Selection.

Clock Modes

The ADS8343 can be used with an external serial clock or an

internal clock to perform the successive-approximation con-

version. In both clock modes, the external clock shifts data

in and out of the device. Internal clock mode is selected

when PD1 is HIGH and PD0 is LOW.

There are two ways of handling this requirement. One is

presented in Figure 6, where the beginning of the next

control byte appears at the same time the LSB is being

clocked out of the ADS8343. This method allows for maxi-

mum throughput and 24 clock cycles per conversion.

If the user decides to switch from one clock mode to the

other, an extra conversion cycle will be required before the

t_CL

t_CSH

t_CSS

t_CH

t_BD

t_D0

DCLK

DIN

t_DH

t_DS

PD0

t_BDV

t_BTR

BUSY

DOUT

t_DV

t_TR

FIGURE 7. Detailed Timing Diagram.

ADS8343

SBAS183C

www.ti.com

The other method is shown in Figure 8, which uses 32 clock

cycles per conversion; the last seven clock cycles simply

shift out zeros on the DOUT line. BUSY and DOUT go into

a high-impedance state when CS goes HIGH; after the next

CS falling edge, BUSY will go LOW.

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

t_ACQ

t_DS

Acquisition Time

DIN Valid Prior to DCLK Rising

DIN Hold After DCLK HIGH

DCLK Falling to DOUT Valid

CS Falling to DOUT Enabled

CS Rising to DOUT Disabled

CS Falling to First DCLK Rising

CS Rising to DCLK Ignored

DCLK HIGH

1.5

100

µs

t_DH

t_DO

t_DV

200

Internal Clock Mode

t_TR

In internal clock mode, the ADS8343 generates its own

conversion clock internally. This relieves the microprocessor

from having to generate the SAR conversion clock and

allows the conversion result to be read back at the processor’s

convenience, at any clock rate from 0MHz to 2.0MHz. BUSY

goes LOW at the start of conversion and then returns HIGH

when the conversion is complete. During the conversion,

BUSY will remain LOW for a maximum of 8µs. Also, during

the conversion, DCLK should remain LOW to achieve the

best noise performance. The conversion result is stored in an

internal register; the data may be clocked out of this register

any time after the conversion is complete.

t_CSS

t_CSH

t_CH

100

200

t_CL

DCLK LOW

t_BD

DCLK Falling to BUSY Rising

CS Falling to BUSY Enabled

CS Rising to BUSY Disabled

200

t_BDV

t_BTR

TABLE VI. Timing Specifications (+V_CC= +2.7V to 3.6V,

T_A= –40°C to +85°C, C_LOAD= 50pF).

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

t_ACQ

t_DS

Acquisition Time

DIN Valid Prior to DCLK Rising

DIN Hold After DCLK HIGH

DCLK Falling to DOUT Valid

CS Falling to DOUT Enabled

CS Rising to DOUT Disabled

CS Falling to First DCLK Rising

CS Rising to DCLK Ignored

DCLK HIGH

1.7

µs

If CS is LOW when BUSY goes LOW following a conversion,

the next falling edge of the external serial clock will write out

the MSB on the DOUT line. The remaining bits (D14-D0) will

be clocked out on each successive clock cycle following the

MSB. If CS is HIGH when BUSY goes LOW then the DOUT

line will remain in tri-state until CS goes LOW, as shown in

Figure 9. CS does not need to remain LOW once a conver-

sion has started. Note that BUSY is not tri-stated when CS

goes HIGH in internal clock mode.

t_DH

t_DO

t_DV

100

t_TR

t_CSS

t_CSH

t_CH

150

t_CL

DCLK LOW

t_BD

DCLK Falling to BUSY Rising

CS Falling to BUSY Enabled

CS Rising to BUSY Disabled

100

Data can be shifted in and out of the ADS8343 at clock rates

exceeding 2.4MHz, provided that the minimum acquisition time

t_BDV

t_BTR

_ACQ, is kept above 1.7µs.

TABLE VII. Timing Specifications (+V_CC= +4.75V to +5.25V,

Digital Timing

T_A= –40°C to +85°C, C_LOAD= 50pF).

Figure 4 and Tables VI and VII provide detailed timing for the

digital interface of the ADS8343.

t_ACQ

DCLK

DIN

Idle

Acquire

Conversion

Idle

SGL/

DIF

A2 A1 A0

PD1 PD0

(START)

BUSY

DOUT

Zero Filled...

14 13 12 11 10

(MSB)

(LSB)

FIGURE 8. External Clock Mode 32 Clocks Per Conversion.

t_ACQ

DCLK

DIN

Idle

Acquire

Conversion

SGL/

DIF

A2 A1 A0

PD1 PD0

(START)

BUSY

DOUT

(MSB)

14 13 12 11 10

Zero Filled...

(LSB)

FIGURE 9. Internal Clock Mode Timing.

ADS8343

SBAS183C

www.ti.com

If DCLK is active and CS is LOW while the ADS8343 is in

auto power-down mode, the device will continue to dissipate

some power in the digital logic. The power can be reduced

to a minimum by keeping CS HIGH. The differences in

supply current for these two cases are shown in Figure 11.

DATA FORMAT

The output data from the ADS8343 is in Binary Two’s

Complement format, as shown in Table VIII. This table

represents the ideal output code for the given input voltage

and does not include the effects of offset, gain, or noise.

Operating the ADS8343 in auto power-down mode will result

in the lowest power dissipation, and there is no conversion

time “penalty” on power-up. The very first conversion will be

valid. SHDN can be used to force an immediate power-down.

DESCRIPTION

ANALOG VALUE

2 • V_REF

DIGITAL OUTPUT

Full-Scale Range

BINARY TWO’S COMPLEMENT

Least Significant

Bit (LSB)

2 • V_REF/65536

BINARY CODE

HEX CODE

+Full-Scale

Midscale

+V_REF– 1LSB

0111 1111 1111 1111

0000 0000 0000 0000

1111 1111 1111 1111

1000 0000 0000 0000

7FFF

0000

FFFF

8000

1000

Midscale – 1LSB

–Full-Scale

0V – 1LSB

–V_REF

f_CLK= 24 • f_SAMPLE

100

TABLE VIII. Ideal Input Voltages and Output Codes.

POWER DISSIPATION

f_CLK= 2.4MHz

There are three power modes for the ADS8343: full-power

(PD1 = PD0 = 1_B), auto power-down (PD1 = PD0 = 0_B), and

shutdown (SHDN LOW). The affects of these modes varies

depending on how the ADS8343 is being operated. For

example, at full conversion rate and 24-clocks per conver-

sion, there is very little difference between full-power mode

and auto power-down, a shutdown (SHDN LOW) will not

lower power dissipation.

T_A= 25°C

+V_CC= +2.7V

V_REF= +2.5V

PD1 = PD0 = 0

10k

100k

_SAMPLE(Hz)

FIGURE 10. Supply Current versus Directly Scaling the Fre-

quency of DCLK with Sample Rate or Keeping

DCLK at the Maximum Possible Frequency.

When operating at full-speed and 24 clocks per conversion

(see Figure 6), the ADS8343 spends most of its time acquir-

ing or converting. There is little time for auto power-down,

assuming that this mode is active. Thus, the difference

between full-power mode and auto power-down is negligible.

If the conversion rate is decreased by simply slowing the

frequency of the DCLK input, the two modes remain approxi-

mately equal. However, if the DCLK frequency is kept at the

maximum rate during a conversion, but conversion are sim-

ply done less often, then the difference between the two

modes is dramatic. Figure 10 shows the difference between

reducing the DCLK frequency (“scaling” DCLK to match the

conversion rate) or maintaining DCLK at the highest fre-

quency and reducing the number of conversion per second.

In the later case, the converter spends an increasing per-

centage of its time in power-down mode (assuming the auto

power-down mode is active).

T_A= 25°C

+V_CC= +2.7V

_REF= +2.5V

_CLK= 24 • f_SAMPLE

PD1 = PD0 = 0

CS LOW

(GND)

CS HIGH (+V_CC

)

0.09

0.00

10k

100k

_SAMPLE(Hz)

FIGURE 11. Supply Current vs State of CS

ADS8343

SBAS183C

www.ti.com

AVERAGING

NOISE

The noise of the A/D converter can be compensated by

averaging the digital codes. By averaging conversion results,

transition noise will be reduced by a factor of 1/√n, where n

is the number of averages. For example, averaging 4 conver-

sion results will reduce the transition noise by 1/2 to

±0.25LSBs. Averaging should only be used for input signals

with frequencies near DC.

The noise floor of the ADS8343 itself is extremely low, as can

be seen from Figures 12 and 13, and is much lower than

competing A/D converters. The ADS8343 was tested at both

5V and 2.7V and in both the internal and external clock

modes. A low-level DC input was applied to the analog input

pins and the converter was put through 5000 conversions.

The digital output of the A/D converter will vary in output code

due to the internal noise of the ADS8343. This is true for all

16-bit, SAR-type, A/D converters. Using a histogram to plot

the output codes, the distribution should appear bell-shaped

with the peak of the bell curve representing the nominal code

for the input value. The ±1σ, ±2σ, and ±3σ distributions will

represent the 68.3%, 95.5%, and 99.7%, respectively, of all

codes. The transition noise can be calculated by dividing the

number of codes measured by 6 and this will yield the ±3σ

distribution or 99.7% of all codes. Statistically, up to 3 codes

could fall outside the distribution when executing 1000 con-

versions. The ADS8343, with < 3 output codes for the ±3σ

distribution, will yield a < ±0.5LSB transition noise at 5V

operation. Remember, to achieve this low noise perfor-

mance, the peak-to-peak noise of the input signal and

reference must be < 50µV.

For AC signals, a digital filter can be used to low-pass filter

and decimate the output codes. This works in a similar

manner to averaging; for every decimation by 2, the signal-

to-noise ratio will improve 3dB.

LAYOUT

For optimum performance, care should be taken with the

physical layout of the ADS8343 circuitry. This is particularly true

if the reference voltage is low and/or the conversion rate is high.

The basic SAR architecture is sensitive to glitches or sudden

changes on the power supply, reference, ground connections,

and digital inputs that occur just prior to latching the output of the

analog comparator. Thus, during any single conversion for an n-

bit SAR converter, there are n “windows” in which large external

transient voltages can easily affect the conversion result. Such

glitches might originate from switching power supplies, nearby

digital logic, and high-power devices. The degree of error in the

digital output depends on the reference voltage, layout, and the

exact timing of the external event. The error can change if the

external event changes in time with respect to the DCLK input.

3295

With this in mind, power to the ADS8343 should be clean and

well bypassed. A 0.1µF ceramic bypass capacitor should be

placed as close to the device as possible. In addition, a 1µF

to 10µF capacitor and a 5Ω or 10Ω series resistor may be

used to low-pass filter a noisy supply.

774

705

131

0002_H

The reference should be similarly bypassed with a 1µF

capacitor. Again, a series resistor and large capacitor can be

used to low-pass filter the reference voltage. If the reference

voltage originates from an op amp, make sure that it can

drive the bypass capacitor without oscillation (the series

resistor can help in this case). The ADS8343 draws very little

current from the reference on average, but it does place

larger demands on the reference circuitry over short periods

of time (on each rising edge of DCLK during a conversion).

FFFE_H

FFFF_H

0000_H

Code

0001_H

FIGURE 12. Histogram of 5000 Conversions of a DC Input at the

Code Transition, 5V Operation External Clock Mode.

2387

The ADS8343 architecture offers no inherent rejection of

noise or voltage variation in regards to the reference input.

This is of particular concern when the reference input is tied

to the power supply. Any noise and ripple from the supply will

appear directly in the digital results. While high-frequency

noise can be filtered out as discussed in the previous

paragraph, voltage variation due to line frequency (50Hz or

60Hz) can be difficult to remove.

905

694

512

411

The GND pin should be connected to a clean ground point. In

many cases, this will be the “analog” ground. Avoid connec-

tions which are too near the grounding point of a microcontroller

or digital signal processor. If needed, run a ground trace

directly from the converter to the power-supply entry point. The

ideal layout will include an analog ground plane dedicated to

the converter and associated analog circuitry.

FFFC_HFFFD_HFFFE_HFFFF_H0000_H0001_H0002_H0003_H0004_H

Code

FIGURE 13. Histogram of 5000 Conversions of a DC Input at the

Code Center, 2.7V Operation Internal Clock Mode.

ADS8343

SBAS183C

www.ti.com

PACKAGE OPTION ADDENDUM

www.ti.com

7-Oct-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

ADS8343E

ADS8343E/2K5

ADS8343EB

ACTIVE

SSOP

DBQ

RoHS & Green

Call TI

Level-2-260C-1 YEAR

-40 to 85

ADS

8343E

ACTIVE

DBQ

2500 RoHS & Green

Call TI

ADS

8343E

DBQ

RoHS & Green

ADS

8343E

ADS8343EBG4

ACTIVE

SSOP

DBQ

Call TI

Level-2-260C-1 YEAR

-40 to 85

ADS

8343E

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

7-Oct-2021

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADS8343E/2K5

SSOP

DBQ

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SSOP DBQ 16

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 35.0

ADS8343E/2K5

2500

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TUBE

*All dimensions are nominal

Device

Package Name Package Type

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

ADS8343E

ADS8343EB

ADS8343EBG4

DBQ

SSOP

506.6

3940

4.32

Pack Materials-Page 3

PACKAGE OUTLINE

DBQ0016A

SSOP - 1.75 mm max height

SCALE 2.800

SHRINK SMALL-OUTLINE PACKAGE

SEATING PLANE

.228-.244 TYP

[5.80-6.19]

.004 [0.1] C

PIN 1 ID AREA

14X .0250

[0.635]

.189-.197

[4.81-5.00]

NOTE 3

.175

[4.45]

16X .008-.012

[0.21-0.30]

.150-.157

[3.81-3.98]

NOTE 4

.069 MAX

[1.75]

.007 [0.17]

C A

.005-.010 TYP

[0.13-0.25]

SEE DETAIL A

.010

[0.25]

GAGE PLANE

.004-.010

[0.11-0.25]

0 - 8

.016-.035

[0.41-0.88]

DETAIL A

TYPICAL

(.041 )

[1.04]

4214846/A 03/2014

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 inch, per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MO-137, variation AB.

www.ti.com

EXAMPLE BOARD LAYOUT

DBQ0016A

SSOP - 1.75 mm max height

SHRINK SMALL-OUTLINE PACKAGE

16X (.063)

[1.6]

SEE

DETAILS

SYMM

16X (.016 )

[0.41]

14X (.0250 )

[0.635]

(.213)

[5.4]

LAND PATTERN EXAMPLE

SCALE:8X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

.002 MAX

[0.05]

ALL AROUND

.002 MIN

[0.05]

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4214846/A 03/2014

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DBQ0016A

SSOP - 1.75 mm max height

SHRINK SMALL-OUTLINE PACKAGE

16X (.063)

[1.6]

SYMM

16X (.016 )

[0.41]

SYMM

14X (.0250 )

[0.635]

(.213)

[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.127 MM] THICK STENCIL

SCALE:8X

4214846/A 03/2014

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

ADS8343 [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E