ADS8344NB [TI]

16-Bit, 8-Channel Serial Output Sampling; 16位8通道串行输出采样


型号：	ADS8344NB
厂家：	TEXAS INSTRUMENTS
描述：	16-Bit, 8-Channel Serial Output Sampling 16位8通道串行输出采样
文件：	总25页 (文件大小：1156K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS8344

SBAS139E – SEPTEMBER 2000 – REVISED SEPTEMBER 2006

16-Bit, 8-Channel Serial Output Sampling

ANALOG-TO-DIGITAL CONVERTER

DESCRIPTION

FEATURES

ꢀ PIN FOR PIN WITH ADS7844

ꢀ SINGLE SUPPLY: 2.7V to 5V

The ADS8344 is an 8-channel, 16-bit, sampling

Analog-to-Digital (A/D) converter with a synchronous serial

interface. Typical power dissipation is 10mW at a 100kHz

throughput rate and a +5V supply. The reference voltage

(V_REF) can be varied between 500mV and V_CC, providing a

corresponding input voltage range of 0V to V_REF. The

device includes a shutdown mode that reduces power dissi-

pation to under 15µW. The ADS8344 is tested down to 2.7V

operation.

ꢀ 8-CHANNEL SINGLE-ENDED OR

4-CHANNEL DIFFERENTIAL INPUT

ꢀ UP TO 100kHz CONVERSION RATE

ꢀ 84dB SINAD

ꢀ SERIAL INTERFACE

ꢀ QSOP-20 AND SSOP-20 PACKAGES

Low power, high speed, and an on-board multiplexer make

the ADS8344 ideal for battery-operated systems such as

personal digital assistants, portable multi-channel data log-

gers, and measurement equipment. The serial interface also

provides low-cost isolation for remote data acquisition. The

ADS8344 is available in a QSOP-20 or SSOP-20 package

and is ensured over the –40°C to +85°C temperature range.

APPLICATIONS

ꢀ DATA ACQUISITION

ꢀ TEST AND MEASUREMENT EQUIPMENT

ꢀ INDUSTRIAL PROCESS CONTROL

ꢀ PERSONAL DIGITAL ASSISTANTS

ꢀ BATTERY-POWERED SYSTEMS

ADS8341

ADS8343

ADS8344

ADS8345

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

V_REF

CH0

CH1

CH2

CH3

COM

SAR

DCLK

4-Channel

Multiplexer

8-Channel

Multiplexer

Comparator

SHDN

D_IN

Serial

Interface

and

CDAC

D_OUT

Control

BUSY

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

www.ti.com

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

+V_CCto GND ........................................................................ –0.3V to +6V

Analog Inputs to GND ............................................ –0.3V to +V_CC+ 0.3V

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instruments

recommends that all integrated circuits be handled with appropriate

precautions. Failure to observe proper handling and installation proce-

dures can cause damage.

Digital Inputs to GND ........................................................... –0.3V to +6V

Power Dissipation .......................................................................... 250mW

Maximum Junction Temperature ................................................... +150°C

Operating Temperature Range ........................................–40°C to +85°C

Storage Temperature Range .........................................–65°C to +150°C

Lead Temperature (soldering, 10s) ............................................... +300°C

ESD damage can range from subtle performance degradation to

complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could

cause the device not to meet its published specifications.

NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may

cause permanent damage to the device. Exposure to absolute maximum

conditions for extended periods may affect device reliability.

PACKAGE/ORDERING INFORMATION⁽¹⁾

MINIMUM

RELATIVE

MAXIMUM

SPECIFIED

PACKAGE

ACCURACY GAIN ERROR TEMPERATURE

PACKAGE

DESIGNATOR PACKAGE-LEAD

DRAWING

NUMBER

ORDERING

NUMBER

TRANSPORT

MEDIA, QUANTITY

PRODUCT

(LSB)

(%)

RANGE

ADS8344E

±0.05

–40°C to +85°C

DBQ

QSOP-20

DBQ

ADS8344E

ADS8344E/2K5

ADS8344N

ADS8344N/1K

ADS8344EB

ADS8344EB/2K5 Tape and Reel, 2500

ADS8344NB

ADS8344NB/1K

Rails, 56

Tape and Reel, 2500

Rails, 68

Tape and Reel, 1000

Rails, 56

DBQ

ADS8344N

SSOP-20

ADS8344EB

±0.024

–40°C to +85°C

QSOP-20

ADS8344NB

SSOP-20

Rails, 68

Tape and Reel, 1000

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI web site at

www.ti.com.

PIN CONFIGURATION

PIN DESCRIPTIONS

Top View

SSOP

NAME

DESCRIPTION

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

Analog Input Channel 0

Analog Input Channel 1

Analog Input Channel 2

Analog Input Channel 3

Analog Input Channel 4

Analog Input Channel 5

Analog Input Channel 6

Analog Input Channel 7

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

20 +V_CC

19 DCLK

18 CS

Ground reference for analog inputs. Sets zero code

voltageinsingle–endedmode.Connectthispintoground

or ground reference point.

SHDN

V_REF

Shutdown. When LOW, the device enters a very

low-power shutdown mode.

17 D_IN

16 BUSY

15 D_OUT

14 GND

13 GND

12 +V_CC

11 V_REF

Voltage Reference Input. See Electrical Characteristics

Table for ranges.

ADS8344

+V_CC

GND

D_OUT

Power Supply, 2.7V to 5V

Ground

Serial Data Output. Data is shifted on the falling edge of

DCLK. This output is high impedance when CS is HIGH.

Busy Output. Busy goes LOW when the D_INcontrol bits

are being read and also when the device is converting.

The Output is high impedance when CS is HIGH.

Serial Data Input. If CS is LOW, data is latched on rising

BUSY

SHDN 10

D_IN

edge of D_CLK

Chip Select Input. Active LOW. Data will not be clocked

into D_INunless CS is LOW. When CS is HIGH, D_OUTis

high impedance.

DCLK

+V_CC

External Clock Input. The clock speed determines the

conversion rate by the equation f_DCLK= 24 • f_SAMPLE

Power Supply

ADS8344

SBAS139E

ELECTRICAL CHARACTERISTICS: +5V

At T_A= –40°C to +85°C, +V_CC= +5V, V_REF= +5V, f_SAMPLE= 100kHz, and f_CLK= 24 • f_SAMPLE= 2.4MHz, unless otherwise noted.

ADS8344E, N

ADS8344EB, NB

PARAMETER

RESOLUTION

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

BITS

ꢀ

ANALOG INPUT

Full-Scale Input Span

Absolute Input Range

Positive Input - Negative Input

Positive Input

–0.2

V_REF

+V_CC+ 0.2

+1.25

ꢀ

Negative Input

Capacitance

Leakage Current

±1

ꢀ

µA

SYSTEM PERFORMANCE

No Missing Codes

Integral Linearity Error

Offset Error

Offset Error Match

Gain Error

Gain Error Match

Noise

Power-Supply Rejection

Bits

LSB

LSB⁽¹⁾

LSB

±2

±0.05

±1

ꢀ

±0.024

ꢀ

1.2

ꢀ

1.0

ꢀ

µVrms

LSB⁽¹⁾

+4.75V < V_CC< 5.25V

SAMPLING DYNAMICS

Conversion Time

Acquisition Time

ꢀ

CLK Cycles

kHz

4.5

ꢀ

Throughput Rate

100

Multiplexer Settling Time

Aperture Delay

Aperture Jitter

Internal Clock Frequency

External Clock Frequency

500

100

2.4

ꢀ

MHz

SHDN = V_DD

0.024

2.4

ꢀ

Data Transfer Only

DYNAMIC CHARACTERISTICS

Total Harmonic Distortion⁽²⁾

Signal-to-(Noise + Distortion)

Spurious–Free Dynamic Range

Channel-to-Channel Isolation

V_IN= 5Vp-p at 10kHz

–90

ꢀ

100

REFERENCE INPUT

Range

Resistance

0.5

+V_CC

100

ꢀ

DCLK Static

2.5

ꢀ

GΩ

µA

Input Current

f_SAMPLE= 12.5kHz

DCLK Static

0.001

DIGITAL INPUT/OUTPUT

Logic Family

Logic Levels

V_IH

V_IL

V_OH

CMOS

ꢀ

| I_IH| ≤ +5µA

| I_IL| ≤ +5µA

I_OH= –250µA

I_OL= 250µA

3.0

–0.3

3.5

5.5

+0.8

ꢀ

V_OL

0.4

ꢀ

Data Format

Straight Binary

ꢀ

POWER-SUPPLY REQUIREMENTS

+V_CC

Quiescent Current

Specified Performance

4.75

5.25

2.0

ꢀ

µA

1.5

300

f_SAMPLE= 100kHz

Power-Down Mode⁽³⁾, CS = +V_CC

ꢀ

µA

Power Dissipation

7.5

TEMPERATURE RANGE

Specified Performance

–40

+85

ꢀ

°C

ꢀ Same specifications as ADS8344E, N.

NOTES: (1) LSB means Least Significant Bit. With V_REFequal to +5.0V, one LSB is 76µV. (2) First nine harmonics of the test frequency. (3) Auto power-down mode

(PD1 = PD0 = 0) active or SHDN = GND.

ADS8344

SBAS139E

ELECTRICAL CHARACTERISTICS: +2.7V

At T_A= –40°C to +85°C, +V_CC= +2.7V, V_REF= +2.7V, f_SAMPLE= 100kHz, and f_CLK= 24 • f_SAMPLE= 2.4MHz, unless otherwise noted.

ADS8344E, N

ADS8344EB, NB

TYP

PARAMETER

RESOLUTION

CONDITIONS

MIN

TYP

MAX

MIN

MAX

UNITS

BITS

ꢀ

ANALOG INPUT

Full-Scale Input Span

Absolute Input Range

Positive Input - Negative Input

Positive Input

–0.2

V_REF

+V_CC+ 0.2

+0.2

ꢀ

Negative Input

Capacitance

Leakage Current

±1

ꢀ

µA

SYSTEM PERFORMANCE

No Missing Codes

Integral Linearity Error

Offset Error

Offset Error Match

Gain Error

Gain Error Match

Noise

Power-Supply Rejection

Bits

LSB

% of FSR

LSB

±1

±0.05

0.5

ꢀ

±0.024

ꢀ

1.2

ꢀ

µVrms

LSB⁽¹⁾

+2.7 < V_CC< +3.3V

SAMPLING DYNAMICS

Conversion Time

Acquisition Time

ꢀ

CLK Cycles

kHz

4.5

ꢀ

Throughput Rate

100

Multiplexer Settling Time

Aperture Delay

Aperture Jitter

Internal Clock Frequency

External Clock Frequency

500

100

2.4

ꢀ

MHz

SHDN = V_DD

0.024

2.4

2.0

2.4

When used with Internal Clock

Data Transfer Only

ꢀ

DYNAMIC CHARACTERISTICS

Total Harmonic Distortion⁽²⁾

Signal-to-(Noise + Distortion)

Spurious-Free Dynamic Range

Channel-to-Channel Isolation

V_IN= 2.5Vp-p at 1kHz

–90

ꢀ

_IN= 2.5Vp-p at 1kHz

_IN= 2.5Vp-p at 10kHz

100

REFERENCE INPUT

Range

Resistance

0.5

+V_CC

ꢀ

DCLK Static

2.5

ꢀ

GΩ

µA

Input Current

f_SAMPLE= 12.5kHz

DCLK Static

0.001

DIGITAL INPUT/OUTPUT

Logic Family

Logic Levels

V_IH

V_IL

V_OH

CMOS

ꢀ

| I_IH| ≤ +5µA

| I_IL| ≤ +5µA

I_OH= –250µA

I_OL= 250µA

+V_CC• 0.7

–0.3

+V_CC• 0.8

5.5

+0.8

ꢀ

V_OL

0.4

ꢀ

Data Format

Straight Binary

ꢀ

POWER-SUPPLY REQUIREMENTS

+V_CC

Quiescent Current

Specified Performance

2.7

3.6

1.85

ꢀ

µA

1.2

220

ꢀ

f_SAMPLE= 100kHz

Power-Down Mode⁽³⁾, CS = +V_CC

ꢀ

Power Dissipation

3.2

TEMPERATURE RANGE

Specified Performance

–40

+85

ꢀ

°C

ꢀ Same specifications as ADS8344E, N.

NOTES: (1) LSB means Least Significant Bit. With V_REFequal to +2.5V, one LSB is 38µV. (2) First nine harmonics of the test frequency. (3) Auto power-down mode

(PD1 = PD0 = 0) active or SHDN = GND.

ADS8344

SBAS139E

TYPICAL CHARACTERISTICS: +5V

At T_A= +25°C, +V_CC= +5V, V_REF= +5V, f_SAMPLE= 100kHz, and f_DCLK= 24 • f_SAMPLE= 2.4MHz, unless otherwise noted.

FREQUENCY SPECTRUM

(4096 Point FFT; f_IN= 1.001kHz, –0.2dB)

FREQUENCY SPECTRUM

(4096 Point FFT; f_IN= 9.985kHz, –0.2dB)

–20

–40

–60

–80

–100

–120

–140

–160

–100

–120

–140

–160

100

Frequency (kHz)

SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-

(NOISE+DISTORTION) vs INPUT FREQUENCY

SPURIOUS-FREE DYNAMIC RANGE AND TOTAL

HARMONIC DISTORTION vs INPUT FREQUENCY

100

–100

–90

–80

–70

–60

100

SNR

SFDR

THD⁽¹⁾

SINAD

NOTE: (1) First Nine Harmonics

of the Input Frequency

100

Frequency (kHz)

EFFECTIVE NUMBER OF BITS

vs INPUT FREQUENCY

CHANGE IN SIGNAL-TO-(NOISE+DISTORTION)

vs TEMPERATURE

15.0

14.5

14.0

13.5

13.0

12.5

12.0

11.5

11.0

0.4

0.2

f_IN= 9.985kHz, –0.2dB

0.0

–0.2

–0.4

–0.6

–0.8

–40

–25

100

Temperature (°C)

Frequency (kHz)

ADS8344

SBAS139E

TYPICAL CHARACTERISTICS: +5V (Cont.)

At T_A= +25°C, +V_CC= +5V, V_REF= +5V, f_SAMPLE= 100kHz, and f_DCLK= 24 • f_SAMPLE= 2.4MHz, unless otherwise noted.

INTEGRAL LINEARITY ERROR vs CODE

DIFFERENTIAL LINEARITY ERROR vs CODE

–1

–2

–3

–4

–1

–2

–3

0000_H

4000_H

8000_H

C000_H

FFFF_H

0000_H

4000_H

8000_H

C000_H

FFFF_H

Output Code

WORST CASE CHANNEL-TO-CHANNEL

OFFSET MATCH vs TEMPERATURE

WORST CASE CHANNEL-TO-CHANNEL

GAIN MATCH vs TEMPERATURE

3.0

2.5

2.0

1.5

1.0

2.0

1.5

1.0

0.5

0.0

–50

–25

100

–50

–25

100

Temperature (°C)

CHANGE IN OFFSET vs TEMPERATURE

CHANGE IN GAIN vs TEMPERATURE

1.0

0.5

–1

–2

–3

0.0

–0.5

–50

–25

100

–50

–25

100

Temperature (°C)

ADS8344

SBAS139E

TYPICAL CHARACTERISTICS: +5V (Cont.)

At T_A= +25°C, +V_CC= +5V, V_REF= +5V, f_SAMPLE= 100kHz, and f_DCLK= 24 • f_SAMPLE= 2.4MHz, unless otherwise noted.

POWER DOWN SUPPLY CURRENT

vs TEMPERATURE

SUPPLY CURRENT vs TEMPERATURE

3.0

2.5

2.0

1.5

1.0

1.8

1.7

1.6

1.5

1.4

1.3

–50

–25

100

–50

–25

100

Temperature (°C)

ADS8344

SBAS139E

TYPICAL CHARACTERISTICS: +2.7V

At T_A= +25°C, +V_CC= +2.7V, V_REF= +2.7V, f_SAMPLE= 100kHz, and f_DCLK= 24 • f_SAMPLE= 2.4MHz, unless otherwise noted.

FREQUENCY SPECTRUM

(4096 Point FFT; f_IN= 9.985kHz, –0.2dB)

FREQUENCY SPECTRUM

(4096 Point FFT; f_IN= 1.001kHz, –0.2dB)

–20

–40

–60

–80

–100

–120

–140

–160

–100

–120

–140

–160

Frequency (kHz)

SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-

(NOISE+DISTORTION) vs INPUT FREQUENCY

SPURIOUS-FREE DYNAMIC RANGE AND TOTAL

HARMONIC DISTORTION vs INPUT FREQUENCY

100

–100

–90

–80

–70

–60

–50

SNR

SFDR

THD⁽¹⁾

SINAD

NOTE: (1) First Nine Harmonics

of the Input Frequency

100

Frequency (kHz)

EFFECTIVE NUMBER OF BITS

vs INPUT FREQUENCY

CHANGE IN SIGNAL-TO-(NOISE+DISTORTION)

vs TEMPERATURE

2.0

1.5

f_IN= 9.985kHz, –0.2dB

1.0

0.5

0.0

–0.5

–1.0

–1.5

–2.0

–40

–25

100

Temperature (°C)

Frequency (kHz)

ADS8344

SBAS139E

TYPICAL CHARACTERISTICS: +2.7V (Cont.)

At T_A= +25°C, +V_CC= +2.7V, V_REF= +2.7V, f_SAMPLE= 100kHz, and f_DCLK= 24 • f_SAMPLE= 2.4MHz, unless otherwise noted.

INTEGRAL LINEARITY ERROR vs CODE

DIFFERENTIAL LINEARITY ERROR vs CODE

–1

–2

–3

–1

–2

–3

0000_H

4000_H

8000_H

C000_H

FFFF_H

0000_H

4000_H

8000_H

C000_H

FFFF_H

Output Code

WORST CASE CHANNEL-TO-CHANNEL

OFFSET MATCH vs TEMPERATURE

WORST CASE CHANNEL-TO-CHANNEL

GAIN MATCH vs TEMPERATURE

1.2

1.0

0.8

0.6

0.4

0.2

1.2

1.0

0.8

0.6

0.4

–50

–25

100

–50

–25

100

Temperature (°C)

CHANGE IN GAIN vs TEMPERATURE

CHANGE IN OFFSET vs TEMPERATURE

0.3

0.2

0.1

0.0

–0.1

–1

–0.2

–50

–25

100

–50

–25

100

Temperature (°C)

ADS8344

SBAS139E

TYPICAL CHARACTERISTICS: +2.7V (Cont.)

At T_A= +25°C, +V_CC= +2.7V, V_REF= +2.7V, f_SAMPLE= 100kHz, and f_DCLK= 24 • f_SAMPLE= 2.4MHz, unless otherwise noted.

SUPPLY CURRENT vs TEMPERATURE

SUPPLY CURRENT vs +V_SS

f_SAMPLE= 100kHz, V_REF= +V_SS

1.25

1.20

1.15

1.10

1.05

1.00

1.6

1.5

1.4

1.3

1.2

1.1

1.0

–50

–25

100

2.5

3.0

3.5

4.0

4.5

5.0

Temperature (°C)

+V_SS(V)

POWER DOWN SUPPLY CURRENT

vs TEMPERATURE

3.0

2.5

2.0

1.5

1.0

–50

–25

100

Temperature (°C)

ADS8344

SBAS139E

ANALOG INPUT

THEORY OF OPERATION

See Figure 2 for a block diagram of the input multiplexer on

the ADS8344. The differential input of the converter is

derived from one of the eight inputs in reference to the COM

pin, or four of the eight inputs. Table I and Table II show the

relationship between the A2, A1, A0, and SGL/DIF control

bits and the configuration of the analog multiplexer. The

control bits are provided serially via the D_INpin (see the

Digital Interface section of this data sheet for more details).

The ADS8344 is a classic Successive Approximation

capacitive redistribution that inherently includes a sample-

and-hold function. The converter is fabricated on a 0.6µs

CMOS process.

The basic operation of the ADS8344 is shown in Figure 1.

The device requires an external reference and an external

clock. It operates from a single supply of 2.7V to 5.25V. The

external reference can be any voltage between 500mV and

+V_CC. The value of the reference voltage directly sets the

input range of the converter. The average reference input

current depends on the conversion rate of the ADS8344.

When the converter enters the hold mode, the voltage

difference between the +IN and –IN inputs is captured on

the internal capacitor array (see Figure 2). The voltage on

the –IN input is limited between –0.2V and 1.25V, allowing

the input to reject small signals that are common to both the

+IN and –IN input. The +IN input has a range of –0.2V to

+V_CC+ 0.2V.

The analog input to the converter is differential and is

provided via an 8-channel multiplexer. The input can be

provided in reference to a voltage on the COM pin (which

is generally ground) or differentially by using four of the

eight input channels (CH0 - CH7). The particular configura-

tion is selectable via the digital interface.

The input current on the analog inputs depends on the conver-

sion rate of the device. During the sample period, the source

must charge the internal sampling capacitor (typically 25pF).

After the capacitor has been fully charged, there is no further

input current. The rate of charge transfer from the analog

source to the converter is a function of conversion rate.

A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM

+IN

–IN

CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

+IN

–IN

+IN

–IN

+IN

–IN

+IN

–IN

+IN

–IN

+IN

–IN

+IN

–IN

+IN

TABLE II. Differential Channel Control (SGL/DIF LOW).

TABLE I. Single-Ended Channel Selection (SGL/DIF HIGH).

+2.7V to +5V

ADS8344

+V_CC20

1µF to 10µF

0.1µF

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

Serial/Conversion Clock

Chip Select

DCLK 19

CS 18

Single-ended

or differential

analog inputs

Serial Data In

D_IN17

BUSY 16

D_OUT15

GND 14

GND 13

+V_CC12

V_REF11

Serial Data Out

External

V_REF

10 SHDN

1µF

1µF to 10µF

FIGURE 1. Basic Operation of the ADS8344.

ADS8344

SBAS139E

(Least Significant Bit) size and is equal to the reference

voltage divided by 65536. Any offset or gain error inherent

in the A/D converter will appear to increase, in terms of LSB

size, as the reference voltage is reduced. For example, if the

offset of a given converter is 2LSBs with a 2.5V reference,

then it will typically be 10LSBs with a 0.5V reference. In

each case, the actual offset of the device is the same,

76.3µV.

A2-A0

(shown 00o_B)⁽¹⁾

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

Likewise, the noise or uncertainty of the digitized output

will increase with lower LSB size. With a reference voltage

of 500mV, the LSB size is 7.6µV. This level is below the

internal noise of the device. As a result, the digital output

code will not be stable and will vary around a mean value by

a number of LSBs. The distribution of output codes will be

gaussian and the noise can be reduced by simply averaging

consecutive conversion results or applying a digital filter.

+IN

Converter

–IN

With a lower reference voltage, care should be taken to

provide a clean layout including adequate bypassing, a clean

(low-noise, low-ripple) power supply, a low-noise reference,

and a low-noise input signal. Because the LSB size is lower,

the converter will also be more sensitive to nearby digital

signals and electromagnetic interference.

COM

The voltage into the V_REFinput is not buffered and directly

drives the Capacitor Digital-to-Analog Converter (CDAC)

portion of the ADS8344. Typically, the input current is

13µA with a 2.5V reference. This value will vary by

microamps depending on the result of the conversion. The

reference current diminishes directly with both conversion

rate and reference voltage. As the current from the reference

is drawn on each bit decision, clocking the converter more

quickly during a given conversion period will not reduce

overall current drain from the reference.

SGL/DIF

(shown HIGH)

NOTE: (1) See Truth Tables, Table I

and Table II for address coding.

FIGURE 2. Simplified Diagram of the Analog Input.

REFERENCE INPUT

The external reference sets the analog input range. The

ADS8344 will operate with a reference in the range of

100mV to +V_CC. Keep in mind that the analog input is the

difference between the +IN input and the –IN input, as

shown in Figure 2. For example, in the single-ended mode,

a 1.25V reference with the COM pin grounded, the selected

input channel (CH0 - CH7) will properly digitize a signal in

the range of 0V to 1.25V. If the COM pin is connected to

0.5V, the input range on the selected channel is 0.5V to

1.75V.

DIGITAL INTERFACE

The ADS8344 has a four-wire serial interface compatible

with several microprocessor families (note that the digital

inputs are over-voltage tolerant up to +5.5V, regardless of

+V_CC). Figure 3 shows the typical operation of the ADS8344

digital interface.

Most microprocessors communicate using 8-bit transfers;

the ADS8344 can complete a conversion with three such

transfers, for a total of 24 clock cycles on the DCLK input,

provided the timing is as shown in Figure 3.

There are several critical items concerning the reference

input and its wide-voltage range. As the reference voltage is

reduced, the analog voltage weight of each digital output

code is also reduced. This is often referred to as the LSB

t_ACQ

DCLK

D_IN

Idle

Acquire

Conversion

Idle

Acquire

Conversion

SGL/

DIF

SGL/

DIF

A2 A1 A0

PD1 PD0

A2 A1 A0

PD1 PD0

(START)

BUSY

D_OUT

14 13 12 11 10

Zero Filled...

15 14

(MSB)

(LSB)

FIGURE 3. Conversion Timing, 24-Clocks per Conversion, 8-Bit Bus Interface. No DCLK Delay Required with Dedicated

Serial Port.

ADS8344

SBAS139E

The first eight clock cycles are used to provide the control

byte via the D_INpin. When the converter has enough

information about the following conversion to set the input

multiplexer appropriately, it enters the acquisition (sample)

mode. After four more clock cycles, the control byte is

complete and the converter enters the conversion mode. At

this point, the input sample-and-hold goes into the Hold

mode. The next sixteen clock cycles accomplish the actual

A/D conversion.

HIGH, the device is always powered up. If both PD1 and

PD0 are LOW, the device enters a power-down mode

between conversions. When a new conversion is initiated,

the device will resume normal operation instantly—no delay

is needed to allow the device to power up and the very first

conversion will be valid.

PD1

PD0

DESCRIPTION

Power-down between conversions. When each

conversion is finished, the converter enters a

low-power mode. At the start of the next conver-

sion, the device instantly powers up to full power.

There is no need for additional delays to assure full

operation and the very first conversion is valid.

Control Byte

See Figure 3 for placement and order of the control bits

within the control byte. Tables III and IV give detailed

information about these bits. The first bit, the “S” bit, must

always be HIGH and indicates the start of the control byte.

The ADS8344 will ignore inputs on the D_INpin until the

START bit is detected. The next three bits (A2-A0) select

the active input channel or channels of the input multiplexer

(see Tables I and II and Figure 2).

Selects Internal Clock Mode.

Reserved for Future Use.

No power-down between conversions, device al-

ways powered. Selects external clock mode.

TABLE V. Power-Down Selection.

Clock Modes

BIT 7

(MSB)

BIT 0

(LSB)

The ADS8344 can be used with an external serial clock or an

internal clock to perform the successive-approximation con-

version. In both clock modes, the external clock shifts data in

and out of the device. Internal clock mode is selected when

PD1 is HIGH and PD0 is LOW.

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

—

SGL/DIF PD1

PD0

TABLE III. Order of the Control Bits in the Control Byte.

If the user decides to switch from one clock mode to the other,

an extra conversion cycle will be required before the

ADS8344 can switch to the new mode. The extra cycle is

required because the PD0 and PD1 control bits need to be

written to the ADS8344 prior to the change in clock modes.

BIT

NAME

DESCRIPTION

Start Bit. Control byte starts with first HIGH bit on

D_IN

6 - 4

A2 - A0

Channel Select Bits. Along with the SGL/DIF bit,

these bits control the setting of the multiplexer input,

see Tables I and II.

When power is first applied to the ADS8344, the user must

set the desired clock mode. It can be set by writing PD1

= 1 and PD0 = 0 for internal clock mode or PD1 = 1 and PD0

= 1 for external clock mode. After enabling the required

clock mode, only then should the ADS8344 be set to power-

down between conversions (i.e., PD1 = PD0 = 0). The

ADS8344 maintains the clock mode it was in prior to

entering the power-down modes.

SGL/DIF

Single-Ended/Differential Select Bit. Along with bits

A2 - A0, this bit controls the setting of the multiplexer

input, see Tables I and II.

1 - 0 PD1 - PD0 Power-Down Mode Select Bits. See Table V for

details.

TABLE IV. Descriptions of the Control Bits within the

Control Byte.

External Clock Mode

In external clock mode, the external clock not only shifts data

in and out of the ADS8344, it also controls the A/D conversion

steps. BUSY will go HIGH for one clock period after the last

bit of the control byte is shifted in. Successive-approximation

bit decisions are made and appear at D_OUTon each of the next

16 DCLK falling edges (see Figure 3). Figure 4 shows the

BUSY timing in external clock mode.

The SGL/DIF-bit controls the multiplexer input mode: ei-

ther in single-ended mode, where the selected input channel

is referenced to the COM pin, or in differential mode, where

the two selected inputs provide a differential input.

See Tables I and II and Figure 2 for more information. The

last two bits (PD1 - PD0) select the power-down mode and

Clock mode, as shown in Table V. If both PD1 and PD0 are

t_CL

t_CSH

t_CSS

t_CH

t_BD

t_D0

DCLK

D_IN

t_DH

t_DS

PD0

t_BDV

t_BTR

BUSY

D_OUT

t_DV

t_TR

FIGURE 4. Detailed Timing Diagram.

ADS8344

SBAS139E

Since one clock cycle of the serial clock is consumed with

BUSY going HIGH (while the MSB decision is being

made), 16 additional clocks must be given to clock out all 16

bits of data; thus, one conversion takes a minimum of 25

clock cycles to fully read the data. Since most microproces-

sors communicate in 8-bit transfers, this means that an

additional transfer must be made to capture the LSB.

If CS is LOW when BUSY goes LOW following a conver-

sion, the next falling edge of the external serial clock will

write out the MSB on the D_OUTline. The remaining bits

(D14-D0) will be clocked out on each successive clock cycle

following the MSB. If CS is HIGH when BUSY goes LOW

then the D_OUTline will remain in tri-state until CS goes

LOW, as shown in Figure 6. CS does not need to remain

LOW once a conversion has started. Note that BUSY is not

tri-stated when CS goes HIGH in internal clock mode.

There are two ways of handling this requirement. One is

where the beginning of the next control byte appears at the

same time the LSB is being clocked out of the ADS8344

(see Figure 3). This method allows for maximum throughput

and 24 clock cycles per conversion.

Data can be shifted in and out of the ADS8344 at clock rates

exceeding 2.4MHz, provided that the minimum acquisition

time t_ACQ, is kept above 1.7µs.

The other method is shown in Figure 5, which uses 32 clock

cycles per conversion; the last seven clock cycles simply

shift out zeros on the D_OUTline. BUSY and D_OUTgo into a

high-impedance state when CS goes HIGH; after the next

CS falling edge, BUSY will go LOW.

Digital Timing

Figure 4 and Tables VI and VII provide detailed timing for

the digital interface of the ADS8344.

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

Internal Clock Mode

t_ACQ

t_DS

Acquisition Time

D_INValid Prior to DCLK Rising

D_INHold After DCLK HIGH

DCLK Falling to D_OUTValid

CS Falling to D_OUTEnabled

CS Rising to D_OUTDisabled

CS Falling to First DCLK Rising

CS Rising to DCLK Ignored

DCLK HIGH

1.5

100

µs

In internal clock mode, the ADS8344 generates its own

conversion clock internally. This relieves the microproces-

sor from having to generate the SAR conversion clock and

allows the conversion result to be read back at the processor’s

convenience, at any clock rate from 0MHz to 2.0MHz.

BUSY goes LOW at the start of a conversion and then

returns HIGH when the conversion is complete. During the

conversion, BUSY will remain LOW for a maximum of 8µs.

Also, during the conversion, DCLK should remain LOW to

achieve the best noise performance. The conversion result is

stored in an internal register; the data may be clocked out of

this register any time after the conversion is complete.

t_DH

t_DO

t_DV

200

t_TR

t_CSS

t_CSH

t_CH

100

200

t_CL

DCLK LOW

t_BD

DCLK Falling to BUSY Rising

CS Falling to BUSY Enabled

CS Rising to BUSY Disabled

200

t_BDV

t_BTR

TABLE VI. Timing Specifications (+V_CC= +2.7V to 3.6V,

T_A= –40°C to +85°C, C_LOAD= 50pF).

t_ACQ

DCLK

Idle

Acquire

Conversion

Idle

SGL/

DIF

D_IN

A2 A1 A0

PD1 PD0

(START)

BUSY

D_OUT

Zero Filled...

14 13 12 11 10

(MSB)

(LSB)

FIGURE 5. External Clock Mode, 32 Clocks Per Conversion.

t_ACQ

DCLK

Idle

Acquire

Conversion

SGL/

DIF

D_IN

A2 A1 A0

PD1 PD0

(START)

BUSY

D_OUT

(MSB)

14 13 12 11 10

Zero Filled...

(LSB)

FIGURE 6. Internal Clock Mode Timing.

ADS8344

SBAS139E

remain approximately equal. However, if the DCLK fre-

quency is kept at the maximum rate during a conversion, but

conversions are simply done less often, then the difference

between the two modes is dramatic. In the latter case, the

converter spends an increasing percentage of its time in

power-down mode (assuming the auto power-down mode is

active).

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

t_ACQ

t_DS

Acquisition Time

D_INValid Prior to DCLK Rising

D_INHold After DCLK HIGH

DCLK Falling to D_OUTValid

CS Falling to D_OUTEnabled

CS Rising to D_OUTDisabled

CS Falling to First DCLK Rising

CS Rising to DCLK Ignored

DCLK HIGH

1.7

µs

t_DH

t_DO

t_DV

100

t_TR

t_CSS

t_CSH

t_CH

If DCLK is active and CS is LOW while the ADS8344 is in

auto power-down mode, the device will continue to dissipate

some power in the digital logic. The power can be reduced

to a minimum by keeping CS HIGH.

150

t_CL

DCLK LOW

t_BD

DCLK Falling to BUSY Rising

CS Falling to BUSY Enabled

CS Rising to BUSY Disabled

100

t_BDV

t_BTR

Operating the ADS8344 in auto power-down mode will

result in the lowest power dissipation, and there is no

conversion time “penalty” on power-up. The very first

conversion will be valid. SHDN can be used to force an

immediate power-down.

TABLE VII. Timing Specifications (+V_CC= +4.75V to

+5.25V, T_A= –40°C to +85°C, C_LOAD= 50pF).

Data Format

The ADS8344 output data is in straight binary format, as

shown in Figure 7. This figure shows the ideal output code

for the given input voltage and does not include the effects

of offset, gain, or noise.

NOISE

The noise floor of the ADS8344 itself is extremely low, as

shown in Figures 8 thru 11, and is much lower than compet-

ing A/D converters. The ADS8344 was tested at both 5V

and 2.7V, and in both the internal and external clock modes.

A low-level DC input was applied to the analog-input pins

and the converter was put through 5,000 conversions. The

digital output of the A/D converter will vary in output code

due to the internal noise of the ADS8344. This is true for all

16-bit SAR-type A/D converters. Using a histogram to plot

the output codes, the distribution should appear bell-shaped

with the peak of the bell curve representing the nominal code

for the input value. The ±1σ, ±2σ, and ±3σ distributions will

represent the 68.3%, 95.5%, and 99.7%, respectively, of all

codes. The transition noise can be calculated by dividing the

number of codes measured by 6 and this will yield the ±3σ

distribution, or 99.7%, of all codes. Statistically, up to 3

codes could fall outside the distribution when executing

1,000 conversions. The ADS8344, with < 3 output codes for

the ±3σ distribution, will yield a < ±0.5LSB transition noise

at 5V operation. Remember, to achieve this low-noise per-

formance, the peak-to-peak noise of the input signal and

reference must be < 50µV.

FS = Full-Scale Voltage = V_REF

1LSB = V_REF/65,536

1LSB

11...111

11...110

11...101

00...010

00...001

00...000

FS – 1LSB

Input Voltage⁽¹⁾(V)

NOTE: (1) Voltage at converter input, after multiplexer: +IN – (–IN). (See Figure 2.)

FIGURE 7. Ideal Input Voltages and Output Codes.

POWER DISSIPATION

There are three power modes for the ADS8344: full-power

(PD1 - PD0 = 11B), auto power-down (PD1 - PD0 = 00B),

and shutdown (SHDN LOW). The effects of these modes

varies depending on how the ADS8344 is being operated.

For example, at full conversion rate and 24-clocks per

conversion, there is very little difference between

full-power mode and auto power-down; a shutdown will not

lower power dissipation.

4561

When operating at full-speed and 24-clocks per conversion

(see Figure 3), the ADS8344 spends most of its time

acquiring or converting. There is little time for auto

power-down, assuming that this mode is active. Thus, the

difference between full-power mode and auto power-down

is negligible. If the conversion rate is decreased by simply

slowing the frequency of the DCLK input, the two modes

242

197

7FFD

7FFE

7FFF

Code

8000

8001

FIGURE 8. Histogram of 5,000 Conversions of a DC Input at the

Code Transition, 5V operation external clock mode.

ADS8344

SBAS139E

sion results will reduce the transition noise by 1/2 to

±0.25LSBs. Averaging should only be used for input signals

with frequencies near DC.

4507

For AC signals, a digital filter can be used to low-pass filter

and decimate the output codes. This works in a similar

manner to averaging: for every decimation by 2, the

signal-to-noise ratio will improve 3dB.

LAYOUT

251

242

For optimum performance, care should be taken with the

physical layout of the ADS8344 circuitry. This is particu-

larly true if the reference voltage is LOW and/or the conver-

sion rate is HIGH.

7FFD

7FFE

7FFF

Code

8000

8001

FIGURE 9. Histogram of 5,000 Conversions of a DC Input at the

Code Center, 5V operation internal clock mode.

The basic SAR architecture is sensitive to glitches or sudden

changes on the power supply, reference, ground connec-

tions, and digital inputs that occur just prior to latching the

output of the analog comparator. Thus, during any single

conversion for an n-bit SAR converter, there are n “win-

dows” in which large external transient voltages can easily

affect the conversion result. Such glitches might originate

from switching power supplies, nearby digital logic, and

high-power devices. The degree of error in the digital output

depends on the reference voltage, layout, and the exact

timing of the external event. The error can change if the

external event changes in time with respect to the DCLK

input.

3511

666

721

With this in mind, power to the ADS8344 should be clean

and well bypassed. A 0.1µF ceramic bypass capacitor should

be placed as close to the device as possible. In addition, a

1µF to 10µF capacitor and a 5Ω or 10Ω series resistor may

be used to low-pass filter a noisy supply.

7FFD

7FFE

7FFF

Code

8000

8001

FIGURE 10. Histogram of 5,000 Conversions of a DC Input at the

Code Transition, 2.7V operation external clock mode.

The reference should be similarly bypassed with a 0.1µF

capacitor. Again, a series resistor and large capacitor can be

used to low-pass filter the reference voltage. If the reference

voltage originates from an op amp, make sure that it can

drive the bypass capacitor without oscillation (the series

resistor can help in this case). The ADS8344 draws very

little current from the reference on average, but it does place

larger demands on the reference circuitry over short periods

of time (on each rising edge of DCLK during a conversion).

2868

1137

858

The ADS8344 architecture offers no inherent rejection of

noise or voltage variation in regards to the reference input.

This is of particular concern when the reference input is tied

to the power supply. Any noise and ripple from the supply

will appear directly in the digital results. While

high-frequency noise can be filtered out as discussed in the

previous paragraph, voltage variation due to line frequency

(50Hz or 60Hz) can be difficult to remove.

7FFD

7FFE

7FFF

Code

8000

8001

FIGURE 11. Histogram of 5,000 Conversions of a DC Input at the

Code Center, 2.7V operation internal clock mode.

The GND pin should be connected to a clean ground point.

In many cases, this will be the “analog” ground. Avoid

connections that are too near the grounding point of a

microcontroller or digital signal processor. If needed, run a

ground trace directly from the converter to the power-supply

entry point. The ideal layout will include an analog ground

plane dedicated to the converter and associated analog

circuitry.

AVERAGING

The noise of the A/D converter can be compensated by

averaging the digital codes. By averaging conversion results,

transition noise will be reduced by a factor of 1/√n, where n

is the number of averages. For example, averaging 4 conver-

ADS8344

SBAS139E

Revision History

DATE

REVISION PAGE

SECTION

DESCRIPTION

Package/Ordering Info

Added quantity to last column.

9/06

Electrical Characteristics Fixed typo. Changed +2.7V Gain Error minimum value (for EB, NB grade)

from ±0.0024 to ±0.024.

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

ADS8344

SBAS139E

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

PACKAGING INFORMATION

Orderable Device

ADS8344E

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 85

Top-Side Markings

Samples

Drawing

Qty

(1)

(2)

(3)

(4)

ACTIVE

SSOP

DBQ

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

Level-3-260C-168 HR

Level-2-260C-1 YEAR

ADS8344E

ADS8344E/2K5

ADS8344E/2K5G4

ADS8344EB

ACTIVE

DBQ

2500

Green (RoHS

& no Sb/Br)

ADS8344E

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

ADS8344E

ADS8344EB/2K5

ADS8344EB/2K5G4

ADS8344EBG4

ADS8344EG4

2500

Green (RoHS

& no Sb/Br)

ADS8344E

Green (RoHS

& no Sb/Br)

ADS8344E

Green (RoHS

& no Sb/Br)

ADS8344E

Green (RoHS

& no Sb/Br)

ADS8344E

ADS8344N

Green (RoHS

& no Sb/Br)

ADS8344N

ADS8344N/1K

ADS8344N/1KG4

ADS8344NB

1000

Green (RoHS

& no Sb/Br)

ADS8344N

Green (RoHS

& no Sb/Br)

ADS8344N

Green (RoHS

& no Sb/Br)

ADS8344N

ADS8344NB/1K

ADS8344NB/1KG4

ADS8344NBG4

ADS8344NG4

1000

Green (RoHS

& no Sb/Br)

ADS8344N

Green (RoHS

& no Sb/Br)

ADS8344N

Green (RoHS

& no Sb/Br)

ADS8344N

Green (RoHS

& no Sb/Br)

ADS8344N

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

24-Jul-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADS8344E/2K5

ADS8344EB/2K5

ADS8344N/1K

SSOP

DBQ

2500

1000

330.0

16.4

6.5

8.2

9.0

7.5

2.1

2.5

8.0

16.0

12.0

ADS8344NB/1K

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

24-Jul-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

ADS8344E/2K5

ADS8344EB/2K5

ADS8344N/1K

SSOP

DBQ

2500

1000

367.0

38.0

ADS8344NB/1K

Pack Materials-Page 2

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38

0,22

0,65

0,15

0,25

0,09

5,60

5,00

8,20

7,40

Gage Plane

0,25

0°–ā8°

0,95

0,55

Seating Plane

0,10

2,00 MAX

0,05 MIN

PINS **

DIM

6,50

5,90

6,50

5,90

7,50

8,50

7,90

10,50

9,90

10,50 12,90

A MAX

A MIN

6,90

9,90

12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

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which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of

non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products

Applications

Audio

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

Medical

Logic

Security

www.ti.com/security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense

Video and Imaging

www.ti.com/space-avionics-defense

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/omap

OMAP Applications Processors

Wireless Connectivity

TI E2E Community

e2e.ti.com

www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

ADS8344NB [TI]

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