ADS8353IPWR [TI]
具有单端输入的 16 位 600kSPS 双通道同步采样 SAR ADC | PW | 16 | -40 to 125;
| 型号： | ADS8353IPWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有单端输入的 16 位 600kSPS 双通道同步采样 SAR ADC | PW | 16 | -40 to 125 |
| 文件： | 总74页 (文件大小：3674K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADS8353, ADS7853, ADS7253
ZHCSCQ1B –OCTOBER 2013–REVISED AUGUST 2014
ADSxx53 双路高速 16 位、14 位和 12 位
同步采样模数转换器
1 特性
(3mm × 3mm) 和 16 引脚薄型小外形尺寸
(TSSOP) 封装
1
•
•
•
•
16 位、14 位和 12 位引脚兼容系列
双通道同步采样
支持单端和伪差分输入
高速：
2 应用
•
电机控制：
使用编码器进行位置测量
–
–
–
ADS8353：16 位，600kSPS
ADS7853：14 位，1MSPS
ADS7253：12 位，1MSPS
•
•
•
•
•
光纤网络：掺铒光纤放大器 (EDFA) 增益控制环路
保护中继器
电源质量测量
三相电源控制
可编程逻辑控制器
•
出色的直流性能：
–
ADS8353：
16 位丢码率 (NMC) 差分非线性
–
(DNL)，±2.5 最低有效位 (LSB)，最大积分
非线性 (INL)
3 说明
ADS8353、ADS7853 和 ADS7253 均属于引脚兼容的
双路高速同步采样模数转换器 (ADC) 产品系列，支持
单端和伪差分模拟输入。
–
–
ADS7853：
–
14 位 NMC DNL，±2 LSB，最大 INL
ADS7253：
每个器件均包含两个可独立编程的基准电压源，可用于
系统级的增益校准。 并且配有一个可在宽电源供电范
围内运行的灵活串行接口，从而轻松实现与多种主机控
制器的通信。 该系列器件支持两种低功耗模式，可针
对给定输出优化功耗。 所有器件都在扩展工业温度范
围（-40°C 至 + 125°C）内完全额定运行，并且采用引
脚兼容的 WQFN-16 (3mm ×
–
12 位 NMC DNL，±1 LSB，最大 INL
•
出色的交流性能：
–
ADS8353：
89dB 信噪比 (SNR)，-100dB 总谐波失真
(THD)
ADS7853：
–
–
–
–
82dB SNR，-90dB THD
3mm) 和 TSSOP-16 封装。
ADS7253：
器件信息(1)
–
72dB SNR，-90dB THD
•
•
•
双路、可编程和经缓冲的
2.5V 内部基准电压
部件号
ADSxx53
封装
TSSOP (16)
WQFN (16)
封装尺寸（标称值）
5.00mm x 4.40mm
3.00mm x 3.00mm
在 -40°C 至 125℃ 的扩展工业温度范围内完全额定
运行
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
小封装尺寸：
16 引脚超薄型四方扁平无引线 (WQFN) 封装
典型应用图
AVDD
VCM
AVDD
OPA836
+
4 ꢀꢀ
+
1 kꢀꢀ
AVDD
AINP
-
VIN+
1.8 nF
ADSxx53
1kꢀꢀ
AINM
GND
4 ꢀꢀ
VDC
INPUT DRIVER
ADS8353 : 16-bit, 600 kSPS
ADS7853 : 14-bit, 1 MSPS
ADS7253 : 12-bit, 1 MSPS
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SBAS584
ADS8353, ADS7853, ADS7253
ZHCSCQ1B –OCTOBER 2013–REVISED AUGUST 2014
www.ti.com.cn
目录
ADS7853, and ADS7253 ......................................... 27
Detailed Description ............................................ 28
8.1 Overview ................................................................. 28
8.2 Functional Block Diagram ....................................... 28
8.3 Feature Description................................................. 29
8.4 Device Functional Modes........................................ 35
8.5 Register Maps and Serial Interface......................... 35
Application and Implementation ........................ 49
9.1 Application Information............................................ 49
9.2 Typical Applications ................................................ 51
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configurations and Functions....................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ..................................... 5
7.2 Handling Ratings....................................................... 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics: ADS8353 ......................... 6
7.6 Electrical Characteristics: ADS7853 ......................... 7
7.7 Electrical Characteristics: ADS7253 ......................... 8
7.8 Electrical Characteristics: All Devices....................... 9
7.9 Timing Requirements: Interface Mode.................... 11
7.10 Timing Characteristics: Serial Interface ................ 11
7.11 Typical Characteristics: ADS8353 ........................ 13
7.12 Typical Characteristics: ADS7853 ........................ 17
7.13 Typical Characteristics: ADS7253 ........................ 22
7.14 Typical Characteristics: Common to ADS8353,
8
9
10 Power-Supply Recommendations ..................... 59
11 Layout................................................................... 60
11.1 Layout Guidelines ................................................. 60
11.2 Layout Example .................................................... 60
12 器件和文档支持 ..................................................... 61
12.1 相关链接................................................................ 61
12.2 相关文档ꢀ ............................................................ 61
12.3 Trademarks........................................................... 61
12.4 Electrostatic Discharge Caution............................ 61
12.5 术语表 ................................................................... 61
13 机械封装和可订购信息 .......................................... 61
4 修订历史记录
Changes from Revision A (July 2014) to Revision B
Page
•
•
•
更改了 ADS8353 预览器件并移动到了生产数据状态.............................................................................................................. 1
将文档状态从混合状态更改为生产数据................................................................................................................................... 1
Corrected cross-reference for Figure 99 .............................................................................................................................. 48
Changes from Original (October 2013) to Revision A
Page
•
更改了产品预览数据表............................................................................................................................................................ 1
2
Copyright © 2013–2014, Texas Instruments Incorporated
ADS8353, ADS7853, ADS7253
www.ti.com.cn
ZHCSCQ1B –OCTOBER 2013–REVISED AUGUST 2014
5 Device Comparison Table
RESOLUTION
PRODUCT
ADS8354
ADS7854
ADS7254
(Bits)
INPUT CONFIGURATION
Fully-differential
NMC (Bits)
INL (LSB)
±2.5
SNR (dB)
93 (typ)
88 (typ)
74 (typ)
16
16
14
12
14
Fully-differential
±1.5
12
Fully-differential
±1
Single-ended and
pseudo-differential
ADS8353
ADS7853
ADS7253
16
14
12
16
14
12
±2.5
±2
89 (typ)
84 (typ)
Single-ended and
pseudo-differential
Single-ended and
pseudo-differential
±1
73.5 (typ)
Copyright © 2013–2014, Texas Instruments Incorporated
3
ADS8353, ADS7853, ADS7253
ZHCSCQ1B –OCTOBER 2013–REVISED AUGUST 2014
www.ti.com.cn
6 Pin Configurations and Functions
RTE Package
WQFN-16
(Top View)
PW Package
TSSOP-16
(Top View)
AINP_A
AINM_A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AVDD
GND
REFIO_A
REFGND_A
REFGND_B
REFIO_B
1
2
3
4
12 SDO_B
REFIO_A
REFGND_A
REFGND_B
REFIO_B
AINM_B
SDO_B
SDO_A
SCLK
CS
11
10
9
SDO_A
SCLK
CS
Thermal Pad
SDI
AINP_B
DVDD
Pin Functions
PIN
NO.
NAME
TSSOP
WQFN
16
5
I/O
DESCRIPTION
AINM_A
AINM_B
AINP_A
AINP_B
AVDD
2
7
Analog input
Analog input
Analog input
Analog input
Supply
Negative analog input, channel A
Negative analog input, channel B
Positive analog input, channel A
Positive analog input, channel B
Supply voltage for ADC operation
Chip-select signal; active low
Digital I/O supply
1
15
6
8
16
11
9
14
9
CS
Digital input
Digital I/O supply
Supply
DVDD
7
GND
15
4
13
2
Digital ground
REFGND_A
REFGND_B
REFIO_A
REFIO_B
SCLK
Supply
Reference ground potential A
Reference ground potential B
Reference voltage input/output, channel A
Reference voltage input/output, channel B
Clock for serial communication
Data input for serial communication
5
3
Supply
3
1
Analog input/output
Analog input/output
Digital input
Digital input
Digital output
Digital output
6
4
12
10
13
14
10
8
SDI
SDO_A
SDO_B
11
12
Data output for serial communication, channel A and channel B
Data output for serial communication, channel B
Thermal
pad
Exposed thermal pad (only for WQFN). TI recommends
connecting this pin to the printed circuit board (PCB) ground.
Thermal pad
—
Supply
4
Copyright © 2013–2014, Texas Instruments Incorporated
ADS8353, ADS7853, ADS7253
www.ti.com.cn
ZHCSCQ1B –OCTOBER 2013–REVISED AUGUST 2014
7 Specifications
7.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
AVDD to REFGND_x or DVDD to GND
–0.3
6
V
Analog (AINP_x and AINM_x) and reference input (REFIO_x) voltage with
respect to REFGND_x
REFGND_x – 0.3
GND – 0.3
AVDD + 0.3
V
Digital input voltage with respect to GND
Ground voltage difference |REFGND_x-GND|
Input current to any pin except supply pins
Maximum virtual junction temperature, TJ
DVDD + 0.3
V
V
0.3
±10
150
mA
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
MIN
MAX
UNIT
Tstg
Storage temperature range
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
–2000
–500
2000
500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
5
MAX
UNIT
AVDD
DVDD
Analog supply voltage
Digital supply voltage
V
V
3.3
7.4 Thermal Information
ADS8353, ADS7853, ADS7253
THERMAL METRIC(1)
RTE (WQFN)
16 PINS
33.3
PW (TSSOP)
16 PINS
86.9
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
RθJC(top)
RθJB
29.5
21
7.3
39.1
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
0.8
ψJB
7.4
38.4
RθJC(bot)
0.9
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2013–2014, Texas Instruments Incorporated
5
ADS8353, ADS7853, ADS7253
ZHCSCQ1B –OCTOBER 2013–REVISED AUGUST 2014
www.ti.com.cn
7.5 Electrical Characteristics: ADS8353
All minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 5 V, DVDD = 3.3 V, VREF_A = VREF_B = VREF
2.5 V (internal), and fDATA = 600 kSPS, unless otherwise noted.
=
Typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
RESOLUTION
Resolution
16
Bits
DC ACCURACY(1)
NMC
INL
No missing codes
32-clock mode
16
–2.5
–0.99
–1
Bits
LSB
LSB
mV
Integral nonlinearity
Differential nonlinearity
Input offset error
EIO match
32-clock mode
32-clock mode
±1
±0.6
±0.5
±0.5
1
2.5
2
DNL
EIO
1
ADC_A to ADC_B
–1
1
mV
dEIO/dT
EG
Input offset thermal drift
Gain error
μV/°C
Referenced to the voltage at REFIO_x
ADC_A to ADC_B
–0.1
–0.1
±0.05
±0.05
1
0.1 %FS
0.1 %FS
ppm/°C
EG match
dEG/dT
Gain error thermal drift
Referenced to the voltage at REFIO_x
AC ACCURACY(2)
VREF = 2.5 V,
VREF input range, 32-clock mode
80.2
80.5
83
83.9
88.7
83
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
VREF = 2.5 V,
2 × VREF input range, 32-clock mode
SINAD
SNR
Signal-to-noise + distortion
VREF = 5 V (external),
VREF input range, 32-clock mode
VREF = 2.5 V,
VREF input range, 32-clock mode
VREF = 2.5 V,
2 × VREF input range, 32-clock mode
Signal-to-noise ratio
84
VREF = 5 V (external),
VREF input range, 32-clock mode
89
VREF = 2.5 V,
VREF input range, 32-clock mode
–100
–100
–100
105
105
105
VREF = 2.5 V,
2 × VREF input range, 32-clock mode
THD
Total harmonic distortion
Spurious-free dynamic range
VREF = 5 V (external),
VREF input range, 32-clock mode
VREF = 2.5 V,
VREF input range, 32-clock mode
VREF = 2.5 V,
2 × VREF input range, 32-clock mode
SFDR
VREF = 5 V (external),
VREF input range, 32-clock mode
(1) LSB = least significant bit.
(2) All ac parameters are tested at –0.5 dBFS and a 2-kHz input frequency.
6
Copyright © 2013–2014, Texas Instruments Incorporated
ADS8353, ADS7853, ADS7253
www.ti.com.cn
ZHCSCQ1B –OCTOBER 2013–REVISED AUGUST 2014
7.6 Electrical Characteristics: ADS7853
All minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 5 V, DVDD = 3.3 V, VREF_A = VREF_B = VREF
=
2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
Typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
RESOLUTION
Resolution
14
Bits
DC ACCURACY(1)
32-clock mode
16-clock mode
32-clock mode
16-clock mode
32-clock mode
16-clock mode
14
13
Bits
Bits
NMC
INL
No missing codes
–2
±0.7
±1
2
2.5
1
LSB
LSB
LSB
LSB
mV
Integral nonlinearity
–2.5
–0.99
–1
±0.5
±0.9
±0.5
±0.5
±1
DNL
EIO
Differential nonlinearity
2
Input offset error
EIO match
–1
1
ADC_A to ADC_B
–1
1
mV
dEIO/dT
EG
Input offset thermal drift
Gain error
μV/°C
Referenced to the voltage at REFIO_x
ADC_A to ADC_B
–0.1
–0.1
±0.05
±0.05
±1
0.1 %FS
0.1 %FS
ppm/°C
EG match
dEG/dT
Gain error thermal drift
Referenced to the voltage at REFIO_x
AC ACCURACY(2)
32-clock mode
16-clock mode
32-clock mode
16-clock mode
32-clock mode
16-clock mode
32-clock mode
16-clock mode
32-clock mode
16-clock mode
32-clock mode
16-clock mode
32-clock mode
16-clock mode
32-clock mode
16-clock mode
32-clock mode
16-clock mode
32-clock mode
16-clock mode
32-clock mode
16-clock mode
32-clock mode
16-clock mode
78.4
80.9
80.3
81.4
80.8
83.9
82.9
81
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
VREF = 2.5 V,
VREF input range
VREF = 2.5 V,
2 × VREF input range
SINAD
Signal-to-noise + distortion
VREF = 5 V (external),
VREF input range
78.5
VREF = 2.5 V,
VREF input range
80.5
81.5
81
VREF = 2.5 V,
2 × VREF input range
SNR
Signal-to-noise ratio
84
VREF = 5 V (external),
VREF input range
83.5
–100
–93
–98
–94
–102
–92
100
95
VREF = 2.5 V,
VREF input range
VREF = 2.5 V,
2 × VREF input range
THD
Total harmonic distortion
VREF = 5 V (external),
VREF input range
VREF = 2.5 V,
VREF input range
100
95
VREF = 2.5 V,
2 × VREF input range
SFDR
Spurious-free dynamic range
ADC-to-ADC isolation
102
95
VREF = 5 V (external),
VREF input range
fIN = 15 kHz at 10 %FS,
fNOISE = 25 kHz at FS
ISOXT
–100
dB
(1) LSB = least significant bit.
(2) All ac parameters are tested at –0.5 dBFS and a 2-kHz input frequency.
Copyright © 2013–2014, Texas Instruments Incorporated
7
ADS8353, ADS7853, ADS7253
ZHCSCQ1B –OCTOBER 2013–REVISED AUGUST 2014
www.ti.com.cn
7.7 Electrical Characteristics: ADS7253
All minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 5 V, DVDD = 3.3 V, VREF_A = VREF_B = VREF
2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
=
Typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
RESOLUTION
Resolution
12
Bits
DC ACCURACY(1)
NMC
INL
No missing codes
12
–1
Bits
LSB
LSB
mV
Integral nonlinearity
Differential nonlinearity
Input offset error
EIO match
±0.3
±0.3
±0.5
±0.5
±1
1
1
2
2
DNL
EIO
–0.99
–2
ADC_A to ADC_B
–2
mV
dEIO/dT
EG
Input offset thermal drift
Gain error
μV/°C
Referenced to the voltage at REFIO_x
ADC_A to ADC_B
–0.2
–0.2
±0.05
±0.05
±1
0.2 %FS
0.2 %FS
ppm/°C
EG match
dEG/dT
Gain error thermal drift
Referenced to the voltage at REFIO_x
AC ACCURACY(2)
VREF = 2.5 V,
VREF input range
71
72.9
72.9
73.4
73
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
VREF = 2.5 V,
2 × VREF input range
SINAD
SNR
Signal-to-noise + distortion
VREF = 5 V (external),
VREF input range
VREF = 2.5 V,
VREF input range
71.5
VREF = 2.5 V,
2 × VREF input range
Signal-to-noise ratio
73
VREF = 5 V (external),
VREF input range
73.5
–90
–90
–90
93.5
93.5
93.5
–80
VREF = 2.5 V,
VREF input range
VREF = 2.5 V,
2 × VREF input range
THD
Total harmonic distortion
VREF = 5 V (external),
VREF input range
VREF = 2.5 V,
VREF input range
VREF = 2.5 V,
2 × VREF input range
SFDR
Spurious-free dynamic range
ADC-to-ADC isolation
VREF = 5 V (external),
VREF input range
fIN = 15 kHz at 10 %FS,
fNOISE = 25 kHz at FS
ISOXT
(1) LSB = least significant bit.
(2) All ac parameters are tested at –0.5 dBFS and a 2-kHz input frequency.
8
Copyright © 2013–2014, Texas Instruments Incorporated
ADS8353, ADS7853, ADS7253
www.ti.com.cn
ZHCSCQ1B –OCTOBER 2013–REVISED AUGUST 2014
7.8 Electrical Characteristics: All Devices
All minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 5 V, DVDD = 3.3 V, VREF_A = VREF_B = VREF
=
2.5 V, and fDATA = maximum, unless otherwise noted.
Typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V.
PARAMETER
ANALOG INPUT
TEST CONDITIONS
MIN
TYP
MAX UNIT
Single-ended input,
AINM_x = GND
0
VREF
V
V
VREF
range
Pseudo-differential input,
AINM_x = +VREF / 2
–VREF / 2
VREF / 2
Full-scale input range(1)
(AINP_x – AINM_x)
Single-ended input,
AINM_x = GND,
AVDD ≥ 2 × VREF
FSR
0
2 × VREF
V
V
2 × VREF
range
Pseudo-differential input,
AINM_x = +VREF,
–VREF
VREF
AVDD ≥ 2 × VREF
VREF range
0
0
VREF
2 × VREF
0.1
V
V
V
V
Absolute input voltage
(AINP_x to REFGND)
VINP
2 × VREF range, AVDD ≥ 2 × VREF
Single-ended input
–0.1
VREF
range
Pseudo-differential input
VREF / 2 – 0.1 VREF / 2 VREF / 2 + 0.1
Absolute input voltage
(AINM_x to REFGND)
Single-ended input,
AVDD ≥ 2 × VREF
VINM
–0.1
0.1
V
V
2 × VREF
range
Pseudo-differential input,
AVDD ≥ 2 × VREF
VREF – 0.1
VREF
VREF + 0.1
In sample mode
In hold mode
40
4
pF
pF
µA
Ci
Input capacitance
Ilkg(i)
Input leakage current
0.1
INTERNAL VOLTAGE REFERENCE
REFDAC_x = 1FFh (default),
at 25°C
VREFOUT
Reference output voltage
2.495
2.500
2.505
V
REFDAC_x = 1FFh (default),
at 25°C
VREF-match
VREF_A to VREF_B matching
REFDAC_x resolution(2)
±1
1.1
±10
150
1
mV
mV
Reference voltage
temperature drift
dVREFOUT/dT
dVREFOUT/dt
RO
REFDAC_x = 1FFh (default)
1000 hours
ppm/°C
ppm
Ω
Long-term stability
Internal reference output
impedance
Reference output dc
current
IREFOUT
CREFOUT
tREFON
2
10
8
mA
µF
Recommended output
capacitor
Reference output settling
time
For CREF = 10 μF
ms
VOLTAGE REFERENCE INPUT
VREF Reference voltage (input)
IREF
VREF range
2.4
2.4
2.5
2.5
AVDD
V
V
2 × VREF range
AVDD / 2
Average Reference input
current
Per ADC
300
μA
External ceramic
reference capacitance
CREF
10
μF
μA
Ilkg(dc)
DC leakage current
±0.1
(1) Ideal input span, does not include gain or offset error.
(2) Refer to the Reference section for more details.
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Electrical Characteristics: All Devices (continued)
All minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 5 V, DVDD = 3.3 V, VREF_A = VREF_B = VREF
2.5 V, and fDATA = maximum, unless otherwise noted.
=
Typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V.
PARAMETER
SAMPLING DYNAMICS
TEST CONDITIONS
MIN
TYP
MAX UNIT
tA
Aperture delay
tA match
8
40
50
ns
ps
ps
ADC_A to ADC_B
tAJIT
Aperture jitter
DIGITAL INPUTS(3)
DVDD > 2.3 V
DVDD ≤ 2.3 V
DVDD > 2.3 V
DVDD ≤ 2.3 V
0.7 DVDD
0.8 DVDD
–0.3
DVDD + 0.3
DVDD + 0.3
0.3 DVDD
0.2 DVDD
V
V
VIH
VIL
High-level input voltage
V
Low-level input voltage
Input current
–0.3
V
±10
nA
DIGITAL OUTPUTS(3)
VOH
VOL
High-level output voltage
Low-level output voltage
IOH = 500-µA source
IOH = 500-µA sink
0.8 DVDD
0
DVDD
V
V
0.2 DVDD
POWER SUPPLY
Internal reference
4.5
4.5
5.0
5.0
5.5
5.5
V
V
External reference:
VEXT_REF < 4.5 V
±VREF
range
Analog supply voltage
(AVDD to AGND)
AVDD
DVDD
External reference:
VEXT_REF > 4.5 V
VEXT_REF
5.0
5.5
V
Internal reference
External reference
5.0
5.0
5.0
5.5
5.5
V
V
±2 × VREF
range
2 × VREF_EXT
Digital supply voltage
(DVDD to AGND)
1.65
5.5
10
V
AVDD = 5 V, fastest throughput
internal reference
8.5
7.5
5.5
4.5
2.5
mA
mA
mA
mA
mA
AVDD = 5 V, fastest throughput
external reference(4)
AVDD = 5 V, no conversion
internal reference
7
AIDD
Analog supply current
AVDD = 5 V, no conversion
external reference(4)
AVDD = 5 V, STANDBY mode
Internal Reference
AVDD = 5 V, STANDBY mode
external reference(4)
1
10
mA
μA
Power-down mode
50
50
DVDD = 3.3 V, CLOAD = 10 pF,
fastest throughput
0.5
mA
DIDD
PD
Digital supply current
DVDD = 5 V, CLOAD = 10 pF
fastest throughput
1
mA
Power dissipation
(normal operation)
AVDD = 5V, fastest throughput,
internal reference
42.5
mW
(3) Specified by design; not production tested.
(4) With internal reference powered down, CFR.B6 = 0.
10
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ZHCSCQ1B –OCTOBER 2013–REVISED AUGUST 2014
7.9 Timing Requirements: Interface Mode(1)
PARAMETER
ASSOCIATED FIGURES
Figure 1, Figure 91, Figure 92, Figure 93, Figure 94
Figure 91, Figure 92, Figure 93, Figure 94
Figure 91, Figure 92, Figure 93, Figure 94
tCLK
CLOCK period
Acquisition time
Conversion time
tACQ
tCONV
(1) These parameters are specific to the interface mode of operation. Refer to the Conversion Data Read section for more details.
7.10 Timing Characteristics: Serial Interface
PARAMETER
TEST CONDITIONS
ASSOCIATED FIGURES
MIN
TYP
MAX UNIT
TIMING REQUIREMENTS
tPH_CK
tPL_CK
fCLK
CLOCK high time
CLOCK low time
CLOCK frequency
CS high time
0.4
0.4
0.6 tCLK
Figure 1
Figure 1
Figure 99
0.6 tCLK
1 / tCLK MHz
tPH_CS
40
150
100
70
ns
ns
ns
ns
ADS8353
tPH_CS_SHRT
CS high time after frame abort
ADS7853
ADS7253
Setup time: CS falling edge to
SCLK falling edge
tSU_CSCK
tD_CKCS
15
15
5
ns
ns
ns
ns
µs
Delay time: Last SCLK falling edge
to CS rising edge
Figure 1
Setup time: DIN data valid to SCLK
falling edge
tSU_CKDI
tHT_CKDI
tPU_STDBY
Hold time: SCLK falling edge to
(previous) data valid on DIN
5
Power-up time from STANDBY
mode
Figure 96
Figure 98
1
With internal reference
With external reference
3
1
ms
ms
tPU_SPD
Power-up time from SPD mode
TIMING SPECIFICATIONS
ADS8353
ADS7853
32-CLK mode
1.666
µs
µs
µs
µs
µs
Figure 91, Figure 92
32-CLK mode
16-CLK mode
32-CLK mode
16-CLK mode
1
1
1
1
tTHROUGHPUT
Throughput time
Figure 93, Figure 94
Figure 91, Figure 92
Figure 93, Figure 94
ADS7253
Figure 91, Figure 92,
Figure 93, Figure 94
fTHROUGHPUT
tDV_CSDO
tDZ_CSDO
tD_CKDO
Throughput
1 / tTHROUGHPUT kSPS
Delay time: CS falling edge to data
enable
12
12
20
ns
ns
ns
Delay time: CS rising edge to data
going to 3-state
Figure 1
Delay time: SCLK falling edge to
next data valid
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Figure 1 shows the details of the serial interface between the device and the digital host controller.
CS
CS
SCLK
SDO
tSU_CSCK
2
tDV_CSDO
1
2
12
13
14
15
16
1
SCLK
tSU_CKDI
tHT_CKDI
B2
B14
B4
B15
B3
B1
SDI
Sample
N + 1
Sample
N
tPH_CS
CS
tSCLK
tD_CKCS
tPH_CK
tPL_CK
N-
N-
1
N-
8
N-
4
N-
3
N-
2
N-
9
N-
7
N-
6
1
2
SCLK
N
5
tD_CKDO
D9
tDZ_CSDO
D1 D0
SDO-
ADS8353/4
D6
D4
D5
D4
D3
D2
D0
0
V
V
D8
D6
D4
D7
SDO-
ADS7853/4
D3
D1
D2
D0
D1
0
0
0
0
0
V
V
V
V
D7
D5
D5
D3
SDO-
ADS7253/4
D2
Figure 1. Serial Interface Timing Diagram
12
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7.11 Typical Characteristics: ADS8353
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 600 kSPS, unless otherwise noted.
0
±20
0
±20
±40
±40
±60
±60
±80
±80
±100
±120
±140
±160
±180
±200
±100
±120
±140
±160
±180
±200
0
60
120
180
240
300
0
60
120
180
240
300
C201
C202
Input Frequency (kHz)
Input Frequency (kHz)
fIN = 2 kHz
SNR = 84.2 dB
THD = -101.3 dB
fIN = 100 kHz
SNR = 80.8 dB
THD = -99.1 dB
Figure 2. Typical FFT
Figure 3. Typical FFT
87
87
86
85
84
83
82
81
86
85
84
83
82
81
80
80
26
59
92
125
26
59
92
125
±40
±7
±40
±7
Free-Air Temperature (oC)
Free-Air Temperature (oC)
C203
C204
fIN = 2 kHz
Figure 4. SNR vs Temperature
fIN = 2 kHz
Figure 5. SINAD vs Temperature
90
90
89
88
87
86
85
84
83
82
89
88
87
86
85
84
83
82
2
2.5
3
3.5
4
4.5
5
5.5
2
2.5
3
3.5
4
4.5
5
5.5
C205
C206
Reference Voltage (V)
Reference Voltage (V)
fIN = 2 kHz
fIN = 2 kHz
Figure 7. SINAD vs Reference Voltage
Figure 6. SNR vs Reference Voltage
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Typical Characteristics: ADS8353 (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 600 kSPS, unless otherwise noted.
85
84
83
82
81
80
79
78
77
76
75
85
83
81
79
77
75
0
60
120
180
240
300
0
60
120
180
240
300
C207
C208
Input Frequency (kHz)
Input Frequency (kHz)
VREF = 5 V
Figure 8. SNR vs Input Frequency
VREF = 5 V
Figure 9. SINAD vs Input Frequency
±70
±70
±80
±80
±90
±90
±100
±110
±120
±130
±100
±110
±120
±130
26
59
92
125
2
2.5
3
3.5
4
4.5
5
5.5
±40
±7
Free-Air Temperature (oC)
Reference Voltage (V)
C209
C211
fIN = 2 kHz
Figure 10. THD vs Temperature
fIN = 2 kHz
Figure 11. THD vs Reference Voltage
±70
10
9.5
9
±80
±90
8.5
8
±100
±110
±120
±130
7.5
7
6.5
6
0
60
120
180
240
300
26
59
92
125
±40
±7
Free-Air Temperature (oC)
C213
C224
Input Frequency (kHz)
VREF = 5 V
Figure 12. THD vs Input Frequency
Figure 13. Analog Supply Current vs Temperature
14
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Typical Characteristics: ADS8353 (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 600 kSPS, unless otherwise noted.
40000
30000
20000
10000
0
10
9
8
7
6
5
4
3
2
32771 32772 32773 32774 32775 32776 32777
Code
0
4
8
12
16
20
C215
C225
SCLK Frequency (MHz)
65536 data points
VIN-DIFF = 0 V
Figure 15. DC Histogram
Figure 14. Analog Supply Current vs SCLK Frequency
1000
100
75
750
500
50
250
25
0
0
±250
±500
±750
±1000
±25
±50
±75
±100
±40
26
59
92
125
26
59
92
125
±40
±7
±7
Free-Air Temperature (oC)
Free-Air Temperature (oC)
C216
C217
Figure 16. Offset Error vs Temperature
Figure 17. Gain Error vs Temperature
2
1.5
1
2.5
2
1.5
1
0.5
0
0.5
0
-0.5
-1
-1.5
-2
-0.5
-1
-2.5
0
65535
0
65535
C218
C219
Code
Code
Figure 18. Typical DNL
Figure 19. Typical INL
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Typical Characteristics: ADS8353 (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 600 kSPS, unless otherwise noted.
2
1.5
1
2.5
2
1.5
1
Maximum
0.5
0
Maximum
Minimum
0.5
0
-0.5
-1
Minimum
92
-1.5
-2
-0.5
-1
-2.5
26
59
92
125
26
59
125
±40
±7
±40
±7
Free-Air Temperature (oC)
Free-Air Temperature (oC)
C221
C220
Figure 20. DNL vs Temperature
Figure 21. INL vs Temperature
2
1.5
1
2.5
2
1.5
1
Maximum
0.5
0
Maximum
Minimum
0.5
0
-0.5
-1
Minimum
-1.5
-2
-0.5
-1
-2.5
2
2.5
3
3.5
4
4.5
5
5.5
2
2.5
3
3.5
4
4.5
5
5.5
C222
C223
Reference Voltage (V)
Reference Voltage (V)
Figure 22. DNL vs Reference Voltage
Figure 23. INL vs Reference Voltage
16
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7.12 Typical Characteristics: ADS7853
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
0
±20
0
±20
±40
±40
±60
±60
±80
±80
±100
±120
±140
±160
±180
±200
±100
±120
±140
±160
±180
±200
0
100
100
±7
200
300
400
500
0
100
100
±7
200
300
400
500
C102
C101
Input Frequency (kHz)
Input Frequency (kHz)
fIN = 2 kHz
SNR = 81.1 dB
THD = –94.2 dB
fIN = 250 kHz
SNR = 80.2 dB
THD = –90.4 dB
16-CLK interface
16-CLK interface
Figure 24. Typical FFT
Figure 25. Typical FFT
0
±20
0
±20
±40
±40
±60
±60
±80
±80
±100
±120
±140
±160
±180
±100
±120
±140
±160
±180
±200
±200
0
200
300
400
500
0
200
300
400
500
C151
C152
Input Frequency (kHz)
Input Frequency (kHz)
fIN = 2 kHz
SNR = 81.9 dB
THD = –98.1 dB
fIN = 250 kHz
SNR = 80.8 dB
THD = –92.1 dB
32-CLK interface
32-CLK interface
Figure 26. Typical FFT
Figure 27. Typical FFT
85
84.5
84
84
83.5
83
32 CLK Mode
32 CLK Mode
83.5
83
82.5
82
16 CLK Mode
82.5
82
81.5
81
16 CLK Mode
81.5
80.5
81
80
26
59
92
125
26
59
92
125
±40
±40
Free-Air Temperature (oC)
Free-Air Temperature (oC)
C103
C104
fIN = 2 kHz
fIN = 2 kHz
Figure 28. SNR vs Temperature
Figure 29. SINAD vs Temperature
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Typical Characteristics: ADS7853 (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
84
83.5
83
85
84.5
84
83.5
83
82.5
82
82.5
82
81.5
81
81.5
81
80.5
80
80.5
80
2
2.5
3
3.5
4
4.5
5
5.5
2
2.5
3
3.5
4
4.5
5
5.5
C106
C105
Reference Voltage (V)
Reference Voltage (V)
fIN = 2 kHz
Figure 30. SNR vs Reference Voltage
fIN = 2 kHz
Figure 31. SINAD vs Reference Voltage
85
84.5
84
85
84.5
84
83.5
83
83.5
83
82.5
82
82.5
82
81.5
81
81.5
81
0
50
100
150
200
250
300
0
50
100
150
200
250
300
C108
C107
Input Frequency (kHz)
Input Frequency (kHz)
VREF = 5 V
VREF = 5 V
Figure 32. SNR vs Input Frequency
Figure 33. SINAD vs Input Frequency
±60
±70
±60
±70
±80
±80
16 CLK Mode
32 CLK Mode
16 CLK Mode
32 CLK Mode
±90
±90
±100
±110
±120
±100
±110
±120
26
59
92
125
2
2.5
3
3.5
4
4.5
5
5.5
±40
±7
Free-Air Temperature (oC)
Reference Voltage (V)
C109
C111
fIN = 2 kHz
Figure 34. THD vs Temperature
fIN = 2 kHz
Figure 35. THD vs Reference Voltage
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Typical Characteristics: ADS7853 (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
±60
10
9.5
9
±70
±80
8.5
8
±90
7.5
7
±100
±110
±120
6.5
6
0
50
100
150
200
250
300
26
59
92
125
±40
±7
Free-Air Temperature (oC)
C113
C124
Input Frequency (kHz)
VREF = 5 V
Figure 36. THD vs Input Frequency
Figure 37. Analog Supply Current vs Temperature
10
10
9
8
7
6
5
4
3
2
9
8
7
6
5
4
0
8
16
24
32
40
0
4
8
12
16
20
C125
C030
SCLK Frequency (MHz)
SCLK Frequency (MHz)
32-CLK interface
Figure 39. Analog Supply Current vs SCLK Frequency
16-CLK interface
Figure 38. Analog Supply Current vs SCLK Frequency
70000
70000
60000
50000
40000
30000
20000
10000
0
60000
50000
40000
30000
20000
10000
0
8098
8099
Code
8100
8099
8100
Code
8101
C115
C155
16-CLK interface
65536 data points
VIN-DIFF = 0 V
32-CLK interface
65536 data points
VIN-DIFF = 0 V
Figure 40. DC Histogram
Figure 41. DC Histogram
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Typical Characteristics: ADS7853 (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
100
1000
75
750
32 CLK Mode
16 CLK Mode
50
500
16 CLK Mode
25
250
0
0
32 CLK Mode
±25
±50
±75
±100
±250
±500
±750
±1000
26
59
92
125
±40
±7
26
59
92
125
±40
±7
Free-Air Temperature (oC)
Free-Air Temperature (oC)
C11
C116
Figure 43. Gain Error vs Temperature
Figure 42. Offset Error vs Temperature
1
0.75
0.5
2
1.5
1
0.25
0
0.5
0
-0.25
-0.5
-0.75
-1
-0.5
-1
-1.5
-2
0
16384
0
16384
C119
C118
Code
Code
16-CLK interface
16-CLK interface
Figure 44. Typical DNL
Figure 45. Typical INL
2
1.5
1
2
1.5
1
0.5
0
0.5
0
-0.5
-1
-0.5
-1.5
-1
0
-2
0
16384
16384
C153
C154
Code
Code
32-CLK interface
32-CLK interface
Figure 46. Typical DNL
Figure 47. Typical INL
20
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Typical Characteristics: ADS7853 (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
2
1.5
1
2
1.5
1
Maximum 16 CLK Mode
Maximum 32 CLK Mode
Maximum 16 CLK Mode
Maximum 32 CLK Mode
0.5
0
0.5
0
Minimum 32 CLK Mode
-0.5
-1
Minimum 32 CLK Mode
-0.5
-1
Minimum 16 CLK Mode
-1.5
-2
Minimum 16 CLK Mode
26
59
92
125
26
59
92
125
±40
±7
±40
±7
Free-Air Temperature (oC)
Free-Air Temperature (oC)
C120
C121
Figure 48. DNL vs Temperature
Figure 49. INL vs Temperature
2
1.5
1
2
1.5
1
Maximum 16 CLK Mode
Maximum 32 CLK Mode
Maximum 16 CLK Mode
0.5
0
0.5
0
Maximum 32 CLK Mode
Minimum 16 CLK Mode
Minimum 32 CLK Mode
Minimum 32 CLK Mode
-0.5
-1
-0.5
-1
Minimum 16 CLK Mode
2
2.5
3
3.5
4
4.5
5
5.5
2
2.5
3
3.5
4
4.5
5
5.5
C123
C122
Reference Voltage (V)
Reference Voltage (V)
Figure 50. DNL vs Reference Voltage
Figure 51. INL vs Reference Voltage
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7.13 Typical Characteristics: ADS7253
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
0
±20
0
±20
±40
±40
±60
±60
±80
±80
±100
±120
±140
±160
±180
±200
±100
±120
±140
±160
±180
±200
0
100
100
±7
200
300
400
500
0
100
100
±7
200
300
400
500
C002
C001
Input Frequency (kHz)
Input Frequency (kHz)
fIN = 2 kHz
SNR = 73.2 dB
THD = –90.5 dB
fIN = 250 kHz
SNR = 73.1 dB
THD = –90.1 dB
16-CLK interface
16-CLK interface
Figure 52. Typical FFT
Figure 53. Typical FFT
0
±20
0
±20
±40
±40
±60
±60
±80
±80
±100
±120
±140
±160
±180
±100
±120
±140
±160
±180
±200
±200
0
200
300
400
500
0
200
300
400
500
C052
C051
Input Frequency (kHz)
Input Frequency (kHz)
fIN = 2 kHz
SNR = 73.6 dB
THD = –91.6 dB
fIN = 250 kHz
SNR = 73.4 dB
THD = –90.6 dB
32-CLK interface
32-CLK interface
Figure 54. Typical FFT
Figure 55. Typical FFT
74
73.5
73
74
73.5
73
32 CLK Mode
16 CLK Mode
72.5
72
72.5
72
71.5
71
71.5
71
70.5
70.5
70
70
26
59
92
125
26
59
92
125
±40
±40
Free-Air Temperature (oC)
Free-Air Temperature (oC)
C003
C004
fIN = 2 kHz
fIN = 2 kHz
Figure 56. SNR vs Temperature
Figure 57. SINAD vs Temperature
22
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Typical Characteristics: ADS7253 (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
74
73.5
73
74
73
72
71
70
32 CLK Mode
32 CLK Mode
16 CLK Mode
16 CLK Mode
72.5
72
71.5
71
70.5
70
2
2.5
3
3.5
4
4.5
5
5.5
2
2.5
3
3.5
4
4.5
5
5.5
C005
C00
Reference Voltage (V)
Reference Voltage (V)
fIN = 2 kHz
fIN = 2 kHz
Figure 58. SNR vs Reference Voltage
Figure 59. SINAD vs Reference Voltage
75
74.5
74
75
74.5
74
16 CLK Mode
16 CLK Mode
73.5
73
73.5
73
32 CLK Mode
72.5
72
72.5
72
71.5
71
71.5
71
0
50
100
150
200
250
300
0
50
100
150
200
250
300
C007
C008
Input Frequency (kHz)
Input Frequency (kHz)
VREF = 5 V
Figure 60. SNR vs Input Frequency
VREF = 5 V
Figure 61. SINAD vs Input Frequency
±60
±60
±70
±70
±80
±80
32 CLK Mode
16 CLK Mode
±90
±90
±100
±110
±120
±100
±110
±120
26
59
92
125
2
2.5
3
3.5
4
4.5
5
5.5
±40
±7
C009
Free-Air Temperature (oC)
Reference Voltage (V)
C011
fIN = 2 kHz
fIN = 2 kHz
Figure 63. THD vs Reference Voltage
Figure 62. THD vs Temperature
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Typical Characteristics: ADS7253 (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
±60
8
7.5
7
±70
±80
6.5
6
16 CLK Mode
32 CLK Mode
±90
5.5
5
±100
±110
±120
4.5
4
0
50
100
150
200
250
300
26
59
92
125
±40
±7
Free-Air Temperature (oC)
C013
C024
Input Frequency (kHz)
VREF = 5 V
Figure 64. THD vs Input Frequency
Figure 65. Analog Supply Current vs Temperature
10
10
9
8
7
6
5
4
3
2
9
8
7
6
5
4
0
8
16
24
32
40
0
4
8
12
16
20
C125
C030
SCLK Frequency (MHz)
SCLK Frequency (MHz)
32-CLK interface
Figure 67. Analog Supply Current vs SCLK Frequency
16-CLK interface
Figure 66. Analog Supply Current vs SCLK Frequency
60000
60000
50000
40000
30000
20000
10000
0
50000
40000
30000
20000
10000
0
2024
2025
Code
2026
2024
2025
Code
2026
C015
C015
16-CLK interface
65536 data points
VIN-DIFF = 0 V
32-CLK interface
65536 data points
VIN-DIFF = 0 V
Figure 68. DC Histogram
Figure 69. DC Histogram
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Typical Characteristics: ADS7253 (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
2000
1500
1000
500
100
32 CLK Mode
75
16 CLK Mode
50
16 CLK Mode
25
32 CLK Mode
0
0
±500
±1000
±1500
±2000
±25
±50
±75
±100
26
59
92
125
26
59
92
125
±40
±7
±40
±7
Free-Air Temperature (oC)
Free-Air Temperature
C016
C01
Figure 70. Offset Error vs Temperature
Figure 71. Gain Error vs Temperature
1
0.75
0.5
1
0.75
0.5
0.25
0
0.25
0
-0.25
-0.5
-0.75
-1
-0.25
-0.5
-0.75
-1
0
4096
0
4096
C019
C018
Code
Code
16-CLK interface
16-CLK interface
Figure 72. Typical DNL
Figure 73. Typical INL
1
0.75
0.5
1
0.75
0.5
0.25
0
0.25
0
-0.25
-0.5
-0.75
-0.25
-0.5
-0.75
-1
0
-1
0
4096
4096
C053
C054
Code
Code
32-CLK interface
32-CLK interface
Figure 74. Typical DNL
Figure 75. Typical INL
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Typical Characteristics: ADS7253 (continued)
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = 1 MSPS, unless otherwise noted.
1
0.75
0.5
1
0.75
0.5
Maximum 16 CLK Mode
Maximum 32 CLK Mode
Maximum 16 CLK Mode
Maximum 32 CLK Mode
0.25
0
0.25
0
Minimum 32 CLK Mode
Minimum 32 CLK Mode
-0.25
-0.5
-0.75
-1
-0.25
-0.5
-0.75
-1
Minimum 16 CLK Mode
Minimum 16 CLK Mode
26
59
92
125
26
59
92
125
±40
±7
±40
±7
Free-Air Temperature (oC)
Free-Air Temperature (oC)
C020
C021
Figure 76. DNL vs Temperature
Figure 77. DNL vs Temperature
1
0.75
0.5
1
0.75
0.5
Maximum 16 CLK Mode
Maximum 16 CLK Mode
0.25
0
0.25
0
Maximum 32 CLK Mode
Minimum 32 CLK Mode
Maximum 32 CLK Mode
Minimum 32 CLK Mode
-0.25
-0.5
-0.75
-1
-0.25
-0.5
-0.75
-1
Minimum 16 CLK Mode
Minimum 16 CLK Mode
2
2.5
3
3.5
4
4.5
5
5.5
C022
2
2.5
3
3.5
4
4.5
5
5.5
Reference Voltage (V)
Reference Voltage (V)
C023
Figure 78. DNL vs Reference Voltage
Figure 79. INL vs Reference Voltage
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7.14 Typical Characteristics: Common to ADS8353, ADS7853, and ADS7253
At TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V (internal), and fDATA = maximum, unless otherwise noted.
200
160
120
80
3
2.5
2
16 CLK Mode
1.5
1
32 CLK Mode
40
0.5
0
16 CLK Mode
32 CLK Mode
0
-40
-7
26
59
92
125
C028
-40
-7
26
59
92
125
C027
Free- AirTemperature (oC)
Free-Air Temperature (oC)
Figure 80. STANDBY Current vs Temperature
Figure 81. Power-Down Current vs Temperature
2.55
2.53
2.51
2.49
2.47
2.45
2.6
2.55
2.5
2.45
2.4
2.35
2.3
-40
-7
26
59
92
125
-5
0
5
10
15
20
25
30
C017
Free-Air Temperature (oC)
C016
Load Current (mA)
ROUT = 0.67 Ω
Figure 83. Internal Reference Output Impedance
Figure 82. Internal Reference Output vs Temperature
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8 Detailed Description
8.1 Overview
These devices belong to a family of pin-compatible, dual, high-speed, simultaneous-sampling, analog-to-digital
converters (ADCs). The ADS8353, ADS7853, and ADS7253 support single-ended and pseudo-differential input
signals. The devices provide a simple, serial interface to the host controller and operate over a wide range of
analog and digital power supplies.
These devices have two independently programmable internal references to achieve system-level gain error
correction. The Functional Block Diagram section provides a functional block diagram of the device.
8.2 Functional Block Diagram
REF_A
Comparator
S/H
CDAC
SAR
SAR
ADC_A
ADC_B
Serial
Interface
CDAC
S/H
Comparator
REF_B
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8.3 Feature Description
8.3.1 Reference
The device has two simultaneous sampling ADCs (ADC_A and ADC_B). ADC_A and ADC_B operate with
reference voltages VREF_A and VREF_B present on the REFIO_A and REFIO_B pins, respectively. The REFIO_A
and REFIO_B pins should be decoupled with the REFGND_A and REFGND_B pins, respectively, with 10-µF
decoupling capacitors.
The device supports operation either with an internal or external reference source, as shown in Figure 84. The
reference voltage source is determined by setting bit 6 of the configuration register (CFR.B6). Note that this bit is
common to ADC_A and ADC_B.
AINP_A
ADC_A
AINM_A
REFGND_A
REFDAC_A
DAC_A
REFIO_A
10 PF
Enable
CFR.B6
INTREF
DAC_B
REFIO_B
REFDAC_B
10 PF
REFGND_B
AINP_B
AINM_B
ADC_B
Figure 84. Reference Configurations and Connections
When CFR.B6 is 0, the device shuts down the internal reference source (INTREF) and ADC_A and ADC_B
operate on external reference voltages provided by the user on the REFIO_A and REFIO_B pins, respectively.
When CFR.B6 is 1, the device operates with the internal reference source (INTREF) connected to REFIO_A and
REFIO_B via DAC_A and DAC_B, respectively. In this configuration, VREF_A and VREF_B can be changed
independently by writing to the respective user-programmable registers, REFDAC_A and REFDAC_B,
respectively. Refer to the REFDAC Registers (REFDAC_A and REFDAC_B) section for more details.
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Feature Description (continued)
8.3.2 Analog Inputs
The ADS8353, ADS7853, and ADS7253 support single-ended or pseudo-differential analog inputs on both ADC
channels. These inputs are sampled and converted simultaneously by the two ADCs, ADC_A and ADC_B.
ADC_A samples and converts (VAINP_A – VAINM_A), and ADC_B samples and converts (VAINP_B – VAINM_B).
Figure 85a and Figure 85b show equivalent circuits for the ADC_A and ADC_B analog input pins, respectively.
Series resistance, RS, represents the on-state sampling switch resistance (typically 50 Ω) and CSAMPLE is the
device sampling capacitor (typically 40 pF).
AVDD
AVDD
RS CSAMPLE
RS CSAMPLE
AINP_A
AINP_B
GND
GND
AVDD
AVDD
RS CSAMPLE
RS CSAMPLE
AINM_A
AINM_B
GND
GND
a) ADC_A
b) ADC_B
Figure 85. Equivalent Circuit for the Analog Input Pins
8.3.2.1 Analog Input: Full-Scale Range Selection
The full-scale range (FSR) supported at the analog inputs of the device is programmable with bit B9 of the
configuration register (CFR.B9). This bit is common for both ADCs (ADC_A and ADC_B). The FSR is given by
Equation 1 and Equation 2 :
For CFR.B9 = 0, FSR_ADC_A = 0 to VREF_A and FSR_ADC_B = 0 to VREF_B
(1)
For CFR.B9 = 1, FSR_ADC_A = 0 to 2 × VREF_A and FSR_ADC_B = 0 to 2 × VREF_B
where:
•
VREF_A and VREF_B are the reference voltages going to ADC_A and ADC_B, respectively (as described in the
Reference section).
(2)
Therefore, with appropriate settings of the REFDAC_A and REFDAC_B registers, CFR.B7, and CFR.B9, the
maximum dynamic range of the ADC can be used.
Note that while using CFR.B9 set to 1, care must be taken so that the ADC analog supply (AVDD) is as in
Equation 3 and Equation 4:
2 × VREF_A ≤ AVDD ≤ AVDD(max)
2 × VREF_B ≤ AVDD ≤ AVDD(max)
(3)
(4)
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Feature Description (continued)
8.3.2.2 Analog Input: Single-Ended and Pseudo-Differential Configurations
The ADS8353, ADS7853, and ADS7253 can support single-ended or pseudo-differential input configurations.
For supporting single-ended inputs, B7 in the configuration register (CFR.B7) must be set to 0 (CFR.B7 = 0) and
AINM_A and AINM_B must be externally connected to GND.
For supporting pseudo-differential inputs, CFR.B7 must be set to 1 (CFR.B7 = 1) and AINM_A and AINM_B must
be externally connected to FSR_ADC_A / 2 and FSR_ADC_B / 2, respectively. Note that CFR.B7 is common to
both ADCs.
The CFR.B9 and CFR.B7 settings can be combined to select the desired input configuration, as shown in
Table 1.
Table 1. Input Configurations
INPUT RANGE SELECTION
AINM SELECTION
CONNECTION DIAGRAM
VREF_x
VREF_x
REFIO_x
AINP_x
CFR.B9 = 0
CFR.B7 = 0
(FSR_ADC_A = 0 to VREF_A
(FSR_ADC_B = 0 to VREF_B
)
)
(AINM_A = GND)
(AINM_B = GND)
0 V
Device
AINM_x
2 u VREF_x
VREF_x
REFIO_x
AINP_x
CFR.B9 = 1
CFR.B7 = 0
(FSR_ADC_A = 0 to 2 x VREF_A
(FSR_ADC_B = 0 to 2 x VREF_B
)
)
(AINM_A = GND)
(AINM_B = GND)
0 V
Device
AINM_x
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Feature Description (continued)
Table 1. Input Configurations (continued)
INPUT RANGE SELECTION
AINM SELECTION
CONNECTION DIAGRAM
VREF_x
VREF_x
REFIO_x
AINP_x
0 V
VREF_x / 2
2 u VREF_x
CFR.B9 = 0
(FSR_ADC_A = VREF_A
(FSR_ADC_B = VREF_B
CFR.B7 = 1
(AINM_A = VREF_A/2)
(AINM_B = VREF_B/2)
Device
)
)
AINM_x
VREF_x
REFIO_x
AINP_x
0 V
CFR.B9 = 1
(FSR_ADC_A = 2 x VREF_A
(FSR_ADC_B = 2 x VREF_B
CFR.B7 = 1
(AINM_A = VREF_A
(AINM_B = VREF_B
Device
)
)
)
)
AINM_x
VREF_x
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8.3.3 Transfer Function
The device supports two input configurations:
1. Single-ended inputs, CFR.B7 = 0 (default), or
2. Pseudo-differential inputs, CFR.B7 = 1.
The device also supports two output data formats:
1. Straight binary output, CFR.B4 = 0 (default), or
2. Twos compliment output, CFR.B4 = 1.
Device resolution is calculated by Equation 5:
1 LSB = (FSR_ADC_x) / (2N)
where:
•
•
N = 16 (ADS8353), 14 (ADS7853), or 12 (ADS7253) and
FSR_ADC_x is the full-scale input range of the ADC (refer to the Analog Input section for more details)
(5)
Table 2 and Table 3 show the different input voltages and the corresponding output codes from the device.
Table 2. Transfer Characteristics for Straight Binary Output (CFR.B4 = 0, Default)
OUTPUT CODE (Hex)
INPUT VOLTAGE
INPUT
STRAIGHT BINARY (CFR.B4 = 0, Default)
CONFIGURATION
AINP_x
AINM_x
AINP_x - AINM_x
CODE
ADS8353
ADS7853
ADS7253
≤ 1 LSB
≤ 1 LSB
ZC
0000
0000
000
7FF
FFF
000
7FF
FFF
Single-ended
(CFR.B7 = 0,
default)
FSR_ADC_x / 2
≥ FSR_ADC_x – 1 LSB
≤ 1 LSB
0
FSR_ADC_x / 2
MC
7FFF
1FFF
3FFF
0000
≥ FSR_ADC_x – 1 LSB
≤ –FSR_ADC_x / 2 + 1 LSB
0
FSC
ZC
FFFF
0000
Pseudo-differential
(CFR.B7 = 1)
FSR_ADC_x / 2
≥ FSR_ADC_x – 1 LSB
FSR_ADC_x / 2
MC
7FFF
1FFF
3FFF
≥ FSR_ADC_x / 2 – 1 LSB
FSC
FFFF
Table 3. Transfer Characteristics for Twos Compliment Output (CFR.B4 = 1)
OUTPUT CODE (Hex)
TWOS COMPLIMENT (CFR.B4 = 1)
INPUT VOLTAGE
AINM_x
INPUT
CONFIGURATION
AINP_x
≤ 1 LSB
AINP_x - AINM_x
≤ 1 LSB
CODE
NFSC
MC
ADS8353
8000
ADS7853
2000
ADS7253
800
Single-ended
(CFR.B7 = 0,
default)
FSR_ADC_x / 2
≥ FSR_ADC_x – 1 LSB
≤ 1 LSB
0
FSR_ADC_x / 2
0000
0000
000
≥ FSR_ADC_x – 1 LSB
≤ –FSR_ADC_x / 2 + 1 LSB
0
PFSC
NFSC
MC
7FFF
8000
1FFF
2000
7FF
800
Pseudo-differential
(CFR.B7 = 1)
FSR_ADC_x / 2
≥ FSR_ADC_x – 1 LSB
FSR_ADC_x / 2
0000
0000
000
≥ FSR_ADC_x / 2 – 1 LSB
PFSC
7FFF
1FFF
7FF
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Figure 86 shows the ideal device transfer characteristics for the single-ended analog input.
FSC
PFSC
MC
MC
NFSC
ZC
1 LSB
FSR_ADC_x / 2
FSR_ADC_x ± 1 LSB
Single-Ended Analog Input
VIN
(AINP_x ± AINM_x)
Figure 86. Ideal Transfer Characteristics for a Single-Ended Analog Input
Figure 87 shows the ideal device transfer characteristics for the pseudo-differential analog input.
FSC
PFSC
-FSR_ADC_x/2
+ 1 LSB
0
MC
FSR_ADC_x/2
MC
± 1 LSB
ZC
NFSC
Pseudo-Differential Analog Input
(AINP_x ± AINM_x)
Figure 87. Ideal Transfer Characteristics for a Pseudo-Differential Analog Input
34
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8.4 Device Functional Modes
The device provides three user-programmable registers: the configuration register (CFR), the REFDAC_A
register, and the REFDAC_B register. These registers support write (refer to the Write to User Programmable
Registers section) and readback (refer to the Reading User-Programmable Registers section) operations and
allow the user to customize ADC behavior for specific application requirements.
The device supports four interface modes (refer to the Conversion Data Read section), two low-power modes
(refer to the Low-Power Modes section), and short-cycling/reconversion feature (refer to the Frame Abort,
Reconversion, or Short-Cycling section).
8.5 Register Maps and Serial Interface
8.5.1 Serial Interface
The device uses the serial clock (SCLK) for synchronizing data transfers in and out of the device.
The CS signal defines one conversion and serial transfer frame. A frame starts with a CS falling edge and ends
with a CS rising edge. Between the start and end of the frame, a minimum of N SCLK falling edges must be
provided to validate the read or write operation. As shown in Table 4, N depends upon the interface mode used
to read the conversion result. When N SCLK falling edges are provided, the write operation attempted in the
frame is validated and the internal user-programmable registers are updated on the subsequent CS rising edge.
This CS rising edge also ends the frame.
Table 4. SCLK Falling Edges for a Valid Write Operation
MINIMUM SCLK FALLING EDGES REQUIRED TO
INTERFACE MODE
VALIDATE WRITE OPERATION N
32-CLK, dual-SDO mode (default). See the 32-CLK, Dual-SDO Mode section.
32-CLK, single-SDO mode. See the 32-CLK, Single-SDO Mode section.
16-CLK, dual-SDO mode. See the 16-CLK, Dual-SDO Mode section.
16-CLK, single SDO mode. See the 16-CLK, Single SDO Mode section.
32
48
16
32
If CS is brought high before providing N SCLK falling edges, the write operation attempted in the frame is not
valid. Refer to the Frame Abort, Reconversion, or Short-Cycling section for more details.
8.5.2 Write to User Programmable Registers
The device features three user-programmable registers: the configuration register (CFR), the REFDAC_A
register, and the REFDAC_B register. These registers can be written with the device SDI pin. The first 16 bits of
data on SDI are latched into the device on the first 16 SCLK falling edges. However, the new configuration takes
effect only when the read or write operation is validated. If these registers are not required to update, SDI must
remain low during the respective frames.
The first four SDI data bits (B[15:12]) determine what operation is performed (that is, either a read or write
operation or no operation), which register address the operation uses, and the function of the next 12 SDI data
bits (B[11:0]). Table 5 lists the various combinations supported for B[15:12].
Table 5. Data Write Operation
B15
0
B14
0
B13
0
B12
0
OPERATION
No operation is performed
REFDAC_A read
FUNCTION OF BITS B[11:0]
These bits are ignored
0
0
0
1
000h; see the Reading User-Programmable Registers section
000h; see the Reading User-Programmable Registers section
000h; see the Reading User-Programmable Registers section
See the Configuration Register (CFR) section
See the REFDAC_A section
0
0
1
0
REFDAC_B read
0
0
1
1
CFR read
1
0
0
0
CFR write
1
0
0
1
REFDAC_A write
REFDAC_B write
No operation is performed
No operation is performed
1
0
1
0
See the REFDAC_B section
1
0
1
1
These bits are ignored
X
1
X
X
These bits are ignored
Copyright © 2013–2014, Texas Instruments Incorporated
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8.5.2.1 Configuration Register (CFR)
The device operation configuration is controlled by the configuration register (CFR) status. Data written into the
CFR in a valid frame (F) determine the device configuration for frame (F+1). The bit functions are outlined in
Figure 88. On power-up, all bits in the CFR default to 0.
Figure 88. CFR Bit Functions
15
WRITE/READ
7
14
13
ADDR1
5
12
ADDR0
4
11
10
9
8
0
0
0
RD_CLK_
MODE
RD_DATA_
LINES
0
6
INPUT_RANGE
3
2
1
0
RD_DATA_
FORMAT
INM_SEL
REF_SEL
STANDBY
0
0
Table 6. Configuration Register (CFR) Field Descriptions
Bit
15
14
13
12
Field
WRITE/READ
Type
W
Reset
0h
Description
These bits select the user-programmable register.
1000 = Select this combination to write to the CFR register and
to enable bits 11:0
0
R/W
R/W
R/W
0h
ADDR1
ADDR0
0h
0h
This bit provides clock mode selection for the serial interface.
0 = Selects 32-CLK mode (default)
11
10
RD_CLK_MODE
RD_DATA_LINES
R/W
R/W
0h
0h
1 = Selects 16-CLK mode
(Note that the ADS8353 only supports 32-CLK mode. This bit is
ignored for the ADS8353.)
This bit provides data line selection for the serial interface.
0 = Use SDO_A to output ADC_A data and SDO_B to output of
ADC_B data (default)
1 = Use only SDO_A to output of ADC_A data followed by
ADC_B data
This bit selects the maximum input range for the ADC as a
function of the reference voltage provided to the ADC. See the
Analog Inputs section for more details.
0 = FSR equals VREF
9
8
INPUT_RANGE
0
R/W
R/W
0h
0h
1 = FSR equals 2 × VREF
This bit must be set to 0 (default)
This bit selects the voltage to be externally connected to the
INM pin.
0 = INM must be externally connected to the GND potential
(default)
7
INM_SEL
R/W
0h
1 = INM must be externally connected to the FSR_ADC_x / 2
potential
This bit selects the ADC reference voltage source. Refer to the
Reference section for more details.
0 = Use external reference (default)
6
5
REF_SEL
STANDBY
R/W
W
0h
0h
1 = Use internal reference
This bit is used by the device to enter or exit STANDBY mode.
Refer to the STANDBY Mode section for more details.
This bit selects the output data format.
0 = Output is in straight binary format (default)
1 = Output is in twos compliment format
4
RD_DATA_FORMAT
0
R/W
R/W
0h
0h
3:0
These bits must be set to 0 (default)
36
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ZHCSCQ1B –OCTOBER 2013–REVISED AUGUST 2014
8.5.2.2 REFDAC Registers (REFDAC_A and REFDAC_B)
The REFDAC registers, bit functions, and resolution information are described in this section.
Figure 89. REFDAC_X Bit Functions
15
14
0
13
ADDR1
5
12
ADDR0
4
11
D8
3
10
D7
2
9
D6
1
8
D5
0
WRITE/READ
7
6
D4
D3
D2
D1
D0
0
0
0
Table 7. REFDAC Registers Field Descriptions
Bit
15
14
13
12
Field
Type
W
Reset
0h
Description
WRITE/READ
0
These bits select the configurable register address.
1001 = Select this combination to write to the REFDAC_A
register
1010 = Select this combination to write to the REFDAC_B
register
R/W
R/W
R/W
0h
ADDR1
ADDR0
0h
0h
Data to program the individual DAC output voltage.
Note: These bits are valid only for bits 15:12 = 1001 or bits
15:12 = 1010.
Table 8 shows the relationship between the REFDAC_x
programmed value and the DAC_x output voltage.
11:3
2:0
D[8:0]
0
R/W
R/W
0h
0h
This bit must be set to 0 (default)
Table 8. REFDAC Settings
REFDAC_x VALUE (Bits 11:3 in Hex)
B[2:0]
Typical DAC_x OUPTUT VOLTAGE (V)(1)
1FF (default)
000
000
000
—
2.5000
2.4989
2.4978
—
1FE
1FD
—
1D7
—
000
—
2.45
—
1AE
—
000
—
2.40
—
186
—
000
—
2.35
—
15D
—
000
—
2.30
—
134
—
000
—
2.25
—
10C
—
000
—
2.20
—
0E3
—
000
—
2.15
—
0BA
—
000
—
2.10
—
091
—
000
—
2.05
—
069
—
000
—
2.00
—
064 to 000
000
Do not use
(1) Actual output voltage may vary by a few millivolts from the specified value. To obtain the desired output voltage, TI recommends starting
with the specified register setting and then experimenting with five codes on either side of the specified register setting.
Copyright © 2013–2014, Texas Instruments Incorporated
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8.5.3 Data Read Operation
The device supports two types of read operations: reading user-programmable registers and reading conversion
results.
8.5.3.1 Reading User-Programmable Registers
The device supports a readback option for all user-programmable registers: CFR, REFDAC_A, and REFDAC_B.
Figure 90 shows a detailed timing diagram for this operation.
Frame (F)
Frame (F+1)
Frame (F+2)
Frame (F+3)
CS
1
2
N
1
2
3
4
5
16
48
1
2
1
2
N
15
16
47
48
SCLK
R14
Valid Data
Valid Data
Valid data as per device configuration.
Valid data as per device configuration.
R15
R1
Valid Data
Valid Data
R0
SDO-A
SDO-B
SDI
No change in device
configuration
No change in device
configuration
B14 B13 B12
X
X
X
X
B15
Device configuration for frame (F+3)
Note that N is a function of the device configuration, as described in Table 4.
Figure 90. Register Readback Timing
To readback the user-programmable register settings, the appropriate control word should be transmitted to the
device during frame (F+1), as shown in Table 9. Frame (F+1) must have at least 48 SCLK falling edges.
Table 9. Control Word to Readback User-Programmable Registers
CONTROL WORD TO BE PROGRAMMED IN FRAME (F+1)
USER-PROGRAMMABLE REGISTER
B[15:12] (Binary)
0011b
B[11:0] (Hex)
000h
CFR
REFDAC_A
REFDAC_B
0001b
000h
0010b
000h
Frame (F+2) must have at least 48 SCLK falling edges. During frame (F+2), SDO_A outputs the contents of the
selected user-programmable register on the first 16 SCLK falling edges (as shown in Table 10) and then outputs
0s for any subsequent SCLK falling edges. The SDO_B pin outputs 0s for all the SCLK falling edges.
Table 10. Register Data Read Back
USER-
DATA READ ON SDO-A IN FRAME (F+2)
PROGRAMMABLE
REGISTER
R15
R14
R13
R12 R11
—
R3
R2
R1
R0
CFR
0
0
0
0
0
0
1
0
1
1
1
0
CFG.B11
—
—
—
CFG.B3 CFG.B2
CFG.B1
CFG.B0
REFDAC_A
REFDAC_B
REFDAC_A.D8
REFDAC_B.D8
REFDAC_A.D0
REFDAC_B.D0
0
0
0
0
0
0
Register settings programmed during frame (F+2) determine the device configuration in frame (F+3).
38
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ZHCSCQ1B –OCTOBER 2013–REVISED AUGUST 2014
8.5.3.2 Conversion Data Read
The device provides four different interface modes to the user for reading the conversion result. These modes
offer flexible hardware connections and firmware programming. Table 11 shows how to select one of the four
interface modes.
Table 11. Interface Mode Selection
MINIMUM SCLK FALLING EDGES
CFR.B11
CFR.B10
INTERFACE MODE
REQUIRED TO VALIDATE WRITE
OPERATION N
0
0
1
1
0
1
0
1
32-CLK, dual-SDO mode (default)
32-CLK, single-SDO mode
16-CLK, dual-SDO mode
32
48
16
32
16-CLK, single SDO mode
In the 32-CLK interface modes, the device uses an internal clock to convert the sampled analog signal. The
conversion is completed during the first 16 periods of SCLK and the conversion result can be read on the
subsequent SCLK falling edges. All devices in the family (that is, ADS8353, ADS7853, and ADS7253) support
the 32-CLK interface modes.
In addition to the 32-CLK interface modes, the ADS7853 and ADS7253 also support the 16-CLK interface
modes. By using the 16-CLK interface modes, the same throughput can be achieved at much lower SCLK
speeds.
The following sections detail the various interface modes supported by the device.
8.5.3.2.1 32-CLK, Dual-SDO Mode (CFR.B11 = 0, CFR.B10 = 0, Default)
The 32-CLK, dual-SDO mode is the default mode supported by all devices. This mode can also be selected by
writing CFR.B11 = 0 and CFR.B10 = 0.
In this mode, the SDO_A pin outputs the ADC_A conversion result and the SDO_B pin outputs the ADC_B
conversion result. Figure 91 shows a detailed timing diagram for this mode.
Sample
N
Sample
N + 1
tTHROUGHPUT
tCONV
tACQ
CS
tSCLK
1
2
14
15
16
17
18
25
26
27
28
29
30
31
D1
0
32
SCLK
ADS8353, ADS8354
SDO_A and SDO_B
D15 D14
D13 D12
D11 D10
X
D7
D6
D5
D4
D3
D2
D0
0
D0
Data From Sample N
D5 D4 D3 D2
Data From Sample N
ADS7853, ADS7854
SDO_A and SDO_B
D1
0
0
0
ADS7253, ADS7254
SDO_A and SDO_B
D3
D2
D1
D0
0
Data From Sample N
B15
B14
B2
B1
B0
X
X
X
X
X
X
X
X
X
SDI
Figure 91. 32-CLK, Dual-SDO Mode Timing Diagram
Copyright © 2013–2014, Texas Instruments Incorporated
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ADS8353, ADS7853, ADS7253
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www.ti.com.cn
A CS falling edge brings the serial data bus out of 3-state and also outputs a 0 on the SDO_A and SDO_B pins.
The device converts the sampled analog input during the conversion time (tCONV). SDO_A and SDO_B read 0
during this period. After completing the conversion process, the sample-and-hold circuit returns to sample mode.
The device outputs the MSBs of ADC_A and ADC_B on SDO_A and SDO_B pins, respectively, on the 16th
SCLK falling edge. The subsequent SCLK falling edges are used to shift out the rest of the bits of the conversion
result, as shown in Table 12.
Table 12. Data Launch Edge
LAUNCH EDGE
DEVICE
PINS
CS
↓
SCLK
↓28
CS
↑
↓1
0
—
—
—
—
—
—
—
↓15 ↓16
—
—
—
—
—
—
—
↓27
D4_A
D4_B
D2_A
D2_B
D0_A
D0_B
↓29
D2_A
D2_B
D0_A
D0_B
0
↓30
↓31
↓32 ...
0 ...
0 ...
0 ...
0 ...
0 ...
0 ...
SDO-A
SDO-B
SDO-A
SDO-B
SDO-A
SDO-B
0
0
0
0
0
0
0
D15_A
D3_A
D3_B
D1_A
D1_B
0
D1_A
D0_A
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
ADS8353
ADS7853
ADS7253
0
0
D15_B
D13_A
D13_B
D11_A
D11_B
D1_B
D0_B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
In this mode, at least 32 SCLK falling edges must be given to validate the read or write frame. A CS rising edge
ends the frame and puts the serial bus into 3-state.
Refer to Table 13 for timing specifications specific to this serial interface mode.
Table 13. 32-CLK, Dual-SDO Interface Specific Timing
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TIMING REQUIREMENTS
ADS8353
ADS7853
ADS7253
50
29.4
29.4
ns
ns
ns
ns
tCLK
CLOCK period
tACQ
Acquisition time
33 × tCLK – tCONV
TIMING SPECIFICATIONS
ADS8353
ADS7853
ADS7253
730
450
450
ns
ns
ns
tCONV
Conversion time
40
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ZHCSCQ1B –OCTOBER 2013–REVISED AUGUST 2014
8.5.3.2.2 32-CLK, Single-SDO Mode (CFR.B11 = 0, CFR.B10 = 1)
The 32-CLK, single-SDO mode provides the option of using only one SDO pin (SDO_A) to read conversion
results from both ADCs (ADC_A and ADC_B). SDO_B remains in 3-state and can be treated as a no connect
(NC) pin.
This mode can be selected by writing CFR.B11 = 0 and CFR.B10 = 1. Figure 92 shows a detailed timing diagram
for this mode.
Sample
N
Sample
N+1
tTHROUGHPUT
tCONV
tACQ
CS
1
2
14
15
16
17
28
31
45
47
48
SCLK
18
29
30
32
33
34
44
46
D1
5-A 4-A
D1
D4- D3- D2- D1- D0- D1
D4- D3- D2- D1- D0-
ADS8353, ADS8354
SDO_A
A
A
A
A
A
5-B
B
B
B
B
B
Data From Sample N
D2- D1- D0-
ADS7853, ADS7854
SDO_A
D1
3-A 2-A
D1
D1
3-B
D2- D1- D0-
0
0
0
0
A
A
A
B
B
B
Data From Sample N
D0-
ADS7253, ADS7254
SDO_A
D1
1-A 0-A
D1
D1
1-B
D0-
B
0
0
0
0
0
0
0
0
A
Data From Sample N
All Devices
SDO_B
B15
B14 B3
B2
B1
B0
X
X
X
X
X
X
X
X
X
X
X
X
X
SDI
Figure 92. 32-CLK, Single-SDO Mode Timing Diagram
A CS falling edge brings the serial data bus out of 3-state and also outputs a 0 on the SDO_A pin. The device
converts the sampled analog input during the conversion time (tCONV). SDO_A reads 0 during this period. After
competing the conversion process, the sample-and-hold circuit goes back into sample mode. The device outputs
the MSB of ADC_A on the SDO_A pin on the 16th SCLK falling edge. The subsequent SCLK falling edges are
used to shift out the conversion result of ADC_A followed by the conversion result of ADC_B on the SDO_A pin,
as shown in Table 14.
Table 14. Data Launch Edge
LAUNCH EDGE
DEVICE
PIN
CS
↓
SCLK
CS
↑
↓1
0
—
—
—
—
↓15 ↓16
—
—
—
—
↓27
↓28
↓29
↓30
↓31
↓32
—
—
—
—
↓43
↓44
↓45
↓46
↓47
↓48 ...
0 ...
ADS8353 SDO-A
ADS7853 SDO-A
ADS7253 SDO-A
0
0
0
0
D15_A
D4_A D3_A D2_A D1_A D0_A D15_B
D4_B D3_B D2_B D1_B D0_B
Hi-Z
Hi-Z
Hi-Z
0
0
D13_A
D11_A
D2_A D1_A D0_A
D0_A
0
0
0
0
0
0
D2_B D1_B D0_B
D0_B
0
0
0
0
0 ...
0
0
0
0
0
0
0 ...
In this mode, at least 48 SCLK falling edges must be given to validate the read or write frame. A CS rising edge
ends the frame and puts the serial bus into 3-state.
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Refer to Table 15 for timing specifications specific to this serial interface mode.
Table 15. 32-CLK, Single-SDO Interface Specific Timing
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TIMING REQUIREMENTS
ADS8353
ADS7853
ADS7253
50
29.4
29.4
ns
ns
ns
ns
tCLK
CLOCK period
tACQ
Acquisition time
49 × tCLK – tCONV
TIMING SPECIFICATIONS
ADS8353
ADS7853
ADS7253
730
450
450
ns
ns
ns
tCONV
Conversion time
8.5.3.2.3 16-CLK, Dual-SDO Mode (CFR.B11 = 1, CFR.B10 = 0)
The 16-CLK, dual-SDO mode is designed to support the maximum throughput at lower SCLK frequencies. This
interface mode is not supported by the ADS8353.
For the ADS7853 and ADS7253, this interface mode can be selected by writing CFR.B11 = 1 and CFR.B10 = 0.
In this mode, the SDO_A pin outputs the ADC_A conversion result and the SDO_B pin outputs the ADC_B
conversion result. Figure 93 shows a detailed timing diagram for this mode.
Sample
N
Sample
N + 1
tTHROUGHPUT
tPH_CS
CS
tSCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
tCONV
tACQ
ADS7853, ADS7854
SDO_A and SDO_B
0
0
D13
D11
D12
D10
D11
D9
D10
D8
D9
tCONV
D7
D8
D7
D5
D6
D5
D4
D3
D2
D1
D0
tACQ
ADS7253, ADS7254
SDO_A and SDO_B
0
0
D6
D4
D3
D2
D1
D0
0
0
Data From Sample N
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
SDI
Figure 93. 16-CLK, Dual-SDO Mode Timing Diagram
42
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ZHCSCQ1B –OCTOBER 2013–REVISED AUGUST 2014
A CS falling edge brings the serial data bus out of 3-state and also outputs a 0 on the SDO_A and SDO_B pins.
The subsequent SCLK falling edges are used for conversion and for data transfer using the serial interface, as
shown in Table 16.
The sample-and-hold circuit goes back into sample mode as soon as the conversion process is over.
Table 16. Data Launch Edge
LAUNCH EDGE
DEVICE
PINS
CS
↓
SCLK
↓13
CS
↑
↓1
0
↓2
—
—
—
—
—
↓14
D1_A
D1_B
0
↓15
D0_A
D0_B
0
↓16 ...
0 ...
SDO-A
SDO-B
SDO-A
SDO-B
0
D13_A
D13_B
D11_A
D11_B
D2_A
D2_B
D0_A
D0_B
Hi-Z
Hi-Z
Hi-Z
Hi-Z
ADS7853
ADS7253
0
0
0 ...
0
0
0 ...
0
0
0
0
0 ...
In this mode, at least 16 SCLK falling edges must be given to validate the read or write frame. A CS rising edge
ends the frame and puts the serial bus into 3-state.
Refer to Table 17 for timing specifications specific to this serial interface mode.
Table 17. 16-CLK, Dual-SDO Interface Specific Timing
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TIMING REQUIREMENTS
ADS7853
ADS7253
ADS7853
ADS7253
55.5
55.5
ns
ns
ns
ns
tCLK
CLOCK period
Acquisition time
4 × tCLK
6 × tCLK
tACQ
TIMING SPECIFICATIONS
tCONV Conversion time
ADS7853
ADS7253
14 × tCLK
12 × tCLK
ns
ns
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8.5.3.2.4 16-CLK, Single-SDO Mode (CFR.B11 = 1, CFR.B10 = 1)
The 16-CLK, single-SDO mode provides the option of using only one SDO pin (SDO_A) and a lower-speed clock
to read the conversion results of both ADCs. This interface mode is not supported by the ADS8353.
For the ADS7853 and ADS7253, this mode can be selected by writing CFR.B11 = 1 and CFR.B10 = 1. The
SDO_A pin is used to output the conversion results of both ADCs (ADC_A and ADC_B). SDO_B remains in 3-
state and can be treated as a no connect (NC) pin. Figure 94 shows a detailed timing diagram for this mode.
Sample
N
Sample
N+1
tTHROUGHPUT
tPH_CS
CS
tSCLK
1
2
3
4
5
14
15
16
17
18
19
20
21
30
31
13
SCLK
32
tCONV
tACQ
ADS7853, ADS7854
SDO_A
D13- D12- D11-
D13- D12- D11-
0
0
D2-A D1-A D0-A
0
0
D2-B D1-B
D0-B
D3-A
D1-A
A
A
A
B
B
B
tCONV
tACQ
ADS7253, ADS7254
SDO_A
D11- D10-
D11- D10-
0
0
D9-A
D0-A
0
0
0
0
D9-B D0-B
0
0
A
A
B
B
Data From Sample N
All Devices
SDO_B
B15
B14
B13
B12
B3
B2
B1
B0
X
X
X
X
X
X
X
X
SDI
Figure 94. 16-CLK, Single-SDO Mode Timing Diagram
A CS falling edge brings the serial data bus out of 3-state and also outputs a 0 on the SDO_A pin. The
subsequent SCLK falling edges are used for conversion and for data transfer using the serial interface, as shown
in Table 18.
The sample-and-hold circuit goes back into sample mode as soon as the conversion process is over.
Table 18. Data Launch Edge
LAUNCH EDGE
DEVICE
PIN
CS
↓
SCLK
CS
↑
↓1 ↓2
—
—
—
↓13
D2_A D1_A
D0_A
↓14
↓15
D0_A
0
↓16 ↓17 ↓18
—
—
—
↓29
D2_B D1_B
D0_B
↓30
↓31
D0_B
0
↓32 ...
0 ...
ADS7853
ADS7253
SDO-A
SDO-A
0
0
0
D13_A
D11_A
0
0
0
0
D13_B
D11_B
Hi-Z
Hi-Z
0
0
0
0 ...
44
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In this mode, at least 32 SCLK falling edges must be given to validate the read/write frame. A CS rising edge
ends the frame and puts the serial bus into 3-state.
Refer to Table 19 for timing specifications specific to this serial interface mode.
Table 19. 16-CLK, Single-SDO Interface Specific Timing
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TIMING REQUIREMENTS
ADS7853
ADS7253
ADS7853
ADS7253
55.5
55.5
ns
ns
ns
ns
tCLK
CLOCK period
Acquisition time
19 × tCLK
21 × tCLK
tACQ
TIMING SPECIFICATIONS
tCONV Conversion time
ADS7853
ADS7253
14 × tCLK
12 × tCLK
ns
ns
8.5.4 Low-Power Modes
In normal mode of operation, all internal circuits of the device are always powered up and the device is always
ready to commence a new conversion. This mode enables the device to support the rated throughput. The
device also supports two low-power modes to optimize the power consumption at lower throughputs: STANDBY
mode and software power-down (SPD) mode.
8.5.4.1 STANDBY Mode
The device supports a STANDBY mode of operation where some of the internal circuits of the device are
powered down. However, if bit 6 in configuration register is set to 1 (CFR.B6 = 1), then the internal reference is
not powered down and the contents of the REFDAC_A and REFDAC_B registers are retained to enable faster
power-up to a normal mode of operation.
As shown in Figure 95, a valid write operation in frame (F) to program the configuration register with B5 set to 1
(CFR.B5 = 1) places the device into a STANDBY mode of operation on the following CS rising edge. While in
STANDBY mode, SDO_A and SDO_B output all 1s when CS is low and remain in 3-state when CS is high.
To remain in STANDBY mode, SDI must remain low in the subsequent frames.
Device enters
STANDBY mode
Frame (F)
Frame (F+1)
Device in
STANDBY mode
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
2
N
SCLK
16
SDO-A and
SDO-B
Valid Data as per device configuration
CFG.B[5] = 1
SDI
CFG.B[4:0] = 00000b
CFG.B[15:12] = 1000b
CFG.B[11:6]
Note that N is a function of the device configuration, as described in Table 4.
Figure 95. Enter STANDBY Mode
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As shown in Figure 96, a valid write operation in frame (F+3) by writing the configuration register with B5 set to 0
(CFR.B5 = 0) brings the device out of STANDBY mode on the following CS rising edge. Frame (F+3) must have
at least 48 SCLK falling edges.
After exiting the STANDBY mode, a delay of tPU_STDBY must elapse for the internal circuits to fully power-up and
resume normal operation in frame (F+4). Device configuration for frame (F+4) is determined by the status of the
CFR.B[11:6] bits programmed during frame (F+3).
Frame (F+2)
Frame (F+3)
Device exits
STANDBY mode
Frame (F+4)
Device in
STANDBY
mode
tPU_STDBY
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
2
15
16
N
SCLK
16
48
SDO-A
and
SDO-B
Valid Data as per device configuration
CFG settings for Frame (F+5)
These bits set device
configuration for Frame (F+4)
CFG.B[5] = 0
SDI
CFG.B[15:12] = 1000b
CFG.B[11:6]
CFG.B[4:0] = 00000b
Note that N is a function of the device configuration, as described in Table 4.
Figure 96. Exit STANDBY Mode
Refer to the Timing Characteristics: Serial Interface for timing specifications for this operating mode.
46
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8.5.4.2 Software Power-Down (SPD) Mode
In software power-down (SPD) mode, all internal circuits (including the internal references) are powered down.
However, the contents of the REFDAC_A and REFDAC_B registers are retained.
As shown in Figure 97, to enter SPD mode, the device must be selected (by bringing CS low) and SDI must be
kept high for a minimum of 48 SCLK cycles during frame (F). The device goes to SPD on the CS rising edge
following frame (F). While in SPD mode, SDO_A and SDO_B go to 3-state irrespective of the status of the CS
signal.
To remain in SPD mode, SDI must remain high in subsequent frames.
Device enters SPD
Frame (F)
Frame (F+1)
mode
Device in SPD
mode
CS
1
2
3
47
1
2
SCLK
48
SDO-A and
SDO-B
Valid Data as per device configuration
SDI
Figure 97. Enter SPD Mode
As shown in Figure 98, to exit SPD mode, the device must be selected (by bringing CS low) and SDI must be
kept low for a minimum of 48 SCLK cycles during frame (F+3). The device starts powering-up on a CS rising
edge following frame (F+3). After frame (F+3), a delay of tPU_SPD must elapse before programming the
configuration register.
A valid write operation in frame (F+4) sets the device configuration for frame (F+5). Frame (F+4) must have at
least 48 SCLK falling edges. The output data in frame (F+4) should be discarded.
Frame (F+2)
Frame (F+3)
Frame (F+4)
Frame (F+5)
Device exits
SPD
tPU_SPD
Device in
SPD
CS
SCLK
1
2
47
48
1
2
15
16
48
1
2
15
16
N
SDO-A
and
SDO-B
Invalid Data
Valid Data as per device configuration
CFG settings for Frame (F+6)
SDI
CFG settings for Frame (F+5)
Note that N is a function of the device configuration, as described in Table 4.
Figure 98. Exit SPD Mode
Refer to the Timing Characteristics: Serial Interface for timing specifications for this operating mode.
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8.5.5 Frame Abort, Reconversion, or Short-Cycling
As discussed in Figure 99, the minimum number of SCLK falling edges (N) that must be provided between the
beginning and end of the frame depends on the serial interface mode. The SCLK falling edges (N) program the
device and retrieve the conversion result. If CS is brought high before the expected number of SCLK falling
edges are provided, the current frame is aborted and the device starts sampling the new analog input signal.
If frame (F) is aborted, then the register write operation attempted in frame (F) is considered invalid and the
internal registers are not updated. The device continues to have the same configuration in frame (F+1) from
frame (F).
The output data bits latched before the CS rising edge are still valid data that correspond to sample N.
tPL_CS
tPH_CS_SHRT
CS
1
2
SCLK
SDO
Sample
Sample
N + 1
N
tCONV
tACQ
tPH_CS_SHRT
CS
22
V
23
V
1
2
13
14
15
16
V
17
V
24
V
SCLK
SDO
Data From Sample N
Figure 99. Frame Abort, Reconversion, or Short-Cycling Feature
Refer to the Timing Characteristics: Serial Interface for timing specifications for this operating mode.
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9 Application and Implementation
9.1 Application Information
The two primary circuits required to maximize the performance of a high-precision, successive approximation
register (SAR), analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This
section details some general principles for designing these circuits, and some application circuits designed using
these devices.
The device supports operation either with an internal or external reference source. Refer to the Reference
section for details about the decoupling requirements.
The reference source to the ADC must provide low-drift and very accurate dc voltage and support the dynamic
charge requirements without affecting the noise and linearity performance of the device. The output broadband
noise (typically in the order of a few 100 μVRMS) of the reference source must be appropriately filtered by using a
low-pass filter with a cutoff frequency of a few hundred hertz. After band-limiting the noise from the reference
source, the next important step is to design a reference buffer that can drive the dynamic load posed by the
reference input of the ADC. At the start of each conversion, the reference buffer must regulate the voltage of the
reference pin within 1 LSB of the intended value. This condition necessitates the use of a large filter capacitor at
the reference pin of the ADC. The amplifier selected to drive the reference input pin must be stable while driving
this large capacitor and should have low output impedance, low offset, and temperature drift specifications. To
reduce the dynamic current requirements and crosstalk between the channels, a separate reference buffer is
recommended for driving the reference input of each ADC channel.
The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and a fly-wheel
RC filter. The amplifier is used for signal conditioning of the input voltage and its low output impedance provides
a buffer between the signal source and the switched capacitor inputs of the ADC. The RC filter helps attenuate
the sampling charge injection from the switched-capacitor input stage of the ADC and functions as an antialiasing
filter to band-limit the wideband noise contributed by the front-end circuit. Careful design of the front-end circuit is
critical to meet the linearity and noise performance of a high-precision ADC.
9.1.1 Input Amplifier Selection
Selection criteria for the input amplifiers is highly dependent on the input signal type and the performance goals
of the data acquisition system. Some key amplifier specifications to consider while selecting an appropriate
amplifier to drive the inputs of the ADC are:
•
Small-signal bandwidth. Select the small-signal bandwidth of the input amplifiers to be as high as possible
after meeting the power budget of the system. Higher bandwidth reduces the closed-loop output impedance
of the amplifier, thus allowing the amplifier to more easily drive the low cutoff frequency RC filter at the ADC
inputs. Higher bandwidth also minimizes the harmonic distortion at higher input frequencies. In order to
maintain the overall stability of the input driver circuit, the amplifier bandwidth should be selected as
described in Equation 6:
§
·
1
¨
¨
¸
¸
Unity ꢁ Gain Bandwidth t 4u
2S
u(RFLT ꢀ RFLT )uCFLT
©
¹
(6)
•
Noise. Noise contribution of the front-end amplifiers should be as low as possible to prevent any degradation
in SNR performance of the system. As a rule of thumb, to ensure that the noise performance of the data
acquisition system is not limited by the front-end circuit, the total noise contribution from the front-end circuit
should be kept below 20% of the input-referred noise of the ADC. Noise from the input driver circuit is band-
limited by designing a low cutoff frequency RC filter and is calculated by Equation 7:
2
SNR
ꢀ
dB
ꢁ
§
¨
·
¸
V
§
¨
·
¸
ꢂ
1
_ AMP_PP
S
2
1
5
VREF
2
20
ꢃ en2_RMS
u
u fꢂ3dB
d
u
u10
f
©
¹
NG u 2 u
¨
¨
¸
¸
6.6
©
¹
where:
•
•
•
•
V1 / f_AMP_PP is the peak-to-peak flicker noise in µV,
en_RMS is the amplifier broadband noise density in nV/√Hz,
f–3dB is the 3-dB bandwidth of the RC filter, and
NG is the noise gain of the front-end circuit, which is equal to 1 in a buffer configuration.
(7)
49
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Application Information (continued)
•
•
Distortion. Both the ADC and the input driver introduce nonlinearity in a data acquisition block. As a rule of
thumb, to ensure that the distortion performance of the data acquisition system is not limited by the front-end
circuit, the distortion of the input driver should be at least 10 dB lower than the distortion of the ADC, as
shown in Equation 8.
THDAMP d THDADC ꢂ 10
dB
(8)
Settling Time. For dc signals with fast transients that are common in a multiplexed application, the input signal
must settle to the desired accuracy at the inputs of the ADC during the acquisition time window. This
condition is critical to maintain the overall linearity performance of the ADC. Typically, the amplifier data
sheets specify the output settling performance only up to 0.1% to 0.001%, which may not be sufficient for the
desired accuracy. Therefore, the settling behavior of the input driver should always be verified by TINA™-
SPICE simulations before selecting the amplifier.
9.1.2 Antialiasing Filter
Converting analog-to-digital signals requires sampling an input signal at a constant rate. Any higher frequency
content in the input signal beyond half the sampling frequency is digitized and folded back into the low-frequency
spectrum. This process is called aliasing. Therefore, an analog, antialiasing filter must be used to remove the
harmonic content from the input signal before being sampled by the ADC. An antialiasing filter is designed as a
low-pass, RC filter, for which the 3-dB bandwidth is optimized based on specific application requirements. For dc
signals with fast transients (including multiplexed input signals), a high-bandwidth filter is designed to allow
accurately settling the signal at the ADC inputs during the small acquisition time window. For ac signals, the filter
bandwidth should be kept low to band-limit the noise fed into the ADC input, thereby increasing the signal-to-
noise ratio (SNR) of the system.
A filter capacitor, CFLT, connected across the ADC inputs (as shown in Figure 100), filters the noise from the
front-end drive circuitry, reduces the sampling charge injection and provides a charge bucket to quickly charge
the internal sample-and-hold capacitors during the acquisition process. As a rule of thumb, the value of this
capacitor should be at least 10 times the specified value of the ADC sampling capacitance. For these devices,
the input sampling capacitance is equal to 40 pF. Thus, the value of CFLT should be greater than 400 pF. The
capacitor should be a COG- or NPO-type because these capacitor types have a high-Q, low-temperature
coefficient, and stable electrical characteristics under varying voltages, frequency, and time.
Note that driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier
marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of
the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a
result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance,
input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability
and distortion of the design. For these devices, TI recommends limiting the value of RFLT to a maximum of 22 Ω
in order to avoid any significant degradation in linearity performance. The tolerance of the selected resistors can
be chosen as 1% because the use of a differential capacitor at the input balances the effects resulting from any
resistor mismatch.
RFLT ꢀ22 ꢀꢀ
AINP
1
ADS8353
ADS7853
ADS7253
fꢃ3dB
CFLT ꢀꢀ400 pF
2S u
ꢀ
RFLT ꢂ RFLT u CFLT
ꢁ
AINM
GND
RFLT ꢀ22 ꢀꢀ
Figure 100. Antialiasing Filter
The input amplifier bandwidth should be much higher than the cutoff frequency of the antialiasing filter. TI
strongly recommends performing a SPICE simulation to confirm that the amplifier has more than 40° phase
margin with the selected filter. If an amplifier has less than a 40° phase margin with 22-Ω resistors, using a
different amplifier with higher bandwidth or reducing the filter cutoff frequency with a larger differential capacitor
is advisable.
50
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9.2 Typical Applications
9.2.1 DAQ Circuit to Achieve Maximum SINAD for a 10-kHz Input Signal at Full Throughput
AVDD
VCM
AVDD
OPA836
+
10 ꢀꢀ
+
1 kꢀꢀ
AVDD
-
AINP
AINM
8.2 nF
COG
(NPO)
VIN+
ADSxx53
1kꢀꢀ
GND
10 ꢀꢀ
VDC
Where;
VDC = 0 V for CFR.B7 = 0
VDC = FSR_ADC_x/2 for CFR.B7 = 1
VCM = FSR_ADC_x/2
ADS8353 : 16-bit, 600 kSPS
ADS7853 : 14-bit, 1 MSPS
ADS7253 : 12-bit, 1 MSPS
INPUT DRIVER
NOTE: Only one ADC channel is shown in this diagram. Replicate the same circuit for other ADC channels.
Figure 101. DAQ Circuit: Maximum SINAD for a 10-kHz Input Signal at Full Throughput, 32-CLK Interface
AVDD
VCM
AVDD
OPA836
+
4 ꢀꢀ
+
1 kꢀꢀ
AVDD
-
AINP
AINM
1.8 nF
COG
(NPO)
VIN+
ADSxx53
1kꢀꢀ
GND
4 ꢀꢀ
VDC
Where;
VDC = 0 V for CFR.B7 = 0
VDC = FSR_ADC_x/2 for CFR.B7 = 1
VCM = FSR_ADC_x/2
ADS7853 : 14-bit, 1 MSPS
ADS7253 : 12-bit, 1 MSPS
INPUT DRIVER
NOTE: Only one ADC channel is shown in this diagram. Replicate the same circuit for other ADC channels.
Figure 102. DAQ Circuit: Maximum SINAD for a 10-kHz Input Signal at Full Throughput, 16-CLK Interface
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Typical Applications (continued)
AVDD
10 µF
AVDD
REF5025,
REF5040,
REF5050(1)
REFGND-A
1 kꢀꢀ
0.1 ꢀꢀ
+
-
ADC_A
AVDD
REFIN-A
1 µF
VOUT
TRIM
Device
AVDD
0.22 ꢀꢀ
1 kꢀꢀ
+
-
REFIN-B
1 µF
10 µF
1 µF
ADC_B
0.1 ꢀꢀ
REFGND-B
10 µF
OPA2350
(1) When using the REF5050, AVDD must be set to 5.5 V.
Figure 103. Reference Drive Circuit
9.2.1.1 Design Requirements
To design an application circuit optimized to achieve target specifications listed in Table 20.
Table 20. Target Specifications
TARGET SPECIFICATIONS
TEST CONDITIONS
INPUT SIGNAL
FREQUENCY
SNR
THD
DEVICE
THROUGHPUT
INTERFACE MODE
> 83 dB
> 81 dB
< -100 dB
< –95 dB
< –85 dB
< –88 dB
< –80 dB
ADS8353
ADS7853
ADS7853
ADS7253
ADS7253
10 kHz
10 kHz
10 kHz
10 kHz
10 kHz
Maximum supported
Maximum supported
Maximum supported
Maximum supported
Maximum supported
32-CLK, dual-SDO
32-CLK, dual-SDO
16-CLK, dual-SDO
32-CLK, dual-SDO
16-CLK, dual-SDO
> 77.5 dB
> 71.5 dB
> 70.5 dB
9.2.1.2 Detailed Design Procedure
Best practice is for the distortion from the input driver to be at least 10 dB less than the ADC distortion. The
distortion resulting from variation in the common-mode signal is eliminated by using the amplifier in an inverting
gain configuration that establishes a fixed common-mode level for the circuit. This configuration also eliminates
the requirement of rail-to-rail swing at the amplifier input. The low-power OPA836, used as an input driver,
provides exceptional ac performance because of its extremely low-distortion and high-bandwidth specifications.
In addition, the components of the antialiasing filter are such that the noise from the front-end circuit is kept low
without adding distortion to the input signal.
The application circuit illustrated in Figure 101 is optimized to achieve the lowest distortion and lowest noise for a
10-kHz input signal fed to the ADS8353 or ADS7853 or ADS7253 operating at full throughput with the default 32-
CLK, dual-SDO interface mode. The input signal is processed through a high-bandwidth, low-distortion amplifier
in an inverting gain configuration and a low-pass RC filter before being fed into the device.
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The ADS7853 and the ADS7253 also support 16-CLK interface modes that achieve the rated throughput rate at
much lower SCLK frequencies. However, when using the 16-CLK interface modes, the device receives less
acquisition time when compared to the 32-CLK interface modes. The application circuit illustrated in Figure 102 is
optimized to achieve the lowest distortion and lowest noise for a 10-kHz input signal fed to the ADS7853 or
ADS7253 operating at full throughput with the 16-CLK, dual-SDO interface mode. The input signal is processed
through a high-bandwidth, low-distortion amplifier in an inverting gain configuration and a low-pass RC filter
before being fed into the device.
Figure 103 illustrates the reference driver circuit when operation with an external reference is desired. The
reference voltage is generated by the high-precision, low-noise REF50xx circuit. The output broadband noise of
the reference is heavily filtered by a low-pass filter with a 3-dB cutoff frequency of 160 Hz. The decoupling
capacitor on each reference pin is selected to be 10 µF. The low output impedance, low noise, and fast settling
time makes the OPA2350 a good choice for driving this high capacitive load.
9.2.1.3 Application Curves
To minimize external components and to maximize the dynamic range of the ADC, device is configured to
operate with internal reference (CFR.B6 = 1) and 2 x VREF_x input full scale range (CFR.B9 = 1).
Figure 104, Figure 105, and Figure 106, show the FFT plots and test results obtained with the ADS8353,
ADS7853, and ADS7253, respectively, operating at full throughput with a 32-CLK interface and the circuit
configuration of Figure 101.
0
±20
0
±30
±40
±60
±80
±60
±100
±120
±140
±160
±180
±200
±90
±120
±150
0
60
120
180
240
300
0
100
200
300
400
500
C301
Input Frequency (kHz)
Input Frequency (kHz)
C003
SNR = 83.5 dB
THD = –101.2 dB
fIN = 10.1 kHz
SNR = 82.1 dB
THD = –98.2 dB
fIN = 10.1 kHz
Figure 104. ADS8353 in 32-CLK Interface Mode
Figure 105. ADS7853 in 32-CLK Interface Mode
0
±30
±60
±90
±120
±150
0
100
200
300
400
500
C001
Input Frequency (kHz)
SNR = 72.5 dB
THD = –94.2 dB
Figure 106. ADS7253 in 32-CLK Interface Mode
fIN = 10.1 kHz
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Figure 107 and Figure 108 show the FFT plots and test results obtained with the ADS7853 and ADS7253,
respectively, operating at full throughput with 16-CLK interface and the circuit configuration of Figure 102.
0
±30
0
±30
±60
±60
±90
±90
±120
±150
±120
±150
0
100
200
300
400
500
0
100
200
300
400
500
Input Frequency (kHz)
C002
Input Frequency (kHz)
C004
SNR = 78.1 dB
THD = –89.8 dB
fIN = 10.1 kHz
SNR = 71.2 dB
THD = –84.9 dB
fIN = 10.1 kHz
Figure 107. ADS7853 in 16-CLK Interface Mode
Figure 108. ADS7253 in 16-CLK Interface Mode
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9.2.2 DAQ Circuit to Achieve Maximum SINAD for a 100-kHz Input Signal at Full Throughput
+15 V
VCM
AVDD
THS4032
+
4.7 ꢀ
602 ꢀ
AVDD
-
AINP
1 nF
COG
(NPO)
VIN+
ADSxx53
-15 V
602 ꢀ
AINM
GND
10 pF
4.7 ꢀ
+15 V
VDC
+
THS4032
-
-15 V
ADS8353 : 16-bit, 600 kSPS
ADS7853 : 14-bit, 1 MSPS
ADS7253 : 12-bit, 1 MSPS
Where;
VDC = 0 V for CFR.B7 = 0
VDC = FSR_ADC_x/2 for CFR.B7 = 1
VCM = FSR_ADC_x/2
INPUT DRIVER
NOTE: Only one ADC channel is shown in this diagram. Replicate the same circuit for other ADC channels.
Figure 109. DAQ Circuit: Maximum SINAD for a 100-kHz Input Signal at Full Throughput
AVDD
10 µF
AVDD
REF5025,
REF5040,
REF5050(1)
REFGND-A
1 kꢀꢀ
0.1 ꢀꢀ
+
-
ADC_A
AVDD
REFIN-A
1 µF
VOUT
TRIM
Device
AVDD
0.22 ꢀꢀ
1 kꢀꢀ
+
-
REFIN-B
1 µF
10 µF
1 µF
ADC_B
0.1 ꢀꢀ
REFGND-B
10 µF
OPA2350
(1) When using the REF5050, AVDD must be set to 5.5 V.
Figure 110. Reference Drive Circuit
Copyright © 2013–2014, Texas Instruments Incorporated
55
ADS8353, ADS7853, ADS7253
ZHCSCQ1B –OCTOBER 2013–REVISED AUGUST 2014
www.ti.com.cn
9.2.2.1 Design Requirements
To design an application circuit optimized to achieve target specifications listed in Table 21.
Table 21. Target Specifications
TARGET SPECIFICATIONS
TEST CONDITIONS
INPUT SIGNAL
FREQUENCY
SNR
THD
DEVICE
THROUGHPUT
INTERFACE MODE
> 83 dB
> 78.5 dB
> 77.5 dB
> 71.5 dB
> 71 dB
< -95 dB
< –88 dB
< –85 dB
< –85 dB
< –84 dB
ADS8353
ADS7853
ADS7853
ADS7253
ADS7253
100 kHz
100 kHz
100 kHz
100 kHz
100 kHz
Maximum supported
Maximum supported
Maximum supported
Maximum supported
Maximum supported
32-CLK, dual-SDO
32-CLK, dual-SDO
16-CLK, dual-SDO
32-CLK, dual-SDO
16-CLK, dual-SDO
9.2.2.2 Detailed Design Procedure
Best practice is for the distortion from the input driver to be at least 10 dB less than the ADC distortion. The
distortion resulting from variation in the common-mode signal is eliminated by using the amplifier in an inverting
gain configuration that establishes a fixed common-mode level for the circuit. This configuration also eliminates
the requirement of rail-to-rail swing at the amplifier input. The low-power OPA836, used as an input driver,
provides exceptional ac performance because of its extremely low-distortion and high-bandwidth specifications.
In addition, the components of the antialiasing filter are such that the noise from the front-end circuit is kept low
without adding distortion to the input signal. To take full advantage of the pseudo-differential input structure of the
ADC, the AINM pin must be driven to the appropriate VDC with the same amplifier and matching source
impedance.
The application circuit illustrated in Figure 109 is optimized to achieve the lowest distortion and lowest noise for a
100-kHz input signal fed to the ADS8353 or ADS7853 or ADS7253 operating at full throughput. The THS4032,
used as an input driver, provides exceptional ac performance because of its extremely low-distortion, low-noise,
and high-bandwidth specifications. In addition, the components of the antialiasing filter are such that the noise
from the front-end circuit is kept low without adding distortion to the input signal. External clamp circuit may be
required to ensure that the inputs to the device do not exceed AVDD.
Figure 103 illustrates the reference driver circuit when operation with an external reference is desired. The
reference voltage is generated by the high-precision, low-noise REF50xx circuit. The output broadband noise of
the reference is heavily filtered by a low-pass filter with a 3-dB cutoff frequency of 160 Hz. The decoupling
capacitor on each reference pin is selected to be 10 µF. The low output impedance, low noise, and fast settling
time makes the OPA2350 a good choice for driving this high capacitive load.
56
Copyright © 2013–2014, Texas Instruments Incorporated
ADS8353, ADS7853, ADS7253
www.ti.com.cn
ZHCSCQ1B –OCTOBER 2013–REVISED AUGUST 2014
9.2.2.3 Application Curves
To minimize external components and to maximize the dynamic range of the ADC, device is configured to
operate with internal reference (CFR.B6 = 1) and 2 x VREF_x input full scale range (CFR.B9 = 1).
Figure 111, Figure 112, and Figure 113 show the FFT plots and test results obtained with the ADS8353,
ADS7853 and ADS7253, respectively, operating at full throughput with a 32-CLK interface and the circuit
configuration of Figure 109.
0
0
±20
±40
±30
±60
±80
±60
±100
±120
±90
±140
±160
±120
±180
±200
±150
0
60
120
180
240
300
0
100
200
300
400
500
C303
C007
Input Frequency (kHz)
Input Frequency (dB)
SNR = 83.1 dB
THD = –95.5 dB
fIN = 100.2 kHz
SNR = 79.6 dB
THD = –90.9 dB
fIN = 100.2 kHz
Figure 111. ADS8353 in 32-CLK Interface Mode
Figure 112. ADS7853 in 32-CLK Interface Mode
0
±30
±60
±90
±120
±150
0
100
200
300
400
500
Input Frequency (kHz)
C005
SNR = 72.9 dB
THD = –85.8 dB
Figure 113. ADS7253 in 32-CLK Interface Mode
fIN = 100.2 kHz
Copyright © 2013–2014, Texas Instruments Incorporated
57
ADS8353, ADS7853, ADS7253
ZHCSCQ1B –OCTOBER 2013–REVISED AUGUST 2014
www.ti.com.cn
Figure 114 and Figure 115 show the FFT plots and test results obtained with the ADS7853 and ADS7253,
respectively, operating with a 16-CLK interface and the circuit configuration of Figure 109.
0
±30
0
±30
±60
±60
±90
±90
±120
±150
±120
±150
0
100
200
300
400
500
0
100
200
300
400
500
Input Frequency (kHz)
Input Frequency (kHz)
C008
C006
SNR = 78.2 dB
THD = –87.2 dB
fIN = 100.2 kHz
SNR = 72.3 dB
THD = –84.3 dB
fIN = 100.2 kHz
Figure 114. ADS7853 in 16-CLK Interface Mode
Figure 115. ADS7253 in 16-CLK Interface Mode
58
Copyright © 2013–2014, Texas Instruments Incorporated
ADS8353, ADS7853, ADS7253
www.ti.com.cn
ZHCSCQ1B –OCTOBER 2013–REVISED AUGUST 2014
10 Power-Supply Recommendations
The devices have two separate power supplies: AVDD and DVDD. The device operates on AVDD; DVDD is
used for the interface circuits. AVDD and DVDD can be independently set to any value within the permissible
ranges.
When using the device with 2 × VREF input range (CFR.B9 = 1), the AVDD supply voltage value defines the
permissible voltage swing on the analog input pins. To avoid saturation of output codes, and to use the full
dynamic range on the analog input pins, AVDD must be set as shown in Equation 9, Equation 10, and
Equation 11:
AVDD ≥ 2 × VREF_A
AVDD ≥ 2 × VREF_B
4.75 V ≤ AVDD ≤ 5.25 V
(9)
(10)
(11)
Decouple the AVDD and DVDD pins with the GND pin using individual 10-µF decoupling capacitors, as shown in
Figure 116.
AVDD
AVDD (pin 14)
GND (pin 13)
DVDD (pin 7)
10 PF
10 PF
DVDD
Figure 116. Power-Supply Decoupling
Copyright © 2013–2014, Texas Instruments Incorporated
59
ADS8353, ADS7853, ADS7253
ZHCSCQ1B –OCTOBER 2013–REVISED AUGUST 2014
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
Figure 117 shows a board layout example for the ADS8353, ADS7853, and ADS7253 with the WQFN package.
Use a ground plane underneath the device and partition the PCB into analog and digital sections. Avoid crossing
digital lines with the analog signal path and keep the analog input signals and the reference input signals away
from noise sources. As shown in Figure 117, the analog input and reference signals are routed on the left side of
the board and the digital connections are routed on the right side of the device.
The power sources to the device must be clean and well-bypassed. Use 10-μF, ceramic bypass capacitors in
close proximity to the analog (AVDD) and digital (DVDD) power-supply pins. Avoid placing vias between the
AVDD and DVDD pins and the bypass capacitors. Connect all ground pins to the ground plane using short, low
impedance paths.
The REFIO-A and REFIO-B reference inputs and outputs are bypassed with 10-μF, X7R-grade, 0805-size, 16-V
rated ceramic capacitors (CREF-x). Place the reference bypass capacitors as close as possible to the reference
REFIO-x pins and connect the bypass capacitors using short, low-inductance connections. Avoid placing vias
between the REFIO-x pins and the bypass capacitors. Small 0.1-Ω to 0.2-Ω resistors (RREF-x) are used in series
with the reference bypass capacitors to improve stability.
The fly-wheel RC filters are placed immediately next to the input pins. Among ceramic surface-mount capacitors,
COG (NPO) ceramic capacitors provide the best capacitance precision. The type of dielectric used in COG
(NPO) ceramic capacitors provides the most stable electrical properties over voltage, frequency, and temperature
changes. Figure 117 shows CIN-A and CIN-B filter capacitors placed across the analog input pins of the device.
11.2 Layout Example
AVDD
GND
CREF-A
CIN-A
CAVDD
GND
SDO-A
SDO-B
SCLK
/CS
REFIO-A
GND
GND
REFGND-A
REFGND-B
GND
REFIO-B
GND
CDVDD
CREF-B
CIN-B
DVDD
GND
GND
Figure 117. Recommended Layout
60
Copyright © 2013–2014, Texas Instruments Incorporated
ADS8353, ADS7853, ADS7253
www.ti.com.cn
ZHCSCQ1B –OCTOBER 2013–REVISED AUGUST 2014
12 器件和文档支持
12.1 相关链接
以下表格列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买
链接。
Table 22. 相关链接
部件
产品文件夹
请单击此处
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
请单击此处
ADS8353
ADS7853
ADS7253
12.2 相关文档ꢀ
•
TIPD117 验证设计参考指南：针对电机控制应用中光学编码器的 12 位 1MSPS 单电源双通道数据采集系统参
考设计，SLAU517。
•
•
•
•
REF5050 数据表，SBOS410。
OPA2350 数据表，SBOS099。
OPA836、OPA2836 数据表，SLOS712。
THS4032 数据表，SLOS224。
12.3 Trademarks
TINA is a trademark of Texas Instruments Inc..
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
13 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
Copyright © 2013–2014, Texas Instruments Incorporated
61
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS7253IPW
ADS7253IPWR
ADS7253IRTER
ADS7253IRTET
ADS7853IPW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
WQFN
WQFN
TSSOP
TSSOP
WQFN
WQFN
TSSOP
TSSOP
WQFN
WQFN
PW
PW
16
16
16
16
16
16
16
16
16
16
16
16
90
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
ADS7253
2000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
ADS7253
7253
RTE
RTE
PW
250
90
RoHS & Green
RoHS & Green
7253
ADS7853
ADS7853
7853
ADS7853IPWR
ADS7853IRTER
ADS7853IRTET
ADS8353IPW
PW
2000 RoHS & Green
3000 RoHS & Green
RTE
RTE
PW
250
90
RoHS & Green
RoHS & Green
7853
ADS8353
ADS8353
8353
ADS8353IPWR
ADS8353IRTER
ADS8353IRTET
PW
2000 RoHS & Green
3000 RoHS & Green
RTE
RTE
250
RoHS & Green
8353
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS7253IPWR
ADS7253IRTER
ADS7253IRTET
ADS7853IPWR
ADS7853IRTER
ADS7853IRTET
ADS8353IPWR
ADS8353IRTER
ADS8353IRTET
TSSOP
WQFN
WQFN
TSSOP
WQFN
WQFN
TSSOP
WQFN
WQFN
PW
RTE
RTE
PW
16
16
16
16
16
16
16
16
16
2000
3000
250
330.0
330.0
180.0
330.0
330.0
180.0
330.0
330.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
6.9
3.3
3.3
6.9
3.3
3.3
6.9
3.3
3.3
5.6
3.3
3.3
5.6
3.3
3.3
5.6
3.3
3.3
1.6
1.1
1.1
1.6
1.1
1.1
1.6
1.1
1.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q2
Q2
Q1
Q2
Q2
Q1
Q2
Q2
2000
3000
250
RTE
RTE
PW
2000
3000
250
RTE
RTE
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS7253IPWR
ADS7253IRTER
ADS7253IRTET
ADS7853IPWR
ADS7853IRTER
ADS7853IRTET
ADS8353IPWR
ADS8353IRTER
ADS8353IRTET
TSSOP
WQFN
WQFN
TSSOP
WQFN
WQFN
TSSOP
WQFN
WQFN
PW
RTE
RTE
PW
16
16
16
16
16
16
16
16
16
2000
3000
250
367.0
367.0
210.0
367.0
367.0
210.0
367.0
367.0
210.0
367.0
367.0
185.0
367.0
367.0
185.0
367.0
367.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
2000
3000
250
RTE
RTE
PW
2000
3000
250
RTE
RTE
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ADS7253IPW
ADS7853IPW
ADS8353IPW
PW
PW
PW
TSSOP
TSSOP
TSSOP
16
16
16
90
90
90
530
530
530
10.2
10.2
10.2
3600
3600
3600
3.5
3.5
3.5
Pack Materials-Page 3
GENERIC PACKAGE VIEW
RTE 16
3 x 3, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225944/A
www.ti.com
PACKAGE OUTLINE
RTE0016D
WQFN - 0.8 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.15
2.85
A
B
PIN 1 INDEX AREA
3.15
2.85
C
0.8
0.7
SEATING PLANE
0.08 C
0.05
0.00
2X 1.5
SYMM
(0.2) TYP
5
8
EXPOSED
THERMAL PAD
4
9
SYMM
17
2X 1.5
0.8 0.1
12X 0.5
1
12
PIN 1 ID
0.30
0.18
16X
16
13
0.5
0.3
0.1
C A B
16X
0.05
4219118/A 11/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTE0016D
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
0.8)
SYMM
SEE SOLDER MASK
DETAIL
16
13
16X (0.6)
12
16X (0.24)
1
17
SYMM
(2.8)
12X (0.5)
(R0.05) TYP
4
9
(
0.2) TYP
VIA
5
8
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219118/A 11/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTE0016D
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
0.76)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
12X (0.5)
(2.8)
9
4
(R0.05) TYP
5
8
SYMM
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 17
90% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219118/A 11/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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