ADS8371IPFBTG4 [TI]
ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE;
| 型号： | ADS8371IPFBTG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE 转换器 |
| 文件： | 总29页 (文件大小：959K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
B
u
r
r
Ć
B
r
o
w
n
P
r
o
d
u
c
t
s
f
r
o
m
T
e
x
a
s
I
n
s
t
r
u
m
e
n
t
s
ADS8406
SLAS426A–AUGUST 2004–REVISED DECEMBER 2004
16-BIT, 1.25 MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICRO POWER
SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE
FEATURES
APPLICATIONS
•
•
•
DWDM
Instrumentation
High-Speed, High-Resolution, Zero Latency
Data Acquisition Systems
•
Pseudo-Bipolar, Fully Differential Input, -VREF
to VREF
•
•
•
•
•
•
•
•
•
•
•
16-Bit NMC at 1.25 MSPS
±2 LSB INL Max, -1/+1.25 LSB DNL
90 dB SNR, -95 dB THD at 100 kHz Input
Zero Latency
•
•
•
Transducer Interface
Medical Instruments
Communications
Internal 4.096 V Reference
High-Speed Parallel Interface
Single 5 V Analog Supply
Wide I/O Supply: 2.7 V to 5.25 V
Low Power: 155 mW at 1.25 MHz Typ
Pin Compatible With ADS8412/8402
48-Pin TQFP Package
DESCRIPTION
The ADS8406 is a 16-bit, 1.25 MHz A/D converter
with an internal 4.096-V reference. The device in-
cludes a 16-bit capacitor-based SAR A/D converter
with inherent sample and hold. The ADS8406 offers a
full 16-bit interface and an 8-bit option where data is
read using two 8-bit read cycles.
The ADS8406 has a pseudo-bipolar, fully differential
input. It is available in a 48-lead TQFP package and
is characterized over the industrial -40°C to 85°C
temperature range.
High Speed SAR Converter Family
Type/Speed
500 kHz
ADS8383
580 kHz
ADS8381
750 MHZ
1.25 MHz
2 MHz
3 MHz
4 MHz
18 Bit Pseudo-Diff
ADS8371
ADS8401
ADS8411
16 Bit Pseudo-Diff
ADS8405
ADS8402
ADS8406
ADS7890 (S)
ADS8412
16 Bit Pseudo Bipolar,
Fully Differential
14 Bit Pseudo-Diff
12 Bit Pseudo-Diff
ADS7891
ADS7881
BYTE
16-/8-Bit
Parallel DATA
Output Bus
Output
Latches
and
3-State
Drivers
SAR
+
_
+IN
−IN
CDAC
Comparator
RESET
CONVST
BUSY
CS
REFIN
Conversion
and
Control Logic
4.096-V
Internal
Reference
REFOUT
Clock
RD
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADS8406
www.ti.com
SLAS426A–AUGUST 2004–REVISED DECEMBER 2004
ORDERING INFORMATION(1)
MAXIMUM
INTEGRAL
LINEARITY
(LSB)
MAXIMUM
DIFFERENTIAL
LINEARITY
(LSB)
NO MISSING
PACKAGE
DESIG-
NATOR
TEMPERA-
TURE
RANGE
TRANSPORT
MEDIA
QUANTITY
CODES
RESOLUTION
(BIT)
PACKAGE
TYPE
ORDERING
INFORMATION
MODEL
Tape and reel
250
ADS8406IPFBT
ADS8406IPFBR
ADS8406IBPFBT
ADS8406IBPFBR
48 Pin
TQFP
ADS8406I
–4 to +4
–2 to +2
–2 to +2
15
16
PFB
PFB
–40°C to 85°C
–40°C to 85°C
Tape and reel
1000
Tape and reel
250
48 Pin
TQFP
ADS8406IB
–1 to +1.25
Tape and reel
1000
(1) For the most current specifications and package information, refer to our website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
+IN to AGND
Voltage
–0.4 V to +VA + 0.1 V
–0.4 V to +VA + 0.1 V
–0.3 V to 7 V
–IN to AGND
+VA to AGND
Voltage range
+VBD to BDGND
+VA to +VBD
–0.3 V to 7 V
–0.3 V to 2.55 V
–0.3 V to +VBD + 0.3 V
–0.3 V to +VBD + 0.3 V
–40°C to 85°C
–65°C to 150°C
150°C
Digital input voltage to BDGND
Digital output voltage to BDGND
Operating free-air temperature range
Storage temperature range
TA
Tstg
Junction temperature (TJ max)
Power dissipation
TQFP package
(TJMax - TA)/θJA
86°C/W
θJA thermal impedance
Vapor phase (60 sec)
Infrared (15 sec)
215°C
Lead temperature, soldering
220°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
ADS8406
www.ti.com
SLAS426A–AUGUST 2004–REVISED DECEMBER 2004
SPECIFICATIONS
TA = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1.25 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
(1)
Full-scale input voltage
+IN – (–IN)
–Vref
–0.2
–0.2
Vref
Vref + 0.2
Vref + 0.2
V
V
+IN
–IN
Absolute input voltage
Input capacitance
Input leakage current
SYSTEM PERFORMANCE
Resolution
25
pF
nA
0.5
16
Bits
Bits
ADS8406I
ADS8406IB
ADS8406I
ADS8406IB
ADS8406I
ADS8406IB
ADS8406I
ADS8406IB
ADS8406I
ADS8406IB
15
16
No missing codes
–4
±2
±1
4
2
(2)(3)
INL
DNL
EO
Integral linearity
Differential linearity
Offset error(4)
LSB
LSB
–2
–2
±1
2
–1
±0.5
±1
1.25
2.5
–2.5
–1.5
–0.12
–0.098
mV
mV
±0.5
1.5
0.12
0.098
EG
Gain error(4)(5)
%FS
dB
At dc (0.2 V around Vref/2)
+IN – (–IN) = 1 Vpp at 1 MHz
At 7FFFh output code, +VA
80
80
CMRR Common mode rejection ratio
PSRR
DC Power supply rejection ratio
= 4.75 V to 5.25 V, Vref
4.096 V
=
2
LSB
(4)
SAMPLING DYNAMICS
Conversion time
500
150
650
ns
ns
Acquisition time
Throughput rate
1.25
MHz
ns
Aperture delay
2
25
Aperture jitter
ps
Step response
100
100
ns
Overvoltage recovery
DYNAMIC CHARACTERISTICS
ns
VIN = 8 Vpp at 100 kHz
VIN = 8 Vpp at 500 kHz
VIN = 8 Vpp at 100 kHz
VIN = 8 Vpp at 100 kHz
VIN = 8 Vpp at 100 kHz
VIN = 8 Vpp at 500 kHz
–95
–90
90
88
95
93
5
(6)
THD
SNR
Total harmonic distortion
Signal-to-noise ratio
dB
dB
dB
SINAD Signal-to-noise + distortion
SFDR
Spurious free dynamic range
-3dB Small signal bandwidth
dB
MHz
EXTERNAL VOLTAGE REFERENCE INPUT
Reference voltage at REFIN, Vref
2.5
4.096
500
4.2
V
(7)
Reference resistance
kΩ
(1) Ideal input span, does not include gain or offset error.
(2) LSB means least significant bit
(3) This is endpoint INL, not best fit.
(4) Measured relative to an ideal full-scale input [+IN – (–IN)] of 8.192 V
(5) This specification does not include the internal reference voltage error and drift.
(6) Calculated on the first nine harmonics of the input frequency
(7) Can vary ±20%
3
ADS8406
www.ti.com
SLAS426A–AUGUST 2004–REVISED DECEMBER 2004
SPECIFICATIONS (continued)
TA = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1.25 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INTERNAL REFERENCE OUTPUT
From 95% (+VA) with 1-µF
storage capacitor
Internal reference start-up time
120
ms
Vref
Reference voltage
Source current
Line regulation
Drift
IOUT = 0
4.065
4.096
4.13
10
V
µA
Static load
+VA = 4.75 to 5.25 V
IOUT = 0
0.6
36
mV
PPM/°C
DIGITAL INPUT/OUTPUT
Logic family — CMOS
VIH
VIL
High level input voltage
Low level input voltage
IIH = 5 µA
+VBD – 1
–0.3
+VBD + 0.3
0.8
IIL = 5 µA
V
VOH
VOL
High level output voltage
Low level output voltage
Data format — 2's complement
IOH = 2 TTL loads
IOL = 2 TTL loads
+VBD – 0.6
0
+VBD
0.4
POWER SUPPLY REQUIREMENTS
+VBD
+VA
2.7
3
5
5.25
5.25
34
V
V
Power supply voltage
4.75
Supply current, +VA(8)
Power dissipation(8)
fs = 1.25 MHz
fs = 1.25 MHz
31
mA
mW
PD
TEMPERATURE RANGE
TA Operating free-air temperature
155
170
–40
85
°C
(8) This includes only +VA current. +VBD current is typically 1 mA with 5-pF load capacitance on output pins.
4
ADS8406
www.ti.com
SLAS426A–AUGUST 2004–REVISED DECEMBER 2004
TIMING CHARACTERISTICS
All specifications typical at –40°C to 85°C, +VA = +VBD = 5 V
(1)(2)(3)
PARAMETER
MIN
500
150
TYP
MAX
UNIT
ns
tCONV Conversion time
650
tACQ
tpd1
tpd2
tw1
Acquisition time
ns
CONVST low to BUSY high
40
5
ns
Propagation delay time, end of conversion to BUSY low
Pulse duration, CONVST low
Setup time, CS low to CONVST low
Pulse duration, CONVST high
CONVST falling edge jitter
ns
20
0
ns
tsu1
tw2
ns
20
ns
10
ps
tw3
tw4
Pulse duration, BUSY signal low
Pulse duration, BUSY signal high
Min(tACQ
)
ns
610
ns
Hold time, First data bus data transition (RD low, or CS low for
read cycle, or BYTE input changes) after CONVST low
th1
td1
40
0
ns
ns
Delay time, CS low to RD low (or BUSY low to RD low when CS =
0)
tsu2
tw5
ten
td2
td3
tw6
tw7
Setup time, RD high to CS high
0
ns
ns
ns
ns
ns
ns
ns
Pulse duration, RD low time
50
Enable time, RD low (or CS low for read cycle) to data valid
Delay time, data hold from RD high
Delay time, BYTE rising edge or falling edge to data valid
Pulse duration, RD high
20
20
0
2
20
20
Pulse duration, CS high time
Hold time, last RD (or CS for read cycle ) rising edge to CONVST
falling edge
th2
50
ns
tsu3
th3
Setup time, BYTE transition to RD falling edge
Hold time, BYTE transition to RD falling edge
0
0
ns
ns
Disable time, RD high (CS high for read cycle) to 3-stated data
bus
tdis
td5
20
10
ns
ns
ns
Delay time, end of conversion to MSB data valid
Byte transition setup time, from BYTE transition to next BYTE
transition
tsu4
50
td6
td7
Delay time, CS rising edge to BUSY falling edge
Delay time, BUSY falling edge to CS rising edge
50
50
ns
ns
Setup time, from the falling edge of CONVST (used to start the
valid conversion) to the next falling edge of CONVST (when CS =
0 and CONVST used to abort) or to the next falling edge of CS
(when CS is used to abort)
tsu(AB)
60
500
ns
Setup time, falling edge of CONVST to read valid data (MSB) from
current conversion
tsu5
th4
MAX(tCONV) + MAX(td5
)
ns
ns
Hold time, data (MSB) from previous conversion hold valid from
falling edge of CONVST
MIN(tCONV
)
(1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2.
(2) See timing diagrams.
(3) All timings are measured with 20-pF equivalent loads on all data bits and BUSY pins.
5
ADS8406
www.ti.com
SLAS426A–AUGUST 2004–REVISED DECEMBER 2004
TIMING CHARACTERISTICS
All specifications typical at –40°C to 85°C, +VA = 5 V, +VBD = 3 V(1)(2)(3)
PARAMETER
MIN
500
150
TYP
MAX
650
UNIT
ns
tCONV Conversion time
tACQ
tpd1
tpd2
tw1
Acquisition time
ns
ns
ns
ns
ns
ns
ps
ns
ns
CONVST low to BUSY high
50
10
Propagation delay time, end of conversion to BUSY low
Pulse duration, CONVST low
Setup time, CS low to CONVST low
Pulse duration, CONVST high
CONVST falling edge jitter
20
0
tsu1
tw2
20
10
tw3
tw4
Pulse duration, BUSY signal low
Pulse duration, BUSY signal high
Min(tACQ)
610
Hold time, first data bus transition (RD low, or CS low for read
cycle, or BYTE or BUS 16/16 input changes) after CONVST low
th1
td1
40
0
ns
ns
Delay time, CS low to RD low (or BUSY low to RD low when CS =
0)
tsu2
tw5
ten
td2
td3
tw6
tw7
Setup time, RD high to CS high
0
ns
ns
ns
ns
ns
ns
ns
Pulse duration, RD low
50
Enable time, RD low (or CS low for read cycle) to data valid
Delay time, data hold from RD high
Delay time, BYTE rising edge or falling edge to data valid
Pulse duration, RD high time
30
30
0
2
20
20
Pulse duration, CS high time
Hold time, last RD (or CS for read cycle ) rising edge to CONVST
falling edge
th2
50
ns
tsu3
th3
tdis
td5
Setup time, BYTE transition to RD falling edge
0
0
ns
ns
ns
ns
Hold time, BYTE transition to RD falling edge
Disable time, RD high (CS high for read cycle) to 3-stated data bus
Delay time, end of conversion to MSB data valid
30
20
Byte transition setup time, from BYTE transition to next BYTE
transition
tsu4
50
ns
td6
td7
Delay time, CS rising edge to BUSY falling edge
Delay time, BUSY falling edge to CS rising edge
50
50
ns
ns
Setup time, from the falling edge of CONVST (used to start the
valid conversion) to the next falling edge of CONVST (when CS = 0
and CONVST used to abort) or to the next falling edge of CS
(when CS is used to abort)
tsu(AB)
70
500
ns
Setup time, falling edge of CONVST to read valid data (MSB) from
current conversion
tsu5
th4
MAX(tCONV) + MAX(td5
)
ns
ns
Hold time, data (MSB) from previous conversion hold valid from
falling edge of CONVST
MIN(tCONV
)
(1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2.
(2) See timing diagrams.
(3) All timings are measured with 20-pF equivalent loads on all data bits and BUSY pins.
6
ADS8406
www.ti.com
SLAS426A–AUGUST 2004–REVISED DECEMBER 2004
PIN ASSIGNMENTS
PFB PACKAGE
(TOP VIEW)
36 35 34 33 32 31 30 29 28 27 26 25
24
+VBD
RESET
BYTE
CONVST
RD
+VBD
DB8
DB9
37
38
39
40
41
42
43
44
45
46
47
48
23
22
21
20
19
18
17
16
15
14
13
DB10
DB11
DB12
DB13
DB14
DB15
AGND
AGND
+VA
CS
+VA
AGND
AGND
+VA
REFM
REFM
1
2
3
4
5
6
7
8
9 10 11 12
NC - No connection
7
ADS8406
www.ti.com
SLAS426A–AUGUST 2004–REVISED DECEMBER 2004
Terminal Functions
NAME
NO.
I/O
DESCRIPTION
AGND
5, 8, 11, 12, 14,
15, 44, 45
–
Analog ground
BDGND
BUSY
BYTE
25, 35
36
–
O
I
Digital ground for bus interface digital supply
Status output. High when a conversion is in progress.
39
Byte select input. Used for 8-bit bus reading. 0: No fold back 1: Low byte D[7:0] of the 16 most
significant bits is folded back to high byte of the 16 most significant pins DB[15:8].
CONVST
40
42
I
I
Convert start. The falling edge of this input ends the acquisition period and starts the hold
period.
CS
Chip select. The falling edge of this input starts the acquisition period.
8-Bit Bus
16-Bit Bus
BYTE = 0
D15 (MSB)
D14
Data Bus
BYTE = 0
BYTE = 1
D7
DB15
DB14
DB13
DB12
DB11
DB10
DB9
16
17
18
19
20
21
22
23
26
27
28
29
30
31
32
33
7
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
D15 (MSB)
D14
D6
D13
D5
D13
D12
D4
D12
D11
D3
D11
D10
D2
D10
D9
D1
D9
DB8
D8
D0 (LSB)
All ones
All ones
All ones
All ones
All ones
All ones
All ones
All ones
D8
DB7
D7
D7
DB6
D6
D6
DB5
D5
D5
DB4
D4
D4
DB3
D3
D3
DB2
D2
D1
D2
DB1
D1
DB0
D0 (LSB)
D0 (LSB)
–IN
Inverting input channel
+IN
6
I
Non inverting input channel
No connection
NC
3
–
REFIN
REFM
REFOUT
1
I
Reference input
47, 48
2
I
Reference ground
O
Reference output. Add 1-µF capacitor between the REFOUT pin and REFM pin when internal
reference is used.
RESET
RD
38
41
I
I
Current conversion is aborted and output latches are cleared (set to zeros) when this pin is
asserted low. RESET works independantly of CS.
Synchronization pulse for the parallel output. When CS is low, this serves as the output enable
and puts the previous conversion result on the bus.
+VA
4, 9, 10, 13, 43,
46
–
–
Analog power supplies, 5-V dc
+VBD
24, 34, 37
Digital power supply for bus
8
ADS8406
www.ti.com
SLAS426A–AUGUST 2004–REVISED DECEMBER 2004
TIMING DIAGRAMS
t
w2
t
w1
CONVST
(used in normal
conversion)
t
cycle
CONVST
(used in ABORT)
t
t
su(AB)
su(AB)
t
t
pd1
pd2
t
pd1
t
w4
t
w3
BUSY
t
t
w7
su1
t
d7
CS
t
d6
†
CONVERT
t
CONV
t
CONV
†
SAMPLING
(When CS Toggle)
t
ACQ
BYTE
t
su4
t
h1
t
su2
t
d1
t
h2
RD
Invalid
Invalid
Data to
be read
Previous Conversion
Current Conversion
†
t
h4
t
t
en
t
dis
su5
Hi−Z
Hi−Z
Hi−Z
Hi−Z
DB[15:8]
DB[7:0]
D [7:0]
D [15:8]
D [7:0]
†
Signal internal to device
Figure 1. Timing for Conversion and Acquisition Cycles With CS and RD Toggling
9
ADS8406
www.ti.com
SLAS426A–AUGUST 2004–REVISED DECEMBER 2004
TIMING DIAGRAMS (continued)
t
w1
t
w2
CONVST
(used in normal
conversion)
t
cycle
CONVST
(used in ABORT)
t
t
su(AB)
su(AB)
t
t
pd2
pd1
t
w4
t
w3
BUSY
t
w7
t
su1
t
d7
CS
†
t
d6
CONVERT
t
CONV
t
CONV
†
SAMPLING
(When CS Toggle)
t
ACQ
BYTE
t
t
h1
su4
t
en
t
h2
RD = 0
t
dis
t
dis
t
en
Invalid
Invalid
Data to
be read
Previous Conversion
Current Conversion
†
t
h4
t
su5
Repeated
D [15:8]
Previous
D [15:8]
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
DB[15:8]
DB[7:0]
D [15:8]
D [7:0]
D [7:0]
Repeated
D [7:0]
Previous
D [7:0]
t
en
†
Signal internal to device
Figure 2. Timing for Conversion and Acquisition Cycles With CS Toggling, RD Tied to BDGND
10
ADS8406
www.ti.com
SLAS426A–AUGUST 2004–REVISED DECEMBER 2004
TIMING DIAGRAMS (continued)
t
w1
t
w2
CONVST
(used in normal
t
cycle
conversion)
CONVST
(used in ABORT)
t
t
su(AB)
su(AB)
t
t
pd2
t
pd1
pd1
t
w4
t
w3
BUSY
CS = 0
†
CONVERT
t
CONV
t
CONV
t
(ACQ)
†
SAMPLING
(When CS = 0)
BYTE
t
su4
t
h1
t
h2
RD
t
dis
t
en
Invalid
Invalid
Data to
be read
Previous Conversion
Current Conversion
†
t
h4
t
su5
Hi−Z
Hi−Z
Hi−Z
Hi−Z
DB[15:8]
D [15:8]
D [7:0]
D [7:0]
DB[7:0]
†
Signal internal to device
Figure 3. Timing for Conversion and Acquisition Cycles With CS Tied to BDGND, RD Toggling
11
ADS8406
www.ti.com
SLAS426A–AUGUST 2004–REVISED DECEMBER 2004
TIMING DIAGRAMS (continued)
t
w1
t
w2
CONVST
(used in normal
conversion)
t
cycle
CONVST
(used in ABORT)
t
t
su(AB)
su(AB)
t
t
pd2
pd1
t
w4
t
pd1
t
pd2
t
w3
BUSY
CS = 0
†
CONVERT
t
CONV
t
CONV
t
ACQ
†
SAMPLING
(When CS Toggle)
t
h1
t
h1
BYTE
RD = 0
t
d3
t
d3
t
d5
t
d5
t
h4
t
h4
t
t
d3
su5
t
su5
Previous
MSB
Invalid
Invalid
DB[15:8]
MSB
MSB
MSB
MSB
LSB
LSB
Invalid
Previous
Previous
LSB
Invalid
DB[7:0]
LSB
†
Signal internal to device
Figure 4. Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGND—Auto Read
CS
RD
t
su4
BYTE
t
en
t
d3
t
dis
t
dis
t
en
Hi−Z
Hi−Z
Hi−Z
Valid
Valid
Valid
DB[15:0]
Figure 5. Detailed Timing for Read Cycles
12
ADS8406
www.ti.com
SLAS426A–AUGUST 2004–REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS
At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and fsample = 1.25 MHz
(unless otherwise noted)
SIGNAL-TO-NOISE RATIO
HISTOGRAM (DC Code Spread)
HALF SCALE 131071 CONVERSIONS
vs
FREE-AIR TEMPERATURE
90.9
90.8
80000
f = 50 kHz,
i
+VA = 5 V,
Full Scale Input,
VA = 5 V,
70000
+VBD = 3.3 V,
VBD = 3 V,
Internal Reference = 4.096 V
T
A
= 25°C,
60000
50000
40000
Code = 65292
90.7
90.6
90.5
30000
20000
90.4
90.3
10000
0
−40 −25 −10
5
20 35 50 65 80
T
A
− Free-Air Temperature − 5C
Figure 6.
Figure 7.
SIGNAL-TO-NOISE AND DISTORTION
EFFECTIVE NUMBER OF BITS
vs
FREE-AIR TEMPERATURE
vs
FREE-AIR TEMPERATURE
91
14.8
f = 50 kHz,
i
Full Scale Input,
VA = 5 V,
VBD = 3 V,
Internal Reference = 4.096 V
90.5
14.7
14.6
90
f = 50 kHz,
i
89.5
14.5
14.4
Full Scale Input,
VA = 5 V,
VBD = 3 V,
Internal Reference = 4.096 V
89
−40 −25 −10
5
20 35 50 65 80
−40 −25 −10
5
20 35 50 65 80
T
A
− Free-Air Temperature − 5C
T
A
− Free-Air Temperature − 5C
Figure 8.
Figure 9.
13
ADS8406
www.ti.com
SLAS426A–AUGUST 2004–REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS (continued)
SPURIOUS FREE DYNAMIC RANGE
TOTAL HARMONIC DISTORTION
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
−94
−95
102
f = 50 kHz,
i
Full Scale Input,
VA = 5 V,
101
100
VBD = 3 V,
Internal Reference = 4.096 V
−96
−97
−98
−99
99
98
97
f = 50 kHz,
−100
i
96
95
94
Full Scale Input,
VA = 5 V,
VBD = 3 V,
Internal Reference = 4.096 V
−101
−102
−40 −25 −10
5
20 35 50 65 80
−40 −25 −10
5
20 35 50 65 80
T
A
− Free-Air Temperature − 5C
T
A
− Free-Air Temperature − 5C
Figure 10.
Figure 11.
SIGNAL-TO-NOISE RATIO
vs
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY
INPUT FREQUENCY
92
14.9
14.8
Full Scale Input,
VA = 5 V,
91.8
91.6
91.4
VBD = 5 V,
T
= 25°C,
A
Internal Reference = 4.096 V
91.2
91
14.7
14.6
90.8
90.6
90.4
90.2
Full Scale Input,
VA = 5 V,
14.5
14.4
VBD = 5 V,
90
T
= 25°C,
A
Internal Reference = 4.096 V
89.8
0
10 20 30 40 50 60 70 80 90 100
0
10 20 30 40 50 60 70 80 90 100
f − Input Frequency − kHz
i
f − Input Frequency − kHz
i
Figure 12.
Figure 13.
SIGNAL-TO-NOISE AND DISTORTION
SPURIOUS FREE DYNAMIC RANGE
vs
vs
INPUT FREQUENCY
INPUT FREQUENCY
91.5
101
100
99
91
90.5
98
97
90
89.5
96
Full Scale Input,
VA = 5 V,
VBD = 5 V,
Full Scale Input,
VA = 5 V,
89
VBD = 5 V,
95
94
T
= 25°C,
A
T
= 25°C,
A
Internal Reference = 4.096 V
Internal Reference = 4.096 V
88.5
0
10 20 30 40 50 60 70 80 90 100
10 20 30 40 50 60 70 80 90 100
0
f − Input Frequency − kHz
i
f − Input Frequency − kHz
i
Figure 14.
Figure 15.
14
ADS8406
www.ti.com
SLAS426A–AUGUST 2004–REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS (continued)
TOTAL HARMONIC DISTORTION
SUPPLY CURRENT
vs
SAMPLE RATE
vs
INPUT FREQUENCY
30.5
30
−94
Full Scale Input,
VA = 5 V,
T
= 25°C,
A
−95
−96
−97
−98
−99
VBD = 5 V,
= 25°C,
Current of +VA Only,
VBD = 5 V,
VA = 5 V
T
A
Internal Reference = 4.096 V
29.5
29
28.5
28
27.5
−100
−101
27
26.5
0
10 20 30 40 50 60 70 80 90 100
250
500
750
1000
1250
f − Input Frequency − kHz
i
Throughput − KSPS
Figure 16.
Figure 17.
GAIN ERROR
vs
SUPPLY VOLTAGE
OFFSET ERROR
vs
SUPPLY VOLTAGE
0.4
0.2
T
= 25°C,
A
0.18
External Reference = 4.096 V,
VBD = 5 V
0.3
0.2
0.1
0
0.16
0.14
0.12
0.1
0.08
−0.1
−0.2
T
A
= 25°C,
0.06
External Reference = 4.096 V,
VBD = 5 V
0.04
0.02
0
−0.3
−0.4
4.75
5
5.25
4.75
5
5.25
V
− Supply Voltage − V
V
− Supply Voltage − V
CC
CC
Figure 18.
Figure 19.
INTERNAL VOLTAGE REFERENCE
GAIN ERROR
vs
FREE-AIR TEMPERATURE
vs
FREE-AIR TEMPERATURE
1.5
4.1
VBD = 5 V,
VA = 5 V
4.098
4.096
4.094
1
0.5
0
4.092
4.09
−0.5
External Refence = 4.096 V,
VBD = 5 V,
VA = 5 V
−1
4.088
4.086
−1.5
−40 −25 −10
5
20 35 50 65 80
−40 −25 −10
5
20 35 50 65 80
T
A
− Free-Air Temperature − 5C
T
A
− Free-Air Temperature − 5C
Figure 20.
Figure 21.
15
ADS8406
www.ti.com
SLAS426A–AUGUST 2004–REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS (continued)
OFFSET ERROR
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
0.14
0.12
0.1
30.4
30.2
30
29.8
0.08
0.06
29.6
29.4
29.2
0.04
External Reference = 4.096 V,
External Reference = 4.096 V,
Current of +VA Only,
VBD = 5 V,
VBD = 5 V,
VA = 5 V
0.02
29
VA = 5 V
0
28.8
−40 −25 −10
5
20 35 50 65 80
−40 −25 −10
5
20 35 50 65 80
T
A
− Free-Air Temperature − 5C
T
A
− Free-Air Temperature − 5C
Figure 22.
Figure 23.
DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
1.5
1.5
Max
1
1
Max
0.5
0.5
0
0
Min
External Reference = 4.096 V,
VBD = 5 V,
VA = 5 V
−0.5
−0.5
−1
External Reference = 4.096 V,
VBD = 5 V,
−1
Min
VA = 5 V
−1.5
−1.5
−40 −25 −10
5
20 35 50 65 80
−40 −25 −10
5
20 35 50 65 80
T
A
− Free-Air Temperature − 5C
T
A
− Free-Air Temperature − 5C
Figure 24.
Figure 25.
DIFFERENTIAL NONLINEARITY
vs
INTEGRAL NONLINEARITY
vs
REFERENCE VOLTAGE
REFERENCE VOLTAGE
2
2
T
= 25°C,
T
= 25°C,
A
A
VA = 5 V,
VA = 5 V,
VBD = 5 V
1.5
1.5
1
Max
VBD = 5 V
Max
1
0.5
0
0.5
0
Min
−0.5
−0.5
−1
−1
−1.5
−2
Min
−1.5
−2
2.5
3
3.5
4
2.5
3
3.5
4
V
− Reference Voltage − V
V
− Reference Voltage − V
REF
REF
Figure 26.
Figure 27.
16
ADS8406
www.ti.com
SLAS426A–AUGUST 2004–REVISED DECEMBER 2004
TYPICAL CHARACTERISTICS (continued)
DNL
2.5
2
1.5
1
0.5
0
−0.5
−1
−1.5
−2
−2.5
0
16384
32768
49152
65536
Code
Figure 28.
INL
2.5
2
1.5
1
0.5
0
−0.5
−1
−1.5
−2
−2.5
0
16384
32768
Code
49152
65536
Figure 29.
FFT
0
f = 100 kHz,
i
−20
−40
−60
−80
f
= 1.25 MHz,
s
A
T
= 25°C,
Internal Reference = 4.096 V
−100
−120
−140
−160
−180
−200
0
100 k
200 k
300 k
400 k
500 k
600 k
Samples
Figure 30.
17
ADS8406
www.ti.com
SLAS426A–AUGUST 2004–REVISED DECEMBER 2004
APPLICATION INFORMATION
MICROCONTROLLER INTERFACING
ADS8406 to 8-Bit Microcontroller Interface
Figure 31 shows a parallel interface between the ADS8406 and a typical microcontroller using the 8-bit data bus.
The BUSY signal is used as a falling-edge interrupt to the microcontroller.
Analog 5 V
0.1 µF
AGND
10 µF
Ext Ref Input
0.1 µF
1 µF
Analog Input
Micro
Controller
Digital 3 V
ADS8406
GPIO
CS
0.1 µF
GPIO
P[7:0]
BYTE
BDGND
DB[15:8]
RD
CONVST
BUSY
BDGND
RD
GPIO
INT
+VBD
Figure 31. ADS8406 Application Circuitry (using external reference)
Analog 5 V
AGND
0.1 µF
10 µF
0.1 µF
1 µF
AGND
ADS8406
Figure 32. Use Internal Reference
PRINCIPLES OF OPERATION
The ADS8406 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The
architecture is based on charge redistribution, which inherently includes a sample/hold function. See Figure 31
for the application circuit for the ADS8406.
The conversion clock is generated internally. The conversion time of 650 ns is capable of sustaining a 1.25-MHz
throughput.
18
ADS8406
www.ti.com
SLAS426A–AUGUST 2004–REVISED DECEMBER 2004
PRINCIPLES OF OPERATION (continued)
The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential input
on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are
disconnected from any internal function.
REFERENCE
The ADS8406 can operate with an external reference with a range from 2.5 V to 4.2 V. A 4.096-V internal
reference is included. When internal reference is used, pin 2 (REFOUT) should be connected to pin 1 (REFIN)
with a 0.1-µF decoupling capacitor and 1-µF storage capacitor between pin 2 (REFOUT) and pins 47 and 48
(REFM) (see Figure 33). The internal reference of the converter is double buffered. If an external reference is
used, the second buffer provides isolation between the external reference and the CDAC. This buffer is also
used to recharge all of the capacitors of the CDAC during conversion. Pin 2 (REFOUT) can be left unconnected
(floating) if external reference is used.
ANALOG INPUT
When the converter enters the hold mode, the voltage difference between the +IN and -IN inputs is captured on
the internal capacitor array. Both +IN and –IN inputs have a range of –0.2 V to Vref + 0.2 V. The input span (+IN
– (–IN)) is limited to -Vref to Vref..
The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and source
impedance. Essentially, the current into the ADS8406 charges the internal capacitor array during the sample
period. After this capacitance has been fully charged, there is no further input current. The source of the analog
input voltage must be able to charge the input capacitance (25 pF) to an 16-bit settling level within the acquisition
time (150 ns) of the device. When the converter goes into the hold mode, the input impedance is greater than 1
GΩ.
Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the
+IN and –IN inputs and the span (+IN – (–IN)) should be within the limits specified. Outside of these ranges, the
converter's linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass
filters should be used.
Care should be taken to ensure that the output impedance of the sources driving +IN and –IN inputs are
matched. If this is not observed, the two inputs could have different setting time. This may result in offset error,
gain error and linearity error which varies with temperature and input voltage.
A typical input circuit using TI's THS4503 is shown in Figure 33. Input from a single-ended source may be
converted into a differential signal for the ADS8406 as shown in the figure. In case the source itself is differential,
then the THS4503 may be used in differential input and differential output modes.
68 pF
R
S
R
G
1 kΩ
50 Ω
V
CC+
R
T
IN−
ADS8406
_
+
20 pF
THS4503
_
+
IN+
+
_
OCM
V
CC−
1 kΩ
1 kΩ
50 Ω
R
R
V
R , and R should be chosen such that
S T
68 pF
G,
R
|| R = 1 k Ω
T
G +
OCM
S
= 2 V, +V = 7 V, and −V = −7 V
CC CC
Figure 33. Using the THS4503 With the ADS8406
19
ADS8406
www.ti.com
SLAS426A–AUGUST 2004–REVISED DECEMBER 2004
PRINCIPLES OF OPERATION (continued)
DIGITAL INTERFACE
Timing And Control
See the timing diagrams in the specifications section for detailed information on timing signals and their
requirements.
The ADS8406 uses an internal oscillator generated clock which controls the conversion rate and in turn the
throughput of the converter. No external clock input is required.
Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum
requirement has been met, the CONVST pin can be brought high), while CS is low. The ADS8406 switches from
the sample to the hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge of
this signal is important to the performance of the converter. The BUSY output is brought high after CONVST
goes low. BUSY stays high throughout the conversion process and returns low when the conversion has ended.
Sampling starts as soon as the conversion is over when CS is tied low or starts with the falling edge of CS when
BUSY is low.
Both RD and CS can be high during and before a conversion with one exception (CS must be low when
CONVST goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the
parallel output bus with the conversion.
Reading Data
The ADS8406 outputs full parallel data in two's complement format as shown in Table 1. The parallel output is
active when CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of
CONVST. This is 50 ns prior to the falling edge of CONVST and 40 ns after the falling edge. No data read should
be attempted within this zone. Any other combination of CS and RD sets the parallel output to 3-state. BYTE is
used for multiword read operations. BYTE is used whenever lower bits of the converter result are output on the
higher byte of the bus. Refer to Table 1 for ideal output codes.
Table 1. Ideal Input Voltages and Output Codes
DESCRIPTION
Full scale range
ANALOG VALUE
DIGITAL OUTPUT
2'S COMPLEMENT
2(+Vref
)
Least significant bit (LSB)
+Full scale
2(+Vref)/65536
(+Vref) – 1 LSB
0 V
BINARY CODE
HEX CODE
7FFF
0111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
1000 0000 0000 0000
Midscale
0000
Midscale – 1 LSB
– Full scale
0 V– 1 LSB
FFFF
( –Vref
)
8000
The output data is a full 16-bit word (D15–D0) on DB15–DB0 pins (MSB–LSB) if BYTE is low.
The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB15–DB8. In this
case two reads are necessary: the first as before, leaving BYTE low and reading the 8 most significant bits on
pins DB15–DB8, then bringing BYTE high. When BYTE is high, the low bits (D7–D0) appear on pins DB15–D8.
These multiword read operations can be done with multiple active RD (toggling) or with RD tied low for simplicity.
Conversion Data Readout
DATA READ OUT
BYTE
DB15–DB8 Pins
D7–D0
DB7–DB0 Pins
All one's
High
Low
D15–D8
D7–D0
20
ADS8406
www.ti.com
SLAS426A–AUGUST 2004–REVISED DECEMBER 2004
RESET
RESET is an asynchronous active low input signal (that works independently of CS). Minimum RESET low time
is 25 ns. Current conversion will be aborted no later than 50 ns after the converter is in the reset mode. In
addition, all output latches are cleared (set to zero's) after RESET. The converter goes back to normal operation
mode no later than 20 ns after RESET input is brought high.
The converter starts the first sampling period 20 ns after the rising edge of RESET. Any sampling period except
for the one immediately after a RESET is started with the falling edge of the previous BUSY signal or the falling
edge of CS, whichever is later.
Another way to reset the device is through the use of the combination of CS and CONVST. This is useful when
the dedicated RESET pin is tied to the system reset but there is a need to abort only the conversion in a specific
converter. Since the BUSY signal is held high during the conversion, either one of these conditions triggers an
internal self-clear reset to the converter just the same as a reset via the dedicated RESET pin. The reset does
not have to be cleared as for the dedicated RESET pin. A reset can be started with either of the two following
steps.
•
Issue a CONVST when CS is low and a conversion is in progress. The falling edge of CONVST must satisfy
the timing as specified by the timing parameter tsu(AB) mentioned in the timing characteristics table to ensure
a reset. The falling edge of CONVST starts a reset. Timing is the same as a reset using the dedicated
RESET pin except the instance of the falling edge is replaced by the falling edge of CONVST.
•
Issue a CS while a conversion is in progress. The falling edge of CS must satisfy the timing as specified by
the timing parameter tsu(AB) mentioned in the timing characteristics table to ensure a reset.The falling edge of
CS causes a reset. Timing is the same as a reset using the dedicated RESET pin except the instance of the
falling edge is replaced by the falling edge of CS.
POWER-ON INITIALIZATION
RESET is not required after power on. An internal power-on-reset circuit generates the reset. To ensure that all
of the registers are cleared, the three conversion cycles must be given to the converter after power on.
LAYOUT
For optimum performance, care should be taken with the physical layout of the ADS8406 circuitry.
As the ADS8406 offers single-supply operation, it is often used in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and
the higher the switching speed, the more difficult it is to achieve good performance from the converter.
The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground
connections and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving
any single conversion for an n-bit SAR converter, there are at least n windows in which large external transient
voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby
digital logic, or high power devices.
The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the
external event.
On average, the ADS8406 draws very little current from an external reference, as the reference voltage is
internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive
the bypass capacitor or capacitors without oscillation. A 0.1-µF bypass capacitor and a 1-µF storage capacitor
are recommended from pin 1 (REFIN) directly to pin 48 (REFM). REFM and AGND should be shorted on the
same ground plane under the device.
The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the
analog ground. Avoid connections which are close to the grounding point of a microcontroller or digital signal
processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal
layout consists of an analog ground plane dedicated to the converter and associated analog circuitry.
21
ADS8406
www.ti.com
SLAS426A–AUGUST 2004–REVISED DECEMBER 2004
As with the AGND connections, +VA should be connected to a 5-V power supply plane or trace that is separate
from the connection for digital logic until they are connected at the power entry point. Power to the ADS8406
should be clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to the device
as possible. See Table 2 for the placement of the capacitor. In addition, a 1-µF to 10-µF capacitor is
recommended. In some situations, additional bypassing may be required, such as a 100-µF electrolytic capacitor
or even a Pi filter made up of inductors and capacitors—all designed to essentially low-pass filter the 5-V supply,
removing the high frequency noise.
Table 2. Power Supply Decoupling Capacitor Placement
POWER SUPPLY PLANE
CONVERTER ANALOG SIDE
CONVERTER DIGITAL SIDE
SUPPLY PINS
Pin pairs that require shortest path to decoupling capacitors
Pins that require no decoupling
(4,5), (8,9), (10,11), (13,15),
(43,44), (45,46)
(24,25), (34, 35)
37
12, 14
22
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jul-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
ADS8406IBPFBR
ADS8406IBPFBRG4
ADS8406IBPFBT
ADS8406IBPFBTG4
ADS8406IPFBT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
PFB
PFB
PFB
PFB
PFB
PFB
48
48
48
48
48
48
2000
2000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
ADS8406IPFBTG4
250
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jul-2011
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS8406IBPFBR
ADS8406IBPFBT
ADS8406IPFBT
TQFP
TQFP
TQFP
PFB
PFB
PFB
48
48
48
2000
250
330.0
330.0
330.0
16.4
16.4
16.4
9.6
9.6
9.6
9.6
9.6
9.6
1.5
1.5
1.5
12.0
12.0
12.0
16.0
16.0
16.0
Q2
Q2
Q2
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS8406IBPFBR
ADS8406IBPFBT
ADS8406IPFBT
TQFP
TQFP
TQFP
PFB
PFB
PFB
48
48
48
2000
250
367.0
367.0
367.0
367.0
367.0
367.0
38.0
38.0
38.0
250
Pack Materials-Page 2
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
Gage Plane
6,80
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4073176/B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products
Audio
Applications
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
www.ti.com/security
Medical
Logic
Security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense www.ti.com/space-avionics-defense
microcontroller.ti.com
www.ti-rfid.com
Video and Imaging
www.ti.com/video
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community
e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明