ADS8471IBRGZT [TI]
具有基准的 16 位 1MSPS 伪差动 SAR ADC | RGZ | 48 | -40 to 85;
| 型号： | ADS8471IBRGZT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有基准的 16 位 1MSPS 伪差动 SAR ADC | RGZ | 48 | -40 to 85 转换器 |
| 文件： | 总30页 (文件大小：2123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADS8471
SLAS517–DECEMBER 2007
16-BIT, 1-MSPS, PSEUDO-BIPOLAR, UNIPOLAR INPUT, MICROPOWER SAMPLING
ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE
1
FEATURES
•
48-Pin 7x7 QFN Package
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0 to 1 MSPS Sampling Rate
±0.7 LSB Typ, ±1 LSB Max INL
±0.4 LSB Typ, ±0.75 LSB Max DNL
16-Bit NMC Ensured Over Temperature
±0.1 mV Offset Error
APPLICATIONS
•
•
•
•
•
Medical Instruments
Optical Networking
Transducer Interface
High Accuracy Data Acquisition Systems
Magnetometers
±0.15 ppm/°C Offset Error Drift
±0.015 %FSR Gain Error
DESCRIPTION
±0.7 ppm/°C Gain Error Drift
93 dB SNR, -110dB THD, 112dB SFDR
Zero Latency
The ADS8471 is an 16-bit, 1-MSPS A/D converter
with an internal 4.096-V reference and
pseudo-bipolar, unipolar input. The device includes a
16-bit capacitor-based SAR A/D converter with
inherent sample and hold. The ADS8471 offers a full
16-bit interface or an 8-bit bus option using two read
cycles.
a
Low Power: 220 mW at 1 MSPS
Unipolar Input Range: 0 V to Vref
Onboard Reference
Onboard Reference Buffer
High-Speed Parallel Interface
Wide Digital Supply 2.7 V ~ 5.25 V
8-/16-Bit Bus Transfer
The ADS8471 is available in a 48-lead 7x7 QFN
package and is characterized over the industrial
–40°C to 85°C temperature range.
HIGH-SPEED SAR CONVERTER FAMILY(1)
TYPE/SPEED
18-Bit Pseudo-Diff
500 kHz
580 kHz
750 kHz
1 MHz
1.25 MHz
2 MHz
3 MHz
4MHz
ADS8383
ADS8381
ADS8380 (S)
ADS8382 (S)
ADS8370 (S)
18-Bit Pseudo-Bipolar, Fully Diff
16-Bit Pseudo-Diff
ADS8482
ADS8471
ADS8484
ADS8401
ADS8405
ADS8402
ADS8406
ADS7890 (S)
ADS8327 (S)
ADS8328 (S)
ADS8371
ADS8411
ADS8410 (S)
ADS8412
ADS8329/30 (S)
ADS8472
ADS8372 (S)
ADS8422
ADS7881
16-Bit Pseudo-Bipolar, Fully Diff
ADS8413 (S)
14-Bit Pseudo-Diff
12-Bit Pseudo-Diff
ADS7891
ADS7886
(1) S: Serial
BYTE
16-/8-Bit
Parallel DATA
Output Bus
Output
Latches
and
3-State
Drivers
SAR
+
+IN
CDAC
_
−IN
Comparator
REFIN
CONVST
BUSY
CS
Conversion
and
Control Logic
4.096-V
Internal
Reference
REFOUT
Clock
RD
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADS8471
www.ti.com
SLAS517–DECEMBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
MAXIMUM
INTEGRAL
LINEARITY
(LSB)
MAXIMUM
DIFFERENTIAL
LINEARITY (LSB)
NO MISSING
CODES
RESOLUTION
(BIT)
TRANS-
PORT
MEDIA
QTY.
TEMPER-
ATURE
RANGE
PACKAGE
TYPE
PACKAGE
DESIGNATOR
ORDERING
INFORMATION
MODEL
ADS8471IRGZT
ADS8471IRGZR
ADS8471IBRGZT
ADS8471IBRGZR
Tape and
reel 250
7x7 48 Pin
QFN
–40°C to
85°C
ADS8471I
±2
±1
±1
16
16
RGZ
RGZ
Tape and
reel 1000
Tape and
reel 250
7x7 48 Pin
QFN
–40°C to
85°C
ADS8471IB
±0.75
Tape and
reel 1000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
–0.4 to +VA + 0.1
–0.4 to 0.5
–0.3 to 7
UNIT
V
+IN to AGND
–IN to AGND
+VA to AGND
+VBD to BDGND
+VA to +VBD
V
Voltage
V
–0.3 to 7
V
–0.3 to 2.55
–0.3 to +VBD + 0.3
–0.3 to +VBD + 0.3
–40 to 85
V
Digital input voltage to BDGND
Digital output voltage to BDGND
V
V
TA
Operating free-air temperature range
Storage temperature range
°C
°C
°C
Tstg
–65 to 150
150
Junction temperature (TJ max)
Power dissipation
(TJMax – TA)/θJA
22
QFN package
θJA thermal impedance
Vapor phase (60 sec)
Infrared (15 sec)
°C/W
°C
215
Lead temperature, soldering
220
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
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Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS8471
ADS8471
www.ti.com
SLAS517–DECEMBER 2007
SPECIFICATIONS
TA = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1 MSPS (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Full-scale input voltage(1)
+IN – (–IN)
0
–0.2
–0.2
Vref
Vref +0.2
0.2
V
V
+IN
–IN
Absolute input voltage
Input capacitance
Input leakage current
SYSTEM PERFORMANCE
Resolution
65
1
pF
nA
16
Bits
Bits
ADS8471I
ADS8471IB
ADS8471I
ADS8471IB
ADS8471I
ADS8471IB
ADS8471I
ADS8471IB
ADS8471I
ADS8471IB
ADS8471I
ADS8471IB
ADS8471I
ADS8471IB
16
16
No missing codes
–2
±0.7
±0.7
2
1
LSB
(16 bit)
INL
Integral linearity(2) (3)
Differential linearity
Offset error(4)
–1
–1
±0.4
1
LSB
(16 bit)
DNL
–0.75
–0.5
–0.5
±0.4
0.75
0.5
0.5
±0.1
mV
±0.1
±0.15
±0.15
Offset error temperature drift
Gain error(4) (5)
ppm/°C
Vref = 4.096 V
Vref = 4.096 V
–0.075 ±0.015
0.075
0.075
%FS
%FS
–0.075 ±0.015
±0.7
±0.7
25
Gain error temperature drift
ppm/°C
Noise
µV RMS
Power supply rejection ratio
At FFFFh output code
60
dB
SAMPLING DYNAMICS
Conversion time
Acquisition time
Throughput rate
Aperture delay
670
700
1
ns
ns
270
300
MHz
ns
4
5
Aperture jitter
ps
Step response
150
150
ns
Overvoltage recovery
ns
(1) Ideal input span, does not include gain or offset error.
(2) LSB means least significant bit
(3) This is endpoint INL, not best fit.
(4) Measured relative to an ideal full-scale input [+IN – (–IN)] of 8.192 V
(5) This specification does not include the internal reference voltage error and drift.
Copyright © 2007, Texas Instruments Incorporated
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3
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ADS8471
www.ti.com
SLAS517–DECEMBER 2007
SPECIFICATIONS (Continued)
TA = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1 MSPS (unless otherwise noted)
PARAMETER
DYNAMIC CHARACTERISTICS
TEST CONDITIONS
MIN
TYP
MAX UNIT
ADS8471I
ADS8471IB
ADS8471I
ADS8471IB
ADS8471I
ADS8471IB
ADS8471I
ADS8471IB
ADS8471I
ADS8471IB
ADS8471I
ADS8471IB
ADS8471I
ADS8471IB
ADS8471I
ADS8471IB
ADS8471I
ADS8471IB
ADS8471I
ADS8471IB
ADS8471I
ADS8471IB
ADS8471I
ADS8471IB
–110
–112
–105
–107
–101
–102
93
VIN = 4 Vpp at 2 kHz
THD
SNR
Total harmonic distortion(1)
VIN = 4 Vpp at 20 kHz
VIN = 4 Vpp at 100 kHz
VIN = 4 Vpp at 2 kHz
VIN = 4 Vpp at 20 kHz
VIN = 4 Vpp at 100 kHz
VIN = 4 Vpp at 2 kHz
VIN = 4 Vpp at 20 kHz
VIN = 4 Vpp at 100 kHz
VIN = 4 Vpp at 2 kHz
VIN = 4 Vpp at 20 kHz
VIN = 4 Vpp at 100 kHz
dB
dB
dB
93
92.5
92.7
91.5
91.6
93
Signal-to-noise ratio(1)
93
92.4
92.6
91
(1)
SINAD Signal-to-noise + distortion
91.1
112
114
107
109
102
103
15
(1)
SFDR
Spurious free dynamic range
dB
–3dB Small signal bandwidth
VOLTAGE REFERENCE INPUT
MHz
Vref
Reference voltage at REFIN,
Reference resistance(2)
Reference current drain
3.0
4.096 +VA – 0.8
V
500
kΩ
mA
fs = 1 MHz
1
(1) Calculated on the first nine harmonics of the input frequency.
(2) Can vary ±20%
4
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Product Folder Link(s): ADS8471
ADS8471
www.ti.com
SLAS517–DECEMBER 2007
SPECIFICATIONS (Continued)
TA = –40C to 85C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1 MSPS (unless otherwise noted)
PARAMETER
INTERNAL REFERENCE OUTPUT
Internal reference start-up time
TEST CONDITIONS
MIN
TYP
MAX UNIT
From 95% (+VA), with 1-µF storage
120
ms
capacitor
Vref
Reference voltage range
Source current
Line regulation
Drift
IO = 0 A
4.081 4.096
4.111
10
V
µA
Static load
+VA = 4.75 V to 5.25 V
IO = 0 A
60
±6
µV
PPM/°C
DIGITAL INPUT/OUTPUT
Logic family – CMOS
VIH
VIL
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Data format – Straight binary
IIH = 5 µA
+VBD–1
+VBD +0.3
0.8
IIL = 5 µA
–0.3
V
VOH
VOL
IOH = 2 TTL loads
IOL = 2 TTL loads
+VBD – 0.6
0.4
POWER SUPPLY REQUIREMENTS
+VBD
+VA
2.7
3.3
5
5.25
5.25
48
V
V
Power supply voltage
4.75
Supply current(1)
Power dissipation(1)
fs = 1 MHz
fs = 1 MHz
44
mA
mW
220
240
TEMPERATURE RANGE
Operating free-air
–40
85
°C
(1) This includes only +VA current. +VBD current is typical 1 mA with 5-pF load capacitance on all output pins.
Copyright © 2007, Texas Instruments Incorporated
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ADS8471
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SLAS517–DECEMBER 2007
TIMING CHARACTERISTICS
All specifications typical at –40°C to 85°C, +VA =+VBD = 5 V
(1) (2) (3)
PARAMETER
MIN TYP
MAX UNIT
t(CONV)
t(ACQ)
t(HOLD)
tpd1
Conversion time
670
700
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ns
ns
Acquisition time
270
300
Sample capacitor hold time
CONVST low to BUSY high
Propagation delay time, end of conversion to BUSY low
25
40
15
15
tpd2
tpd3
Propagation delay time, start of convert state to rising edge of BUSY
Pulse duration, CONVST low
tw1
40
20
20
tsu1
Setup time, CS low to CONVST low
Pulse duration, CONVST high
tw2
CONVST falling edge jitter
10
tw3
tw4
th1
Pulse duration, BUSY signal low
t(ACQ)min
Pulse duration, BUSY signal high
700
Hold time, first data bus transition (RD low, or CS low for read cycle, or BYTE input
changes) after CONVST low
40
ns
td1
Delay time, CS low to RD low
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu2
tw5
ten
Setup time, RD high to CS high
Pulse duration, RD low
50
Enable time, RD low (or CS low for read cycle) to data valid
Delay time, data hold from RD high
20
20
td2
5
10
20
20
50
td3
Delay time, BYTE rising edge or falling edge to data valid
Pulse duration, RD high
tw6
tw7
th2
Pulse duration, CS high
Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge
tpd4
Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling
edge
0
ns
td4
tsu3
th3
tdis
td5
td6
td7
tsu5
Delay time, BYTE edge to edge skew
0
10
10
ns
ns
ns
ns
ns
ns
ns
ns
Setup time, BYTE transition to RD falling edge
Hold time, BYTE transition to RD falling edge
Disable time, RD high (CS high for read cycle) to 3-stated data bus
Delay time, BUSY low to MSB data valid delay
20
0
Delay time, CS rising edge to BUSY falling edge
Delay time, BUSY falling edge to CS rising edge
BYTE transition setup time, from BYTE transition to next BYTE transition
50
50
50
tsu(ABORT) Setup time from the falling edge of CONVST (used to start the valid conversion) to the
next falling edge of CONVST (when CS = 0 and CONVST are used to abort) or to the
next falling edge of CS (when CS is used to abort).
60
600
ns
(1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2.
(2) See timing diagrams.
(3) All timing are measured with 20-pF equivalent loads on all data bits and BUSY pins.
6
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ADS8471
www.ti.com
SLAS517–DECEMBER 2007
TIMING CHARACTERISTICS
All specifications typical at –40°C to 85°C, +VA = 5 V +VBD = 3 V
(1) (2) (3)
PARAMETER
MIN TYP
MAX UNIT
t(CONV)
t(ACQ)
t(HOLD)
tpd1
Conversion time
67
700
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ns
ns
Acquisition time
270
300
Sample capacitor hold time
CONVST low to BUSY high
Propagation delay time, end of conversion to BUSY low
25
40
25
25
tpd2
tpd3
Propagation delay time, start of convert state to rising edge of BUSY
Pulse duration, CONVST low
tw1
40
20
20
tsu1
Setup time, CS low to CONVST low
Pulse duration, CONVST high
tw2
CONVST falling edge jitter
10
tw3
tw4
th1
Pulse duration, BUSY signal low
t(ACQ)min
Pulse duration, BUSY signal high
700
Hold time, first data bus transition (RD low, or CS low for read cycle, or BYTE input
changes) after CONVST low
40
ns
td1
Delay time, CS low to RD low
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu2
tw5
ten
Setup time, RD high to CS high
Pulse duration, RD low
50
Enable time, RD low (or CS low for read cycle) to data valid
Delay time, data hold from RD high
30
30
td2
5
10
20
20
50
td3
Delay time, BYTE rising edge or falling edge to data valid
Pulse duration, RD high
tw6
tw7
th2
Pulse duration, CS high
Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge
tpd4
Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling
edge
0
ns
td4
tsu3
th3
tdis
td5
td6
td7
tsu5
Delay time, BYTE edge to edge skew
0
10
10
ns
ns
ns
ns
ns
ns
ns
ns
Setup time, BYTE or transition to RD falling edge
Hold time, BYTE or transition to RD falling edge
Disable time, RD high (CS high for read cycle) to 3-stated data bus
Delay time, BUSY low to MSB data valid delay
30
0
Delay time, CS rising edge to BUSY falling edge
Delay time, BUSY falling edge to CS rising edge
BYTE transition setup time, from BYTE transition to next BYTE transition
50
50
50
tsu(ABORT) Setup time from the falling edge of CONVST (used to start the valid conversion) to the
next falling edge of CONVST (when CS = 0 and CONVST are used to abort) or to the
next falling edge of CS (when CS is used to abort).
60
600
ns
(1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2.
(2) See timing diagrams.
(3) All timing are measured with 20-pF equivalent loads on all data bits and BUSY pins.
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SLAS517–DECEMBER 2007
PIN ASSIGNMENTS
RGZ PACKAGE
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
+VBD
BDGND
BYTE
CONVST
RD
+VBD
DB8
DB9
1
36
35
34
33
32
31
30
29
28
27
26
25
2
3
DB10
DB11
DB12
DB13
DB14
DB15
AGND
AGND
+VA
4
5
CS
+VA
6
7
AGND
AGND
+VA
REFM
REFM
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
NC − No internal connection
NOTE: The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
TERMINAL FUNCTIONS
NAME
NO
I/O
DESCRIPTION
8, 9, 17, 20,
23, 24, 26,
27
AGND
–
Analog ground
BDGND
BUSY
2, 37
48
–
Digital ground for bus interface digital supply
O
Status output. High when a conversion is in progress.
Byte select input. Used for 8-bit bus reading.
0: No fold back
BYTE
3
I
1: Low byte D[9:2] of the 16 most significant bits is folded back to high byte of the 16 most significant pins DB[17:10].
Convert start. The falling edge of this input ends the acquisition period and starts the hold period.
Chip select. The falling edge of this input starts the acquisition period.
CONVST
CS
4
6
I
I
8-BIT BUS
16-BIT BUS
BYTE = 0
Data Bus
BYTE = 0
BYTE = 1
DB15
DB14
DB13
DB12
DB11
DB10
DB9
28
29
30
31
32
33
34
35
38
39
40
41
42
O
O
O
O
O
O
O
O
O
O
O
O
O
D15 (MSB)
D14
D13
D12
D11
D10
D9
D7
D15(MSB)
D14
D13
D12
D11
D10
D9
D6
D5
D4
D3
D2
All ones
All ones
All ones
All ones
All ones
All ones
All ones
DB8
D8
D8
DB7
D7
D7
DB6
D6
D6
DB5
D5
D5
DB4
D4
D4
DB3
D3
D3
8
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SLAS517–DECEMBER 2007
TERMINAL FUNCTIONS (continued)
NAME
NO
43
44
45
I/O
O
DESCRIPTION
DB2
DB1
DB0
D2
All ones
All ones
All ones
D2
O
D1
D1
O
D0 (LSB)
D0 (LSB)
–IN
19
18
I
I
Inverting input channel
Noninverting input channel
No connection
+IN
NC
15, 46, 47
13
REFIN
REFOUT
REFM
I
O
I
Reference input
14
Reference output. Add 1-µF capacitor between the REFOUT pin and REFM pin when internal reference is used.
11, 12
Reference ground
Synchronization pulse for the parallel output. When CS is low, this serves as output enable and puts the previous
conversion results on the bus.
RD
5
I
7, 10, 16,
21, 22, 25
+VA
–
–
Analog power supplies, 5-V DC
Digital power supply for bus
+VBD
1, 36
TYPICAL CHARACTERISTICS
INTERNAL REFERENCE VOLTAGE
INTERNAL REFERENCE VOLTAGE
DC HISTOGRAM
(8192 Conversion Outputs)
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
7000
4.098
4.0972
4.09719
4.09718
+VA = 5 V,
+VBD = 5 V
T
= 25°C
6140
A
6000
5000
4.0975
4.097
+VA = 5 V,
+VBD = 5 V,
T
= 25°C,
A
f
= 1 MSPS,
= 4.096 V,
S
4000
4.09717
4.09716
V
ref
Input = Midscale
4.0965
4.096
3000
2000
1000
0
4.09715
1621
4.09714
4.09713
4.0955
4.095
426
1
4
4.75
4.85
4.95
5.05
5.15
5.25
32766 32767 32768 32769 32770
-40 -25 -10
5
20 35
50 65 80
Supply Voltage - V
Code
T
- Free-Air Temperature - °C
A
Figure 1.
Figure 2.
Figure 3.
SUPPLY CURRENT
vs
FREE-AIR TEM PERATURE
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY CURRENT
vs
SAMPLE RATE
44
43.8
43.6
43.5
43
43.25
43.2
+VA = 5 V,
+VBD = 5 V,
+VA = 5 V,
+VBD = 5 V,
T
f
= 25°C,
A
= 1 MSPS,
= 4.096 V,
T = 25°C,
A
S
f
= 1 MSPS,
42.5
42
S
V
V
= 4.096 V
ref
V
= 4.096 V,
ref
ref
43.4
43.2
43
41.5
41
43.15
40.5
40
43.1
43.05
43
42.8
39.5
39
42.6
42.4
42.2
38.5
38
-40 -25 -10
5
20 35 50 65 80
4.75
4.85
4.95
5.05
5.15
5.25
250
500
750
1000
Supply Voltage - V
T
- Free-Air Temperature - °C
Sample Rate - KSPS
A
Figure 4.
Figure 5.
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
DIFFERENTIAL NONLINEARITY
INTEGRAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
DIFFERENTIAL NONLINEARITY
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
1
0.8
0.6
0.4
0.2
0.75
0.5
0.75
0.5
+VA = 5 V,
+VBD = 5 V,
T
f
= 25°C,
Max
A
= 1 MSPS,
= 4.096 V,
S
f
= 1 MSPS,
S
V
ref
V
= 4.096 V,
ref
+VA = 5 V,
+VBD = 5 V,
Max
Max
0.25
0
0.25
0
f
= 1 MSPS,
S
V
= 4.096 V,
ref
0
-0.2
-0.4
Min
-0.25
-0.25
Min
Min
-0.6
-0.5
-0.5
-0.8
-1
-0.75
-0.75
-40 -25 -10
5
20 35 50 65 80
4.75
4.85
4.95 5.05
Supply Voltage - V
5.15
5.25
-40 -25 -10
5
20 35 50 65 80
T - Free-Air Temperature - °C
A
T
- Free-Air Temperature - °C
A
Figure 7.
Figure 8.
Figure 9.
INTEGRAL NONLINEARITY
vs
DIFFERENTIAL NONLINEARITY
vs
INTEGRAL NONLINEARITY
vs
REFERENCE VOLTAGE
SUPPLY VOLTAGE
REFERENCE VOLTAGE
1
0.8
0.6
1
0.8
0.6
0.4
0.2
0.75
0.5
Max
T
f
= 25°C,
Max
A
= 1 MSPS,
= 5 V
S
V
DD
Max
T = 25°C,
A
+VA = 5 V,
+VBD = 5 V,
0.4
0.2
0
f
= 1 MSPS,
= 5 V
0.25
0
S
f
= 1 MSPS,
S
V
DD
V
= 4.096 V,
ref
0
-0.2
-0.4
-0.6
-0.2
-0.4
-0.6
-0.8
-1
Min
Min
-0.25
Min
-0.50
-0.75
-0.8
-1
3
3.2
3.4
3.6
3.8
4
4.2
4.75
4.85
4.95
5.05
5.15
5.25
3
3.2
3.4
3.6
3.8
4
4.2
Reference Voltage - V
Supply Voltage - V
Reference Voltage - V
Figure 10.
Figure 11.
Figure 12.
OFFSET ERROR
vs
FREE-AIR TEMPERATURE
OFFSET ERROR
vs
SUPPLY VOLTAGE
OFFSET ERROR
vs
REFERENCE VOLTAGE
0.1
0.08
0.06
0.04
0.25
0.2
0.1
0.08
0.06
0.04
0.02
T
= 25°C,
+VA = 5 V,
+VBD = 5 V,
T
f
= 25°C,
A
A
f
= 1 MSPS,
= 4.096 V,
= 1 MSPS,
= 5 V
S
S
f
= 1 MSPS,
0.15
0.1
S
V
V
ref
DD
V
= 4.096 V,
ref
0.02
0
0.05
0
-0.05
-0.1
0
-0.02
-0.04
-0.02
-0.04
-0.15
-0.06
-0.08
-0.10
-0.06
-0.08
-0.1
-0.2
-0.25
-40 -25 -10
4.75
4.85
4.95 5.05
Supply Voltage - V
5.15
5.25
5
20 35 50 65 80
3
3.2
3.4
3.6
3.8
Reference Voltage - V
4
4.2
T
- Free-Air Temperature - °C
A
Figure 13.
Figure 14.
Figure 15.
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TYPICAL CHARACTERISTICS (continued)
GAIN ERROR
vs
SUPPLY VOLTAGE
GAIN ERROR
vs
FREE-AIR TEMPERATURE
GAIN ERROR
vs
REFERENCE VOLTAGE
0.1
0.02
0.018
0.016
0.03
0.025
0.02
V = 5 V,
DD
0.08
+VA = 5 V,
+VBD = 5 V,
T
f
= 25°C,
A
T
= 25°C,
A
= 1 MSPS,
= 4.096 V,
S
f = 1 MSPS
i
0.06
0.04
f
= 1 MSPS,
S
V
ref
V
= 4.096 V,
ref
0.014
0.012
0.02
0
0.01
0.008
0.006
0.004
0.002
0
0.015
0.01
-0.02
-0.04
-0.06
0.005
0
-0.08
-0.1
-40 -25 -10
5
20 35 50 65 80
4.75
4.85
4.95 5.05
Supply Voltage - V
5.15
5.25
3
3.2
3.4
3.6
3.8
4
4.2
T
- Free-Air Temperature - °C
A
Reference Voltage - V
Figure 16.
Figure 17.
Figure 18.
TOTAL HARMONIC DISTORTION
OFFSET ERROR TEMPERATURE
DRIFT DISTRIBUTION (25 Samples)
GAIN ERROR TEMPERATURE
DRIFT DISTRIBUTION (25 Samples)
vs
REFERENCE VOLTAGE
12
-106
-107
-108
-109
-110
10
+VA = 5 V,
+VBD = 5 V,
+VA = 5 V,
+VBD = 5 V,
+VA = 5 V,
+VBD = 5 V,
10
8
10
8
f = 1 MSPS,
i
f = 1 MSPS
i
8
6
4
T
= 25°C,
A
V
= 4.096 V
ref
V
= 4.096 V
ref
f
= 1 MSPS,
S
V = 2 kHz
I
7
5
6
4
4
4
3
3
2
2
2
0
-111
-112
2
0
1
1
3
3.2
3.4
3.6
3.8
4
4.2
-0.54 -0.16 0.21
0.59 0.97
1.30
0.02 0.06
0.10 0.14 0.18 0.22
V
- Reference Voltage - V
Gain Error Drift - ppm/C
Offset Drift - ppm/C
ref
Figure 19.
Figure 20.
Figure 21.
SIGNAL-TO-NOISE RATIO
vs
REFERENCE VOLTAGE
SIGNAL-TO-NOISE + DISTORTION
TOTAL HARMONIC DISTORTION
vs
vs
REFERENCE VOLTAGE
FREE-AIR TEMPERATURE
93.5
93
93.5
-109
+VA = 5 V,
+VBD = 5 V,
+VA = 5 V,
+VBD = 5 V,
+VA = 5 V,
+VBD = 5 V,
-109.2
-109.4
-109.6
-109.8
-110
T
= 25°C,
A
T
= 25°C,
T
= 25°C,
93
92.5
92
A
A
V
= 4.096 V,
ref
V
= 4.096 V,
f
= 1 MSPS,
ref
S
f = 2 kHz
I
f = 2 kHz
I
f = 2 kHz
I
92.5
92
SNR
SINAD
-110.2
-110.4
-110.6
91.5
91
91.5
91
-110.8
-111
-40 -25 -10
5
20 35 50 65 80
3
3.2
3.4
3.6
3.8
4
4.2
3
3.2
3.4
3.6
3.8
4
4.2
V
- Reference Voltage - V
V
- Reference Voltage - V
T
- Free-Air Temperature - °C
ref
ref
A
Figure 22.
Figure 23.
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
SPURIOUS FREE DYNAMIC RANGE
SIGNAL-TO-NOISE RATIO
vs
FREE-AIR TEMPERATURE
SIGNAL-TO-NOISE + DISTORTION
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
113
112.8
112.6
112.4
93.05
93
93.05
+VA = 5 V,
+VBD = 5 V,
+VA = 5 V,
+VBD = 5 V,
93
92.95
92.9
f
= 1 MSPS,
f
= 1 MSPS,
S
S
92.95
92.9
92.85
92.8
92.75
92.7
V
= 4.096 V,
V
= 4.096 V,
ref
ref
f = 2 kHz
I
f = 2 kHz
I
SNR
112.2
92.85
92.8
112
SINAD
+VA = 5 V,
+VBD = 5 V,
111.8
f
= 1 MSPS,
S
92.75
92.7
111.6
111.4
V
= 4.096 V,
ref
f = 2 kHz
I
92.65
92.6
92.65
92.6
111.2
111
-40 -25 -10
5
20 35 50 65 80
-40 -25 -10
5
20 35 50 65 80
-40 -25 -10
5
20 35 50 65 80
T
- Free-Air Temperature - °C
T
- Free-Air Temperature - °C
T
- Free-Air Temperature - °C
A
A
A
Figure 25.
Figure 26.
Figure 27.
0.75
+VA = 5 V, +VBD = 5 V,
T
= 25°C, f = 1 MSPS,
S
= 4.096 V,
A
0.5
0.25
0
V
ref
-0.25
-0.5
-0.75
0
8192
16384
24576
32768
40960
49152
57344
65536
Output Code
Figure 28.
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
+VA = 5 V, +VBD = 5 V,
= 25°C, f = 1 MSPS,
S
T
-0.6
A
V
= 4.096 V,
-0.8
-1
ref
0
8192
16384
24576
32768
40960
49152
57344
65536
Output Code
Figure 29.
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TYPICAL CHARACTERISTICS (continued)
0
+VA = 5 V +VBD = 5 V,
= 25°C, f = 1 MSPS,
T
A
S
= 4.096 V, Points = 65536,
-50
V
ref
Amplitude = 4 V
PP
-100
-150
-200
0
50000 100000 150000 200000 250000 300000 350000 400000 450000 500000
f - Frequency - Hz
Figure 30.
TIMING DIAGRAMS
t
w2
t
w1
CONVST
t
t
pd1
pd2
t
w4
t
w3
BUSY
t
t
w7
su1
CS
t
pd3
†
CONVERT
t
(CONV)
t
(CONV)
t
(HOLD)
†
SAMPLING
(When CS Toggle)
t
(ACQ)
t
t
su(ABORT)
su(ABORT)
t
su5
BYTE
t
su5
t
su5
t
h1
t
su5
t
su2
t
pd4
t
h2
t
d1
RD
t
dis
t
en
Hi−Z
Hi−Z
Hi−Z
Hi−Z
DB[15:8]
D[15:8]
D[7:0]
D[7:0]
DB[7:0]
†
Signal internal to device
Figure 31. Timing for Conversion and Acquisition Cycles With CS and RD Toggling
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TYPICAL CHARACTERISTICS (continued)
t
w1
t
w2
CONVST
BUSY
t
t
pd2
pd1
t
w4
t
w3
t
w7
t
su6
CS
t
pd3
†
CONVERT
t
(CONV)
t
(CONV)
t
(HOLD)
†
SAMPLING
(When CS Toggle)
t
(ACQ)
t
t
su(ABORT)
su(ABORT)
t
su5
BYTE
t
su5
t
h1
t
su5
t
su5
t
dis
t
su2
t
pd4
t
h2
t
en
RD = 0
t
en
t
en
t
dis
Previous
D [15:8]
Previous
D [15:8]
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
DB[15:8]
D[15:8]
D[7:0]
D[7:0]
Previous
D [7:0]
Previous
D [7:0]
DB[7:0]
†
Signal internal to device
Figure 32. Timing for Conversion and Acquisition Cycles With CS Toggling, RD Tied to BDGND
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TYPICAL CHARACTERISTICS (continued)
t
w1
t
w2
CONVST
t
t
pd1
pd2
t
w4
t
w3
BUSY
CS = 0
t
pd3
†
CONVERT
t
(CONV)
t
(CONV)
t
(HOLD)
t
(ACQ)
†
SAMPLING
(When CS = 0)
t
t
su(ABORT)
su(ABORT)
t
su5
BYTE
t
su5
t
h1
t
pd4
t
h2
RD
t
dis
t
en
Hi−Z
Hi−Z
Hi−Z
Hi−Z
DB[15:8]
D[15:8]
D[7:0]
D[7:0]
DB[7:0]
†
Signal internal to device
Figure 33. Timing for Conversion and Acquisition Cycles With CS Tied to BDGND, RD Toggling
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TYPICAL CHARACTERISTICS (continued)
t
w2
t
w1
CONVST
t
t
pd2
pd1
t
w4
t
w3
BUSY
CS = 0
†
CONVERT
t
t
(CONV)
(CONV)
t
pd3
t
pd3
t
(HOLD)
t
(HOLD)
t
(ACQ)
†
SAMPLING
(When CS = 0)
t
t
su(ABORT)
su(ABORT)
BYTE
t
su5
t
su5
t
h1
t
h1
t
dis
t
su5
t
su5
RD = 0
t
d5
DB[15:8]
Previous D[7:0]
D[7:0]
Next D[15:8]
Next D[7:0]
D[15:8]
D[7:0]
DB[7:0]
†
Signal internal to device
Figure 34. Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGND - Auto Read
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TYPICAL CHARACTERISTICS (continued)
CS
RD
t
su4
BYTE
t
en
t
d3
t
dis
t
dis
t
en
Hi−Z
Hi−Z
Hi−Z
Valid
Valid
Valid
DB[15:0]
Figure 35. Detailed Timing for Read Cycles
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APPLICATION INFORMATION
ADS8471 TO A HIGH PERFORMANCE DSP INTERFACE
Figure 36 shows a parallel interface between the ADS8471 and a Texas instruments high performance DSP
such as the TMS320C6713 using the full 16-bit bus. The ADS8471 is mapped onto the CE2 memory space of
the TMS320C6713 DSP. The read and reset signals are generated by using a 3-to-8 decoder. A read operation
from the address 0xA000C000 generates a pulse on the RD pin of the data converter, wheras a read operation
form word address 0xA0014000 generates a pulse on the RESET/PD1 pin. The CE2 signal of the DSP acts as
CS (chip select) for the converter. As the TMS320C6713 features a 32-bit external memory interface, the BYTE
input of the converter can be tied permanently low, disabling the foldback of the data bus. The BUSY signal of
the ADS8471 is appiled to the EXT_INT6 interrupt input of the DSP, enabling the EDMA controller to react on the
falling edge of this signal and to collect the conversion result. The TOUT1 (timer out 1) pin of the TMS320C6713
is used to source the CONVST signal of the converter.
+VA = 5 V
0.1 mF
AGND
10 mF
Ext Ref
Input
1 mF
Analog
Input
CE2
CS
TMS320C6713
DSP
I/O Supply
+VBD +2.7 V
Address
Decoder
+VBD
ADS8471
RD
EA[16:14]
ARE
0.1 mF
BDGND
BYTE
TOUT1
CONVST
BUSY
EXT_INT6
ED[15:0]
I/O Digital Ground
DB[15:0]
BDGND
Figure 36. ADS8471 Application Circuitry
Analog 5 V
AGND
0.1 µF
10 µF
0.1 µF
1 µF
AGND
ADS8471
Figure 37. ADS8471 Using Internal Reference
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PRINCIPLES OF OPERATION
The ADS8471 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The
architecture is based on charge redistribution which inherently includes a sample/hold function. See Figure 36 for
the application circuit for the ADS8471.
The conversion clock is generated internally. The conversion time of 700 ns is capable of sustaining a 1-MHz
throughput.
The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential input
on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are
disconnected from any internal function.
REFERENCE
The ADS8471 can operate with an external reference with a range from 3.0 V to 4.2 V. The reference voltage on
the input pin 13 (REFIN) of the converter is internally buffered. A clean, low noise, well-decoupled reference
voltage on this pin is required to ensure good performance of the converter. A low noise band-gap reference like
the REF5040 can be used to drive this pin. A 0.1-µF decoupling capacitor is required between REFIN and REFM
pins (pin 13 and pin 12) of the converter. This capacitor should be placed as close as possible to the pins of the
device. Designers should strive to minimize the routing length of the traces that connect the terminals of the
capacitor to the pins of the converter. An RC network can also be used to filter the reference voltage. A 100-Ω
series resistor and a 0.1-µF capacitor, which can also serve as the decoupling capacitor can be used to filter the
reference voltage.
REFM
ADS8471
0.1 mF
100 W
REFIN
REF5040
Figure 38. ADS8471 Using External Reference
The ADS8471 also has limited low pass filtering capability built into the converter. The equivalent circuitry on the
REFIN input is as shown in Figure 39.
10 kW
REFIN
+
_
To CDAC
300 pF
830 pF
REFM
To CDAC
Figure 39. Reference Circuit
The REFM input of the ADS8471 should always be shorted to AGND.
A 4.096-V internal reference is included. When internal reference is used, pin 14 (REFOUT) is connected to pin
13 (REFIN) with a 0.1-µF decoupling capacitor and 1-µF storage capacitor between pin 14 (REFOUT) and pins
11 and 12 (REFM) (see Figure 37). The internal reference of the converter is double buffered. If an external
reference is used, the second buffer provides isolation between the external reference and the CDAC. This buffer
is also used to recharge all of the capacitors of the CDAC during conversion. Pin 14 (REFOUT) can be left
unconnected (floating) if an external reference is used.
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ANALOG INPUT
When the converter enters the hold mode, the voltage difference between the +IN and –IN inputs is captured on
the internal capacitor array. The voltage on the -IN input is limited between –0.2 V and 0.2 V, allowing the input
to reject small signals which are common to both the +IN and –IN inputs. The +IN input has a range of –0.2 V to
Vref + 0.2 V. The input span [+IN – (–IN)] is limited to 0 V to Vref.
The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and source
impedance. Essentially, the current into the ADS8471 charges the internal capacitor array during the sample
period. After this capacitance has been fully charged, there is no further input current. The source of the analog
input voltage must be able to charge the input capacitance (65 pF) to an 16-bit settling level within the acquisition
time (270 ns) of the device. When the converter goes into the hold mode, the input impedance is greater than 1
GΩ.
Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the
+IN and –IN inputs and the span [+IN – (–IN)] must be within the limits specified. Outside of these ranges, the
converter's linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass
filters are used.
Care must be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are
matched. If this is not observed, the two inputs could have different settling times. This may result in offset error,
gain error, and linearity error which varies with temperature and input voltage.
The analog input to the converter needs to be driven with a low noise, high-speed op-amp like the THS4031. An
RC filter is recommended at the input pins to low-pass filter the noise from the source. A series resistor of 20 Ω
and a decoupling capacitor of 680 pF is recommended. The input to the converter is a uni-polar input voltage in
the range 0 to Vref. The THS4031 can be used in the source follower configuration to drive the converter (see
Figure 40).
Low-Pass Filter
V
+
20 W
IN
THS4031
_
INP
50 W
ADS8471
680 pF
INM
Figure 40. Unipolar Input Driving Circuit
In systems, where the input is bi-polar, the THS4031 can be used in the inverting configuration with an additional
DC bias applied to its + input so as to keep the input to the ADS8471 within its rated operating voltage range
(see Figure 41). This configuration is also recommended when the ADS8471 is used in signal processing
applications where good SNR and THD performance is required. The DC bias can be derived from the REF3220
or the REF5040 reference voltage ICs. The input configuration shown below is capable of delivering better than
91dB SNR and -100db THD at an input frequency of 100 kHz. In case band-pass filters are used to filter the
input, care should be taken to ensure that the signal swing at the input of the band-pass filter is small so as to
keep the distortion introduced by the filter minimal. In such cases, the gain of the circuit shown below can be
increased to keep the input to the ADS8471 large to keep the SNR of the system high. Note that the gain of the
system from the + input to the output of the THS4031 in such a configuration is a function of the gain of the AC
signal. A resistor divider can be used to scale the output of the REF3220 or REF5040 to reduce the voltage at
the DC input to THS4031 to keep the voltage at the input of the converter within its rated operating range.
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Bipolar to Unipolar Conversion
Low-Pass Filter
380 W
_
V
IN
20 W
380 W
THS4031
INP
+
Vdc
ADS8471
680 pF
INM
Figure 41. Bipolar Input Driving Circuit
DIGITAL INTERFACE
Timing and Control
See the timing diagrams in the specifications section for detailed information on timing signals and their
requirements.
The ADS8471 uses an internal oscillator generated clock which controls the conversion rate and in turn the
throughput of the converter. No external clock input is required.
Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum
requirement has been met, the CONVST pin can be brought high), while CS is low. The ADS8471 switches from
the sample to the hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge of
this signal is important to the performance of the converter. The BUSY output is brought high immediately
following CONVST going low. BUSY stays high throughout the conversion process and returns low when the
conversion has ended.
Sampling starts with the falling edge of the BUSY signal when CS is tied low or starts with the falling edge of CS
when BUSY is low.
Both RD and CS can be high during and before a conversion with one exception (CS must be low when
CONVST goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the
parallel output bus with the conversion.
Reading Data
The ADS8471 outputs full parallel data in straight binary format as shown in Table 1. The parallel output is active
when CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of CONVST.
This is 50 ns prior to the falling edge of CONVST and 40 ns after the falling edge. No data read should attempted
within this zone. Any other combination of CS and RD sets the parallel output to 3-state. BYTE is used for
multiword read operations. BYTE is used whenever lower bits on the bus are output on the higher byte of the
bus. Refer to Table 1 for ideal output codes.
Copyright © 2007, Texas Instruments Incorporated
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ADS8471
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SLAS517–DECEMBER 2007
Table 1. Ideal Input Voltages and Output Codes
DESCRIPTION
ANALOG VALUE
DIGITAL OUTPUT STRAIGHT BINARY
Full scale range
Least significant bit (LSB)
+Full scale
+Vref
+Vref/65536
(+Vref) – 1 LSB
+Vref/2
BINARY CODE
HEX CODE
FFFF
1111 1111 1111 1111
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
Midscale
8000
Midscale – 1 LSB
Zero
+Vref/2 – 1 LSB
0 V
7FFF
0000
The output data is a full 16-bit word (D15–D0) on DB15–DB0 pins (MSB–LSB) if BYTE is low.
The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB15–DB8. In this
case two reads are necessary: the first as before, leaving BYTE low and reading the 8 most significant bits on
pins DB15–DB8, then bringing BYTE high. When BYTE is high, the low bits (D7–D0) appear on pins DB15–DB8.
All of these multiword read operations can be performed with multiple active RD (toggling) or with RD held low
for simplicity. This is referred to as the AUTO READ operation.
Table 2. Conversion Data Read Out
DATA READ OUT
BYTE
PINS
PINS
DB15–DB8
DB7–DB0
High
Low
D7-D0
All One's
D7–D0
D15-D8
RESET
On power-up, internal POWER-ON RESET circuitry generates the reset required for the device. The first three
conversions after power-up are used to load factory trimming data for a specific device to assure high accuracy
of the converter. The results of the first three conversions are invalid and should be discarded.
The device can also be reset through the use of the combination of CS and CONVST. Since the BUSY signal is
held at high during the conversion, either one of these conditions triggers an internal self-clear reset to the
converter.
•
Issue a CONVST when CS is low and the internal convert state is high. The falling edge of CONVST starts a
reset.
•
Issue a CS (select the device) while the internal convert state is high. The falling edge of CS causes a reset.
Once the device is reset, all output latches are cleared (set to zeroes) and the BUSY signal is brought low. A
new sampling period is started at the falling edge of the BUSY signal immediately after the instant of the internal
reset.
22
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Product Folder Link(s): ADS8471
ADS8471
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SLAS517–DECEMBER 2007
LAYOUT
For optimum performance, care must be taken with the physical layout of the ADS8471 circuitry.
As the ADS8471 offers single-supply operation, it is often used in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and
the higher the switching speed, the more difficult it is to achieve good performance from the converter.
The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground
connections and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving
any single conversion for an n-bit SAR converter, there are at least n windows in which large external transient
voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby
digital logic, or high power devices.
The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the
external event.
On average, the ADS8471 draws very little current from an external reference as the reference voltage is
internally buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive
the bypass capacitor or capacitors without oscillation. A 0.1-µF capacitor is recommended from pin 13 (REFIN)
directly to pin 12 (REFM). REFM and AGND must be shorted on the same ground plane under the device.
The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the
analog ground. Avoid connections which are too close to the grounding point of a microcontroller or digital signal
processor. If required, run a ground trace directly from the converter to the power supply entry point. The ideal
layout consists of an analog ground plane dedicated to the converter and associated analog circuitry.
As with the AGND connections, +VA should be connected to a 5-V power supply plane or trace that is separate
from the connection for digital logic until they are connected at the power entry point. Power to the ADS8471
should be clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to the device
as possible. See Table 3 for the placement of the capacitor. In addition, a 1-µF to 10-µF capacitor is
recommended. In some situations, additional bypassing may be required, such as a 100-µF electrolytic capacitor
or even a Pi filter made up of inductors and capacitors—all designed to essentially low-pass filter the 5-V supply,
removing the high frequency noise.
Table 3. Power Supply Decoupling Capacitor Placement
POWER SUPPLY PLANE
SUPPLY PINS
CONVERTER
DIGITAL SIDE
CONVERTER ANALOG SIDE
Pin pairs that require shortest path to decoupling capacitors
Pins that require no decoupling
(7,8), (9,10), (16,17), (20,21), (22,23), (25,26)
24, 26
36, 37
1,2
Copyright © 2007, Texas Instruments Incorporated
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Product Folder Link(s): ADS8471
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
PACKAGING INFORMATION
Orderable Device
ADS8471IBRGZT
ADS8471IRGZT
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ACTIVE
VQFN
VQFN
RGZ
48
48
250
RoHS & Green
RoHS & Green
Call TI
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
ADS
8471I
B
ACTIVE
RGZ
250
Call TI
-40 to 85
ADS
8471I
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
GENERIC PACKAGE VIEW
RGZ 48
7 x 7, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A
www.ti.com
PACKAGE OUTLINE
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
A
7.1
6.9
B
(0.1) TYP
7.1
6.9
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
PIN 1 INDEX AREA
(0.45) TYP
CHAMFERED LEAD
CORNER LEAD OPTION
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 5.5
5.15±0.1
(0.2) TYP
13
24
44X 0.5
12
25
SEE SIDE WALL
DETAIL
SYMM
2X
5.5
1
36
0.30
0.18
PIN1 ID
(OPTIONAL)
48X
48
37
SYMM
0.1
C A B
C
0.5
0.3
48X
0.05
SEE LEAD OPTION
4219044/D 02/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
5.15)
SYMM
(
48X (0.6)
37
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(1.26)
2X
(1.065)
(R0.05)
TYP
25
12
21X (Ø0.2) VIA
TYP
24
13
2X (1.065)
2X (1.26)
2X (5.5)
LAND PATTERN EXAMPLE
SCALE: 15X
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219044/D 02/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
SYMM
(
1.06)
37
48X (0.6)
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(0.63)
2X
(1.26)
(R0.05)
TYP
25
12
24
13
2X
(1.26)
2X (0.63)
2X (5.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
67% PRINTED COVERAGE BY AREA
SCALE: 15X
4219044/D 02/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
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