ADS8504IBDWR [TI]
具有并行接口 2.5V 内部基准的 12 位 250kHz CMOS 模数转换器 | DW | 28 | -40 to 85;
| 型号： | ADS8504IBDWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有并行接口 2.5V 内部基准的 12 位 250kHz CMOS 模数转换器 | DW | 28 | -40 to 85 光电二极管 转换器 模数转换器 |
| 文件： | 总25页 (文件大小：1011K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
B
u
r
r
Ć
B
r
o
w
n
P
r
o
d
u
c
t
s
f
r
o
m
T
e
x
a
s
I
n
s
t
r
u
m
e
n
t
s
ADS8504
SLAS434A–JUNE 2005–REVISED JUNE 2007
12-BIT 250-KSPS SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER
FEATURES
APPLICATIONS
•
•
•
•
•
Industrial Process Control
Data Acquisition Systems
Digital Signal Processing
Medical Equipment
•
•
•
•
•
•
•
•
•
•
250-kHz Sampling Rate
Standard ±10-V Input Range
73-dB SINAD With 45-kHz Input
±0.45 LSB Max INL
Instrumentation
±0.45 LSB Max DNL
12 Bit No Missing Code
DESCRIPTION
±1 LSB Bipolar Zero Errors
±0.4 PPM/°C Bipolar Zero Error Drift
Single 5-V Supply Operation
The ADS8504 is a complete 12-bit sampling A/D
converter using state-of-the-art CMOS structures. It
contains a complete 12-bit, capacitor-based, SAR
A/D with S/H, reference, clock, interface for
microprocessor use, and 3-state output drivers.
Pin-Compatible With ADS7804/05 (Low Speed)
and 16-Bit ADS8505
The ADS8504 is specified at a 250-kHz sampling
rate over the full temperature range. Precision
resistors provide an industry standard ±10-V input
range, while the innovative design allows operation
from a single +5-V supply, with power dissipation
under 100 mW.
•
•
•
•
Uses Internal or External Reference
Full Parallel Data Output
70-mW Typ Power Dissipation at 250 KSPS
28-Pin SOIC Package
The ADS8504 is available in a 28-pin SOIC package
and is fully specified for operation over the industrial
-40°C to 85°C temperature range.
R/C
CS
Clock
Successive Approximation Register and Control Logic
BYTE
BUSY
CDAC
Output
Latches
and
Three
State
Three
State
Parallel
Data
9.8 kΩ
± 10 V Input
2 kΩ
5 kΩ
Comparator
Bus
Drivers
CAP
Internal
+2.5 V Ref
Buffer
4 kΩ
REF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2007, Texas Instruments Incorporated
ADS8504
www.ti.com
SLAS434A–JUNE 2005–REVISED JUNE 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PACKAGE/ORDERING INFORMATION(1)
MINIMUM
NO
MISSING
CODE
MINIMUM
SINAD
(dB)
SPECIFICATION
TEMPERATURE
RANGE
RELATIVE
ACCURACY
(LSB)
PACKAGE
LEAD
PACKAGE
DESIGNATOR
ORDERING
NUMBER
TRANSPORT
MEDIA, QTY
PRODUCT
ADS8504IBDW
Tube, 20
Tape and Reel, 1000
ADS8504IB
±0.45
12
72
-40°C to 85°C
SO-28
DW
ADS8504IBDWR
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)(2)
ADS8504
Analog inputs
VIN
±25V
CAP
+VANA + 0.3 V to AGND2 - 0.3 V
REF
Indefinite short to AGND2, momentary short to VANA
Ground voltage differences
DGND, AGND1, AGND2
±0.3 V
VANA
6 V
VDIG to VANA
VDIG
0.3 V
6 V
Digital inputs
-0.3 V to +VDIG + 0.3 V
165°C
Maximum junction temperature
Internal power dissipation
825 mW
Lead temperature (soldering, 1,6mm from case, 10 seconds)
260°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
ELECTRICAL CHARACTERISTICS
TA = -40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, using internal reference (unless otherwise noted)
PARAMETER
Resolution
ANALOG INPUT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
12
Bits
Voltage range
Impedance
±10
11.5
50
V
kΩ
pF
Capacitance
THROUGHPUT SPEED
Conversion cycle
Throughput rate
DC ACCURACY
Acquire and convert
4
µs
250
kHz
INL
Integral linearity error
Differentiall linearity error
No missing codes
-0.45
-0.45
12
0.45
0.45
LSB(1)
LSB(1)
Bits
DNL
Transition noise(2)
0.1
LSB
(1) LSB means least significant bit. For the 12-bit, ±10-V input ADS8504, one LSB is 4.88 mV.
(2) Typical rms noise at worst case transitions and temperatures.
2
Submit Documentation Feedback
ADS8504
www.ti.com
SLAS434A–JUNE 2005–REVISED JUNE 2007
ELECTRICAL CHARACTERISTICS (continued)
TA = -40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, using internal reference (unless otherwise noted)
PARAMETER
Full-scale error(3)(4)
TEST CONDITIONS
Int. Ref.
MIN
TYP
MAX
UNIT
%FSR
ppm/°C
%FSR
ppm/°C
LSB
-0.25
0.25
Full-scale error drift
Full-scale error(3)(4)
Full-scale error drift
Bipolar zero error(3)
Bipolar zero error drift
Int. Ref.
±7
Ext. 2.5-V Ref.
Ext. 2.5-V Ref.
-0.25
-1
0.25
1
±2
±0.4
ppm/°C
Power supply sensitivity
(VDIG = VANA = VD)
-0.5
0.5
+4.75 V < VD < +5.25 V
LSB
AC ACCURACY
SFDR
THD
Spurious-free dynamic range
Total harmonic distortion
fI = 45 kHz
fI = 45 kHz
fI = 45 kHz
–60-dB Input
fI = 45 kHz
86
72
72
94
-95
73
dB(5)
dB
-86
dB
SINAD
SNR
Signal-to-(noise+distortion)
32
dB
Signal-to-noise ratio
73
dB
Full-power bandwidth(6)
500
kHz
SAMPLING DYNAMICS
Aperture delay
5
ns
µs
ns
Transient response
Overvoltage recovery(7)
REFERENCE
FS Step
2
150
Internal reference voltage
2.48
2.3
2.5
1
2.52
V
µA
Internal reference source current (must use
external buffer)
Internal reference drift
8
ppm/°C
V
External reference voltage range for specified
linearity
2.5
2.7
External reference current drain
Ext. 2.5-V Ref.
100
µA
DIGITAL INPUTS
Logic levels
VIL
VIH
IIL
Low-level input voltage
High-level input voltage
Low-level input current
High-level input current
-0.3
2.0
0.8
VDIG +0.3 V
±10
V
V
µA
µA
IIH
±10
DIGITAL OUTPUTS
Data format (Parallel 12-bits)
Data coding (Binary 2's complement)
Low-level output voltage
High-level output voltage
Leakage current
VOL
VOH
ISINK = 1.6 mA
0.4
V
V
ISOURCE = 500 µA
Hi-Z state, VOUT = 0 V to VDIG
Hi-Z state
4
±5
µA
pF
Output capacitance
15
DIGITAL TIMING
Bus access timing
83
ns
(3) As measured with fixed resistors shown in Figure 24. Adjustable to zero with external potentiometer.
(4) Full-scale error is the worst case of -full-scale or +full-scale deviation from ideal first and last code transitions, divided by the transition
voltage (not divided by the full-scale range) and includes the effect of offset error.
(5) All specifications in dB are referred to a full-scale ±10-V input.
(6) Full-power bandwidth is defined as the full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 dB, or 10 bits of
accuracy.
(7) Recovers to specified performance after 2 x FS input overvoltage.
3
Submit Documentation Feedback
ADS8504
www.ti.com
SLAS434A–JUNE 2005–REVISED JUNE 2007
ELECTRICAL CHARACTERISTICS (continued)
TA = -40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, using internal reference (unless otherwise noted)
PARAMETER
Bus relinquish timing
POWER SUPPLIES
TEST CONDITIONS
MIN
TYP
MAX
UNIT
83
ns
VDIG
VANA
IDIG
Digital input voltage
Analog input voltage
Digital input current
Analog input current
Power dissipation
4.75
4.75
5
5
5.25
5.25
V
V
Must be ≤ VANA
4
mA
mA
mW
IANA
10
70
fS = 250 kHz
100
TEMPERATURE RANGE
Specified performance
-40
-55
-65
85
125
150
°C
°C
°C
Derated performance(8)
Storage
THERMAL RESISTANCE (ΘJA
)
SO
46
°C/W
(8) The internal reference may not be started correctly beyond the industrial temperature range (-40°C to 85°C), therefore use of an
external reference is recommended.
DEVICE INFORMATION
DW PACKAGE
(TOP VIEW)
V
1
2
3
4
5
6
7
8
9
28 V
DIG
IN
AGND1
REF
27 V
ANA
26
BUSY
CAP
25 CS
AGND2
D11 (MSB)
D10
24 R/C
23
BYTE
22 DZ
21
20
D9
DZ
DZ
D8
D7 10
19 DZ
11
18
17
D0 (LSB)
D1
D6
12
D5
13
14
16 D2
15
D4
D3
DGND
4
Submit Documentation Feedback
ADS8504
www.ti.com
SLAS434A–JUNE 2005–REVISED JUNE 2007
DEVICE INFORMATION (continued)
Terminal Functions
TERMINAL
DIGITAL
DESCRIPTION
I/O
NAME
AGND1
DW NO.
2
5
Analog ground. Used internally as ground reference point.
AGND2
BUSY
Analog ground.
26
O
I
At the start of a conversion, BUSY goes low and stays low until the conversion is
completed and the digital outputs have been updated.
BYTE
CAP
23
4
Selects 8 most significant bits (low) or 8 least significant bits (high).
Reference buffer capacitor. 2.2-µF tantalum capacitor to ground.
Internally ORed with R/C. If R/C low, a falling edge on CS initiates a new conversion.
Digital ground.
CS
25
14
6
I
DGND
D11 (MSB)
O
Data bit 11. Most significant bit (MSB) of conversion results. Hi-Z state when CS is
high, or when R/C is low.
D10
D9
7
O
O
O
O
O
O
O
O
O
O
O
Data bit 10. Hi-Z state when CS is high, or when R/C is low.
Data bit 9. Hi-Z state when CS is high, or when R/C is low.
Data bit 8. Hi-Z state when CS is high, or when R/C is low.
Data bit 7. Hi-Z state when CS is high, or when R/C is low.
Data bit 6. Hi-Z state when CS is high, or when R/C is low.
Data bit 5. Hi-Z state when CS is high, or when R/C is low.
Data bit 4. Hi-Z state when CS is high, or when R/C is low.
Data bit 3. Hi-Z state when CS is high, or when R/C is low.
Data bit 2. Hi-Z state when CS is high, or when R/C is low.
Data bit 1. Hi-Z state when CS is high, or when R/C is low.
8
D8
9
D7
10
11
12
13
15
16
17
18
D6
D5
D4
D3
D2
D1
D0 (LSB)
Data bit 0. Least significant bit (LSB) of conversion results. Hi-Z state when CS is high,
or when R/C is low.
DZ
DZ
DZ
DZ
R/C
19
20
21
22
24
O
O
O
O
I
Low when CS low, R/C high. Hi-Z state when CS is high, or when R/C is low.
Low when CS low, R/C high. Hi-Z state when CS is high, or when R/C is low.
Low when CS low, R/C high. Hi-Z state when CS is high, or when R/C is low.
Low when CS low, R/C high. Hi-Z state when CS is high, or when R/C is low.
With CS low and BUSY high, a falling edge on R/C initiates a new conversion. With CS
low, a rising edge on R/C enables the parallel output.
REF
3
Reference input/output. 2.2-µF tantalum capacitor to ground.
VANA
27
Analog supply input. Nominally +5 V. Decouple to ground with 0.1-µF ceramic and
10-µF tantalum capacitors.
VDIG
VIN
28
1
Digital supply input. Nominally +5 V. Connect directly to pin 27. Must be ≤ VANA.
Analog input.
5
Submit Documentation Feedback
ADS8504
www.ti.com
SLAS434A–JUNE 2005–REVISED JUNE 2007
Typical Characteristics
SPURIOUS FREE DYNAMIC RANGE
TOTAL HARMONIC DISTORTION
vs
SIGNAL-TO-NOISE RATIO
vs
FREE-AIR TEMPERATURE
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
110
80
70
60
−100
f = 45 kHz
i
−95
−90
−85
−80
−75
−70
100
90
80
50
40
f = 45 kHz
i
70
−40
−20
0
20
40
60
80
−40
−20
0
20
40
60
80
−40
−20
0
20
40
60
80
T
A
− Free-Air-Temperature − 5C
T
A
− Free-Air-Temperature − 5C
T
A
− Free-Air-Temperature − 5C
Figure 1.
Figure 2.
Figure 3.
SIGNAL-TO-NOISE
AND DISTORTION
vs
SIGNAL-TO-NOISE
AND DISTORTION
vs
SIGNAL-TO-NOISE RATIO
vs
FREE-AIR TEMPERATURE
INPUT FREQUENCY
INPUT FREQUENCY
80
75
70
65
60
55
50
80
80
75
70
65
60
55
50
70
60
50
40
f = 45 kHz
i
−40
−20
0
20
40
60
80
1
10
100
1000
1
10
100
1000
T
A
− Free-Air-Temperature − 5C
f − Input Frequency − kHz
i
f − Input Frequency − kHz
i
Figure 4.
Figure 5.
Figure 6.
SPURIOUS FREE DYNAMIC RANGE
TOTAL HARMONIC DISTORTION
BIPOLAR ZERO ERROR
vs
FREE-AIR TEMPERATURE
vs
vs
INPUT FREQUENCY
INPUT FREQUENCY
100
5
−100
−90
−80
−70
−60
−50
−40
4
3
2
1
90
80
70
0
−1
−30
−20
−10
−2
−3
−4
−5
60
50
0
10
100
1000
1
10
100
1000
−40
−20
0
20
40
60
80
1
f − Input Frequency − kHz
i
5
f − Input Frequency − kHz
i
T
− Free-Air Temperature − C
A
Figure 7.
Figure 8.
Figure 9.
6
Submit Documentation Feedback
ADS8504
www.ti.com
SLAS434A–JUNE 2005–REVISED JUNE 2007
Typical Characteristics (continued)
NEGATIVE FULL-SCALE ERROR
POSITIVE FULL-SCALE ERROR
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
vs
FREE-AIR TEMPERATURE
20
19
18
17
16
15
14
13
12
11
10
0.25
0.2
0.25
0.2
0.15
0.1
0.15
0.1
0.05
0.05
0
−0.05
−0.1
0
−0.05
−0.1
−0.15
−0.2
−0.15
−0.2
−0.25
−0.25
−40
−20
0
20
40
60
80
−40
−20
0
20
40
60
80
−40
−20
0
20
40
60
80
5
5
T
− Free-Air Temperature −
C
5
T
− Free-Air Temperature −
C
T
− Free-Air Temperature − C
A
A
A
Figure 10.
Figure 11.
Figure 12.
INL
0.5
f
= 250 KSPS
0.4
0.3
0.2
0.1
s
0
−0.1
−0.2
−0.3
−0.4
−0.5
0
512
1024
1536
2048
2560
3072
3584
4096
Code
(Binary 2’s Complement in Decimal)
Figure 13.
DNL
0.5
0.4
0.3
0.2
0.1
f
= 250 KSPS
s
0
−0.1
−0.2
−0.3
−0.4
−0.5
0
512
1024
1536
2048
2560
3072
3584
4096
Code
(Binary 2’s Complement in Decimal)
Figure 14.
7
Submit Documentation Feedback
ADS8504
www.ti.com
SLAS434A–JUNE 2005–REVISED JUNE 2007
Typical Characteristics (continued)
FFT
20
0
8192 Points
= 250 KSPS
f
s
f = 1 kHz, 0dB
SINAD = 73.47 dB
THD = −94.03 dB
i
−20
−40
−60
−80
−100
−120
−140
−160
0
25
50
75
100
125
f − Frequency − Hz
Figure 15.
FFT
20
8192 Points
0
−20
f
= 250 KSPS
s
f = 45 kHz, 0dB
SINAD = 73.62 dB
THD = −94.03 dB
i
−40
−60
−80
−100
−120
−140
−160
0
25
50
75
100
125
f − Frequency − Hz
Figure 16.
BASIC OPERATION
Figure 17 shows a basic circuit to operate the ADS8504 with a full parallel data output. Taking R/C (pin 24) low
for a minimum of 40 ns (1.75 µs max if BUSY is used to latch the data) initiates a conversion. BUSY (pin 26)
goes low and stays low until the conversion is completed and the output registers are updated. Data is output in
binary 2's complement with the MSB on pin 6. BUSY going high can be used to latch the data.
The ADS8504 begins tracking the input signal at the end of the conversion. Allowing 4 µs between convert
commands assures accurate acquisition of a new signal.
The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors
compensate for this adjustment and can be left out if the offset and gain are corrected in software (refer to the
Calibration section).
STARTING A CONVERSION
The combination of CS (pin 25) and R/C (pin 24) low for a minimum of 40 ns immediately puts the sample/hold
of the ADS8504 in the hold state and starts conversion n. BUSY (pin 26) goes low and stays low until
conversion n is completed and the internal output register has been updated. All new convert commands during
BUSY low will abort the conversion in progress and reset the ADC (see Figure 22).
The ADS8504 begins tracking the input signal at the end of the conversion. Allowing 4 µs between convert
commands assures accurate acquisition of a new signal. Refer to Table 1 for a summary of CS, R/C, and BUSY
states and Figure 19, Figure 20, and Figure 21 for the timing diagrams.
8
Submit Documentation Feedback
ADS8504
www.ti.com
SLAS434A–JUNE 2005–REVISED JUNE 2007
BASIC OPERATION (continued)
CS and R/C are internally ORed and level triggered. There is not a requirement which input goes low first when
initiating a conversion. If, however, it is critical that CS or R/C initiates conversion n, be sure the less critical
input is low at least 10 ns prior to the initiating input.
To reduce the number of control pins, CS can be tied low using R/C to control the read and convert modes. The
parallel output becomes active whenever R/C goes high. Refer to the READING DATA section.
Table 1. Control Line Functions for Read and Convert
CS
1
R/C
X
0
BUSY
OPERATION
X
1
1
↑
None. Databus is in Hi-Z state.
↓
Initiates conversion n. Databus remains in Hi-Z state.
0
↓
Initiates conversion n. Databus enters Hi-Z state.
0
1
Conversion n completed. Valid data from conversion n on the databus.
↓
1
1
0
0
↑
Enables databus with valid data from conversion n.
↓
1
Enables databus with valid data from conversion n-1(1). Conversion n in progress.
Enables databus with valid data from conversion n-1(1). Conversion n in progress.
Data is invalid. CS and/or R/C must be high when BUSY goes high.
Conversion n is halted. Causes ADC to reset.(2)
0
↑
0
0
X
↓
0
(1) See Figure 19 and Figure 20 for constraints on data valid from conversion n-1.
(2) See Figure 22 for details on ADC reset.
200 Ω
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+5V
10 µF
+
+
33.2 kΩ
0.1 µF
3
+
2.2 µF
BUSY
R/C
4
+
Convert Pulse
40 ns Min
2.2 µF
5
6
D11 (MSB)
D10
7
DZ Low
DZ Low
DZ Low
DZ Low
D0 (LSB)
D1
ADS8504
8
D9
9
D8
D7
D6
D5
D4
10
11
12
13
14
D2
D3
Figure 17. Basic Operation
READING DATA
The ADS8504 outputs full or byte-reading parallel data in binary 2's complement data output format. The parallel
output is active when R/C (pin 24) is high and CS (pin 25) is low. Any other combination of CS and R/C 3-states
the parallel output. Valid conversion data can be read in a full parallel, 12-bit word or two 8-bit bytes on pins
6-13 and pins 15-22. BYTE (pin 23) can be toggled to read both bytes within one conversion cycle. Refer to
Table 2 for ideal output codes and Figure 18 for bit locations relative to the state of BYTE.
9
Submit Documentation Feedback
ADS8504
www.ti.com
SLAS434A–JUNE 2005–REVISED JUNE 2007
Table 2. Ideal Input Voltages and Output Codes
DIGITAL OUTPUT BINARY 2's COMPLEMENT
DESCRIPTION
ANALOG INPUT
BINARY CODE
HEX CODE
Full-scale range
Least significant bit (LSB)
Full scale (10 V-1 LSB)
Midscale
±10 V
4.88 mV
9.99512 V
0 V
0111 1111 1111
0000 0000 0000
1111 1111 1111
1000 0000 0000
7FF
000
FFF
800
One LSB below midscale
-Full scale
-4.88 mV
-10 V
PARALLEL OUTPUT (After a Conversion)
After conversion n is completed and the output registers have been updated, BUSY (pin 26) goes high. Valid
data from conversion n is available on D11-D0 (pins 6-13 and 15-18). BUSY going high can be used to latch the
data. Refer to Table 3 and Figure 19, Figure 20, and Figure 21 for timing specifications.
PARALLEL OUTPUT (During a Conversion)
After conversion n has been initiated, valid data from conversion n-1 can be read and is valid up to t2 (2.2 µs
typ) after the start of conversion n. Do not attempt to read data from t2 (2.2 µs typ) after the start of conversion n
until BUSY (pin 26) goes high; this may result in reading invalid data. Refer to Table 3 and Figure 19, Figure 20,
and Figure 21 for timing specifications.
Note: For the best possible performance, data should not be read during a conversion. The switching noise of
the asynchronous data transfer can cause digital feedthrough degrading the converter's performance.
The number of control lines can be reduced by tying CS low while using the falling edge of R/C to initiate
conversions and the rising edge of R/C to activate the output mode of the converter. See Figure 19.
Table 3. Conversion Timing
SYMBOL DESCRIPTION
tw1 Pulse duration, convert
ta
MIN
TYP
MAX
1750
3.2
UNITS
ns
40
Access time, data valid after R/C low
Propagation delay time, BUSY from R/C low
Pulse duration, BUSY low
2.2
15
µs
ns
tpd
tw2
td1
td2
tconv
tacq
tdis
td3
tv
25
2.2
µs
ns
Delay time, BUSY after end of conversion
Delay time, aperture
5
5
ns
Conversion time
2.2
83
µs
µs
ns
Acquisition time
1.8
10
Disable time, bus
30
50
2
Delay time, BUSY after data valid
Valid time, previous data remains valid after R/C low
35
ns
1.5
µs
µs
ns
tconv + tacq Throughput time
4
tsu
tc
Setup time, R/C to CS
10
4
Cycle time between conversions
Enable time, bus
µs
ns
ten
td4
10
5
30
10
83
30
Delay time, BYTE
ns
10
Submit Documentation Feedback
ADS8504
www.ti.com
SLAS434A–JUNE 2005–REVISED JUNE 2007
BYTE LOW
ADS8504
BYTE HIGH
+5 V
Bit 4
Bit 11 (MSB)
Bit 10
6
7
23
22
21
20
19
18
17
16
15
6
23
22
21
20
19
18
17
16
15
Bit 3
Bit 2
Bit 1
Bit 0
Low
Low
Low
Low
7
Low
ADS8504
Bit 9
8
8
Bit 5
Low
Bit 8
9
9
Bit 6
Low
Bit 7
10
10
11
12
13
14
Bit 7
Low
Bit 6 11
Bit 5 12
Bit 8
Bit 0 (LSB)
Bit 1
Bit 9
Bit 4
13
14
Bit 10
Bit 11 (MSB)
Bit 2
Bit 3
Figure 18. Bit Locations Relative to State of BYTE (Pin 23)
t
w1
R/C
t
c
t
a1
t
w2
BUSY
MODE
t
t
pd
t
d1
d2
Acquire
Convert
t
Acquire
Convert
t
conv
acq
Previous
Data Valid
Previous
Data Valid
Hi−Z
Not Valid Data Valid
Hi−Z
Data Valid
DATA BUS
t
d3
t
dis
t
v
Figure 19. Conversion Timing with Outputs Enabled after Conversion (CS Tied Low)
t
su
t
su
t
su
t
su
R/C
CS
t
w1
t
pd
t
w2
BUSY
MODE
t
d2
Convert
conv
Acquire
Acquire
t
Hi−Z State
Data Valid
DATA BUS
Hi−Z State
t
en
t
dis
Figure 20. Using CS to Control Conversion and Read Timing
11
Submit Documentation Feedback
ADS8504
www.ti.com
SLAS434A–JUNE 2005–REVISED JUNE 2007
t
su
t
su
R/C
CS
BYTE
Pins 6 − 13 Hi−Z
Pins 15 − 18 Hi−Z
High Byte
Low Byte
Hi−Z
t
en
t
d4
t
dis
Low Byte
High Byte
Hi−Z
Figure 21. Using CS and BYTE to Control Data Bus
tc
tw1
tw1
R/C
tpd
tpd
BUSY
0 ns MIN
4.75V
VANA
VDIG
Unknown
Hi-Z
Not Valid
Hi-Z
Not Valid
Data Valid
td3
DATA BUS
Figure 22. ADC Reset
ADC RESET
The ADC reset function of the ADS8504 can be used to terminate the current conversion cycle. Bringing R/C low
for at least 40 ns while BUSY is low will initiate the ADC reset. To initiate a new conversion, R/C must return to
the high state and remain high long enough to acquire a new sample (see Table 3, tc) before going low to initiate
the next conversion sequence. In applications that do not monitor the BUSY signal, it is recommended that the
ADC reset function be implemented as part of a system initialization sequence.
INPUT RANGES
The ADS8504 offers a standard ±10-V input range. Figure 24 shows the necessary circuit connections for the
ADS8504 with and without hardware trim. Offset and full-scale error specifications are tested and specified with
the fixed resistors shown in Figure 24(b). Full-scale error includes offset and gain errors measured at both +FS
and -FS. Adjustments for offset and gain are described in the Calibration section of this data sheet.
The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors
compensate for this adjustment and can be left out if the offset and gain are corrected in software (refer to the
Calibration section).
12
Submit Documentation Feedback
ADS8504
www.ti.com
SLAS434A–JUNE 2005–REVISED JUNE 2007
The nominal input impedance of 11.5 kΩ results from the combination of the internal resistor network shown on
the front page of the product data sheet and the external resistors. The input resistor divider network provides
inherent overvoltage protection assured to at least ±25 V. The 1% resistors used for the external circuitry do not
compromise the accuracy or drift of the converter. They have little influence relative to the internal resistors, and
tighter tolerances are not required.
The input signal must be referenced to AGND1. This will minimize the ground loop problem typical to analog
designs. The analog input should be driven by a low impedance source. A typical driving circuit using OPA627
or OPA132 is shown in Figure 23.
+15V
2.2 mF
22 pF
ADS8504
200 W
100 nF
VIN
GND
2 kW
Pin 7
Pin 2
Pin1
2 kW
REF
Vin
−
OPA 627
22 pF
2.2 mF
or
33.2 kW
2.2 mF
Pin 6
OPA 132
+
AGND1
CAP
Pin3
Pin4
GND
2.2 mF
GND
DGND
GND
100 nF
GND
AGND2
−15V
GND
Figure 23. Typical Driving Circuitry (±10 V, No Trim)
13
Submit Documentation Feedback
ADS8504
www.ti.com
SLAS434A–JUNE 2005–REVISED JUNE 2007
APPLICATION INFORMATION
CALIBRATION
The ADS8504 can be trimmed in hardware or software. The offset should be trimmed before the gain since the
offset directly affects the gain. To achieve optimum performance, several iterations may be required.
Hardware Calibration
To calibrate the offset and gain of the ADS8504, install the proper resistors and potentiometers as shown in
Figure 24(a).
Software Calibration
To calibrate the offset and gain of the ADS8504 in software, no external resistors are required. See the No
Calibration section for details on the effects of the external resistors. Refer to Table 4 for range of offset and
gain errors with and without external resistors.
No Calibration
See Figure 24(b) for circuit connections. The external resistors shown in Figure 24(b) may not be necessary in
some applications. These resistors provide compensation for an internal adjustment of the offset and gain which
allows calibration with a single supply. Refer to Table 4 for range of offset and gain errors with and without
external resistors.
Table 4. Typical Offset (Bipolar Zero Error, BPZ) and Gain Errors With and Without External Resistors
WITH EXTERNAL RESISTORS
-4.88 < BPZ < 4.88
-1 < BPZ < 1
WITHOUT EXTERNAL RESISTORS
-56.6 < BPZ < -32.2
UNITS
mV
BPZ
-11.6 < BPZ < -6.6
LSBs
+Full scale
–Full scale
-0.25 < Error < 0.25
-0.25 < Error < 0.25
-2.5 < Error < -1.25
Gain error
% of FSR
-3.5 < Error < -2.25
200 Ω
200 Ω
1
1
2
3
4
5
±10 V
V
IN
V
±10 V
IN
2
3
4
5
AGND1
AGND1
REF
33.2 kΩ
+5 V
2.2 µF
2.2 µF
2.2 µF
33.2 kΩ
+
+
+
REF
576 kΩ
50 kΩ
Gain
Offset
CAP
CAP
+
50 kΩ
2.2 µF
AGND2
AGND2
(a) ±10 V With Hardware Trim
Note: Use 1% metal film resistors.
(b) ±10 V Without Hardware Trim
Figure 24. Circuit Diagram With and Without External Trim Hardware
REFERENCE
The ADS8504 can operate with its internal 2.5-V reference or an external reference. By applying an external
reference to pin 5, the internal reference can be bypassed. The reference voltage at REF is buffered internally
with the output on CAP (pin 4).
The internal reference has an 8 ppm/°C drift (typical) and accounts for approximately 20% of the full-scale error
(FSE = ±0.5%).
14
Submit Documentation Feedback
ADS8504
www.ti.com
SLAS434A–JUNE 2005–REVISED JUNE 2007
REF
REF (pin 3) is an input for an external reference or the output for the internal 2.5-V reference. A 2.2-µF capacitor
should be connected as close to the REF pin as possible. The capacitor and the output resistance of REF create
a low-pass filter to bandlimit noise on the reference. Using a smaller value capacitor introduces more noise to
the reference degrading the SNR and SINAD. The REF pin should not be used to drive external ac or dc loads.
The range for the external reference is 2.3 V to 2.7 V and determines the actual LSB size. Increasing the
reference voltage increases the full-scale range and the LSB size of the converter which can improve the SNR.
CAP
CAP (pin 4) is the output of the internal reference buffer. A 2.2-µF capacitor should be placed as close to the
CAP pin as possible to provide optimum switching currents for the CDAC throughout the conversion cycle and
compensation for the output of the internal buffer. Using a capacitor any smaller than 1 µF can cause the output
buffer to oscillate and may not have sufficient charge for the CDAC. Capacitor values larger than 2.2 µF have
little affect on improving performance. The ESR (equivalent series resistance) of these compensation capacitors
is also critical. Keep the total ESR under 3 Ω. See the TYPICAL CHARACTERISTICS section for how
performance is affected by ESR.
The output of the buffer is capable of driving up to 2 mA of current to a dc load. A dc load requiring more than 2
mA of current from the CAP pin begins to degrade the linearity of the ADS8504. Using an external buffer allows
the internal reference to be used for larger dc loads and ac loads. Do not attempt to directly drive an ac load
with the output voltage on CAP. This causes performance degradation of the converter.
LAYOUT
POWER
For optimum performance, tie the analog and digital power pins to the same +5-V power supply and tie the
analog and digital grounds together. As noted in the electrical specifications, the ADS8504 uses 90% of its
power for the analog circuitry. The ADS8504 should be considered as an analog component.
The +5-V power for the A/D should be separate from the +5 V used for the system's digital logic. Connecting
VDIG (pin 28) directly to a digital supply can reduce converter performance due to switching noise from the digital
logic. For best performance, the +5-V supply can be produced from whatever analog supply is used for the rest
of the analog signal conditioning. If +12-V or +15-V supplies are present, a simple +5-V regulator can be used.
Although it is not suggested, if the digital supply must be used to power the converter, be sure to properly filter
the supply. Either using a filtered digital supply or a regulated analog supply, both VDIG and VANA should be tied
to the same +5-V source.
GROUNDING
Three ground pins are present on the ADS8504. DGND is the digital supply ground. AGND2 is the analog
supply ground. AGND1 is the ground which all analog signals internal to the A/D are referenced. AGND1 is more
susceptible to current induced voltage drops and must have the path of least resistance back to the power
supply.
All the ground pins of the A/D should be tied to the analog ground plane, separated from the system's digital
logic ground, to achieve optimum performance. Both analog and digital ground planes should be tied to the
system ground as near to the power supplies as possible. This helps to prevent dynamic digital ground currents
from modulating the analog ground through a common impedance to power ground.
SIGNAL CONDITIONING
The FET switches used for the sample hold on many CMOS A/D converters release a significant amount of
charge injection which can cause the driving op amp to oscillate. The FET switch on the ADS8504, compared to
the FET switches on other CMOS A/D converters, releases 5%-10% of the charge. There is also a resistive front
end which attenuates any charge which is released. The end result is a minimal requirement for the anti-alias
filter on the front end. Any op amp sufficient for the signal in an application is sufficient to drive the ADS8504.
The resistive front end of the ADS8504 also provides an assured ±25-V overvoltage protection. In most cases,
this eliminates the need for external input protection circuitry.
15
Submit Documentation Feedback
ADS8504
www.ti.com
SLAS434A–JUNE 2005–REVISED JUNE 2007
LAYOUT (continued)
INTERMEDIATE LATCHES
The ADS8504 does have 3-state outputs for the parallel port, but intermediate latches should be used if the bus
is to be active during conversions. If the bus is not active during conversion, the 3-state outputs can be used to
isolate the A/D from other peripherals on the same bus. The 3-state outputs can also be used when the A/D is
the only peripheral on the data bus.
Intermediate latches are beneficial on any monolithic A/D converter. The ADS8504 has an internal LSB size of
610 µV. Transients from fast switching signals on the parallel port, even when the A/D is 3-stated, can be
coupled through the substrate to the analog circuitry causing degradation of converter performance.
16
Submit Documentation Feedback
ADS8504
www.ti.com
SLAS434A–JUNE 2005–REVISED JUNE 2007
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (June, 2005) to A Revision ....................................................................................................... Page
•
•
•
•
•
Deleted text from basic operation description ...................................................................................................................... 8
Changed text in starting a conversion description................................................................................................................ 8
Changed operation descriptions and R/C in table................................................................................................................ 9
Added SAR Reset Timing................................................................................................................................................... 12
Added ADC RESET section ............................................................................................................................................... 12
17
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS8504IBDW
ACTIVE
ACTIVE
SOIC
SOIC
DW
DW
28
28
20
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
ADS8504IB
ADS8504IB
ADS8504IBDWR
1000 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS8504IBDWR
SOIC
DW
28
1000
330.0
32.4
11.35 18.67
3.1
16.0
32.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 28
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 66.0
ADS8504IBDWR
1000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
DW SOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ADS8504IBDW
28
20
506.98
12.7
4826
6.6
Pack Materials-Page 3
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明