ADS8509IBDWRG4 [TI]
具有可编程 (±10/±5/±3.3V) 输入范围和 SPI 接口的 16 位、250kSPS、单通道 SAR ADC | DW | 20 | -40 to 85;
| 型号： | ADS8509IBDWRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有可编程 (±10/±5/±3.3V) 输入范围和 SPI 接口的 16 位、250kSPS、单通道 SAR ADC | DW | 20 | -40 to 85 |
| 文件： | 总35页 (文件大小：1123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS8509
www.ti.com
SLAS324C –OCTOBER 2004–REVISED APRIL 2010
16-BIT 250-KSPS SERIAL CMOS SAMPLING ANALOG-TO-DIGITAL CONVERTER
Check for Samples: ADS8509
1
FEATURES
DESCRIPTION
2
•
250-kHz Sampling Rate
The ADS8509 is
a
complete 16-bit sampling
analog-to-digital (A/D) converter using state-of-the-art
CMOS structures. It contains a complete 16-bit,
capacitor-based, successive approximation register
(SAR) A/D converter with sample-and-hold,
reference, clock, and a serial data interface. Data can
be output using the internal clock or can be
synchronized to an external data clock. The ADS8509
also provides an output synchronization pulse for
ease of use with standard DSP processors.
•
4-V, 5-V, 10-V, ±3.33-V, ±5-V, and ±10-V Input
Ranges
•
•
•
±2 LSB Max INL
±1 LSB Max DNL, 16-Bit No Missing Codes
SPI Compatible Serial Output with Daisy-Chain
(TAG) Feature
•
•
Single 5-V Supply
Pin-Compatible with ADS7809 (Low Speed)
and 12-Bit ADS8508/7808
The ADS8509 is specified at a 250-kHz sampling rate
over the full temperature range. Precision resistors
provide various input ranges including ±10 V and 0 V
to 5 V, while the innovative design allows operation
from a single +5-V supply with power dissipation
under 100 mW.
•
•
•
•
Uses Internal or External Reference
70-mW Typ Power Dissipation at 250 KSPS
20-Pin SO and 28-Pin SSOP Packages
Simple DSP Interface
The ADS8509 is available in 20-pin SO and 28-pin
SSOP packages, both fully specified for operation
over the industrial -40°C to 85°C temperature range.
APPLICATIONS
•
•
•
•
•
Industrial Process Control
Data Acquisition Systems
Digital Signal Processing
Medical Equipment
Instrumentation
Successive Approximation Register
Clock
EXT/INT
CDAC
9.8 kΩ
R1
R2
IN
BUSY
4.9 kΩ
2.5 kΩ
Serial
Data
Out
&
IN
DATACLK
DATA
R/C
10 kΩ
R3
IN
Comparator
Control
CAP
SB/BTC
CS
Internal
+2.5 V Ref
Buffer
4 kΩ
PWRD
REF
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2010, Texas Instruments Incorporated
ADS8509
SLAS324C –OCTOBER 2004–REVISED APRIL 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
MINIMUM
NO
MISSING
CODE
MINIMUM
SINAD
(dB)
SPECIFICATION
TEMPERATURE
RANGE
RELATIVE
ACCURACY
(LSB)
PACKAGE
LEAD
PACKAGE
DESIGNATOR
ORDERING
NUMBER
TRANSPORT
MEDIA, QTY
PRODUCT
ADS8509IBDW
ADS8509IBDWR
ADS8509IBDB
ADS8509IBDBR
ADS8509IDW
ADS8509IDWR
ADS8509IDB
Tube, 25
SO-20
SSOP-28
SO-20
DW
DB
DW
DB
Tape and Reel, 2000
Tube, 50
ADS8509IB
±2
±3
16
15
85
83
–40°C to 85°C
–40°C to 85°C
Tape and Reel, 2000
Tube, 25
Tape and Reel, 2000
Tube, 50
ADS8509I
SSOP-28
ADS8509IDBR
Tape and Reel, 2000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
R1IN
±25 V
R2IN
±25 V
Analog inputs
R3IN
±25 V
REF
+VANA + 0.3 V to AGND2 – 0.3 V
CAP
Indefinite short to AGND2, momentary short to VANA
DGND, AGND2
VANA
±0.3 V
6 V
0.3 V
Ground voltage differences
VDIG to VANA
VDIG
6 V
Digital inputs
–0.3 V to +VDIG + 0.3 V
165°C
Maximum junction temperature
Storage temperature range
Internal power dissipation
–65°C to 150°C
700 mW
Lead temperature (soldering, 1.6 mm from case 10 seconds)
260°C
(1) All voltage values are with respect to network ground terminal.
2
Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS8509
ADS8509
www.ti.com
SLAS324C –OCTOBER 2004–REVISED APRIL 2010
ELECTRICAL CHARACTERISTICS
At TA = –40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, using internal reference and 0.1%, 0.25-W fixed resistors (see
Figure 29 and Figure 30) (unless otherwise specified)
ADS8509I
ADS8509IB
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
Resolution
ANALOG INPUT
16
16
Bits
Voltage range(1)
Impedance(1)
Capacitance
50
50
pF
THROUGHPUT SPEED
Conversion cycle
Throughput rate
Acquire and convert
4
4
ms
250
250
kHz
DC ACCURACY
INL
Integral linearity error
Differential linearity error
No missing codes
–3
–2
15
3
2
–2
–1
16
2
1
LSB(2)
LSB
Bits
DNL
Transition noise(3)
1
1
LSB
±10-V Range
All other ranges
Int. ref. with 0.1% external fixed
resistors
–0.5
–0.5
0.5
0.5
–0.5
–0.5
0.5
0.5
Full-scale
%FSR
ppm/°C
%FSR
(5)
error(4)
Full-scale error drift
Int. ref.
±7
±7
±10-V Range
All other ranges
Ext. ref. with 0.1% external
fixed resistors
–0.5
–0.5
0.5
0.5
–0.5
–0.5
0.5
0.5
Full-scale
(5)
error(4)
Full-scale error drift
Bipolar zero error(4)
Bipolar zero error drift
Ext. ref.
±2
±2
ppm/°C
mV
–10
10
–5
5
±0.4
±0.4
ppm/°C
10-V Range
–5
–3
5
3
–5
–3
5
3
Unipolar zero
error(4)
mV
4-V and 5-V
Range
Unipolar zero error drift
±2
1
±2
1
ppm/°C
ms
Recovery to rated accuracy after 1-mF Capacitor to CAP
power down
Power supply sensitivity
+4.75 V < VD < +5.25 V
(VDIG = VANA = VD)
–8
8
–8
8
LSB
AC ACCURACY
SFDR
THD
Spurious-free dynamic range
fI = 20 kHz
fI = 20 kHz
fI = 20 kHz
–60-dB Input
fI = 20 kHz
90
83
83
99
–98
88
95
85
86
99
–98
88
dB(6)
dB
Total harmonic distortion
–90
–93
SINAD
dB
Signal-to-(noise+distortion)
30
32
dB
SNR
Signal-to-noise ratio
88
88
dB
Full-power bandwidth(7)
500
500
kHz
SAMPLING DYNAMICS
Aperture delay
5
5
ns
ms
ns
Transient response
Overvoltage recovery(8)
FS Step
2
2
150
150
(1) ±10 V, 0 V to 5 V, etc. (see Table 2). For normal operation, the analog input should not exceed configured range ±20%.
(2) LSB means least significant bit. For the ±10-V input range, one LSB is 305 mV.
(3) Typical rms noise at worst case transitions and temperatures.
(4) As measured with fixed resistors shown in Figure 29 and Figure 30. Adjustable to zero with external potentiometer. Factory calibrated
with 0.1%, 0.25-W resistors.
(5) For bipolar input ranges, full-scale error is the worst case of –full-scale or +full-scale uncalibrated deviation from ideal first and last code
transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. For unipolar input
ranges, full-scale error is the deviation of the last code transition divided by the transition voltage. It also includes the effect of offset
error.
(6) All specifications in dB are referred to a full-scale ±10-V input.
(7) Full-power bandwidth is defined as the full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 dB.
(8) Recovers to specified performance after 2 x FS input overvoltage.
Copyright © 2004–2010, Texas Instruments Incorporated
3
Product Folder Link(s): ADS8509
ADS8509
SLAS324C –OCTOBER 2004–REVISED APRIL 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
At TA = –40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, using internal reference and 0.1%, 0.25-W fixed resistors (see
Figure 29 and Figure 30) (unless otherwise specified)
ADS8509I
ADS8509IB
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
REFERENCE
Internal reference voltage
No load
2.48
2.5
1
2.52
2.48
2.5
1
2.52
V
mA
Internal reference source current
(must use external buffer)
Internal reference drift
8
8
ppm/°C
V
External reference voltage range
for specified linearity
2.3
2.5
2.7
2.3
2.5
2.7
External reference current drain
Ext. 2.5-V ref.
100
100
mA
DIGITAL INPUTS
Logic levels
VIL
VIH
IIL
Low-level input voltage
High-level input voltage
Low-level input current
High-level input current
–0.3
2.0
0.8
VDIG +0.3 V
±10
–0.3
2.0
0.8
V
V
VDIG +0.3 V
±10
VIL = 0 V
VIH = 5 V
mA
mA
IIH
±10
±10
DIGITAL OUTPUTS
Data format (serial 16-bits)
Data coding (binary 2's
complement or straight binary)
Pipeline delay (conversion results
only available after completed
conversion)
Data clock (selectable for internal
or external data clock)
Internal clock (output only when
transmitting data)
EXT/INT Low
EXT/INT High
9
9
MHz
MHz
External clock (can run
continually but not recommended
for optimum performance)
0.1
4
26
0.1
4
26
VOL
VOH
Low-level output voltage
High-level output voltage
ISINK = 1.6 mA
0.4
0.4
V
V
ISOURCE = 500 mA
Hi-Z State,
VOUT = 0 V to VDIG
±5
15
±5
15
mA
Leakage current
Output capacitance
Hi-Z State
pF
POWER SUPPLIES
VDIG
VANA
IDIG
Digital input voltage
4.75
4.75
5
5
5.25
5.25
4.75
4.75
5
5
5.25
5.25
V
V
Analog input voltage
Digital input current
Analog input current
Must be ≤ VANA
4
4
mA
mA
IANA
10
10
POWER DISSIPATION
PWRD Low
fS = 250 kHz
70
50
100
70
50
100
mW
PWRD High
mW
TEMPERATURE RANGE
Specified performance
Derated performance(9)
–40
–55
–65
85
125
150
–40
–55
–65
85
125
150
°C
°C
°C
Storage
THERMAL RESISTANCE (qJA
)
SSOP
SO
62
46
62
46
°C/W
°C/W
(9) The internal reference may not be started correctly beyond the industrial temperature range (–40°C to 85°C), therefore use of an
external reference is recommended.
4
Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS8509
ADS8509
www.ti.com
SLAS324C –OCTOBER 2004–REVISED APRIL 2010
PIN CONFIGURATIONS
DW PACKAGE
SO-20
(TOP VIEW)
R1IN
VDIG
1
2
3
4
5
6
7
8
9
20
19
VANA
AGND1
R2IN
18 PWRD
R3IN
17
16
15
BUSY
CS
CAP
REF
R/C
AGND2
SB/BTC
EXT/INT
14 TAG
13 DATA
12 DATACLK
11 SYNC
DGND 10
DB PACKAGE
SSOP-28
(TOP VIEW)
VDIG
28
R1IN
1
VANA
27
AGND1
R2IN
2
3
4
5
6
7
8
9
26 PWRD
R3IN
25
BUSY
24
NC
CAP
CS
23
NC
REF
22 NC
21
R/C
NC
20 NC
AGND2
19 TAG
NC 10
NC 11
18
17
NC
SB/BTC
EXT/INT
12
13
DATA
16 DATACLK
15
DGND 14
SYNC
Copyright © 2004–2010, Texas Instruments Incorporated
5
Product Folder Link(s): ADS8509
ADS8509
SLAS324C –OCTOBER 2004–REVISED APRIL 2010
www.ti.com
Terminal Functions
TERMINAL
DESCRIPTION
NAME
AGND1
AGND2
BUSY
DB NO. DW NO.
I/O
–
2
9
2
7
Analog ground. Used internally as ground reference point. Minimal current flow.
Analog ground
–
25
17
O
Busy output. Falls when a conversion is started and remains low until the conversion is completed
and the data is latched into the output shift register.
CAP
CS
6
5
–
–
Reference buffer capacitor. 2.2-mF Tantalum to ground.
24
17
16
13
Chip select. Internally ORed with R/C.
DATA
O
Serial data output. Data is synchronized to DATACLK with the format determined by the level of
SB/BTC. In the external clock mode, after 16 bits of data, the ADS8509 outputs the level input on
TAG as long as CS is low and R/C is high (see Figure 8 and Figure 9). If EXT/INT is low, data is
valid on both the rising and falling edges of DATACLK, and between conversions DATA stays at
the level of the TAG input when the conversion was started.
DATACLK
16
12
I/O Either an input or an output depending on the EXT/INT level. Output data is synchronized to this
clock. If EXT/INT is low, DATACLK transmits 16 pulses after each conversion and then remains
low between conversions.
DGND
14
13
10
9
–
–
Digital ground
EXT/INT
Selects external or internal clock for transmitting data. If high, data is output synchronized to the
clock input on DATACLK. If low, a convert command initiates the transmission of the data from the
previous conversion, along with 16-clock pulses output on DATACLK.
NC
5, 8, 10,
11, 18,
20, 22,
23
–
–
No connect
PWRD
R/C
26
18
15
I
I
Power down input. If high, conversions are inhibited and power consumption is significantly
reduced. Results from the previous conversion are maintained in the output shift register.
21
Read/convert input. With CS low, a falling edge on R/C puts the internal sample-and-hold into the
hold state and starts a conversion. When EXT/INT is low, this also initiates the transmission of the
data results from the previous conversion. If EXT/INT is high, a rising edge on R/C with CS low or
a falling edge on CS with R/C high transmits a pulse on SYNC and initiates the transmission of
data from the previous conversion.
REF
7
6
I/O Reference input/output. Outputs internal 2.5-V reference. Can also be driven by external system
reference. In both cases, bypass to ground with a 2.2-mF tantalum capacitor.
R1IN
1
3
1
3
4
8
I
I
I
I
Analog input. See Table 2 for input range connections.
Analog input. See Table 2 for input range connections.
Analog input. See Table 2 for input range connections.
R2IN
R3IN
4
SB/BTC
12
Select straight binary or binary 2's complement data output format. If high, data is output in a
straight binary format. If low, data is output in a binary 2's complement format.
SYNC
15
11
O
Sync output. This pin is used to supply a data synchronization pulse when the EXT level is high
and at least one external clock pulse has occurred when not in the read mode. See the external
clock modes desciptions.
TAG
VANA
VDIG
19
27
28
14
19
20
I
I
I
Tag input for use in the external clock mode. If EXT is high, digital data input from TAG is output
on DATA with a delay that is dependent on the external clock mode. See Figure 8 and Figure 9.
Analog supply input. Nominally +5 V. Connect directly to pin 20 and decouple to ground with
0.1-mF ceramic and 10-mF tantalum capacitors.
Digital supply input. Nominally +5 V. Connect directly to pin 19. Must be ≤ VANA
.
6
Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS8509
ADS8509
www.ti.com
SLAS324C –OCTOBER 2004–REVISED APRIL 2010
TIMING REQUIREMENTS, TA = –40°C to 85°C
PARAMETER
MIN
TYP
MAX
UNIT
ns
ns
ms
ns
ns
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ms
ns
ns
tw1
td1
tw2
td2
Pulse duration, convert
Delay time, BUSY from R/C low
Pulse duration, BUSY low
Delay time, BUSY, after end of conversion
Delay time, aperture
40
6
20
2.2
5
5
td3
tconv
tacq
Conversion time
2.2
4
Acquisition time
1.8
tconv + tacq Cycle time
td4
tc1
Delay time, R/C low to internal DATACLK output
270
110
35
Cycle time, internal DATACLK
td5
Delay time, data valid to internal DATACLK high
Delay time, data valid after internal DATACLK low
Cycle time, external DATACLK
15
20
35
15
15
15
10
3
td6
35
tc2
tw3
tw4
tsu1
tsu2
td7
Pulse duration, external DATACLK high
Pulse duration, external DATACLK low
Setup time, R/C rise/fall to external DATACLK high
Setup time, R/C transition to CS transition
Delay time, SYNC, after external DATACLK high
Delay time, data valid
35
20
td8
2
td9
Delay time, CS to rising edge
10
2
td10
tsu3
td11
tsu3
th1
Delay time, previous data available after CS, R/C low
Setup time, BUSY transition to first external DATACLK
Delay time, final external DATACLK to BUSY falling edge
Setup time, TAG valid
5
1
0
2
Hold time, TAG valid
PARAMETER MEASUREMENT INFORMATION
R/C
CS
CS
R/C
t
t
su1
t
t
su1
su1
su1
External
DATACLK
External
DATACLK
CS Set Low, Discontinuous Ext DATACLK
CS
R/C Set Low, Discontinuous Ext DATACLK
BUSY
t
t
su2
su2
t
su3
1
2
External
DATACLK
R/C
CS Set Low, Discontinuous Ext DATACLK
Figure 1. Critical Timing
Copyright © 2004–2010, Texas Instruments Incorporated
7
Product Folder Link(s): ADS8509
ADS8509
SLAS324C –OCTOBER 2004–REVISED APRIL 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
t
t
w1
w1
R/C
t
t
d1
t
d1
t
w2
w2
BUSY
t
d2
t
d2
t
d3
t
d3
t
t
d11
d11
Error
Correction
Error
Correction
(N+1)th Accquisition
(N+2)th Accquisition
Nth Conversion
STATUS
(N+1)th Conversion
t
t
t
t
conv
conv
acq
acq
t
t
c1
t
d4
d4
Internal
1
2
16
D0
2
16
D0
1
DATACLK
t
d6
t
d5
TAG = 0
D15
D15
DATA
TAG = 0
TAG = 0
Nth Conversion Data
(N−1)th Conversion Data
CS, EXT/INT, and TAG are tied low
8 starts READ
Figure 2. Basic Conversion Timing (Internal DATACLK - Read Previous Data During Conversion)
t
t
w1
w1
R/C
t
t
d1
d1
t
t
w2
w2
BUSY
t
t
d2
d2
t
t
d3
d3
t
t
d11
d11
Error
Correction
Error
Correction
STATUS
Nth Conversion
(N+1)th Accquisition
(N+1)th Conversion
(N+2)th Accquisition
t
t
t
t
acq
acq
conv
conv
t
t
t
su3
su3
su1
t
su1
External
1
1
16
2
16
2
1
16
1
16
DATACLK
No more
data to
shift out
No more
data to
shift out
TAG = 0
TAG = 0
Nth Data
TAG = 0
(N+1)th Data
TAG = 0
DATA
TAG = 0
EXT/INT tied high, CS and TAG are tied low
t
+ t
starts READ
su1
w1
Figure 3. Basic Conversion Timing (External DATACLK)
8
Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS8509
ADS8509
www.ti.com
SLAS324C –OCTOBER 2004–REVISED APRIL 2010
PARAMETER MEASUREMENT INFORMATION (continued)
t
w1
R/C
t
su1
t
d1
t
d1
t
w2
BUSY
t
t
d2
t
d3
t
d3
d11
Error
Correction
(N+1) th Accquisition
Nth Conversion
STATUS
t
su3
t
t
acq
conv
t
t
su1
c2
t
w4
External
t
w3
DATACLK
0
1
2
3
4
5
10
11
12
13
14
15
16
SYNC = 0
DATA
Nth Conversion Data
t
t
d8
d8
Null
D15 D14 D13 D12 D11 D10
D05 D04 D03 D02 D01 D00
T00
T17
Txx
Tyy
t
h1
t
su3
T01 T02 T03
Null
TAG
T00
T04 T05 T06
T11 T12 T13 T14 T15 T16
EXT/INT tied high, CS tied low
t
+ t
starts READ
su1
w1
Figure 4. Read After Conversion (Discontinuous External DATACLK)
t
w1
R/C
t
d1
t
w2
BUSY
t
t
d2
t
d10
d3
Error
Correction
Nth Conversion
STATUS
t
su3
t
conv
t
c2
t
t
t
d11
w3
w4
t
su1
External
1
2
3
4
5
10
11
12
13
14
15
16
0
DATACLK
SYNC = 0
DATA
Nth Conversion Data
t
t
d8
d8
D05 D04 D03 D02 D01 D00
D15 D14 D13 D12 D11 D10
Rising DATACLK change DATA, t + t
Starts READ
su1
w1
EXT/INT tied high, CS and TAG tied low
TAG is not recommended for this mode. There is not enough
time to do so without violating t
.
d11
Figure 5. Read During Conversion (Discontinuous External DATACLK)
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9
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PARAMETER MEASUREMENT INFORMATION (continued)
t
w1
R/C
t
t
t
d1
d1
t
su1
su1
t
w2
BUSY
t
d2
t
t
d3
d3
t
d11
Error
(N+1)th Accquisition
Nth Conversion
STATUS
Correction
t
t
conv
acq
t
c2
t
t
su3
su1
t
su1
t
t
w4
w3
External
0
1
2
3
4
5
6
7
12
13
14
15
16
17
18
DATACLK
t
c2
t
d7
=0
SYNC
DATA
TAG
Nth Conversion Data
t
t
d8
d8
D15 D14 D13 D12 D11 D10
D05 D04 D03 D02 D01 D00
Null
T00
Txx
Tyy
t
h1
T01 T02 T03
t
su3
T00
T04 T05 T06
T11 T12 T13
T14
T15 T16
T17
t
+ t
starts READ
su1
EXT/INT tied high, CS tied low
w1
Figure 6. Read After Conversion With SYNC (Discontinuous External DATACLK)
t
w1
R/C
t
d1
t
w2
BUSY
t
t
d3
t
d2
d10
Error
Correction
Nth Conversion
STATUS
t
su3
t
conv
t
t
c2
t
t
su1
su1
t
t
w3
d11
w4
t
su1
External
DATACLK
0
1
2
3
4
5
6
7
12
13
14
15
16
17
18
t
d7
t
c2
SYNC = 0
Nth Conversion Data
t
t
d8
d8
D15 D14 D13 D12 D11 D10
D05 D04 D03 D02 D01 D00
DATA
t
+ t
Starts READ
su1
w1
EXT/INT tied high, CS and TAG tied low
TAG is not recommended for this mode. There is not enough
time to do so without violating t
.
d11
Figure 7. Read During Conversion With SYNC (Discontinuous External DATACLK)
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PARAMETER MEASUREMENT INFORMATION (continued)
Figure 8. Conversion and Read Timing with Continuous External DATACLK (EXT/INT Tied High) Read
After Conversions (Not Recommended)
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PARAMETER MEASUREMENT INFORMATION (continued)
Figure 9. Conversion and Read Timing with Continous External DATACLK (EXT/INT Tied High) Read
Previous Conversion Results During Conversion (Not Recommended)
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TYPICAL CHARACTERISTICS
SPURIOUS FREE DYNAMIC RANGE
TOTAL HARMONIC DISTORTION
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
−100
105
100
95
−95
−90
−85
−80
−75
−70
90
85
f
= 250 KSPS,
f
= 250 KSPS,
80
s
s
f = 20 kHz
f = 20 kHz
i
i
75
−40
25
85
−40
25
85
T
A
− Free-Air Temperature − 5C
T
A
− Free-Air Temperature − 5C
Figure 10.
Figure 11.
SIGNAL-TO-NOISE RATIO
vs
SIGNAL-TO-NOISE AND DISTORTION
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
100
95
90
85
80
75
70
100
f
= 250 KSPS,
f
= 250 KSPS,
s
s
f = 20 kHz
f = 20 kHz
i
i
95
90
85
80
75
70
−40
25
85
−40
25
85
T
A
− Free-Air Temperature − 5C
T
A
− Free-Air Temperature − 5C
Figure 12.
Figure 13.
SIGNAL-TO-NOISE RATIO
vs
SIGNAL-TO-NOISE AND DISTORTION
vs
INPUT FREQUENCY
INPUT FREQUENCY
90
85
80
75
70
65
90
85
80
75
70
65
1
10
100
1
10
100
f − Input Frequency − kHz
i
f − Input Frequency − kHz
i
Figure 14.
Figure 15.
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TYPICAL CHARACTERISTICS (continued)
SPURIOUS FREE DYNAMIC RANGE
TOTAL HARMONIC DISTORTION
vs
vs
INPUT FREQUENCY
INPUT FREQUENCY
105
100
95
−105
−100
−95
−90
90
−85
85
−80
80
−75
−70
75
70
1
10
100
1
10
100
f − Input Frequency − kHz
i
f − Input Frequency − kHz
i
Figure 16.
Figure 17.
INTERNAL REFERENCE VOLTAGE
BIPOLAR ZERO SCALE ERROR
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
2.510
2.508
2.506
2.504
2.502
2.500
2.498
2.496
2.494
2.492
2.490
5
External Reference,
4
±10-V Range
3
2
1
0
−1
−2
−3
−4
−5
−55 −35 −15
5
25 45 65 85 105
−40 −25 −10
5
20 35 50 65 80
T
A
− Free-Air Temperature − 5C
T
A
− Free-Air Temperature − 5C
Figure 18.
Figure 19.
FULL SCALE ERROR
vs
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
20
19
18
17
16
15
14
13
12
11
10
0.20
0.15
0.10
0.05
0
External Reference,
±10 V Range
for 5 Representative
Parts
−0.05
−0.10
−0.15
−0.20
−40 −25 −10
5
20 35 50 65 80
−40 −25 −10
5
20 35 50 65 80
T
A
− Free-Air Temperature − 5C
T
A
− Free-Air Temperature − 5C
Figure 20.
Figure 21.
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TYPICAL CHARACTERISTICS (continued)
PERFORMANCE
vs
HISTOGRAM
CAP PIN CAPACITOR ESR
4500
4000
3500
3000
100
95
90
85
80
75
70
65
60
4224
8192
Conversions
of a DC Input
|THD|
SINAD
2500
2000
2082
1484
1500
1000
500
0
2.2 µF Capacitor on
CAP Pin (pin 6)
55
50
238
2
4
149
−2
11
3
−3
−1
0
1
10 11
0
1
2
3
4
5
6
7
8
9
ESR − Resistance − W
Code
Figure 22.
Figure 23.
INTEGRAL NONLINEARITY
2.5
f
= 250 KSPS
s
2
1.5
1
0.5
0
−0.5
−1
−1.5
−2
−2.5
0
16384
32768
49152
65536
Code
Figure 24.
DIFFERENTIAL NONLINEARITY
2.5
f
= 250 KSPS
s
2
1.5
1
0.5
0
−0.5
−1
−1.5
−2
−2.5
0
16384
32768
49152
65536
Code
Figure 25.
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TYPICAL CHARACTERISTICS (continued)
FFT (20-kHz Input)
20
8192 Points,
= 250 KSPS,
0
f
s
f = 20 kHz, 0 dB
SINAD = 86.0 dB,
THD = −98.7 dB
i
−20
−40
−60
−80
−100
−120
−140
−160
−180
0
25
50
75
100
125
f − Frequency − kHz
Figure 26.
BASIC OPERATION
Two signals control conversion in the ADS8509: CS and R/C. These two signals are internally ORed together. To
start a conversion the chip must be selected, CS low, and the conversion signal must be active, R/C low. Either
signal can be brought low first. Conversion starts on the falling edge of the second signal. BUSY goes low when
conversion starts and returns high after the data from that conversion is shifted into the internal storage register.
Sampling begins when BUSY goes high.
To reduce the number of control pins CS can be tied low permanently. The R/C pin now controls conversion and
data reading exclusively. In the external clock mode this means that the ADS8509 clocks out data whenever R/C
is brought high and the external clock is active. In the internal clock mode data is clocked out every convert cycle
regardless of the states of CS and R/C. The ADS8509 provides a TAG input for cascading multiple converters
together.
READING DATA
The conversion result is available as soon as BUSY returns to high, therefore data always represents the
conversion previously completed even when it is read during a conversion. The ADS8509 outputs serial data in
either straight binary or binary two’s compliment format. The SB/BTC pin controls the format. Data is shifted out
MSB first. The first conversion immediately following a power-up does not produce a valid conversion result.
Data can be clocked out with either the internally generated clock or with an external clock. The EXT/INT pin
controls this function. If an external clock is used, the TAG input can be used to daisy-chain multiple ADS8509
data pins together.
INTERNAL DATACLK
In internal clock mode data for the previous conversion is clocked out during each conversion period. The
internal data clock is synchronized to the internal conversion clock so that is does not interfere with the
conversion process.
The DATACLK pin becomes an output when EXT/INT is low. 16 Clock pulses are generated at the beginning of
each conversion after timing t8 is satisfied, i.e. only the previous conversion result can be read during conversion.
DATACLK returns to low when it is inactive. The 16 bits of serial data are shifted out the DATA pin synchronous
to this clock with each bit available on a rising and then a falling edge. The DATA pin returns to the state of the
TAG pin input sensed at the start of transmission.
EXTERNAL DATACLK
The external clock mode offers several ways to retrieve conversion results. However, since the external clock
cannot be synchronized to the internal conversion clock care must be taken to avoid corrupting the data.
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When EXT/INT is set high, the R/C and CS signals control the read state. When the read state is initiated, the
result from the previously completed conversion is shifted out the DATA pin synchronous to the external clock
that is connected to the DATACLK pin. Each bit is available on a falling and then a rising edge. The maximum
external clock speed of 28.5 MHz allows data to be shifted out quickly either at the beginning of conversion or
the beginning of sampling.
There are several modes of operation available when using an external clock. It is recommended that the
external clock run only while reading data. This is discontinuous clock mode. Since the external clock is not
synchronized to the internal clock that controls conversion slight changes in the external clock can cause
conflicts that can corrupt the conversion process. Specifications with a continuously running external clock
cannot be ensured. It is especially important that the external clock does not run during the second half of the
conversion cycle (approximately the time period specified by td11, see the TIMING REQUIREMENTS table).
In discontinuous clock mode data can be read during conversion or during sampling, with or without a SYNC
pulse. Data read during conversion must meet the td11 timing specification. Data read during sampling must be
complete before starting a conversion.
Whether reading during sampling or during conversion a SYNC pulse is generated whenever at least one rising
edge of the external clock occurs while the part is not in the read state. In the discontinuous external clock with
SYNC mode a SYNC pulse follows the first rising edge after the read command. The data is shifted out after the
SYNC pulse. The first rising clock edge after the read command generates a SYNC pulse. The SYNC pulse can
be detected on the next falling edge and then the next rising edge. Successively, each bit can be read first on the
falling edge and then on the next rising edge. Thus 17 clock pulses after the read command are required to read
on the falling edge. 18 Clock pulses are necessary to read on the rising edge.
Table 1. DATACLK Pulses
DATACLK PULSES REQUIRED
DESCRIPTION
WITH SYNC
WITHOUT SYNC
Read on falling edge of DATACLK
Read on rising edge of DATACLK
17
18
16
17
If the clock is entirely inactive when not in the read state a SYNC pulse is not generated. In this case the first
rising clock edge shifts out the MSB. The MSB can be read on the first falling edge or on the next rising edge. In
this discontinuous external clock mode with no SYNC, 16 clocks are necessary to read the data on the falling
edge and 17 clocks for reading on the rising edge. Data always represents the conversion already completed.
TAG FEATURE
The TAG feature allows the data from multiple ADS8509 converters to be read on a single serial line. The
converters are cascaded together using the DATA pins as outputs and the TAG pins as inputs as illustrated in
Figure 27. The DATA pin of the last converter drives the processor's serial data input. Data is then shifted
through each converter, synchronous to the externally supplied data clock, onto the serial data line. The internal
clock cannot be used for this configuration.
The preferred timing uses the discontinuous external data clock during the sampling period. Data must be read
during the sampling period because there is not sufficient time to read data from multiple converters during a
conversion period without violating the td11 constraint (see the EXTERNAL DATACLOCK section). The sampling
period must be sufficiently long to allow all data words to be read before starting a new conversion.
Note, in Figure 27, that a NULL bit separates the data word from each converter. The state of the DATA pin at
the end of a READ cycle reflects the state of the TAG pin at the start of the cycle. This is true in all READ
modes, including the internal clock mode. For example, when a single converter is used in internal clock mode,
the state of the TAG pin determines the state of the DATA pin after all 16 bits have shifted out. When multiple
converters are cascaded together, this state forms the NULL bit that separates the words. Thus, with the TAG
pin of the first converter grounded as shown in Figure 27 the NULL bit becomes a zero between each data word.
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Processor
ADS8509A
DATA
ADS8509B
DATA (A)
Null
Null
A00
B00
A15
B15
A16
B16
TAG(A)
TAG(B)
DATA
CS
R/C
D
D
Q
Q
D
D
Q
Q
D
D
Q
Q
D
D
Q
Q
TAG
TAG
CS
R/C
DATACLK
DATACLK
SCLK
DATA (B)
GPIO
GPIO
SDI
DATACLK
R/C
(both A & B)
BUSY
(both A & B)
SYNC
(both A & B)
External
DATACLK
1
2
3
4
16
17
19
20
21
34
35
36
18
Null
A15 A14 A13
A01 A00
DATA ( A )
DATA ( B )
TAG(A) = 0
Nth Conversion Data
Null
A
Null
A
B15
B00
A15
B14 B13
B01
A14 A13
A01 A00
B
TAG(A) = 0
EXT/INT tied high, CS of both converter A and B, TAG input of converter A are tied low.
.
Figure 27. Timing of TAG Feature With Single Conversion (Using External DATACLK)
ANALOG INPUTS
The ADS8509 has six analog input ranges as shown in Table 2. The offset and gain specifications are factory
calibrated with 0.1%, 0.25-W, external resistors as shown in Figure 29 and Figure 30. The external resistors can
be omitted if larger gain and offset errors are acceptable or if using software calibration. The hardware trim
circuitry shown in Figure 29 and Figure 30 can reduce the errors to zero.
The analog input pins R1IN, R2IN, and R3IN have ±25-V overvoltage protection. The input signal must be
referenced to AGND1. This minimizes the ground loop problem typical to analog designs. The analog input
should be driven by a low impedance source. A typical driving circuit using OPA627 or OPA132 is shown in
Figure 28.
The ADS8509 can operate with its internal 2.5-V reference or an external reference. An external reference
connected to pin 6 (REF) bypasses the internal reference. The external reference must drive the 4-kΩ resistor
that separates pin 6 from the internal reference (see the illustration on page 1). The load varies with the
difference between the internal and external reference voltages. The external reference voltage can vary from
2.3 V to 2.7 V. The internal reference is approximately 2.5 V. The reference, whether internal or external, is
buffered internally with a buffer with its output on pin 5 (CAP).
The ADS8509 is factory tested with 2.2-mF capacitors connected to pins 5 and 6 (CAP and REF). Each capacitor
should be placed as close as possible to its pin. The capacitor on pin 6 band limits the internal reference noise. A
smaller capacitor can be used but it may degrade SNR and SINAD. The capacitor on pin 5 stabilizes the
reference buffer and provides switching charge to the CDAC during conversion. Capacitors smaller than 1 mF
can cause the buffer to become unstable and may not hold sufficient charge for the CDAC. The parts are tested
to specifications with 2.2 mF so larger capacitors are not necessary. The equivalent series resistor (ESR) of these
compensation capacitors is also critical. The total ESR must be kept under 3 Ω. See the TYPICAL
CHARACTERISTICS section concerning how ESR affects performance.
Neither the internal reference nor the buffer should be used to drive an external load. Such loading can degrade
performance. Any load on the internal reference causes a voltage drop across the 4-kΩ resistor and affects gain.
The internal buffer is capable of driving ±2-mA loads but any load can cause perturbations of the reference at the
CDAC, degrading performance. It should be pointed out that, unlike other competitor’s parts with similar input
structure, the ADS8509 does not require a second high-speed amplifier used as a buffer to isolate the CAP pin
from the signal dependent current in the R3IN pin but can tolerate it if one does exist.
18
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The external reference voltage can vary from 2.3 V to 2.7 V. The reference voltage determines the size of the
least significant bit (LSB). The larger reference voltages produce a larger LSB, which can improve SNR. Smaller
reference voltages can degrade SNR.
+15V
2.2 mF
22 pF
ADS8509
200 W
100 nF
R1
IN
GND
2 kW
AGND1
Pin 7
Pin 2
Pin1
100 W
2 kW
R2
IN
Vin
−
OPA 627
22 pF
or
33.2 kW
Pin 6
GND
OPA 132
+
R3
IN
Pin3
Pin4
CAP
REF
2.2 mF
GND
2.2 mF
DGND
GND
2.2 mF
100 nF
GND
AGND2
−15V
GND
Figure 28. Typical Driving Circuitry (±10 V, No Trim)
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Table 2. Input Range Connections (See Figure 29 and Figure 30 for Complete
Information)
ANALOG
INPUT RANGE
CONNECT R1IN VIA CONNECT R2IN VIA
CONNECT
R3 TO
IMPEDANCE
200 Ω TO
100 Ω TO
AGND
VIN
±10 V
±5 V
VIN
CAP
CAP
CAP
AGND
VIN
11.5 kΩ
6.7 kΩ
5.4 kΩ
6.7 kΩ
5.0 kΩ
5.4 kΩ
AGND
VIN
±3.33 V
VIN
0 V to 10 V
0 V to 5 V
0 V to 4 V
AGND
AGND
VIN
VIN
AGND
AGND
VIN
Table 3. Control Truth Table
SPECIFIC FUNCTION
CS
1 > 0
0
R/C
0
BUSY
EXT/INT
DATACLK
Output
PWRD
SB/BTC
OPERATION
Initiate conversion and
output data using internal
clock
1
1
0
0
0
0
x
x
Initiates conversion n. Data from conversion n - 1
clocked out on DATA synchronized to 16 clock
pulses output on DATACLK.
1 > 0
Output
1 > 0
0
0
1 > 0
1
1
1
1
1
1
1
Input
Input
Input
0
0
x
x
x
x
Initiates conversion n.
Initiates conversion n.
Initiate conversion and
output data using external
clock
1 > 0
Outputs data with or without SYNC pulse. See
section READING DATA.
1 > 0
1
0 > 1
0
0
0
1
1
x
x
Input
Input
x
0
0
0
0
x
x
x
x
Outputs data with or without SYNC pulse. See
section READING DATA.
0
0
x
No actions
0 > 1
x
This is an acceptable condition.
x
x
Analog circuitry powered. Conversion can
proceed..
Power down
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
x
x
x
0
1
Analog circuitry disabled. Data from previous
conversion maintained in output registers.
Serial data is output in binary 2's complement
format.
Select output format
Serial data is output in straight binary format.
Table 4. Output Codes and Ideal Input Voltages
DIGITAL OUTPUT
BINARY 2'S
COMPLEMENT
(SB/BTC LOW)
STRAIGHT
BINARY
(SB/BTC HIGH)
DESCRIPTI
ON
ANALOG INPUT
BINARY CODE
HEX CODE
BINARY CODE
HEX CODE
Full-scale
±10
±5
±3.33 V
0 V to 10 V
0 V to 5 V
0 V to 4 V
range
Least
significant
bit (LSB)
305 mV
153 mV
102 mV
153 mV
76 mV
61 mV
Full scale
(FS - 1LSB)
4.999847
V
9.999695 V
0 V
3.333231 V
0 V
9.999847 V
5 V
4.999924 V
2.5 V
3.999939 V
2 V
0111 1111 1111 1111
0000 0000 0000 0000
7FFF
0000
1111 1111 1111 1111
1000 0000 0000 0000
FFFF
8000
Midscale
0 V
153 mV
–5 V
One LSB
below
midscale
–305 mV
±102 µV
4.999847 V
0 V
2.499924 V
0 V
1.999939 V
0 V
1111 1111 1111 1111
1000 0000 0000 0000
FFFF
8000
0111 1111 1111 1111
0000 0000 0000 0000
7FFF
0000
–Full scale
–10 V
–3.333333 V
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With Trim
Input Range
Without Trim
(Adjust Offset First at 0 V, Then Adjust Gain)
200 Ω
200 Ω
R1
R1
IN
IN
AGND1
AGND1
100 Ω
2.2 µF
100 Ω
0 V − 10 V
R2
R2
V
IN
V
IN
IN
33.2 kΩ
IN
R3
R3
33.2 kΩ
IN
IN
+ 5 V
+
+ 5 V
CAP
REF
CAP
REF
+
50 kΩ
576 kΩ
2.2 µF
2.2 µF
200 Ω
50 kΩ
+
+
2.2 µF
AGND2
AGND2
200 Ω
R1
IN
R1
IN
AGND1
AGND1
100 Ω
100 Ω
R2
R3
IN
R2
33.2 kΩ
IN
33.2 kΩ
IN
V
IN
V
IN
R3
0 V − 5 V
IN
+5 V
CAP
REF
CAP
REF
+5 V
+
50 kΩ
576 kΩ
2.2 µF
2.2 µF
+
2.2 µF
+
+
50 kΩ
2.2 µF
AGND2
AGND2
200 Ω
200 Ω
V
IN
R1
V
IN
R1
IN
IN
AGND1
AGND1
100 Ω
100 Ω
R2
R2
IN
IN
R3
R3
IN
IN
0 V − 4 V
33.2 kΩ
+5 V
33.2 kΩ
+5 V
+
+
2.2 µF
576 kΩ
CAP
REF
+
CAP
REF
2.2 µF
50 kΩ
50 kΩ
+
2.2 µF
2.2 µF
AGND2
AGND2
Figure 29. Offset/Gain Circuits for Unipolar Input Ranges
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With Trim
Input Range
Without Trim
(Adjust Offset First at 0 V, Then Adjust Gain)
200 Ω
200 Ω
V
IN
R1
IN
R1
V
IN
IN
AGND1
AGND1
100 Ω
100 Ω
R2
R2
IN
IN
±10 V
+5 V
33.2 kΩ
+5 V
R3
33.2 kΩ
R3
IN
IN
50 kΩ
+
+
CAP
REF
+
CAP
REF
2.2 µF
2.2F
576 kΩ
+
50 kΩ
2.2F
2.2 µF
AGND2
AGND2
200 Ω
200 Ω
R1
R1
IN
IN
AGND1
AGND1
100 Ω
100 Ω
V
IN
33.2 kΩ
V
IN
R2
R2
IN
IN
33.2 kΩ
R3
R3
IN
± 5 V
IN
+
+5 V
2.2 µF
+5 V
CAP
REF
CAP
REF
+
50 kΩ
576 kΩ
2.2 µF
50 kΩ
+
+
2.2 µF
2.2 µF
AGND2
AGND2
200 Ω
200 Ω
V
IN
R1
R1
IN
IN
V
IN
100 Ω
AGND1
AGND1
100 Ω
R2
R2
IN
IN
R3
R3
33.2 kΩ
2.2 µF
+5 V
33.2 kΩ
IN
IN
+
±3.3 V
+5 V
CAP
CAP
50 kΩ
576 kΩ
+
2.2 F
REF
50 kΩ
REF
+
+
2.2 F
2.2 µF
AGND2
AGND2
Figure 30. Offset/Gain Circuits for Bipolar Input Ranges
22
Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS8509
ADS8509
www.ti.com
SLAS324C –OCTOBER 2004–REVISED APRIL 2010
REVISION HISTORY
Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April 2007) to Revision C
Page
•
•
•
Deleted Lead Temperature from Absolute Maximum Ratings .............................................................................................. 2
Changed SB/BTC pin from "O" to "I" .................................................................................................................................... 6
Changed location of Timing Requirements table to be closer to timing diagrams ............................................................... 7
Copyright © 2004–2010, Texas Instruments Incorporated
23
Product Folder Link(s): ADS8509
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS8509IBDB
ADS8509IBDW
ACTIVE
SSOP
SOIC
SOIC
SOIC
SOIC
DB
28
20
20
20
20
50
RoHS & Green
RoHS & Green
RoHS & Green
Call TI
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
ADS8509I
B
Samples
Samples
Samples
Samples
Samples
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DW
25
NIPDAU
NIPDAU
NIPDAU
NIPDAU
ADS8509I
B
ADS8509IBDWG4
ADS8509IBDWR
ADS8509IBDWRG4
DW
25
ADS8509I
B
DW
2000 RoHS & Green
2000 RoHS & Green
ADS8509I
B
DW
ADS8509I
B
ADS8509IDB
ADS8509IDBR
ADS8509IDW
ADS8509IDWG4
ADS8509IDWR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SOIC
SOIC
SOIC
DB
DB
28
28
20
20
20
50
RoHS & Green
Call TI
Call TI
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
ADS8509I
ADS8509I
ADS8509I
ADS8509I
ADS8509I
Samples
Samples
Samples
Samples
Samples
2000 RoHS & Green
DW
DW
DW
25
25
RoHS & Green
RoHS & Green
NIPDAU
NIPDAU
NIPDAU
2000 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS8509IBDWR
ADS8509IDBR
ADS8509IDWR
SOIC
SSOP
SOIC
DW
DB
20
28
20
2000
2000
2000
330.0
330.0
330.0
24.4
16.4
24.4
10.8
8.1
13.3
10.4
13.3
2.7
2.5
2.7
12.0
12.0
12.0
24.0
16.0
24.0
Q1
Q1
Q1
DW
10.8
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS8509IBDWR
ADS8509IDBR
ADS8509IDWR
SOIC
SSOP
SOIC
DW
DB
20
28
20
2000
2000
2000
350.0
350.0
350.0
350.0
350.0
350.0
43.0
43.0
43.0
DW
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ADS8509IBDB
ADS8509IBDW
ADS8509IBDWG4
ADS8509IDB
DB
DW
DW
DB
SSOP
SOIC
SOIC
SSOP
SOIC
SOIC
28
20
20
28
20
20
50
25
25
50
25
25
530
10.5
12.7
12.7
10.5
12.7
12.7
4000
4826
4826
4000
4826
4826
4.1
6.6
6.6
4.1
6.6
6.6
506.98
506.98
530
ADS8509IDW
DW
DW
506.98
506.98
ADS8509IDWG4
Pack Materials-Page 3
PACKAGE OUTLINE
DB0028A
SSOP - 2 mm max height
S
C
A
L
E
1
.
5
0
0
SMALL OUTLINE PACKAGE
C
8.2
7.4
TYP
A
0.1 C
SEATING
PIN 1 INDEX AREA
PLANE
26X 0.65
28
1
2X
10.5
9.9
8.45
NOTE 3
14
15
0.38
0.22
28X
0.15
C A B
5.6
5.0
B
NOTE 4
2 MAX
0.25
GAGE PLANE
(0.15) TYP
SEE DETAIL A
0.95
0.55
0.05 MIN
0 -8
A
15
DETAIL A
TYPICAL
4214853/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0028A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
28X (1.85)
(R0.05) TYP
28
1
28X (0.45)
26X (0.65)
SYMM
14
15
(7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4214853/B 03/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DB0028A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
28X (1.85)
SYMM
(R0.05) TYP
28
1
28X (0.45)
26X (0.65)
SYMM
14
15
(7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4214853/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
18X 1.27
20
1
13.0
12.6
NOTE 3
2X
11.43
10
11
0.51
0.31
20X
2.65 MAX
7.6
7.4
B
0.25
C A B
NOTE 4
0.33
0.10
TYP
0.25
SEE DETAIL A
GAGE PLANE
0 - 8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
10
11
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
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Copyright © 2022, Texas Instruments Incorporated
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