ADS8515IBDBRG4 [TI]
16-BIT 250-KSPS SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER; 16位250 KSPS采样CMOS模拟数字转换器
| 型号： | ADS8515IBDBRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT 250-KSPS SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER |
| 文件： | 总22页 (文件大小：527K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADS8515
SLAS460A–JUNE 2007–REVISED NOVEMBER 2007
16-BIT 250-KSPS SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER
1
FEATURES
DESCRIPTION
•
•
•
•
•
Standard ±10-V Input Range
90-dB Min SNR with 20-kHz Input
±2.0 LSB Max INL
The ADS8515 is a complete 16-bit sampling A/D
converter using state-of-the-art CMOS structures. It
contains a complete 16-bit, capacitor-based, SAR
A/D with S/H, reference, clock, interface for
microprocessor use, and 3-state output drivers.
±1 LSB Max DNL, 16-Bits No Missing Code
5-V Analog Supply, Flexible I/O Supply Voltage
at 1.65 V to 5.25 V
The ADS8515 is specified at a 250-kHz sampling rate
over the full temperature range. Precision resistors
provide an industry standard ±10-V input range, while
the innovative design allows operation from a single
+5-V supply, with power dissipation under 100 mW.
•
Pin-Compatible With ADS7805/10 (Low Speed),
and 12-Bit ADS7804/8504
•
•
•
•
Uses Internal or External Reference
Full Parallel Data Output
The ADS8515 is available in a 28-pin SSOP package
and is fully specified for operation over the industrial
-40°C to 85°C temperature range.
100-mW Typ Power Dissipation at 250 KSPS
28-Pin SSOP Package
APPLICATIONS
•
•
•
•
•
Industrial Process Control
Data Acquisition Systems
Digital Signal Processing
Medical Equipment
Instrumentation
R/C
CS
Clock
Successive Approximation Register and Control Logic
BYTE
BUSY
CDAC
Output
Latches
and
Three
State
Three
State
Parallel
Data
7 kΩ
± 10 V Input
25.67 kΩ
2 kΩ
Comparator
Drivers
Bus
CAP
Internal
+4.096 V Ref
Buffer
4 kΩ
REF
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
ADS8515
www.ti.com
SLAS460A–JUNE 2007–REVISED NOVEMBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PACKAGE/ORDERING INFORMATION(1)
MINIMUM
INL
(LSB)
NO
MISSING
CODE
MINIMUM
SINAD
(dB)
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE
LEAD
PACKAGE
DESIGNATOR
ORDERING
NUMBER
TRANSPORT
MEDIA, QTY
PRODUCT
ADS8515IBDB
ADS8515IBDBR
ADS8515IDB
Tube, 50
ADS8515IB
ADS8515I
±2
±3
16
16
89
87
-40°C to 85°C
-40°C to 85°C
SSOP-28
SSOP-28
DB
DB
Tape and Reel, 2000
Tube, 50
ADS8515IDBR
Tape and Reel, 2000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)(2)
ADS8515
Analog inputs
VIN
±25V
CAP
+VANA + 0.3 V to AGND2 - 0.3 V
REF
Indefinite short to AGND2, momentary short to VANA
Ground voltage differences
DGND, AGND1, AGND2
±0.3 V
VANA
6 V
VDIG to VANA
VDIG
0.3 V
6 V
Digital inputs
-0.3 V to +VDIG + 0.3 V
165°C
Maximum junction temperature
Internal power dissipation
825 mW
Lead temperature (soldering, 10s)
300°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
ELECTRICAL CHARACTERISTICS
TA = -40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, using internal reference (unless otherwise noted)
ADS8515I
TYP
ADS8515IB
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
Resolution
ANALOG INPUT
16
16
Bits
Voltage range
Impedance
±10
8.885
75
±10
8.885
75
V
kΩ
pF
Capacitance
THROUGHPUT SPEED
Conversion cycle time
Throughput rate
DC ACCURACY
Acquire and convert
4
4
µs
250
250
kHz
INL
Integral linearity error
Differential linearity error
No missing codes
-3
-1
3
2
-2
-1
2
1
LSB(1)
LSB(1)
Bits
DNL
16
16
Transition noise(2)
0.67
0.67
LSB
(1) LSB means least significant bit. For the 16-bit, ±10-V input ADS8515, one LSB is 305 µV.
(2) Typical rms noise at worst case transitions and temperatures.
2
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SLAS460A–JUNE 2007–REVISED NOVEMBER 2007
ELECTRICAL CHARACTERISTICS (continued)
TA = -40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, using internal reference (unless otherwise noted)
ADS8515I
TYP
ADS8515IB
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
TYP
MAX
Full-scale
-0.5
0.5
-0.25
0.25
Int. Ref.
%FSR
ppm/°C
%FSR
error(3)(4)
Full-scale error drift
Int. Ref.
±7
±7
Full-scale
error(3)(4)
-0.25
0.25
-0.1
0.1
Ext. 4.096-V Ref.
Ext. 4.096-V Ref.
Full-scale error drift
Bipolar zero error(3)
Bipolar zero error drift
±2
±2
±2
±2
ppm/°C
mV
-4
-8
4
8
-2
-8
2
8
ppm/°C
Power supply sensitivity
(VDIG = VANA = VD)
+4.75 V < VD < +5.25 V
LSB
AC ACCURACY
SFDR
THD
Spurious-free dynamic range
Total harmonic distortion
fI = 20 kHz
fI = 20 kHz
fI = 20 kHz
–60-dB Input
fI = 20 kHz
95
87
88
102
-100
91
97
89
90
102
-100
91
dB(5)
dB
-94
-96
dB
SINAD
SNR
Signal-to-(noise+distortion)
30
32
dB
Signal-to-noise ratio
92
92
dB
Full-power bandwidth(6)
500
500
kHz
SAMPLING DYNAMICS
Aperture delay
5
5
ns
µs
ns
Transient response
Overvoltage recovery(7)
REFERENCE
FS Step
2
2
150
150
Internal reference voltage
4.076
3.9
4.096
1
4.116
4.076
3.9
4.096
1
4.116
V
µA
Internal reference source current (must
use external buffer)
Internal reference drift
8
8
ppm/°C
V
External reference voltage range for
specified linearity
4.096
4.2
4.096
4.2
External reference current drain
Ext. 4.096-V Ref.
100
100
µA
DIGITAL INPUTS
Logic levels
VIL
VIH
IIL
Low-level input voltage
High-level input voltage
Low-level input current
High-level input current
VDIG = 1.65 V – 5.25 V
VDIG = 1.65 V – 5.25 V
VIL = 0 V
-0.3
0.8
VDIG+0.3 V
±10
-0.3
0.35*VDIG
VDIG+0.3 V
±10
V
V
0.65*VDIG
0.65*VDIG
µA
µA
IIH
VIH = 5 V
±10
±10
DIGITAL OUTPUTS
Data format (Parallel 16-bits)
Data coding (Binary 2's complement)
Low-level output voltage
VOL
VOH
ISINK = 1.6 mA
0.4
0.4
V
V
High-level output voltage
ISOURCE = 500 µA
0.8×VDIG
0.8×VDIG
Hi-Z state,
VOUT = 0 V to VDIG
±5
15
±5
15
µA
Leakage current
Output capacitance
Hi-Z state
pF
DIGITAL TIMING
Bus access timing
Bus relinquish timing
POWER SUPPLIES
83
83
83
83
ns
ns
(3) As measured with fixed resistors shown in Figure 22. Adjustable to zero with external potentiometer.
(4) Full-scale error is the worst case of -full-scale or +full-scale deviation from ideal first and last code transitions, divided by the transition
voltage (not divided by the full-scale range) and includes the effect of offset error.
(5) All specifications in dB are referred to a full-scale ±10-V input.
(6) Full-power bandwidth is defined as the full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 dB, or 10 bits of
accuracy.
(7) Recovers to specified performance after 2 x FS input overvoltage.
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SLAS460A–JUNE 2007–REVISED NOVEMBER 2007
ELECTRICAL CHARACTERISTICS (continued)
TA = -40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, using internal reference (unless otherwise noted)
ADS8515I
TYP
ADS8515IB
PARAMETER
TEST CONDITIONS
UNIT
MAX
MIN
1.65
4.75
MAX
5.25
5.25
1
MIN
1.65
4.75
TYP
VDIG
VANA
IDIG
Digital input voltage
Analog input voltage
Digital input current
Analog input current
Power dissipation
5.25
5.25
1
V
V
5
0.1
20
5
0.1
20
Must be ≤ VANA
mA
mA
mW
IANA
25
25
fS = 250 kHz
100
125
100
125
TEMPERATURE RANGE
Specified performance
-40
-55
-65
85
125
150
-40
-55
-65
85
125
150
°C
°C
°C
Derated performance(8)
Storage
THERMAL RESISTANCE (ΘJA
)
SSOP
67
67
°C/W
(8) The internal reference may not be started correctly beyond the industrial temperature range (-40°C to 85°C), therefore use of an
external reference is recommended.
4
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SLAS460A–JUNE 2007–REVISED NOVEMBER 2007
DEVICE INFORMATION
DB PACKAGE
(TOP VIEW)
V
1
2
3
4
5
6
7
8
9
28 V
DIG
IN
AGND1
REF
27 V
ANA
26
BUSY
CAP
25 CS
AGND2
D15 (MSB)
D14
24 R/C
23
BYTE
22 D0 (LSB)
21
20
D13
D1
D2
D12
D11 10
19 D3
11
18
17
D4
D5
D10
12
D9
13
14
16 D6
15
D8
D7
DGND
Terminal Functions
TERMINAL
DIGITAL
I/O
DESCRIPTION
NAME
SSOP
NO.
AGND1
2
5
Analog ground. Used internally as ground reference point.
Analog ground.
AGND2
BUSY
26
O
I
At the start of a conversion, BUSY goes low and stays low until the conversion is
completed and the digital outputs have been updated.
BYTE
CAP
23
4
Selects 8 most significant bits (low) or 8 least significant bits (high).
Reference buffer capacitor. 2.2-µF tantalum capacitor to ground.
Internally ORed with R/C. If R/C low, a falling edge on CS initiates a new conversion.
Digital ground.
CS
25
14
6
I
DGND
D15 (MSB)
O
Data bit 15. Most significant bit (MSB) of conversion results. Hi-Z state when CS is high, or
when R/C is low.
D14
D13
D12
D11
D10
D9
7
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Data bit 14. Hi-Z state when CS is high, or when R/C is low.
Data bit 13. Hi-Z state when CS is high, or when R/C is low.
Data bit 12. Hi-Z state when CS is high, or when R/C is low.
Data bit 11. Hi-Z state when CS is high, or when R/C is low.
Data bit 10. Hi-Z state when CS is high, or when R/C is low.
Data bit 9. Hi-Z state when CS is high, or when R/C is low.
Data bit 8. Hi-Z state when CS is high, or when R/C is low.
Data bit 7. Hi-Z state when CS is high, or when R/C is low.
Data bit 6. Hi-Z state when CS is high, or when R/C is low.
Data bit 5. Hi-Z state when CS is high, or when R/C is low.
Data bit 4. Hi-Z state when CS is high, or when R/C is low.
Data bit 3. Hi-Z state when CS is high, or when R/C is low.
Data bit 2. Hi-Z state when CS is high, or when R/C is low.
Data bit 1. Hi-Z state when CS is high, or when R/C is low.
8
9
10
11
12
13
15
16
17
18
19
20
21
D8
D7
D6
D5
D4
D3
D2
D1
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Terminal Functions (continued)
D0 (LSB)
R/C
22
24
O
I
Data bit 0. Least significant bit (LSB) of conversion results. Hi-Z state when CS is high, or
when R/C is low.
With CS low and BUSY high, a falling edge on R/C initiates a new conversion. With CS
low, a rising edge on R/C enables the parallel output.
REF
3
Reference input/output. 2.2-µF tantalum capacitor to ground.
VANA
27
Analog supply input. Nominally +5 V. Decouple to ground with 0.1-µF ceramic and 10-µF
tantalum capacitors.
VDIG
VIN
28
1
Digital supply input. Nominally +5 V. Connect directly to pin 27. Must be ≤ VANA.
Analog input. See Figure 24
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
SIGNAL-TO-NOISE RATIO
vs
SIGNAL-TO-NOISE AND DISTORTION
vs
vs
INPUT FREQUENCY
INPUT FREQUENCY
INPUT FREQUENCY
95
90
85
95
100
95
90
85
80
90
85
80
80
75
70
75
70
75
70
1
10
100
1000
1
10
100
1000
1
10
100
1000
fi - input frequency - kHz
fi - input frequency - kHz
f
- Input Frequency - kHz
i
Figure 1.
Figure 2.
Figure 3.
SPURIOUS FREE DYNAMIC RANGE
SIGNAL-TO-NOISE RATIO
vs
FREE-AIR TEMPERATURE
SIGNAL-TO-NOISE AND DISTORTION
vs
vs
INPUT FREQUENCY
FREE-AIR TEMPERATURE
105
100
95
100
fs = 250 KSPS
fi = 20 kHz
fs = 250 KSPS
fi = 20 kHz
100
95
90
85
80
75
70
95
90
85
90
85
80
80
75
70
75
70
-55 -40 -25 -10
5
20 35 50 65 80 95 110125
110
125
-55 -40 -25-10
5
20 35 50 65 80 95
1
10
100
1000
TA - Free-Air-Temperature - °C
TA - Free-Air-Temperature - °C
fi - input frequency - kHz
Figure 4.
Figure 5.
Figure 6.
6
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SLAS460A–JUNE 2007–REVISED NOVEMBER 2007
TYPICAL CHARACTERISTICS (continued)
SPURIOUS FREE DYNAMIC RANGE
TOTAL HARMONIC DISTORTION
vs
INTERNAL REFERENCE VOLTAGE
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
4.1
100
-70
-75
fs = 250 KSPS
fi = 20 kHz
4.099
4.098
4.097
95
90
85
80
75
70
-80
-85
4.096
4.095
4.094
-90
4.093
4.092
4.091
4.09
-95
fs = 250 KSPS
fi = 20 kHz
-100
-55 -40 -25 -10
5
20 35 50 65 80 95 110125
-40 -25 -10
5
20 35 50 65 80
-55 -40 -25 -10
5
20 35 50 65 80 95 110125
TA - Free-Air-Temperature - °C
TA - Free-Air-Temperature - °C
TA - Free-Air-Temperature - °C
Figure 7.
Figure 8.
Figure 9.
BIPOLAR ZERO ERROR
vs
FREE-AIR TEMPERATURE
NEGATIVE FULL-SCALE ERROR
vs
NEGATIVE FULL-SCALE ERROR
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
5
0.25
0.2 Internal Reference
0.15
0.1
0.08
0.06
0.04
0.02
0
External Reference
4
3
2
1
0.1
0.05
0
0
-1
-0.02
-0.05
-2
-0.1
-0.04
-0.06
-3
-4
-5
-0.15
-0.08
-0.1
-0.2
-0.25
-40 -25 -10
5
20 35 50 65 80
-40 -25 -10
5
20 35 50 65 80
-40 -25 -10
5
20 35 50 65 80
TA - Free-Air-Temperature - °C
TA - Free-Air-Temperature - °C
TA - Free-Air-Temperature - °C
Figure 10.
Figure 11.
Figure 12.
POSITIVE FULL-SCALE ERROR
vs
FREE-AIR TEMPERATURE
POSITIVE FULL-SCALE ERROR
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
0.25
0.2
0.1
0.08
0.06
0.025
External Reference
Internal Reference
0.15
0.1
0.023
0.021
0.04
0.02
0.05
0
0
-0.02
-0.04
-0.06
-0.05
-0.1
-0.15
0.019
0.017
0.015
-0.2
-0.08
-0.1
-0.25
-40 -25 -10
5
20 35 50 65 80
-40 -25 -10
5
20 35 50 65 80
-40 -25 -10
5
20 35 50 65 80
TA - Free-Air-Temperature - °C
TA - Free-Air-Temperature - °C
TA - Free-Air-Temperature - °C
Figure 13.
Figure 14.
Figure 15.
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TYPICAL CHARACTERISTICS (continued)
HISTOGRAM
4500
4000
3500
3000
4103
3645
2500
2000
1500
1000
335
500
0
109
0
0
0
0
65529
65531
65532
Code
65533
65535
65536
65530
65534
Figure 16.
INL
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
0
10000
20000
30000
40000
50000
60000
70000
Code
Figure 17.
DNL
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
0
10000
20000
30000
40000
50000
60000
70000
Code
Figure 18.
BASIC OPERATION
Figure 19 shows a basic circuit to operate the ADS8515 with a full parallel data output. Taking R/C (pin 24) low
for a minimum of 40 ns initiates a conversion. BUSY (pin 26) goes low and stays low until the conversion is
completed and the output registers are updated. Data is output in binary 2's complement with the MSB on pin 6.
BUSY going high can be used to latch the data.
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The ADS8515 begins tracking the input signal at the end of the conversion. Allowing 4 µs between convert
commands assures accurate acquisition of a new signal.
STARTING A CONVERSION
The combination of CS (pin 25) and R/C (pin 24) low for a minimum of 40 ns immediately puts the sample/hold of
the ADS8515 in the hold state and starts conversion n. BUSY (pin 26) goes low and stays low until conversion n
is completed and the internal output register has been updated.
The ADS8515 begins tracking the input signal at the end of the conversion. Allowing 4 µs between convert
commands assures accurate acquisition of a new signal. Refer to Table 1 for a summary of CS, R/C, and BUSY
states and Figure 21, Figure 22, and Figure 23 for the timing diagrams.
CS and R/C are internally ORed and level triggered. There is not a requirement which input goes low first when
initiating a conversion. If, however, it is critical that CS or R/C initiates conversion n, be sure the less critical input
is low at least 10 ns prior to the initiating input.
To reduce the number of control pins, CS can be tied low using R/C to control the read and convert modes. The
parallel output becomes active whenever R/C goes high. Refer to the Reading Data section.
Table 1. Control Line Functions for Read and Convert
CS
1
R/C
X
0
BUSY
OPERATION
X
1
1
↑
None. Databus is in Hi-Z state.
↓
Initiates conversion n. Databus remains in Hi-Z state.
0
↓
Initiates conversion n. Databus enters Hi-Z state.
0
1
Conversion n completed. Valid data from conversion n on the databus.
Enables databus with valid data from conversion n.
Enables databus with valid data from conversion –1(1). Conversion n in progress.
Enables databus with valid data from conversion –1(1). Conversion n in progress.
↓
1
1
0
0
↑
↓
1
0
↑
0
0
New conversion initiated without acquisition of a new signal. Data is invalid. CS and/or R/C
must be high when BUSY goes high.
X
X
0
Conversion n in progress.
(1) See Figure 21 and Figure 22 for constraints on data valid from conversion n-1.
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+5V
10 µF
+
+
0.1 µF
3
+
2.2 µF
BUSY
R/C
4
+
Convert Pulse
40 ns Min
2.2 µF
5
6
D15 (MSB)
D14
7
D0 (LSB)
D1
ADS8515
8
D13
9
D2
D12
D11
D10
D9
10
11
12
13
14
D3
D4
D5
D8
D6
D7
Figure 19. Basic Operation
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READING DATA
The ADS8515 outputs full or byte-reading parallel data in binary 2's complement data output format. The parallel
output is active when R/C (pin 24) is high and CS (pin 25) is low. Any other combination of CS and R/C 3-states
the parallel output. Valid conversion data can be read in a full parallel, 16-bit word or two 8-bit bytes on pins 6-13
and pins 15-22. BYTE (pin 23) can be toggled to read both bytes within one conversion cycle. Refer to Table 2
for ideal output codes and Figure 20 for bit locations relative to the state of BYTE.
Table 2. Ideal Input Voltages and Output Codes
DIGITAL OUTPUT BINARY 2's COMPLEMENT
DESCRIPTION
ANALOG INPUT
BINARY CODE
HEX CODE
Full-scale range
Least significant bit (LSB)
Full scale (10 V-1 LSB)
Midscale
±10 V
305 µV
9.999695 V
0 V
0111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
1000 0000 0000 0000
7FFF
0000
FFFF
8000
One LSB below midscale
-Full scale
-305 µV
-10 V
PARALLEL OUTPUT (After a Conversion)
After conversion n is completed and the output registers have been updated, BUSY (pin 26) goes high. Valid
data from conversion n is available on D15-D0 (pins 6-13 and 15-22). BUSY going high can be used to latch the
data. Refer to Table 3 and Figure 21, Figure 22, and Figure 23 for timing specifications.
PARALLEL OUTPUT (During a Conversion)
After conversion n has been initiated, valid data from conversion –1 can be read and is valid up to t2 after the
start of conversion n. Do not attempt to read data from t2 after the start of conversion n until BUSY (pin 26) goes
high; this may result in reading invalid data. Refer to Table 3 and Figure 21, Figure 22, and Figure 23 for timing
specifications.
Note: For the best possible performance, data should not be read during a conversion. The switching noise of
the asynchronous data transfer can cause digital feedthrough degrading the converter's performance.
The number of control lines can be reduced by tying CS low while using the falling edge of R/C to initiate
conversions and the rising edge of R/C to activate the output mode of the converter. See Figure 21.
Table 3. Conversion Timing
SYMBOL DESCRIPTION
tw1 Pulse duration, convert
ta
MIN
TYP
MAX
UNITS
ns
40
Access time, data valid after R/C low
Propagation delay time, BUSY from R/C low
Pulse duration, BUSY low
0.8
6
1.2
20
2
µs
ns
tpd
tw2
td1
td2
tconv
tacq
tdis
td3
tv
µs
ns
Delay time, BUSY after end of conversion
Delay time, aperture
5
5
ns
Conversion time
2
µs
µs
ns
Acquisition time
2
Disable time, bus
10
35
1.5
15
50
2
83
Delay time, BUSY after data valid
Valid time, previous data remains valid after R/C low
ns
µs
µs
ns
tconv + tacq Throughput time
4
tsu
tc
Setup time, R/C to CS
10
4
Cycle time between conversions
Enable time, bus
µs
ns
ten
td4
10
10
15
15
30
30
Delay time, BYTE
ns
10
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BYTE LOW
ADS8515
BYTE HIGH
+5 V
Bit 8
Bit 15 (MSB)
Bit 14
6
7
23
22
21
20
19
18
17
16
15
6
23
22
21
20
19
18
17
16
15
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
7
Bit 0 (LSB)
Bit 1
ADS8515
Bit 13
8
8
Bit 9
Bit 12
9
9
Bit 10
Bit 2
Bit 11
10
10
11
12
13
14
Bit 11
Bit 3
Bit 10 11
Bit 9 12
Bit 12
Bit 4
Bit 13
Bit 5
Bit 8
13
14
Bit 0 (LSB)
Bit 14
Bit 6
Bit 7
Bit 15 (MSB)
Figure 20. Bit Locations Relative to State of BYTE (Pin 23)
t
w1
R/C
t
c
t
a1
t
w2
BUSY
MODE
t
t
pd
t
d1
d2
Acquire
Convert
t
Acquire
Convert
t
conv
acq
Previous
Data Valid
Previous
Data Valid
Hi−Z
Not Valid Data Valid
Hi−Z
Data Valid
DATA BUS
t
d3
t
dis
t
v
Figure 21. Conversion Timing with Outputs Enabled after Conversion (CS Tied Low)
t
su
t
su
t
su
t
su
R/C
CS
t
w1
t
pd
t
w2
BUSY
MODE
t
d2
Convert
conv
Acquire
Acquire
t
Hi−Z State
Data Valid
DATA BUS
Hi−Z State
t
en
t
dis
Figure 22. Using CS to Control Conversion and Read Timing
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t
su
t
su
R/C
CS
BYTE
Pins 6 − 13 Hi−Z
High Byte
Low Byte
Hi−Z
t
en
t
d4
t
dis
Pins 15 − 22 Hi−Z
Low Byte
High Byte
Hi−Z
Figure 23. Using CS and BYTE to Control Data Bus
ADC RESET
The ADC reset function of the ADS8515 can be used to terminate the current conversion cycle. Bringing R/C low
for at least 40 ns while BUSY is low will initiate the ADC reset. To initiate a new conversion, R/C must return to
the high state and remain high long enough to acquire a new sample (see Table 3, tc) before going low to initiate
the next conversion sequence. In applications that do not monitor the BUSY signal, it is recommended that the
ADC reset function be implemented as part of a system initialization sequence.
INPUT RANGES
The ADS8515 offers a standard ±10-V input range. Figure 24 shows the necessary circuit connections for the
ADS8515 with and without hardware trim. Offset and full-scale error specifications are tested and specified with
the fixed resistors shown in Figure 25(b). Full-scale error includes offset and gain errors measured at both +FS
and -FS. Adjustments for offset and gain are described in the Calibration section of this data sheet.
The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors
compensate for this adjustment and can be left out if the offset and gain are corrected in software (refer to the
Calibration section).
The nominal input impedance of 6.35 kΩ results from the combination of the internal resistor network shown on
the front page of the product data sheet. The input resistor divider network provides inherent overvoltage
protection assured to at least ±25 V. The 1% resistors used for the external circuitry do not compromise the
accuracy or drift of the converter. They have little influence relative to the internal resistors, and tighter tolerances
are not required.
The input signal must be referenced to AGND1. This minimizes the ground loop problem typical to analog
designs. The analog signal should be driven by a low impedance source. A typical driving circuit using an
OPA627 or OPA132 is shown in Figure 24.
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+15V
2.2 mF
22 pF
ADS8515
VIN
100 nF
GND
Vin
2 kW
Pin 7
Pin 2
Pin1
2 kW
REF
−
OPA 627
22 pF
2.2 mF
or
Pin 6
OPA 132
+
AGND1
Pin3
Pin4
GND
CAP
2.2 mF
2.2 mF
GND
DGND
GND
100 nF
GND
AGND2
−15V
GND
Figure 24. Typical Driving Circuit (±10 V, No Trim)
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APPLICATION INFORMATION
CALIBRATION
The gain of the ADS8515 can be trimmed in software. To achieve optimum performance, several iterations may
be required.
Hardware Calibration
To calibrate the gain of the ADS8515, install the resistors and potentiometer as shown in Figure 25(a). The
calibration range is approximately ±100 mV.
Software Calibration
The offset and gain of the ADS8515 is calibrated with software. See Figure 25(b) for the circuit connections.
1
2
3
4
5
1
2
3
4
5
±10 V
V
IN
V
±10 V
IN
AGND1
REF
AGND1
REF
+5 V
2.2 µF
2.2 µF
2.2 µF
+
+
+
175 kΩ
20 kΩ
30 kΩ
CAP
CAP
+
Gain
2.2 µF
AGND2
AGND2
(a) ±10 V With Hardware Trim
Note: Use 1% metal film resistors.
(b) ±10 V Without Hardware Trim
Figure 25. Circuit Diagram For Software Trim
REFERENCE
The ADS8515 can operate with its internal 4.096-V reference or an external reference. By applying an external
reference to pin 5, the internal reference can be bypassed. The reference voltage at REF is buffered internally
with the output on CAP (pin 4).
The internal reference has an 8 ppm/°C drift (typical) and accounts for approximately 20% of the full-scale error
(FSE = ±0.5% for low grade, ±0.25% for high grade).
REF
REF (pin 3) is an input for an external reference or the output for the internal 4.096-V reference. A 2.2-µF
capacitor should be connected as close to the REF pin as possible. The capacitor and the output resistance of
REF create a low-pass filter to bandlimit noise on the reference. Using a smaller value capacitor introduces more
noise to the reference degrading the SNR and SINAD. The REF pin should not be used to drive external ac or dc
loads.
The range for the external reference is 3.9 V to 4.2 V and determines the actual LSB size. Increasing the
reference voltage increases the full-scale range and the LSB size of the converter which can improve the SNR.
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CAP
CAP (pin 4) is the output of the internal reference buffer. A 2.2-µF capacitor should be placed as close to the
CAP pin as possible to provide optimum switching currents for the CDAC throughout the conversion cycle and
compensation for the output of the internal buffer. Using a capacitor any smaller than 1 µF can cause the output
buffer to oscillate and may not have sufficient charge for the CDAC. Capacitor values larger than 2.2 µF have
little affect on improving performance. The ESR (equivalent series resistance) of these compensation capacitors
is also critical. Keep the total ESR under 3 Ω. See Typical Characteristics section for how the worst case ILE is
affected by ESR.
The output of the buffer is capable of driving up to 2 mA of current to a dc load, but any external load from the
CAP pin may degrade the linearity of the ADS8515. Using an external buffer allows the internal reference to be
used for larger dc loads and ac loads. Do not attempt to directly drive an ac load with the output voltage on CAP.
This causes performance degradation of the converter. The ESR (equivalent series resistance) of these
compensation capacitors is also critical. Keep the total ESR under 3 Ω. See the TYPICAL CHARACTERISTICS
section concerning how ESR affects performance.
LAYOUT
POWER
For optimum performance, tie the analog and digital power pins to the same +5-V power supply and tie the
analog and digital grounds together. As noted in the electrical specifications, the ADS8515 uses 90% of its power
for the analog circuitry. The ADS8515 should be considered as an analog component.
The +5-V power for the A/D should be separate from the +5 V used for the system's digital logic. Connecting
VDIG (pin 28) directly to a digital supply can reduce converter performance due to switching noise from the digital
logic. For best performance, the +5-V supply can be produced from whatever analog supply is used for the rest
of the analog signal conditioning. If +12-V or +15-V supplies are present, a simple +5-V regulator can be used.
Although it is not suggested, if the digital supply must be used to power the converter, be sure to properly filter
the supply. Either using a filtered digital supply or a regulated analog supply, both VDIG and VANA should be tied
to the same +5-V source.
GROUNDING
Three ground pins are present on the ADS8515. DGND is the digital supply ground. AGND2 is the analog supply
ground. AGND1 is the ground which all analog signals internal to the A/D are referenced. AGND1 is more
susceptible to current induced voltage drops and must have the path of least resistance back to the power
supply.
All the ground pins of the A/D should be tied to the analog ground plane, separated from the system's digital
logic ground, to achieve optimum performance. Both analog and digital ground planes should be tied to the
system ground as near to the power supplies as possible. This helps to prevent dynamic digital ground currents
from modulating the analog ground through a common impedance to power ground.
SIGNAL CONDITIONING
The FET switches used for the sample hold on many CMOS A/D converters release a significant amount of
charge injection which can cause the driving op amp to oscillate. The FET switch on the ADS8515, compared to
the FET switches on other CMOS A/D converters, releases 5%-10% of the charge. There is also a resistive front
end which attenuates any charge which is released. The end result is a minimal requirement for the anti-alias
filter on the front end. Any op amp sufficient for the signal in an application is sufficient to drive the ADS8515.
The resistive front end of the ADS8515 also provides an assured ±25-V overvoltage protection. In most cases,
this eliminates the need for external input protection circuitry.
INTERMEDIATE LATCHES
The ADS8515 does have 3-state outputs for the parallel port, but intermediate latches should be used if the bus
is to be active during conversions. If the bus is not active during conversion, the 3-state outputs can be used to
isolate the A/D from other peripherals on the same bus. The 3-state outputs can also be used when the A/D is
the only peripheral on the data bus.
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Intermediate latches are beneficial on any monolithic A/D converter. The ADS8515 has an internal LSB size of
38 µV. Transients from fast switching signals on the parallel port, even when the A/D is 3-stated, can be coupled
through the substrate to the analog circuitry causing degradation of converter performance.
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Revision History
Changes from Original (June 2007) to Revision A ......................................................................................................... Page
Changed ADS8515I VIH MIN from 2 V to 0.65*VDIG .............................................................................................................. 3
•
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PACKAGE OPTION ADDENDUM
www.ti.com
29-Aug-2007
PACKAGING INFORMATION
Orderable Device
ADS8515IBDBR
ADS8515IBDBRG4
ADS8515IDB
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DB
28
28
28
28
28
28
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP
SSOP
SSOP
SSOP
SSOP
DB
DB
DB
DB
DB
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
ADS8515IDBG4
ADS8515IDBR
50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
ADS8515IDBRG4
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Nov-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
(mm)
16
ADS8515IBDBR
ADS8515IDBR
DB
DB
28
28
SITE 60
SITE 60
8.1
8.2
10.4
10.5
2.5
2.5
12
12
16
16
Q1
Q1
330
16
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Nov-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
ADS8515IBDBR
ADS8515IDBR
DB
DB
28
28
SITE 60
SITE 60
346.0
346.0
346.0
346.0
33.0
33.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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