ADS8517IBDWRG4 [TI]
1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PDSO28, GREEN, PLASTIC, SOIC-28;型号: | ADS8517IBDWRG4 |
厂家: | TEXAS INSTRUMENTS |
描述: | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PDSO28, GREEN, PLASTIC, SOIC-28 光电二极管 转换器 |
文件: | 总38页 (文件大小:960K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ADS8517
www.ti.com ................................................................................................................................................. SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009
16-Bit, 200-kSPS, Low-Power, Sampling ANALOG-TO-DIGITAL CONVERTER
with Internal Reference and Parallel/Serial Interface
1
FEATURES
APPLICATIONS
•
•
•
•
•
•
Portable Test Equipment
USB Data Acquisition Module
Medical Equipment
Industrial Process Control
Digital Signal Processing
Instrumentation
23
•
200-kHz Minimum Sampling Rate
•
4-V, 5-V, and ±10-V Input Ranges with
High-Impedance Input
•
•
•
•
•
•
±1.5 LSB Max INL
+1.5/–1 LSB Max/Min DNL, 16 Bits NMC
±2-mV Max BPZ, ±0.6 ppm/°C BPZ Drift
±2-mV Max UPZ, ±0.15 ppm/°C UPZ Drift
88.8-dB SINAD with 10-kHz Input
DESCRIPTION
The ADS8517 is a complete low-power, single 5-V
supply, 16-bit sampling analog-to-digital (A/D)
converter.
capacitor-based, successive approximation register
(SAR) A/D converter with sample-and-hold, clock,
reference, and data interface. The converter can be
configured for a variety of input ranges including
±10 V, 4 V, and 5 V. For most input ranges, the input
voltage can swing to 25 V or –25 V without damage
to the device.
SPI™-Compatible Serial Output With
Daisy-Chain (TAG), SPI Master/Slave Feature
It
contains
a
complete,
16-bit,
•
•
Full Parallel Interface
Binary Twos Complement or Straight Binary
Output Code Formats
•
Single 4.5-V to 5.5-V Analog Supply, 1.65-V to
5.5-V Interface Supply
•
•
•
Uses Internal 2.5-V or External Reference
No External Precision Resistors Required
Low Power Dissipation (ADC+REF+BUF):
An SPI-compatible serial interface allows data to be
synchronized to an internal or external clock. A full
parallel interface using the selectable BYTE pin is
also provided to allow the maximum system design
flexibility. The ADS8517 is specified at a 200-kHz
sampling rate over the industrial –40°C to +85°C
temperature range.
–
47 mW Typ, 60 mW Max at 200 kSPS
•
•
50-µW Max Power-Down Mode
Pin-Compatible with 16-Bit ADS7807 and
ADS8507, and 12-Bit ADS7806 and ADS8506
•
SO-28 and TSSOP-28 Packages
ADC
Parallel
Data
Successive Approximation Register (SAR)
PWRD
BYTE
BUSY
CS
Parallel
and
CDAC
40 kW
Serial
Data Out
and
R1IN
R/C
SB/BTC
TAG
Control
10 kW
SDATA
DATACLK
20 kW
40 kW
R2IN
CAP
Comparator
EXT/INT
REFD
Clock
BUF
Ref
Buffer
REF
6 kW
2.5-V
Internal Reference
REF
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
SPI is a trademark of Motorola, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2009, Texas Instruments Incorporated
ADS8517
SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009................................................................................................................................................. www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PACKAGE/ORDERING INFORMATION(1)
MINIMUM
RELATIVE
ACCURACY
(LSB)
NO
MISSING
CODE
MINIMUM
SINAD
(dB)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
ORDERING
NUMBER
TRANSPORT
MEDIA, QTY
PRODUCT
ADS8517IBDW
ADS8517IBDWR
ADS8517IBPW
ADS8517IBPWR
ADS8517IDW
ADS8517IDWR
ADS8517W
Tube, 20
Tape and Reel, 1000
Tube, 50
SO-28
TSSOP-28
SO-28
DW
PW
DW
PW
ADS8517IB
±1.5
±3
16
15
87
85
-40°C to +85°C
-40°C to +85°C
Tape and Reel, 2000
Tube, 20
Tape and Reel, 1000
Tube, 50
ADS8517I
TSSOP-28
ADS8517IPWR
Tape and Reel, 2000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(1)(2)
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted).
UNIT
R1IN
±25 V
Analog inputs
R2IN
±25 V
REF
+VANA + 0.3 V to AGND2 – 0.3 V
DGND, AGND2
VANA
±0.3 V
6 V
Ground voltage differences
VDIG to VANA
VDIG
0.3 V
6 V
Digital inputs
-0.3 V to +VDIG + 0.3 V
+165°C
Maximum junction temperature
Storage temperature range
Internal power dissipation
–65°C to +150°C
700 mW
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
ELECTRICAL CHARACTERISTICS
At TA = -40°C to +85°C, fS = 200 kHz, VDIG = VANA = 5 V, using internal reference (see Figure 39), unless otherwise noted.
ADS8517I
TYP
ADS8517IB(1)
PARAMETER
Resolution
ANALOG INPUT
TEST CONDITIONS
MIN
MAX
MIN
TYP
MAX
UNIT
16
16
Bits
–10
0
10
–10
0
10
5
Voltage ranges
See Table 1
5
4
V
0
0
4
Impedance
See Table 1
Capacitance
45
45
pF
(1) Shaded cells indicate different specifications for high-grade version of the device.
2
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8517
ADS8517
www.ti.com ................................................................................................................................................. SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009
ELECTRICAL CHARACTERISTICS (continued)
At TA = -40°C to +85°C, fS = 200 kHz, VDIG = VANA = 5 V, using internal reference (see Figure 39), unless otherwise noted.
ADS8517I
TYP
ADS8517IB(1)
PARAMETER
THROUGHPUT SPEED
TEST CONDITIONS
MIN
MAX
MIN
TYP
MAX
UNIT
Conversion time
Complete cycle
Throughput rate
2.5
5
2.5
5
µs
µs
Acquire and convert
200
200
kHz
DC ACCURACY
INL
Integral linearity error
Differential linearity error
No missing codes
Transition noise(3)
Gain error
–3
–2
15
3
3
–1.5
–1
1.5 LSB(2)
DNL
1.5
LSB
Bits
16
0.9
0.8
LSB
±0.2
±0.1
%
Internal reference
–0.75
–0.75
0.75
0.75
–0.75
–0.75
0.75
0.75
%
Full-scale error(4)
External 2.5-V reference
Internal reference
%
±9
±1
±9
±1
ppm/°C
ppm/°C
mV
Full-scale error drift
External 2.5-V reference
±10 V range
BPZ
UPZ
Bipolar zero error
–5
–3
±1
5
3
–2
–2
±1
2
2
Bipolar zero error drift
Unipolar zero error
Unipolar zero error drift
±10 V range
±0.6
±0.1
±0.15
±0.6
±0.1
±0.15
ppm/°C
mV
0 V to 5 V, 0 V to 4 V ranges
0 V to 5 V, 0 V to 4 V ranges
ppm/°C
Recovery time to rated accuracy
from power down(5)
2.2-µF capacitor to CAP
1
1
ms
+4.75 V < VANA < +5.25 V
+4.5 V < VANA < +5.5 V
–8
+8
–6
+6
Power-supply sensitivity
(VDIG = VANA = VS)
LSB
–20
+20
–12
+12
AC ACCURACY
SFDR
THD
Spurious-free dynamic range
Total harmonic distortion
fIN = 10 kHz, ±10 V
fIN = 10 kHz, ±10 V
fIN = 10 kHz, ±10 V
–60 dB Input
92
85
85
100
–97
88
96
87
88
101
–98
88.5
29
dB(6)
dB
–92
–95
SINAD Signal-to-(noise+distortion)
dB
29
SNR
Signal-to-noise ratio
SNR usable bandwidth(7)
fIN = 10 kHz, ±10 V
fIN = 10 kHz, ±10 V
88
89
dB
130
600
130
600
kHz
kHz
SNR full-power bandwidth (–3 dB) fIN = 10 kHz, ±10 V
SAMPLING DYNAMICS
Aperture delay
40
20
40
20
ns
ps
µs
ns
Aperture jitter
Transient response
Overvoltage recovery(8)
FS step
5
5
750
750
(2) LSB means Least Significant Bit. One LSB for the ±10 V input range is 305 µV.
(3) Typical rms noise at worst-case transitions.
(4) Full-scale error is the worst case of –Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by
the transition voltage (not divided by the full-scale range) and includes the effect of offset error.
(5) This is the time delay after the ADS8517 is brought out of Power-Down mode until all internal settling occurs and the analog input is
acquired to rated accuracy. A Convert command after this delay will yield accurate results.
(6) All specifications in dB are referred to a full-scale input.
(7) Usable bandwidth defined as full-scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60 dB.
(8) Recovers to specified performance after 2 x FS input overvoltage.
Copyright © 2008–2009, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Link(s): ADS8517
ADS8517
SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009................................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
At TA = -40°C to +85°C, fS = 200 kHz, VDIG = VANA = 5 V, using internal reference (see Figure 39), unless otherwise noted.
ADS8517I
TYP
ADS8517IB(1)
PARAMETER
TEST CONDITIONS
MIN
MAX
MIN
TYP
MAX
UNIT
REFERENCE
Internal reference voltage
No load
2.48
2.5
1
2.52
2.48
2.5
1
2.52
V
µA
Internal reference source current
(must use external buffer)
Internal reference drift
8
8
ppm/°C
V
External reference voltage range
for specified linearity
2.3
2.5
2.7
2.3
2.5
2.7
External reference current drain
External 2.5-V reference
100
100
µA
DIGITAL INPUTS
VIL
VIH
IIL
Low-level input voltage(9)
High-level input voltage(9)
Low-level input current
High-level input current
VDIG = 1.65 V to 5.5 V
VDIG = 1.65 V to 5.5 V
VIL = 0 V
–0.3
0.6
VDIG + 0.3
±10
–0.3
0.6
VDIG + 0.3
±10
V
V
0.5 x VDIG
0.5 x VDIG
µA
µA
IIH
VIH = 5 V
±10
±10
DIGITAL OUTPUTS
Data format - Parallel 16-bits in 2-bytes, Serial
Data coding - Binary twos complement or straight binary
ISINK = 1.6mA,
Low-level output voltage
VOL
VOH
0.45
0.45
V
V
VDIG = 1.65V to 5.5V
ISOURCE = 500µA,
High-level output voltage
VDIG – 0.45
VDIG – 0.45
VDIG = 1.65V to 5.5V
High-Z state,
Leakage current
±5
15
±5
15
µA
VOUT = 0 V to VDIG
Output capacitance
DIGITAL TIMING
Bus access time
Bus relinquish time
POWER SUPPLIES
High-Z state
pF
RL = 3.3 kΩ, CL = 50 pF
RL = 3.3 kΩ, CL = 10 pF
83
83
83
83
ns
ns
VDIG
VANA
IDIG
Interface voltage
ADC core voltage
Interface current
ADC core current
1.65
4.5
1.8
5
5.5
5.5
1.65
4.5
1.8
5
5.5
5.5
V
V
VDIG = 5 V
VANA = 5 V
0.3
9
0.3
9
mA
mA
IANA
VANA = VDIG = 5 V,
fS = 200 kHz
47
60
47
60
mW
Power dissipation
REFD high with BUF on
PWRD and REFD high
42
50
42
50
mW
µW
TEMPERATURE RANGE
Specified performance
–40
–55
–65
+85
+125
+150
–40
–55
–65
+85
+125
+150
°C
°C
°C
Derated performance
Storage temperature
TSSOP
SO
62
46
62
46
θJA
Thermal impedance
°C/W
(9) TTL-compatible at 5V supply.
Table 1. Analog Input Range Connections (see Figure 38 and Figure 39)
ANALOG INPUT
RANGE
CONNECT R1IN VIA 200 Ω TO
CONNECT R2IN VIA 100 Ω TO
IMPEDANCE
45.7 kΩ
±10 V
VIN
AGND
VIN
CAP
VIN
0 V to 5 V
0 V to 4 V
20.0 kΩ
VIN
21.4 kΩ
4
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8517
ADS8517
www.ti.com ................................................................................................................................................. SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009
PIN CONFIGURATION
DW, PW PACKAGES
SO-28, TSSOP-28
(TOP VIEW)
R1IN
AGND1
R2IN
1
2
3
4
5
6
7
8
9
28 VDIG
27 VANA
26
25
24
REFD
PWRD
BUSY
CAP
REF
23 CS
AGND2
SB/BTC
EXT/INT
D7
R/C
22
21
ADS8517
BYTE
20 TAG
D6 10
19 SDATA
11
12
13
18
17
16
15
D5
D4
D3
DATACLK
D0
D1
D2
DGND 14
PIN ASSIGNMENTS
PIN
DIGITAL
I/O
NAME
R1IN
NO.
1
DESCRIPTION
Analog Input.
AGND1
R2IN
2
Analog sense ground. Used internally as ground reference point. Minimal current flow
Analog Input.
3
CAP
4
Reference buffer output. 2.2-µF tantalum capacitor to ground.
Reference input/output. Outputs internal 2.5-V reference. Can also be driven by external system
reference. In both cases, bypass to ground with a 2.2-µF tantalum capacitor.
REF
5
6
AGND2
Analog ground
Output mode select. Selects straight binary or binary twos complement for output data format. If
high, data are output in a straight binary format. If low, data are output in a binary twos
complement format.
SB/BTC
7
I
External/internal data select. Selects external/internal data clock for transmitting data. If high,
data is output synchronized to the clock input on DATACLK. If low, a convert command initiates
the transmission of the data from the previous conversion, along with 16-clock pulses output on
DATACLK.
EXT/INT
D7
8
9
I
Data bit 7 if BYTE is high. Data bit 15 (MSB) if BYTE is low. High-Z when CS is high and/or R/C
is low. Leave unconnected when using serial output.
O
D6
D5
10
11
12
13
14
15
16
O
O
O
O
Data bit 6 if BYTE is high. Data bit 14 if BYTE is low. High-Z when CS is high and/or R/C is low.
Data bit 5 if BYTE is high. Data bit 13 if BYTE is low. High-Z when CS is high and/or R/C is low.
Data bit 4 if BYTE is high. Data bit 12 if BYTE is low. High-Z when CS is high and/or R/C is low.
Data bit 3 if BYTE is high. Data bit 11 if BYTE is low. High-Z when CS is high and/or R/C is low.
Digital ground
D4
D3
DGND
D2
O
O
Data bit 2 if BYTE is high. Data bit 10 if BYTE is low. High-Z when CS is high and/or R/C is low.
Data bit 1 if BYTE is high. Data bit 9 if BYTE is low. High-Z when CS is high and/or R/C is low.
D1
Data bit 0 (LSB) if BYTE is high. Data bit 8 if BYTE is low. High-Z when CS is high and/or R/C is
low.
D0
17
O
Copyright © 2008–2009, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Link(s): ADS8517
ADS8517
SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009................................................................................................................................................. www.ti.com
PIN ASSIGNMENTS (continued)
Data clock. Either an input or an output, depending on the EXT/INT level. Output data are
DATACLK
SDATA
18
19
I/O
O
synchronized to this clock. If EXT/INT is low, DATACLK transmits 16 pulses after each
conversion, and then remains low between conversions.
Serial data output. Data are synchronized to DATACLK, with the format determined by the level
of SB/BTC. In the external clock mode, after 16 bits of data, the ADC outputs the level input on
TAG as long as CS is low and R/C is high. If EXT/INT is low, data are valid on both the rising
and falling edges of DATACLK, and between conversions SDATA stays at the level of the TAG
input when the conversion was started.
Tag input for use in the external clock mode. If EXT is high, digital data input from TAG is output
on DATA with a delay that depends on the external clock mode.
TAG
20
21
I
I
Byte select. Selects the eight most significant bits (low) or eight least significant bits (high) on
parallel output pins.
BYTE
Read/convert input. With CS low, a falling edge on R/C puts the internal sample-and-hold circuit
into the hold state and starts a conversion. With EXT/INT is low, the transmission of the data
results from the previous conversion is initiated.
R/C
CS
22
23
I
I
Chip select. Internally ORed with R/C. If R/C is low, a falling edge on CS initiates a new
conversion. If EXT/INT is low, this same falling edge will start the transmission of serial data
results from the previous conversion.
Busy output. At the start of a conversion, BUSY goes low and stays low until the conversion is
completed and the digital outputs have been updated.
BUSY
PWRD
REFD
24
25
26
O
I
Power-down input. If high, conversions are inhibited and power consumption is significantly
reduced. Results from the previous conversion are maintained in the output shift register.
Reference disable. REFD high shuts down the internal reference. The external reference is
required for conversions.
I
VANA
VDIG
27
28
ADC core supply. Nominally +5 V. Decouple with 0.1-µF ceramic and 10-µF tantalum capacitors.
I/O supply. Nominally +1.8 V.
6
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8517
ADS8517
www.ti.com ................................................................................................................................................. SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009
TYPICAL CHARACTERISTICS
At fS = 200 kHz, VDIG = VANA = 5 V, and using internal reference (see Figure 39), unless otherwise specified.
POWER-SUPPLY CURRENT
vs FREE-AIR TEMPERATURE
INTERNAL REFERENCE VOLTAGE
vs FREE-AIR TEMPERATURE
10.0
9.5
9.0
8.5
8.0
2.520
2.515
2.510
2.505
2.500
2.495
2.490
2.485
2.480
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Figure 1.
Figure 2.
POWER-SUPPLY CURRENT
vs SAMPLING FREQUENCY
BIPOLAR OFFSET ERROR
vs FREE-AIR TEMPERATURE
10.0
9.5
9.0
8.5
8.0
2
1
Bipolar ±10 V Range
0
-1
-2
50
100
150
200
-50
-25
0
25
50
75
100
125
Sampling Frequency (kHz)
Temperature (°C)
Figure 3.
Figure 4.
BIPOLAR POSITIVE FULL-SCALE ERROR
vs FREE-AIR TEMPERATURE
BIPOLAR NEGATIVE FULL-SCALE ERROR
vs FREE-AIR TEMPERATURE
0.10
0.05
0
0
-0.05
-0.10
Bipolar 10 V Range
Bipolar 10 V Range
-40
-50
0
25
50
75
100
125
-50
-45
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Figure 5.
Figure 6.
Copyright © 2008–2009, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Link(s): ADS8517
ADS8517
SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009................................................................................................................................................. www.ti.com
TYPICAL CHARACTERISTICS (continued)
At fS = 200 kHz, VDIG = VANA = 5 V, and using internal reference (see Figure 39), unless otherwise specified.
UNIPOLAR OFFSET ERROR
vs FREE-AIR TEMPERATURE
UNIPOLAR OFFSET ERROR
vs FREE-AIR TEMPERATURE
0.2
0.1
0.2
0.1
Unipolar 4 V Range
Unipolar 5 V Range
0
0
-0.1
-0.2
-0.1
-0.2
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Figure 7.
Figure 8.
UNIPOLAR FULL-SCALE ERROR
vs FREE-AIR TEMPERATURE
UNIPOLAR FULL-SCALE ERROR
vs FREE-AIR TEMPERATURE
0.10
0.05
0
0.10
0.05
0
Unipolar 4 V Range
Unipolar 5 V Range
-0.05
-0.10
-0.05
-0.10
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Figure 9.
Figure 10.
AC PARAMETERS
vs FREE-AIR TEMPERATURE
SIGNAL-TO-(NOISE+DISTORTION)
vs FREE-AIR TEMPERATURE
110
-80
89.5
89.0
88.5
88.0
87.5
fIN = 10 kHz, 0 dB
fIN = 10 kHz, 0 dB
fS = 150 kHz
105
100
95
-85
SFDR
-90
fS = 200 kHz
-95
THD
SNR
fS = 50 kHz
fS = 100 kHz
90
-100
-105
-110
SINAD
85
80
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Figure 11.
Figure 12.
8
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8517
ADS8517
www.ti.com ................................................................................................................................................. SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009
TYPICAL CHARACTERISTICS (continued)
At fS = 200 kHz, VDIG = VANA = 5 V, and using internal reference (see Figure 39), unless otherwise specified.
SIGNAL-TO-(NOISE+DISTORTION)
vs INPUT FREQUENCY AND INPUT AMPLITUDE
SIGNAL-TO-NOISE RATIO
vs INPUT FREQUENCY
100
90
80
70
60
50
40
30
20
10
100
0 dB
-20 dB
90
-60 dB
80
0
2
4
6
8
10
12
14
16
18 20
1
10
100
Input Signal Frequency (kHz)
Input Sampling Frequency (kHz)
Figure 13.
Figure 14.
SIGNAL-TO-(NOISE+DISTORTION)
vs INPUT FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE
vs INPUT FREQUENCY
100
110
100
90
90
80
80
70
1
10
100
1
10
100
Input Sampling Frequency (kHz)
Input Sampling Frequency (kHz)
Figure 15.
Figure 16.
TOTAL HARMONIC DISTORTION
vs INPUT FREQUENCY
AC PARAMETERS
vs CAP PIN CAPACITOR ESR
-70
-80
110
105
100
95
-80
fIN = 10 kHz, 0 dB
-85
SFDR
-90
-90
-95
THD
-100
-110
-120
90
-100
-105
-110
SNR
SINAD
85
80
1
10
100
0
1
2
3
4
5
6
7
8
9
10
Input Sampling Frequency (kHz)
ESR (W)
Figure 17.
Figure 18.
Copyright © 2008–2009, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Link(s): ADS8517
ADS8517
SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009................................................................................................................................................. www.ti.com
TYPICAL CHARACTERISTICS (continued)
At fS = 200 kHz, VDIG = VANA = 5 V, and using internal reference (see Figure 39), unless otherwise specified.
AC PARAMETERS
vs POWER-SUPPLY VOLTAGE
OUTPUT REJECTION
vs POWER-SUPPLY RIPPLE FREQUENCY
110
105
100
95
-70
-20
-30
-40
-50
-60
-70
-80
fIN = 10 kHz, 0 dB
-75
SFDR
-80
-85
SNR
90
-90
SINAD
85
-95
THD
80
-100
-105
-110
75
70
4.00
4.25
4.50
4.75
5.00
5.25
5.50
10
100
1k
10k
100k
1M
Power-Supply Voltage (V)
Power-Supply Ripple Frequency (Hz)
Figure 19.
Figure 20.
INTEGRAL LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs POWER-SUPPLY VOLTAGE
CONVERSION TIME
vs FREE-AIR TEMPERATURE
2.40
2.35
2.30
2.25
2.20
2.0
1.5
1.0
INL Max
0.5
DNL Max
DNL Min
0
-0.5
-1.0
-1.5
-2.0
INL Min
-50
-25
0
25
50
75
100
125
4.00
4.25
4.50
4.75
5.00
5.25
5.50
Temperature (°C)
Power-Supply Voltage (V)
Figure 21.
Figure 22.
INTEGRAL LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
3
2
3
2
1
1
0
0
-1
-2
-3
-1
-2
-3
All Codes INL
All Codes DNL
0
8192 16384 24576 32768 40960 49152 57344 65535
0
8192 16384 24576 32768 40960 49152 57344 65535
Code
Code
Figure 23.
Figure 24.
10
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8517
ADS8517
www.ti.com ................................................................................................................................................. SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009
TYPICAL CHARACTERISTICS (continued)
At fS = 200 kHz, VDIG = VANA = 5 V, and using internal reference (see Figure 39), unless otherwise specified.
FFT
FFT
0
-10
0
-10
4096 Point FFT
fIN = 1 kHz, 0 dB
4096 Point FFT
fIN = 10 kHz, 0 dB
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-130
-100
-110
-120
-130
0
25
50
75
100
0
25
50
75
100
Frequency (kHz)
Frequency (kHz)
Figure 25.
Figure 26.
FFT
0
4096 Point FFT
-10
-20
fIN = 20 kHz, 0 dB
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
0
25
50
75
100
Frequency (kHz)
Figure 27.
Copyright © 2008–2009, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Link(s): ADS8517
ADS8517
SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009................................................................................................................................................. www.ti.com
BASIC OPERATION
PARALLEL OUTPUT
Figure 28 shows a basic circuit for operating the ADS8517 with a ±10-V input range and parallel output. Taking
R/C (pin 22) low for a minimum of 40 ns (5 µs max) initiates a conversion. BUSY (pin 24) goes low and stays low
until the conversion completes and the output register updates. If BYTE (pin 21) is low, the eight most significant
bits (MSBs) will be valid when BUSY rises; if BYTE is high, the eight least significant bits (LSBs) will be valid
when BUSY rises. Data are output in binary twos complement (BTC) format. BUSY going high can be used to
latch the data. After the first byte has been read, BYTE can be toggled, allowing the remaining byte to be read.
All convert commands are ignored while BUSY is low.
The ADS8517 begins tracking the input signal at the end of the conversion. Allowing 5 µs between convert
commands assures accurate acquisition of a new signal.
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
±10 V
+1.8 V
0.1 mF
+5 V
10 mF
+
+
3
0.1 mF
4
5
BUSY
+
2.2 mF
2.2 mF
Convert Pulse
40 ns min
6
7
R/C
ADS8517
8
+5 V
BYTE
9
NC(1)
10
11
12
13
14
Pin 21
LOW
B15 B14 B13 B12 B11
(MSB)
B10 B9 B8
Pin 21
HIGH
B7 B6 B5 B4 B3
B2 B1 B0
(LSB)
NOTE: (1) NC = not connected.
Figure 28. Basic ±10-V Operation, Both Parallel and Serial Output
12
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8517
ADS8517
www.ti.com ................................................................................................................................................. SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009
SERIAL OUTPUT
Figure 29 shows a basic circuit to operate the ADS8517 with a ±10-V input range and serial output. Taking R/C
(pin 22) low for 40 ns (5 µs max) initiates a conversion and outputs valid data from the previous conversion on
SDATA (pin 19) synchronized to 16 clock pulses output on DATACLK (pin 18). BUSY (pin 24) goes low and
stays low until the conversion completes and the serial data have been transmitted. Data are output in BTC
format, MSB first, and are valid on both the rising and falling edges of the data clock. BUSY going high can be
used to latch the data. All convert commands are ignored while BUSY is low.
The ADS8517 begins tracking the input signal at the end of the conversion. Allowing 5 µs between convert
commands assures accurate acquisition of a new signal.
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+1.8 V
0.1 mF
±10 V
+5 V
10 mF
+
+
3
0.1 mF
4
5
BUSY
R/C
+
+
22 mF
2.2 mF
Convert Pulse
40 ns min
6
7
ADS8517
8
NC(1)
NC(1)
NC(1)
9
SDATA
10
11
12
13
14
DATACLK
NC(1)
NC(1)
NC(1)
NC(1)
NC(1)
NOTE: (1) NC = not connected.
Figure 29. Basic ±10-V Operation with Serial Output
Copyright © 2008–2009, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Link(s): ADS8517
ADS8517
SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009................................................................................................................................................. www.ti.com
STARTING A CONVERSION
The combination of CS (pin 23) and R/C (pin 22) held low for a minimum of 40 ns puts the sample-and-hold of
the ADS8517 in the hold state and starts conversion N. BUSY (pin 24) goes low and stays low until conversion N
completes and the internal output register has been updated. All new convert commands received while BUSY is
low are ignored.
The ADS8517 begins tracking the input signal at the end of the conversion. Allowing 5 µs between convert
commands assures accurate acquisition of a new signal. Refer to Table 2 and Table 3 for a summary of CS,
R/C, and BUSY states, and Figure 30 through Figure 36 for timing diagrams.
Table 2. Control Functions When Using Parallel Output (DATACLK Tied Low, EXT/INT Tied High)
CS
1
R/C
X
0
BUSY
OPERATION
X
1
1
↑
None. Data bus is in High-Z state.
↓
Initiates conversion N. Data bus remains in High-Z state.
0
↓
Initiates conversion N. Data bus enters High-Z state.
0
1
Conversion N completed. Valid data from conversion N on the data bus.
↓
1
1
0
0
↑
Enables data bus with valid data from conversion N.
↓
1
Enables data bus with valid data from conversion N–1(1). Conversion N in progress.
Enables data bus with valid data from conversion N–1(1). Conversion N in progress.
0
↑
0
0
New conversion initiated without acquisition of a new signal. Data are invalid. CS and/or R/C
must be high when BUSY goes high.
X
X
0
New convert commands ignored. Conversion N in progress.
(1) See Figure 30 and Figure 31 for constraints on data valid from conversion N–1.
CS and R/C are internally ORed and level-triggered. It does not matter which input goes low first when initiating a
conversion. If, however, it is critical that CS or R/C initiates conversion N, be sure the less critical input is low at
least tsu2 ≥ 10 ns before the initiating input. If EXT/INT (pin 8) is low when initiating conversion N, serial data from
conversion N–1 is output on SDATA (pin 19) following the start of conversion N. See Internal Data Clock in the
Reading Data section for more information.
To reduce the number of control pins, CS can be tied low using R/C to control the read and convert modes. This
configuration has no effect when using the internal data clock in the serial output mode. However, when using an
active external data clock, the parallel and serial outputs are affected whenever R/C goes high; refer to the
Reading Data section for more information. In the internal clock mode, data are clocked out every convert cycle
regardless of the states of CS and R/C. The conversion result is available as soon as BUSY returns to high.
Therefore, data always represent the previously-completed conversion, even when read during a conversion.
14
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8517
ADS8517
www.ti.com ................................................................................................................................................. SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009
READING DATA
The ADS8517 outputs serial or parallel data in straight binary (SB) or binary twos complement data output
format. If SB/BTC (pin 7) is high, the output is in SB format; if it is low, the output is in BTC format. Refer to
Table 4 for the ideal output codes. The first conversion immediately following a power-up does not produce a
valid conversion result.
The parallel output can be read without affecting the internal output registers; however, reading the data through
the serial port shifts the internal output registers one bit per data clock pulse. As a result, data can be read on the
parallel port before reading the same data on the serial port, but data cannot be read through the serial port
before reading the same data on the parallel port.
Table 3. Control Functions When Using Serial Output(1)
CS
↓
R/C
0
BUSY EXT/INT DATACLK
OPERATION
1
1
1
1
1
0
0
1
1
1
Output
Output
Input
Initiates conversion N. Valid data from conversion N–1 clocked out on SDATA.
Initiates conversion N. Valid data from conversion N–1 clocked out on SDATA.
Initiates conversion N. Internal clock still runs conversion process.
Initiates conversion N. Internal clock still runs conversion process.
0
↓
↓
0
0
↓
↓
1
Input
Input
Input
Input
X
Conversion N completed. Valid data from conversion N clocked out on SDATA
synchronized to external data clock.
↓
0
0
X
1
↑
0
0
↑
0
1
1
Valid data from conversion N–1 output on SDATA synchronized to external data clock.
Conversion N in progress.
Valid data from conversion N–1 output on SDATA synchronized to external data clock.
Conversion N in progress.
0
X
X
X
New conversion initiated without acquisition of a new signal. Data are invalid. CS and/or
R/C must be high when BUSY goes high.
New convert commands ignored. Conversion N in progress..
(1) See Figure 34, Figure 35, and Figure 36 for constraints on data valid from conversion N–1.
Table 4. Output Codes and Ideal Input Voltages
DIGITAL OUTPUT
BINARY TWOS COMPLEMENT
(SB/BTC LOW)
STRAIGHT BINARY (SB/BTC HIGH)
DESCRIPTION
Full-scale range
ANALOG INPUT
0 V to 5 V
76 µV
±10
305 µV
9.999695 V
0 V
0 V to 4 V
HEX
Least significant bit (LSB)
+Full-scale (FS – 1LSB)
Midscale
61 µV
BINARY CODE
CODE
7FFF
0000
FFFF
8000
BINARY CODE
HEX CODE
FFFF
4.999924 V 3.999939 V
2.5 V 2 V
2.499924 V 1.999939 V
0 V 0 V
0111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
1000 0000 0000 0000
1111 1111 1111 1111
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
8000
1 LSB below midscale
–Full-scale
305 µV
-10 V
7FFF
0000
Parallel Output
To use the parallel output, tie EXT/INT (pin 8) high and DATACLK (pin 18) low. SDATA (pin 19) should be left
unconnected. The parallel output is active when R/C (pin 22) is high and CS (pin 23) is low. Any other
combination of CS and R/C 3-states the parallel output. Valid conversion data can be read in two 8-bit bytes on
D7-D0 (pins 9-13 and 15-17). When BYTE (pin 21) is low, the eight most significant bits are valid with the MSB
on D7. When BYTE is high, the eight least significant bits are valid with the LSB on D0. BYTE can be toggled to
read both bytes within one conversion cycle.
Upon initial device power-up, the parallel output contains indeterminate data.
Copyright © 2008–2009, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Link(s): ADS8517
ADS8517
SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009................................................................................................................................................. www.ti.com
Parallel Output (After a Conversion)
After conversion N is completed and the output registers have been updated, BUSY (pin 24) goes high. Valid
data from conversion N are available on D7-D0 (pin 9-13 and 15-17). BUSY going high can be used to latch the
data. Refer to Table 5, Figure 30, and Figure 31 for timing specifications.
t
1
t
1
R/C
t
3
t
3
t
4
BUSY
t
6
t
5
t
6
t
7
t
8
Acquire
Convert
Acquire
Convert
MODE
t
12
t
12
t
10
t
11
Parallel
Data Bus
Previous
High Byte Valid
Previous High Previous Low
High Byte
Valid
Low Byte
Valid
High Byte
Valid
Hi-Z
Not Valid
Hi-Z
Byte Valid
Byte Valid
t
2
t
9
t
12
t
12
t
12
t
9
t
12
BYTE
Figure 30. Conversion Timing With Parallel Output (CS and DATACLK Tied Low, EXT/INT Tied High)
t
21
t
21
t
21
t
21
t
1
R/C
CS
t
21
t
21
t
3
t
4
BUSY
t
21
t
21
BYTE
t
21
t
21
Data Bus
Hi-Z State
High Byte Hi-Z State Low Byte
Hi-Z State
t
21
t
21
t
9
t
9
Figure 31. CS to Control Conversion and Read Timing With Parallel Outputs
16
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8517
ADS8517
www.ti.com ................................................................................................................................................. SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009
Parallel Output (During a Conversion)
After conversion N has been initiated, valid data from conversion N–1 can be read and are valid up to 2.2 µs
after the start of conversion N. Do not attempt to read data beyond 2.2 µs after the start of conversion N until
BUSY (pin 24) goes high; doing so may result in reading invalid data. Refer to Table 5, Figure 30, and Figure 31
for timing constraints.
Table 5. Conversion and Data Timing with Parallel Interface at TA = –40°C to +85°C
SYMBOL
DESCRIPTION
MIN
TYP
MAX
5
UNITS
µs
t1
t2
Convert pulse width
0.04
Data valid delay after R/C low
2.3
20
2.5
85
µs
t3
BUSY delay from start of conversion
BUSY low
ns
t4
2.3
90
2.5
µs
t5
BUSY delay after end of conversion
Aperture delay
ns
t6
40
ns
t7
Conversion time
1.8
2.2
2.7
µs
t8
Acquisition time
µs
t9
Bus relinquish time
10
20
1.8
10
83
5
ns
t10
t11
t21
t7 + t8
BUSY delay after data valid
Previous data valid after start of conversion
R/C to CS setup time
Throughput time
60
ns
2.2
µs
ns
µs
Serial Output
Data can be clocked out with the internal data clock or an external data clock. When using the serial output, be
careful with the parallel outputs, D7-D0 (pins 9-13 and 15-17), because these pins come out of a High-Z state
whenever CS (pin 23) is low and R/C (pin 22) is high. The serial output cannot be 3-stated and is always active.
Refer to the Applications Information section for specific serial interfaces. If an external clock is used, the TAG
input can be used to daisy-chain multiple ADS8517 data pins together.
Internal Data Clock (During a Conversion)
To use the internal data clock, tie EXT/INT (pin 8) low. The combination of R/C (pin 22) and CS (pin 23) low
initiates conversion N and activates the internal data clock (typically, a 900-kHz clock rate). The ADS8517
outputs 16 bits of valid data, MSB first, from conversion N–1 on SDATA (pin 19), synchronized to 16 clock pulses
output on DATACLK (pin 18). The data are valid on both the rising and falling edges of the internal data clock.
The rising edge of BUSY (pin 24) can be used to latch the data. After the 16th clock pulse, DATACLK remains
low until the next conversion is initiated, while SDATA returns to the state of the TAG pin input sensed at the
start of transmission. Refer to Table 6 and Figure 33 for more information.
Copyright © 2008–2009, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Link(s): ADS8517
ADS8517
SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009................................................................................................................................................. www.ti.com
External Data Clock
To use an external data clock, tie EXT/INT (pin 8) high. The external data clock is not and cannot be
synchronized with the internal conversion clock; care must be taken to avoid corrupting the data. To enable the
output mode of the ADS8517, CS (pin 23) must be low and R/C (pin 22) must be high. DATACLK must be high
for 20% to 70% of the total data clock period; the clock rate can be between dc and 10 MHz. Serial data from
conversion N can be output on SDATA (pin 19) after conversion N completes or during conversion N+1.
An obvious way to simplify control of the converter is to tie CS low and use R/C to initiate conversions.
While this configuration is perfectly acceptable, there is a possible problem when using an external data clock. At
an indeterminate point from 12 µs after the start of conversion N until BUSY rises, the internal logic shifts the
results of conversion N into the output register. If CS is low, R/C high, and the external clock is high at this point,
data are lost. Consequently, with CS low, either R/C and/or DATACLK must be low during this period to avoid
losing valid data.
External Data Clock (After a Conversion)
After conversion N is completed and the output registers have been updated, BUSY (pin 24) goes high. With CS
low and R/C high, valid data from conversion N are output on SDATA (pin 19) synchronized to the external data
clock input on DATACLK (pin 18). The MSB is valid on the first falling edge and the second rising edge of the
external data clock. The LSB is valid on the 16th falling edge and 17th rising edge of the data clock. TAG (pin
20) inputs a bit of data for every external clock pulse. The first bit input on TAG is valid on SDATA on the 17th
falling edge and the 18th rising edge of DATACLK; the second input bit is valid on the 18th falling edge and the
19th rising edge, etc. With a continuous data clock, TAG data is output on SDATA until the internal output
registers are updated with the results from the next conversion. Refer to Table 6 and Figure 35 for more
information.
External Data Clock (During a Conversion)
After conversion N has been initiated, valid data from conversion N–1 can be read and are valid up to 2.2 µs
after the start of conversion N. Do not attempt to clock out data from 2.2 µs after the start of conversion N until
BUSY (pin 24) rises; doing so results in data loss.
NOTE:
For the best possible performance when using an external data clock, data should not
be clocked out during a conversion.
The switching noise of the asynchronous data clock can cause digital feedthrough, degrading converter
performance. Refer to Table 6 and Figure 36 for more information.
18
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8517
ADS8517
www.ti.com ................................................................................................................................................. SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009
Table 6. Timing Requirements (TA = –40°C to +85°C)
PARAMETER
MIN
TYP
MAX
5
UNIT
µs
ns
µs
ns
ns
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
tw1
td1
tw2
td2
Pulse duration, convert
0.04
Delay time, BUSY from R/C low
Pulse duration, BUSY low
20
2.3
90
85
2.5
Delay time, BUSY, after end of conversion
Delay time, aperture
td3
40
tconv
tacq
Conversion time
2.0
2.6
2.2
2.7
2.4
5
Acquisition time
tconv + tacq Cycle time
td4
tc1
Delay time, R/C low to internal DATACLK output
171
96
Cycle time, internal DATACLK
92
2
98
td5
Delay time, data valid to internal DATACLK high
Delay time, data valid after internal DATACLK low
Cycle time, external DATACLK
3.5
43
td6
41
35
15
15
15
10
2
tc2
tw3
tw4
tsu1
tsu2
td8
Pulse duration, external DATACLK high
Pulse duration, external DATACLK low
Setup time, R/C rise/fall to external DATACLK high
Setup time, R/C transition to CS transition
Delay time, data valid from external DATCLK high
Delay time, CS rising edge to external DATACLK rising edge
Delay time, previous data available after CS, R/C low
Setup time, BUSY transition to first external DATACLK
Delay time, final external DATACLK to BUSY rising edge
Setup time, TAG valid before rising edge of DATACLK
Hold time, TAG valid after rising edge of DATACLK
25
40
td9
15
1.8
5
td10
tsu3
td11
tsu4
th1
2.2
825
2
2
R/C
CS
CS
t
d9
R/C
t
t
su1
t
t
su1
su1
su1
External
DATACLK
External
DATACLK
CS Set Low, Discontinuous Ext DATACLK
CS
R/C Set Low, Discontinuous Ext DATACLK
BUSY
t
t
su2
su2
t
su3
1
2
External
DATACLK
R/C
CS Set Low, Discontinuous Ext DATACLK
Figure 32. Critical Timing Parameters
Copyright © 2008–2009, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Link(s): ADS8517
ADS8517
SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009................................................................................................................................................. www.ti.com
t
t
w1
w1
R/C
t
t
d1
t
d1
t
w2
w2
(N + 1)th
(N + 2)th
BUSY
t
d2
t
t
d2
t
t
d3
t
d3
d11
d11
Error
Correction
Error
Correction
(N+1)th Accquisition
(N+2)th Accquisition
Nth Conversion
STATUS
(N+1)th Conversion
t
t
t
t
conv
conv
acq
acq
t
t
c1
t
d4
d4
Internal
1
2
16
D0
2
16
D0
1
DATACLK
t
d6
t
d5
TAG = 0
D15
D15
SDATA
TAG = 0
TAG = 0
Nth Conversion Data
(N−1)th Conversion Data
CS, EXT/INT, and TAG are tied low
8 starts READ
Figure 33. Basic Conversion Timing: Internal DATACLK (Read Previous Data During Conversion)
t
t
w1
w1
R/C
t
t
d1
d1
t
t
w2
w2
BUSY
(N + 1)th
(N + 2)th
t
t
d2
d2
t
t
d3
d3
t
t
d11
d11
Error
Correction
Error
Correction
STATUS
Nth Conversion
(N+1)th Accquisition
(N+1)th Conversion
(N+2)th Accquisition
t
t
t
t
acq
acq
conv
conv
t
t
t
su3
su3
su1
t
su1
External
1
1
16
2
16
2
1
16
1
16
DATACLK
No more
data to
shift out
No more
data to
shift out
TAG = 0
TAG = 0
Nth Data
TAG = 0
(N+1)th Data
TAG = 0
SDATA
TAG = 0
EXT/INT tied high, CS and TAG are tied low
t
+ t starts READ
su1
w1
Figure 34. Basic Conversion Timing: External DATACLK
20
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8517
ADS8517
www.ti.com ................................................................................................................................................. SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009
t
w1
R/C
t
su1
t
d1
t
d1
t
w2
BUSY
t
t
d2
t
d3
t
d3
d11
Error
Correction
(N+1) th Accquisition
Nth Conversion
STATUS
t
su3
t
t
conv
acq
t
t
su1
c2
t
w4
External
t
w3
DATACLK
0
1
2
3
4
5
10
11
12
13
14
15
16
SYNC = 0
DATA
Nth Conversion Data
D05 D04 D03 D02 D01 D00
t
t
d8
d8
D15
D14 D13 D12 D11 D10
T00
T17
Txx
Tyy
t
t
h1
su4
T02 T03
T01
T11 T12 T13 T14
T16
T00
T04 T05 T06
T15
TAG
EXT/INT tied high, CS tied low
t
+ t
starts READ
su1
w1
Figure 35. Read After Conversion (Discontinuous External DATACLK)
t
w1
R/C
t
d1
t
w2
BUSY
t
t
d2
t
d10
d3
Error
Correction
(N + 1)th Conversion
STATUS
t
su3
t
conv
t
c2
t
t
t
d11
w3
w4
t
su1
External
1
2
3
4
5
10
11
12
13
14
15
16
0
DATACLK
Nth Conversion Data
t
t
d8
d8
D05 D04 D03 D02 D01 D00
D15 D14 D13 D12 D11 D10
SDATA
Rising DATACLK change DATA, t + t
w1 su1
Starts READ
EXT/INT tied high, CS and TAG tied low
TAG is not recommended for this mode. There is not enough
time to do so without violating t
.
d11
Figure 36. Read During Conversion (Discontinuous External DATACLK)
Copyright © 2008–2009, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Link(s): ADS8517
ADS8517
SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009................................................................................................................................................. www.ti.com
TAG FEATURE
The TAG feature allows data from multiple ADS8517 converters to be read on a single serial line. The converters
are cascaded together using the DATA pins as outputs and the TAG pins as inputs, as illustrated in Figure 37.
The DATA pin of the last converter drives the processor serial data input. Data are then shifted through each
converter, synchronous to the externally supplied data clock, onto the serial data line. The internal clock cannot
be used for this configuration.
The preferred timing uses the discontinuous, external data clock during the sampling period. Data must be read
during the sampling period because there is not sufficient time to read data from multiple converters during a
conversion period without violating the td11 constraint (see the External Data Clock section). The sampling period
must be sufficiently long enough to allow all data words to be read before starting a new conversion.
Note that in Figure 37, the state of the DATA pin at the end of a READ cycle reflects the state of the TAG pin at
the start of the cycle for each converter. The ADS8517 works the same way when it is running in external or
internal clock mode. That is, the state of the TAG pin is shown on the DATA pin at the 17th clock after all 16 bits
have shifted out. However, it is only practical to use the TAG feature with the external clock mode when multiple
ADS8517s are daisy-chained, so that they are running at the same clock speed. For example, when two
converters (ADS8517A and ADS8517B) are cascaded together, the 17th external clock cycle brings the MSB
data of ADS8517A onto the DATA pin of ADS8517B.
ADS8517A
ADS8517B
Processor
DATA (A)
TAG DATA
CS
TAG DATA
A00
B00
A15
B15
D
D
Q
Q
D
D
Q
Q
CS
R/C
R/C
DATACLK
DATACLK
SCLK
GPIO
GPIO
SDI
DATA (B)
TAG (B)
DATACLK
R/C
(both A and B)
BUSY
(both A and B)
SYNC
(both A and B)
External
DATACLK
1
2
3
4
15
16
18
19
20
21
32
33
34
17
DATA (A)
DATA (B)
A15 A14 A13
B15 B14 B13
A01 A00
TAG(A) = 0
Nth Conversion Data
B01
B00 A15 A14 A13 A12
A00
TAG(A) = 0
EXT/INT tied high, CS of both converter A and B, TAG input of converter A are tied low.
Figure 37. Timing of TAG Feature With Single Conversion (Using External DATACLK)
22
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8517
ADS8517
www.ti.com ................................................................................................................................................. SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009
ANALOG INPUTS
The ADS8517 offers three analog input ranges, as shown in Table 1. The offset specification is factory-calibrated
with internal resistors. The gain specification is factory-calibrated with 0.1%, 0.25-W external resistors, as shown
in Figure 38 and Figure 39. The external resistors can be omitted if a larger gain error is acceptable or if using
software calibration. The hardware trim circuitry shown in Figure 38 and Figure 39 can reduce the error to zero.
±10 V
0 V to 5 V
0 V to 4 V
1
2
1
2
3
4
5
6
1
2
3
4
5
6
R1
R1
VIN
IN
IN
R1
IN
VIN
AGND1
AGND1
AGND1
3
4
R2
IN
R2
IN
VIN
R2
IN
+5 V
+5 V
+
+
+5 V
CAP
CAP
CAP
+
+
2.2 mF
2.2 mF
2.2 mF
2.2 mF
1 MW
1 MW
1 MW
5
6
50 kW
50 kW
50 kW
REF
REF
REF
+
+
2.2 mF
2.2 mF
AGND2
AGND2
AGND2
Figure 38. Circuit Diagrams (with Gain Adjust Trim)
±10 V
0 V to 5 V
0 V to 4 V
1
2
1
1
2
3
4
5
6
R1
R1
VIN
IN
IN
R1
IN
2
3
4
5
6
VIN
AGND1
AGND1
AGND1
3
4
R2
IN
R2
IN
VIN
R2
IN
+
+
+
CAP
CAP
CAP
+
+
2.2 mF
2.2 mF
2.2 mF
2.2 mF
1 MW
5
6
REF
REF
REF
+
2.2 mF
2.2 mF
AGND2
AGND2
AGND2
Figure 39. Circuit Diagrams (Without Gain Adjust Trim)
Copyright © 2008–2009, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Link(s): ADS8517
ADS8517
SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009................................................................................................................................................. www.ti.com
Analog input pins R1IN and R2IN have ±25-V overvoltage protection. The input signal must be referenced to
AGND1. This referencing minimizes ground-loop problems typical to analog designs. The analog input should be
driven by a low-impedance source. A typical driving circuit using the OPA627 or OPA132 is shown in Figure 40.
+15 V
22 pF
2.2 mF
ADS8517
R1IN
2 kW
100 nF
Pin 7
Pin 1
AGND1
R2IN
2 kW
Pin 2
Pin 3
VIN
OPA627
or
OPA132
Pin 6
22 pF
CAP
REF
Pin 4
EXT/INT
DGND
2.2 mF
2.2 mF
2.2 mF
100 nF
AGND2
-15 V
GND
GND
GND
GND
GND
GND
Figure 40. Typical Driving Circuit (±10 V, No Trim)
24
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8517
ADS8517
www.ti.com ................................................................................................................................................. SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009
REFERENCE
The ADS8517 can operate with the internal 2.5 V reference or an external reference. An external reference
connected to pin 5 (REF) bypasses the internal reference. The external reference must drive the 6-kΩ resistor
that separates pin 5 from the internal reference (see the front page diagram). The load varies with the difference
between the internal and external reference voltages. The internal reference is approximately 2.5 V (range is
from 2.48 V to 2.52 V). The external reference voltage can vary from 2.3 V to 2.7 V. The reference, whether
internal or external, is buffered internally with the output on pin 4 (CAP). Figure 41 shows characteristic
impedances at the input and output of the buffer with all combinations of power-down and reference power-down.
The reference voltage determines the size of the least significant bit (LSB). The larger reference voltages
produce a larger LSB, which can improve SNR. Smaller reference voltages can degrade SNR.
Z
CAP
CAP
CDAC
(Pin 4)
Buffer
Z
REF
Internal
REF
Reference
(Pin 5)
PWRD 0
REFD 0
1
PWRD 0
REFD 1
1
PWRD 1
REFD 0
200
PWRD 1
REFD 1
200
Z
W
W
CAP
Z
6 k
1 M
6 k
1 M
REF
Figure 41. Characteristic Impedances of the Internal Buffer
The ADS8517 is factory-tested with 2.2 µF capacitors connected to pin 4 (CAP) and pin 5 (REF). Each capacitor
should be placed as close as possible to the pin. The capacitor on pin 5 band-limits the internal reference noise.
A smaller capacitor can be used, but it may degrade SNR and SINAD. The capacitor on pin 4 stabilizes the
reference buffer and provides switching charge to the CDAC during conversion. Capacitors smaller than 1 µF
may cause the buffer to become unstable and not hold sufficient charge for the CDAC. The devices are tested to
specifications with 2.2 µF, making larger capacitors unnecessary (Figure 42 shows how capacitor values larger
than 2.2 µF have little effect on improving performance). The equivalent series resistance (ESR) of these
compensation capacitors is also critical; keep the total ESR under 3 Ω. See the Typical Characteristics section
concerning how ESR affects performance.
7000
6000
5000
4000
3000
2000
1000
0
0.1
1
10
100
CAP − Pin Value − mF
Figure 42. Power-Down to Power-Up Time versus Capacitor Value on CAP
Neither the internal reference nor the buffer should be used to drive an external load. Such loading can degrade
performance, as shown in Figure 41. Any load on the internal reference causes a voltage drop across the 6-kΩ
resistor and affects gain. The internal buffer is capable of driving ±2-mA loads, but any load can cause
perturbations of the reference at the CDAC, thus degrading performance.
Copyright © 2008–2009, Texas Instruments Incorporated
Submit Documentation Feedback
25
Product Folder Link(s): ADS8517
ADS8517
SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009................................................................................................................................................. www.ti.com
POWER-DOWN
The ADS8517 has analog power-down and reference power-down capabilities via PWRD (pin 25) and REFD (pin
26), respectively. PWRD and REFD high powers down all analog circuitry, maintaining data from the previous
conversion in the internal registers, provided that the data have not already been shifted out through the serial
port. Typical power consumption in this mode is 50 µW. Power recovery is typically 1 ms, using a 2.2-µF
capacitor connected to CAP. Figure 42 shows power-down to power-up recovery time relative to the capacitor
value on CAP. With +5 V applied to VDIG, the digital circuitry of the ADS8517 remains active at all times,
regardless of PWRD and REFD states.
PWRD
PWRD high powers down all of the analog circuitry except for the reference. Data from the previous conversion
are maintained in the internal registers and can still be read. With PWRD high, a convert command yields
meaningless data.
REFD
REFD high powers down the internal 2.5-V reference. All other analog circuitry, including the reference buffer, is
active. REFD should be high when using an external reference to minimize power consumption and the loading
effects on the external reference. See Figure 41 for the characteristic impedance of the reference buffer input for
both REFD high and low. The internal reference consumes approximately 5 mW.
26
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8517
ADS8517
www.ti.com ................................................................................................................................................. SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009
LAYOUT
POWER
For host processors that are able to advantage of a lower interface supply voltage, the ADS8517 offers a wide
range of voltages—from 5.5V to as low as 1.65V. The ADS8517 should be considered as an analog component
because, as noted in the Electrical Characteristics, it uses 95% of its power for the analog circuitry. If the
interface is at the same +5V as the analog supply, the two +5-V supplies should be separate. Connecting VDIG
(pin 28) directly to a digital supply can reduce converter performance because of switching noise from the digital
logic. For best performance, the +5-V supply should be produced from whichever analog supply is present for the
rest of the analog signal conditioning. If a +12-V or +15-V suppy is present in the system, a simple +5-V regulator
can be used. Although it is not suggested, if the digital supply in the system must be used to power the
converter, be sure it is properly filtered.
POWER-ON SEQUENCE
Care must be taken with power sequencing when the interface and analog supplies are different. Refer to the
Absolute Maximum Ratings for details. The analog supply should be powered on before the digital supply (used
for the interface). It is important that the voltage difference between VDIG and the digital inputs does not exceed
the limit of –0.3V to VDIG + 0.3V. All digital inputs should be kept inactive (logic low) until the digital (interface)
supply is steady.
GROUNDING
Three ground pins are present on the ADS8517. DGND is the digital supply ground. AGND2 is the analog supply
ground. AGND1 is the ground to which all analog signals internal to the A/D converter are referenced. AGND1 is
more susceptible to current induced voltage drops and must have the path of least resistance back to the power
supply.
To achieve optimum performance, all the ground pins of the A/D converter should be tied to an analog ground
plane, separated from the system digital logic ground. Both analog and digital ground planes should be tied to
the system ground as near to the power supplies as possible. This configuration helps to prevent dynamic digital
ground currents from modulating the analog ground through a common impedance to power ground.
SIGNAL CONDITIONING
The ADS8517 features high-impedance inputs as the result of the resistive input attenuation circuit. For ±10V, 0V
to 5V, and 0V to 4V inputs, the equivalent input impedances are 45.7kΩ, 20kΩ and 21.4kΩ respectively. Lower
cost op amps may be used to drive the ADC inputs because the driving requirement is not as high compared to
other converters. This input circuit not only reduces the power consumption on the signal conditioning op amp,
but it also works as a buffer to attenuate any charge injection resulting from the operation of the CDAC FET
sample switches, even though the design of those FET switches is optimized to give minimal charge injection.
Another benefit provided by the ADS8517 high-impedance front-end is assured ±25V overvoltage protection. In
most cases, this internal protection eliminates the need for external input protection circuitry.
INTERMEDIATE LATCHES
The ADS8517 does have 3-state outputs for the parallel port, but intermediate latches should be used if the bus
is active during conversion. If the bus is not active during conversion, the 3-state outputs can be used to isolate
the A/D converter from other peripherals on the same bus.
Intermediate latches are beneficial on any monolithic A/D converter. The ADS8517 has an internal LSB size of
38 µV (with a 2.5-V internal reference). Transients from fast-switching signals on the parallel port, even when the
A/D converter is 3-stated, can be coupled through the substrate to the analog circuitry, causing degradation of
converter performance.
Copyright © 2008–2009, Texas Instruments Incorporated
Submit Documentation Feedback
27
Product Folder Link(s): ADS8517
ADS8517
SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009................................................................................................................................................. www.ti.com
APPLICATION INFORMATION
TRANSITION NOISE
Apply a dc input to the ADS8517 and initiate 1000 conversions. The digital output of the converter varies in
output codes because of the internal noise of the ADS8517. This variance is true for all 16-bit SAR converters.
The transition noise specification found in the Electrical Characteristics section is a statistical figure that
represents the one sigma limit or rms value of these output codes.
Using a histogram to plot the output codes, the distribution should appear bell-shaped, with the peak of the bell
curve representing the nominal output code for the input voltage value. The ±1σ, ±2σ, and ±3σ distributions
represent 68.3%, 95.5%, and 99.7%, respectively, of all codes. Multiplying the transition noise (TN) by 6 yields
the ±3σ distribution, or 99.7%, of all codes. Statistically, up to three codes could fall outside the five-code
distribution when executing 1000 conversions. The ADS8517 has a TN of 0.8 LSBs, which yields five output
codes for a ±3σ distribution. Figure 43 shows 16,384 conversion histogram results.
7740
4230
3855
288
247
16
8
8003
7FFD 7FFE 7FFF
8000
8001
8002
Figure 43. Histogram of 16,384 Conversions with VIN = 0 V in ±10 V Bipolar Range
AVERAGING
The noise of the converter can be compensated by averaging the digital codes. By averaging conversion results,
transition noise is reduced by a factor of 1/√n where n is the number of averages. For example, averaging four
conversion results reduces the TN by 1/2 to 0.4 LSBs. Averaging should only be used for input signals with
frequencies near dc.
For ac signals, a digital filter can be used to low-pass filter and decimate the output codes. This action works in a
similar manner to averaging: for every decimation by 2, the signal-to-noise ratio improves by 3 dB.
28
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8517
ADS8517
www.ti.com ................................................................................................................................................. SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009
ADS8517 AS AN SPI MASTER DEVICE (INT/EXT TIED LOW)
Figure 44 shows a simple interface between the ADS8517 and an SPI-equipped microcontroller or TMS320
series digital signal processor (DSP) when using the internal serial data clock. This interface assumes that the
microcontroller or DSP is configured as an SPI slave, is capable of receiving 16-bit transfers, and that the
ADS8517 is the only serial peripheral on the SPI bus.
Microcontroller
ADS8517
TOUT
SS
R/C
BUSY
MOSI
SCLK
SDATA
DATACLK
EXT/INT
SPI Slave
CS
BYTE
SPI Master
NOTE: CPOL = 0 (inactive SCLK is LOW)
CPHA = 0 or 1 (data valid on either SCLK edge)
Figure 44. ADS8517 as SPI Master
To maintain synchronization with the ADS8517, the microcontroller slave select (SS) input should be connected
to the BUSY output of the ADS8517. When a transition from high-to-low occurs on BUSY (indicating the current
conversion is in process), the ADS8517 internal SCLK begins shifting the previous conversion data into the
MOSI pin of the microcontroller. In this scenario, the CONV input to the ADS8517 can be controlled from an
external trigger source, or a trigger generated by the microcontroller. The ADS8517 internal SCLK provides 2 ns
(min) of setup time and 41 ns (min) of hold time on the SDATA output (see td5 and td6 in Table 6), allowing the
microcontroller to sample data on either the rising or falling edge of SCLK.
Copyright © 2008–2009, Texas Instruments Incorporated
Submit Documentation Feedback
29
Product Folder Link(s): ADS8517
ADS8517
SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009................................................................................................................................................. www.ti.com
ADS8517 AS AN SPI SLAVE DEVICE (INT/EXT TIED HIGH)
Figure 45 shows another interface between the ADS8517 and an SPI-equipped microcontroller or DSP in which
the host processor acts as an SPI master device.
VS
Microcontroller
ADS8517
R/C EXT/INT
TOUT
INT
BUSY
MOSI
SCLK
SDATA
DATACLK
CS
SPI Master
BYTE
SPI Slave
NOTE: CPOL = 0 (inactive SCLK is LOW)
CPHA = 1 (data valid on SCLK falling edge)
Figure 45. ADS8517 as SPI Slave
In this configuration, the data transfer from the ADS8517 is triggered by the rising edge of the serial data clock
provided by the SPI master. The SPI interface should be configured to read valid SDATA on the falling edge of
SCLK. When a minimum of 17 SCLKs are provided to the ADS8517, data can be strobed to the host processor
on the rising SCLK edge providing a 2ns (min) hold time (see td8 in Table 6).
When using an external interrupt to facilitate serial data transfers, as shown in Figure 45, there are two options
for the configuration of the interrupt service routine (ISR): falling-edge-triggered or rising-edge-triggered.
A falling-edge-triggered transfer would initiate an SPI transfer after the falling edge of BUSY, providing the host
controller with the previous conversion results, while the current conversion cycle is underway. The timing for this
type of interface is described in detail in Figure 36. Care must be taken to ensure the entire 16-bit conversion
result is retrieved from the ADS8517 before BUSY returns high to avoid the potential corruption of the current
conversion cycle.
A rising-edge-triggered transfer is the preferred method of obtaining the conversion results. This timing is
depicted in Figure 35. This method of obtaining data ensures that SCLK is static during the conversion cycle and
provides the host processor with current cycle conversion results.
8-BIT SPI INTERFACE
For microcontrollers that only support 8-bit SPI transfers, it is recommended to configure the ADS8517 for SPI
slave operation, as depicted in Figure 45. With the microcontroller configured as the SPI master, two 8-bit
transfers are required to obtain full 16-bit conversion results from the ADS8517. The eight MSBs of the
conversion result are considered valid on the falling SCLK edges of the first transfer, with the remaining four
LSBs being valid on the first four falling SCLK edges in the second transfer.
30
Submit Documentation Feedback
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): ADS8517
ADS8517
www.ti.com ................................................................................................................................................. SLAS527A–SEPTEMBER 2008–REVISED JUNE 2009
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (September 2008) to Revision A ............................................................................................... Page
•
•
Changed data sheet to reflect TSSOP-28 package availability............................................................................................. 1
Deleted lead temperature specification from Absolute Maximum Ratings ............................................................................ 2
Copyright © 2008–2009, Texas Instruments Incorporated
Submit Documentation Feedback
31
Product Folder Link(s): ADS8517
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jun-2009
PACKAGING INFORMATION
Orderable Device
ADS8517IBDW
ADS8517IBDWG4
ADS8517IBDWR
ADS8517IBDWRG4
ADS8517IBPW
ADS8517IBPWR
ADS8517IDW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
DW
28
28
28
28
28
28
28
28
28
28
28
28
20 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOIC
SOIC
DW
DW
DW
PW
PW
DW
DW
DW
DW
PW
PW
20 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOIC
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TSSOP
TSSOP
SOIC
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
ADS8517IDWG4
ADS8517IDWR
ADS8517IDWRG4
ADS8517IPW
SOIC
20 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOIC
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOIC
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TSSOP
TSSOP
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
ADS8517IPWR
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jun-2009
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jun-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
ADS8517IBDWR
ADS8517IBPWR
ADS8517IDWR
ADS8517IPWR
SOIC
TSSOP
SOIC
DW
PW
DW
PW
28
28
28
28
1000
2000
1000
2000
330.0
330.0
330.0
330.0
32.4
16.4
32.4
16.4
11.35
6.9
18.67
10.2
3.1
1.8
3.1
1.8
16.0
12.0
16.0
12.0
32.0
16.0
32.0
16.0
Q1
Q1
Q1
Q1
11.35
6.9
18.67
10.2
TSSOP
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jun-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS8517IBDWR
ADS8517IBPWR
ADS8517IDWR
ADS8517IPWR
SOIC
TSSOP
SOIC
DW
PW
DW
PW
28
28
28
28
1000
2000
1000
2000
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
49.0
33.0
49.0
33.0
TSSOP
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Applications
Audio
Automotive
Broadband
Digital Control
Medical
Military
Optical Networking
Security
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
www.ti.com/audio
Data Converters
DLP® Products
DSP
Clocks and Timers
Interface
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
Logic
Power Mgmt
Microcontrollers
RFID
Telephony
Video & Imaging
Wireless
RF/IF and ZigBee® Solutions www.ti.com/lprf
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2009, Texas Instruments Incorporated
相关型号:
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明