ADS8665IPWR [TI]
具有可编程 (±12/±10/±6/±5/±2.5V) 输入范围、+5V 电源的 12 位、500kSPS、单通道 SAR ADC | PW | 16 | -40 to 125;
| 型号： | ADS8665IPWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有可编程 (±12/±10/±6/±5/±2.5V) 输入范围、+5V 电源的 12 位、500kSPS、单通道 SAR ADC | PW | 16 | -40 to 125 光电二极管 转换器 |
| 文件： | 总72页 (文件大小：2951K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS8661, ADS8665
ZHCSFU0B – DECEMBER 2016 – REVISED MARCH 2021
具有可编程双极输入范围的 ADS866x 12 位、高速、单电源、SAR ADC 数据采
集系统
1 特性
3 说明
•
•
具有集成模拟前端的 12 位 ADC
高速：
– ADS8661：1.25MSPS
– ADS8665：500kSPS
可通过软件编程的输入范围：
– 双极范围：±12.288V、±10.24V、±6.144V、
±5.12V 和 ±2.56V
ADS8661 和 ADS8665 属于基于逐次逼近型 (SAR) 模
数转换器 (ADC) 的集成数据采集系统系列。此类器件
采用高速高精度 SAR ADC、集成模拟前端 (AFE) 输入
驱动器电路、高达 ±20V 的过压保护电路以及一个温度
漂移极低的 4.096V 片上基准电压。
•
此类器件由 5V 模拟电源供电，但支持 ±12.288V、
±6.144V、±10.24V、±5.12V 和 ±2.56V 实际双极输入
范围，以及 0V 至 12.288V、0V 至 10.24V、0V 至
6.144V 和 0V 至 5.12V 的单极输入范围。各输入范围
的增益和偏移误差均可在特定数值范围内进行调节，确
保直流精度较高。通过针对器件内部寄存器进行编程可
选择输入范围。此类器件提供高阻性输入阻抗 (≥
1MΩ)，不受所选输入范围的影响。
– 单极范围：0V–12.288V、0V–10.24V、0V–
6.144V 以及 0V–5.12V
• 5V 模拟电源：1.65V 至 5V I/O 电源
•
恒定的阻性输入阻抗 ≥ 1MΩ
输入过压保护：高达 ±20V
•
• 4.096V 片上低漂移基准电压
•
出色的性能：
multiSPI 数字接口向后兼容传统 SPI 协议。此外，可
配置特性简化了与各种主机控制器的接口。
– DNL：±0.1LSB；INL：±0.15LSB
– SNR：74dB；THD：-102dB
警报 → 高，低阈值
器件信息(1)
•
•
•
™multiSPI 增强型 SPI 兼容接口，支持菊花链连接
工业级工作温度范围：
封装尺寸（标称值）
器件型号
ADS866x
封装
TSSOP (16)
5.00mm × 4.40mm
–40°C 至 +125°C
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
•
•
•
•
模拟输入模块
混合模块（AI、AO、DI、DO）
数据采集 (DAQ)
轨道旁信令和控制
DVDD
AVDD
ADS866x
REFIO
4.096-V
Reference
REFCAP
CONVST/CS
SCLK
1 MW
AIN_P
OVP
OVP
2nd-Order
LPF
Digital Logic
12-Bit
ADC
Driver
PGA
SDI
AIN_GND
and Interface
SAR ADC
SDO
1 MW
VBIAS
Oscillator
AGND
DGND
REFGND
方框图
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBAS780
ADS8661, ADS8665
ZHCSFU0B – DECEMBER 2016 – REVISED MARCH 2021
www.ti.com.cn
Table of Contents
7.1 Overview...................................................................20
7.2 Functional Block Diagram.........................................20
7.3 Feature Description...................................................21
7.4 Device Functional Modes..........................................33
7.5 Programming............................................................ 38
7.6 Register Maps...........................................................47
8 Application and Implementation..................................56
8.1 Application Information............................................. 56
8.2 Typical Application.................................................... 56
9 Power Supply Recommendations................................59
9.1 Power Supply Decoupling.........................................59
9.2 Power Saving............................................................59
10 Layout...........................................................................61
10.1 Layout Guidelines................................................... 61
10.2 Layout Example...................................................... 62
11 Device and Documentation Support..........................63
11.1 Documentation Support.......................................... 63
11.2 接收文档更新通知................................................... 63
11.3 支持资源..................................................................63
11.4 Trademarks............................................................. 63
11.5 静电放电警告...........................................................63
11.6 术语表..................................................................... 63
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Timing Requirements: Conversion Cycle....................8
6.7 Timing Requirements: Asynchronous Reset...............8
6.8 Timing Requirements: SPI-Compatible Serial
Interface........................................................................ 8
6.9 Timing Requirements: Source-Synchronous
Serial Interface (External Clock)....................................9
6.10 Timing Requirements: Source-Synchronous
Serial Interface (Internal Clock).....................................9
6.11 Timing Diagrams..................................................... 10
6.12 Typical Characteristics............................................13
7 Detailed Description......................................................20
4 Revision History
Changes from Revision A (October 2018) to Revision B (March 2021)
Page
更新了整个文档的表、图和交叉参考的编号格式 ............................................................................................... 1
更改了应用 部分..................................................................................................................................................1
•
•
• Changed AIN_P, AIN_GND to GND specification in Absolute Maximum Ratings table .................................... 4
• Updated specification of Input Overvoltage Protection Circuit, VOVP parameter, to ±15 V for test condition
AVDD = floating.................................................................................................................................................. 5
• Changed Standard SPI Timing Protocol figures...............................................................................................45
• Changed DEVICE_ADDR[3:0] type to R/W from R in DEVICE_ID_REG Register .........................................47
• Changed the description of PAR_EN bit in DATAOUT_CTL_REG Register ................................................... 51
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5 Pin Configuration and Functions
DGND
AVDD
1
2
3
4
5
6
7
8
16 DVDD
15 RVS
AGND
14 ALARM/SDO-1/GPO
13 SDO-0
REFIO
REFGND
REFCAP
AIN_P
12 SCLK
11 CONVST/CS
10 SDI
AIN_GND
9
RST
图 5-1. PW Package, 16-Pin TSSOP, Top View (Not to Scale)
表 5-1. Pin Functions
NO.
NAME
TYPE(1)
DESCRIPTION
TSSOP
AGND
3
8
7
P
Analog ground pin. Decouple with the AVDD pin.
AIN_GND
AIN_P
AI
AI
Analog input: negative. Decouple with the AIN_P pin.
Analog input: positive. Decouple with the AIN_GND pin.
Multi-function output pin. Active high alarm.
Data output 1 for serial communication. General-purpose output pin.
ALARM/SDO-1/GPO
AVDD
14
2
DO
P
Analog supply pin. Decouple with the AGND pin.
Dual-functionality pin.
Active high logic: conversion start input pin; a CONVST rising edge brings the device from
acquisition phase to conversion phase.
CONVST/CS
11
DI
Active low logic: chip-select input pin; the device takes control of the data bus when CS is
low; the SDO-x pins go to tri-state when CS is high.
DGND
1
16
6
P
P
Digital ground pin. Decouple with the DVDD pin.
DVDD
Digital supply pin. Decouple with the DGND pin.
REFCAP
AO
ADC reference buffer decoupling capacitor pin. Decouple with the REFGND pin.
Reference ground pin; short to the analog ground plane. Decouple with the REFIO and
REFCAP pins.
REFGND
5
P
REFIO
RST
4
9
AIO
DI
Internal reference output and external reference input pin. Decouple with REFGND.
Active low logic input to reset the device.
Multi-function output pin for serial interface; see the RESET State section.
With CS held high, RVS reflects the status of the internal ADCST signal.
With CS low, the status of RVS depends on the output protocol selection.
RVS
15
12
DO
DI
Serial communication: clock input pin for the serial interface.
All system-synchronous data transfer protocols are timed with respect to the SCLK signal.
SCLK
Dual function: data input pin for serial communication.
Chain data input during serial communication in daisy-chain mode.
SDI
10
13
DI
SDO-0
DO
Serial communication: data output 0
(1) AI = analog input, AIO = analog input/output, DI = digital input, DO = digital output, and P = power supply.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–20
–15
–0.3
–0.3
–0.3
–0.3
–0.3
–40
–65
MAX
UNIT
AVDD = 5 V(2)
AIN_P, AIN_GND to GND
20
V
AVDD = floating(3)
15
7
5.7
AVDD to GND or DVDD to GND
REFCAP to REFGND or REFIO to REFGND
GND to REFGND
V
V
V
V
V
0.3
DVDD + 0.3
DVDD + 0.3
125
Digital input pins to GND
Digital output pins to GND
Operating, TA
Temperature
Storage, Tstg
°C
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) AVDD = 5 V.
(3) AVDD = floating.
6.2 ESD Ratings
VALUE UNIT
Analog input pins
±4000
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
(AIN_P, AIN_GND)
V(ESD) Electrostatic discharge
V
All other pins
±2000
±500
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.75
1.65
NOM
5
MAX
5.25
UNIT
AVDD
DVDD
Analog supply voltage
Digital supply voltage
V
V
3.3
AVDD
6.4 Thermal Information
ADS8661,
ADS8665
PW (TSSOP)
16 PINS
95.7
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
29.3
41.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.5
ψJT
40.8
ψJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
all minimum and maximum specifications are at TA = –40°C to +125°C; typical specifications are at TA = 25°C; AVDD = 5 V,
DVDD = 3.3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Input range = ±3 × VREF
12.288
10.24
6.144
5.12
–12.288
–10.24
–6.144
–5.12
–2.56
0
Input range = ±2.5 × VREF
Input range = ±1.5 × VREF
Input range = ±1.25 × VREF
Input range = ±0.625 × VREF
Input range = 3 × VREF
Input range = 2.5 × VREF
Input range = 1.5 × VREF
Input range = 1.25 × VREF
Input range = ±3 × VREF
Input range = ±2.5 × VREF
Input range = ±1.5 × VREF
Input range = ±1.25 × VREF
Input range = ±0.625 × VREF
Input range = 3 × VREF
Input range = 2.5 × VREF
Input range = 1.5 × VREF
Input range = 1.25 × VREF
All input ranges
Full-scale input span(1)
(AIN_P to AIN_GND)
VIN
V
2.56
12.288
10.24
6.144
5.12
0
0
0
12.288
10.24
6.144
5.12
–12.288
–10.24
–6.144
–5.12
–2.56
0
AIN_P
Operating input range
V
2.56
12.288
10.24
6.144
5.12
0
0
0
AIN_GND
Operating input range
0
1.2
1.2
1.2
1.2
1
0.1
V
–0.1
1.02
1.02
1.02
1.02
0.85
0.85
0.85
0.85
0.85
Input range = ±3 × VREF
1.38
Input range = ±1.5 × VREF
Input range = 3 × VREF
1.38
1.38
Input range = 1.5 × VREF
Input range = ±2.5 × VREF
Input range = ±1.25 × VREF
Input range = ±0.625 × VREF
Input range = 2.5 × VREF
Input range = 1.25 × VREF
1.38
RIN
Input impedance
At TA = 25°C
1.15
MΩ
1
1.15
1
1.15
1
1.15
1
1.15
Input impedance drift
7
25 ppm/°C
Input range = ±3 × VREF
Input range = ±2.5 × VREF
Input range = ±1.5 × VREF
Input range = ±1.25 × VREF
(VIN – 2.5) / RIN
(VIN – 2.2) / RIN
(VIN – 2.0) / RIN
(VIN – 2.0) / RIN
(VIN – 1.6) / RIN
(VIN – 2.6) / RIN
(VIN – 2.5) / RIN
(VIN – 2.7) / RIN
(VIN – 2.5) / RIN
With voltage at
IIN
Input current
the AIN_P pin Input range = ±0.625 × VREF
µA
= VIN
Input range = 3 × VREF
Input range = 2.5 × VREF
Input range = 1.5 × VREF
Input range = 1.25 × VREF
INPUT OVERVOLTAGE PROTECTION CIRCUIT
VOVP All input ranges
AVDD = 5 V, all input ranges
20
V
15
–20
–15
AVDD = floating, all input ranges
INPUT BANDWIDTH
f–3 dB
All input ranges
All input ranges
15
–3 dB
Small-signal Input
bandwidth
kHz
f–0.1 dB
2.5
–0.1 dB
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6.5 Electrical Characteristics (continued)
all minimum and maximum specifications are at TA = –40°C to +125°C; typical specifications are at TA = 25°C; AVDD = 5 V,
DVDD = 3.3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYSTEM PERFORMANCE
Resolution
12
12
Bits
Bits
LSB
LSB
NMC
DNL
INL
No missing codes
Differential nonlinearity(4)
Integral nonlinearity(4)
All input ranges
All input ranges
±0.1
±0.15
±0.2
0.35
0.35
1
–0.35
–0.35
–1
All bipolar ranges(8)
All unipolar ranges(9)
EO
Offset error(2)
At TA = 25°C
mV
±0.2
2
–2
Offset error drift with temperature
Gain error(5)
All input ranges
±0.75
±0.01
±1
3
ppm/°C
–3
EG
At TA = 25°C, all input ranges
All input ranges
0.025 %FSR
–0.025
–5
Gain error drift with temperature(6)
5
ppm/°C
DYNAMIC CHARACTERISTICS
SNR
Signal-to-noise ratio(7)
All input ranges
All input ranges
All input ranges
All input ranges
73
73.5
–102
73.4
dB
dB
dB
dB
THD
Total harmonic distortion(3) (7)
Signal-to-noise + distortion(7)
Spurious-free dynamic range(7)
SINAD
SFDR
72.9
103
SAMPLING DYNAMICS
ADS8661
ADS8665
ADS8661
ADS8665
ADS8661
ADS8665
550
tCONV Conversion time
ns
ns
1000
250
tACQ
Acquisition time
1000
1250
500
Maximum throughput rate
without latency
fcycle
kSPS
INTERNAL REFERENCE OUTPUT
On the REFIO pin
VREFIO
At TA = 25°C
At TA = 25°C
4.095
4.096
4
4.097
V
(configured as an output)
dVREFIO/dTA
COUT_REFIO
Internal reference temperature drift
Decoupling capacitor on REFIO pin
ppm/°C
µF
4.7
Reference voltage to the ADC
(on the REFCAP pin)
VREFCAP
4.095
4.096
0.5
4.097
2
V
REFCAP temperature drift
Decoupling capacitor on REFCAP pin
Turn-on time
ppm/°C
μF
COUT_REFCAP
10
COUT_REFCAP = 10 µF, COUT_REFIO = 10 µF
REFIO pin configured as an input
20
ms
EXTERNAL REFERENCE INPUT
VREFIO_EXT
External reference voltage on REFIO
4.046
4.096
4.146
V
AVDD COMPARATOR
VTH_HIGH
VTH_LOW
High threshold voltage
Low threshold voltage
5.3
4.7
V
V
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6.5 Electrical Characteristics (continued)
all minimum and maximum specifications are at TA = –40°C to +125°C; typical specifications are at TA = 25°C; AVDD = 5 V,
DVDD = 3.3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER-SUPPLY REQUIREMENTS
AVDD
Analog power-supply voltage
4.75
1.65
2.7
5
3.3
3.3
7
5.25
AVDD
AVDD
9
Operating range
V
DVDD
Digital power-supply voltage
Supply range for specified performance
ADS8661
Internal
Analog supply current,
device converting at maximum
throughput
reference
ADS8665
4.9
5.8
3.7
2.9
1.7
2.8
1.6
10
6.5
IAVDD_DYN
mA
ADS8661
External
reference
7.25
4.5
ADS8665
Internal reference
External reference
Internal reference
External reference
Internal reference
External reference
4
Analog supply current,
device not converting
IAVDD_STC
IAVDD_STDBY
IAVDD_PD
mA
mA
μA
2.25
Analog supply current,
device in STANDBY mode
Analog supply current,
device in PD mode
10
Digital supply current,
maximum throughput
IDVDD_DYN
IDVDD_STDBY
IDVDD_PD
0.2
1
0.25
mA
μA
μA
Digital supply current,
device in STANDBY mode
Digital supply current,
device in PD mode
1
DIGITAL INPUTS (CMOS)
0.7 ×
DVDD
DVDD +
0.3
DVDD > 2.35 V
DVDD ≤ 2.35 V
DVDD > 2.35 V
DVDD ≤ 2.35 V
VIH
Digital high input voltage logic level
V
V
0.8 ×
DVDD
DVDD +
0.3
0.3 ×
DVDD
–0.3
–0.3
VIL
Digital low input voltage logic level
0.2 ×
DVDD
Input leakage current
Input pin capacitance
100
5
nA
pF
DIGITAL OUTPUTS (CMOS)
0.8 ×
DVDD
VOH
VOL
Digital high output voltage logic level
DVDD
V
V
IO = 500-μA source
0.2 ×
DVDD
Digital low output voltage logic level
0
IO = 500-μA sink
Floating state leakage current
Internal pin capacitance
Only for digital output pins
1
5
µA
pF
TEMPERATURE RANGE
TA Operating free-air temperature
125
°C
–40
(1) Ideal input span, does not include gain or offset error.
(2) Measured relative to actual measured reference.
(3) Calculated on the first nine harmonics of the input frequency.
(4) This specification indicates the endpoint INL, not best-fit INL.
(5) Excludes internal reference accuracy error.
(6) Excludes internal reference temperature drift.
(7) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with a 1-kHz input signal 0.25 dB below
full-scale, unless otherwise specified.
(8) Bipolar ranges are ±12.288 V, ±10.24 V, ±6.144 V, ±5.12 V, and ±2.56 V.
(9) Unipolar ranges are 0 V–12.288 V, 0 V–10.24 V, 0 V–6.144 V, and 0 V–5.12 V.
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6.6 Timing Requirements: Conversion Cycle
all minimum and maximum specifications are at TA = –40°C to +125°C; typical specifications are at TA = 25°C; AVDD = 5 V,
DVDD = 3.3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted)
MIN
TYP
MAX
UNIT
TIMING REQUIREMENTS
ADS8661
ADS8665
1250
500
fcycle
tcycle
tacq
Sampling frequency
ADC cycle time period
Acquisition time
kSPS
1/fcycle
250
ADS8661
ADS8665
ns
ns
1000
TIMING SPECIFICATIONS
tconv Conversion time
ADS8661
ADS8665
550
1000
6.7 Timing Requirements: Asynchronous Reset
all minimum and maximum specifications are at TA = –40°C to +125°C; typical specifications are at TA = 25°C; AVDD = 5 V,
DVDD = 3.3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted)
MIN
TYP
MAX
UNIT
TIMING REQUIREMENTS
twl_RST
Pulse duration: RST high
100
ns
TIMING SPECIFICATIONS
tD_RST_POR Delay time for POR reset: RST rising to RVS rising
20
20
ms
µs
tD_RST_APP
tNAP_WKUP
tPWRUP
Delay time for application reset: RST rising to CONVST/CS rising
Wake-up time: NAP mode
1
20
µs
Power-up time: PD mode
ms
6.8 Timing Requirements: SPI-Compatible Serial Interface
all minimum and maximum specifications are at TA = –40°C to +125°C; typical specifications are at TA = 25°C; AVDD = 5 V,
DVDD = 3.3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted)
MIN
TYP
MAX
UNIT
TIMING REQUIREMENTS
fCLK
Serial clock frequency
66.67
MHz
tCLK
Serial clock time period
1/fCLK
0.45
0.45
7.5
tPH_CK
tPL_CK
SCLK high time
0.55
0.55
tCLK
tCLK
ns
SCLK low time
tSU_CSCK
tSU_CKDI
tHT_CKDI
tHT_CKCS
Setup time: CONVST/CS falling to first SCLK capture edge
Setup time: SDI data valid to SCLK capture edge
Hold time: SCLK capture edge to (previous) data valid on SDI
Delay time: last SCLK capture edge to CONVST/CS rising
7.5
ns
7.5
ns
7.5
ns
TIMING SPECIFICATIONS
tDEN_CSDO
tDZ_CSDO
tD_CKDO
Delay time: CONVST/CS falling edge to data enable
9.5
10
12
14
ns
ns
ns
ns
Delay time: CONVST/CS rising to SDO-x going to 3-state
Delay time: SCLK launch edge to (next) data valid on SDO-x
Delay time: CONVST/CS rising edge to RVS falling
tD_CSRVS
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6.9 Timing Requirements: Source-Synchronous Serial Interface (External Clock)
all minimum and maximum specifications are at TA = –40°C to +125°C; typical specifications are at TA = 25°C; AVDD = 5 V,
DVDD = 3.3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted)
MIN
TYP
MAX
UNIT
TIMING REQUIREMENTS
fCLK
Serial clock frequency
66.67
MHz
tCLK
Serial clock time period
SCLK high time
1/fCLK
0.45
tPH_CK
tPL_CK
0.55
0.55
tCLK
tCLK
SCLK low time
0.45
TIMING SPECIFICATIONS
tDEN_CSDO
tDZ_CSDO
tD_CKRVS_r
tD_CKRVS_f
tD_RVSDO
tD_CSRVS
Delay time: CONVST/CS falling edge to data enable
9.5
10
14
14
2.5
15
ns
ns
ns
ns
ns
ns
Delay time: CONVST/CS rising to SDO-x going to 3-state
Delay time: SCLK rising edge to RVS rising
Delay time: SCLK falling edge to RVS falling
Delay time: RVS rising to (next) data valid on SDO-x
Delay time: CONVST/CS rising edge to RVS displaying internal device state
6.10 Timing Requirements: Source-Synchronous Serial Interface (Internal Clock)
all minimum and maximum specifications are at TA = –40°C to +125°C; typical specifications are at TA = 25°C; AVDD = 5 V,
DVDD = 3.3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted)
MIN
TYP
MAX
UNIT
TIMING SPECIFICATIONS
tDEN_CSDO Delay time: CONVST/CS falling edge to data enable
tDZ_CSDO Delay time: CONVST/CS rising to SDO-x going to 3-state
tDEN_CSRVS Delay time: CONVST/CS falling edge to first rising edge on RVS
9.5
10
ns
ns
50
ns
tD_RVSDO
tINTCLK
Delay time: RVS rising to (next) data valid on SDO-x
Time period: internal clock
Time period: RVS signal
RVS high time
2.5
ns
15
15
ns
tCYC_RVS
tWH_RVS
tWL_RVS
ns
0.4
0.4
0.6
0.6
tINTCLK
tINTCLK
RVS low time
Delay time: CONVST/CS rising edge to RVS displaying internal
device state
tD_CSRVS
15
ns
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6.11 Timing Diagrams
The CS falling edge can
be issued after tconv_max
or when RVS goes high.
tcycle
CONVST/CS
tconv
tacq
ADCST (Internal)
RVS
图 6-1. Conversion Cycle Timing Diagram
trst
twl_RST
RST
RVS
td_rst
图 6-2. Asynchronous Reset Timing Diagram
tcycle
Data Read Time
tconv_max
CONVST/CS
tD_CSRVS
tD_CSRVS
RVS
tHT_CKCS
tSU_CSCK
CPOL = 0
SCLK
CPOL = 1
tD_CSDO
tD_CKDO
tDEN_CSDO
M
M-1
L+1
L
M-2
SDO-0
tSU_CKDI
tHT_CKDI
SDI
图 6-3. Standard SPI Interface Timing Diagram for CPHA = 0
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tcycle
tconv_max
Data Read Time
CONVST/CS
RVS
tD_CSRVS
tD_CSRVS
tHT_CKCS
tSU_CSCK
CPOL = 0
CPOL = 1
SCLK
tD_CKDO
L+1
tDZ_CSDO
tDEN_CSDO
SDO-0
SDI
0
M
M-1
L
tSU_CKDI
tHT_CKDI
图 6-4. Standard SPI Interface Timing Diagram for CPHA = 1
tcycle
Data Read Time
tconv_max
CONVST/CS
tD_CSRVS
tD_CSRVS
RVS
tHT_CKCS
tSU_CSCK
CPOL = 0
SCLK
CPOL = 1
tD_CSDO
tD_CKDO
tDEN_CSDO
M
M-2
M-3
L+3
L+2
L+1
M-4
SDO-0
SDO-1
M-1
L
M-5
tSU_CKDI
tHT_CKDI
SDI
图 6-5. multiSPI Interface Timing Diagram for Dual SDO-x and CPHA = 0
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tcycle
Data Read Time
tconv_max
CONVST/CS
tD_CSRVS
tD_CSRVS
RVS
tHT_CKCS
tSU_CSCK
CPOL = 0
SCLK
CPOL = 1
tD_CKDO
tDZ_CSDO
tDEN_CSDO
SDO-0
0
0
M
M-2
M-1
L+3
L+1
L
M-1
L+2
SDO-1
SDI
tSU_CKDI
tHT_CKDI
图 6-6. multiSPI Interface Timing Diagram for Dual SDO-x and CPHA = 1
Data Read Time
tconv
CONVST/CS
tSU_CSCK
SCLK
tDEN_CSDO
tDZ_CSDO
tD_RVSDO
SDO-0
RVS
M
M-1
M-k
M-k-1 M-k-2
L+1
L
tD_CKRVS_r
tD_CSRVS
tD_CKRVS_f
tD_CSRD
图 6-7. multiSPI Source-Synchronous External Clock Serial Interface Timing Diagram
Data Read Time
tconv_max
CONVST/CS
SCLK
tDEN_CSDO
tDZ_CSDO
SDO-0
RVS
L+1
L
M
M-1
M-k
M-k-1
M-k-2
tD_RVSDO
tD_CSRVS
tWH_RVS
tDEN_CSRVS
tCYC_RVS
tWL_RVS
图 6-8. multiSPI Source-Synchronous Internal Clock Serial Interface Timing Diagram
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6.12 Typical Characteristics
at TA = 25°C, AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted)
15
9
15
12.288 V
10.24 V
6.144 V
5.12 V
2.56 V
-40C
25C
125C
9
0-12.288 V
0-10.24 V
0-6.144 V
0-5.12 V
3
3
-3
-9
-15
-3
-9
-15
-12.288 -8.192
-12.288 -8.192
-4.096
0
Input Voltage (V)
4.096
8.192
12.288
-4.096
0
Input Voltage (V)
4.096
8.192
12.288
D001
D002
Range = ±12.288 V
图 6-9. Input I-V Characteristic Across Input Ranges
图 6-10. Input I-V Characteristic Across Temperature
400
1600
1400
1200
1000
800
200
0
600
12.288 V
10.24 V
6.144 V
5.12 V
0-12.288 V
0-10.24 V
0-6.144 V
0-5.12 V
400
-200
200
2.56 V
0
-400
1.02 1.06 1.1 1.14 1.18 1.22 1.26 1.3 1.34 1.38
Input Impedance (MW)
-40
-7
26
59
92
125
Free- Air Temperature (èC)
D004
D003
Number of samples = 3398
图 6-12. Typical Distribution of Input Impedance
75000
图 6-11. Input Impedance Drift vs Temperature
75000
60000
45000
30000
15000
0
60000
45000
30000
15000
0
2045
2046
Output Codes
2047
2045
2046
Output Codes
2047
D002
D001
Mean = 2046, sigma = 0, input = 0 V
图 6-14. DC Histogram for Mid-Scale Inputs (±10.24 V)
Mean = 2046, sigma = 0, input = 0 V
图 6-13. DC Histogram for Mid-Scale Inputs (±12.288 V)
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6.12 Typical Characteristics (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted)
75000
60000
45000
30000
15000
0
75000
60000
45000
30000
15000
0
2045
2046
Output Codes
2047
2045
2046
Output Codes
2047
D003
D005
D007
D004
Mean = 2046, sigma = 0, input = 0 V
Mean = 2046, sigma = 0, input = 0 V
图 6-15. DC Histogram for Mid-Scale Inputs (±6.144 V)
图 6-16. DC Histogram for Mid-Scale Inputs (±5.12 V)
75000
75000
60000
45000
30000
15000
0
60000
45000
30000
15000
0
2045
2046
Output Codes
2047
2048
2049
Output Codes
2050
D006
Mean = 2046, sigma = 0, input = 0 V
Mean = 2049, sigma = 0, input = 6.144 V
图 6-17. DC Histogram for Mid-Scale Inputs (±2.56 V)
图 6-18. DC Histogram for Mid-Scale Inputs (0 V–12.288 V)
75000
75000
60000
45000
30000
15000
0
60000
45000
30000
15000
0
2044
2045
Output Codes
2046
2044
2045
Output Codes
2046
D008
Mean = 2045, sigma = 0, input = 3.072 V
Mean = 2045, sigma = 0, input = 5.12 V
图 6-20. DC Histogram for Mid-Scale Inputs (0 V–6.144 V)
图 6-19. DC Histogram for Mid-Scale Inputs (0 V–10.24 V)
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6.12 Typical Characteristics (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted)
75000
60000
45000
30000
15000
0
0.5
0.25
0
-0.25
-0.5
2045
2046
Output Codes
2047
0
1024
2048
Codes (LSB)
3072
4095
D009
D010
Mean = 2046, sigma = 0, input = 2.56 V
All input ranges
图 6-22. Typical DNL for All Codes
图 6-21. DC Histogram for Mid-Scale Inputs (0 V–5.12 V)
0.5
0.5
0.25
0
Maximum
Minimum
0.25
0
-0.25
-0.5
-0.25
-0.5
0
1024
2048
Codes (LSB)
3072
4095
-40
-7
26
59
92
125
Free-Air Temperature (èC)
D012
D011
All input ranges
图 6-24. Typical INL for All Codes (All Bipolar Ranges)
图 6-23. DNL vs Temperature
0.5
0.5
Maximum
Minimum
0.25
0
0.25
0
-0.25
-0.5
-0.25
-0.5
0
1024
2048
Codes (LSB)
3072
4095
-40
-7
26
59
92
125
Free-Air Temperature (èC)
D013
D014
图 6-25. Typical INL for All Codes (All Unipolar Ranges)
图 6-26. INL vs Temperature (All Bipolar Ranges)
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6.12 Typical Characteristics (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted)
0.5
0.25
0
1
0.75
0.5
Maximum
Minimum
12.288 V
10.24 V
6.144 V
5.12 V
2.56 V
0-12.288 V
0-10.24 V
0-6.144 V
0-5.12 V
0.25
0
-0.25
-0.5
-0.75
-1
-0.25
-0.5
-40
-7
26
59
92
125
-40
-7
26
59
92
125
Free-Air Temperature (0C)
Free-Air Temperature (èC)
D015
D036
图 6-27. INL vs Temperature (All Unipolar Ranges)
图 6-28. Offset Error vs Temperature Across Input Ranges
12.5
0.025
12.288 V
10.24 V
6.144 V
5.12 V
2.56 V
0-12.288 V
0-10.24 V
0-6.144 V
0-5.12 V
0.015
0.005
10
7.5
5
-0.005
-0.015
-0.025
2.5
0
-40
-7
26
59
92
125
0
0.2 0.4 0.6 0.8
1 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8
Offset Drift (ppm/ºC)
3
Free-Air Temperature (0C)
D038
D037
图 6-30. Gain Error vs Temperature Across Input Ranges
图 6-29. Typical Histogram for Offset Drift
25
1.1
12.288 V
10.24 V
6.144 V
5.12 V
2.56 V
0-12.288 V
0-10.24 V
0-6.144 V
0-5.12 V
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
20
15
10
5
-0.1
0
0
2000
4000
6000
8000
10000
0
0.5
1
1.5
2
2.5
3
Gain Drift (ppm/ºC)
3.5
4
4.5
5
Source Resistance (W)
D040
D039
图 6-32. Gain Error vs External Resistance (REXT
)
图 6-31. Typical Histogram for Gain Error Drift
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6.12 Typical Characteristics (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted)
0
0
-30
-30
-60
-60
-90
-90
-120
-150
-180
-120
-150
-180
0
125000
250000 375000
Input Frequency (Hz)
500000
625000
0
50000
100000 150000
Input Frequency (Hz)
200000
250000
D016
D017
Number of points = 64k, fIN = 1 kHz
Number of points = 64k, fIN = 1 kHz
图 6-33. Typical FFT Plot (All Ranges) for the ADS8661
图 6-34. Typical FFT Plot (All Ranges) for the ADS8665
74
74
73.5
73
73.5
73
12.288 V
10.24 V
6.144 V
5.12 V
0-12.288 V
0-10.24 V
0-6.144 V
0-5.12 V
12.288 V
10.24 V
6.144 V
5.12 V
0-12.288 V
0-10.24 V
0-6.144 V
0-5.12 V
72.5
72.5
2.56 V
2.56 V
72
72
100
1k
Input Frequency (Hz)
10k
-40
-7
26
59
92
125
Free-Air Temperature (èC)
D018
D019
fIN = 1 kHz
图 6-35. SNR vs Input Frequency
图 6-36. SNR vs Temperature
74
73
72
71
70
74
73
72
71
70
12.288 V
10.24 V
6.144 V
5.12 V
2.56 V
0-12.288 V
0-10.24 V
0-6.144 V
0-5.12 V
12.288 V
10.24 V
6.144 V
5.12 V
0-12.288 V
0-10.24 V
0-6.144 V
0-5.12 V
2.56 V
100
1k
Input Frequency (Hz)
10k
-40
-7
26
59
92
125
Free-AirTemperature (èC)
D020
D021
fIN = 1 kHz
图 6-37. SINAD vs Input Frequency
图 6-38. SINAD vs Temperature
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6.12 Typical Characteristics (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted)
-80
-80
12.288 V
10.24 V
6.144 V
5.12 V
0-12.288 V
0-10.24 V
0-6.144 V
0-5.12 V
12.288 V
10.24 V
6.144 V
5.12 V
2.56 V
0-12.288 V
0-10.24 V
0-6.144 V
0-5.12 V
-90
-90
2.56 V
-100
-110
-120
-100
-110
-120
100
1k
Input Frequency (Hz)
10k
-40
-7
26
59
92
125
Free-AirTemperature (èC)
D022
D023
fIN = 1 kHz
图 6-39. THD vs Input Frequency
图 6-40. THD vs Temperature
9
8
7
6
5
4
3
2
1
7
6.5
6
5.5
5
4.5
4
ADS8661
ADS8665
3.5
0
250
500 750
Throughput (ksps)
1000
1250
-40
-7
26
59
92
125
Free-Air Temperature (èC)
D026
D024
图 6-42. AVDD Current vs Throughput
图 6-41. AVDD Current vs Temperature
4
3.5
3
2.8
2.7
2.6
2.5
2.4
12.288 V
10.24 V
6.144 V
5.12 V
2.56 V
0-12.288 V
0-10.24 V
0-6.144 V
0-5.12 V
2.5
2
-40
-7
26
59
92
125
-40
-7
26
59
92
125
Free-Air Temperature (èC)
Free-Air Temperature (0C)
D025
D067
图 6-43. AVDD Current vs Temperature (During Sampling)
图 6-44. AVDD Current vs Temperature (Standby Mode)
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6.12 Typical Characteristics (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and maximum throughput (unless otherwise noted)
3
12.288 V
10.24 V
6.144 V
5.12 V
2.56 V
0-12.288 V
0-10.24 V
0-6.144 V
0-5.12 V
2.5
2
1.5
1
0.5
0
-40
-7
26
59
92
125
Free-Air Temperature (0C)
D068
图 6-45. AVDD Current vs Temperature (Power-Down Mode)
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7 Detailed Description
7.1 Overview
The ADS866x devices belong to a family of high-speed, high-performance, easy-to-use integrated data
acquisition system. This single-channel device supports true bipolar input voltage swings up to ±12.288 V,
operating on a single 5-V analog supply. The device features an enhanced SPI interface (multiSPI) that allows
the sampling rate to be maximized even with lower speed host controllers.
The device consists of a high-precision successive approximation register (SAR) analog-to-digital converter
(ADC) and a power-optimized analog front-end (AFE) circuit for signal conditioning that includes:
• A high-resistive input impedance (≥ 1 MΩ) that is independent of the sampling rate
• A programmable gain amplifier (PGA) with a pseudo-differential input configuration supporting nine software-
programmable unipolar and bipolar input ranges
• A second-order, low-pass antialiasing filter
• An ADC driver amplifier that ensures quick settling of the SAR ADC input for high accuracy
• An input overvoltage protection circuit up to ±20 V
The device also features a low temperature drift, 4.096-V internal reference with a fast-settling buffer and a
multiSPI serial interface with daisy-chain (DAISY) and ALARM features.
The integration of the precision AFE circuit with high input impedance and a precision ADC operating from a
single 5-V supply offers a simplified end solution without requiring external high-voltage bipolar supplies and
complicated driver circuits.
7.2 Functional Block Diagram
DVDD
AVDD
ADS866x
REFIO
4.096-V
Reference
REFCAP
CONVST/CS
SCLK
1 MW
1 MW
AIN_P
OVP
OVP
2nd-Order
LPF
Digital Logic
and Interface
ADC
Driver
12-Bit
SAR ADC
PGA
SDI
AIN_GND
SDO
VBIAS
Oscillator
AGND
DGND
REFGND
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7.3 Feature Description
7.3.1 Analog Input Structure
The device features a pseudo-differential input structure, meaning that the single-ended analog input signal is
applied at the positive input AIN_P and the negative input AIN_GND is tied to GND. 图 7-1 shows the simplified
circuit schematic for the AFE circuit, including the input overvoltage protection circuit, PGA, low-pass filter (LPF),
and high-speed ADC driver.
1 MW
CONVST/CS
AIN_P
OVP
OVP
2nd-Order
LPF
ADC
Driver
SCLK
SDI
SDO
PGA
ADC
AIN_GND
1 MW
VB
图 7-1. Simplified Analog Front-End Circuit Schematic
The device can support multiple unipolar or bipolar, single-ended input voltage ranges based on the
configuration of the program registers. As explained in the RANGE_SEL_REG register, the input voltage range
can be configured to bipolar ±3 × VREF, ±2.5 × VREF, ±1.5 × VREF, ±1.25 × VREF, and ±0.625 × VREF or unipolar 0
to 3 × VREF, 0 to 2.5 × VREF, 0 to 1.5 × VREF and 0 to 1.25 × VREF. With the internal or external reference voltage
set to 4.096 V, the input ranges of the device can be configured to bipolar ranges of ±12.288 V, ±10.24 V, ±6.144
V, ±5.12 V, and ±2.56 V or unipolar ranges of 0 V to 12.288 V, 0 V to 10.24 V, 0 V to 6.144 V, and 0 V to 5.12 V.
The device samples the voltage difference (AIN_P – AIN_GND) between the analog input and the AIN_GND
pin. The device allows a ±0.1-V range on the AIN_GND pin. This feature is useful in modular systems where the
sensor or signal-conditioning block is further away from the ADC on the board and when a difference in the
ground potential of the sensor or signal conditioner from the ADC ground is possible. In such cases, running
separate wires from the AIN_GND pin of the device to the sensor or signal-conditioning ground is recommended.
In order to obtain optimum performance, the input currents and impedances along each input path are
recommended to be matched. The two single-ended signals to AIN_P and AIN_GND must be routed as
symmetrically as possible from the signal source to the ADC input pins.
If the analog input pin (AIN_P) to the device is left floating, the output of the ADC corresponds to an internal
biasing voltage. The output from the ADC must be considered as invalid if the device is operated with floating
input pins. This condition does not cause any damage to the device, which becomes fully functional when a valid
input voltage is applied to the pins.
7.3.2 Analog Input Impedance
The device presents a resistive input impedance ≥ 1 MΩ on each of the analog inputs. The input impedance is
independent of the ADC sampling frequency or the input signal frequency. The primary advantage of such high-
impedance inputs is the ease of driving the ADC inputs without requiring driving amplifiers with low output
impedance. Bipolar, high-voltage power supplies are not required in the system because this ADC does not
require any high-voltage, front-end drivers. In most applications, the signal sources or sensor outputs can be
directly connected to the ADC input, thus significantly simplifying the design of the signal chain.
In order to maintain the dc accuracy of the system, matching the external source impedance on the AIN_P input
pin with an equivalent resistance on the AIN_GND pin is recommended. This matching helps cancel any
additional offset error contributed by the external resistance.
7.3.3 Input Protection Circuit
The device features an internal overvoltage protection (OVP) circuit on each of the analog inputs. Use the
internal protection circuit only as a secondary protection scheme. The external protection devices in the end
application are highly recommended to be used to protect against surges, electrostatic discharge (ESD), and
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electrical fast transient (EFT) conditions. A conceptual block diagram of the internal OVP circuit is shown in 图
7-2.
AVDD
VP+
RFB
0 V
ESD
AVDD
1 MΩ
VP-
RS
D1p
D2p
AIN_P
Vœ
V+
AVDD
D1n
D2n
VOUT
RS
AIN_GND
+
1 MΩ
RDC
ESD
VB
GND
图 7-2. Input Overvoltage Protection Circuit Schematic
As shown in 图 7-2, the combination of the 1-MΩ (or, 1.2 MΩ for appropriate input ranges) input resistors along
with the PGA gain-setting resistors RFB and RDC limit the current flowing into the input pin. A combination of anti-
parallel diodes, D1 and D2 are added to protect the internal circuitry and set the overvoltage protection limits.
表 7-1 explains the various operating conditions for the device when powered on. This table indicates that when
the device is properly powered up (AVDD = 5 V) or offers a low impedance of < 30 kΩ, the internal overvoltage
protection circuit can withstand up to ±20 V on the analog input pins.
表 7-1. Input Overvoltage Protection Limits When AVDD = 5 V(1)
INPUT CONDITION
(VOVP = ±20 V)
TEST
CONDITION
ADC
OUTPUT
COMMENTS
CONDITION
RANGE
All input
ranges
|VIN| < |VRANGE
|
Within operating range
Valid
Device functions as per data sheet specifications.
Beyond operating range but
within overvoltage range
All input
ranges
ADC output is saturated, but device is internally protected
(not recommended for extended time).
|VRANGE| < |VIN| < |VOVP
|
Saturated
Saturated
All input
ranges
This usage condition can cause irreversible damage to the
device.
|VIN| > |VOVP
|
Beyond overvoltage range
(1) GND = 0 V, AIN_GND = 0 V, |VRANGE| is the maximum input voltage for any selected input range, and |VOVP| is the break-down voltage
for the internal OVP circuit. Assume that RS is approximately 0 Ω.
The results indicated in 表 7-1 are based on an assumption that the analog input pin is driven by a very low
impedance source (RS is approximately 0 Ω). However, if the source driving the input has higher impedance, the
current flowing through the protection diodes reduces further, thereby increasing the OVP voltage range. Higher
source impedances result in gain errors and contribute to overall system noise performance.
图 7-3 shows the voltage versus current response of the internal overvoltage protection circuit when the device is
powered on. According to this current-to-voltage (I-V) response, the current flowing into the device input pin is
limited by the 1-MΩ (or 1.2 MΩ for appropriate input ranges) input impedance. However, for voltages beyond
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±20 V, the internal node voltages surpass the break-down voltage for internal transistors, thus setting the limit for
overvoltage protection on the input pin.
The same overvoltage protection circuit also provides protection to the device when the device is not powered
on and AVDD is floating. This condition can arise when the input signals are applied before the ADC is fully
powered on. The overvoltage protection limits for this condition are shown in 表 7-2.
表 7-2. Input Overvoltage Protection Limits When AVDD = Floating(1)
INPUT CONDITION
(VOVP = ±15 V)
TEST CONDITION
ADC OUTPUT
COMMENTS
CONDITION
RANGE
Device is not functional but is protected internally by the
OVP circuit.
|VIN| < |VOVP
|
|
Within overvoltage range
All input ranges
All input ranges
Invalid
Invalid
This usage condition can cause irreversible damage to the
device.
|VIN| > |VOVP
Beyond overvoltage range
(1) AVDD = floating, GND = 0 V, AIN_GND = 0 V, |VRANGE| is the maximum input voltage for any selected input range, and |VOVP| is the
break-down voltage for the internal OVP circuit. Assume that RS is approximately 0 Ω.
图 7-4 shows the I-V response of the internal overvoltage protection circuit when the device is not powered on.
According to this I-V response, the current flowing into the device input pin is limited by the 1-MΩ input
impedance. However, for voltages beyond ±15 V, the internal node voltage surpasses the break-down voltage
for internal transistors, thus setting the limit for overvoltage protection on the input pin.
30
20
24
18
12
6
10
0
0
-6
-10
-20
-30
-12
-18
-24
-20 -16 -12
-8
-4
0
4
Input voltage (V)
8
12
16
20
-30 -24 -18 -12
-6
Input voltage (V)
0
6
12
18
24
30
D006
D005
图 7-3. I-V Curve for the Input OVP Circuit (AVDD =
图 7-4. I-V Curve for the Input OVP Circuit (AVDD =
5 V)
Floating)
7.3.4 Programmable Gain Amplifier (PGA)
The device features a programmable gain amplifier (PGA) as part of the analog signal-conditioning circuit that
converts the original single-ended input signal into a fully-differential signal to drive the internal SAR ADC. The
PGA also adjusts the common-mode level of the input signal before feeding it into the SAR ADC to ensure
maximum usage of the ADC input dynamic range. Depending on the range of the input signal, the PGA gain can
be adjusted by setting the RANGE_SEL[3:0] bits in the configuration register (see the RANGE_SEL_REG
register). The default or power-on state for the RANGE_SEL[3:0] bits is 0000, corresponding to an input signal
range of ±3 × VREF. 表 7-3 lists the various configurations of the RANGE_SEL[3:0] bits for the different analog
input voltage ranges.
The PGA uses a precisely-matched network of resistors for multiple gain configurations. Matching between
these resistors is accurately trimmed to keep the overall gain error low across all input ranges.
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表 7-3. Input Range Selection Bits Configuration
RANGE_SEL[3:0]
ANALOG INPUT RANGE
BIT 3
BIT 2 BIT 1
BIT 0
±3 × VREF
±2.5 × VREF
0
0
0
0
0
1
1
1
1
0
0
0
1
0
1
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
1
0
0
0
1
1
±1.5 × VREF
±1.25 × VREF
±0.625 × VREF
0–3 × VREF
0–2.5 × VREF
0–1.5 × VREF
0–1.25 × VREF
7.3.5 Second-Order, Low-Pass Filter (LPF)
In order to mitigate the noise of the front-end amplifier and gain resistors of the PGA, the AFE circuit of the
device features a second-order, antialiasing LPF at the output of the PGA. The magnitude and phase response
of the analog antialiasing filter are shown in 图 7-5 and 图 7-6, respectively. For maximum performance, the –3-
dB cutoff frequency for the antialiasing filter is typically set to 15 kHz. The performance of the filter is consistent
across all input ranges supported by the ADC.
3
0
45
0
-3
12.288 V
10.24 V
6.144 V
5.12 V
2.56 V
0-12.288 V
0-10.24 V
0-6.144 V
0-5.12 V
12.288 V
10.24 V
6.144 V
5.12 V
2.56 V
0-12.288 V
0-10.24 V
0-6.144 V
0-5.12 V
-45
-90
-135
-6
-9
-12
-15
10
10
100
1k
Input Frequency (Hz)
10k
100k
100
1k
Input Frequency (Hz)
10k
100k
D059
D058
图 7-6. Second-Order LPF Phase Response
图 7-5. Second-Order LPF Magnitude Response
7.3.6 ADC Driver
In order to meet the performance of the device at the maximum sampling rate, the sample-and-hold capacitors at
the input of the ADC must be successfully charged and discharged during the acquisition time window. This drive
requirement at the input of the ADC necessitates the use of a high-bandwidth, low-noise, and stable amplifier
buffer. Such an input driver is integrated in the front-end signal path of the analog input channel of the device.
7.3.7 Reference
The device can operate with either an internal voltage reference or an external voltage reference using the
internal buffer. The internal or external reference selection is determined by programming the INTREF_DIS bit of
the RANGE_SEL_REG register. The internal reference source is enabled (INTREF_DIS = 0) by default after
reset or when the device powers up. The INTREF_DIS bit must be programmed to logic 1 to disable the internal
reference source whenever an external reference source is used.
7.3.7.1 Internal Reference
The device features an internal reference source with a nominal output value of 4.096 V. In order to select the
internal reference, the INTREF_DIS bit of the RANGE_SEL_REG register must be programmed to logic 0. When
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the internal reference is used, the REFIO pin becomes an output with the internal reference value. A 4.7-µF
(minimum) decoupling capacitor is recommended to be placed between the REFIO pin and REFGND, as shown
in 图 7-7. The capacitor must be placed as close to the REFIO pin as possible. The output impedance of the
internal band-gap circuit creates a low-pass filter with this capacitor to band-limit the noise of the reference. The
use of a smaller capacitor value allows higher reference noise in the system that can potentially degrade SNR
and SINAD performance. The REFIO pin must not be used to drive external ac or dc loads because of limited
current output capability. The REFIO pin can be used as a source if followed by a suitable op amp buffer (such
as the OPA320).
AVDD
4.096 VREF
RANGE_SEL_REG[6] = 0
(INTREF_DIS)
REFIO
4.7 mF
REFCAP
10 mF
1 mF
REFGND
ADC
AGND
图 7-7. Device Connections for Using an Internal 4.096-V Reference
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The device internal reference is factory-trimmed to ensure the initial accuracy specification. The histogram in 图
7-8 shows the distribution of the internal voltage reference output taken from more than 3420 production
devices.
1000
900
800
700
600
500
400
300
200
100
0
4.094 4.0945 4.095 4.0955 4.096 4.0965 4.097 4.0975 4.098
REFIO Voltage (V)
D060
图 7-8. Internal Reference Accuracy Histogram at Room Temperature
The initial accuracy specification for the internal reference can be degraded if the die is exposed to any
mechanical or thermal stress. Heating the device when being soldered to a printed circuit board (PCB) and any
subsequent solder reflow is a primary cause for shifts in the VREF value. The main cause of thermal hysteresis is
a change in die stress and is therefore a function of the package, die-attach material, and molding compound, as
well as the layout of the device itself.
In order to illustrate this effect, 30 devices were soldered using lead-free solder paste with the manufacturer
suggested reflow profile, as explained in the AN-2029 Handling & Process Recommendations application report.
The internal voltage reference output is measured before and after the reflow process and the typical shift in
value is shown in 图 7-9. Although all tested units exhibit a positive shift in their output voltages, negative shifts
are also possible. The histogram in 图 7-9 shows the typical shift for exposure to a single reflow profile.
Exposure to multiple reflows, which is common on PCBs with surface-mount components on both sides, causes
additional shifts in the output voltage. If the PCB is to be exposed to multiple reflows, solder the ADS866x in the
second pass to minimize device exposure to thermal stress.
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-7
-6
-5
-4
-3
-2
-1
Error in REFIO Voltage (mV)
0
1
D070
图 7-9. Solder Heat Shift Distribution Histogram
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The internal reference is also temperature compensated to provide excellent temperature drift over an extended
industrial temperature range of –40°C to +125°C. 图 7-10 shows the variation of the internal reference voltage
across temperature for different values of the AVDD supply voltage. The temperature drift of the internal
reference is also a function of the package type. 图 7-11 shows histogram distribution of the reference voltage
drift.
4.1
4.099
4.098
4.097
4.096
4.095
4.094
4.093
4.092
4.091
4.09
14
12
10
8
AVDD = 5.25 V
AVDD = 5 V
AVDD = 4.75 V
6
4
2
0
-40
-7
26
59
92
125
Free-Air Temperature (0C)
3.1 3.5 3.9 4.3 4.7 5.1 5.5 5.9 6.3 6.7 7.1
REFIO Drift (ppm/ºC)
D061
D062
AVDD = 5 V, number of devices = 30, ΔT = –40°C to +125°C
图 7-10. REFIO Voltage Variation Across AVDD and
图 7-11. Internal Reference Temperature Drift
Temperature
Histogram
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7.3.7.2 External Reference
For applications that require a better reference voltage or a common reference voltage for multiple devices, the
device provides a provision to use an external reference source along with an internal buffer to drive the ADC
reference pin. In order to select the external reference mode, the INTREF_DIS bit of the RANGE_SEL_REG
register must be programmed to logic 1. In this mode, an external 4.096-V reference must be applied at the
REFIO pin, which functions as an input. Any low-power, low-drift, or small-size external reference can be used in
this mode because the internal buffer is optimally designed to handle the dynamic loading on the REFCAP pin
that is internally connected to the ADC reference input. The output of the external reference must be
appropriately filtered to minimize the resulting effect of the reference noise on system performance. A typical
connection diagram for this mode is shown in 图 7-12.
AVDD
4.096 VREF
AVDD
RANGE_SEL_REG[6] = 1
(INTREF_DIS)
REF5040
(See the device datasheet for
a detailed pin configuration.)
OUT
REFIO
CREF
REFCAP
1 mF
10 mF
REFGND
AGND
ADC
图 7-12. Device Connections for Using an External 4.096-V Reference
The output of the internal reference buffer appears at the REFCAP pin. A minimum capacitance of 10 µF must
be placed between the REFCAP and REFGND pins. Place another capacitor of 1 µF as close to the REFCAP
pin as possible for decoupling high-frequency signals. Do not use the internal buffer to drive external ac or dc
loads because of the limited current output capability of this buffer.
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The performance of the internal buffer output is very stable across the entire operating temperature range of –
40°C to +125°C. 图 7-13 shows the variation in the REFCAP output across temperature for different values of
the AVDD supply voltage. The typical specified value of the reference buffer drift over temperature is 0.5 ppm/°C,
as shown in 图 7-14, and the maximum specified temperature drift is equal to 2 ppm/°C.
4.1
4.099
4.098
4.097
4.096
4.095
4.094
4.093
4.092
4.091
4.09
24
20
16
12
8
AVDD = 5.25 V
AVDD = 5 V
AVDD = 4.75 V
4
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
REFCAP Drift (ppm/ºC)
-40
-7
26
59
92
125
Free-Air Temperature (0C)
D064
D063
AVDD = 5 V, number of devices = 30, ΔT = –40°C to +125°C
图 7-14. Reference Buffer Temperature Drift
图 7-13. Reference Buffer Output (REFCAP)
Histogram
Variation vs Supply and Temperature
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7.3.8 ADC Transfer Function
The device supports a pseudo-differential input supporting both bipolar and unipolar input ranges. The output of
the device is in straight-binary format for both bipolar and unipolar input ranges.
The ideal transfer characteristic for all input ranges is shown in 图 7-15. The full-scale range (FSR) for each input
signal is equal to the difference between the positive full-scale (PFS) input voltage and the negative full-scale
(NFS) input voltage. The LSB size is equal to FSR / 212. For a reference voltage of VREF = 4.096 V, the LSB
values corresponding to the different input ranges are listed in 表 7-4.
FFFh
800h
001h
FSR œ 1 LSB
1 LSB
FSR / 2
NFS
PFS
Analog Input
(AIN_P œ AIN_GND)
图 7-15. Device Transfer Function (Straight-Binary Format)
表 7-4. ADC LSB Values for Different Input Ranges (VREF = 4.096 V)
POSITIVE FULL-SCALE NEGATIVE FULL-SCALE
FULL-SCALE RANGE
(V)
INPUT RANGE
LSB
(V)
(V)
–12.288
–10.24
–6.144
–5.12
–2.56
0
±3 × VREF
±2.5 × VREF
12.288
10.24
6.144
5.12
24.576
20.48
12.288
10.24
5.12
6 mV
5 mV
±1.5 × VREF
3 mV
±1.25 × VREF
±0.625 × VREF
0 to 3 × VREF
0 to 2.5 × VREF
0 to 1.5 × VREF
0 to 1.25 × VREF
2.5 mV
1.25 mV
3 mV
2.56
12.288
10.24
6.144
5.12
12.288
10.24
6.144
5.12
0
2.5 mV
1.5 mV
1.25 mV
0
0
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7.3.9 Alarm Features
The device features an active-high alarm output on the ALARM/SDO-1/GPO pin, provided that the pin is
configured for alarm functionality. To enable the ALARM output on the multi-function pin, se the
SDO1_CONFIG[1:0] bits of the SDO_CTL_REG register to 01b (see the SDO_CTL_REG register).
The device features two types of alarm functions: an input alarm and an AVDD alarm.
• For the input alarm, the voltage at the input of the ADC is monitored and compared against user-
programmable high and low threshold values. The device sets an active high alarm output when the
corresponding digital value of the input signal goes beyond the high or low threshold set by the user; see the
Input Alarm section for a detailed explanation of the input alarm feature functionality.
• For the AVDD alarm, the analog supply voltage (AVDD) of the ADC is monitored and compared against the
specified typical low threshold (4.7 V) and high threshold (5.3 V) values of the AVDD supply. The device sets
an active high alarm output if the value of AVDD crosses the specified low (4.7 V) and high threshold (5.3 V)
values in either direction.
When the alarm functionality is turned on, both the input and AVDD alarm functions are enabled by default.
These alarm functions can be selectively disabled by programming the IN_AL_DIS and VDD_AL_DIS bits
(respectively) of the RST_PWRCTL_REG register.
Each alarm (input alarm or AVDD alarm) has two types of alarm flags associated with it: the active alarm flag
and the tripped alarm flag. All the alarm flags can be read in the ALARM_REG register. Both flags are set when
the associated alarm is triggered. However while the active alarm is cleared at the end of the current ADC
conversion (and set again if the alarm condition persists), the tripped flag is cleared only after ALARM_REG is
read.
The ALARM output flags are updated internally at the end of every conversion. These output flags can be read
during any data frame that the user initiates by bringing the CONVST/CS signal to a low level.
The ALARM output flags can be read in three different ways: either via the ALARM output pin, by reading the
internal ALARM registers, or by appending the ALARM flags to the data output.
• A high level on the ALARM pin indicates an over- or undervoltage condition on AVDD or on the analog input
channel of the device. This pin can be wired to interrupt the host input.
• The internal ALARM flag bits in the ALARM_REG register are updated at the end of conversion. After
receiving an ALARM interrupt on the output pin, the internal alarm flag registers can be read to obtain more
details on the conditions that generated the alarm.
• The alarm output flags can be selectively appended to the data output bit stream (see the
DATAOUT_CTL_REG register for configuration details).
图 7-16 depicts a functional block diagram for the device alarm functionality.
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AVDD High Alarm
AVDD Low Alarm
Other Input Alarm
Input Alarm Threshold
+/-
Hysteresis
ALARM
Input Active Alarm Flag
+
ADC Output
S
R
Q
Q
Input Tripped Alarm Flag
Alarm Flag Read
ADCST Rising
(End of Conversion)
ADC
SDO
图 7-16. Alarm Functionality Schematic
7.3.9.1 Input Alarm
The device features a high and a low alarm on the analog input. The alarms corresponding to the input signal
have independently-programmable thresholds and a common hysteresis setting that can be controlled through
the ALARM_H_TH_REG and ALARM_L_TH_REG registers.
The device sets the input high alarm when the digital output exceeds the high alarm upper limit [high alarm
threshold (T)]. The alarm resets when the digital output is less than or equal to the high alarm lower limit [high
alarm (T) – H – 1). This function is shown in 图 7-17.
Similarly, the input low alarm is triggered when the digital output falls below the low alarm lower limit [low alarm
threshold (T)]. The alarm resets when the digital output is greater than or equal to the low alarm higher limit [low
alarm (T) + H + 1]. This function is shown in 图 7-18.
L_ALARM On
H_ALARM On
L_ALARM Off
H_ALARM Off
(T)
(T + H + 1)
ADC Output
(T)
ADC Output
(T œ H œ 1)
图 7-18. Low ALARM Hysteresis
图 7-17. High ALARM Hysteresis
7.3.9.2 AVDD Alarm
The device features a high and a low alarm on the analog voltage supply, AVDD. Unlike the input signal alarm,
the AVDD alarm has fixed trip points that are set by design. The device features an internal analog comparator
that constantly monitors the analog supply against the high and low threshold voltages. The high alarm is set if
AVDD exceeds a typical value of 5.3 V and the low alarm is asserted if AVDD drops below 4.7 V. This feature is
specially useful for debugging unusual device behavior caused by a glitch or brown-out condition on the analog
AVDD supply.
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7.4 Device Functional Modes
The device features the multiSPI digital interface for communication and data transfer between the device and
the host controller. The multiSPI interface supports many data transfer protocols that the host uses to exchange
data and commands with the device. The host can transfer data into the device using one of the standard SPI
modes. However, the device can be configured to output data in a number of ways to suit the application
demands of throughput and latency. The data output in these modes can be controlled either by the host or the
device, and the timing can either be system synchronous or source synchronous. For detailed explanation of the
supported data transfer protocols, see the Data Transfer Protocols section.
This section describes the main components of the digital interface module as well as supported configurations
and protocols. As shown in 图 7-19, the interface module is comprised of shift registers (both input and output),
configuration registers, and a protocol unit. During any particular data frame, data are transferred both into and
out of the device. As a result, the host always perceives the device as a 32-bit input-output shift register, as
shown in 图 7-19.
Interface Module
SDI
Output Register (Data and Flags from Device)
D31
D30
D1
MSB-1
B1
D0
MSB
B0
Unified Shift Register
LSB
B31
LSB+1
B30
SDO-0
ADC
RST
CONVST
Input Register
CS
Digital
Control
Logic
SCLK
Command Processor
ALARM/SDO-1/GPO
RVS
SCLK
Counter
Configuration Registers
图 7-19. Device Interface Module
The Pin Configuration and Functions section provides descriptions of the interface pins; the Data Transfer Frame
section details the functions of shift registers, the SCLK counter, and the command processor; the Data Transfer
Protocols section details supported protocols; and the Register Maps section explains the configuration registers
and bit settings.
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7.4.1 Host-to-Device Connection Topologies
The multiSPI interface and device configuration registers offer great flexibility in the ways a host controller can
exchange data or commands with the device. This section describes how to select the hardware connection
topology to meet different system requirements.
7.4.1.1 Single Device: All multiSPI Options
图 7-20 shows the pin connection between a host controller and a stand-alone device to exercise all options
provided by the multiSPI interface.
DVDD
Isolation
(Optional)
RST
CONVST/CS
SCLK
Host
Controller
Device
SDI
SDO-0
ALARM/SDO-1/GPO
RVS
图 7-20. All multiSPI Protocols Pin Configuration
7.4.1.2 Single Device: Standard SPI Interface
图 7-21 shows the minimum pin interface for applications using a standard SPI protocol.
DVDD
Isolation
(Optional)
(Optional)
RST
CONVST/CS
SCLK
Host
Controller
Device
SDI
SDO-0
ALARM/SDO-1/GPO
RVS
(Optional)
图 7-21. Standard SPI Protocol Pin Configuration
The CONVST/CS, SCLK, SDI, and SDO-0 pins constitute a standard SPI port of the host controller. The RST pin
can be tied to DVDD. The RVS pin can be monitored for timing benefits. The ALARM/SDO-1/GPO pin may not
have any external connection.
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7.4.1.3 Multiple Devices: Daisy-Chain Topology
A typical connection diagram showing multiple devices in a daisy-chain topology is shown in 图 7-22.
Host Controller
Device 1
Device 2
Device N
图 7-22. Daisy-Chain Connection Schematic
The CONVST/CS and SCLK inputs of all devices are connected together and controlled by a single CONVST/
CS and SCLK pin of the host controller, respectively. The SDI input pin of the first device in the chain (device 1)
is connected to the SDO-x pin of the host controller, the SDO-0 output pin of device 1 is connected to the SDI
input pin of device 2, and so forth. The SDO-0 output pin of the last device in the chain (device N) is connected
to the SDI pin of the host controller.
To operate multiple devices in a daisy-chain topology, the host controller must program the configuration
registers in each device with identical values. The devices must operate with a single SDO-0 output, using the
external clock with any of the legacy, SPI-compatible protocols for data read and data write operations. In the
SDO_CTL_REG register, bits 7-0 must be programmed to 00h.
All devices in the daisy-chain topology sample their analog input signals on the rising edge of the CONVST/CS
signal and the data transfer frame starts with a falling edge of the same signal. At the launch edge of the SCLK
signal, every device in the chain shifts out the MSB to the SDO-0 pin. On every SCLK capture edge, each device
in the chain shifts in data received on its SDI pin as the LSB bit of the unified shift register; see 图 7-19.
Therefore, in a daisy-chain configuration, the host controller receives the data of device N, followed by the data
of device N-1, and so forth (in MSB-first fashion). On the rising edge of the CONVST/CS signal, each device
decodes the contents in its unified and takes appropriate action.
For N devices connected in a daisy-chain topology, an optimal data transfer frame must contain 32 × N SCLK
capture edges (see 图 7-23). A shorter data transfer frame can result in an erroneous device configuration and
must be avoided. For a data transfer frame with > 32 × N SCLK capture edges, the host controller must
appropriately align the configuration data for each device before bringing CONVST/CS high.
The overall throughput of the system is proportionally reduced with the number of devices connected in a daisy-
chain topology.
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A typical timing diagram for three devices connected in a daisy-chain topology and using the SPI-00-S protocol
is shown in 图 7-23.
CONVST/CS
SCLK
1
2
31
Configuration Data: Device 3
B94 B65
32
33
Configuration Data: Device 2
B62 B33
34
63
64
65
66
Configuration Data: Device 1
B30 B1
Configuration Data: Device 2
B62 B33
Configuration Data: Device 3
B94 B65
Output Data: Device 1
{D30}1 {D1}1
95
96
{SDO}HOST
{SDI}1
B95
B64
B63
B32
B31
B0
{SDO-0}1
{SDI}2
{D31}1
{D31}2
{D31}3
{D30}1
{D1}1
{D0}1
{D0}2
{D0}3
B95
B94
B65
B64
{D0}1
{D0}2
B63
B95
B32
B64
{SDO-0}2
{SDI}3
{D30}2
Output Data: Device 3
{D30}3 {D1}3
{D1}2
{D31}1
{D31}2
{D30}1
Output Data: Device 2
{D30}2 {D1}2
{D1}1
{SDO-0}3
{SDI}HOST
{D31}1
{D0}1
图 7-23. Three Devices in Daisy-Chain Mode Timing Diagram
7.4.2 Device Operational Modes
As shown in 图 7-24, the device supports three functional states: RESET, ACQ, and CONV. The device state is
determined by the status of the CONVST/CS and RST control signals provided by the host controller.
Power-Up
ACQ
)
e
g
Ed
g
R
n
ST
si
i
R
(
(
R
S
i
si
n
C
/
n
R
g
Ed
o
ST
VST
rsi
ve
g
N
(
F
e
)
O
n
o
a
C
l
l
i
C
n
f
g
o
Ed
g
d
En
e
)
RST (Falling Edge)
CONV
RESET
图 7-24. Device Functional States
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7.4.2.1 RESET State
The device features an active-low RST pin that is an asynchronous digital input. In order to enter a RESET state,
the RST pin must be pulled low and kept low for the twl_RST duration (as specified in the Timing Requirements:
Asynchronous Reset table).
The device features two different types of reset functions: an application reset or a power-on reset (POR). The
functionality of the RST pin is determined by the state of the RSTn_APP bit in the RST_PWRCTL_REG register.
• In order to configure the RST pin to issue an application reset, the RSTn_APP bit in the RST_PWRCTL_REG
register must be configured to 1b. In this RESET state, all configuration registers (see the Register Maps
section) are reset to their default values, the RVS pins remain low, and the SDO-x pins are tri-stated.
• The default configuration for the RST pin is to issue a power-on reset when pulled to a low level. The
RSTn_APP bit is set to 0b in this state. When a POR is issued, all internal circuitry of the device (including
the PGA, ADC driver, and voltage reference) are reset. When the device comes out of the POR state, the
tD_RST_POR time duration must be allowed for (see the Timing Requirements: Asynchronous Reset table) in
order for the internal circuitry to accurately settle.
In order to exit any of the RESET states, the RST pin must be pulled high with CONVST/CS and SCLK held low.
After a delay of tD_RST_POR or tD_RST_APP (see the Timing Requirements: Asynchronous Reset table), the device
enters ACQ state and the RVS pin goes high.
To operate the device in any of the other two states (ACQ or CONV), the RST pin must be held high. With the
RST pin held high, transitions on the CONVST/CS pin determine the functional state of the device. A typical
conversion cycle is illustrated in 图 6-1.
7.4.2.2 ACQ State
In ACQ state, the device acquires the analog input signal. The device enters ACQ state on power-up, after any
asynchronous reset, or after the end of every conversion.
The falling edge of the RST falling edge takes the device from an ACQ state to a RESET state. A rising edge of
the CONVST/CS signal takes the device from ACQ state to a CONV state.
The device offers a low-power NAP mode to reduce power consumption in the ACQ state; see the NAP Mode
section for more details on NAP mode.
7.4.2.3 CONV State
The device moves from ACQ state to CONV state on the rising edge of the CONVST/CS signal. The conversion
process uses an internal clock and the device ignores any further transitions on the CONVST/CS signal until the
ongoing conversion is complete (that is, during the time interval of tconv).
At the end of conversion, the device enters ACQ state. The cycle time for the device is given by 方程式 1:
tcycle-min = tconv + tacq-min
(1)
Note
The conversion time, tconv, can vary within the specified limits of tconv_min and tconv_max (as specified in
the Timing Requirements: Conversion Cycle table). After initiating a conversion, the host controller
must monitor for a low-to-high transition on the RVS pin or wait for the tconv_max duration to elapse
before initiating a new operation (data transfer or conversion). If RVS is not monitored, substitute tconv
in 方程式 1 with tconv_max
.
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7.5 Programming
The device features nine configuration registers (as described in the Register Maps section) and supports two
types of data transfer operations: data write (the host configures the device), and data read (the host reads data
from the device).
7.5.1 Data Transfer Frame
A data transfer frame between the device and the host controller begins at the falling edge of the CONVST/CS
pin and ends when the device starts conversion at the subsequent rising edge. The host controller can initiate a
data transfer frame by bringing the CONVST/CS signal low (as shown in 图 7-25) after the end of the CONV
phase, as described in the CONV State section.
Frame F
CONVST/CS
RVS
As per output protocol selection.
td_RVS
SCLK
N SCLKs
SDI
Valid Command
SDO-x
Data Output or OSR Contents
SCLK Counter
0
SCLK Counter
N
Output Data Word
Input Shift Register (ISR)
B31
D31
D0
D0
B0
D31
B31
B0
Output Shift Register (OSR)
Command Processor
图 7-25. Data Transfer Frame
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For a typical data transfer frame F:
1. The host controller pulls CONVST/CS low to initiate a data transfer frame. On the falling edge of the
CONVST/CS signal:
• RVS goes low, indicating the beginning of the data transfer frame.
• The internal SCLK counter is reset to 0.
• The device takes control of the data bus. As illustrated in 图 7-25, the contents of the output data word
are loaded into the 32-bit output shift register (OSR).
• The internal configuration register is reset to 0000h, corresponding to a NOP command.
2. During the frame, the host controller provides clocks on the SCLK pin:
• On each SCLK capture edge, the SCLK counter is incremented and the data bit received on the SDI pin
is shifted into the LSB of the input shift register.
• On each launch edge of the output clock (SCLK in this case), the MSB of the output shift register data is
shifted out on the selected SDO-x pins.
• The status of the RVS pin depends on the output protocol selection (see the Protocols for Reading From
the Device section).
3. The host controller pulls the CONVST/CS pin high to end the data transfer frame. On the rising edge of
CONVST/CS:
• The SDO-x pins go to tri-state.
• As illustrated in 图 7-25, the contents of the input shift register are transferred to the command processor
for decoding and further action.
• RVS output goes low, indicating the beginning of conversion.
After pulling CONVST/CS high, the host controller must monitor for a low-to-high transition on the RVS pin or
wait for the tconv_max time (see the Timing Requirements: Conversion Cycle table) to elapse before initiating a
new data transfer frame.
At the end of the data transfer frame F:
• If the SCLK counter = 32, then the device treats the frame F as an optimal data transfer frame for any read or
write operation. At the end of an optimal data transfer frame, the command processor treats the 32-bit
contents of the input shift register as a valid command word.
• If the SCLK counter is < 32, then the device treats the frame F as a short data transfer frame.
– The data write operation to the device in invalid and the device treats this frame as an NOP command.
– The output data bits transferred during a short frame on the SDO-x pins are still valid data. The host
controller can use the short data transfer frame to read only the required number of MSB bits from the 32-
bit output shift register.
• If the SCLK counter is > 32, then the device treats the frame F as a long data transfer frame. At the end of a
long data transfer frame, the command processor treats the 32-bit contents of the input shift register as a
valid command word. There is no restriction on the maximum number of clocks that can be provided within
any data transfer frame F. However, when the host controller provides a long data transfer frame, the last 32
bits shifted into the device prior to the CONVST/CS rising edge must constitute the desired command.
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7.5.2 Input Command Word and Register Write Operation
Any data write operation to the device is always synchronous to the external clock provided on the SCLK pin.
The device allows either one byte or two bytes (equivalent to half a word) to be read or written during any device
programming operation. 表 7-5 lists the input commands supported by the device. The input commands
associated with reading or writing two bytes in a single operation are suffixed as HWORD.
For any HWORD command, the LSB of the 9-bit address is always ignored and considered as 0b. For example,
regardless whether address 04h or 05h is entered for any particular HWORD command, the device always
exercises the command on address 04h.
表 7-5. List of Input Commands
OPCODE
B[31:0]
COMMAND
ACRONYM
COMMAND DESCRIPTION
00000000_000000000_
00000000_00000000
NOP
No operation
•
•
Command used to clear any (or a group of) bits of a register.
Any bit marked 1 in the data field results in that particular bit of the specified register being
reset to 0, leaving the other bits unchanged.
11000_xx_<9-bit address>_
<16-bit data>(1)
CLEAR_HWORD
•
•
Half-word command (that is, the command functions on 16 bits at a time).
LSB of the 9-bit address is always ignored and considered as 0b.(2)
•
•
•
•
Command used to perform a 16-bit read operation.
Half-word command (that is, the device outputs 16 bits of register data at a time).
LSB of the 9-bit address is always ignored and considered as 0b.
11001_xx_<9-bit address>_
00000000_00000000
READ_HWORD
READ
Upon receiving this command, the device sends out 16 bits of the register in the next frame.
•
Same as the READ_HWORD except that only eight bits of the register (byte read) are
returned in the next frame.
01001_xx_<9-bit address>_
00000000_00000000
•
•
Half-word write command (two bytes of input data are written into the specified address).
LSB of the 9-bit address is always ignored and considered as 0b.
11010_00_<9-bit address>_
<16-bit data>
•
•
•
Half-word write command.
LSB of the 9-bit address is always ignored and considered as 0b.
With this command, only the MS byte of the 16-bit data word is written at the specified register
address. The LS byte is ignored.
11010_01_<9-bit address>_
<16-bit data>
WRITE
•
•
•
Half-word write command.
LSB of the 9-bit address is always ignored and considered as 0b.
With this command, only the LS byte of the 16-bit data word is written at the specified register
address. The MS byte is ignored.
11010_10_<9-bit address>_
<16-bit data>
•
•
Command used to set any (or a group of) bits of a register.
Any bit marked 1 in the data field results in that particular bit of the specified register being set
to 1, leaving the other bits unchanged.
11011_xx_<9-bit address>_
<16-bit data>
SET_HWORD
NOP
•
•
Half-word command (that is, the command functions on 16 bits at a time).
LSB of the 9-bit address is always ignored and considered as 0b.
All other input command combinations
No operation
(1) <9-bit address> is realized by adding a 0 at the MSB location followed by an 8-bit register address as defined in 表 7-10. The <9-bit
address> for register 0x04h is 0x0-0000-0100b.
(2) An HWORD command operates on a set of 16 bits in the register map that is usually identified as two registers of eight bits each. For
example, the command 11000_xx_<0_0000_0101><16-bit data> is treated the same as the command 11000_xx_<0_0000_0100><16-
bit data> for bits 15:0 of the RST_PWRCTL_REG register.
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All input commands (including the CLEAR_HWORD, WRITE, and SET_HWORD commands listed in 表 7-5)
used to configure the internal registers must be 32 bits long. If any of these commands are provided in a
particular data frame F, that command gets executed at the rising edge of the CONVST/CS signal.
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7.5.3 Output Data Word
The data read from the device can be synchronized to the external clock on the SCLK pin or to an internal clock
of the device by programming the configuration registers (see the Data Transfer Protocols section for details).
In any data transfer frame, the contents of the internal output shift register are shifted out on the SDO-x pins.
The output data for any frame (F+1) is determined by the command issued in frame F and the status of
DATA_VAL[2:0] bits:
• If the DATA_VAL[2:0] bits in the DATAOUT_CTL_REG register are set to 1xxb, then the output data word for
frame (F+1) contains fixed data pattern as described in the DATAOUT_CTL_REG register.
• If a valid READ command is issued in frame F, the output data word for frame (F+1) contains 8-bit register
data, followed by 0's.
• If a valid READ_HWORD command is issued in frame F, the output data word for frame (F+1) contains 16-bit
register data, followed by 0's.
• For all other combinations, the output data word for frame (F+1) contains the latest 12-bit conversion result.
Program the DATAOUT_CTL_REG register to append various data flags to the conversion result. The data
flags are appended as per following sequence:
1. DEVICE_ADDR[3:0] bits are appended if the DEVICE_ADDR_INCL bit is set to 1
2. AVDD ALARM FLAGS are appended if the VDD_ACTIVE_ALARM_INCL bit is set to 1
3. INPUT ALARM FLAGS are appended if the IN_ACTIVE_ALARM_INCL bit is set to 1
4. ADC INPUT RANGE FLAGS are appended if the RANGE_INCL bit is set to 1
5. PARITY bits are appended if the PAR_EN bit is set to 1
6. All the remaining bits in the 32-bit output data word are set to 0.
表 7-6 shows the output data word with all data flags enabled.
表 7-6. Output Data Word With All Data Flags Enabled
DEVICE_ADDR_INCL = 1b, VDD_ACTIVE_ALARM_INCL = 1b, IN_ACTIVE_ALARM_INCL = 1b, RANGE_INCL = 1b, and PAR_EN = 1b
D[31:20]
D[19:16]
D[15:14]
D[13:12]
D[11:8]
D[7:6]
D[5:0]
Conversion result
Device address
AVDD alarm flags Input alarm flags
ADC input range
Parity bits
000000b
表 7-7 shows output data word with only some of the data flags enabled.
表 7-7. Output Data Word With Only Some Data Flags Enabled
DEVICE_ADDR_INCL = 0b, VDD_ACTIVE_ALARM_INCL = 1b, IN_ACTIVE_ALARM_INCL = 0b, RANGE_INCL = 1b, and PAR_EN = 1b
D[31:20]
D[19:18]
D[17:14]
D[13:12]
D[11:0]
Conversion result
AVDD alarm flags
ADC input range
Parity bits
000000000000b
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7.5.4 Data Transfer Protocols
The device features a multiSPI interface that allows the host controller to operate at slower SCLK speeds and
still achieve the required cycle time with a faster response time.
• For any data write operation, the host controller can use any of the four legacy, SPI-compatible protocols to
configure the device, as described in the Protocols for Configuring the Device section.
• For any data read operation from the device, the multiSPI interface module offers the following options:
– Legacy, SPI-compatible protocol with a single SDO-x (see the Legacy, SPI-Compatible (SYS-xy-S)
Protocols with a Single SDO-x section)
– Legacy, SPI-compatible protocol with dual SDO-x (see the Legacy, SPI-Compatible (SYS-xy-S) Protocols
With Dual SDO-x section)
– ADC master clock or source-synchronous (SRC) protocol for data transfer (see the Source-Synchronous
(SRC) Protocols section)
7.5.4.1 Protocols for Configuring the Device
As described in 表 7-8, the host controller can use any of the four legacy, SPI-compatible protocols (SPI-00-S,
SPI-01-S, SPI-10-S, or SPI-11-S) to write data into the device.
表 7-8. SPI Protocols for Configuring the Device
SCLK POLARITY
(At CS Falling Edge)
SCLK PHASE
(Capture Edge)
PROTOCOL
SDI_CTL_REG
SDO_CTL_REG
DIAGRAM
SPI-00-S
SPI-01-S
SPI-10-S
SPI-11-S
Low
Low
High
High
Rising
Falling
Falling
Rising
00h
01h
02h
03h
00h
00h
00h
00h
图 7-26
图 7-26
图 7-27
图 7-27
On power-up or after coming out of any asynchronous reset, the device supports the SPI-00-S protocol for data
read and data write operations. To select a different SPI-compatible protocol, program the SDI_MODE[1:0] bits
in the SDI_CNTL_REG register. This first write operation must adhere to the SPI-00-S protocol. Any subsequent
data transfer frames must adhere to the newly-selected protocol. The SPI protocol selected by the configuration
of the SDI_MODE[1:0] is applicable to both read and write operations.
图 7-26 and 图 7-27 detail the four protocols using an optimal data frame; see the Timing Requirements: SPI-
Compatible Serial Interface table for associated timing parameters.
Note
As explained in the Data Transfer Frame section, a valid write operation to the device requires a
minimum of 32 SCLKs to be provided within a data transfer frame.
CONVST/CS
CONVST/CS
RVS
RVS
CPOL = 0
CPOL = 0
SCLK
SCLK
CPOL = 1
CPOL = 1
B31
B30
B29
B1
B0
SDI
SDI
B31
B30
B2
B1
B0
图 7-26. Standard SPI Timing Protocol (CPHA = 0,
图 7-27. Standard SPI Timing Protocol (CPHA = 1,
32 SCLK Cycles)
32 SCLK Cycles)
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7.5.4.2 Protocols for Reading From the Device
The protocols for the data read operation can be broadly classified into three categories:
1. Legacy, SPI-compatible protocols with a single SDO-x
2. Legacy, SPI-compatible protocols with dual SDO-x
3. ADC master clock or source-synchronous (SRC) protocol for data transfer
7.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols with a Single SDO-x
As shown in 表 7-9, the host controller can use any of the four legacy, SPI-compatible protocols (SPI-00-S,
SPI-01-S, SPI-10-S, or SPI-11-S) to read data from the device.
表 7-9. SPI Protocols for Reading From the Device
SCLK POLARITY
(At CS Falling
Edge)
SCLK PHASE
(Capture Edge)
MSB BIT
LAUNCH EDGE
PROTOCOL
SDI_CTL_REG
SDO_CTL_REG
DIAGRAM
SPI-00-S
SPI-01-S
SPI-10-S
SPI-11-S
Low
Low
High
High
Rising
Falling
Falling
Rising
CS falling
1st SCLK rising
CS falling
00h
01h
02h
03h
00h
00h
00h
00h
图 7-28
图 7-28
图 7-29
图 7-29
1st SCLK falling
On power-up or after coming out of any asynchronous reset, the device supports the SPI-00-S protocol for data
read and data write operations. To select a different SPI-compatible protocol for both the data transfer
operations:
1. Program the SDI_MODE[1:0] bits in the SDI_CTL_REG register. This first write operation must adhere to the
SPI-00-S protocol. Any subsequent data transfer frames must adhere to the newly-selected protocol.
2. Set the SDO_MODE[1:0] bits = 00b in the SDO_CTL_REG register.
Note
The SPI transfer protocol selected by configuring the SDI_MODE[1:0] bits in the SDI_CTL_REG
register determines the data transfer protocol for both write and read operations. Either data can be
read from the device using the selected SPI protocol by configuring the SDO_MODE[1:0] bits = 00b in
the SDO_CTL_REG register, or one of the SRC protocols can be selected for data read, as explained
in the Source-Synchronous (SRC) Protocols section.
When using any of the SPI-compatible protocols, the RVS output remains low throughout the data transfer
frame; see the Timing Requirements: SPI-Compatible Serial Interface table for associated timing parameters.
图 7-28 and 图 7-29 explain the details of the four protocols. As explained in the Data Transfer Frame section,
the host controller can use a short data transfer frame to read only the required number of MSB bits from the 32-
bit output data word.
If the host controller uses a long data transfer frame with SDO_CNTL_REG[7:0] = 00h, then the device exhibits
daisy-chain operation (see the Multiple Devices: Daisy-Chain Topology section).
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CONVST/CS
CONVST/CS
RVS
RVS
CPOL = 0
CPOL = 1
SCLK
CPOL = 0
CPOL = 1
SCLK
M
M-1
L+1
L
SDO-0
M-2
SDO-0
0
M
M-1
L+1
L
图 7-28. Standard SPI Timing Protocol
(CPHA = 0, Single SDO-x)
图 7-29. Standard SPI Timing Protocol
(CPHA = 1, Single SDO-x)
7.5.4.2.2 Legacy, SPI-Compatible (SYS-xy-S) Protocols With Dual SDO-x
The device provides an option to increase the SDO-x bus width from one bit (default, single SDO-x) to two bits
(dual SDO-x) when operating with any of the data transfer protocols. In order to operate the device in dual SDO
mode, the SDO1_CONFIG[1:0] bits in the SDO_CTL_REG register must be set to 11b. In this mode, the
ALARM/SDO-1/GPO pin functions as SDO-1.
In dual SDO mode, two bits of data are launched on the two SDO-x pins (SDO-0 and SDO-1) on every SCLK
launch edge, as shown in 图 7-30 and 图 7-31.
CONVST/CS
CONVST/CS
RVS
RVS
CPOL = 0
CPOL = 1
CPOL = 0
CPOL = 1
SCLK
SCLK
M
M-2
M-3
L+3
L+2
L+1
SDO-1
SDO-0
M-4
M-5
SDO-1
SDO-0
0
0
M
M-2
M-1
L+3
L+2
L+1
M-1
L
M-1
L
图 7-30. Standard SPI Timing Protocol
图 7-31. Standard SPI Timing Protocol
(CPHA = 0, Dual SDO-x)
(CPHA = 1, Dual SDO-x)
Note
For any particular SPI protocol, the device follows the same timing specifications for single and dual
SDO modes. The only difference is that the device requires half as many SCLK cycles to output the
same number of bits when in single SDO mode, thus reducing the minimum required SCLK frequency
for a certain sampling rate of the ADC.
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7.5.4.2.3 Source-Synchronous (SRC) Protocols
The multiSPI interface supports an ADC master clock or source-synchronous mode of data transfer between the
device and host controller. In this mode, the device provides an output clock that is synchronous with the output
data. Furthermore, the host controller can also select the output clock source and data bus width options in this
mode of operation. In all SRC modes of operation, the RVS pin provides the output clock, synchronous to the
device data output.
The SRC protocol allows the clock source (internal or external) and the width of the output bus to be configured,
similar to the SPI protocols.
7.5.4.2.3.1 Output Clock Source Options
The device allows the output clock on the RVS pin to be synchronous to either the external clock provided on the
SCLK pin or to the internal clock of the device. This selection is done by configuring the SSYNC_CLK bit, as
explained in the SDO_CTL_REG register. The timing diagram and specifications for operating the device with an
SRC protocol in external CLK mode are provided in 图 6-7 and the Timing Requirements: Source-Synchronous
Serial Interface (External Clock) table. The timing diagram and specifications for operating the device with an
SRC protocol in internal CLK mode are provided in 图 6-8 and the Timing Requirements: Source-Synchronous
Serial Interface (Internal Clock) table.
7.5.4.2.3.2 Output Bus Width Options
The device provides an option to increase the SDO-x bus width from one bit (default, single SDO-x) to two bits
(dual SDO-x) when operating with any of the SRC protocols. In order to operate the device in dual SDO mode,
the SDO1_CONFIG[1:0] bits in the SDO_CTL_REG register must be set to 11b. In this mode, the ALARM/
SDO-1/GPO pin functions as SDO-1.
Note
For any particular SRC protocol, the device follows the same timing specifications for single and dual
SDO modes. The only difference is that the device requires half as many clock cycles to output the
same number of bits when in single SDO mode, thus reducing the minimum required clock frequency
for a certain sampling rate of the ADC.
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7.6 Register Maps
7.6.1 Device Configuration and Register Maps
The device features nine configuration registers, mapped as described in 表 7-10. Each configuration registers is
comprised of four registers, each containing a data byte.
表 7-10. Configuration Registers Mapping
ADDRESS
00h
REGISTER NAME
DEVICE_ID_REG
RST_PWRCTL_REG
SDI_CTL_REG
REGISTER FUNCTION
Device ID register
04h
Reset and power control register
SDI data input control register
SDO-x data input control register
Output data control register
08h
0Ch
10h
SDO_CTL_REG
DATAOUT_CTL_REG
RANGE_SEL_REG
ALARM_REG
14h
Input range selection control register
ALARM output register
20h
24h
ALARM_H_TH_REG
ALARM_L_TH_REG
ALARM high threshold and hysteresis register
ALARM low threshold register
28h
7.6.1.1 DEVICE_ID_REG Register (address = 00h)
This register contains the unique identification numbers associated to a device that is used in a daisy-chain
configuration involving multiple devices.
图 7-17. DEVICE_ID_REG Register
31
15
30
14
29
13
28
Reserved
R-00h
27
26
25
24
23
22
Reserved
R-0000b
21
20
4
19
3
18
17
16
0
DEVICE_ADDR[3:0]
R/W-0000b
12
11
10
9
8
7
6
5
2
1
Reserved
R-0000h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -0, -1 = Condition after application reset;
LEGEND: -<0>, -<1> = Condition after power-on reset
Address for bits 7-0 = 00h
Address for bits 15-8 = 01h
Address for bits 23-16 = 02h
Address for bits 31-24 = 03h
表 7-11. DEVICE_ID_REG Register Field Descriptions
Bit
Field
Type
Reset
Description
31-24
23-20
19-16
Reserved
R
00h
Reserved. Reads return 00h.
Reserved. Reads return 0000b.
Reserved
R
0000b
0000b
DEVICE_ADDR[3:0](1)
R/W
These bits can be used to identify up to 16 different devices in a
system.
15-0
Reserved
R
0000h
Reserved. Reads return 0000h.
(1) These bits are useful in daisy-chain mode.
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7.6.1.2 RST_PWRCTL_REG Register (address = 04h)
This register controls the reset and power-down features offered by the converter.
Any write operation to the RST_PWRCTL_REG register must be preceded by a write operation with the register
address set to 05h and the register data set to 69h.
图 7-18. RST_PWRCTL_REG Register
31 30 29 28 27 26 25 24 23 22
21
20
19
18
17
16
Reserved
R-0000h
15 14 13 12 11 10
WKEY[7:0]
9
8
7
6
5
4
3
2
1
0
VDD_AL_
DIS
Reserved
R-00b
IN_AL_DIS
R/W-0b
Reserved
R-0b
RSTn_APP
R/W-<0>b
NAP_EN
R/W-<0>b
PWRDN
R/W-0b
R/W-00h
R/W-0b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -0, -1 = Condition after application reset;
LEGEND: -<0>, -<1> = Condition after power-on reset
Address for bits 7-0 = 04h
Address for bits 15-8 = 05h
Address for bits 23-16 = 06h
Address for bits 31-24 = 07h
表 7-12. RST_PWRCTL_REG Register Field Descriptions
Bit
Field
Type
Reset
0000h
00h
Description
31-16 Reserved
R
Reserved. Reads return 0000h.
15-8
WKEY[7:0]
R/W
This value functions as a protection key to enable writes to bits 5-0.
Bits are written only if WKEY is set to 69h first.
7-6
5
Reserved
R
00b
0b
Reserved. Reads return 00b
VDD_AL_DIS
R/W
0b = VDD alarm is enabled
1b = VDD alarm is disabled
4
IN_AL_DIS
R/W
0b
0b = Input alarm is enabled
1b = Input alarm is disabled
3
2
Reserved
R
0b
0b
Reserved. Reads return 0h.
RSTn_APP(1)
R/W
0b = RST pin functions as a POR class reset (causes full device
initialization)
1b = RST pin functions as an application reset (only user-programmed
modes are cleared)
1
0
NAP_EN(2)
PWRDN(2)
R/W
R/W
0b
0b
0b = Disables the NAP mode of the converter
1b = Enables the converter to enter NAP mode if CONVST/CS is held high
after the current conversion completes
0b = Puts the converter into active mode
1b = Puts the converter into power-down mode
(1) Setting this bit forces the RST pin to function as an application reset until the next power cycle.
(2) See the Electrical Characteristics table for details on the latency encountered when entering and exiting the associated low-power
mode.
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7.6.1.3 SDI_CTL_REG Register (address = 08h)
This register configures the protocol used for writing data to the device.
图 7-19. SDI_CTL_REG Register
31
15
30
14
29
13
28
27
26
25
24
Reserved
R-0000h
23
22
21
20
4
19
3
18
2
17
1
16
0
12
11
10
9
8
7
6
5
SDI_MODE
[1:0]
Reserved
R-00h
Reserved
R-000000b
R/W-<00>b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -0, -1 = Condition after application reset;
LEGEND: -<0>, -<1> = Condition after power-on reset
Address for bits 7-0 = 08h
Address for bits 15-8 = 09h
Address for bits 23-16 = 0Ah
Address for bits 31-24 = 0Bh
表 7-13. SDI_CTL_REG Register Field Descriptions
Bit
Field
Type
Reset
0000h
00h
Description
31-16 Reserved
R
Reserved. Reads return 0000h.
Reserved. Reads return 00h.
15-8
7-2
Reserved
R
Reserved
R
000000b Reserved. Reads return 000000b.
1-0
SDI_MODE[1:0]
R/W
00b
These bits select the protocol for reading from or writing to the device.
00b = Standard SPI with CPOL = 0 and CPHASE = 0
01b = Standard SPI with CPOL = 0 and CPHASE = 1
10b = Standard SPI with CPOL = 1 and CPHASE = 0
11b = Standard SPI with CPOL = 1 and CPHASE = 1
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7.6.1.4 SDO_CTL_REG Register (address = 0Ch)
This register controls the data protocol used to transmit data out from the SDO-x pins of the device.
图 7-20. SDO_CTL_REG Register
31
15
30
29
13
28
27
11
26
10
25
9
24
8
23
Reserved
R-0000h
7
22
6
21
5
20
4
19
3
18
2
17
1
16
0
14
12
SDO1_
CONFIG
[1:0]
SDO_
MODE[1:0]
Reserved
R-000b
GPO_VAL
R/W-0b
Reserved
R-00b
Reserved SSYNC_CLK
R-0b R/W-<0>b
Reserved
R-0h
R/W-00b
R/W-<0>b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -0, -1 = Condition after application reset;
LEGEND: -<0>, -<1> = Condition after power-on reset
Address for bits 7-0 = 0Ch
Address for bits 15-8 = 0Dh
Address for bits 23-16 = 0Eh
Address for bits 31-24 = 0Fh
表 7-14. SDO_CTL_REG Register Field Descriptions
Bit
Field
Type
Reset
0000h
000b
0b
Description
31-16 Reserved
15-13 Reserved
R
Reserved. Reads return 0h.
Reserved. Reads return 000b.
1-bit value for the output on the GPO pin.
Reserved. Reads return 00b.
R
12
GPO_VAL
R/W
R
11-10 Reserved
00b
9-8
SDO1_CONFIG[1:0]
R/W
00b
Two bits are used to configure ALARM/SDO-1/GPO:
00b = SDO-1 is always tri-stated; 1-bit SDO mode
01b = SDO-1 functions as ALARM; 1-bit SDO mode
10b = SDO-1 functions as GPO; 1-bit SDO mode
11b = SDO-1 combined with SDO-0 offers a 2-bit SDO mode
7
6
Reserved
R
0b
Reserved. Reads return 0b.
This bit controls the source of the clock selected for source-synchronous
transmission.
0b = External SCLK (no division)
SSYNC_CLK(1)
Reserved
R/W
R
0b
1b = Internal clock (no division)
5-2
0000b
Reserved. Reads return 0000b.
These bits control the data output modes of the device.
0xb = SDO mode follows the same SPI protocol as that used for SDI; see
the SDI_CTL_REG register
1-0
SDO_MODE[1:0]
R/W
00b
10b = Invalid configuration
11b = SDO mode follows the ADC master clock or source-synchronous
protocol
(1) This bit takes effect only in the ADC master clock or source-synchronous mode of operation.
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7.6.1.5 DATAOUT_CTL_REG Register (address = 10h)
This register controls the data output by the device.
图 7-21. DATAOUT_CTL_REG Register
31
30
29
28
27
26
25
Reserved
R-0000h
9
24
23 22 21 20
19
18 17 16
15
14
13
12
11
10
8
7
6
5
4
3
2
1
0
DEVICE_
Reserved ADDR_
INCL
VDD_ACTIVE_
ALARM_INCL[1:0]
IN_ACTIVE_
ALARM_INCL[1:0]
RANGE_
INCL
DATA_VAL
[2:0]
Reserved
R-0b
Reserved
R-0000b
PAR_EN
R-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-
<0>b
R/W-000b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -0, -1 = Condition after application reset;
LEGEND: -<0>, -<1> = Condition after power-on reset
Address for bits 7-0 = 10h
Address for bits 15-8 = 11h
Address for bits 23-16 = 12h
Address for bits 31-24 = 13h
表 7-15. DATAOUT_CTL_REG Register Field Descriptions
Bit
Field
Type
Reset
0000h
0b
Description
31-16 Reserved
R
Reserved. Reads return 0000h.
Reserved. Reads return 0b.
15
14
Reserved
R
DEVICE_ADDR_INCL
R/W
0b
Control to include the 4-bit DEVICE_ADDR register value in the
SDO-x output bit stream.
0b = Do not include the register value
1b = Include the register value
13-12 VDD_ACTIVE_ALARM_INCL[1:0]
11-10 IN_ACTIVE_ALARM_INCL[1:0]
R/W
R/W
00b
00b
Control to include the active VDD ALARM flags in the SDO-x output
bit stream.
00b = Do not include
01b = Include ACTIVE_VDD_H_FLAG
10b = Include ACTIVE_VDD_L_FLAG
11b = Include both flags
Control to include the active input ALARM flags in the SDO-x output
bit stream.
00b = Do not include
01b = Include ACTIVE_IN_H_FLAG
10b = Include ACTIVE_IN_L_FLAG
11b = Include both flags
9
8
Reserved
R
0b
0b
Reserved. Reads return 0h.
RANGE_INCL
R/W
Control to include the 4-bit input range setting in the SDO-x output bit
stream.
0b = Do not include the range configuration register value
1b = Include the range configuration register value
7-4
3
Reserved
R
0000b
0b
Reserved. Reads return 0000b.
0b = Output data does not contain parity information
1b = Two parity bits (ADC output and output data frame) are
appended to the LSBs of the output data
The ADC output parity bit reflects an even parity for the ADC output
bits only.
PAR_EN(1)
R/W
The output data frame parity bit reflects an even parity signature for
the entire output data frame, including the ADC output bits and any
internal flags or register settings. The ADC output parity bit is not
included in the frame parity bit computation.
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表 7-15. DATAOUT_CTL_REG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2-0
DATA_VAL[2:0]
R/W
000b
These bits control the data value output by the converter.
0xxb = Value output is the conversion data
100b = Value output is all 0's
101b = Value output is all 1's
110b = Value output is alternating 0's and 1's
111b = Value output is alternating 00's and 11's
(1) Setting this bit increases the length of the output data by two bits.
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7.6.1.6 RANGE_SEL_REG Register (address = 14h)
This register controls the configuration of the internal reference and input voltage ranges for the converter.
图 7-22. RANGE_SEL_REG Register
31
15
30
14
29
13
28
27
26
25
24
23
Reserved
R-0000h
7
22
21
20
19
3
18
17
16
0
12
11
10
9
8
6
5
4
2
1
Reser
ved
Reserved
R-00h
INTREF_ DIS
R/W-0b
Reserved
R-00b
RANGE_SEL[3:0]
R/W-<0000>b
R-0b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -0, -1 = Condition after application reset;
LEGEND: -<0>, -<1> = Condition after power-on reset
Address for bits 7-0 = 14h
Address for bits 15-8 = 15h
Address for bits 23-16 = 16h
Address for bits 31-24 = 17h
表 7-16. RANGE_SEL_REG Register Field Descriptions
Bit
Field
Type
Reset
0000h
00h
Description
31-16 Reserved
R
Reserved. Reads return 0000h.
Reserved. Reads return 00h.
Reserved. Reads return 0b.
15-8
Reserved
R
7
6
Reserved
R
0b
INTREF_DIS
R/W
0b
Control to disable the ADC internal reference.
0b = Internal reference is enabled
1b = Internal reference is disabled
5-4
3-0
Reserved
R
00b
Reserved. Reads return 00b.
RANGE_SEL[3:0]
R/W
0000b
These bits comprise the 4-bit register that selects the nine input ranges of
the ADC.
0000b = ±3 × VREF
0001b = ±2.5 × VREF
0010b = ±1.5 × VREF
0011b = ±1.25 × VREF
0100b = ±0.625 × VREF
1000b = 3 × VREF
1001b = 2.5 × VREF
1010b = 1.5 × VREF
1011b = 1.25 × VREF
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7.6.1.7 ALARM_REG Register (address = 20h)
This register contains the output alarm flags (active and tripped) for the input and AVDD alarm.
图 7-23. ALARM_REG Register
31
15
30
14
29 28
13 12
27
11
26
10
25 24
23
22
21
5
20
4
19 18 17
16
0
Reserved
R-0000h
7
9
8
6
3
2
1
ACTIVE_ ACTIVE_
VDD_L_F VDD_H_ Reserved
ACTIVE_ ACTIVE_
TRP_
TRP_
TRP_IN_ TRP_IN_
L_FLAG H_FLAG
OVW_
ALARM
IN_L_
FLAG
IN_H_ Reserved VDD_L_ VDD_H_
FLAG
Reserved
R-000b
LAG
FLAG
FLAG
FLAG
R-0b
R-0b
R-00b
R-0b
R-0b
R-00b
R-0b
R-0b
R-0b
R-0b
R-0b
LEGEND: R = Read only; -n = value after reset; -0, -1 = Condition after application reset; -<0>, -<1> = Condition after power-on reset
Address for bits 7-0 = 20h Address for bits 15-8 = 21h Address for bits 23-16 = 22h Address for bits 31-24 = 23h
表 7-17. ALARM_REG Register Field Descriptions
Bit
Field
Type
Reset
0000h
0b
Description
31-16 Reserved
R
Reserved. Reads return 0000h.
15
14
ACTIVE_VDD_L_FLAG
R
Active ALARM output flag for low AVDD voltage.
0b = No ALARM condition
1b = ALARM condition exists
ACTIVE_VDD_H_FLAG
R
0b
Active ALARM output flag for high AVDD voltage.
0b = No ALARM condition
1b = ALARM condition exists
13-12 Reserved
R
R
00b
0b
Reserved. Reads return 00b.
11
ACTIVE_IN_L_FLAG
Active ALARM output flag for high input voltage.
0b = No ALARM condition
1b = ALARM condition exists
10
ACTIVE_IN_H_FLAG
R
0b
Active ALARM output flag for low input voltage.
0b = No ALARM condition
1b = ALARM condition exists
9-8
7
Reserved
R
R
00b
0b
Reserved. Reads return 00b.
TRP_VDD_L_FLAG
Tripped ALARM output flag for low AVDD voltage.
0b = No ALARM condition
1b = ALARM condition exists
6
5
4
TRP_VDD_H_FLAG
TRP_IN_L_FLAG
TRP_IN_H_FLAG
R
R
R
0b
0b
0b
Tripped ALARM output flag for high AVDD voltage.
0b = No ALARM condition
1b = ALARM condition exists
Tripped ALARM output flag for high input voltage.
0b = No ALARM condition
1b = ALARM condition exists
Tripped ALARM output flag for low input voltage.
0b = No ALARM condition
1b = ALARM condition exists
3-1
0
Reserved
R
R
000b
0b
Reserved. Reads return 000b.
OVW_ALARM
Logical OR outputs all tripped ALARM flags.
0b = No ALARM condition
1b = ALARM condition exists
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7.6.1.8 ALARM_H_TH_REG Register (address = 24h)
This register controls the hysteresis and high threshold for the input alarm.
图 7-24. ALARM_H_TH_REG Register
31
15
30
14
29
28
27
26
25
24
23
22
21
20
Reserved
R-00h
19
18
2
17
1
16
0
INP_ALRM_HYST[7:0]
R/W-00h
13
12
11
10
9
8
7
6
5
4
3
INP_ALRM_HIGH_TH[15:0]
R/W-FFFFh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -0, -1 = Condition after application reset;
LEGEND: -<0>, -<1> = Condition after power-on reset
Address for bits 7-0 = 24h
Address for bits 15-8 = 25h
Address for bits 23-16 = 26h
Address for bits 31-24 = 27h
表 7-18. ALARM_H_TH_REG Register Field Descriptions
Bit
Field
Type
Reset
Description
31-24 INP_ALRM_HYST[7:0]
R/W
00h
INP_ALRM_HYST[7:6]: 2-bit hysteresis value for the input ALARM.
INP_ALRM_HYST[5:0] must be set to 000000b.
23-16 Reserved
R
00h
Reserved. Reads return 00h.
15-0
INP_ALRM_HIGH_TH[15:0]
R/W
FFFFh
Threshold for comparison is INP_ALRM_HIGH_TH[15:4].
INP_ALRM_HIGH_TH[3:0] must be set to 0000b.
7.6.1.9 ALARM_L_TH_REG Register (address = 28h)
This register controls the low threshold for the input alarm.
图 7-25. ALARM_L_TH_REG Register
31
15
30
14
29
13
28
12
27
11
26
25
24
Reserved
R-0000h
23
22
21
20
4
19
3
18
2
17
1
16
0
10
9
8
7
6
5
INP_ALRM_LOW_TH[15:0]
R/W-0000h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -0, -1 = Condition after application reset;
LEGEND: -<0>, -<1> = Condition after power-on reset
Address for bits 7-0 = 28h
Address for bits 15-8 = 29h
Address for bits 23-16 = 2Ah
Address for bits 31-24 = 2Bh
表 7-19. ALARM_L_TH_REG Register Field Descriptions
Bit
Field
Type
Reset
0000h
0000h
Description
32:16 Reserved
R
Reserved. Reads return 0000h.
15-0
INP_ALRM_LOW_TH[15:0]
R/W
Threshold for comparison is INP_ALRM_LOW_TH[15:4].
INP_ALRM_LOW_TH[3:0] must be set to 0000b.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The ADS866x is a fully-integrated data acquisition (DAQ) system based on a 12-bit successive approximation
(SAR) analog-to-digital converter (ADC). The device includes an integrated analog front-end (AFE) circuit to
drive the inputs of the ADC and an integrated precision reference with a buffer. As such, this device does not
require any additional external circuits for driving the reference or analog input pins of the ADC.
8.2 Typical Application
Isolation
Barrier
Local Power Supply
System Power Supply
Isolated
DC-DC
Converter
GND
IGND
VINP
SAR ADC
VINM
Input Signal
Digital Isolator
Digital Host
IGND
GND
GND
IGND
IGND
GND
The potential difference between IGND and GND can be as high as the barrier breakdown voltage (often thousands of volts).
图 8-1. 12-Bit Isolated DAQ System for High Common-Mode Rejection
8.2.1 Design Requirements
Design a 12-bit DAQ system for processing input signals up to ±12 V superimposed on large dc or ac common-
mode offsets relative to the ground potential of the system main power supply. The specific performance
requirements are as follows:
• Input signal: ±12-V amplitude signal of a 1-kHz frequency superimposed on a ±75-V common-mode with
frequency between dc and 15 kHz
• CMRR > 100 dB over stipulated common-mode frequency range
• SNR > 70 dB
• THD < –96 dB
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8.2.2 Detailed Design Procedure
The design uses galvanic isolation between the DAQ system inputs and main power supply to achieve extremely
high CMRR, as indicated by 图 8-1. The system not only tolerates large common-mode voltages beyond its
absolute maximum ratings but also delivers excellent performance largely independent of common-mode
amplitude and frequency (within the specified operating limits). The relevant performance characteristics are
illustrated in 图 8-7, 图 8-3, and 图 8-4.
The system performance requirements by itself can be easily satisfied by using the ADS866x. This device
simplifies system design because the ADS866x eliminates the need for designing a discrete high-performance
signal chain needed with most other SAR ADCs. In addition, the use of galvanic isolation has the following
system design implications:
• A local floating supply is needed to power the ADS866x because the device cannot load the system main
power supply
• A digital isolator is required to facilitate data transfer between the isolated ADS866x serial interface and the
digital host controller
The floating power supply can be realized as an isolated transformer-based, push-pull converter followed by a
rectifier and low-dropout (LDO) regulator to largely eliminate the ADC power-supply ripple by taking advantage
of the high PSRR provided by most LDOs. A schematic of this design is shown in 图 8-2.
Isolation
Barrier
Full-Wave Rectifier and
Smoothing Capacitor
LDO
VOUT
S2
VIN
S1
VIN
Isolated 5 V
Main Power Supply
(> 4.3 V)
D1
D2
CS
GND
IGND
Transformer
Driver
M
GND
IGND
IGND
GND
LDO
VOUT
IGND
GND
VIN
Isolated 3.3 V
1:NS (>1)
GND
IGND
Isolated Switching Power Supply
图 8-2. Isolated Power-Supply Design
Recommended components for the circuit shown in 图 8-2 are given below:
• The SN6501 transformer driver is selected for its low input voltage requirement, small form-factor, and the
flexibility offered for easily adjusting the system isolation voltage rating by substituting the transformer
• A miniature printed circuit board (PCB)-mount, center-tapped transformer with a gain > 1 maintains line
regulation at the LDO outputs
• Schottky rectifiers for minimal forward voltage drop
• Smoothing capacitor for sufficiently low ripple at the LDO input
• The TPS7A4901 LDOs for an ultra-low noise contribution relative to the ADS866x and high PSRR over a
wide frequency range to attenuate output ripple to levels below the LDO output noise level
With regard to the digital isolator, the ISO7640FM is recommended for the following reasons:
• Supports > a 50-MHz SCLK and the required logic levels for operating the ADS866x at the full throughput
• Quad-channel device that facilitates excellent delay-matching between critical interface signals for reliable
operation at high speed
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8.2.3 Application Curves
0
0
-40
-40
-80
-80
-120
-160
-120
-160
0
125
250 375
Frequency (kHz)
500
625
0
125
250 375
Frequency (kHz)
500
625
D700
D701
fSAMPLE = 1.25 MSPS, VIN = ±12 V, fIN = 1 kHz, VCM = 50 VDC
,
fSAMPLE = 1.25 Msps, VIN = ±12 V, fIN = 1 kHz, VCM = 155 VPP,
SINAD = 72 dB, THD = –102 dB
SINAD = 71.9 dB, THD = –102 dB
图 8-3. FFT Plot With a DC Common-Mode at
图 8-4. FFT Plot With an AC Common-Mode at
1.25 MSPS
1.25 MSPS
0
-40
0
-40
-80
-80
-120
-160
-120
-160
0
50
100 150
Frequency (kHz)
200
250
0
50
100 150
Frequency (kHz)
200
250
D702
D703
fSAMPLE = 500 kSPS, VIN = ±12 V, fIN = 1 kHz, VCM = 50 VDC
,
fSAMPLE = 500 kSPS, VIN = ±12 V, fIN = 1 kHz, VCM = 155 VPP,
SINAD = 72 dB, THD = –102 dB
SINAD = 71.9 dB, THD = –102 dB
图 8-5. FFT Plot With a DC Common-Mode at
图 8-6. FFT Plot With an AC Common-Mode at
500 kSPS
500 kSPS
160
150
140
130
120
110
100
90
80
20
100 1000
Common-Mode Signal Frequency (Hz)
1000020000
D200
图 8-7. Common-Mode Rejection Ratio vs Frequency
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9 Power Supply Recommendations
The device uses two separate power supplies: AVDD and DVDD. The internal circuits of the device operate on
AVDD and DVDD is used for the digital interface. AVDD and DVDD can be independently set to any value within
the permissible range.
9.1 Power Supply Decoupling
The AVDD supply pins must be decoupled with AGND by using a minimum 10-µF and 1-µF capacitor on each
supply. Place the 1-µF capacitor as close to the supply pins as possible. Place a minimum 10-µF decoupling
capacitor very close to the DVDD supply to provide the high-frequency digital switching current. The effect of
using the decoupling capacitor is illustrated in the difference between the power-supply rejection ratio (PSRR)
performance of the device. 图 9-1 shows the PSRR of the device without using a decoupling capacitor. The
PSRR improves when the decoupling capacitors are used, as shown in 图 9-2.
-30
-40
-50
-60
-70
-80
-50
12.288 V
10.24 V
6.144 V
5.12 V
2.56 V
0-12.288 V
0-10.24 V
0-6.144 V
0-5.12 V
12.288 V
10.24 V
6.144 V
5.12 V
2.56 V
0-12.288 V
0-10.24 V
0-6.144 V
0-5.12 V
-60
-70
-80
-90
-100
100
1k
10k
100k
100
1k
10k
100k
Input Frequency (Hz)
Input Frequency (Hz)
D056
D057
图 9-2. PSRR With a Decoupling Capacitor
图 9-1. PSRR Without a Decoupling Capacitor
9.2 Power Saving
In normal mode of operation, the device does not power down between conversions, and therefore achieves
high throughput.However, the device offers two programmable low-power modes: NAP and power-down (PD) to
reduce power consumption when the device is operated at lower throughput rates.
9.2.1 NAP Mode
In NAP mode, the internal blocks of the device are placed into a low-power mode to reduce the overall power
consumption of the device in the ACQ state.
To enable NAP mode:
• Write 69h to register address 05h to unlock the RST_PWRCTL_REG register.
• The NAP_EN bit in the RST_PWRCTL_REG register must be set to 1b. The CONVST/CS pin must be kept
high at the end of the conversion process. The device then enters NAP mode at the end of conversion and
remains in NAP mode as long as the CONVST/CS pin is held high.
A falling edge on the CONVST/CS brings the device out of NAP mode; however, the host controller can initiate a
new conversion (CONVST/CS rising edge) only after the tNAP_WKUP time has elapsed (see the Timing
Requirements: Asynchronous Reset table).
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9.2.2 Power-Down (PD) Mode
The device also features a deep power-down mode (PD) to reduce the power consumption at very low
throughput rates.
The following steps must be taken to enter PD mode:
1. Write 69h to register address 05h to unlock the RST_PWRCTL_REG register.
2. Set the PWRDN bit in the RST_PWRCTL_REG register to 1b. The device enters PD mode on the rising
edge of the CONVST/CS signal.
In PD mode, all analog blocks within the device are powered down; however, the interface remains active and
the register contents are also retained. The RVS pin is high, indicating that the device is ready to receive the
next command.
In order to exit PD mode:
1. Clear the PWRDN bit in the RST_PWRCTL_REG register to 0b.
2. The RVS pin goes high, indicating that the device has started coming out of PD mode. However, the host
controller must wait for the tPWRUP time (see the Timing Requirements: Asynchronous Reset table) to elapse
before initiating a new conversion.
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10 Layout
10.1 Layout Guidelines
图 10-1 illustrates a PCB layout example for the ADS866x.
• Partition the PCB into analog and digital sections. Care must be taken to ensure that the analog signals are
kept away from the digital lines. This layout helps keep the analog input and reference input signals away
from the digital noise. In this layout example, the analog input and reference signals are routed on the lower
side of the board and the digital connections are routed on the top side of the board.
• Using a single dedicated ground plane is strongly encouraged.
• Power sources to the ADS866x must be clean and well-bypassed. Using a 1-μF, X7R-grade, 0603-size
ceramic capacitor with at least a 10-V rating in close proximity to the analog (AVDD) supply pins is
recommended. For decoupling the digital supply pin (DVDD), a 1-μF, X7R-grade, 0603-size ceramic
capacitor with at least a 10-V rating is recommended. Placing vias between the AVDD, DVDD pins and the
bypass capacitors must be avoided. All ground pins must be connected to the ground plane using short, low-
impedance paths.
• There are two decoupling capacitors used for the REFCAP pin. The first is a small, 1-μF, 0603-size ceramic
capacitor placed close to the device pins for decoupling the high-frequency signals and the second is a
10-μF, 0805-size ceramic capacitor to provide the charge required by the reference circuit of the device. A
capacitor with an ESR less than 0.2 Ω is recommended for the 10-μF capacitor. Both of these capacitors
must be directly connected to the device pins without any vias between the pins and capacitors.
• The REFIO pin also must be decoupled with a minimum of 4.7-μF ceramic capacitor if the internal reference
of the device is used. The capacitor must be placed close to the device pins.
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10.2 Layout Example
GND
External
Reference
DVDD
AVDD
1µF
1µF
GND
DVDD
4.7 µF
16
AVDD
RVS
2
GND
ALARM/SDO-1/GPO
GND
REFIO
REFGND
REFCAP
SDO-0
SCLK
4
5
6
1µF
CONVST/CS
SDI
10 µF
GND
RST
Analog Input
GND
Optional
图 10-1. Board Layout for the ADS866x
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, OPA320 Precision, 20MHz, 0.9pA, Low-Noise, RRIO, CMOS Operational Amplifier with
Shutdown data sheet
• Texas Instruments, SN6501 Transformer Driver for Isolated Power Supplies data sheet
• Texas Instruments, TPS7A49 36-V, 150-mA, Ultralow-Noise, Positive Linear Regulator data sheet
• Texas Instruments, ISO764xFM Low-Power Quad-Channel Digital Isolators data sheet
• Texas Instruments, AN-2029 Handling and Process Recommendations application report
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
™ and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 静电放电警告
静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS8661IPW
ADS8661IPWR
ADS8665IPW
ADS8665IPWR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
16
16
16
16
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
ADS8661
2000 RoHS & Green
90 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
ADS8661
ADS8665
ADS8665
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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5-Feb-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS8661IPWR
ADS8665IPWR
TSSOP
TSSOP
PW
PW
16
16
2000
2000
330.0
330.0
12.4
12.4
6.9
6.9
5.6
5.6
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS8661IPWR
ADS8665IPWR
TSSOP
TSSOP
PW
PW
16
16
2000
2000
367.0
367.0
367.0
367.0
35.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ADS8661IPW
ADS8665IPW
PW
PW
TSSOP
TSSOP
16
16
90
90
530
530
10.2
10.2
3600
3600
3.5
3.5
Pack Materials-Page 3
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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