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ADS8684A, ADS8688A

ZHCSDW1 –JULY 2015

ADS868xA 支持双极输入范围的 16 位 500kSPS 4 和 8 通道、单电源

SAR ADC

1 特性

2 应用

1

•

具有集成模拟前端的 16 位模数转换器 (ADC)

•

电力自动化

•

具有自动和手动扫描功能的 4 通道、8 通道多路复

用器

保护中继器

PLC 模拟输入模块

•

通道独立可编程输入：

3 说明

–

±10.24V、±5.12V、±2.56V、±1.28V、±0.64V

10.24V、5.12V、2.56V、1.28V

ADS8684A 和 ADS8688A 是基于 16 位逐次逼近寄存

器 (SAR) 模数转换器 (ADC) 的 4 通道、8 通道集成数

据采集系统，工作吞吐量达 500kSPS。这些器件提供

了用于各输入通道的集成模拟前端电路（过压保护高达

±20V）、支持自动和手动两种扫描模式的 4 通道或 8

通道多路复用器、以及低温度漂移的片上 4.096V 基准

电压。这些器件由单个 5V 模拟电源供电，每个输入

通道均可支持真正的双极输入范围（（±10.24V、

±5.12V、±2.56V、±1.28V 和 ±0.64V）和单极输入范

围（0V 至 10.24V、0V 至 5.12V、0V 至 2.56V 以及

0V 至 1.28V）。模拟前端在所有输入范围内的增益均

经过了精确调整，以确保高直流精度。输入范围的选

择可通过软件进行编程，各通道输入范围的选择相互独

立。该器件提供了一个 1MΩ 的恒定阻性输入阻抗

（无论所选输入范围为何）。

•

5V 模拟电源：1.65V 到 5V I/O 电源

恒定的阻性输入阻抗：1MΩ

输入过压保护：高达 ±20V

低漂移的片上 4.096V 基准电压

出色的性能：

–

500kSPS 的总吞吐量

差分非线性 (DNL)：±0.5 最低有效位 (LSB)；

最大积分非线性 (INL)：±0.75 LSB

–

增益误差和偏移误差的漂移均较低

信噪比 (SNR)：92dB；总谐波失真

(THD)：–102dB

–

低功耗：65mW

•

AUX 输入 → 直接连接到 ADC 输入

ALARM → 每通道的高低阈值

SPI™- 兼容接口，支持菊花链连接

工业温度范围：-40°C 至 125°C

TSSOP-38 封装 (9.7mm × 4.4mm)

ADS8684A 和 ADS8688A 为数字主机提供了一个兼容

串行外设接口 (SPI) 的简单串行接口，同时支持以菊花

链方式连接多个器件。数字电源可提供 1.65V 到

5.25V 范围内的电压，因此可直接连接各种主机控制

器。

框图

DVDD

AVDD

1

M:

ADS8688A

ADS8684A

OVP

AIN_0P

AIN_0GND

2nd-Order

LPF

ADC

Driver

PGA

器件信息⁽¹⁾

1

M:

V_B0

器件型号

ADS868xA

封装

封装尺寸（标称值）

OVP

AIN_1P

AIN_1GND

2nd-Order

LPF

ADC

Driver

1

M:

V_B1

TSSOP (38)

9.70mm x 4.40mm

OVP

AIN_2P

AIN_2GND

Digital

Logic

and

2nd-Order

LPF

ADC

Driver

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

1

M:

CS

V_B2

Interface

SCLK

SDI

OVP

AIN_3P

AIN_3GND

2nd-Order

LPF

ADC

Driver

增益误差与温度的关系曲线

1

M:

V_B3

0.05

SDO

OVP

AIN_4P

AIN_4GND

16-Bit

SAR ADC

2nd-Order

LPF

ADC

Driver

---- ± 2.5*V_REF,---- 1.25*V_REF

---- 0.625*V_REF,------0.3125*V_REF

DAISY

REFSEL

RST / PD

1

M:

V_B4

-------0.156 V_REF,---- + 2.5*V_REF

---- + 1.25*V_REF,---- + 0.625*V_REF

---- + 0.3125*V_REF

0.03

0.01

OVP

AIN_5P

AIN_5GND

2nd-Order

LPF

ADC

Driver

Oscillator

1

M:

V_B5

ALARM

REFCAP

REFIO

OVP

AIN_6P

AIN_6GND

2nd-Order

LPF

ADC

Driver

1

M:

V_B6

-0.01

-0.03

-0.05

OVP

AIN_7P

AIN_7GND

2nd-Order

LPF

ADC

Driver

4.096-V

Reference

1

M:

V_B7

AUX_IN

AUX_GND

AGND

DGND

REFGND

26

59

92

125

±40

±7

Free-Air Temperature (^oC)

C039

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SBAS680

ADS8684A, ADS8688A

ZHCSDW1 –JULY 2015

www.ti.com.cn

8.4 Device Functional Modes........................................ 37

8.5 Register Maps......................................................... 50

Application and Implementation ........................ 66

9.1 Application Information............................................ 66

9.2 Typical Applications ................................................ 66

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 6

7.6 Timing Requirements: Serial Interface.................... 11

7.7 Typical Characteristics............................................ 12

Detailed Description ............................................ 23

8.1 Overview ................................................................. 23

8.2 Functional Block Diagram ....................................... 23

8.3 Feature Description................................................. 24

9

10 Power-Supply Recommendations ..................... 69

11 Layout................................................................... 70

11.1 Layout Guidelines ................................................. 70

11.2 Layout Example .................................................... 71

12 器件和文档支持 ..................................................... 72

12.1 文档支持................................................................ 72

12.2 相关链接................................................................ 72

12.3 社区资源................................................................ 72

12.4 商标....................................................................... 72

12.5 静电放电警告......................................................... 72

12.6 Glossary................................................................ 72

13 机械、封装和可订购信息....................................... 73

8

4 修订历史记录

日期

修订版本

注释

2014 年 7 月

*

首次发布。

2

ADS8684A, ADS8688A

www.ti.com.cn

ZHCSDW1 –JULY 2015

5 Device Comparison Table

PRODUCT

ADS8684A

ADS8688A

RESOLUTION (Bits)

CHANNELS

4, single-ended

8, single-ended

SAMPLE RATE (kSPS)

16

500

6 Pin Configuration and Functions

DBT Package

38-Pin TSSOP

Top View (Not to Scale)

38

37

36

35

38

37

36

35

SDI

1

2

3

4

5

6

7

8

9

CS

SDI

1

2

3

4

5

6

7

8

9

CS

RST/PD

SCLK

SDO

RST/PD

SCLK

SDO

DAISY

REFSEL

REFIO

DAISY

REFSEL

REFIO

ALARM

34 DVDD

33

REFGND

REFCAP

AGND

REFGND

REFCAP

AGND

DGND

32

AGND

31 AGND

30 AVDD

31 AGND

30 AVDD

AVDD

ADS8684A

ADS8688A

AUX_IN 10

29

28

27

26

25

24

23

22

21

20

AGND

NC

AUX_IN 10

29

28

27

26

25

24

23

22

21

20

AGND

11

12

13

14

15

11

12

13

14

15

AUX_GND

NC

AUX_GND

AIN_6P

AGND

AIN_5P

AIN_5GND

NC

AIN_6GND

AIN_7P

NC

AIN_4P

NC

AIN_7GND

AIN_4GND

AIN_3P

AIN_0P

AIN_0GND

AIN_1P

AIN_0P

AIN_0GND

AIN_1P

16

17

18

19

16

17

18

19

AIN_3GND

AIN_2P

AIN2_GND

AIN_1GND

Pin Functions

NAME

I/O

DESCRIPTION

NO.

ADS8684A

ADS8688A

1

SDI

Digital input

Data input for serial communication.

Active low logic input.

2

3

RST/PD

DAISY

Dual functionality to reset or power-down the device.

Chain the data input during serial communication in daisy-chain mode.

Active low logic input to enable the internal reference.

When low, the internal reference is enabled;

4

REFSEL

Digital input

REFIO becomes an output that includes the V_REFvoltage.

When high, the internal reference is disabled;

REFIO becomes an input to apply the external V_REFvoltage.

5

6

REFIO

Analog input, output Internal reference output and external reference input pin. Decouple with REFGND on pin 6.

Reference GND pin; short to the analog GND plane.

Power supply

REFGND

Decouple with REFIO on pin 5 and REFCAP on pin 7.

7

REFCAP

AGND

Analog output

Power supply

Analog input

ADC reference decoupling capacitor pin. Decouple with REFGND on pin 6.

Analog ground pin. Decouple with AVDD on pin 9.

8

9

AVDD

Analog supply pin. Decouple with AGND on pin 8.

10

11

AUX_IN

AUX_GND

Auxiliary input channel: positive input. Decouple with AUX_GND on pin 11.

Auxiliary input channel: negative input. Decouple with AUX_IN on pin 10.

3

ADS8684A, ADS8688A

ZHCSDW1 –JULY 2015

www.ti.com.cn

Pin Functions (continued)

NAME

NO.

I/O

DESCRIPTION

ADS8684A

ADS8688A

Analog input channel 6, positive input. Decouple with AIN_6GND on pin 13.

No connection for the ADS8684A; this pin can be left floating or connected to AGND.

12

13

14

15

NC

AIN_6P

AIN_6GND

AIN_7P

Analog input

Analog input channel 6, negative input. Decouple with AIN_6P on pin 12.

No connection for the ADS8684A; this pin can be left floating or connected to AGND.

NC

Analog input channel 7, positive input. Decouple with AIN_7GND on pin 15.

No connection for the ADS8684A; this pin can be left floating or connected to AGND.

Analog input channel 7, negative input. Decouple with AIN_7P on pin 14.

No connection for the ADS8684A; this pin can be left floating or connected to AGND.

AIN_7GND

16

17

18

19

20

21

22

23

AIN_0P

Analog input

Analog input channel 0, positive input. Decouple with AIN_0GND on pin 17.

Analog input channel 0, negative input. Decouple with AIN_0P on pin 16.

Analog input channel 1, positive input. Decouple with AIN_1GND on pin 19.

Analog input channel 1, negative input. Decouple with AIN_1P on pin 18.

Analog input channel 2, negative input. Decouple with AIN_2P on pin 21.

Analog input channel 2, positive input. Decouple with AIN_2GND on pin 20.

Analog input channel 3, negative input. Decouple with AIN_3P on pin 23.

Analog input channel 3, positive input. Decouple with AIN_3GND on pin 22.

AIN_0GND

AIN_1P

AIN_1GND

AIN2_GND

AIN_2P

AIN_3GND

AIN_3P

Analog input channel 4, negative input. Decouple with AIN_4P on pin 25.

No connection for the ADS8684A; this pin can be left floating or connected to AGND.

24

25

26

27

NC

AIN_4GND

Analog input

Analog input channel 4, positive input. Decouple with AIN_4GND on pin 24.

No connection for the ADS8684A; this pin can be left floating or connected to AGND.

AIN_4P

AIN_5GND

AIN_5P

Analog input channel 5, negative input. Decouple with AIN_5P on pin 27.

No connection for the ADS8684A; this pin can be left floating or connected to AGND.

Analog input channel 5, positive input. Decouple with AIN_5GND on pin 26.

No connection for the ADS8684A; this pin can be left floating or connected to AGND.

28

29

30

31

32

33

34

35

36

37

38

AGND

AVDD

AGND

DGND

DVDD

Power supply

Digital output

Digital input

Analog ground pin

Analog supply pin. Decouple with AGND on pin 31.

Analog ground pin. Decouple with AVDD on pin 30.

Analog ground pin

Digital ground pin. Decouple with DVDD on pin 34.

Digital supply pin. Decouple with DGND on pin 33.

Active high alarm output

ALARM

SDO

Data output for serial communication

Clock input for serial communication

Active low logic input; chip-select signal

SCLK

CS

Digital input

4

ADS8684A, ADS8688A

www.ti.com.cn

ZHCSDW1 –JULY 2015

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–20

MAX

UNIT

V

AIN_nP, AIN_nGND to GND⁽²⁾

AIN_nP, AIN_nGND to GND⁽³⁾

AUX_GND to GND

20

–11

11

V

–0.3

–40

0.3

AVDD + 0.3

7

V

AUX_IN to GND

V

AVDD to GND or DVDD to GND

REFCAP to REFGND or REFIO to REFGND

GND to REFGND

V

5.7

V

0.3

V

Digital input pins to GND

Digital output pins to GND

Operating temperature, T_A

Storage temperature, T_stg

DVDD + 0.3

125

V

°C

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) AVDD = 5 V or offers a low impedance of < 30 kΩ.

(3) AVDD = floating with an impedance > 30 kΩ.

7.2 ESD Ratings

VALUE

UNIT

Analog input pins

(AIN_nP; AIN_nGND)

±4000

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Electrostatic

discharge

V_(ESD)

V

All other pins

±2000

±500

Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.75

1.65

NOM

5

MAX

UNIT

AVDD

DVDD

Analog supply voltage

Digital supply voltage

5.25

V

3.3

AVDD

7.4 Thermal Information

ADS8684A,

ADS8688A

DBT (TSSOP)

38 PINS

68.8

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

19.9

30.4

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.3

ψ_JB

29.8

R_θJC(bot)

NA

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

5

ADS8684A, ADS8688A

ZHCSDW1 –JULY 2015

www.ti.com.cn

7.5 Electrical Characteristics

Minimum and maximum specifications are at T_A= –40°C to 125°C. Typical specifications are at T_A= 25°C.

AVDD = 5 V, DVDD = 3 V, V_REF= 4.096 V (internal), and f_SAMPLE= 500 kSPS, unless otherwise noted.

TEST

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LEVEL⁽¹⁾

ANALOG INPUTS

Input range = ±2.5 × V_REF

Input range = ±1.25 × V_REF

Input range = ±0.625 × V_REF

–2.5 × V_REF

–1.25 × V_REF

–0.625 × V_REF

2.5 × V_REF

1.25 × V_REF

0.625 × V_REF

A

–0.3125 ×

V_REF

Input range = ±0.3125 × V_REF

Input range = ±0.15625 × V_REF

0.3125 × V_REF

A

Full-scale input span⁽²⁾

(AIN_nP to AIN_nGND)

–0.15625 ×

V_REF

0.15625 ×

V_REF

V

Input range = 2.5 × V_REF

Input range = 1.25 × V_REF

Input range = 0.625 × V_REF

Input range = 0.3125 × V_REF

Input range = ±2.5 × V_REF

Input range = ±1.25 × V_REF

Input range = ±0.625 × V_REF

0

2.5 × V_REF

1.25 × V_REF

0.625 × V_REF

0.3125 × V_REF

2.5 × V_REF

A

0

–2.5 × V_REF

–1.25 × V_REF

–0.625 × V_REF

1.25 × V_REF

0.625 × V_REF

–0.3125 ×

V_REF

Input range = ±0.3125 × V_REF

Input range = ±0.15625 × V_REF

0.3125 × V_REF

A

Operating input range,

positive input

AIN_nP

–0.15625 ×

V_REF

0.15625 ×

V_REF

V

Input range = 2.5 × V_REF

Input range = 1.25 × V_REF

Input range = 0.625 × V_REF

Input range = 0.3125 × V_REF

0

2.5 × V_REF

1.25 × V_REF

A

0.625 × V_REF

0.3125 × V_REF

Operating input range,

negative input

AIN_nGND

All input ranges

–0.1

0.85

0

0.1

V

B

At T_A= 25°C,

all input ranges

z_i

Input impedance

1

7

1.15

MΩ

B

Input impedance drift

All input ranges

25 ppm/°C

V_IN– 2.25

————

R_IN

With voltage at AIN_nP pin = V_IN

input range = ±2.5 × V_REF

,

A

V_IN– 2.00

————

R_IN

With voltage at AIN_nP pin = V_IN

input range = ±1.25 × V_REF

,

With voltage at AIN_nP pin = V_IN

,

V_IN– 1.60

————

R_IN

I_Ikg(in)

Input leakage current

input ranges = ±0.625 × V_REF

;

µA

±0.3125 × V_REF; ±0.15625 × V_REF

V_IN– 2.50

————

R_IN

With voltage at AIN_nP pin = V_IN

,

input range = 2.5 × V_REF

With voltage at AIN_nP pin = V_IN

,

V_IN– 2.50

————

R_IN

input range = 1.25 × V_REF; 0.625 ×

V_REF; 0.3125 × V_REF

INPUT OVERVOLTAGE PROTECTION

AVDD = 5 V or offers low

impedance < 30 kΩ, all input ranges

–20

–11

20

B

V_OVP

Overvoltage protection voltage

V

AVDD = floating with impedance

> 30 kΩ, all input ranges

11

(1) Test Levels: (A) Tested at final test. Over temperature limits are set by characterization and simulation. (B) Limits set by characterization

and simulation, across temperature range. (C) Typical value only for information, provided by design simulation.

(2) Ideal input span, does not include gain or offset error.

6

ADS8684A, ADS8688A

www.ti.com.cn

ZHCSDW1 –JULY 2015

Electrical Characteristics (continued)

Minimum and maximum specifications are at T_A= –40°C to 125°C. Typical specifications are at T_A= 25°C.

AVDD = 5 V, DVDD = 3 V, V_REF= 4.096 V (internal), and f_SAMPLE= 500 kSPS, unless otherwise noted.

TEST

PARAMETER

SYSTEM PERFORMANCE

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LEVEL⁽¹⁾

Resolution

16

Bits

LSB⁽³⁾

A

NMC

DNL

INL

No missing codes

Differential nonlinearity

Integral nonlinearity⁽⁴⁾

Gain error

–0.99

–2

±0.5

±0.75

±0.02

1.5

2

LSB

±0.05 %FSR⁽⁵⁾

E_G

At T_A= 25°C, all input ranges

Gain error matching

(channel-to-channel)

±0.02

1

±0.05

4

%FSR

A

B

A

Gain error temperature drift

All input ranges

At T_A= 25°C,

ppm/°C

±0.5

±1

(6)

input range = ±2.5 × V_REF

At T_A= 25°C,

input range = ±1.25 × V_REF

±0.5

±1

±1.5

±2

A

At T_A= 25°C,

input range = ±0.625 × V_REF

E_O

Offset error

mV

At T_A= 25°C,

input range = ±0.3125 × V_REF

At T_A= 25°C,

input range = ±0.15625 × V_REF

At T_A= 25°C,

all unipolar input ranges

At T_A= 25°C,

input range = ±2.5 × V_REF

±1

(6)

At T_A= 25°C,

input range = ±1.25 × V_REF

±1

At T_A= 25°C,

input range = ±0.625 × V_REF

±1.5

±2

Offset error matching

(channel-to-channel)

mV

At T_A= 25°C,

input range = ±0.3125 × V_REF

At T_A= 25°C,

input range = ±0.15625 × V_REF

At T_A= 25°C,

all unipolar input ranges

Input range = ±2.5 × V_REF

1

2

4

1

2

4

3

6

B

Input range = ±1.25 × V_REF

Input range = ±0.625 × V_REF

Input range = ±0.3125 × V_REF

Input range = ±0.15625 × V_REF

Input range = 0 to 2.5 × V_REF

Input range = 0 to 1.25 × V_REF

Input range = 0 to 0.625 × V_REF

Input range = 0 to 0.3125 × V_REF

Offset error temperature drift

12 ppm/°C

3

6

12

SAMPLING DYNAMICS

t_CONVConversion time

t_ACQ

850

ns

A

Acquisition time

1150

Maximum throughput rate

without latency

f_S

500

kSPS

A

(3) LSB = least significant bit.

(4) This parameter is the endpoint INL, not best-fit INL.

(5) FSR = full-scale range.

(6) Does not include the shift in offset over time.

7

ADS8684A, ADS8688A

ZHCSDW1 –JULY 2015

www.ti.com.cn

Electrical Characteristics (continued)

Minimum and maximum specifications are at T_A= –40°C to 125°C. Typical specifications are at T_A= 25°C.

AVDD = 5 V, DVDD = 3 V, V_REF= 4.096 V (internal), and f_SAMPLE= 500 kSPS, unless otherwise noted.

TEST

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LEVEL⁽¹⁾

DYNAMIC CHARACTERISTICS

Input range = ±2.5 × V_REF

Input range = ±1.25 × V_REF

Input range = ±0.625 × V_REF

Input range = ±0.3125 × V_REF

Input range = ±0.15625 × V_REF

Input range = 2.5 × V_REF

90

89

92

91

A

87.5

81.5

75.5

88.5

87.5

81.5

75.5

89

83

Signal-to-noise ratio

SNR

77

dB

(V_IN– 0.5 dBFS at 1 kHz)

90.5

89

Input range = 1.25 × V_REF

Input range = 0.625 × V_REF

Input range = 0.3125 × V_REF

Input ranges = ±2.5 × V_REF, ±1.25 ×

83

77

V_REF, ±0.625 × V_REF, 2.5 × V_REF

1.25 × V_REF

,

-102

-100

Total harmonic distortion⁽⁷⁾

(V_IN– 0.5 dBFS at 1 kHz)

THD

B

Input ranges = ±0.3125 × V_REF

,

±0.15625 × V_REF, 0.625 × V_REF

0.3125 × V_REF

,

Input range = ±2.5 × V_REF

Input range = ±1.25 × V_REF

Input range = ±0.625 × V_REF

Input range = ±0.3125 × V_REF

Input range = ±0.15625 × V_REF

Input range = 2.5 × V_REF

89

88.5

87

91.5

91

A

89

81

83

Signal-to-noise ratio

SINAD

75

77

(V_IN– 0.5 dBFS at 1 kHz)

87.5

87

90.5

89

Input range = 1.25 × V_REF

Input range = 0.625 × V_REF

Input range = 0.3125 × V_REF

81

83

75

77

Input ranges = ±2.5 × V_REF, ±1.25 ×

V_REF, ±0.625 × V_REF, 2.5 × V_REF

1.25 × V_REF

,

103

101

Spurious-free dynamic range

SFDR

B

(V_IN– 0.5 dBFS at 1 kHz)

Input ranges = ±0.3125 × V_REF

,

±0.15625 × V_REF, 0.625 × V_REF

,

0.3125 × V_REF

Aggressor channel input overdriven

to 2 × maximum input voltage

Crosstalk isolation⁽⁸⁾

Crosstalk memory⁽⁹⁾

110

90

dB

B

Aggressor channel input overdriven

to 2 × maximum input voltage

BW_{(–3 dB)}

Small-signal bandwidth, –3 dB

Small-signal bandwidth, –0.1 dB

At T_A= 25°C, all input ranges

15

kHz

B

BW_{(–0.1 dB)}

2.5

(7) Calculated on the first nine harmonics of the input frequency.

(8) Isolation crosstalk is measured by applying a full-scale sinusoidal signal up to 10 kHz to a channel, not selected in the multiplexing

sequence, and measuring its effect on the output of any selected channel.

(9) Memory crosstalk is measured by applying a full-scale sinusoidal signal up to 10 kHz to a channel that is selected in the multiplexing

sequence, and measuring its effect on the output of the next selected channel for all combinations of input channels.

8

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ZHCSDW1 –JULY 2015

Electrical Characteristics (continued)

Minimum and maximum specifications are at T_A= –40°C to 125°C. Typical specifications are at T_A= 25°C.

AVDD = 5 V, DVDD = 3 V, V_REF= 4.096 V (internal), and f_SAMPLE= 500 kSPS, unless otherwise noted.

TEST

PARAMETER

AUXILIARY CHANNEL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LEVEL⁽¹⁾

Resolution

16

0

Bits

V

A

C

A

B

A

B

V_{(AUX_IN)}

AUX_IN voltage range

(AUX_IN – AUX_GND)

V_REF

AUX_IN

0

V

Operating input range

Input capacitance

AUX_GND

0

75

V

During sampling

During conversion

pF

C_i

5

pF

I_Ikg(in)

DNL

Input leakage current

Differential nonlinearity

Integral nonlinearity

Gain error

100

±0.6

±1.5

±0.02

nA

–0.99

–4

1.5

4

LSB

%FSR

mV

dB

INL

E_G(AUX)

E_O(AUX)

SNR

At T_A= 25°C

±0.2

5

Offset error

At T_A= 25°C

–5

87

Signal-to-noise ratio

Total harmonic distortion⁽⁷⁾

Signal-to-noise + distortion

Spurious-free dynamic range

V_{(AUX_IN)}= –0.5 dBFS at 1 kHz

89

–102

88.5

103

THD

dB

SINAD

SFDR

86

dB

INTERNAL REFERENCE OUTPUT

Voltage on REFIO pin

(configured as output)

(10)

V_{(REFIO_INT)}

At T_A= 25°C

4.095

4.096

4.097

V

A

Internal reference temperature

drift

6

22

10 ppm/°C

µF

B

A

C_{(OUT_REFIO)}

V_(REFCAP)

Decoupling capacitor on REFIO

10

Reference voltage to ADC

(on REFCAP pin)

At T_A= 25°C

4.095

4.096

4.097

V

Reference buffer output

impedance

0.5

0.6

22

1

Ω

B

Reference buffer temperature

drift

1.5 ppm/°C

Decoupling capacitor on

REFCAP

C_{(OUT_REFCAP)}

10

μF

C_{(OUT_REFCAP)}= 22 µF,

C_{(OUT_REFIO)}= 22 µF

Turn-on time

15

ms

EXTERNAL REFERENCE INPUT

External reference voltage on

V_{REFIO_EXT}

4.046

4.096

4.146

V

C

REFIO (configured as input)

(10) Does not include the variation in voltage resulting from solder-shift and long-term effects.

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Electrical Characteristics (continued)

Minimum and maximum specifications are at T_A= –40°C to 125°C. Typical specifications are at T_A= 25°C.

AVDD = 5 V, DVDD = 3 V, V_REF= 4.096 V (internal), and f_SAMPLE= 500 kSPS, unless otherwise noted.

TEST

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LEVEL⁽¹⁾

POWER-SUPPLY REQUIREMENTS

AVDD

Analog power-supply voltage

Analog supply

4.75

1.65

5

5.25

V

B

Digital supply range

3.3

AVDD

DVDD

Digital power-supply voltage

Digital supply range for specified

performance

2.7

3.3

13

5.25

16

B

A

For the ADS8688; AVDD = 5 V, f_S

maximum and internal reference

=

Dynamic,

AVDD

I_{AVDD_DYN}

mA

For the ADS8684; AVDD = 5 V, f_S

maximum and internal reference

8.5

11.5

For the ADS8688; AVDD = 5 V,

device not converting and internal

reference

10

12

A

I_{AVDD_STC}

Analog supply current Static

mA

For the ADS8684; AVDD = 5 V,

device not converting and internal

reference

5.5

3

8.5

A

At AVDD = 5 V, device in STDBY

mode and internal reference

I_STDBY

Standby

4.5

20

Power-

down

I_{PWR_DN}

At AVDD = 5 V, device in PWR_DN

At DVDD = 3.3 V, output = 0000h

3

μA

B

A

I_{DVDD_DYN}

Digital supply current

0.5

mA

DIGITAL INPUTS (CMOS)

V_IH

0.7 × DVDD

–0.3

DVDD + 0.3

0.3 × DVDD

DVDD + 0.3

0.2 × DVDD

A

C

Digital input logic levels

DVDD > 2.1 V

V

V_IL

V_IH

V_IL

0.8 × DVDD

–0.3

Digital input logic levels

DVDD ≤ 2.1 V

Input leakage current

Input pin capacitance

100

5

nA

pF

DIGITAL OUTPUTS (CMOS)

V_OH

I_O= 500-μA source

I_O= 500-μA sink

Only for SDO

0.8 × DVDD

0

DVDD

A

C

Digital output logic levels

V

V_OL

0.2 × DVDD

Floating state leakage current

Internal pin capacitance

1

5

µA

pF

TEMPERATURE RANGE

T_A

Operating free-air temperature

–40

125

°C

B

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ZHCSDW1 –JULY 2015

7.6 Timing Requirements: Serial Interface

Minimum and maximum specifications are at T_A= –40°C to 125°C. Typical specifications are at T_A= 25°C.

AVDD = 5 V, DVDD = 3 V, V_REF= 4.096 V (internal), SDO load = 20 pF, and f_SAMPLE= 500 kSPS, unless otherwise noted.

MIN

TYP

MAX

500

17

UNIT

TIMING SPECIFICATIONS

f_S

Sampling frequency (f_CLK= max)

kSPS

µs

t_S

ADC cycle time period (f_CLK= max)

Serial clock frequency (f_S= max)

Serial clock time period (f_S= max)

Conversion time

2

f_SCLK

t_SCLK

t_CONV

t_{DZ_CSDO}

t_{D_CKCS}

t_{DZ_CSDO}

MHz

ns

59

850

10

ns

Delay time: CS falling to data enable

Delay time: last SCLK falling to CS rising

Delay time: CS rising to SDO going to 3-state

ns

10

ns

TIMING REQUIREMENTS

t_ACQ

Acquisition time

1150

0.4

30

10

25

5

ns

t_SCLK

ns

t_{PH_CK}

Clock high time

0.6

t_{PL_CK}

Clock low time

t_{PH_CS}

CS high time

t_{SU_CSCK}

t_{HT_CKDO}

t_{SU_DOCK}

t_{SU_DICK}

t_{HT_CKDI}

t_{SU_DSYCK}

t_{HT_CKDSY}

Setup time: CS falling to SCLK falling

Hold time: SCLK falling to (previous) data valid on SDO

Setup time: SDO data valid to SCLK falling

Setup time: SDI data valid to SCLK falling

Hold time: SCLK falling to (previous) data valid on SDI

Setup time: DAISY data valid to SCLK falling

Hold time: SCLK falling to (previous) data valid on DAISY

ns

5

ns

5

ns

5

ns

Sample

N

Sample

N + 1

t_S

t_CONV

t_ACQ

t_{PH_CS}

CS

SCLK

SDO

t_SCLK

t_{D_CKCS}

31

t_{DZ_CSDO}

t_{SU_CSCK}

t_{PH_CK}

18

t_{PL_CK}

23

24

26

1

2

14

15

16

17

25

27

28

29

7

8

9

30

32

t_{HT_CKDO}

t_{DZ_CSDO}

t_{SU_DOCK}

D14

#2

D6

#2

D5

#2

D4

#2

D3

#2

D2

#2

D1

#2

D0

#2

D15

#2

D9

#2

D8

#2

D7

#2

Data from sample N

t_{SU_DICK}

B2

t_{HT_CKDI}

B14

B10 B9

B8

B7

X

B15

B1

B0

X

B3

SDI

X

t_{SU_DSYCK}

t_{HT_CKDSY}

D14

#1

D6

#1

D5

#1

D4

#1

D3

#1

D2

#1

D1

#1

D0

#1

D15

#1

D9

#1

D8

#1

D7

#1

DAISY

Figure 1. Serial Interface Timing Diagram

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7.7 Typical Characteristics

At T_A= 25°C, AVDD = 5 V, DVDD = 3 V, internal reference V_REF= 4.096 V, and f_SAMPLE= 500 kSPS, unless otherwise noted.

15

9

15

9

---- ± 2.5*V_REF,---- 1.25*V_REF

---- 0.625*V_REF,------0.3125*V_REF

-------0.156 V_REF,---- + 2.5*V_REF

---- + 1.25*V_REF,---- + 0.625*V_REF

---- + 0.3125*V_REF

3

±3

±9

±15

±3

±9

±15

----- -40⁰C

----- 25⁰C

----- 125⁰C

2

6

10

±10

±6

±2

2

6

10

±10

±6

±2

Input Voltage (V)

C001

Input Voltage (V)

C002

Input range = ±2.5 × V_REF

Figure 3. Input Current vs Temperature

Figure 2. Input I-V Characteristic

350

280

210

140

70

800

640

480

320

160

0

---- ± 2.5*V_REF,---- 1.25*V_REF

---- 0.625*V_REF,------0.3125*V_REF

-------0.156 V_REF,---- + 2.5*V_REF

---- + 1.25*V_REF,---- + 0.625*V_REF

---- + 0.3125*V_REF

0

-70

0.85 0.88 0.91 0.94 0.97

1

1.03 1.06 1.09 1.12 1.15

26

59

92

125

±40

±7

Input Impedance (Mꢀ)

C006

Free-Air Temperature (^oC)

C005

Number of samples = 1160

Figure 4. Input Impedance Variation vs Temperature

Figure 5. Typical Distribution of Input Impedance

20000

24000

20000

16000

12000

16000

12000

8000

4000

0

8000

4000

0

32765 32766 32767 32768 32769 32770 32771

Output Codes

32765 32766 32767 32768 32769 32770 32771

Output Codes

C008

C007

Mean = 32768.67, sigma = 0.58, input = 0 V,

range = ±2.5 × V_REF

Mean = 32768.60, sigma = 0.63, input = 0 V,

range = ±1.25 × V_REF

Figure 6. DC Histogram for Mid-Scale Inputs (±2.5 × V_REF

)

Figure 7. DC Histogram for Mid-Scale Inputs (±1.25 × V_REF)

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Typical Characteristics (continued)

At T_A= 25°C, AVDD = 5 V, DVDD = 3 V, internal reference V_REF= 4.096 V, and f_SAMPLE= 500 kSPS, unless otherwise noted.

20000

16000

12000

8000

4000

0

20000

16000

12000

8000

4000

0

32764 32765 32766 32767 32768 32769 32770 32771 32772

Output Codes

32764 32765 32766 32767 32768 32769 32770 32771 32772

Output Codes

C009

C010

Mean = 32768.8, sigma = 0.76, input = 0 V,

range = ±0.625 × V_REF

Mean = 32767.75, sigma = 0.65, input = 1.25 × V_REF

,

range = 2.5 × V_REF

Figure 8. DC Histogram for Mid-Scale Inputs (±0.625 × V_REF

)

Figure 9. DC Histogram for Mid-Scale Inputs (2.5 × V_REF)

20000

12000

10000

8000

6000

4000

2000

16000

12000

8000

4000

0

32764

32766

32768

32770

32772

32760 32762 32764 32766 32768 32770 32772 32774

Output Codes

C012

C011

Mean = 32768.2, sigma = 0.75, input = 0.625 × V_REF

,

Mean = 32768.5, sigma = 1.30, input = 0 V,

range = ±0.3125 × V_REF

range = 1.25 × V_REF

Figure 10. DC Histogram for Mid-Scale Inputs

(1.25 × V_REF

Figure 11. DC Histogram for Mid-Scale Inputs

)

(±0.3125 x V_REF)

6000

5000

4000

3000

2000

1000

0

10000

8000

6000

4000

2000

0

32757 32760 32763 32766 32769 32772 32775 32778 32781

32760

32763

32766

32769

32772

32775

C013

Output Codes

C014

Mean = 32768.5, sigma = 2.68, input = 0 V,

range = ±0.15625 × V_REF

Mean = 32768.5, sigma = 1.30, input = 0.3125 × V_REF

,

range = 0.625 × V_REF

Figure 12. DC Histogram for Mid-Scale Inputs

Figure 13. DC Histogram for Mid-Scale Inputs

(0.625 x V_REF

(±0.15625 x V_REF

)

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Typical Characteristics (continued)

At T_A= 25°C, AVDD = 5 V, DVDD = 3 V, internal reference V_REF= 4.096 V, and f_SAMPLE= 500 kSPS, unless otherwise noted.

1.4

6000

5000

4000

3000

2000

1000

0

1

0.6

0.2

-0.2

-0.6

-1

0

16384

32768

49152

65536

32757

32762

32767

32772

32777

32782

Codes (LSB)

C016

Output Codes

C015

All input ranges

Mean = 32768.5, sigma = 2.68, input = 0.15625 × V_REF

,

range = 0.3125 × V_REF

Figure 14. DC Histogram for Mid-Scale Inputs

Figure 15. Typical DNL for All Codes

(0.3125 x V_REF

)

2

1.5

1

1.4

1

Maximum

0.6

0.2

-0.2

-0.6

-1

0.5

0

-0.5

-1

Minimum

-1.5

-2

0

16384

32768

49152

65536

26

59

92

125

±40

±7

Free-Air Temperature (^oC)

C018

Codes (LSB)

C017

Range = ±2.5 × V_REF

All input ranges

Figure 17. Typical INL for All Codes

Figure 16. DNL vs Temperature

2

1.5

1

2

1.5

1

0.5

0

0.5

0

-0.5

-1

-0.5

-1

-1.5

-2

-1.5

-2

0

16384

32768

49152

65536

0

16384

32768

49152

65536

Codes (LSB)

C019

Codes (LSB)

C020

Range = ±1.25 × V_REF

Figure 18. Typical INL for All Codes

Range = ±0.625 × V_REF

Figure 19. Typical INL for All Codes

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ZHCSDW1 –JULY 2015

Typical Characteristics (continued)

At T_A= 25°C, AVDD = 5 V, DVDD = 3 V, internal reference V_REF= 4.096 V, and f_SAMPLE= 500 kSPS, unless otherwise noted.

2

1.5

1

2

1.5

1

0.5

0

0.5

0

-0.5

-1

-0.5

-1

-1.5

-2

-1.5

-2

0

16384

32768

49152

65536

0

16384

32768

49152

65536

Codes (LSB)

C022

C021

Range = 1.25 × V_REF

Range = 2.5 × V_REF

Figure 21. Typical INL for All Codes

Figure 20. Typical INL for All Codes

2

1.5

1

2

1.5

1

0.5

0

0.5

0

-0.5

-1

-0.5

-1

-1.5

-2

-1.5

-2

0

16384

32768

49152

65536

0

16384

32768

49152

65536

Codes (LSB)

C023

Codes (LSB)

C024

Range = ±0.3125 × V_REF

Range = ±0.15625 × V_REF

Figure 22. Typical INL for All Codes

Figure 23. Typical INL for All Codes

2

1.5

1

2

1.5

1

0.5

0

0.5

0

-0.5

-1

-0.5

-1

-1.5

-2

-1.5

-2

0

16384

32768

49152

65536

0

16384

32768

49152

65536

C025

Codes (LSB)

C026

Range = 0.625 × V_REF

Range = 0.3125 × V_REF

Figure 24. Typical INL for All Codes

Figure 25. Typical INL for All Codes

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Typical Characteristics (continued)

At T_A= 25°C, AVDD = 5 V, DVDD = 3 V, internal reference V_REF= 4.096 V, and f_SAMPLE= 500 kSPS, unless otherwise noted.

2

1.5

1

2

1

Maximum

Minimum

0.5

0

Maximum

Minimum

0

-0.5

-1

±1

±2

-1.5

-2

26

59

92

125

±40

±7

26

59

92

125

±40

±7

Free-Air Temperature (^oC)

C027

C028

Range = ±2.5 × V_REF

Range = ±1.25 × V_REF

Figure 26. INL vs Temperature (±2.5 × V_REF

)

Figure 27. INL vs Temperature (±1.25 × V_REF)

2

1

2

1.5

1

Maximum

Minimum

Maximum

Minimum

0.5

0

-0.5

-1

-2

-1.5

-2

26

59

92

125

26

59

92

125

±40

±7

±40

±7

Free-Air Temperature (^oC)

C029

C030

Range = ±0.625 × V_REF

Range = 2.5 × V_REF

Figure 28. INL vs Temperature (±0.625 × V_REF

)

Figure 29. INL vs Temperature (2.5 × V_REF)

2

1

2

1

Maximum

Minimum

Maximum

Minimum

0

±1

±2

±1

±2

26

59

92

125

±40

±7

26

59

92

125

±40

±7

Free-Air Temperature (^oC)

C032

C031

Range = 1.25 × V_REF

Figure 30. INL vs Temperature (1.25 × V_REF

Range = ±0.3125 × V_REF

Figure 31. INL vs Temperature (±0.3125 × V_REF

)

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ZHCSDW1 –JULY 2015

Typical Characteristics (continued)

At T_A= 25°C, AVDD = 5 V, DVDD = 3 V, internal reference V_REF= 4.096 V, and f_SAMPLE= 500 kSPS, unless otherwise noted.

2

Maximum

Minimum

1

Maximum

Minimum

0

±1

±2

±1

±2

26

59

92

125

26

59

92

125

±40

±7

±40

±7

Free-Air Temperature (^oC)

C033

C034

Range = ±0.15625 × V_REF

Range = 0.625 × V_REF

Figure 32. INL vs Temperature (±0.15625 × V_REF

)

Figure 33. INL vs Temperature (0.625 × V_REF)

2

1

---- ± 2.5*V_REF,---- 1.25*V_REF

---- 0.625*V_REF,------0.3125*V_REF

-------0.156 V_REF,---- + 2.5*V_REF

---- + 1.25*V_REF,---- + 0.625*V_REF

---- + 0.3125*V_REF

0.75

Maximum

0.5

0.25

0

Minimum

-0.25

-0.5

-0.75

-1

±1

±2

26

59

92

125

C035

±40

±7

26

59

92

125

±40

±7

Free-Air Temperature (^oC)

C036

Free-Air Temperature (^oC)

Range = 0.3125 × V_REF

Figure 34. INL vs Temperature (0.3125 × V_REF

)

Figure 35. Offset Error vs

Temperature Across Input Ranges

80

60

40

20

0

1

......CH0, .......CH1, ......CH2,

.......CH3, ......CH4, .......CH5,

........CH6, .......CH7

0.75

0.5

0.25

0

-0.25

-0.5

-0.75

-1

0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

2.2 2.4 2.6 2.8

3

26

59

92

125

±40

±7

Offset Drift (ppm/^oC)

Free-Air Temperature (^oC)

C037

C038

Range = ±2.5 × V_REF

Figure 36. Typical Histogram for Offset Drift

Range = ±2.5 × V_REF

Figure 37. Offset Error vs Temperature Across Channels

17

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Typical Characteristics (continued)

At T_A= 25°C, AVDD = 5 V, DVDD = 3 V, internal reference V_REF= 4.096 V, and f_SAMPLE= 500 kSPS, unless otherwise noted.

100

80

60

40

20

0

0.05

---- ± 2.5*V_REF,---- 1.25*V_REF

---- 0.625*V_REF,------0.3125*V_REF

-------0.156 V_REF,---- + 2.5*V_REF

---- + 1.25*V_REF,---- + 0.625*V_REF

---- + 0.3125*V_REF

0.03

0.01

-0.01

-0.03

-0.05

0

0.5

1

1.5

2

2.5

3

3.5

4

26

59

92

125

±40

±7

Free-Air Temperature (^oC)

C039

Gain Drift (ppm/^oC)

C040

Range = ±2.5 × V_REF

Figure 38. Gain Error vs Temperature Across Input Ranges

Figure 39. Typical Histogram for Gain Error Drift

0.05

2

1.5

1

......CH0, .......CH1, ......CH2,

.......CH3, ......CH4, .......CH5,

........CH6, .......CH7

0.03

0.01

-0.01

-0.03

-0.05

0.5

0

---- ± 2.5*V_REF,---- 1.25*V_REF

---- 0.625*V_REF,------0.3125*V_REF

-------0.156 V_REF,---- + 2.5*V_REF

---- + 1.25*V_REF,---- + 0.625*V_REF

---- + 0.3125*V_REF

-0.5

26

59

92

125

0

4

8

12

16

20

±40

±7

Free-Air Temperature (^oC)

Source Resistance (kꢀ)

C042

C041

Range = ±2.5 × V_REF

Figure 40. Gain Error vs Temperature Across Channels

Figure 41. Gain Error vs External Resistance (R_EXT

)

0

±40

±80

±40

±80

±120

±160

±200

±120

±160

±200

0

50000

100000

150000

200000

250000

0

50000

100000

150000

200000

250000

Input Frequency (Hz)

C044

C043

Number of points = 64k, f_IN= 1 kHz, SNR = 92.3 dB,

SINAD = 91.9 dB, THD = 101 dB, SFDR = 104 dB

Number of points = 64k, f_IN= 1 kHz, SNR = 91.4 dB,

SINAD = 91.2 dB, THD = 105 dB, SFDR = 107 dB

Figure 42. Typical FFT Plot (±2.5 × V_REF

)

Figure 43. Typical FFT Plot (±1.25 × V_REF)

18

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Typical Characteristics (continued)

At T_A= 25°C, AVDD = 5 V, DVDD = 3 V, internal reference V_REF= 4.096 V, and f_SAMPLE= 500 kSPS, unless otherwise noted.

0

±40

±80

±120

±160

±200

±120

±160

±200

0

50000

100000

150000

200000

250000

0

50000

100000

150000

200000

250000

Input Frequency (Hz)

C045

C046

Number of points = 64k, f_IN= 1 kHz, SNR = 89.6 dB,

SINAD = 89.5 dB, THD = 106 dB, SFDR = 107 dB

Number of points = 64k, f_IN= 1 kHz, SNR = 90.93 dB,

SINAD = 90.48 dB, THD = 100 dB, SFDR = 102 dB

Figure 44. Typical FFT Plot (±0.625 × V_REF

)

Figure 45. Typical FFT Plot (2.5 × V_REF)

0

±40

0

±40

±80

±120

±160

±200

±120

±160

±200

0

50000

100000

150000

200000

250000

0

50000

100000

150000

200000

250000

Input Frequency (Hz)

C047

C048

Number of points = 64k, f_IN= 1 kHz, SNR = 89.6 dB,

SINAD = 89.5 dB, THD = –106 dB, SFDR = 107 dB

Number of points = 64k, f_IN= 1 kHz, SNR = 83.55 dB,

SINAD = 83.5 dB, THD = –104 dB, SFDR = 107 dB

Figure 46. Typical FFT Plot (1.25 × V_REF

)

Figure 47. Typical FFT Plot (±0.3125 × V_REF)

0

±40

0

±40

±80

±120

±160

±200

±120

±160

±200

0

50000

100000

150000

200000

250000

0

50000

100000

150000

200000

250000

C050

Input Frequency (Hz)

C049

Number of points = 64k, f_IN= 1 kHz, SNR = 77.6 dB,

SINAD = 77.6 dB, THD = –106 dB, SFDR = 107 dB

Number of points = 64k, f_IN= 1 kHz, SNR = 83.55 dB,

SINAD = 83.5 dB, THD = –103 dB, SFDR = 107 dB

Figure 48. Typical FFT Plot (±0.15625 × V_REF

)

Figure 49. Typical FFT Plot (0.625 × V_REF)

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Typical Characteristics (continued)

At T_A= 25°C, AVDD = 5 V, DVDD = 3 V, internal reference V_REF= 4.096 V, and f_SAMPLE= 500 kSPS, unless otherwise noted.

0

95

±40

90

±80

85

±120

80

±160

±200

---- ± 2.5*V_REF,---- 1.25*V_REF,---- 0.625*V_REF,

------0.3125*V_REF,-------0.156 V_REF,---- + 2.5*V_REF

---- + 1.25*V_REF,---- + 0.625*V_REF,---- + 0.3125*V_REF

75

70

0

50000

100000

150000

200000

250000

100

1000

10000

C052

C051

Input Frequency (Hz)

Number of points = 64k, f_IN= 1 kHz, SNR = 77.55 dB,

SINAD = 77.5 dB, THD = –100 dB, SFDR = 107 dB

Figure 50. Typical FFT Plot (0.3125 × V_REF

)

Figure 51. SNR vs Input Frequency

95

90

85

80

75

70

95

90

85

80

75

70

---- ± 2.5*V_REF,---- 1.25*V_REF,---- 0.625*V_REF,

------0.3125*V_REF,-------0.156 V_REF,---- + 2.5*V_REF

---- + 1.25*V_REF,---- + 0.625*V_REF,---- + 0.3125*V_REF

---- ± 2.5*V_REF,---- 1.25*V_REF,---- 0.625*V_REF,

------0.3125*V_REF,---0.156 V_REF,---- + 2.5*V_REF

---- + 1.25*V_REF,--- + 0.625*V_REF,--- + 0.3125*V_REF

26

59

92

125

±40

±7

100

1000

10000

Free-Air Temperature (^oC)

C053

Input Frequency (Hz)

C054

f_IN= 1 kHz

Figure 52. SNR vs Temperature

Figure 53. SINAD vs Input Frequency

95

90

85

80

75

70

±80

±85

---- ± 2.5*V_REF,---- 1.25*V_REF,---- 0.625*V_REF,

------0.3125*V_REF,-------0.156 V_REF,---- + 2.5*V_REF

---- + 1.25*V_REF,---- + 0.625*V_REF,---- + 0.3125*V_REF

±90

±95

±100

±105

±110

±115

±120

---- ± 2.5*V_REF,---- 1.25*V_REF,---- 0.625*V_REF,

------0.3125*V_REF,-------0.156 V_REF,---- + 2.5*V_REF

---- + 1.25*V_REF,---- + 0.625*V_REF,---- + 0.3125*V_REF

26

59

92

125

±40

±7

100

1000

10000

Free-Air Temperature (^oC)

C055

C056

Input Frequency (Hz)

f_IN= 1 kHz

Figure 54. SINAD vs Temperature

Figure 55. THD vs Input Frequency

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Typical Characteristics (continued)

At T_A= 25°C, AVDD = 5 V, DVDD = 3 V, internal reference V_REF= 4.096 V, and f_SAMPLE= 500 kSPS, unless otherwise noted.

±80

±100

±120

±140

±160

---- ± 2.5*V_REF,---- 1.25*V_REF,---- 0.625*V_REF,

------0.3125*V_REF,-------0.156 V_REF,---- + 2.5*V_REF

---- + 1.25*V_REF,---- + 0.625*V_REF,---- + 0.3125*V_REF

±90

---- ± 2.5*V_REF,

±100

±110

±120

---- 1.25*V_REF,

---- 0.625*V_REF,

------0.3125*V_REF,

-------0.156 V_REF,

---- + 2.5*V_REF

---- + 1.25*V_REF,

---- + 0.625*V_REF,

---- + 0.3125*V_REF

26

59

92

125

±40

±7

50

500

5000

50000

500000

5000000

Free-Air Temperature (^oC)

C058

C057

Input Frequency (Hz)

f_IN= 1 kHz

Figure 56. THD vs Temperature

Figure 57. Memory Crosstalk vs Frequency

±80

±100

±120

±140

±160

±180

±80

±100

±120

±140

±160

---- ± 2.5*V_REF,

---- 1.25*V_REF,

---- 0.625*V_REF,

------0.3125*V_REF,

-------0.156 V_REF,

---- + 2.5*V_REF

---- + 1.25*V_REF,

---- + 0.625*V_REF,

---- + 0.3125*V_REF

---- ± 2.5*V_REF,---- 1.25*V_REF,---- 0.625*V_REF,

------0.3125*V_REF,-------0.156 V_REF,---- + 2.5*V_REF

---- + 1.25*V_REF,---- + 0.625*V_REF,---- + 0.3125*V_REF

50

500

5000

50000

500000

5000000

50

500

5000

50000

500000

5000000

Input Frequency (Hz)

C060

C059

Input Frequency (Hz)

Input = 2 × maximum input voltage

Figure 58. Isolation Crosstalk vs Frequency

Figure 59. Memory Crosstalk vs Frequency for

Overrange Inputs

12

±80

±100

±120

±140

±160

±180

11.5

11

---- ± 2.5*V_REF,---- 1.25*V_REF,---- 0.625*V_REF,

------0.3125*V_REF,-------0.156 V_REF,---- + 2.5*V_REF

---- + 1.25*V_REF,---- + 0.625*V_REF,---- + 0.3125*V_REF

10.5

10

26

59

92

125

±40

±7

50

500

5000

50000

500000 5000000

Free-Air Temperature (^oC)

C074

Input Frequency (Hz)

C061

Input = 2 × maximum input voltage

Figure 61. AVDD Current vs Temperature for the ADS8688A

(f_S= 500 kSPS)

Figure 60. Isolation Crosstalk vs Frequency for

Overrange Inputs

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Typical Characteristics (continued)

At T_A= 25°C, AVDD = 5 V, DVDD = 3 V, internal reference V_REF= 4.096 V, and f_SAMPLE= 500 kSPS, unless otherwise noted.

9

8.75

8.5

9

8.75

8.5

8.25

8

8.25

8

7.75

7.5

7.75

7.5

26

59

92

125

26

59

92

125

±40

±7

±40

±7

Free-Air Temperature (^oC)

C075

C082

Figure 62. AVDD Current vs Temperature for the ADS8688A

(During Sampling)

Figure 63. AVDD Current vs Temperature for the ADS8684A

(f_S= 500 kSPS)

6

5.75

5.5

2.3

2.2

2.1

2

5.25

5

4.75

4.5

26

59

92

125

±40

±7

26

59

92

125

±40

±7

Free-Air Temperature(^oC)

Free-Air Temperature (^oC)

C076

C083

Figure 64. AVDD Current vs Temperature for the ADS8684A

(During Sampling)

Figure 65. AVDD Current vs Temperature

(STANDBY)

6

5

4

3

2

1

26

59

92

125

±40

±7

Free-Air Temperature (^oC)

C077

Figure 66. AVDD Current vs Temperature

(Power Down)

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8 Detailed Description

8.1 Overview

The ADS8684A and ADS8688A are 16-bit data acquisition systems with 4- and 8-channel analog inputs,

respectively. Each analog input channel consists of an overvoltage protection circuit, a programmable gain

amplifier (PGA), and a second-order, antialiasing filter that conditions the input signal before being fed into a 4-

or 8-channel analog multiplexer (MUX). The output of the MUX is digitized using a 16-bit analog-to-digital

converter (ADC), based on the successive approximation register (SAR) architecture. This overall system can

achieve a maximum throughput of 500 kSPS, combined across all channels. The devices feature a 4.096-V

internal reference with a fast-settling buffer and a simple SPI-compatible serial interface with daisy-chain (DAISY)

and ALARM features.

The devices operate from a single 5-V analog supply and can accommodate true bipolar input signals up to

±2.5 × V_REF. The devices offer a constant 1-MΩ resistive input impedance irrespective of the sampling frequency

or the selected input range. The integration of multichannel precision analog front-end circuits with high input

impedance and a precision ADC operating from a single 5-V supply offers a simplified end solution without

requiring external high-voltage bipolar supplies and complicated driver circuits.

8.2 Functional Block Diagram

DVDD

AVDD

ADS8688A

ADS8684A

1 M:

OVP

AIN_0P

2nd-Order

LPF

ADC

Driver

PGA

AIN_0GND

1 M:

V_B0

V_B1

V_B2

V_B3

V_B4

V_B5

V_B6

V_B7

OVP

AIN_1P

2nd-Order

LPF

ADC

Driver

AIN_1GND

1 M:

OVP

AIN_2P

2nd-Order

LPF

ADC

Driver

Digital

Logic

and

AIN_2GND

CS

1 M:

Interface

SCLK

SDI

OVP

AIN_3P

2nd-Order

LPF

ADC

Driver

AIN_3GND

1 M:

SDO

OVP

AIN_4P

2nd-Order

LPF

16-Bit

SAR ADC

ADC

Driver

AIN_4GND

DAISY

REFSEL

RST/PD

1 M:

OVP

AIN_5P

2nd-Order

LPF

ADC

Driver

Oscillator

AIN_5GND

1 M:

ALARM

OVP

AIN_6P

2nd-Order

LPF

ADC

Driver

REFCAP

AIN_6GND

1 M:

REFIO

OVP

AIN_7P

2nd-Order

LPF

ADC

Driver

AIN_7GND

4.096-V

Reference

1 M:

AUX_IN

AUX_GND

AGND

DGND

REFGND

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8.3 Feature Description

8.3.1 Analog Inputs

The ADS8684A and ADS8688A have either four or eight analog input channels, respectively, such that the

positive inputs AIN_nP (n = 0 to 3 or 7) are the single-ended analog inputs and the negative inputs AIN_nGND

are tied to GND. Figure 67 shows the simplified circuit schematic for each analog input channel, including the

input overvoltage protection circuit, PGA, low-pass filter (LPF), high-speed ADC driver, and analog multiplexer.

1 M:

CS

SCLK

SDI

SDO

DAISY

OVP

AIN_nP

2nd-Order

LPF

ADC

Driver

MUX

PGA

ADC

AIN_nGND

1 M:

V_B

NOTE: n = 0 to 3 for the ADS8684A and n = 0 to 7 for the ADS8688A.

Figure 67. Front-End Circuit Schematic for Each Analog Input Channel

The devices can support multiple unipolar or bipolar, single-ended input voltage ranges based on the

configuration of the program registers. As explained in the Range Select Registers section, the input voltage

range for each analog channel can be configured to bipolar ±2.5 × V_REF, ±1.25 × V_REF, ±0.625 × V_REF, ±0.3125 ×

V_REF, and ±0.15625 × V_REFor unipolar 0 to 2.5 × V_REF, 0 to 1.25 × V_REF, 0 to 0.625 × V_REF, and 0 to 0.3125 ×

V_REF. With the internal or external reference voltage set to 4.096 V, the input ranges of the device can be

configured to bipolar ranges of ±10.24 V, ±5.12 V, ±2.56 V, ±1.28 V, and ±0.64 V or unipolar ranges of 0 V to

10.24 V, 0 V to 5.12 V, 0 V to 2.56 V, and 0 V to 1.28 V. Any of these input ranges can be assigned to any

analog input channel of the device. For instance, the ±2.5 × V_REFrange can be assigned to AIN_1P, the ±1.25 ×

V_REFrange can be assigned to AIN_2P, the 0 V to 2.5 × V_REFrange can be assigned to AIN_3P, and so forth.

The devices sample the voltage difference (AIN_nP – AIN_nGND) between the selected analog input channel

and the AIN_nGND pin. The devices allow a ±0.1-V range on the AIN_nGND pin for all analog input channels.

This feature is useful in modular systems where the sensor or signal-conditioning block is further away from the

ADC on the board and when a difference in the ground potential of the sensor or signal conditioner from the ADC

ground is possible. In such cases, running separate wires from the AIN_nGND pin of the device to the sensor or

signal-conditioning ground is recommended.

If the analog input pins (AIN_nP) to the devices are left floating, the output of the ADC corresponds to an internal

biasing voltage. The output from the ADC must be considered as invalid if the devices are operated with floating

input pins. This condition does not cause any damage to the devices, which are fully functional when a valid

input voltage is applied to the pins.

8.3.2 Analog Input Impedance

Each analog input channel in the device presents a constant resistive impedance of 1 MΩ. The input impedance

is independent of either the ADC sampling frequency, the input signal frequency, or range. The primary

advantage of such high-impedance inputs is the ease of driving the ADC inputs without requiring driving

amplifiers with low output impedance. Bipolar, high-voltage power supplies are not required in the system

because this ADC does not require any high-voltage front-end drivers. In most applications, the signal sources or

sensor outputs can be directly connected to the ADC input, thus significantly simplifying the design of the signal

chain.

In order to maintain the dc accuracy of the system, matching the external source impedance on the AIN_nP input

pin with an equivalent resistance on the AIN_nGND pin is recommended. This matching helps to cancel any

additional offset error contributed by the external resistance.

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Feature Description (continued)

8.3.3 Input Overvoltage Protection Circuit

The ADS8684A and ADS8688A feature an internal overvoltage protection circuit on each of the four or eight

analog input channels, respectively. Use these protection circuits as a secondary protection scheme to protect

the device. Using external protection devices against surges, electrostatic discharge (ESD), and electrical fast

transient (EFT) conditions is highly recommended. The conceptual block diagram of the internal overvoltage

protection (OVP) circuit is shown in Figure 68.

AVDD

V_P+

R_FB

0V

ESD

AVDD

V_P-

10ꢀ

R_S

D1p

D2p

AIN_nP

V_±

V₊

AVDD

V_OUT

D1n

AIN_nGND

+

D2n

R_DC

V_B

ESD

GND

Figure 68. Input Overvoltage Protection Circuit Schematic

As shown in Figure 68, the combination of the 1-MΩ input resistors along with the PGA gain-setting resistors

(R_FBand R_DC) limit the current flowing into the input pins. A combination of antiparallel diodes (D1 and D2) are

added on each input pin to protect the internal circuitry and set the overvoltage protection limits.

Table 1 explains the various operating conditions for the device when the device is powered on. Table 1

indicates that when the AVDD pin of the device is connected to the proper supply voltage (AVDD = 5 V) or offers

a low impedance of < 30 kΩ, the internal overvoltage protection circuit can withstand up to ±20 V on the analog

input pins.

Table 1. Input Overvoltage Protection Limits When AVDD = 5 V or Offers a Low Impedance of < 30 kΩ⁽¹⁾

INPUT CONDITION

(V_OVP= ±20 V)

TEST

ADC

COMMENTS

CONDITION OUTPUT

All input

Valid

|V_IN| < |V_RANGE

|V_RANGE| < |V_IN| < |V_OVP

|V_IN| > |V_OVP

|

Within operating range

Device functions as per data sheet specifications

ranges

Beyond operating range but

within overvoltage range

All input

Saturated

ranges

ADC output is saturated, but device is internally

protected (not recommended for extended time)

|

All input

Saturated

ranges

This usage condition may cause irreversible damage

to the device

|

Beyond overvoltage range

(1) GND = 0, AIN_nGND = 0 V, |V_RANGE| is the maximum input voltage for any selected input range, and |V_OVP| is the break-down voltage

for the internal OVP circuit. Assume that R_Sis approximately 0.

The results indicated in Table 1 are based on an assumption that the analog input pins are driven by very low

impedance sources (R_Sis approximately 0). However, if the sources driving the inputs have higher impedance,

the current flowing through the protection diodes reduces further, thereby increasing the OVP voltage range.

Note that higher source impedance results in gain errors and contributes to overall system noise performance.

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ADS8684A, ADS8688A

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Figure 69 shows the voltage versus current response of the internal overvoltage protection circuit when the

device is powered on. According to this current-to-voltage (I-V) response, the current flowing into the device input

pins is limited by the 1-MΩ input impedance. However, for voltages beyond ±20 V, the internal node voltages

surpass the break-down voltage for internal transistors, thus setting the limit for overvoltage protection on the

input pins.

The same overvoltage protection circuit also provides protection to the device when the device is not powered on

and AVDD is floating with an impedance > 30 kΩ. This condition can arise when the input signals are applied

before the ADC is fully powered on. The overvoltage protection limits for this condition are shown in Table 2.

Table 2. Input Overvoltage Protection Limits When AVDD = Floating with Impedance > 30 kΩ⁽¹⁾

INPUT CONDITION

(V_OVP= ±11 V)

TEST

CONDITION

ADC OUTPUT

Invalid

COMMENTS

Device is not functional but is protected internally by

the OVP circuit.

|V_IN| < |V_OVP

|

Within overvoltage range

Beyond overvoltage range

All input ranges

This usage condition may cause irreversible damage

to the device.

|V_IN| > |V_OVP

Invalid

(1) AVDD = floating, GND = 0, AIN_nGND = 0 V, |V_RANGE| is the maximum input voltage for any selected input range, and |V_OVP| is the

break-down voltage for the internal OVP circuit. Assume that R_Sis approximately 0.

Figure 70 shows the voltage versus current response of the internal overvoltage protection circuit when the

device is not powered on. According to this I-V response, the current flowing into the device input pins is limited

by the 1-MΩ input impedance. However, for voltages beyond ±11 V, the internal node voltages surpass the

break-down voltage for internal transistors, thus setting the limit for overvoltage protection on the input pins.

30

18

20

12

---- ± 2.5*V_REF,---- 1.25*V_REF

---- 0.625*V_REF,------0.3125*V_REF

-------0.156 V_REF,---- + 2.5*V_REF

---- + 1.25*V_REF,---- + 0.625*V_REF

---- + 0.3125*V_REF

6

4

±6

±4

±18

±30

±12

±20

0

10

20

30

±20

±12

±4

4

12

20

±30

±20

±10

C003

Input Voltage (V)

C004

Figure 69. I-V Curve for an Input OVP Circuit

Figure 70. I-V Curve for an Input OVP Circuit

(AVDD = Floating)

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8.3.4 Programmable Gain Amplifier (PGA)

The devices offer a programmable gain amplifier (PGA) at each individual analog input channel, which converts

the original single-ended input signal into a fully-differential signal to drive the internal 16-bit ADC. The PGA also

adjusts the common-mode level of the input signal before being fed into the ADC to ensure maximum usage of

the ADC input dynamic range. Depending on the range of the input signal, the PGA gain can be accordingly

adjusted by setting the Range_CHn[3:0] (n = 0 to 3 or 7) bits in the program register. The default or power-on

state for the Range_CHn[3:0] bits is 0000, which corresponds to an input signal range of ±2.5 × V_REF. Table 3

lists the various configurations of the Range_CHn[3:0] bits for the different analog input voltage ranges.

The PGA uses a very highly-matched network of resistors for multiple gain configurations. Matching between

these resistors and the amplifiers across all channels is accurately trimmed to keep the overall gain error low

across all channels and input ranges.

Table 3. Input Range Selection Bits Configuration

Range_CHn[3:0]

ANALOG INPUT RANGE

BIT 3

BIT 2

BIT 1

BIT 0

±2.5 × V_REF

±1.25 × V_REF

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

±0.625 × V_REF

±0.3125 × V_REF

±0.15625 × V_REF

0 to 2.5 × V_REF

0 to 1.25 × V_REF

0 to 0.625 × V_REF

0 to 0.3125 × V_REF

8.3.5 Second-Order, Low-Pass Filter (LPF)

In order to mitigate the noise of the front-end amplifiers and gain resistors of the PGA, each analog input channel

of the ADS8684A and ADS8688A features a second-order, antialiasing LPF at the output of the PGA. The

magnitude and phase response of the analog antialiasing filter are shown in Figure 71 and Figure 72,

respectively. For maximum performance, the –3-dB cutoff frequency for the antialiasing filter is typically set to

15 kHz. The performance of the filter is consistent across all input ranges supported by the ADC.

2

1

0

±15

±30

±45

±60

±75

±90

0

±1

±2

±3

±4

±5

±6

---- ± 2.5*V_REF,---- 1.25*V_REF

---- 0.625*V_REF,------0.3125*V_REF

-------0.156 V_REF,---- + 2.5*V_REF

---- + 1.25*V_REF,---- + 0.625*V_REF

---- + 0.3125*V_REF

---- ± 2.5*V_REF,---- 1.25*V_REF

---- 0.625*V_REF,------0.3125*V_REF

-------0.156 V_REF,---- + 2.5*V_REF

---- + 1.25*V_REF,---- + 0.625*V_REF

---- + 0.3125*V_REF

100

1000

10000

100

1000

10000

Input Frequency (Hz)

C065

Input Frequency (Hz)

C064

Figure 71. Second-Order LPF Magnitude Response

Figure 72. Second-Order LPF Phase Response

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8.3.6 ADC Driver

In order to meet the performance of a 16-bit, SAR ADC at the maximum sampling rate (500 kSPS), the sample-

and-hold capacitors at the input of the ADC must be successfully charged and discharged during the acquisition

time window. This drive requirement at the inputs of the ADC necessitates the use of a high-bandwidth, low-

noise, and stable amplifier buffer. Such an input driver is integrated in the front-end signal path of each analog

input channel of the device. During transition from one channel of the multiplexer to another channel, the fast

integrated driver ensures that the multiplexer output settles to a 16-bit accuracy within the acquisition time of the

ADC, irrespective of the input levels on the respective channels.

8.3.7 Multiplexer (MUX)

The ADS8684A and ADS8688A feature an integrated 4- and 8-channel analog multiplexer, respectively. For

each analog input channel, the voltage difference between the positive analog input AIN_nP and the negative

ground input AIN_nGND is conditioned by the analog front-end circuitry before being fed into the multiplexer. The

output of the multiplexer is directly sampled by the ADC. The multiplexer in the device can scan these analog

inputs in either manual or auto-scan mode, as explained in the Channel Sequencing Modes section. In manual

mode (MAN_Ch_n), the channel is selected for every sample via a register write; in auto-scan mode

(AUTO_RST), the channel number is incremented automatically on every CS falling edge after the present

channel is sampled. The analog inputs can be selected for an auto scan with register settings (see the Auto-

Scan Sequencing Control Registers section). The devices automatically scan only the selected analog inputs in

ascending order.

The maximum overall throughput for the ADS8684A and ADS8688A is specified at 500 kSPS across all

channels. The per channel throughput is dependent on the number of channels selected in the multiplexer

scanning sequence. For example, the throughput per channel is equal to 250 kSPS if only two channels are

selected, but is equal to 125 kSPS per channel if four channels are selected (as in the ADS8684A), and so forth.

See Table 6 for command register settings to switch between the auto-scan mode and manual mode for

individual analog channels.

8.3.8 Reference

The ADS8684A and ADS8688A can operate with either an internal voltage reference or an external voltage

reference using the internal buffer. The internal or external reference selection is determined by an external

REFSEL pin. The devices have a built-in buffer amplifier to drive the actual reference input of the internal ADC

core for maximizing performance.

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8.3.8.1 Internal Reference

The devices have an internal 4.096-V (nominal value) reference. In order to select the internal reference, the

REFSEL pin must be tied low or connected to AGND. When the internal reference is used, REFIO (pin 5)

becomes an output pin with the internal reference value. Placing a 10-µF (minimum) decoupling capacitor

between the REFIO pin and REFGND (pin 6) is recommended, as shown in Figure 73. The capacitor must be

placed as close to the REFIO pin as possible. The output impedance of the internal band-gap circuit creates a

low-pass filter with this capacitor to band-limit the noise of the reference. The use of a smaller capacitor value

allows higher reference noise in the system, thus degrading SNR and SINAD performance. Do not use the

REFIO pin to drive external ac or dc loads because REFIO has limited current output capability. The REFIO pin

can be used as a source if followed by a suitable op amp buffer (such as the OPA320).

AVDD

4.096 V_REF

REFSEL

REFIO

10 PF

REFCAP

22 PF

1 PF

REFGND

ADC

AGND

Figure 73. Device Connections for Using an Internal 4.096-V Reference

The device internal reference is trimmed to a maximum initial accuracy of ±1 mV. The histogram in Figure 74

shows the distribution of the internal voltage reference output taken from more than 3300 production devices.

600

500

400

300

200

100

0

-1

-0.6

-0.2

0.2

0.6

1

C064

Error in REFIO Voltage (mV)

Figure 74. Internal Reference Accuracy at Room Temperature Histogram

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The initial accuracy specification for the internal reference can be degraded if the die is exposed to any

mechanical or thermal stress. Heating the device when being soldered to a PCB and any subsequent solder

reﬂow is a primary cause for shifts in the V_REFvalue. The main cause of thermal hysteresis is a change in die

stress and therefore is a function of the package, die-attach material, and molding compound, as well as the

layout of the device itself.

In order to illustrate this effect, 80 devices were soldered using lead-free solder paste with the manufacturer's

suggested reflow profile, as explained in application report SNOA550. The internal voltage reference output is

measured before and after the reflow process and the typical shift in value is shown in Figure 75. Although all

tested units exhibit a positive shift in their output voltages, negative shifts are also possible. Note that the

histogram in Figure 75 shows the typical shift for exposure to a single reflow profile. Exposure to multiple reflows,

which is common on PCBs with surface-mount components on both sides, causes additional shifts in the output

voltage. If the PCB is to be exposed to multiple reflows, solder the ADS8684A and ADS8688A in the second

pass to minimize device exposure to thermal stress.

30

25

20

15

10

5

0

-4

-3

-2

-1

0

1

Error in REFIO Voltage (mV)

C065

Figure 75. Solder Heat Shift Distribution Histogram

The internal reference is also temperature compensated to provide excellent temperature drift over an extended

industrial temperature range of –40°C to 125°C. Figure 76 shows the variation of the internal reference voltage

across temperature for different values of the AVDD supply voltage. The typical specified value of the reference

voltage drift over temperature is 6 ppm/°C (Figure 77) and the maximum specified temperature drift is equal to

10 ppm/°C.

4.1

4.099

4.098

4.097

4.096

4.095

4.094

4.093

4.092

4.091

4.09

20

16

12

8

----- AVDD = 5.25 V

------ AVDD = 5 V

------ AVDD = 4.75 V

4

0

26

59

92

125

1

2

3

4

5

6

7

8

9

10

±40

±7

Free-Air Temperature (^oC)

REFIO Drift (ppm/ºC)

C054

C053

AVDD = 5 V, number of devices = 30, ΔT = –40°C to 125°C

Figure 76. Variation of the Internal Reference Output

(REFIO) Across Supply and Temperature

Figure 77. Internal Reference Temperature Drift Histogram

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8.3.8.2 External Reference

For applications that require a better reference voltage or a common reference voltage for multiple devices, the

ADS8684A and ADS8688A offer a provision to use an external reference along with an internal buffer to drive

the ADC reference pin. In order to select the external reference mode, either tie the REFSEL pin high or connect

this pin to the DVDD supply. In this mode, an external 4.096-V reference must be applied at REFIO (pin 5),

which becomes an input pin. Any low-power, low-drift, or small-size external reference can be used in this mode

because the internal buffer is optimally designed to handle the dynamic loading on the REFCAP pin, which is

internally connected to the ADC reference input. The output of the external reference must be appropriately

filtered to minimize the resulting effect of the reference noise on system performance. A typical connection

diagram for this mode is shown in Figure 78.

AVDD

DVDD

4.096 V_REF

REFSEL

AVDD

REF5040

(See the device datasheet for

a detailed pin configuration.)

OUT

C_REF

REFIO

REFCAP

1 PF

22 PF

REFGND

AGND

ADC

Figure 78. Device Connections for Using an External 4.096-V Reference

The output of the internal reference buffer appears at the REFCAP pin. A minimum capacitance of 10 µF must

be placed between REFCAP (pin 7) and REFGND (pin 6). Place another capacitor of 1 µF as close to the

REFCAP pin as possible for decoupling high-frequency signals. Do not use the internal buffer to drive external ac

or dc loads because of the limited current output capability of this buffer.

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The performance of the internal buffer output is very stable across the entire operating temperature range of

–40°C to 125°C. Figure 79 shows the variation in the REFCAP output across temperature for different values of

the AVDD supply voltage. The typical specified value of the reference buffer drift over temperature is 1 ppm/°C

(Figure 80) and the maximum specified temperature drift is equal to 1.5 ppm/°C.

4.097

4.0968

4.0966

4.0964

4.0962

4.096

15

12

9

----- AVDD = 5.25 V

------ AVDD = 5 V

------ AVDD = 4.75 V

6

4.0958

4.0956

4.0954

4.0952

4.095

3

0

0.2

0.4

0.6

0.8

1

1.2

26

59

92

125

±40

±7

Free-Air Temperature (^oC)

C055

REFCAP Drift (ppm/ºC)

C056

AVDD = 5 V, number of devices = 30, ΔT = –40°C to 125°C

Figure 79. Variation of the Reference Buffer Output

(REFCAP) vs Supply and Temperature

Figure 80. Reference Buffer Temperature Drift Histogram

8.3.9 Auxiliary Channel

The devices include a single-ended auxiliary input channel (AUX_IN and AUX_GND). The AUX channel provides

direct interface to an internal, high-precision, 16-bit ADC through the multiplexer because this channel does not

include the front-end analog signal conditioning that the other analog input channels have. The AUX channel

supports a single unipolar input range of 0 V to V_REFbecause there is no front-end PGA. The input signal on the

AUX_IN pin can vary from 0 V to V_REF, whereas the AUX_GND pin must be tied to GND.

When a conversion is initiated, the voltage between these pins is sampled directly on an internal sampling

capacitor (75 pF, typical). The input current required to charge the sampling capacitor is determined by several

factors, including the sampling rate, input frequency, and source impedance. For slow applications that use a

low-impedance source, the inputs of the AUX channel can be directly driven. When the throughput, input

frequency, or the source impedance increases, a driving amplifier must be used at the input to achieve good ac

performance from the AUX channel. Some key requirements of the driving amplifier are discussed in the Input

Driver for the AUX Channel section.

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The AUX channel in the ADS8684A and ADS8688A offers a true 16-bit performance with no missing codes.

Some typical performance characteristics of the AUX channel are shown in Figure 81 to Figure 84.

8000

6000

4000

2000

0

0.1

0.05

0

4.0

3.0

2.0

-0.05

-0.1

-0.15

-0.2

-0.25

-0.3

1.0

Offset Error

0.0

±1.0

±2.0

±3.0

±4.0

Gain Error

-40

-7

26

59

92

125

32763 32764 32765 32766 32767 32768 32769 32770 32771

Output Codes

Free-Air Temperature (^oC)

C067

C066

AUX channel

Mean = 32767.15, sigma = 0.83

Figure 82. Offset and Gain vs Temperature

(AUX Channel)

Figure 81. DC Histogram for Mid-Scale Input

(AUX Channel)

0

±40

90

89

88

87

86

-101.5

-102

SNR

-102.5

-103

SINAD

±80

±120

±160

±200

-103.5

-104

THD

-104.5

-40

-7

26

59

92

125

0

50000

100000

150000

200000

250000

Free-Air Temperature (^oC)

C069

C068

Input Frequency (Hz)

f_IN= 1 kHz

f_IN= 1 kHz, SNR = 88.2 dB, SINAD = 88.1 dB, THD = –102 dB,

SFDR = 102 dB, number of points = 64k

Figure 83. Typical FFT Plot

(AUX Channel)

Figure 84. SNR, SINAD, and THD vs Temperature

(AUX Channel)

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8.3.9.1 Input Driver for the AUX Channel

For applications that use the AUX input channels at high throughput and high input frequency, a driving amplifier

with low output impedance is required to meet the ac performance of the internal 16-bit ADC. Some key

specifications of the input driving amplifier are discussed below:

•

Small-signal bandwidth. The small-signal bandwidth of the input driving amplifier must be much higher than

the bandwidth of the AUX input to ensure that there is no attenuation of the input signal resulting from the

bandwidth limitation of the amplifier. In a typical data acquisition system, a low cut-off frequency, antialiasing

filter is used at the inputs of a high-resolution ADC. The amplifier driving the antialiasing filter must have a low

closed-loop output impedance for stability, thus implying a higher gain bandwidth for the amplifier. Higher

small-signal bandwidth also minimizes the harmonic distortion at higher input frequencies. In general, the

amplifier bandwidth requirements can be calculated on the basis of Equation 1.

GBW t 4uf_{ꢀ3 dB}

where:

•

f_–3dBis the 3-dB bandwidth of the RC filter.

(1)

•

Distortion. In order to achieve the distortion performance of the AUX channel, the distortion of the input driver

must be at least 10 dB lower than the specified distortion of the internal ADC, as shown in Equation 2.

THD_AMPd THD_ADCꢂ10 dB

ꢀ

ꢁ

(2)

Noise. Careful considerations must be made to select a low-noise, front-end amplifier in order to prevent any

degradation in SNR performance of the system. As a rule of thumb, to ensure that the noise performance of

the data acquisition system is not limited by the front-end circuit, keep the total noise contribution from the

front-end circuit below 20% of the input-referred noise of the ADC. Noise from the input driver circuit is band-

limited by the low cut-off frequency of the input antialiasing filter, as explained in Equation 3.

2

SNR dB

ꢀ

ꢁ

V

§

¨

·

¸

1

ꢂ

_ AMP_PP

S

2

1

5

V

N_Gu

ꢃ e_n²_{_RMS}

u

uf_ꢂ3dB

d

u

^FSRu10

2 2

f

20

¨

©

¸

¹

6.6

where:

•

V_{1 / f_AMP_PP}is the peak-to-peak flicker noise,

e_{n_RMS}is the amplifier broadband noise density in nV/√Hz, and

N_Gis the noise gain of the front-end circuit, which is equal to 1 in a buffer configuration.

(3)

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8.3.10 ADC Transfer Function

The ADS8684A and ADS8688A are a family of multichannel devices that support single-ended, bipolar, and

unipolar input ranges on all input channels. The output of the devices is in straight binary format for both bipolar

and unipolar input ranges. The format for the output codes is the same across all analog channels.

The ideal transfer characteristic for each ADC channel for all input ranges is shown in Figure 85. The full-scale

range (FSR) for each input signal is equal to the difference between the positive full-scale (PFS) input voltage

and the negative full-scale (NFS) input voltage. The LSB size is equal to FSR / 2¹⁶= FSR / 65536 because the

resolution of the ADC is 16 bits. For a reference voltage of V_REF= 4.096 V, the LSB values corresponding to the

different input ranges are listed in Table 4.

FFFFh

8000h

0001h

FSR ± 1LSB

Analog Input (AIN_nP t AIN_nGND)

1LSB

FSR/2

NFS

PFS

Figure 85. 16-Bit ADC Transfer Function (Straight-Binary Format)

Table 4. ADC LSB Values for Different Input Ranges (V_REF= 4.096 V)

INPUT RANGE

±2.5 × V_REF

POSITIVE FULL-SCALE NEGATIVE FULL-SCALE

FULL-SCALE RANGE

20.48 V

10.24 V

5.12 V

LSB (µV)

312.50

10.24 V

5.12 V

2.56 V

1.28 V

0.64 V

10.24 V

5.12 V

2.56 V

1.28 V

–10.24 V

–5.12 V

–2.56 V

–1.28 V

–0.64 V

0 V

±1.25 × V_REF

156.25

±0.625 × V_REF

±0.3125 × V_REF

±0.15625 × V_REF

0 to 2.5 × V_REF

0 to 1.25 × V_REF

0 to 0.625 × V_REF

0 to 0.3125 × V_REF

78.125

2.56 V

39.0625

19.53125

156.25

1.28 V

10.24 V

5.12 V

0 V

78.125

0 V

2.56 V

39.0625

19.53125

0 V

1.28 V

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8.3.11 Alarm Feature

The devices have an active-high ALARM output on pin 35. The ALARM signal is synchronous and changes its

state on the 16th falling edge of the SCLK signal. A high level on ALARM indicates that the alarm flag has

tripped on one or more channels of the device. This pin can be wired to interrupt the host input. When an

ALARM interrupt is received, the alarm flag registers are read to determine which channels have an alarm. The

devices feature independently-programmable alarms for each channel. There are two alarms per channel (a low

and a high alarm) and each alarm threshold has a separate hysteresis setting.

The ADS8684A and ADS8688A set a high alarm when the digital output for a particular channel exceeds the

high alarm upper limit [high alarm threshold (T) + hysteresis (H)]. The alarm resets when the digital output for the

channel is less than or equal to the high alarm lower limit (high alarm T – H – 2). This function is shown in

Figure 86.

Similarly, the lower alarm is triggered when the digital output for a particular channel falls below the low alarm

lower limit (low alarm threshold T – H – 1). The alarm resets when the digital output for the channel is greater

than or equal to the low alarm higher limit (low alarm T + H + 1). This function is shown in Figure 87.

L_ALARM On

H_ALARM On

L_ALARM Off

H_ALARM Off

(T ± H ± 1)(T + H + 1)

ADC Output

(T + H)

ADC Output

(T ± H ± 2)

Figure 87. Low-ALARM Hysteresis

Figure 86. High-ALARM Hysteresis

Figure 88 shows a functional block diagram for a single-channel alarm. There are two flags for each high and low

alarm: active alarm flag and tripped alarm flag; see the Alarm Flag Registers (Read-Only) section for more

details. The active alarm flag is triggered when an alarm condition is encountered for a particular channel; the

active alarm flag resets when the alarm shuts off. A tripped alarm flag sets an alarm condition in the same

manner as for an active alarm flag. However, the tripped alarm flag remains latched and resets only when the

appropriate alarm flag register is read.

Alarm Threshold

ALARM

Channel n

+/-

Hysteresis Channel n

Active Alarm Flag

Channel n

+

ADC Output

Channel n

16^th

SCLK

Tripped Alarm Flag

S

R

Q

Channel n

Alarm Flag Read

ADC

SDO

Figure 88. Alarm Functionality Schematic

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8.4 Device Functional Modes

8.4.1 Device Interface

8.4.1.1 Digital Pin Description

The digital data interface for the ADS8684A and ADS8688A is shown in Figure 89.

CS

SCLK

SDI

CS

SCLK

SDO

ADS8684A

ADS8688A

SDO

SDI

RST / PD

DAISY

RST / PD

SDO_N(from previous device)

or DGND

Figure 89. Pin Configuration for the Digital Interface

The signals shown in Figure 89 are summarized as follows:

8.4.1.1.1 CS (Input)

CS indicates an active-low, chip-select signal. CS is also used as a control signal to trigger a conversion on the

falling edge. Each data frame begins with the falling edge of the CS signal. The analog input channel to be

converted during a particular frame is selected in the previous frame. On the CS falling edge, the devices sample

the input signal from the selected channel and a conversion is initiated using the internal clock. The device

settings for the next data frame can be input during this conversion process. When the CS signal is high, the

ADC is considered to be in an idle state.

8.4.1.1.2 SCLK (Input)

This pin indicates the external clock input for the data interface. All synchronous accesses to the device are

timed with respect to the falling edges of the SCLK signal.

8.4.1.1.3 SDI (Input)

SDI is the serial data input line. SDI is used by the host processor to program the internal device registers for

device configuration. At the beginning of each data frame, the CS signal goes low and the data on the SDI line

are read by the device at every falling edge of the SCLK signal for the next 16 SCLK cycles. Any changes made

to the device configuration in a particular data frame are applied to the device on the subsequent falling edge of

the CS signal.

8.4.1.1.4 SDO (Output)

SDO is the serial data output line. SDO is used by the device to output conversion data. The size of the data

output frame varies depending on the register setting for the SDO format; see Table 13. A low level on CS

releases the SDO pin from the Hi-Z state. SDO is kept low for the first 15 SCLK falling edges. The MSB of the

output data stream is clocked out on SDO on the 16th SCLK falling edge, followed by the subsequent data bits

on every falling edge thereafter. The SDO line goes low after the entire data frame is output and goes to a Hi-Z

state when CS goes high.

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Device Functional Modes (continued)

8.4.1.1.5 DAISY (Input)

DAISY is a serial input pin. When multiple devices are connected in daisy-chain mode, as illustrated in Figure 92,

the DAISY pin of the first device in the chain is connected to GND. The DAISY pin of every subsequent device is

connected to the SDO output pin of the previous device, and the SDO output of the last device in the chain goes

to the SDI of the host processor. If an application uses a stand-alone device, the DAISY pin is connected to

GND.

8.4.1.1.6 RST/PD (Input)

RST/PD is a dual-function pin. Figure 90 shows the timing of this pin and Table 5 explains the usage of this pin.

RST / PD

t_{PL_RST_PD}

Figure 90. RST/PD Pin Timing

Table 5. RST/PD Pin Functionality

CONDITION

DEVICE MODE

40 ns < t_{PL_RST_PD}≤ 100 ns

The device is in RST mode and does not enter PWR_DN mode.

The device is in RST mode and may or may not enter PWR_DN mode.

NOTE: This setting is not recommended.

100 ns < t_{PL_RST_PD}< 400 ns

The device enters PWR_DN mode and the program registers are reset to default

value.

t_{PL_RST_PD}≥ 400 ns

The devices can be placed into power-down (PWR_DN) mode by pulling the RST/PD pin to a logic low state for

at least 400 ns. The RST/PD pin is asynchronous to the clock; thus, RST/PD can be triggered at any time

regardless of the status of other pins (including the analog input channels). When the device is in power-down

mode, any activity on the digital input pins (apart from the RST/PD pin) is ignored.

The program registers in the device can be reset to their default values (RST) by pulling the RST/PD pin to a

logic low state for no longer than 100 ns. This input is asynchronous to the clock. When RST/PD is pulled back

to a logic high state, the devices are placed in normal mode. One valid write operation must be executed on the

program register in order to configure the device, followed by an appropriate command (AUTO_RST or MAN) to

initiate conversions.

When the RST/PD pin is pulled back to a logic high level, the devices wake-up in a default state in which the

program registers are reset to their default values.

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8.4.1.2 Data Acquisition Example

This section provides an example of how a host processor can use the device interface to configure the device

internal registers as well as convert and acquire data for sampling a particular input channel. The timing diagram

shown in Figure 91 provides further details.

Sample

N

Sample

N + 1

CS

23

24

26

1

2

14

15

16

17

18

25

27

28

29

7

8

9

SCLK

30

31

32

Data from sample N

D14

D6

D5

D4

D3

D2

D1

D0

D15

D9

D8

D7

X

SDO

SDI

B14

B9

B8

B7

B2

B15

B1

B0

B3

X X X X X X X X

B10

1

2

3

4

Figure 91. Device Operation Using the Serial Interface Timing Diagram

There are four events shown in Figure 91. These events are described below:

•

Event 1: The host initiates a data conversion frame through a falling edge of the CS signal. The analog input

signal at the instant of the CS falling edge is sampled by the ADC and conversion is performed using an

internal oscillator clock. The analog input channel converted during this frame is selected in the previous data

frame. The internal register settings of the device for the next conversion can be input during this data frame

using the SDI and SCLK inputs. Initiate SCLK at this instant and latch data on the SDI line into the device on

every SCLK falling edge for the next 16 SCLK cycles. At this instant, SDO goes low because the device does

not output internal conversion data on the SDO line during the first 16 SCLK cycles.

•

Event 2: During the first 16 SCLK cycles, the device completes the internal conversion process and data are

now ready within the converter. However, the device does not output data bits on SDO until the 16th falling

edge appears on the SCLK input. Because the ADC conversion time is fixed (the maximum value is given in

the Electrical Characteristics table), the 16th SCLK falling edge must appear after the internal conversion is

over, otherwise data output from the device is incorrect. Therefore, the SCLK frequency cannot exceed a

maximum value, as provided in the Timing Requirements: Serial Interface table.

Event 3: At the 16th falling edge of the SCLK signal, the device reads the LSB of the input word on the SDI

line. The device does not read anything from the SDI line for the remaining data frame. On the same edge,

the MSB of the conversion data is output on the SDO line and can be read by the host processor on the

subsequent falling edge of the SCLK signal. For 16 bits of output data, the LSB can be read on the 32nd

SCLK falling edge. The SDO outputs 0 on subsequent SCLK falling edges until the next conversion is

initiated.

Event 4: When the internal data from the device is received, the host terminates the data frame by

deactivating the CS signal to high. The SDO output goes into a Hi-Z state until the next data frame is initiated,

as explained in Event 1.

8.4.1.3 Host-to-Device Connection Topologies

The digital interface of the ADS8684A and ADS8688A offers a lot of flexibility in the ways that a host controller

can exchange data or commands with the device. A typical connection between a host controller and a stand-

alone device is illustrated in Figure 89. However, there are applications that require multiple ADCs but the host

controller has limited interfacing capability. This section describes two connection topologies that can be used to

address the requirements of such applications.

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8.4.1.3.1 Daisy-Chain Topology

A typical connection diagram showing multiple devices in daisy-chain mode is shown in Figure 92. The CS,

SCLK, and SDI inputs of all devices are connected together and controlled by a single CS, SCLK, and SDO pin

of the host controller, respectively. The DAISY₁input pin of the first ADC in the chain is connected to DGND, the

SDO₁output pin is connected to the DAISY₂input of ADC₂, and so forth. The SDO_Npin of the Nth ADC in the

chain is connected to the SDI pin of the host controller. The devices do not require any special hardware or

software configuration to enter daisy-chain mode.

Host Controller

SDI

SDO

CS

SCLK

CS

SCLK SDI

CS

SCLK SDI

CS

SCLK SDI

DAISY₂

SDO₂

DAISY₁

SDO₁

DAISY_N

SDO_N

DGND

ADC₁

ADC₂

ADC_N

Figure 92. Daisy-Chain Connection Schematic

A typical timing diagram for three devices connected in daisy-chain mode is shown in Figure 93.

Sample

N

Sample

N + 1

t_S

CS

1

2

15

16

17

18

33

34

49

50

31

32

47

48

63

64

SCLK

SDI

X

B14

B2

B1

B0

X

B15

X

SDO₁,

DAISY₂

{D15}₁{D14}₁

{D15}₂{D14}₂

{D15}₃{D14}₃

{D1}₁{D0}₁

SDO₂,

DAISY₃

{D1}₂{D0}₂{D15}₁{D14}₁

{D1}₁{D0}₁

{D15}₂{D14}₂

{D1}₃{D0}₃

{D1}₂{D0}₂{D15}₁{D14}₁

{D1}₁{D0}₁

SDO₃

Data from Sample N

ADC₃

Data from Sample N

ADC₂

Data from Sample N

ADC₁

Figure 93. Three Devices Connected in Daisy-Chain Mode Timing Diagram

At the falling edge of the CS signal, all devices sample the input signal at their respective selected channels and

enter into conversion phase. For the first 16 SCLK cycles, the internal register settings for the next conversion

can be entered using the SDI line that is common to all devices in the chain. During this time period, the SDO

outputs for all devices remain low. At the end of conversion, every ADC in the chain loads its own conversion

result into an internal 16-bit shift register. At the 16th SCLK falling edge, every ADC in the chain outputs the MSB

bit on its own SDO output pin. On every subsequent SCLK falling edge, the internal shift register of each ADC

latches the data available on its DAISY pin and shifts out the next bit of data on its SDO pin. Therefore, the

digital host receives the data of ADC_N, followed by the data of ADC_N–1, and so forth (in MSB-first fashion). In

total, a minimum of 16 × N SCLK falling edges are required to capture the outputs of all N devices in the chain.

This example uses three devices in a daisy-chain connection, so 3 × 16 = 48 SCLK cycles are required to

capture the outputs of all devices in the chain along with the 16 SCLK cycles to input the register settings for the

next conversion, resulting in a total of 64 SCLK cycles for the entire data frame. Note that the overall throughput

of the system is proportionally reduced with the number of devices connected in a daisy-chain configuration.

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The following points must be noted about the daisy-chain configuration illustrated in Figure 92:

•

The SDI pins for all devices are connected together so each device operates with the same internal

configuration. This limitation can be overcome by spending additional host controller resources to control the

CS or SDI input of devices with unique configurations.

•

If the number of devices connected in daisy-chain is more than four, loading increases on the shared output

lines from the host controller (CS, SDO, and SCLK). This increased loading can lead to digital timing errors.

This limitation can be overcome by using digital buffers on the shared outputs from the host controller before

feeding the shared digital lines into additional devices.

8.4.1.3.2 Star Topology

A typical connection diagram showing multiple devices in the star topology is shown in Figure 94. The SDI and

SCLK inputs of all devices are connected together and are controlled by a single SDO and SCLK pin of the host

controller, respectively. Similarly, the SDO outputs of all devices are tied together and connected to the SDI input

pin of the host controller. The CS input pin of each device is individually controlled by separate CS control lines

from the host controller.

CS₁

CS₂

CS

SCLK

CS_N

SDO

SDI

ADC₁

CS

SCLK

SDI

SDO

SDI

ADC₂

CS

SCLK

SDI

SDO

SCLK

ADC_N

Figure 94. Star Topology Connection Schematic

The timing diagram for a typical data frame in the star topology is the same as in a stand-alone device operation,

as illustrated in Figure 91. The data frame for a particular device starts with the falling edge of the CS signal and

ends when the CS signal goes high. Because the host controller provides separate CS control signals for each

device in this topology, the user can select the devices in any order and initiate a conversion by bringing down

the CS signal for that particular device. As explained in Figure 91, when CS goes high at the end of each data

frame, the SDO output of the device is placed into a Hi-Z state. Therefore, the shared SDO line in the star

topology is controlled only by the device with an active data frame (CS is low). In order to avoid any conflict

related to multiple devices driving the SDO line at the same time, ensure that the host controller pulls down the

CS signal for only one device at any particular time.

TI recommends connecting a maximum of four devices in the star topology. Beyond that, loading may increase

on the shared output lines from the host controller (SDO and SCLK). This loading can lead to digital timing

errors. This limitation can be overcome by using digital buffers on the shared outputs from the host controller

before being fed into additional devices.

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8.4.2 Device Modes

The ADS8684A and ADS8688A support multiple modes of operation that are software programmable. After

powering up, the device is placed into idle mode and does not perform any function until a command is received

from the user. Table 6 lists all commands to enter the different modes of the device. After power-up, the program

registers wake up with the default values and require appropriate configuration settings before performing any

conversion. The diagram in Figure 95 explains how to switch the device from one mode of operation to another.

RESET

(RST)

Program Registers

are set to default

values

RST

NO_OP

IDLE

Device waits for a

valid command to

initiate conversion

MAN_Ch_n

NO_OP

MANUAL

Channel n

(MAN_Ch_n)

STANDBY

(STDBY)

MAN_Ch_n / AUTO_RST

STDBY / PWR_DN / PROG

AUTO

Ch. Scan

(AUTO)

POWER

DOWN

(PWR_DN)

PROGRAM

REGISTER

(PROG)

AUTO Seq.

RESET

(AUTO_RST)

PWR_DN

PROG

NO_OP

IDLE

AUTO_RST

Figure 95. State Transition Diagram

8.4.2.1 Continued Operation in the Selected Mode (NO_OP)

Holding the SDI line low continuously (equivalent to writing a 0 to all 16 bits) during device operation continues

device operation in the last selected mode (STDBY, PWR_DN, AUTO_RST, or MAN_Ch_n). In this mode, the

device follows the same settings that are already configured in the program registers.

If a NO_OP condition occurs when the device is performing any read or write operation in the program register

(PROG mode), then the device retains the current settings of the program registers. The device goes back to

IDLE mode and waits for the user to enter a proper command to execute the program register read or write

configuration.

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8.4.2.2 Frame Abort Condition (FRAME_ABORT)

As explained in the Data Acquisition Example section, the device digital interface is designed such that each data

frame starts with a falling edge of the CS signal. During the first 16 SCLK cycles, the device reads the 16-bit

command word on the SDI line. The device waits to execute the command until the last bit of the command is

received, which is latched on the 16th SCLK falling edge. During this operation, the CS signal must stay low. If

the CS signal goes high for any reason before the data transmission is complete, the device goes into an

INVALID state and waits for a proper command to be written. This condition is called the FRAME_ABORT

condition. When the device is operating in this INVALID mode, any read operation on the device returns invalid

data on the SDO line. The output of the ALARM pin will continue to reflect the status of input signal on the

previously selected channel.

8.4.2.3 STANDBY Mode (STDBY)

The devices support a low-power standby mode (STDBY) in which only part of the circuit is powered down. The

internal reference and buffer is not powered down, and therefore, the devices can be quickly powered up in 20

µs on exiting the STDBY mode. When the device comes out of STDBY mode, the program registers are not

reset to the default values.

To enter STDBY mode, execute a valid write operation to the command register with a STDBY command of

8200h, as shown in Figure 96. The command is executed and the device enters STDBY mode on the next CS

rising edge following this write operation. The device remains in STDBY mode if no valid conversion command

(AUTO_RST or MAN_Ch_n) is executed and SDI remains low (see the Continued Operation in the Selected

Mode section) during the subsequent data frames. When the device operates in STDBY mode, the program

register settings can be updated (as explained in the Program Register Read/Write Operation section) using 16

SCLK cycles. However, if 32 complete SCLK cycles are provided, then the device returns invalid data on the

SDO line because there is no ongoing conversion in STDBY mode. The program register read operation can

take place normally during this mode.

Sample N

Enters STDBY on

CS Rising Edge

CS can go high immediately after Standby

command or after reading frame data.

CS

16

17

16

1

2

14

15

18

30

31

32

1

2

14

15

SCLK

Stays in STDBY

if SDI is Low in a

Data Frame

X

STDBY Command ± 8200h

X

SDI

Data from Sample N

D14

D2

D1

D0

D15

D3

SDO

Figure 96. Enter and Remain in STDBY Mode Timing Diagram

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In order to exit STDBY mode a valid 16-bit write command must be executed to enter auto (AUTO_RST) or

manual (MAN_CH_n) scan mode, as shown in Figure 97. The device starts exiting STDBY mode on the next CS

rising edge. At the next CS falling edge, the device samples the analog input at the channel selected by the

MAN_CH_n command or the first channel of the AUTO_RST mode sequence. To ensure that the input signal is

sampled correctly, keep the minimum width of the CS signal at 20 µs after exiting STDBY mode so the device

internal circuitry can be fully powered up and biased properly before taking the sample. The data output for the

selected channel can be read during the same data frame, as explained in Figure 91.

Device exits

STDBY Mode on

CS Rising Edge

CS

Min width of CS HIGH = 20µs

for valid sample

16

1

2

3

4

5

12

13

14

15

6

7

8

9

10

11

SCLK

AUTO_RST Command

MAN_CH_n Command

SDI

SDO

Figure 97. Exit STDBY Mode Timing Diagram

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8.4.2.4 Power-Down Mode (PWR_DN)

The devices support a hardware and software power-down mode (PWR_DN) in which all internal circuitry is

powered down, including the internal reference and buffer. A minimum time of 15 ms is required for the device to

power up and convert the selected analog input channel after exiting PWR_DN mode, if the device is operating

in the internal reference mode (REFSEL = 0). The hardware power mode for the device is explained in the

RST/PD (Input) section. The primary difference between the hardware and software power-down modes is that

the program registers are reset to default values when the devices wake up from hardware power-down, but the

previous settings of the program registers are retained when the devices wake up from software power-down.

To enter PWR_DN mode using software, execute a valid write operation on the command register with a

software PWR_DN command of 8300h, as shown in Figure 98. The command is executed and the device enters

PWR_DN mode on the next CS rising edge following this write operation. The device remains in PWR_DN mode

if no valid conversion command (AUTO_RST or MAN_Ch_n) is executed and SDI remains low (see the

Continued Operation in the Selected Mode section) during the subsequent data frames. When the device

operates in PWR_DN mode, the program register settings can be updated (as explained in the Program Register

Read/Write Operation section) using 16 SCLK cycles. However, if 32 complete SCLK cycles are provided, then

the device returns invalid data on the SDO line because there is no ongoing conversion in PWR_DN mode. The

program register read operation can take place normally during this mode.

Sample N

Enters PWR_DN on

CS Rising Edge

CS can go high immediately after PWR_DN

command or after reading frame data.

CS

16

17

16

1

2

14

15

18

30

31

32

1

2

14

15

SCLK

Stays in PWR_DN

if SDI is Low in a

Data Frame

X

PWR_DN Command ± 8300h

X

SDI

Data from Sample N

D14

D2

D1

D0

D15

D3

SDO

Figure 98. Enter and Remain in PWR_DN Mode Timing Diagram

In order to exit from PWR_DN mode a valid 16-bit write command must be executed, as shown in Figure 99. The

device comes out of PWR_DN mode on the next CS rising edge. For operation in internal reference mode

(REFSEL = 0), 15 ms are required for the device to power-up the reference and other internal circuits and settle

to the required accuracy before valid conversion data are output for the selected input channel.

First 16-bit accurate data

frame after recovery from

PWR_DN mode

Device exits PWR_DN Mode, but

waits 15ms for 16-bit settling

CS

16

1

2

3

4

5

12

13

14

15

6

7

8

9

10

11

SCLK

AUTO_RST Command

MAN_CH_n Command

SDI

SDO

Invalid

Data

Figure 99. Exit PWR_DN Mode Timing Diagram

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8.4.2.5 Auto Channel Enable with Reset (AUTO_RST)

The devices can be programmed to scan the input signal on all analog channels automatically by writing a valid

auto channel sequence with a reset (AUTO_RST, A000h) command in the command register, as explained in

Figure 100. As shown in Figure 100, the CS signal can be pulled high immediately after the AUTO_RST

command or after reading the output data of the frame. However, in order to accurately acquire and convert the

input signal on the first selected channel in the next data frame, the command frame must be a complete frame

of 32 SCLK cycles.

The sequence of channels for the automatic scan can be configured by the AUTO SCAN sequencing control

register (01h to 02h) in the program register; see the Program Register Map section. In this mode, the devices

continuously cycle through the selected channels in ascending order, beginning with the lowest channel and

converting all channels selected in the program register. On completion of the sequence, the devices return to

the lowest count channel in the program register and repeat the sequence. The input voltage range for each

channel in the auto-scan sequence can be configured by setting the Range Select Registers of the program

registers.

Samples 2^ndCh. of

Auto-Ch Sequence

Sample N

Enters AUTO_RST Mode on CS Rising Edge

Samples 1^stCh. of Auto-Ch Sequence

CS can go high immediately after AUTO_RST

command or after reading frame data.

CS

16

17

16

32

1

2

14

15

18

30

31

32

1

2

14

15

31

SCLK

Stays in AUTO_RST Mode if

SDI is Low in a Data Frame

X

AUTO_RST Command ± A000h

X

SDI

Data from Sample N

Data from 1^stCh of Seq.

D14

D2

D1

D0

D15

D3

SDO

Figure 100. Enter AUTO_RST Mode Timing Diagram

The devices remain in AUTO_RST mode if no other valid command is executed and SDI is kept low (see the

Continued Operation in the Selected Mode (NO_OP) section) during subsequent data frames. If the AUTO_RST

command is executed again at any time during this mode of operation, then the sequence of the scanned

channels is reset. The devices return to the lowest count channel of the auto-scan sequence in the program

register and repeat the sequence. The timing diagram in Figure 101 shows this behavior using an example in

which channels 0 to 2 are selected in the auto sequence. For switching between AUTO_RST mode and

MAN_Ch_n mode; see the Channel Sequencing Modes section.

Sample

N

Ch 0

Sample

Ch 1

Sample

Ch 2

Sample

Ch 0

Sample

CS

SCLK

SDI

AUTO_RST

xxxx

0000h

xxxx

0000h

xxxx

AUTO_RST

xxxx

0000h

xxxx

SDO

Sample N Data

Ch 0 Data

Ch 1 Data

Ch 2 Data

Ch 0 Data

Based on Previous

Mode Setting

AUTO_RST Mode

(Channel sequence restarted from

AUTO_RST Mode

(Channels 0-2 are selected in sequence.)

lowest count.)

Figure 101. Device Operation Example in AUTO_RST Mode

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8.4.2.6 Manual Channel n Select (MAN_Ch_n)

The devices can be programmed to convert a particular analog input channel by operating in manual channel n

scan mode (MAN_Ch_n). This programming is done by writing a valid manual channel n select command

(MAN_Ch_n) in the command register, as shown in Figure 102. As shown in Figure 102, the CS signal can be

pulled high immediately after the MAN_Ch_n command or after reading the output data of the frame. However, in

order to accurately acquire and convert the input signal on the next channel, the command frame must be a

complete frame of 32 SCLK cycles. See Table 6 for a list of commands to select individual channels during

MAN_Ch_n mode.

Sample N

2^ndSample of Manual Ch. n

Enters MAN_Ch_n Mode on CS Rising Edge

1^stSample of Manual Channel N

CS can go high immediately after MAN_Ch_n

command or after reading frame data.

CS

16

17

16

32

1

2

14

15

18

30

31

32

1

2

14

15

31

SCLK

Stays in MAN_Ch_n Mode if

SDI is Low in a Data Frame

X

MAN_Ch_n Command

X

SDI

Data from Sample N

Sample 1 of Channel n

D14

D2

D1

D0

D15

D3

SDO

Figure 102. Enter MAN_Ch_n Scan Mode Timing Diagram

The manual channel n select command (MAN_Ch_n) is executed and the devices sample the analog input on

the selected channel on the CS falling edge of the next data frame following this write operation. The input

voltage range for each channel in the MAN_Ch_n mode can be configured by setting the Range Select Registers

in the program registers. The device continues to sample the analog input on the same channel if no other valid

command is executed and SDI is kept low (see the Continued Operation in the Selected Mode (NO_OP) section)

during subsequent data frames. The timing diagram in Figure 103 shows this behavior using an example in

which channel 1 is selected in the manual sequencing mode. For switching between MAN_Ch_n mode and

AUTO_RST mode; see the Channel Sequencing Modes section.

Sample

N

Ch 1

Sample

Ch 1

Sample

Ch 1

Sample

Ch 3

Sample

CS

SCLK

SDI

MAN_Ch_1

xxxx

0000h

xxxx

0000h

xxxx

MAN_Ch_3

xxxx

0000h

xxxx

SDO

Sample N Data

Ch 1 Data

Ch 3 Data

Based on Previous

Mode Setting

MAN_Ch_n Mode

(Ch 1 is selected and device continuously converts Ch 1 if NO_OP command is provided)

MAN_Ch_n Mode

(Transition from Ch1 to Ch 3)

Figure 103. Device Operation in MAN_Ch_n Mode

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8.4.2.7 Channel Sequencing Modes

The devices offer two channel sequencing modes: AUTO_RST and MAN_Ch_n.

In AUTO_RST mode, the channel number automatically increments in every subsequent frame. As explained in

the Auto-Scan Sequencing Control Registers section, the analog inputs can be selected for an automatic scan

with a register setting. The device automatically scans only the selected analog inputs in ascending order. The

unselected analog input channels can also be powered down for optimizing power consumption in this mode of

operation. The auto-mode sequence can be reset at any time during an automatic scan (using the AUTO_RST

command). When the reset command is received, the ongoing auto-mode sequence is reset and restarts from

the lowest selected channel in the sequence.

In MAN_Ch_n mode, the same input channel is selected during every data conversion frame. The input

command words to select individual analog channels in MAN_Ch_n mode are listed in Table 6. If a particular

input channel is selected during a data frame, then the analog inputs on the same channel are sampled during

the next data frame. Figure 104 shows the SDI command sequence for transitions from AUTO_RST to

MAN_Ch_n mode.

Ch 0

Ch 5

Ch 1

Ch 3

Sample

CS

SCLK

SDI

0000h

xxxx

MAN_Ch_1

xxxx

MAN_Ch_3

xxxx

MAN_Ch_n

xxxx

SDO

Ch 0 Data

Ch 5 Data

Ch 1 Data

Ch 3 Data

AUTO_RST Mode

MAN_Ch_n Mode

Figure 104. Transitioning from AUTO_RST to MAN_Ch_n Mode

(Channels 0 and 5 are Selected for Auto Sequence)

Figure 105 shows the SDI command sequence for transitions from MAN_Ch_n to AUTO_RST mode. Note that

each SDI command is executed on the next CS falling edge. A RST command can be issued at any instant

during any channel sequencing mode, after which the device is placed into a default power-up state in the next

data frame.

Sample

N

Ch 2

Sample

Ch 0

Sample

Ch 5

Sample

CS

SCLK

SDI

MAN_Ch_2

xxxx

AUTO_RST

xxxx

0000h

xxxx

0000h

xxxx

SDO

Sample N Data

Ch 2 Data

Ch 0 Data

Ch 5 Data

Based on Previous

Mode Setting

MAN_Ch_n Mode

AUTO_RST Mode

Figure 105. Transitioning from MAN_Ch_n to AUTO_RST Mode

(Channels 0 and 5 are Selected for Auto Sequence)

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8.4.2.8 Reset Program Registers (RST)

The devices support a hardware and software reset (RST) mode in which all program registers are reset to their

default values. The devices can be put into RST mode using a hardware pin, as explained in the RST/PD (Input)

section.

The device program registers can be reset to their default values during any data frame by executing a valid

write operation on the command register with a RST command of 8500h, as shown in Figure 106. The device

remains in RST mode if no valid conversion command (AUTO_RST or MAN_Ch_n) is executed and SDI remains

low (see the Continued Operation in the Selected Mode (NO_OP) section) during the subsequent data frames.

When the device operates in RST mode, the program register settings can be updated (as explained in the

Program Register Read/Write Operation section) using 16 SCLK cycles. However, if 32 complete SCLK cycles

are provided, then the device returns invalid data on the SDO line because there is no ongoing conversion in

RST mode. The values of the program register can be read normally during this mode. A valid AUTO_RST or

MAN_CH_n channel selection command must be executed for initiating a conversion on a particular analog

channel using the default program register settings.

All Program

Registers are Reset

Sample N

to Default Values on

CS Rising Edge

CS can go high immediately after RST

command or after reading frame data.

CS

16

17

1

2

13

14

15

18

30

31

32

3

4

5

SCLK

X

Reset Program Registers (RST) ± 8500h

X

SDI

Data from Sample N

D14

D2

D1

D0

D15

D3

SDO

Figure 106. Reset Program Registers (RST) Timing Diagram

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8.5 Register Maps

The internal registers of the ADS8684A and ADS8688A are categorized into two categories: command registers

and program registers.

The command registers are used to select the channel sequencing mode (AUTO_RST or MAN_Ch_n), configure

the device in standby (STDBY) or power-down (PWR_DN) mode, and reset (RST) the program registers to their

default values.

The program registers are used to select the sequence of channels for AUTO_RST mode, select the SDO output

format, control input range settings for individual channels, control the ALARM feature, reading the alarm flags,

and programming the alarm thresholds for each channel.

8.5.1 Command Register Description

The command register is a 16-bit, write-only register that is used to set the operating modes of the ADS8684A

and ADS8688A. The settings in this register are used to select the channel sequencing mode (AUTO_RST or

MAN_Ch_n), configure the device in standby (STDBY) or power-down (PWR_DN) mode, and reset (RST) the

program registers to their default values. All command settings for this register are listed in Table 6. During

power-up or reset, the default content of the command register is all 0's and the device waits for a command to

be written before being placed into any mode of operation. See Figure 1 for a typical timing diagram for writing a

16-bit command into the device. The device executes the command at the end of this particular data frame when

the CS signal goes high.

Table 6. Command Register Map

MSB BYTE

LSB BYTE

B[7:0]

COMMAND

(Hex)

REGISTER

OPERATION IN NEXT FRAME

B15 B14 B13 B12 B11 B10 B9

B8

Continued Operation

(NO_OP)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0000 0000

0000h

8200h

8300h

8500h

A000h

C000h

C400h

C800h

CC00h

D000h

D400h

D800h

DC00h

E000h

Continue operation in previous mode

Device is placed into standby mode

Device is powered down

Standby

(STDBY)

0

1

0

Power Down

(PWR_DN)

Reset program registers

(RST)

Program register is reset to default

Auto mode enabled following a reset

Channel 0 input is selected

Channel 1 input is selected

Channel 2 input is selected

Channel 3 input is selected

Channel 4 input is selected

Channel 5 input is selected

Channel 6 input is selected

Channel 7 input is selected

AUX channel input is selected

Auto Ch. Sequence with Reset

(AUTO_RST)

Manual Ch 0 Selection

(MAN_Ch_0)

Manual Ch 1 Selection

(MAN_Ch_1)

Manual Ch 2 Selection

(MAN_Ch_2)

Manual Ch 3 Selection

(MAN_Ch_3)

Manual Ch 4 Selection

(MAN_Ch_4)⁽¹⁾

Manual Ch 5 Selection

(MAN_Ch_5)

Manual Ch 6 Selection

(MAN_Ch_6)

Manual Ch 7 Selection

(MAN_Ch_7)

Manual AUX Selection

(MAN_AUX)

(1) Shading indicates bits or registers not included in the 4-channel version of the device.

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8.5.2 Program Register Description

The program register is a 16-bit register used to set the operating modes of the ADS8684A and ADS8688A. The

settings in this register are used to select the channel sequence for AUTO_RST mode, configure the device ID in

daisy-chain mode, select the SDO output format, control input range settings for individual channels, control the

ALARM feature, reading the alarm flags, and programming the alarm thresholds for each channel. All program

settings for this register are listed in Table 9. During power-up or reset, the different program registers in the

device wake up with their default values and the device waits for a command to be written before being placed

into any mode of operation.

8.5.2.1 Program Register Read/Write Operation

The program register is a 16-bit read or write register. There must be a minimum of 24 SCLKs after the CS

falling edge for any read or write operation to the program registers. When CS goes low, the SDO line goes low

as well. The device receives the command (see Table 7 and Table 8) through SDI where the first seven bits (bits

15-9) represent the register address and the eighth bit (bit 8) is the write or read instruction.

For a write cycle, the next eight bits (bits 7-0) on SDI are the desired data for the addressed register. Over the

next eight SCLK cycles, the device outputs this 8-bit data that is written into the register. This data readback

allows verification to determine if the correct data are entered into the device. A typical timing diagram for a

program register write cycle is shown in Figure 107.

Table 7. Write Cycle Command Word

REGISTER ADDRESS

(Bits 15-9)

WR/RD

(Bit 8)

DATA

(Bits 7-0)

SDI

ADDR[6:0]

1

DIN[7:0]

Sample

N

CS

24

16

23

15

17

18

1

2

6

7

8

9

10

SCLK

SDI

DIN [7:0]

X X X X

ADDR [6:0]

WR

Data written into register, DIN [7:0]

SDO

Figure 107. Program Register Write Cycle Timing Diagram

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For a read cycle, the next eight bits (bits 7-0) on SDI are don’t care bits and SDO stays low. From the 16th SCLK

falling edge and onwards, SDO outputs the 8-bit data from the addressed register during the next eight clocks, in

MSB-first fashion. A typical timing diagram for a program register read cycle is shown in Figure 108.

Table 8. Read Cycle Command Word

REGISTER ADDRESS

(Bits 15-9)

WR/RD

(Bit 8)

DATA

(Bits 7-0)

SDI

ADDR[6:0]

0000 000

0

XXXXX

SDO

DOUT[7:0]

CS

24

16

23

15

17

18

1

2

6

7

8

9

10

SCLK

SDI

X X X X X X

ADDR [6:0]

RD

DOUT [7:0]

SDO

Figure 108. Program Register Read Cycle Timing Diagram

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8.5.2.3 Program Register Descriptions

8.5.2.3.1 Auto-Scan Sequencing Control Registers

In AUTO_RST mode, the device automatically scans the preselected channels in ascending order with a new

channel selected for every conversion. Each individual channel can be selectively included in the auto channel

sequencing. For channels not selected for auto sequencing, the analog front-end circuitry can be individually

powered down.

8.5.2.3.1.1 Auto-Scan Sequence Enable Register (address = 01h)

This register selects individual channels for sequencing in AUTO_RST mode. The default value for this register is

FFh, which implies that in default condition all channels are included in the auto-scan sequence. If no channels

are included in the auto sequence (that is, the value for this register is 00h), then channel 0 is selected for

conversion by default.

Figure 109. AUTO_SEQ_EN Register

7

6

5

4

3

2

1

0

CH7_EN⁽¹⁾

CH6_EN

R/W-1h

CH5_EN

R/W-1h

CH4_EN

R/W-1h

CH3_EN

R/W-1h

CH2_EN

R/W-1h

CH1_EN

R/W-1h

CH0_EN

R/W-1h

LEGEND: R/W = Read/Write; -n = value after reset

(1) Shading indicates bits or registers that are not included in the 4-channel version of the device. A write operation on any of these bits or

registers has no effect on device behavior. A read operation on any of these bits or registers outputs all 1's on the SDO line.

Table 10. AUTO_SEQ_EN Field Descriptions

Bit

Field

Type

Reset

Description

7

CH7_EN

R/W

1h

Channel 7 enable.

0 = Channel 7 is not selected for sequencing in AUTO_RST mode

1 = Channel 7 is selected for sequencing in AUTO_RST mode

6

5

4

3

2

1

0

CH6_EN

CH5_EN

CH4_EN

CH3_EN

CH2_EN

CH1_EN

CH0_EN

R/W

1h

Channel 6 enable.

0 = Channel 6 is not selected for sequencing in AUTO_RST mode

1 = Channel 6 is selected for sequencing in AUTO_RST mode

Channel 5 enable.

0 = Channel 5 is not selected for sequencing in AUTO_RST mode

1 = Channel 5 is selected for sequencing in AUTO_RST mode

Channel 4 enable.

0 = Channel 4 is not selected for sequencing in AUTO_RST mode

1 = Channel 4 is selected for sequencing in AUTO_RST mode

Channel 3 enable.

0 = Channel 3 is not selected for sequencing in AUTO_RST mode

1 = Channel 3 is selected for sequencing in AUTO_RST mode

Channel 2 enable.

0 = Channel 2 is not selected for sequencing in AUTO_RST mode

1 = Channel 2 is selected for sequencing in AUTO_RST mode

Channel 1 enable.

0 = Channel 1 is not selected for sequencing in AUTO_RST mode

1 = Channel 1 is selected for sequencing in AUTO_RST mode

Channel 0 enable.

0 = Channel 0 is not selected for sequencing in AUTO_RST mode

1 = Channel 0 is selected for sequencing in AUTO_RST mode

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8.5.2.3.1.2 Channel Power Down Register (address = 02h)

This register powers down individual channels that are not included for sequencing in AUTO_RST mode. The

default value for this register is 00h, which implies that in default condition all channels are powered up. If all

channels are powered down (that is, the value for this register is FFh), then the analog front-end circuits for all

channels are powered down and the output of the ADC contains invalid data. If the device is in MAN-Ch_n mode

and the selected channel is powered down, then the device yields invalid output that can also trigger a false

alarm condition.

Figure 110. Channel Power Down Register

7

6

5

4

3

2

1

0

CH7_PD⁽¹⁾

CH6_PD

R/W-0h

CH5_PD

R/W-0h

CH4_PD

R/W-0h

CH3_PD

R/W-0h

CH2_PD

R/W-0h

CH1_PD

R/W-0h

CH0_PD

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

(1) Shading indicates bits or registers that are not included in the 4-channel version of the device. A write operation on any of these bits or

registers has no effect on device behavior. A read operation on any of these bits or registers outputs all 1's on the SDO line.

Table 11. Channel Power Down Register Field Descriptions

Bit

Field

Type

Reset

Description

7

CH7_PD

R/W

0h

Channel 7 power-down.

0 = The analog front-end on channel 7 is powered up and channel 7 can be

included in the AUTO_RST sequence

1 = The analog front-end on channel 7 is powered down and channel 7

cannot be included in the AUTO_RST sequence

6

5

4

3

2

1

0

CH6_PD

CH5_PD

CH4_PD

CH3_PD

CH2_PD

CH1_PD

CH0_PD

R/W

0h

Channel 6 power-down.

0 = The analog front-end on channel 6 is powered up and channel 6 can be

included in the AUTO_RST sequence

1 = The analog front-end on channel 6 is powered down and channel 6

cannot be included in the AUTO_RST sequence

Channel 5 power-down.

0 = The analog front-end on channel 5 is powered up and channel 5 can be

included in the AUTO_RST sequence

1 = The analog front-end on channel 5 is powered down and channel 5

cannot be included in the AUTO_RST sequence

Channel 4 power-down.

0 = The analog front-end on channel 4 is powered up and channel 4 can be

included in the AUTO_RST sequence

1 = The analog front-end on channel 4 is powered down and channel 4

cannot be included in the AUTO_RST sequence

Channel 3 power-down.

0 = The analog front-end on channel 3 is powered up and channel 3 can be

included in the AUTO_RST sequence

1 = The analog front end on channel 3 is powered down and channel 3

cannot be included in the AUTO_RST sequence

Channel 2 power-down.

0 = The analog front end on channel 2 is powered up and channel 2 can be

included in the AUTO_RST sequence

1 = The analog front end on channel 2 is powered down and channel 2

cannot be included in the AUTO_RST sequence

Channel 1 power-down.

0 = The analog front end on channel 1 is powered up and channel 1 can be

included in the AUTO_RST sequence

1 = The analog front end on channel 1 is powered down and channel 1

cannot be included in the AUTO_RST sequence

Channel 0 power-down.

0 = The analog front end on channel 0 is powered up and channel 0 can be

included in the AUTO_RST sequence

1 = The analog front end on channel 0 is powered down and channel 0

cannot be included in the AUTO_RST sequence

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8.5.2.3.2 Device Features Selection Control Register (address = 03h)

The bits in this register can be used to configure the device ID for daisy-chain operation, enable the ALARM

feature, and configure the output bit format on SDO.

Figure 111. Feature Select Register

7

6

5

0

4

3

0

2

1

0

DEV[1:0]

R/W-0h

ALARM_EN

R/W-0h

SDO[2:0]

R/W-0h

R-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 12. Feature Select Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

DEV[1:0]

R/W

0h

Device ID bits.

00 = ID for device 0 in daisy-chain mode

01 = ID for device 1 in daisy-chain mode

10 = ID for device 2 in daisy-chain mode

11 = ID for device 3 in daisy-chain mode

5

4

0

R

0h

Must always be set to 0

R/W

ALARM feature enable.

0 = ALARM feature is disabled

1 = ALARM feature is enabled

3

0

R

0h

Must always be set to 0

2-0

SDO[2:0]

R/W

SDO data format bits (see Table 13).

Table 13. Description of Program Register Bits for SDO Data Format

OUTPUT FORMAT

BITS 8-5

SDO FORMAT

SDO[2:0]

BEGINNING OF THE

OUTPUT BIT STREAM

BITS 24-9

BITS 4-3

BITS 2-0

16th SCLK falling edge,

no latency

Conversion result for selected

channel (MSB-first)

000

001

010

011

SDO pulled low

16th SCLK falling edge,

no latency

Conversion result for selected

channel (MSB-first)

Channel

SDO pulled low

address⁽¹⁾

16th SCLK falling edge,

no latency

Conversion result for selected

channel (MSB-first)

Channel

Device

SDO pulled

low

address⁽¹⁾

16th SCLK falling edge,

no latency

Conversion result for selected

channel (MSB-first)

Channel

Device

Input

address⁽¹⁾

range⁽¹⁾

(1) Table 14 lists the bit descriptions for these channel addresses, device addresses, and input range.

Table 14. Bit Description for the SDO Data

BIT

BIT DESCRIPTION

24-9

8-5

16 bits of conversion result for the channel represented in MSB-first format.

Four bits of channel address.

0000 = Channel 0

0001 = Channel 1

0010 = Channel 2

0011 = Channel 3

0100 = Channel 4 (valid only for the ADS8688A)

0101 = Channel 5 (valid only for the ADS8688A)

0110 = Channel 6 (valid only for the ADS8688A)

0111 = Channel 7 (valid only for the ADS8688A)

4-3

2-0

Two bits of device address (mainly useful in daisy-chain mode).

Three LSB bits of input voltage range (see the Range Select Registers section).

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8.5.2.3.3 Range Select Registers (addresses 05h-0Ch)

Address 05h corresponds to channel 0, address 06h corresponds to channel 1, address 07h corresponds to

channel 2, address 08h corresponds to channel 3, address 09h corresponds to channel 4, address 0Ah

corresponds to channel 5, address 0Bh corresponds to channel 6, and address 0Ch corresponds to channel 7.

These registers allow the selection of input ranges for all individual channels (n = 0 to 3 for the ADS8684A and n

= 0 to 7 for the ADS8688A). The default value for these registers is 00h.

Figure 112. Channel n Input Range Registers

7

0

6

0

5

0

4

0

3

2

1

0

Range_CHn[3:0]

R/W-0h

R-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 15. Channel n Input Range Registers Field Descriptions

Bit

7-4

3-0

Field

Type

R

Reset

0h

Description

0

Must always be set to 0

Range_CHn[3:0]

R/W

0h

Input range selection bits for channel n (n = 0 to 3 for the ADS8684A and

n = 0 to 7 for the ADS8688A).

0000 = Input range is set to ±2.5 x V_REF

0001 = Input range is set to ±1.25 x V_REF

0010 = Input range is set to ±0.625 x V_REF

0011 = Input range is set to ±0.3125 x V_REF

1011 = Input range is set to ±0.15625 x V_REF

0101 = Input range is set to 0 to 2.5 x V_REF

0110 = Input range is set to 0 to 1.25 x V_REF

0111 = Input range is set to 0 to 0.625 x V_REF

1111 = Input range is set to 0 to 0.3125 x V_REF

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8.5.2.3.4 Alarm Flag Registers (Read-Only)

The alarm conditions related to individual channels are stored in these registers. The flags can be read when an

alarm interrupt is received on the ALARM pin. There are two types of flag for every alarm: active and tripped.

The active flag is set to 1 under the alarm condition (when data cross the alarm limit) and remains so as long as

the alarm condition persists. The tripped flag turns on the alarm condition similar to the active flag, but remains

set until read. This feature relieves the device from having to track alarms.

8.5.2.3.4.1 ALARM Overview Tripped-Flag Register (address = 10h)

The ALARM overview tripper-flags register contains the logical OR of high or low tripped alarm flags for all eight

channels.

Figure 113. ALARM Overview Tripped-Flag Register

7

6

5

4

3

2

1

0

Tripped Alarm

Flag Ch7⁽¹⁾

Tripped Alarm

Flag Ch6

Tripped Alarm

Flag Ch5

Tripped Alarm

Flag Ch4

Tripped Alarm

Flag Ch3

Tripped Alarm

Flag Ch2

Tripped Alarm

Flag Ch1

Tripped Alarm

Flag Ch0

R-0h

LEGEND: R = Read only; -n = value after reset

(1) Shading indicates bits or registers that are not included in the 4-channel version of the device. A write operation on any of these bits or

registers has no effect on device behavior. A read operation on any of these bits or registers outputs all 1's on the SDO line.

Table 16. ALARM Overview Tripped-Flag Register Field Descriptions

Bit

7

Field

Type

R

Reset

0h

Description

Tripped Alarm Flag Ch7

Tripped Alarm Flag Ch6

Tripped Alarm Flag Ch5

Tripped Alarm Flag Ch4

Tripped Alarm Flag Ch3

Tripped Alarm Flag Ch2

Tripped Alarm Flag Ch1

Tripped Alarm Flag Ch0

Tripped alarm flag for all analog channels at a glance.

Each individual bit indicates a tripped alarm flag status for each

channel, as per the alarm flags register for channels 7 to 0,

respectively.

0 = No alarm detected

1 = Alarm detected

6

R

0h

5

R

0h

4

R

0h

3

R

0h

2

R

0h

1

R

0h

0

R

0h

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8.5.2.3.4.2 Alarm Flag Registers: Tripped and Active (address = 11h to 14h)

There are two alarm thresholds (high and low) per channel, with two flags for each threshold. An active alarm

flag is enabled when an alarm is triggered (when data cross the alarm threshold) and remains enabled as long

as the alarm condition persists. A tripped alarm flag is enabled in the same manner as an active alarm flag, but

remains latched until read. Registers 11h to 14h in the program registers store the active and tripped alarm flags

for all individual eight channels.

Figure 114. ALARM Ch0-3 Tripped-Flag Register (address = 11h)

7

6

5

4

3

2

1

0

Tripped Alarm

Flag Ch0 Low

Tripped Alarm

Flag Ch0 High

Tripped Alarm

Flag Ch1 Low

Tripped Alarm

Flag Ch1 High

Tripped Alarm

Flag Ch2 Low

Tripped Alarm

Flag Ch2 High

Tripped Alarm

Flag Ch3 Low

Tripped Alarm

Flag Ch3 High

R-0h

LEGEND: R = Read only; -n = value after reset

Table 17. ALARM Ch0-3 Tripped-Flag Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Tripped Alarm Flag Ch n

Low or High (n = 0 to 3)

R

0h

Tripped alarm flag high, low for channel n (n = 0 to 3)

Each individual bit indicates an active high or low alarm flag status for

each channel, as per the alarm flags register for channels 0 to 7.

0 = No alarm detected

1 = Alarm detected

Figure 115. ALARM Ch0-3 Active-Flag Register (address = 12h)

7

6

5

4

3

2

1

0

Active Alarm

Flag Ch0 Low

Flag Ch0 High

Flag Ch1 Low

Flag Ch1 High

Flag Ch2 Low

Flag Ch2 High

Flag Ch3 Low

Flag Ch3 High

R-0h

LEGEND: R = Read only; -n = value after reset

Table 18. ALARM Ch0-3 Active-Flag Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Active Alarm Flag Ch n Low

or High (n = 0 to 3)

R

0h

Active alarm flag high, low for channel n (n = 0 to 3)

Each individual bit indicates an active high or low alarm flag status for

each channel, as per the alarm flags register for channels 0 to 7.

0 = No alarm detected

1 = Alarm detected

Figure 116. ALARM Ch4-7 Tripped-Flag Register (address = 13h)⁽¹⁾

7

6

5

4

3

2

1

0

Tripped Alarm

Flag Ch4 Low

Tripped Alarm

Flag Ch4 High

Tripped Alarm

Flag Ch5 Low

Tripped Alarm

Flag Ch5 High

Tripped Alarm

Flag Ch6 Low

Tripped Alarm

Flag Ch6 High

Tripped Alarm

Flag Ch7 Low

Tripped Alarm

Flag Ch7 High

R-0h

LEGEND: R = Read only; -n = value after reset

(1) This register is not included in the 4-channel version of the device. A write operation on this register has no effect on device behavior. A

read operation on this register outputs all 1's on the SDO line.

Table 19. ALARM Ch4-7 Tripped-Flag Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Tripped Alarm Flag Ch n

Low or High (n = 4 to 7)

R

0h

Tripped alarm flag high, low for channel n (n = 4 to 7).

Each individual bit indicates an active high or low alarm flag status for

each channel, as per the alarm flags register for channels 0 to 7.

0 = No alarm detected

1 = Alarm detected

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Figure 117. ALARM Ch4-7 Active-Flag Register (address = 14h)⁽¹⁾

7

6

5

4

3

2

1

0

Active Alarm

Flag Ch4 Low

Flag Ch4 High

Flag Ch5 Low

Flag Ch5 High

Flag Ch6 Low

Flag Ch6 High

Flag Ch7 Low

Flag Ch7 High

R-0h

LEGEND: R = Read only; -n = value after reset

(1) This register is not included in the 4-channel version of the device. A write operation on this register has no effect on device behavior. A

read operation on this register outputs all 1's on the SDO line.

Table 20. ALARM Ch4-7 Active-Flag Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Active Alarm Flag Ch n Low

or High (n = 4 to 7)

R

0h

Active alarm flag high, low for channel n (n = 4 to 7).

Each individual bit indicates an active high or low alarm flag status for

each channel, as per the alarm flags register for channels 0 to 7.

0 = No alarm detected

1 = Alarm detected

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8.5.2.3.5 Alarm Threshold Setting Registers

The ADS8684A and ADS8688A feature individual high and low alarm threshold settings for each channel. Each

alarm threshold is 16 bits wide with 8-bit hysteresis, which is the same for both high and low threshold settings.

This 40-bit setting is accomplished through five 8-bit registers associated with every high and low alarm.

NAME

ADDR

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

3Bh

3Ch

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Ch 0 Hysteresis

CH0_HYST[7:0]

CH0_HT[15:8]

CH0_HT[7:0]

CH0_LT[15:8]

CH0_LT[7:0]

Ch 0 High Threshold MSB

Ch 0 High Threshold LSB

Ch 0 Low Threshold MSB

Ch 0 Low Threshold LSB

Ch 1 Hysteresis

CH1_HYST[7:0]

CH1_HT[15:8]

CH1_HT[7:0]

CH1_LT[15:8]

CH1_LT[7:0]

Ch 1 High Threshold MSB

Ch 1 High Threshold LSB

Ch 1 Low Threshold MSB

Ch 1 Low Threshold LSB

Ch 2 Hysteresis

CH2_HYST[7:0]

CH2_HT[15:8]

CH2_HT[7:0]

CH2_LT[15:8]

CH2_LT[7:0]

Ch 2 High Threshold MSB

Ch 2 High Threshold LSB

Ch 2 Low Threshold MSB

Ch 2 Low Threshold LSB

Ch 3 Hysteresis

CH3_HYST[7:0]

CH3_HT[15:8]

CH3_HT[7:0]

CH3_LT[15:8]

CH3_LT[7:0]

Ch 3 High Threshold MSB

Ch 3 High Threshold LSB

Ch 3 Low Threshold MSB

Ch 3 Low Threshold LSB

Ch 4 Hysteresis⁽¹⁾

CH4_HYST[7:0]

CH4_HT[15:8]

CH4_HT[7:0]

CH4_LT[15:8]

CH4_LT[7:0]

Ch 4 High Threshold MSB

Ch 4 High Threshold LSB

Ch 4 Low Threshold MSB

Ch 4 Low Threshold LSB

Ch 5 Hysteresis

CH5_HYST[7:0]

CH5_HT[15:8]

CH5_HT[7:0]

CH5_LT[15:8]

CH5_LT[7:0]

Ch 5 High Threshold MSB

Ch 5 High Threshold LSB

Ch 5 Low Threshold MSB

Ch 5 Low Threshold LSB

Ch 6 Hysteresis

CH6_HYST[7:0]

CH6_HT[15:8]

CH6_HT[7:0]

CH6_LT[15:8]

CH6_LT[7:0]

Ch 6 High Threshold MSB

Ch 6 High Threshold LSB

Ch 6 Low Threshold MSB

Ch 6 Low Threshold LSB

Ch 7 Hysteresis

CH7_HYST[7:0]

CH7_HT[15:8]

CH7_HT[7:0]

CH7_LT[15:8]

CH7_LT[7:0]

Ch 7 High Threshold MSB

Ch 7 High Threshold LSB

Ch 7 Low Threshold MSB

Ch 7 Low Threshold LSB

(1) Shading indicates bits or registers not included in the 4-channel version of the device.

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Figure 118. Ch n Hysteresis Registers

7

6

5

4

3

2

1

0

CHn_HYST[7:0]

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21. Channel n Hysteresis Register Field Descriptions

(n = 0 to 7 for the ADS8688A; n = 0 to 3 for the ADS8684A)

Bit

Field

Type

Reset

Description

7-0

Channel n Hysteresis[7-0]

(n = 0 to 7 for the ADS8688A;

n = 0 to 3 for the ADS8684A)

R/W

0h

These bits set the channel high and low alarm hysteresis for

channel n (n = 0 to 7 for the ADS8688A; n = 0 to 3 for the

ADS8684A)

For example, bits 7-0 of the channel 0 register (address 15h) set

the channel 0 alarm hysteresis.

00000000 = No hysteresis

00000001 = ±1-LSB hysteresis

00000010 to 11111110 = ±2-LSB to ±254-LSB hysteresis

11111111 = ±255-LSB hysteresis

Figure 119. Ch n High Threshold MSB Registers

7

6

5

4

3

2

1

0

CHn_HT[15:8]

R/W-1h

LEGEND: R/W = Read/Write; -n = value after reset

Table 22. Channel n High Threshold MSB Register Field Descriptions

(n = 0 to 7 for the ADS8688A; n = 0 to 3 for the ADS8684A)

Bit

Field

Type

Reset

Description

7-0

CHn_HT[15:8]

(n = 0 to 7 for the ADS8688A;

n = 0 to 3 for the ADS8684A)

R/W

1h

These bits set the MSB byte for the 16-bit channel n high alarm.

For example, bits 7-0 of the channel 0 register (address 16h) set

the MSB byte for the channel 0 high alarm threshold. The

channel 0 high alarm threshold is AAFFh when bits 7-0 of the ch

0 high threshold MSB register (address 16h) are set to AAh and

bits 7-0 of the ch 0 high threshold LSB register (address 17h)

are set to FFh.

0000 0000 = MSB byte is 00h

0000 0001 = MSB byte is 01h

0000 0010 to 1110 1111 = MSB byte is 02h to FEh

1111 1111 = MSB byte is FFh

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Figure 120. Ch n High Threshold LSB Registers

7

6

5

4

3

2

1

0

CHn_HT[7:0]

R/W-1h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23. Channel n High Threshold LSB Register Field Descriptions

(n = 0 to 7 for the ADS8688A; n = 0 to 3 for the ADS8684A)

Bit

Field

Type

Reset

Description

7-0

CHn_HT[7-0]

(n = 0 to 7 for the ADS8688A;

n = 0 to 3 for the ADS8684A)

R/W

1h

These bits set the LSB for the 16-bit channel n high alarm.

For example, bits 7-0 of the channel 0 register (address 17h) set

the LSB for the channel 0 high alarm threshold. The channel 0

high alarm threshold is AAFFh when bits 7-0 of the ch 0 high

threshold MSB register (address 16h) are set to AAh and bits 7-

0 of the ch 0 high threshold LSB register (address 17h) are set

to FFh.

0000 0000 = LSB byte is 00h

0000 0001 = LSB byte is 01h

0000 0010 to 1111 1110 = LSB byte is 02h to FEh

1111 1111 = LSB byte is FFh

Figure 121. Ch n Low Threshold MSB Registers

7

6

5

4

3

2

1

0

CHn_LT[15:8]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 24. Channel n Low Threshold MSB Register Field Descriptions

(n = 0 to 7 for the ADS8688A; n = 0 to 3 for the ADS8684A)

Bit

Field

Type

Reset

Description

7-0

CHn_LT[15:8]

(n = 0 to 7 for the ADS8688A;

n = 0 to 3 for the ADS8684A)

R/W

0h

These bits set the MSB byte for the 16-bit channel n low alarm.

For example, bits 7-0 of the channel 0 register (address 18h) set

the MSB byte for the channel 0 low alarm threshold. The

channel 0 low alarm threshold is AAFFh when bits 7-0 of the ch

0 low threshold MSB register (address 18h) are set to AAh and

bits 7-0 of the ch 0 low threshold LSB register (address 19h) are

set to FFh.

0000 0000 = MSB byte is 00h

0000 0001 = MSB byte is 01h

0000 0010 to 1110 1111 = MSB byte is 02h to FEh

1111 1111 = MSB byte is FFh

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Figure 122. Ch n Low Threshold LSB Registers

7

6

5

4

3

2

1

0

CHn_LT[7:0]

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 25. Channel n Low Threshold MSB Register Field Descriptions

(n = 0 to 7 for the ADS8688A; n = 0 to 3 for the ADS8684A)

Bit

Field

Type

Reset

Description

7-0

CHn_LT[7-0]

(n = 0 to 7 for the ADS8688A;

n = 0 to 3 for the ADS8684A)

R/W

0h

These bits set the LSB for the 16-bit channel n low alarm.

For example, bits 7-0 of the channel 0 register (address 19h) set

the LSB for the channel 0 low alarm threshold. The channel 0

low alarm threshold is AAFFh when bits 7-0 of the ch 0 low

threshold MSB register (address 18h) are set to AAh and bits 7-

0 of the ch 0 low threshold LSB register (address 19h) are set to

FFh.

0000 0000 = LSB byte is 00h

0000 0001 = LSB byte is 01h

0000 0010 to 1110 1111 = LSB byte is 02h to FEh

1111 1111 = LSB byte is FFh

8.5.2.3.6 Command Read-Back Register (address = 3Fh)

This register allows the device mode of operation to be read. On execution of this command, the device outputs

the command word executed in the previous data frame. The output of the command register appears on SDO

from the 16th falling edge onwards in an MSB-first format. All information regarding the command register is

contained in the first eight bits and the last eight bits are 0 (see Table 6), thus the command read-back operation

can be stopped after the 24th SCLK cycle.

Figure 123. Command Read-Back Register

7

6

5

4

3

2

1

0

COMMAND_WORD[15:8]

R-0h

LEGEND: R = Read only; -n = value after reset

Table 26. Command Read-Back Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

COMMAND_WORD[15:8]

R

0h

Command executed in previous data frame.

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The ADS8684A and ADS8688A devices are fully-integrated data acquisition systems based on a 16-bit SAR

ADC. The devices include an integrated analog front-end for each input channel and an integrated precision

reference with a buffer. As such, this device family does not require any additional external circuits for driving the

reference or analog input pins of the ADC.

9.2 Typical Applications

9.2.1 Phase-Compensated, 8-Channel, Multiplexed Data Acquisition System for Power Automation

Ch1 Input, V₁

Reference

Input, V_R

Ch n Input, V_n

(n = 1 to 7)

¨ꢀꢀ= Measured Phase Difference

Between Channels

Angle (ꢀ)

¨ꢀ_r1

¨ꢀ_rn

(n = 1 to 7)

AVDD = 5 V

ADS8688A

R_0P

AIN_0P

1 M:

PGA

LPF

C₀

1 M:

AIN_0GND

R_0M

Simple Capture Card

16-Bit

ADC

R_7P

AIN_7P

1 M:

FPGA

SITARA

PGA

LPF

C₇

AIN_7GND

DDR

R_7M

4.096 V

AGND

Typical 50-Hz

Sine-Wave from CT/PT

Balanced RC Filter

on Each Input

Figure 124. 8-Channel, Multiplexed Data Acquisition System for Power Automation

9.2.1.1 Design Requirements

In modern power grids, accurately measuring the electrical parameters of the various areas of the power grid is

extremely critical. This measurement helps determine the operating status and running quality of the grid. Such

accurate measurements also help diagnose potential problems with the power network so that these problems

can be resolved quickly without having any significant service disruption. The key electrical parameters include

amplitude, frequency, and phase, which are important for calculating the power factor, power quality, and other

parameters of the power system.

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Typical Applications (continued)

The phase angle of the electrical signal on the power network buses is a special interest to power system

engineers. The primary objective for this design is to accurately measure the phase and phase difference

between the analog input signals in a multichannel data acquisition system. When multiple input channels are

sampled in a sequential manner as in a multiplexed ADC, an additional phase delay is introduced between the

channels. Thus, the phase measurements are not accurate. However, this additional phase delay is constant and

can be compensated in application software.

The key design requirements are given below:

•

Single-ended sinusoidal input signal with a ±10-V amplitude and typical frequency (f_IN= 50 Hz).

Design an 8-channel multiplexed data acquisition system using a 16-bit SAR ADC.

Design a software algorithm to compensate for the additional phase difference between the channels.

9.2.1.2 Detailed Design Procedure

The application circuit and system diagram for this design is shown in Figure 124. This design includes a

complete hardware and software implementation of a multichannel data acquisition system for power automation

applications.

This system can be designed using the ADS8688A, which is a 16-bit, 500-kSPS, 8-channel, multiplexed input,

SAR ADC with integrated precision reference and analog front-end circuitry for each channel. The ADC supports

bipolar input ranges up to ±10.24 V with a single 5-V supply and provides minimum latency in data output

resulting from the SAR architecture. The integration offered by this device makes the ADS8684A and ADS8688A

an ideal selection for such applications, because the integrated signal conditioning helps minimize system

components and avoids the need for generating high-voltage supply rails. The overall system-level dc precision

(gain and offset errors) and low temperature drift offered by this device helps system designers achieve the

desired system accuracy without calibration. In most applications, using passive RC filters or multi-stage filters in

front of the ADC is preferred to reduce the noise of the input signal.

The software algorithm implemented in this design uses the discrete fourier transform (DFT) method to calculate

and track the input signal frequency, obtain the exact phase angle of the individual signal, calculate the phase

difference, and implement phase compensation. The entire algorithm has four steps:

•

Calculate the theoretical phase difference introduced by the ADC resulting from multiplexing input channels.

Estimate the frequency of the input signal using frequency tracking and DFT techniques.

Calculate the phase angle of all signals in the system based on the estimated frequency.

Compensate the phase difference for all channels using the theoretical value of an additional MUX phase

delay calculated in the first step.

For a step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test

results, see Phase Compensated 8-Channel, Multiplexed Data Acquisition System for Power Automation

Reference Design (TIDU427).

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9.2.2 16-Bit, 8-Channel, Integrated Analog Input Module for Programmable Logic Controllers (PLCs)

24 VDC_LIMIT

24 VDC

Hot Swap

Protection

LM5069

Isolated

Power Supply

6-V V_ISO

5-V V_ISO, 25 mA

LDO

LM5017

TPS71501

9.3 VDC

5-V V_ISO

3.3 VDC,

15 mA

5-V V_ISO

LDO

TPS71533

50-Pin Interface

Connector

Filter

4 SE Voltage Inputs:

±10 VDC

0 VDC to 10 VDC

0 VDC to 5 VDC

1 VDC to 5 VDC

(To Base Board)

AVDD

DVDD

ADS8688A

Protection

SPI

16-Bit, 8-Ch, 500-kSPS

SAR ADC

4 Current Inputs:

0 mA to 20 mA

4 mA to 20 mA

3.3 VDC

Filter

Digital Isolator

ISO7141CC

I²C

EEPROM

Figure 125. 16-Bit, 8-Channel, Integrated Analog Input Module for PLCs

9.2.2.1 Design Requirements

This reference design provides a complete solution for a single-supply industrial control analog input module.

The design is suitable for process control end equipment, such as programmable logic controllers (PLCs),

distributed control systems (DCSs), and data acquisition systems (DAS) modules that must digitize standard

industrial current inputs, and bipolar or unipolar input voltage ranges up to ±10 V. In an industrial environment,

the analog voltage and current ranges typically include ±2.5 V, ±5 V, ±10 V, 0 V to 5 V, 0 V to 10 V, 4 mA to

20 mA, and 0 mA to 20 mA. This reference design can measure all standard industrial voltage and current

inputs. Eight channels are provided on the module, and each channel can be configured as a current or voltage

input with software configuration.

The key design requirements are given below:

•

Up to eight channels of user-programmable inputs:

–

Voltage inputs (with a typical Z_INof 1 MΩ): ±10 V, ±5 V, ±2.5 V, 0 V to 10 V, and 0 V to 5 V.

Current inputs (with a Z_INof 300 Ω): 0 mA to 20 mA, 4 mA to 20 mA, and ±20 mA.

•

A 16-bit SAR ADC with SPI.

Accuracy of ≤ 0.2% at 25°C over the entire input range of voltage and current inputs.

Onboard isolated Fly-Buck™ power supply with inrush current protection.

Slim-form factor 96 mm × 50.8 mm × 10 mm (L × W × H).

LabView-based GUI for signal-chain analysis and functional testing.

Designed to comply with IEC61000-4 standards for ESD, EFT, and surge.

9.2.2.2 Detailed Design Procedure

The application circuit and system diagram for this design is shown in Figure 125.

The module has eight analog input channels, and each channel can be configured as a current or voltage input

with software configuration. This design can be implemented using the ADS8688A, 16-bit, 8-channel, single-

supply SAR ADC with an on-chip PGA and reference. The on-chip PGA provides a high-input impedance

(typically 1 MΩ) and filters noise interference. The on-chip, 4.096-V, ultra-low drift voltage reference is used as

the reference for the ADC core.

Digital isolation is achieved using an ISO7141CC and ISO1541D. The host microcontroller communicates with a

TCA6408A (an 8-bit, I²C, I/O expander over an I²C bus). The ISO1541D is a bidirectional, I²C isolator that

isolates the I²C lines for the TCA6408A. The TCA6408A controls the low R_ONopto-switch (TLP3123) that is used

to switch between voltage-to-current input modes. The input channel configuration is done in microcontroller

firmware.

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A low-cost, constant, on-time, synchronous buck regulator in fly-buck configuration with an external transformer

(LM5017) generates the isolated power supply. The LM5017 has a wide input supply range, making this device

ideal for accepting a 24-V industrial supply. This transformer can accept up to 100 V, thereby making reliable

transient protection of the input supply more easily achievable. The fly-buck power supply isolates and steps the

input voltage down to 6 V. The supply then provides that voltage to the TPS70950 (the low dropout regulator) to

generate 5 V to power the ADS8688A and other circuitry. The LM5017 also features a number of other safety

and reliability functions, such as undervoltage lockout (UVLO), thermal shutdown, and peak current limit

protection.

Input analog signals are protected against high-voltage, fast-transient events often expected in an industrial

environment. The protection circuitry makes use of the transient voltage suppressor (TVS) and ESD diodes. The

RC low-pass mode filters are used on each analog input before the input reaches the ADS8688A, thus

eliminating any high-frequency noise pickups and minimizing aliasing.

For a step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test

results, see 16-Bit, 8-Channel, Integrated Analog Input Module for Programmable Logic Controllers (PLCs)

(TIDU365).

10 Power-Supply Recommendations

The device uses two separate power supplies: AVDD and DVDD. The internal circuits of the device operate on

AVDD; DVDD is used for the digital interface. AVDD and DVDD can be independently set to any value within the

permissible range.

The AVDD supply pins must be decoupled with AGND by using a minimum 10-µF and 1-µF capacitor on each

supply. Place the 1-µF capacitor as close to the supply pins as possible. Place a minimum 10-µF decoupling

capacitor very close to the DVDD supply to provide the high-frequency digital switching current. The effect of

using the decoupling capacitor is illustrated in the difference between the power-supply rejection ratio (PSRR)

performance of the device. Figure 126 shows the PSRR of the device without using a decoupling capacitor. The

PSRR improves when the decoupling capacitors are used, as shown in Figure 127.

150

130

110

90

140

120

100

80

---- ± 2.5*V_REF,---- 1.25*V_REF,---- 0.625*V_REF,

------0.3125*V_REF,-------0.156 V_REF,---- + 2.5*V_REF

---- + 1.25*V_REF,---- + 0.625*V_REF,---- + 0.3125*V_REF

---- ± 2.5*V_REF,---- 1.25*V_REF,---- 0.625*V_REF,

------0.3125*V_REF,-------0.156 V_REF,---- + 2.5*V_REF

---- + 1.25*V_REF,---- + 0.625*V_REF,---- + 0.3125*V_REF

70

60

50

30

40

0.001

0.01

0.1

1

10

0.001

0.01

0.1

1

10

Input Frequency (MHz)

C063

C062

Code output near 32,769

Figure 126. PSRR Without a Decoupling Capacitor

Code output near 32,768

Figure 127. PSRR With a Decoupling Capacitor

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11 Layout

11.1 Layout Guidelines

Figure 128 illustrates a PCB layout example for the ADS8684A and ADS8688A.

•

Partition the PCB into analog and digital sections. Care must be taken to ensure that the analog signals are

kept away from the digital lines. This layout helps keep the analog input and reference input signals away

from the digital noise. In this layout example, the analog input and reference signals are routed on the lower

side of the board and the digital connections are routed on the top side of the board.

•

Using a single dedicated ground plane is strongly encouraged.

Power sources to the ADS8684A and ADS8688A must be clean and well-bypassed. TI recommends using a

1-μF, X7R-grade, 0603-size ceramic capacitor with at least a 10-V rating in close proximity to the analog

(AVDD) supply pins. For decoupling the digital (DVDD) supply pin, a 10-μF, X7R-grade, 0805-size ceramic

capacitor with at least a 10-V rating is recommended. Placing vias between the AVDD, DVDD pins and the

bypass capacitors must be avoided. All ground pins must be connected to the ground plane using short, low

impedance paths.

•

There are two decoupling capacitors used for the REFCAP pin. The first is a small, 1-μF, X7R-grade, 0603-

size ceramic capacitor placed close to the device pins for decoupling the high-frequency signals and the

second is a 22-µF, X7R-grade, 1210-size ceramic capacitor to provide the charge required by the reference

circuit of the device. Both of these capacitors must be directly connected to the device pins without any vias

between the pins and capacitors.

•

The REFIO pin also must be decoupled with a 10-µF ceramic capacitor, if the internal reference of the device

is used. The capacitor must be placed close to the device pins.

For the auxiliary channel, the fly-wheel RC filter components must be placed close to the device. Among

ceramic surface-mount capacitors, COG (NPO) ceramic capacitors provide the best capacitance precision.

The type of dielectric used in COG (NPO) ceramic capacitors provides the most stable electrical properties

over voltage, frequency, and temperature changes.

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11.2 Layout Example

Digital Pins

1: SDI

38: CS

37: SCLK

2: RST/PD

3: REFSEL

4: DAISY

36: SDO

35: NC

DAISY

5: REFIO

34: DVDD

10µF

10µF (When using internal V_REF

)

6: REFGND

1µF

33: DGND

32: AGND

31: AGND

30: AVDD

GND

22µF

7: REFCAP

8: AGND

1µF

9: AVDD

1µF

10: AUX_IN

11: AUX_GND

12: AIN_6P

29: AGND

28: AGND

27: AIN_5P

26: AIN_5GND

25: AIN_4P

24: AIN_4GND

23: AIN_3P

22: AIN_3GND

21: AIN_2P

20: AIN_2GND

`

13: AIN_6GND

14: AIN_7P

Optional RC Filter for

Channel AIN_0 to AIN_7

15: AIN_7GND

16: AIN_0P

17: AIN_0GND

18: AIN_1P

19: AIN_1GND

Analog Pins

Figure 128. Board Layout for the ADS8684A and ADS8688A

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12 器件和文档支持

12.1 文档支持

12.1.1 相关文档ꢀ


型号：	ADS8688AIDBTR
厂家：	TEXAS INSTRUMENTS
描述：	采用 5V 电源和低漂移 VREF 的 16 位 500kSPS 双极输入 8 通道 SAR ADC \| DBT \| 38 \| -40 to 125
文件：	总80页 (文件大小：3237K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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