ADS8688AT [TI]
5V 双极输入、低漂移 VREF、宽温度范围 16 位 500kSPS 8 通道 SAR ADC;型号: | ADS8688AT |
厂家: | TEXAS INSTRUMENTS |
描述: | 5V 双极输入、低漂移 VREF、宽温度范围 16 位 500kSPS 8 通道 SAR ADC |
文件: | 总78页 (文件大小:3611K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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ADS8688AT
ZHCSID7 –JUNE 2018
带双极输入范围的 ADS8688AT 16 位、500kSPS、和 8 通道、单电源
SAR ADC
1 特性
2 应用
1
•
具有集成模拟前端的 16 位 ADC
和 8 通道多路复用器,支持自动和手动扫描
通道独立的可编程输入:
•
•
•
电力自动化
•
•
保护继电器
PLC 模拟输入模块
–
–
±10.24V、±5.12V、±2.56V、±1.28V、±0.64V
10.24V、5.12V、2.56V、1.28 V
3 说明
ADS8688AT 是一款是基于 16 位逐次逼近型 (SAR) 模
数转换器 (ADC) 的 8 通道集成数据采集系统,拥有高
达 500kSPS 吞吐量。该器件 的 每个输入通道都具有
集成的模拟前端电路,过压保护高达 ±20V,具有支持
自动和手动扫描模式的 8 通道多路复用器,以及具有
极低温漂的集成 4.096V 基准电压。
•
•
•
•
•
5V 模拟电源:1.65V 到 5V I/O 电源
恒定的阻性输入阻抗:1MΩ
输入过压保护:高达 ±20V
集成 4.096V 基准电压,温漂为 6ppm/°C
出色的性能:
–
–
500kSPS 的总吞吐量
差分非线性 (DNL):±0.5 最低有效位 (LSB);
最大积分非线性 (INL):±0.75 LSB
采用单一 5V 模拟电源运行,每个输入通道均可支持多
个真正双极和单极输入范围。每个输入范围均可用软件
进行编程,且每个通道相互独立,因此最大程度地提高
了系统灵活性。模拟前端增益经过精确地调整,可保证
所有输入范围的高直流精度。该器件提供了一个 1MΩ
的恒定电阻输入阻抗,可用于任何选定的输入范围,从
而使得传感器能够直接连接到器件。
–
–
–
增益误差和失调电压的温漂为 1ppm/°C
SNR:92dB;THD:–102dB
低功耗:65mW
•
•
•
•
•
AUX 输入 → 直接连接到 ADC 输入
ALARM → 每通道的高低阈值
SPI™兼容接口,支持菊链式连接
温度范围:–55°C 至 +125°C
ADS8688AT 具有一个与数字主机连接的简单 SPI 兼
容串行接口,同时还支持与多个器件进行菊链式连接。
数字电源可提供 1.65V 到 5.25V 的电压,因此可直接
连接各种主机控制器。
TSSOP-38 封装 (9.7mm × 4.4mm)
框图
DVDD
AVDD
器件信息(1)
1
MW
ADS8688AT
OVP
OVP
AIN_0P
2nd-Order
LPF
ADC
Driver
PGA
PGA
PGA
PGA
PGA
PGA
PGA
PGA
AIN_0GND
器件编号
ADS8688AT
封装
封装尺寸(标称值)
1
1
MW
MW
VB0
TSSOP (38)
9.70mm x 4.40mm
OVP
OVP
AIN_1P
2nd-Order
LPF
ADC
Driver
AIN_1GND
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
1
1
MW
MW
VB1
OVP
OVP
AIN_2P
2nd-Order
LPF
ADC
Driver
Digital
Logic
and
AIN_2GND
CS
1
MW
MW
Interface
VB2
VB3
VB4
VB5
1
SCLK
SDI
OVP
OVP
AIN_3P
2nd-Order
LPF
ADC
Driver
AIN_3GND
1
MW
MW
SDO
1
OVP
OVP
AIN_4P
2nd-Order
LPF
16-Bit
SAR ADC
ADC
Driver
AIN_4GND
DAISY
REFSEL
1
1
MW
MW
OVP
OVP
AIN_5P
2nd-Order
LPF
ADC
Driver
Oscillator
AIN_5GND
RST / PD
1
1
MW
MW
ALARM
OVP
OVP
AIN_6P
2nd-Order
LPF
ADC
Driver
REFCAP
AIN_6GND
1
MW
MW
VB6
REFIO
1
OVP
OVP
AIN_7P
2nd-Order
LPF
ADC
Driver
AIN_7GND
4.096-V
Reference
1
MW
VB7
AUX_IN
AUX_GND
AGND
DGND
REFGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBAS813
ADS8688AT
ZHCSID7 –JUNE 2018
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 36
7.5 Register Maps......................................................... 48
Application and Implementation ........................ 65
8.1 Application Information............................................ 65
8.2 Typical Applications ................................................ 65
Power Supply Recommendations...................... 70
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Timing Requirements: Serial Interface.................... 11
6.7 Switching Characteristics: Serial Interface.............. 11
6.8 Typical Characteristics............................................ 12
Detailed Description ............................................ 23
7.1 Overview ................................................................. 23
7.2 Functional Block Diagram ....................................... 23
7.3 Feature Description................................................. 24
8
9
10 Layout................................................................... 71
10.1 Layout Guidelines ................................................. 71
10.2 Layout Example .................................................... 72
11 器件和文档支持 ..................................................... 73
11.1 文档支持................................................................ 73
11.2 接收文档更新通知 ................................................. 73
11.3 社区资源................................................................ 73
11.4 商标....................................................................... 73
11.5 静电放电警告......................................................... 73
11.6 术语表 ................................................................... 73
12 机械、封装和可订购信息....................................... 73
7
4 修订历史记录
日期
修订版本
说明
2018 年 6 月
*
最初发布版本。
2
Copyright © 2018, Texas Instruments Incorporated
ADS8688AT
www.ti.com.cn
ZHCSID7 –JUNE 2018
5 Pin Configuration and Functions
DBT Package
38-Pin TSSOP
Top View
SDI
RST/PD
DAISY
1
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
CS
2
SCLK
3
SDO
REFSEL
REFIO
4
ALARM
DVDD
5
REFGND
REFCAP
AGND
6
DGND
7
AGND
8
AGND
AVDD
9
AVDD
AUX_IN
AUX_GND
AIN_6P
10
11
12
13
14
15
16
17
18
19
AGND
AGND
AIN_5P
AIN_5GND
AIN_4P
AIN_4GND
AIN_3P
AIN_3GND
AIN_2P
AIN2_GND
AIN_6GND
AIN_7P
AIN_7GND
AIN_0P
AIN_0GND
AIN_1P
AIN_1GND
Not to scale
Copyright © 2018, Texas Instruments Incorporated
3
ADS8688AT
ZHCSID7 –JUNE 2018
www.ti.com.cn
Pin Functions
NO.
NAME
I/O
DESCRIPTION
1
2
3
SDI
Digital input
Data input for serial communication.
Active low logic input.
RST/PD
DAISY
Digital input
Digital input
Dual functionality to reset or power-down the device.
Chain the data input during serial communication in daisy-chain mode.
Active low logic input to enable the internal reference.
When low, the internal reference is enabled;
4
REFSEL
Digital input
REFIO becomes an output that includes the VREF voltage.
When high, the internal reference is disabled;
REFIO becomes an input to apply the external VREF voltage.
5
6
REFIO
Analog input, output Internal reference output and external reference input pin. Decouple with REFGND on pin 6.
Reference GND pin; short to the analog GND plane.
Power supply
REFGND
Decouple with REFIO on pin 5 and REFCAP on pin 7.
7
8
9
REFCAP
AGND
Analog output
Power supply
Power supply
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Power supply
Power supply
Power supply
Power supply
Power supply
Power supply
Power supply
Digital output
Digital output
Digital input
Digital input
ADC reference decoupling capacitor pin. Decouple with REFGND on pin 6.
Analog ground pin. Decouple with AVDD on pin 9.
AVDD
Analog supply pin. Decouple with AGND on pin 8.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
AUX_IN
AUX_GND
AIN_6P
AIN_6GND
AIN_7P
AIN_7GND
AIN_0P
AIN_0GND
AIN_1P
AIN_1GND
AIN2_GND
AIN_2P
AIN_3GND
AIN_3P
AIN_4GND
AIN_4P
AIN_5GND
AIN_5P
AGND
Auxiliary input channel: positive input. Decouple with AUX_GND on pin 11.
Auxiliary input channel: negative input. Decouple with AUX_IN on pin 10.
Analog input channel 6, positive input. Decouple with AIN_6GND on pin 13.
Analog input channel 6, negative input. Decouple with AIN_6P on pin 12.
Analog input channel 7, positive input. Decouple with AIN_7GND on pin 15.
Analog input channel 7, negative input. Decouple with AIN_7P on pin 14.
Analog input channel 0, positive input. Decouple with AIN_0GND on pin 17.
Analog input channel 0, negative input. Decouple with AIN_0P on pin 16.
Analog input channel 1, positive input. Decouple with AIN_1GND on pin 19.
Analog input channel 1, negative input. Decouple with AIN_1P on pin 18.
Analog input channel 2, negative input. Decouple with AIN_2P on pin 21.
Analog input channel 2, positive input. Decouple with AIN_2GND on pin 20.
Analog input channel 3, negative input. Decouple with AIN_3P on pin 23.
Analog input channel 3, positive input. Decouple with AIN_3GND on pin 22.
Analog input channel 4, negative input. Decouple with AIN_4P on pin 25.
Analog input channel 4, positive input. Decouple with AIN_4GND on pin 24.
Analog input channel 5, negative input. Decouple with AIN_5P on pin 27.
Analog input channel 5, positive input. Decouple with AIN_5GND on pin 26.
Analog ground pin
AGND
Analog ground pin
AVDD
Analog supply pin. Decouple with AGND on pin 31.
AGND
Analog ground pin. Decouple with AVDD on pin 30.
AGND
Analog ground pin
DGND
Digital ground pin. Decouple with DVDD on pin 34.
DVDD
Digital supply pin. Decouple with DGND on pin 33.
ALARM
SDO
Active high alarm output
Data output for serial communication
SCLK
Clock input for serial communication
CS
Active low logic input; chip-select signal
4
Copyright © 2018, Texas Instruments Incorporated
ADS8688AT
www.ti.com.cn
ZHCSID7 –JUNE 2018
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–20
MAX
UNIT
V
AIN_nP, AIN_nGND to GND(2)
AIN_nP, AIN_nGND to GND(3)
AUX_GND to GND
20
–11
11
V
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–55
0.3
AVDD + 0.3
7
V
AUX_IN to GND
V
AVDD to GND or DVDD to GND
REFCAP to REFGND or REFIO to REFGND
GND to REFGND
V
5.7
V
0.3
V
Digital input pins to GND
Digital output pins to GND
Operating temperature, TA
Storage temperature, Tstg
DVDD + 0.3
DVDD + 0.3
125
V
V
°C
°C
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) AVDD = 5 V.
(3) AVDD = floating.
6.2 ESD Ratings
VALUE
UNIT
Analog input pins
(AIN_nP; AIN_nGND)
±4000
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
discharge
V(ESD)
V
All other pins
±2000
±500
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.75
1.65
NOM
5
MAX
UNIT
AVDD
DVDD
Analog supply voltage
Digital supply voltage
5.25
V
V
3.3
AVDD
6.4 Thermal Information
ADS8688AT
THERMAL METRIC(1)
DBT (TSSOP)
38 PINS
68.8
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
19.9
30.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.3
ψJB
29.8
RθJC(bot)
NA
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2018, Texas Instruments Incorporated
5
ADS8688AT
ZHCSID7 –JUNE 2018
www.ti.com.cn
6.5 Electrical Characteristics
minimum and maximum specifications are at TA = –55°C to +125°C, AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and
fSAMPLE = 500 kSPS (unless otherwise noted); typical specifications are at TA = 25°C
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
ANALOG INPUTS
Input range = ±2.5 × VREF
Input range = ±1.25 × VREF
Input range = ±0.625 × VREF
–2.5 × VREF
–1.25 × VREF
–0.625 × VREF
2.5 × VREF
1.25 × VREF
0.625 × VREF
A
A
A
–0.3125 ×
VREF
Input range = ±0.3125 × VREF
Input range = ±0.15625 × VREF
0.3125 × VREF
A
A
Full-scale input span(2)
(AIN_nP to AIN_nGND)
–0.15625 ×
VREF
0.15625 ×
VREF
V
Input range = 2.5 × VREF
Input range = 1.25 × VREF
Input range = 0.625 × VREF
Input range = 0.3125 × VREF
Input range = ±2.5 × VREF
Input range = ±1.25 × VREF
Input range = ±0.625 × VREF
0
2.5 × VREF
1.25 × VREF
0.625 × VREF
0.3125 × VREF
2.5 × VREF
A
A
A
A
A
A
A
0
0
0
–2.5 × VREF
–1.25 × VREF
–0.625 × VREF
1.25 × VREF
0.625 × VREF
–0.3125 ×
VREF
Input range = ±0.3125 × VREF
Input range = ±0.15625 × VREF
0.3125 × VREF
A
A
Operating input range,
positive input
AIN_nP
–0.15625 ×
VREF
0.15625 ×
VREF
V
Input range = 2.5 × VREF
Input range = 1.25 × VREF
Input range = 0.625 × VREF
Input range = 0.3125 × VREF
0
0
0
0
2.5 × VREF
1.25 × VREF
A
A
A
A
0.625 × VREF
0.3125 × VREF
Operating input range,
negative input
AIN_nGND
All input ranges
–0.1
0.85
0
0.1
V
B
At TA = 25°C,
all input ranges
zi
Input impedance
1
7
1.15
MΩ
B
B
Input impedance drift
All input ranges
32 ppm/°C
VIN – 2.25
————
RIN
With voltage at AIN_nP pin = VIN
input range = ±2.5 × VREF
,
A
A
A
A
A
VIN – 2.00
————
RIN
With voltage at AIN_nP pin = VIN
input range = ±1.25 × VREF
,
With voltage at AIN_nP pin = VIN
,
VIN – 1.60
————
RIN
IIkg(in)
Input leakage current
input ranges = ±0.625 × VREF
;
µA
±0.3125 × VREF; ±0.15625 × VREF
VIN – 2.50
————
RIN
With voltage at AIN_nP pin = VIN
,
input range = 2.5 × VREF
With voltage at AIN_nP pin = VIN
,
VIN – 2.50
————
RIN
input range = 1.25 × VREF; 0.625 ×
VREF; 0.3125 × VREF
INPUT OVERVOLTAGE PROTECTION
VOVP Overvoltage protection voltage
AVDD = 5 V
–20
–11
20
V
11
B
B
AVDD = floating
(1) Test Levels: (A) Tested at final test. Overtemperature limits are set by characterization and simulation. (B) Limits set by characterization
and simulation, across temperature range. (C) Typical value only for information, provided by design simulation.
(2) Ideal input span, does not include gain or offset error.
6
Copyright © 2018, Texas Instruments Incorporated
ADS8688AT
www.ti.com.cn
ZHCSID7 –JUNE 2018
Electrical Characteristics (continued)
minimum and maximum specifications are at TA = –55°C to +125°C, AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and
fSAMPLE = 500 kSPS (unless otherwise noted); typical specifications are at TA = 25°C
TEST
PARAMETER
SYSTEM PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
Resolution
16
16
Bits
Bits
LSB(3)
A
A
A
A
A
NMC
DNL
INL
No missing codes
Differential nonlinearity
Integral nonlinearity(4)
Gain error
–0.99
–2
±0.5
±0.75
±0.02
1.5
2
LSB
±0.05 %FSR(5)
EG
At TA = 25°C, all input ranges
At TA = 25°C, all input ranges
Gain error matching
(channel-to-channel)
±0.02
1
±0.05
6
%FSR
A
B
A
Gain error temperature drift
All input ranges
At TA = 25°C,
ppm/°C
±0.5
±1
(6)
input range = ±2.5 × VREF
At TA = 25°C,
input range = ±1.25 × VREF
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±1
±1.5
±1.5
±1.5
±2
A
A
A
A
A
A
A
A
A
A
A
At TA = 25°C,
input range = ±0.625 × VREF
EO
Offset error
mV
At TA = 25°C,
input range = ±0.3125 × VREF
At TA = 25°C,
input range = ±0.15625 × VREF
At TA = 25°C,
all unipolar input ranges
At TA = 25°C,
input range = ±2.5 × VREF
±1
(6)
At TA = 25°C,
input range = ±1.25 × VREF
±1
At TA = 25°C,
input range = ±0.625 × VREF
±1.5
±1.5
±1.5
±2
Offset error matching
(channel-to-channel)
mV
At TA = 25°C,
input range = ±0.3125 × VREF
At TA = 25°C,
input range = ±0.15625 × VREF
At TA = 25°C,
all unipolar input ranges
Input range = ±2.5 × VREF
1
1
1
2
4
1
1
2
4
15
4
B
B
B
B
B
B
B
B
B
Input range = ±1.25 × VREF
Input range = ±0.625 × VREF
Input range = ±0.3125 × VREF
Input range = ±0.15625 × VREF
Input range = 0 to 2.5 × VREF
Input range = 0 to 1.25 × VREF
Input range = 0 to 0.625 × VREF
Input range = 0 to 0.3125 × VREF
4
15
Offset error temperature drift
26 ppm/°C
12
6
15
26
SAMPLING DYNAMICS
tCONV Conversion time
tACQ
850
ns
ns
A
A
Acquisition time
1150
Maximum throughput rate
without latency
fS
500
kSPS
A
(3) LSB = least significant bit.
(4) This parameter is the endpoint INL, not best-fit INL.
(5) FSR = full-scale range.
(6) Does not include the shift in offset over time.
Copyright © 2018, Texas Instruments Incorporated
7
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ZHCSID7 –JUNE 2018
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Electrical Characteristics (continued)
minimum and maximum specifications are at TA = –55°C to +125°C, AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and
fSAMPLE = 500 kSPS (unless otherwise noted); typical specifications are at TA = 25°C
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
DYNAMIC CHARACTERISTICS
Input range = ±2.5 × VREF
Input range = ±1.25 × VREF
Input range = ±0.625 × VREF
Input range = ±0.3125 × VREF
Input range = ±0.15625 × VREF
Input range = 2.5 × VREF
90
89
92
91
A
A
A
A
A
A
A
A
A
87.5
81.5
75.5
88.5
87.5
81.5
75.5
89
83
Signal-to-noise ratio
SNR
77
dB
(VIN – 0.5 dBFS at 1 kHz)
90.5
89
Input range = 1.25 × VREF
Input range = 0.625 × VREF
Input range = 0.3125 × VREF
Input ranges = ±2.5 × VREF, ±1.25 ×
83
77
VREF, ±0.625 × VREF, 2.5 × VREF
1.25 × VREF
,
–102
–100
Total harmonic distortion(7)
(VIN – 0.5 dBFS at 1 kHz)
THD
dB
dB
dB
B
Input ranges = ±0.3125 × VREF
,
±0.15625 × VREF, 0.625 × VREF
,
0.3125 × VREF
Input range = ±2.5 × VREF
Input range = ±1.25 × VREF
Input range = ±0.625 × VREF
Input range = ±0.3125 × VREF
Input range = ±0.15625 × VREF
Input range = 2.5 × VREF
89
88.5
87
91.5
91
A
A
A
A
A
A
A
A
A
89
81
83
Signal-to-noise ratio
SINAD
75
77
(VIN – 0.5 dBFS at 1 kHz)
87.5
87
90.5
89
Input range = 1.25 × VREF
Input range = 0.625 × VREF
Input range = 0.3125 × VREF
81
83
75
77
Input ranges = ±2.5 × VREF, ±1.25 ×
VREF, ±0.625 × VREF, 2.5 × VREF
1.25 × VREF
,
103
101
Spurious-free dynamic range
SFDR
B
(VIN – 0.5 dBFS at 1 kHz)
Input ranges = ±0.3125 × VREF
±0.15625 × VREF, 0.625 × VREF
,
,
0.3125 × VREF
Aggressor channel input overdriven
to 2 × maximum input voltage
Crosstalk isolation(8)
Crosstalk memory(9)
110
90
dB
dB
B
B
Aggressor channel input overdriven
to 2 × maximum input voltage
BW(–3 dB)
Small-signal bandwidth, –3 dB
Small-signal bandwidth, –0.1 dB
At TA = 25°C, all input ranges
At TA = 25°C, all input ranges
15
kHz
kHz
B
B
BW(–0.1 dB)
2.5
(7) Calculated on the first nine harmonics of the input frequency.
(8) Isolation crosstalk is measured by applying a full-scale sinusoidal signal up to 10 kHz to a channel, not selected in the multiplexing
sequence, and measuring its effect on the output of any selected channel.
(9) Memory crosstalk is measured by applying a full-scale sinusoidal signal up to 10 kHz to a channel that is selected in the multiplexing
sequence, and measuring its effect on the output of the next selected channel for all combinations of input channels.
8
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Electrical Characteristics (continued)
minimum and maximum specifications are at TA = –55°C to +125°C, AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and
fSAMPLE = 500 kSPS (unless otherwise noted); typical specifications are at TA = 25°C
TEST
PARAMETER
AUXILIARY CHANNEL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
Resolution
16
0
Bits
V
A
A
A
A
C
C
A
A
A
A
A
A
B
A
B
V(AUX_IN)
AUX_IN voltage range
(AUX_IN – AUX_GND)
VREF
VREF
AUX_IN
0
V
Operating input range
Input capacitance
AUX_GND
0
75
V
During sampling
During conversion
pF
Ci
5
pF
IIkg(in)
DNL
Input leakage current
Differential nonlinearity
Integral nonlinearity
Gain error
100
±0.6
±1.5
±0.02
nA
–0.99
–4
2
4
LSB
LSB
%FSR
mV
dB
INL
EG(AUX)
EO(AUX)
SNR
At TA = 25°C
±0.2
5
Offset error
At TA = 25°C
–5
87
Signal-to-noise ratio
Total harmonic distortion(7)
Signal-to-noise + distortion
Spurious-free dynamic range
V(AUX_IN) = –0.5 dBFS at 1 kHz
V(AUX_IN) = –0.5 dBFS at 1 kHz
V(AUX_IN) = –0.5 dBFS at 1 kHz
V(AUX_IN) = –0.5 dBFS at 1 kHz
89
–102
88.5
103
THD
dB
SINAD
SFDR
86
dB
dB
INTERNAL REFERENCE OUTPUT
Voltage on REFIO pin
(configured as output)
(10)
V(REFIO_INT)
At TA = 25°C
4.095
4.096
4.097
V
A
Internal reference temperature
drift
6
22
17 ppm/°C
µF
B
B
A
C(OUT_REFIO)
V(REFCAP)
Decoupling capacitor on REFIO
10
Reference voltage to ADC
(on REFCAP pin)
At TA = 25°C
4.095
4.096
4.097
V
Reference buffer output
impedance
0.5
0.6
22
1
Ω
B
B
B
B
Reference buffer temperature
drift
4.5 ppm/°C
Decoupling capacitor on
REFCAP
C(OUT_REFCAP)
10
μF
C(OUT_REFCAP) = 22 µF,
C(OUT_REFIO) = 22 µF
Turn-on time
15
ms
EXTERNAL REFERENCE INPUT
External reference voltage on
VREFIO_EXT
4.046
4.096
4.146
V
C
REFIO (configured as input)
(10) Does not include the variation in voltage resulting from solder-shift and long-term effects.
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Electrical Characteristics (continued)
minimum and maximum specifications are at TA = –55°C to +125°C, AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and
fSAMPLE = 500 kSPS (unless otherwise noted); typical specifications are at TA = 25°C
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
POWER-SUPPLY REQUIREMENTS
AVDD
Analog power-supply voltage
Analog supply
4.75
1.65
5
5.25
V
V
B
B
Digital supply range
3.3
AVDD
DVDD
Digital power-supply voltage
Digital supply range for specified
performance
2.7
3.3
13
10
3
5.25
16
B
A
A
A
Dynamic, AVDD = 5 V, fS = maximum and
AVDD
IAVDD_DYN
IAVDD_STC
ISTDBY
mA
mA
mA
internal reference
AVDD = 5 V, device not converting
and internal reference
Static
12
Analog supply current
Digital supply current
At AVDD = 5 V, device in STDBY
mode and internal reference
Standby
4.5
20
Power-
down
IPWR_DN
At AVDD = 5 V, device in PWR_DN
At DVDD = 3.3 V, output = 0000h
3
μA
B
A
IDVDD_DYN
0.5
mA
DIGITAL INPUTS (CMOS)
DVDD > 2.1 V
DVDD ≤ 2.1 V
DVDD > 2.1 V
DVDD ≤ 2.1 V
0.7 × DVDD
0.8 × DVDD
–0.3
DVDD + 0.3
DVDD + 0.3
0.3 × DVDD
0.2 × DVDD
A
A
A
A
A
C
VIH
VIL
Digital input high logic levels
V
V
Digital input low logic levels
–0.3
Input leakage current
Input pin capacitance
100
5
nA
pF
DIGITAL OUTPUTS (CMOS)
VOH
IO = 500-μA source
IO = 500-μA sink
Only for SDO
0.8 × DVDD
0
DVDD
A
A
A
C
Digital output logic levels
V
VOL
0.2 × DVDD
Floating state leakage current
Internal pin capacitance
1
5
µA
pF
10
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6.6 Timing Requirements: Serial Interface
minimum and maximum specifications are at TA = –55°C to +125°C, AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal),
SDO load = 20 pF, and fSAMPLE = 500 kSPS (unless otherwise noted); typical specifications are at TA = 25°C
MIN
1150
0.4
0.4
30
30
10
25
5
NOM
MAX
UNIT
ns
tACQ
Acquisition time
tPH_CK
Clock high time
0.6
0.6
tSCLK
tSCLK
ns
tPL_CK
Clock low time
tPH_CS
CS high time
tSU_CSCK
tHT_CKDO
tSU_DOCK
tSU_DICK
tHT_CKDI
tSU_DSYCK
tHT_CKDSY
Setup time: CS falling to SCLK falling
Hold time: SCLK falling to (previous) data valid on SDO
Setup time: SDO data valid to SCLK falling
Setup time: SDI data valid to SCLK falling
Hold time: SCLK falling to (previous) data valid on SDI
Setup time: DAISY data valid to SCLK falling
Hold time: SCLK falling to (previous) data valid on DAISY
ns
ns
ns
ns
5
ns
5
ns
5
ns
6.7 Switching Characteristics: Serial Interface
minimum and maximum specifications are at TA = –55°C to +125°C, AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal),
SDO load = 20 pF, and fSAMPLE = 500 kSPS (unless otherwise noted); typical specifications are at TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fS
Sampling frequency (fCLK = max)
500
kSPS
ADC cycle time period
(fCLK = max)
tS
2
µs
MHz
ns
fSCLK
tSCLK
tCONV
tDZ_CSDO
Serial clock frequency (fS = max)
17
Serial clock time period
(fS = max)
59
Conversion time
850
10
ns
Delay time: CS falling to data
enable
ns
Delay time: last SCLK falling to
CS rising
tD_CKCS
10
10
ns
ns
Delay time: CS rising to SDO
going to 3-state
tDZ_CSDO
Sample
N
Sample
N + 1
tS
tCONV
tACQ
tPH_CS
CS
SCLK
SDO
tSCLK
tD_CKCS
31
tDZ_CSDO
tSU_CSCK
tPH_CK
tPL_CK
23
24
26
1
2
14
15
16
17
18
25
27
28
29
7
8
9
30
32
tHT_CKDO
tDZ_CSDO
tSU_DOCK
D14
#2
D6
#2
D5
#2
D4
#2
D3
#2
D2
#2
D1
#2
D0
#2
D15
#2
D9
#2
D8
#2
D7
#2
Data from sample N
tSU_DICK
B2
tHT_CKDI
B14
B10 B9
B8
B7
X
X
X
X
X
B15
B1
B0
X
X
B3
SDI
X
X
X
X
X
tSU_DSYCK
tHT_CKDSY
D14
#1
D6
#1
D5
#1
D4
#1
D3
#1
D2
#1
D1
#1
D0
#1
D15
#1
D9
#1
D8
#1
D7
#1
DAISY
图 1. Serial Interface Timing Diagram
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6.8 Typical Characteristics
at TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 4.096 V, and fSAMPLE = 500 kSPS (unless otherwise noted)
15
9
15
9
---- ± 2.5*VREF, ---- ± 1.25*VREF
---- ± 0.625*VREF, ------±0.3125*VREF
-------±0.156 VREF, ---- + 2.5*VREF
---- + 1.25*VREF, ---- + 0.625*VREF
---- + 0.3125*VREF
-55C
25C
125C
3
3
œ3
œ9
œ15
-3
-9
-15
2
6
10
œ10
œ6
œ2
-10
-6
-2
2
6
10
Input Voltage (V)
C001
Input Voltage (V)
D002
Input range = ±2.5 × VREF
图 3. Input Current vs Temperature
图 2. Input I-V Characteristic
800
640
480
320
160
0
10
6
2
-2
-6
-10
0.85 0.88 0.91 0.94 0.97
1
1.03 1.06 1.09 1.12 1.15
Input Impedance (Mꢀ)
C006
-55
-19
17
53
89
125
Free- Air Temperature (°C)
D005
Number of samples = 1160
All input ranges
图 5. Typical Distribution of Input Impedance
图 4. Input Impedance Variation vs Temperature
20000
16000
12000
8000
4000
0
24000
20000
16000
12000
8000
4000
0
32765 32766 32767 32768 32769 32770 32771
Output Codes
32765 32766 32767 32768 32769 32770 32771
Output Codes
C008
C007
Mean = 32768.67, sigma = 0.58, input = 0 V,
range = ±2.5 × VREF
Mean = 32768.60, sigma = 0.63, input = 0 V,
range = ±1.25 × VREF
图 6. DC Histogram for Mid-Scale Inputs
图 7. DC Histogram for Mid-Scale Inputs
(±2.5 × VREF
)
(±1.25 × VREF)
12
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 4.096 V, and fSAMPLE = 500 kSPS (unless otherwise noted)
20000
16000
12000
8000
4000
0
20000
16000
12000
8000
4000
0
32764 32765 32766 32767 32768 32769 32770 32771 32772
Output Codes
32764 32765 32766 32767 32768 32769 32770 32771 32772
Output Codes
C009
C010
Mean = 32768.8, sigma = 0.76, input = 0 V,
range = ±0.625 × VREF
Mean = 32767.75, sigma = 0.65, input = 1.25 × VREF,
range = 2.5 × VREF
图 8. DC Histogram for Mid-Scale Inputs
图 9. DC Histogram for Mid-Scale Inputs
(±0.625 × VREF
)
(2.5 × VREF)
20000
16000
12000
8000
4000
0
12000
10000
8000
6000
4000
2000
0
32764
32766
32768
32770
32772
32760 32762 32764 32766 32768 32770 32772 32774
Output Codes
Output Codes
C012
C011
Mean = 32768.2, sigma = 0.75, input = 0.625 × VREF
,
Mean = 32768.5, sigma = 1.30, input = 0 V,
range = ±0.3125 × VREF
range = 1.25 × VREF
图 10. DC Histogram for Mid-Scale Inputs
图 11. DC Histogram for Mid-Scale Inputs
(1.25 × VREF
)
(±0.3125 × VREF)
6000
5000
4000
3000
2000
1000
0
10000
8000
6000
4000
2000
0
32757 32760 32763 32766 32769 32772 32775 32778 32781
32760
32763
32766
32769
32772
32775
C013
Output Codes
Output Codes
C014
Mean = 32768.5, sigma = 2.68, input = 0 V,
range = ±0.15625 × VREF
Mean = 32768.5, sigma = 1.30, input = 0.3125 × VREF
,
range = 0.625 × VREF
图 12. DC Histogram for Mid-Scale Inputs
图 13. DC Histogram for Mid-Scale Inputs
(±0.15625 × VREF
)
(0.625 × VREF)
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 4.096 V, and fSAMPLE = 500 kSPS (unless otherwise noted)
1.4
6000
5000
4000
3000
2000
1000
0
1
0.6
0.2
-0.2
-0.6
-1
0
16384
32768
49152
65536
32757
32762
32767
32772
32777
32782
Codes (LSB)
C016
Output Codes
C015
All input ranges
Mean = 32768.5, sigma = 2.68, input = 0.15625 × VREF
,
range = 0.3125 × VREF
图 14. DC Histogram for Mid-Scale Inputs
图 15. Typical DNL for All Codes
(0.3125 × VREF
)
2
1.5
1
1.4
1
Maximum
Minimum
0.6
0.2
-0.2
-0.6
-1
0.5
0
-0.5
-1
-1.5
-2
0
16384
32768
49152
65536
-55
-19
17
53
89
125
Codes (LSB)
C018
Free-Air Temperature (°C)
D017
Range = ±2.5 × VREF
All input ranges
图 17. Typical INL for All Codes
图 16. DNL vs Temperature
2
1.5
1
2
1.5
1
0.5
0
0.5
0
-0.5
-1
-0.5
-1
-1.5
-2
-1.5
-2
0
16384
32768
49152
65536
0
16384
32768
49152
65536
Codes (LSB)
C019
Codes (LSB)
C020
Range = ±1.25 × VREF
图 18. Typical INL for All Codes
Range = ±0.625 × VREF
图 19. Typical INL for All Codes
14
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 4.096 V, and fSAMPLE = 500 kSPS (unless otherwise noted)
2
1.5
1
2
1.5
1
0.5
0
0.5
0
-0.5
-1
-0.5
-1
-1.5
-2
-1.5
-2
0
16384
32768
49152
65536
0
16384
32768
49152
65536
Codes (LSB)
Codes (LSB)
C022
C021
Range = 1.25 × VREF
Range = 2.5 × VREF
图 21. Typical INL for All Codes
图 20. Typical INL for All Codes
2
1.5
1
2
1.5
1
0.5
0
0.5
0
-0.5
-1
-0.5
-1
-1.5
-2
-1.5
-2
0
16384
32768
49152
65536
0
16384
32768
49152
65536
Codes (LSB)
C023
Codes (LSB)
C024
Range = ±0.3125 × VREF
Range = ±0.15625 × VREF
图 22. Typical INL for All Codes
图 23. Typical INL for All Codes
2
1.5
1
2
1.5
1
0.5
0
0.5
0
-0.5
-1
-0.5
-1
-1.5
-2
-1.5
-2
0
16384
32768
49152
65536
0
16384
32768
49152
65536
C025
Codes (LSB)
Codes (LSB)
C026
Range = 0.625 × VREF
Range = 0.3125 × VREF
图 24. Typical INL for All Codes
图 25. Typical INL for All Codes
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 4.096 V, and fSAMPLE = 500 kSPS (unless otherwise noted)
2
2
Maximum
Minimum
Maximum
Minimum
1
1
0
0
-1
-1
-2
-2
-55
-19
17
53
89
125
-55
-19
17
53
89
125
Free-Air Temperature (°C)
Free-Air Temperature (°C)
D027
D028
Range = ±2.5 × VREF
Range = ±1.25 × VREF
图 26. INL vs Temperature (±2.5 × VREF
)
图 27. INL vs Temperature (±1.25 × VREF)
2
1
2
1
Maximum
Minimum
Maximum
Minimum
0
0
-1
-1
-2
-2
-55
-19
17
53
89
125
-55
-19
17
53
89
125
Free-Air Temperature (°C)
Free-Air Temperature (°C)
D029
D030
Range = ±0.625 × VREF
Range = 2.5 × VREF
图 28. INL vs Temperature (±0.625 × VREF
)
图 29. INL vs Temperature (2.5 × VREF)
2
1
2
1
Maximum
Minimum
Maximum
Minimum
0
0
-1
-1
-2
-2
-55
-19
17
53
89
125
-55
-19
17
53
89
125
Free-Air Temperature (°C)
Free-Air Temperature (°C)
D031
D032
Range = 1.25 × VREF
Range = ±0.3125 × VREF
图 30. INL vs Temperature (1.25 × VREF
)
图 31. INL vs Temperature (±0.3125 × VREF)
16
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 4.096 V, and fSAMPLE = 500 kSPS (unless otherwise noted)
2
2
Maximum
Minimum
Maximum
Minimum
1
1
0
0
-1
-1
-2
-2
-55
-19
17
53
89
125
-55
-19
17
53
89
125
Free-Air Temperature (°C)
Free-Air Temperature (°C)
D033
D034
Range = ±0.15625 × VREF
Range = 0.625 × VREF
图 32. INL vs Temperature (±0.15625 × VREF
)
图 33. INL vs Temperature (0.625 × VREF)
2
1
2
1
Maximum
Minimum
± 2.5*VREF
+2.5*VREF
+1.25*VREF
+0.625*VREF
+0.3125*VREF
± 1.25*VREF
± 0.625*VREF
± 0.3125*VREF
± 0.15625*VREF
0
0
-1
-1
-2
-2
-55
-19
17
53
89
125
-55
-19
17
53
89
125
Free-Air Temperature (°C)
Free-Air Temperature (°C)
D035
D036
Range = 0.3125 × VREF
图 34. INL vs Temperature (0.3125 × VREF
)
图 35. Offset Error vs
Temperature Across Input Ranges
80
60
40
20
0
2
1
0
-1
-2
-3
-4
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
-55
-19
17
53
89
125
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2 2.2 2.4 2.6 2.8 3
Free-Air Temperature (°C)
Offset Drift (ppm/oC)
D038
C037
Range = ±2.5 × VREF
Range = ±2.5 × VREF
图 36. Typical Histogram for Offset Drift
图 37. Offset Error vs Temperature Across Channels
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 4.096 V, and fSAMPLE = 500 kSPS (unless otherwise noted)
100
80
60
40
20
0
0.05
± 2.5*VREF
+2.5*VREF
± 1.25*VREF
± 0.625*VREF
± 0.3125*VREF
± 0.15625*VREF
+1.25*VREF
+0.625*VREF
+0.3125*VREF
0.03
0.01
-0.01
-0.03
-0.05
-55
-19
17
53
89
125
0
0.5
1
1.5
2
2.5
3
3.5
4
Free-Air Temperature (°C)
Gain Drift (ppm/oC)
D039
C040
Range = ±2.5 × VREF
图 39. Typical Histogram for Gain Error Drift
图 38. Gain Error vs Temperature Across Input Ranges
2
1.5
1
0.05
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
0.03
0.01
0.5
0
-0.01
-0.03
-0.05
---- ± 2.5*VREF, ---- ± 1.25*VREF
---- ± 0.625*VREF, ------±0.3125*VREF
-------±0.156 VREF, ---- + 2.5*VREF
---- + 1.25*VREF, ---- + 0.625*VREF
---- + 0.3125*VREF
-0.5
0
4
8
12
16
20
-55
-19
17
53
89
125
C042
Source Resistance (kꢀ)
Free-Air Temperature (°C)
D041
Range = ±2.5 × VREF
图 41. Gain Error vs External Resistance (REXT
)
图 40. Gain Error vs Temperature Across Channels
0
0
œ40
œ40
œ80
œ80
œ120
œ160
œ200
œ120
œ160
œ200
0
50000
100000
150000
200000
250000
0
50000
100000
150000
200000
250000
Input Frequency (Hz)
Input Frequency (Hz)
C044
C043
Number of points = 64k, fIN = 1 kHz, SNR = 92.3 dB,
SINAD = 91.9 dB, THD = 101 dB, SFDR = 104 dB
Number of points = 64k, fIN = 1 kHz, SNR = 91.4 dB,
SINAD = 91.2 dB, THD = 105 dB, SFDR = 107 dB
图 42. Typical FFT Plot (±2.5 × VREF
)
图 43. Typical FFT Plot (±1.25 × VREF)
18
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ADS8688AT
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 4.096 V, and fSAMPLE = 500 kSPS (unless otherwise noted)
0
0
œ40
œ40
œ80
œ80
œ120
œ160
œ200
œ120
œ160
œ200
0
50000
100000
150000
200000
250000
0
50000
100000
150000
200000
250000
Input Frequency (Hz)
Input Frequency (Hz)
C045
C046
Number of points = 64k, fIN = 1 kHz, SNR = 89.6 dB,
SINAD = 89.5 dB, THD = 106 dB, SFDR = 107 dB
Number of points = 64k, fIN = 1 kHz, SNR = 90.93 dB,
SINAD = 90.48 dB, THD = 100 dB, SFDR = 102 dB
图 44. Typical FFT Plot (±0.625 × VREF
)
图 45. Typical FFT Plot (2.5 × VREF)
0
œ40
0
œ40
œ80
œ80
œ120
œ160
œ200
œ120
œ160
œ200
0
50000
100000
150000
200000
250000
0
50000
100000
150000
200000
250000
Input Frequency (Hz)
Input Frequency (Hz)
C047
C048
Number of points = 64k, fIN = 1 kHz, SNR = 89.6 dB,
SINAD = 89.5 dB, THD = –106 dB, SFDR = 107 dB
Number of points = 64k, fIN = 1 kHz, SNR = 83.55 dB,
SINAD = 83.5 dB, THD = –104 dB, SFDR = 107 dB
图 46. Typical FFT Plot (1.25 × VREF
)
图 47. Typical FFT Plot (±0.3125 × VREF)
0
œ40
0
œ40
œ80
œ80
œ120
œ160
œ200
œ120
œ160
œ200
0
50000
100000
150000
200000
250000
0
50000
100000
150000
200000
250000
C050
Input Frequency (Hz)
Input Frequency (Hz)
C049
Number of points = 64k, fIN = 1 kHz, SNR = 77.6 dB,
SINAD = 77.6 dB, THD = –106 dB, SFDR = 107 dB
Number of points = 64k, fIN = 1 kHz, SNR = 83.55 dB,
SINAD = 83.5 dB, THD = –103 dB, SFDR = 107 dB
图 48. Typical FFT Plot (±0.15625 × VREF
)
图 49. Typical FFT Plot (0.625 × VREF)
版权 © 2018, Texas Instruments Incorporated
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www.ti.com.cn
Typical Characteristics (接下页)
at TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 4.096 V, and fSAMPLE = 500 kSPS (unless otherwise noted)
0
95
œ40
90
œ80
85
œ120
80
œ160
œ200
---- ± 2.5*VREF, ---- ± 1.25*VREF, ---- ± 0.625*VREF,
------±0.3125*VREF, -------±0.156 VREF, ---- + 2.5*VREF
---- + 1.25*VREF, ---- + 0.625*VREF, ---- + 0.3125*VREF
75
70
0
50000
100000
150000
200000
250000
100
1000
10000
C052
C051
Input Frequency (Hz)
Input Frequency (Hz)
Number of points = 64k, fIN = 1 kHz, SNR = 77.55 dB,
SINAD = 77.5 dB, THD = –100 dB, SFDR = 107 dB
图 50. Typical FFT Plot (0.3125 × VREF
)
图 51. SNR vs Input Frequency
95
90
85
80
75
70
96
90
84
78
72
66
60
± 2.5*VREF
+2.5*VREF
± 1.25*VREF
± 0.625*VREF
± 0.3125*VREF
± 0.15625*VREF
+1.25*VREF
+0.625*VREF
+0.3125*VREF
---- ± 2.5*VREF, ---- ± 1.25*VREF, ---- ± 0.625*VREF,
------±0.3125*VREF, ---±0.156 VREF, ---- + 2.5*VREF
---- + 1.25*VREF, --- + 0.625*VREF,--- + 0.3125*VREF
-55
-19
17
53
89
125
100
1000
10000
Free-Air Temperature (°C)
D053
Input Frequency (Hz)
C054
fIN = 1 kHz
图 52. SNR vs Temperature
图 53. SINAD vs Input Frequency
œ80
œ85
96
90
84
78
72
66
60
---- ± 2.5*VREF, ---- ± 1.25*VREF, ---- ± 0.625*VREF,
------±0.3125*VREF, -------±0.156 VREF, ---- + 2.5*VREF
---- + 1.25*VREF, ---- + 0.625*VREF, ---- + 0.3125*VREF
œ90
œ95
œ100
œ105
œ110
œ115
œ120
± 2.5*VREF
+2.5*VREF
± 1.25*VREF
± 0.625*VREF
± 0.3125*VREF
± 0.15625*VREF
+1.25*VREF
+0.625*VREF
+0.3125*VREF
-55
-19
17
53
89
125
100
1000
10000
Free-Air Temperature (°C)
D055
C056
Input Frequency (Hz)
fIN = 1 kHz
图 54. SINAD vs Temperature
图 55. THD vs Input Frequency
20
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ADS8688AT
www.ti.com.cn
ZHCSID7 –JUNE 2018
Typical Characteristics (接下页)
at TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 4.096 V, and fSAMPLE = 500 kSPS (unless otherwise noted)
-80
œ80
œ100
œ120
œ140
œ160
± 2.5*VREF
+2.5*VREF
± 1.25*VREF
± 0.625*VREF
± 0.3125*VREF
± 0.15625*VREF
+1.25*VREF
+0.625*VREF
+0.3125*VREF
-90
---- ± 2.5*VREF,
-100
-110
-120
---- ± 1.25*VREF,
---- ± 0.625*VREF,
------±0.3125*VREF,
-------±0.156 VREF,
---- + 2.5*VREF
---- + 1.25*VREF,
---- + 0.625*VREF,
---- + 0.3125*VREF
-55
-19
17
53
89
125
50
500
5000
50000
500000
5000000
Free-Air Temperature (°C)
D057
C058
Input Frequency (Hz)
fIN = 1 kHz
图 56. THD vs Temperature
图 57. Memory Crosstalk vs Frequency
œ80
œ100
œ120
œ140
œ160
œ180
œ80
œ100
œ120
œ140
œ160
---- ± 2.5*VREF,
---- ± 1.25*VREF,
---- ± 0.625*VREF,
------±0.3125*VREF,
-------±0.156 VREF,
---- + 2.5*VREF
---- + 1.25*VREF,
---- + 0.625*VREF,
---- + 0.3125*VREF
---- ± 2.5*VREF, ---- ± 1.25*VREF, ---- ± 0.625*VREF,
------±0.3125*VREF, -------±0.156 VREF, ---- + 2.5*VREF
---- + 1.25*VREF, ---- + 0.625*VREF, ---- + 0.3125*VREF
50
500
5000
50000
500000
5000000
50
500
5000
50000
500000
5000000
Input Frequency (Hz)
C060
C059
Input Frequency (Hz)
Input = 2 × maximum input voltage
图 58. Isolation Crosstalk vs Frequency
图 59. Memory Crosstalk vs Frequency for
Overrange Inputs
œ80
œ100
œ120
œ140
œ160
œ180
12
11.5
11
---- ± 2.5*VREF, ---- ± 1.25*VREF, ---- ± 0.625*VREF,
------±0.3125*VREF, -------±0.156 VREF, ---- + 2.5*VREF
---- + 1.25*VREF, ---- + 0.625*VREF, ---- + 0.3125*VREF
10.5
10
-55
-19
17
53
89
125
50
500
5000
50000
500000 5000000
Free-Air Temperature (°C)
D074
Input Frequency (Hz)
C061
Input = 2 × maximum input voltage
图 61. AVDD Current vs Temperature
图 60. Isolation Crosstalk vs Frequency for
(fS = 500 kSPS)
Overrange Inputs
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference VREF = 4.096 V, and fSAMPLE = 500 kSPS (unless otherwise noted)
9
8.5
8
2.4
2.3
2.2
2.1
2
7.5
7
-55
-19
17
53
89
125
-55
-19
17
53
89
125
Free-Air Temperature (°C)
Free-Air Temperature (°C)
D075
D076
图 62. AVDD Current vs Temperature
图 63. AVDD Current vs Temperature
(During Sampling)
(STANDBY)
6
5
4
3
2
1
-55
-19
17
53
89
125
Free-Air Temperature (°C)
D077
图 64. AVDD Current vs Temperature
(Power Down)
22
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ADS8688AT
www.ti.com.cn
ZHCSID7 –JUNE 2018
7 Detailed Description
7.1 Overview
The ADS8688AT is a 16-bit data acquisition system with 8-channel analog inputs. Each analog input channel
consists of an overvoltage protection circuit, a programmable gain amplifier (PGA), and a second-order,
antialiasing filter that conditions the input signal before being fed into an 8-channel analog multiplexer (MUX).
The output of the MUX is digitized using a 16-bit analog-to-digital converter (ADC), based on the successive
approximation register (SAR) architecture. This overall system can achieve a maximum throughput of 500 kSPS,
combined across all channels. The device features a 4.096-V internal reference with a fast-settling buffer and a
simple SPI-compatible serial interface with daisy-chain (DAISY) and ALARM features.
The device operates from a single 5-V analog supply and can accommodate true bipolar input signals up to
±2.5 × VREF. The device offers a constant 1-MΩ resistive input impedance irrespective of the sampling frequency
or the selected input range. The integration of multichannel precision analog front-end circuits with high input
impedance and a precision ADC operating from a single 5-V supply offers a simplified end solution without
requiring external high-voltage bipolar supplies and complicated driver circuits.
7.2 Functional Block Diagram
DVDD
AVDD
ADS8688AT
1 Mꢀ
OVP
OVP
AIN_0P
2nd-Order
LPF
ADC
Driver
PGA
AIN_0GND
1 Mꢀ
1 Mꢀ
VB0
VB1
VB2
VB3
VB4
VB5
VB6
VB7
OVP
OVP
AIN_1P
2nd-Order
LPF
ADC
Driver
PGA
AIN_1GND
1 Mꢀ
1 Mꢀ
OVP
OVP
AIN_2P
2nd-Order
LPF
ADC
Driver
Digital
Logic
PGA
PGA
PGA
PGA
AIN_2GND
and
Interface
1 Mꢀ
1 Mꢀ
CS
SCLK
SDI
OVP
OVP
AIN_3P
2nd-Order
LPF
ADC
Driver
AIN_3GND
1 Mꢀ
1 Mꢀ
SDO
OVP
OVP
AIN_4P
2nd-Order
LPF
16-Bit
SAR ADC
ADC
Driver
AIN_4GND
DAISY
REFSEL
RST/PD
1 Mꢀ
1 Mꢀ
OVP
OVP
AIN_5P
2nd-Order
LPF
ADC
Driver
Oscillator
AIN_5GND
1 Mꢀ
1 Mꢀ
ALARM
OVP
OVP
AIN_6P
2nd-Order
LPF
ADC
Driver
PGA
REFCAP
AIN_6GND
1 Mꢀ
1 Mꢀ
REFIO
OVP
OVP
AIN_7P
2nd-Order
LPF
ADC
Driver
PGA
AIN_7GND
1 Mꢀ
4.096-V
Reference
AUX_IN
AUX_GND
AGND
DGND
REFGND
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7.3 Feature Description
7.3.1 Analog Inputs
The ADS8688AT has eight analog input channels, such that the positive inputs AIN_nP (n = 0 to 7) are the
single-ended analog inputs and the negative inputs AIN_nGND are tied to GND. 图 65 shows the simplified
circuit schematic for each analog input channel, including the input overvoltage protection circuit, PGA, low-pass
filter (LPF), high-speed ADC driver, and analog multiplexer.
1 MW
CS
SCLK
SDI
SDO
DAISY
OVP
OVP
AIN_nP
2nd-Order
LPF
ADC
Driver
MUX
PGA
ADC
AIN_nGND
1 MW
VB
NOTE: n = 0 to 7.
图 65. Front-End Circuit Schematic for Each Analog Input Channel
The device can support multiple unipolar or bipolar, single-ended input voltage ranges based on the configuration
of the program registers. As explained in the range select registers, the input voltage range for each analog
channel can be configured to bipolar ±2.5 × VREF, ±1.25 × VREF, ±0.625 × VREF, ±0.3125 × VREF, and ±0.15625 ×
VREF or unipolar 0 to 2.5 × VREF, 0 to 1.25 × VREF, 0 to 0.625 × VREF, and 0 to 0.3125 × VREF. With the internal or
external reference voltage set to 4.096 V, the input ranges of the device can be configured to bipolar ranges of
±10.24 V, ±5.12 V, ±2.56 V, ±1.28 V, and ±0.64 V or unipolar ranges of 0 V to 10.24 V, 0 V to 5.12 V, 0 V to
2.56 V, and 0 V to 1.28 V. Any of these input ranges can be assigned to any analog input channel of the device.
For instance, the ±2.5 × VREF range can be assigned to AIN_1P, the ±1.25 × VREF range can be assigned to
AIN_2P, the 0 to 2.5 × VREF range can be assigned to AIN_3P, and so forth.
The device samples the voltage difference (AIN_nP – AIN_nGND) between the selected analog input channel
and the AIN_nGND pin. The device allows a ±0.1-V range on the AIN_nGND pin for all analog input channels.
This feature is useful in modular systems where the sensor or signal-conditioning block is further away from the
ADC on the board and when a difference in the ground potential of the sensor or signal conditioner from the ADC
ground is possible. In such cases, running separate wires from the AIN_nGND pin of the device to the sensor or
signal-conditioning ground is recommended.
If the analog input pins (AIN_nP) to the device are left floating, the output of the ADC corresponds to an internal
biasing voltage. The output from the ADC must be considered as invalid if the device is operated with floating
input pins. This condition does not cause any damage to the device, which is fully functional when a valid input
voltage is applied to the pins.
7.3.2 Analog Input Impedance
Each analog input channel in the device presents a constant resistive impedance of 1 MΩ. The input impedance
is independent of either the ADC sampling frequency, the input signal frequency, or range. The primary
advantage of such high-impedance inputs is the ease of driving the ADC inputs without requiring driving
amplifiers with low output impedance. Bipolar, high-voltage power supplies are not required in the system
because this ADC does not require any high-voltage front-end drivers. In most applications, the signal sources or
sensor outputs can be directly connected to the ADC input, thus significantly simplifying the design of the signal
chain.
In order to maintain the dc accuracy of the system, matching the external source impedance on the AIN_nP input
pin with an equivalent resistance on the AIN_nGND pin is recommended. This matching helps to cancel any
additional offset error contributed by the external resistance.
24
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ZHCSID7 –JUNE 2018
Feature Description (接下页)
7.3.3 Input Overvoltage Protection Circuit
The ADS8688AT features an internal overvoltage protection circuit on each of the eight analog input channels.
Use these protection circuits as a secondary protection scheme to protect the device. Using external protection
devices against surges, electrostatic discharge (ESD), and electrical fast transient (EFT) conditions is highly
recommended. 图 66 shows the conceptual block diagram of the internal overvoltage protection (OVP) circuit.
AVDD
VP+
RFB
0V
ESD
AVDD
VP-
1MΩ
1MΩ
RS
RS
D1p
D2p
AIN_nP
Vœ
V+
AVDD
VOUT
D1n
AIN_nGND
+
D2n
RDC
VB
ESD
GND
图 66. Input Overvoltage Protection Circuit Schematic
As shown in 图 66, the combination of the 1-MΩ input resistors along with the PGA gain-setting resistors (RFB
and RDC) limit the current flowing into the input pins. A combination of antiparallel diodes (D1 and D2) are added
on each input pin to protect the internal circuitry and set the overvoltage protection limits.
表 1 explains the various operating conditions for the device when the device is powered on. 表 1 indicates that
when the AVDD pin of the device is connected to the proper supply voltage (AVDD = 5 V), the internal
overvoltage protection circuit can withstand up to ±20 V on the analog input pins.
表 1. Input Overvoltage Protection Limits When AVDD = 5 V(1)
INPUT CONDITION
(VOVP = ±20 V)
TEST
ADC
COMMENTS
CONDITION OUTPUT
All input
Valid
|VIN| < |VRANGE
|VRANGE| < |VIN| < |VOVP
|VIN| > |VOVP
|
Within operating range
Device functions as per data sheet specifications
ranges
Beyond operating range but
within overvoltage range
All input
Saturated
ranges
ADC output is saturated, but device is internally
protected (not recommended for extended time)
|
All input
Saturated
ranges
This usage condition may cause irreversible damage
to the device
|
Beyond overvoltage range
(1) GND = 0 V, AIN_nGND = 0 V, |VRANGE| is the maximum input voltage for any selected input range, and |VOVP| is the break-down
voltage for the internal OVP circuit. Assume that RS is approximately 0 Ω.
The results indicated in 表 1 are based on an assumption that the analog input pins are driven by very low
impedance sources (RS is approximately 0 Ω). However, if the sources driving the inputs have higher impedance,
the current flowing through the protection diodes reduces further, thereby increasing the OVP voltage range.
Higher source impedance results in gain errors and contributes to overall system noise performance.
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ZHCSID7 –JUNE 2018
www.ti.com.cn
图 67 shows the voltage versus current response of the internal overvoltage protection circuit when the device is
powered on. According to this current-to-voltage (I-V) response, the current flowing into the device input pins is
limited by the 1-MΩ input impedance. However, for voltages beyond ±20 V, the internal node voltages surpass
the break-down voltage for internal transistors, thus setting the limit for overvoltage protection on the input pins.
The same overvoltage protection circuit also provides protection to the device when the device is not powered on
and AVDD is floating. This condition can arise when the input signals are applied before the ADC is fully
powered on. 表 2 lists the overvoltage protection limits for this condition.
表 2. Input Overvoltage Protection Limits When AVDD = Floating(1)
INPUT CONDITION
(VOVP = ±11 V)
TEST
CONDITION
ADC OUTPUT
Invalid
COMMENTS
Device is not functional but is protected internally by
the OVP circuit
|VIN| < |VOVP
|
|
Within overvoltage range
Beyond overvoltage range
All input ranges
All input ranges
This usage condition may cause irreversible damage
to the device
|VIN| > |VOVP
Invalid
(1) AVDD = floating, GND = 0 V, AIN_nGND = 0 V, |VRANGE| is the maximum input voltage for any selected input range, and |VOVP| is the
break-down voltage for the internal OVP circuit. Assume that RS is approximately 0 Ω.
图 68 shows the voltage versus current response of the internal overvoltage protection circuit when the device is
not powered on. According to this I-V response, the current flowing into the device input pins is limited by the 1-
MΩ input impedance. However, for voltages beyond ±11 V, the internal node voltages surpass the break-down
voltage for internal transistors, thus setting the limit for overvoltage protection on the input pins.
30
18
20
12
---- ± 2.5*VREF, ---- ± 1.25*VREF
---- ± 0.625*VREF, ------±0.3125*VREF
-------±0.156 VREF, ---- + 2.5*VREF
---- + 1.25*VREF, ---- + 0.625*VREF
---- + 0.3125*VREF
6
4
œ6
œ4
œ18
œ30
œ12
œ20
0
10
20
30
œ20
œ12
œ4
4
12
20
œ30
œ20
œ10
C003
Input Voltage (V)
Input Voltage (V)
C004
图 67. I-V Curve for an Input OVP Circuit
图 68. I-V Curve for an Input OVP Circuit
(AVDD = Floating)
26
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ADS8688AT
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ZHCSID7 –JUNE 2018
7.3.4 Programmable Gain Amplifier (PGA)
The device offers a programmable gain amplifier (PGA) at each individual analog input channel, which converts
the original single-ended input signal into a fully differential signal to drive the internal 16-bit ADC. The PGA also
adjusts the common-mode level of the input signal before being fed into the ADC to ensure maximum usage of
the ADC input dynamic range. Depending on the range of the input signal, the PGA gain can be accordingly
adjusted by setting the Range_CHn[3:0] (n = 0 to 7) bits in the program register. The default or power-on state
for the Range_CHn[3:0] bits is 0000, which corresponds to an input signal range of ±2.5 × VREF. 表 3 lists the
various configurations of the Range_CHn[3:0] bits for the different analog input voltage ranges.
The PGA uses a very highly matched network of resistors for multiple gain configurations. Matching between
these resistors and the amplifiers across all channels is accurately trimmed to keep the overall gain error low
across all channels and input ranges.
表 3. Input Range Selection Bits Configuration
Range_CHn[3:0]
ANALOG INPUT RANGE (V)
BIT 3
BIT 2
BIT 1
BIT 0
±2.5 × VREF
±1.25 × VREF
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
1
1
1
0
0
1
1
1
0
1
1
1
0
1
0
1
1
1
0
1
1
±0.625 × VREF
±0.3125 × VREF
±0.15625 × VREF
0 to 2.5 × VREF
0 to 1.25 × VREF
0 to 0.625 × VREF
0 to 0.3125 × VREF
7.3.5 Second-Order, Low-Pass Filter (LPF)
In order to mitigate the noise of the front-end amplifiers and gain resistors of the PGA, each analog input channel
of the ADS8688AT features a second-order, antialiasing LPF at the output of the PGA. 图 69 and 图 70 show the
magnitude and phase response of the analog antialiasing filter, respectively. For maximum performance, the –3-
dB cutoff frequency for the antialiasing filter is typically set to 15 kHz. The performance of the filter is consistent
across all input ranges supported by the ADC.
2
1
0
œ15
œ30
œ45
œ60
œ75
œ90
0
œ1
œ2
œ3
œ4
œ5
œ6
---- ± 2.5*VREF, ---- ± 1.25*VREF
---- ± 0.625*VREF, ------±0.3125*VREF
-------±0.156 VREF, ---- + 2.5*VREF
---- + 1.25*VREF, ---- + 0.625*VREF
---- + 0.3125*VREF
---- ± 2.5*VREF, ---- ± 1.25*VREF
---- ± 0.625*VREF, ------±0.3125*VREF
-------±0.156 VREF, ---- + 2.5*VREF
---- + 1.25*VREF, ---- + 0.625*VREF
---- + 0.3125*VREF
100
1000
10000
100
1000
10000
Input Frequency (Hz)
C065
Input Frequency (Hz)
C064
图 69. Second-Order LPF Magnitude Response
图 70. Second-Order LPF Phase Response
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7.3.6 ADC Driver
In order to meet the performance of a 16-bit, SAR ADC at the maximum sampling rate (500 kSPS), the sample-
and-hold capacitors at the input of the ADC must be successfully charged and discharged during the acquisition
time window. This drive requirement at the inputs of the ADC necessitates the use of a high-bandwidth, low-
noise, and stable amplifier buffer. Such an input driver is integrated in the front-end signal path of each analog
input channel of the device. During transition from one channel of the multiplexer to another channel, the fast
integrated driver ensures that the multiplexer output settles to a 16-bit accuracy within the acquisition time of the
ADC, irrespective of the input levels on the respective channels.
7.3.7 Multiplexer (MUX)
The ADS8688AT features an integrated 8-channel analog multiplexer. For each analog input channel, the voltage
difference between the positive analog input AIN_nP and the negative ground input AIN_nGND is conditioned by
the analog front-end circuitry before being fed into the multiplexer. The output of the multiplexer is directly
sampled by the ADC. The multiplexer in the device can scan these analog inputs in either manual or auto-scan
mode, as explained in the Channel Sequencing Modes section. In manual mode (MAN_Ch_n), the channel is
selected for every sample via a register write; in auto-scan mode (AUTO_RST), the channel number is
incremented automatically on every CS falling edge after the present channel is sampled. The analog inputs can
be selected for an auto scan with register settings (see the auto-scan sequencing control registers). The device
automatically scans only the selected analog inputs in ascending order.
The maximum overall throughput for the ADS8688AT is specified at 500 kSPS across all channels. The per
channel throughput is dependent on the number of channels selected in the multiplexer scanning sequence. For
example, the throughput per channel is equal to 250 kSPS if only two channels are selected, but is equal to 125
kSPS per channel if four channels are selected, and so forth.
See 表 7 for command register settings to switch between the auto-scan mode and manual mode for individual
analog channels.
7.3.8 Reference
The ADS8688AT can operate with either an internal voltage reference or an external voltage reference using the
internal buffer. The internal or external reference selection is determined by an external REFSEL pin. The device
has a built-in buffer amplifier to drive the actual reference input of the internal ADC core for maximizing
performance.
28
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7.3.8.1 Internal Reference
The device has an internal 4.096-V (nominal value) reference. In order to select the internal reference, the
REFSEL pin must be tied low or connected to AGND. When the internal reference is used, REFIO (pin 5)
becomes an output pin with the internal reference value. 图 71 shows that placing a 10-µF (minimum) decoupling
capacitor between the REFIO pin and REFGND (pin 6) is recommended. The capacitor must be placed as close
to the REFIO pin as possible. The output impedance of the internal band-gap circuit creates a low-pass filter with
this capacitor to band-limit the noise of the reference. The use of a smaller capacitor value allows higher
reference noise in the system, thus degrading SNR and SINAD performance. Do not use the REFIO pin to drive
external ac or dc loads because REFIO has limited current output capability. The REFIO pin can be used as a
source if followed by a suitable op amp buffer (such as the OPA320).
AVDD
4.096 VREF
REFSEL
REFIO
10 mF
REFCAP
22 mF
1 mF
REFGND
ADC
AGND
图 71. Device Connections for Using an Internal 4.096-V Reference
The device internal reference is trimmed to a maximum initial accuracy of ±1 mV. The histogram in 图 72 shows
the distribution of the internal voltage reference output taken from more than 3300 production devices.
600
500
400
300
200
100
0
-1
-0.6
-0.2
0.2
0.6
1
C064
Error in REFIO Voltage (mV)
图 72. Internal Reference Accuracy at Room Temperature Histogram
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The initial accuracy specification for the internal reference can be degraded if the die is exposed to any
mechanical or thermal stress. Heating the device when being soldered to a printed circuit board (PCB) and any
subsequent solder reflow is a primary cause for shifts in the VREF value. The main cause of thermal hysteresis is
a change in die stress and therefore is a function of the package, die-attach material, and molding compound, as
well as the layout of the device itself.
In order to illustrate this effect, 80 devices were soldered using lead-free solder paste with the manufacturer
suggested reflow profile, as explained in application report SNOA550. The internal voltage reference output is
measured before and after the reflow process and 图 73 shows the typical shift in value. Although all tested units
exhibit a positive shift in their output voltages, negative shifts are also possible. The histogram in 图 73 shows
the typical shift for exposure to a single reflow profile. Exposure to multiple reflows, which is common on PCBs
with surface-mount components on both sides, causes additional shifts in the output voltage. If the PCB is to be
exposed to multiple reflows, solder the ADS8688AT in the later pass to minimize device exposure to thermal
stress.
30
25
20
15
10
5
0
-4
-3
-2
-1
0
1
Error in REFIO Voltage (mV)
C065
图 73. Solder Heat Shift Distribution Histogram
The internal reference is also temperature compensated to provide excellent temperature drift over an extended
industrial temperature range of –55°C to +125°C. 图 74 shows the variation of the internal reference voltage
across temperature for different values of the AVDD supply voltage. The typical specified value of the reference
voltage drift over temperature is 6 ppm/°C (图 75) and the maximum specified temperature drift is equal to
17 ppm/°C.
12
10
8
4.098
4.096
4.094
4.092
4.09
6
4
AVDD = 4.75 V
AVDD = 5 V
2
AVDD = 5.25 V
4.088
0
-55
-19
17
53
89
125
6
6.5
7
7.5
8
8.5
9
9.5 10 10.5 11 11.5
Free-Air Temperature (°C)
D053
REFIO Drift (ppm/ºC)
D054
AVDD = 5 V, number of devices = 30, ΔT = –55°C to +125°C
图 74. Variation of the Internal Reference Output (REFIO)
图 75. Internal Reference Temperature Drift Histogram
Across Supply and Temperature
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7.3.8.2 External Reference
For applications that require a better reference voltage or a common reference voltage for multiple devices, the
ADS8688AT offers a provision to use an external reference along with an internal buffer to drive the ADC
reference pin. In order to select the external reference mode, either tie the REFSEL pin high or connect this pin
to the DVDD supply. In this mode, an external 4.096-V reference must be applied at REFIO (pin 5), which
becomes an input pin. Any low-power, low-drift, or small-size external reference can be used in this mode
because the internal buffer is optimally designed to handle the dynamic loading on the REFCAP pin, which is
internally connected to the ADC reference input. The output of the external reference must be appropriately
filtered to minimize the resulting effect of the reference noise on system performance. 图 76 shows a typical
connection diagram for this mode.
AVDD
DVDD
4.096 VREF
REFSEL
AVDD
REF5040
(See the device datasheet for
a detailed pin configuration.)
OUT
CREF
REFIO
REFCAP
1 mF
22 mF
REFGND
AGND
ADC
图 76. Device Connections for Using an External 4.096-V Reference
The output of the internal reference buffer appears at the REFCAP pin. A minimum capacitance of 10 µF must
be placed between REFCAP (pin 7) and REFGND (pin 6). Place another capacitor of 1 µF as close to the
REFCAP pin as possible for decoupling high-frequency signals. Do not use the internal buffer to drive external ac
or dc loads because of the limited current output capability of this buffer.
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The performance of the internal buffer output is very stable across the entire operating temperature range of
–55°C to +125°C. 图 77 shows the variation in the REFCAP output across temperature for different values of the
AVDD supply voltage. The typical specified value of the reference buffer drift over temperature is 0.6 ppm/°C (图
78) and the maximum specified temperature drift is equal to 4.5 ppm/°C.
10
8
4.098
4.096
4.094
4.092
4.09
6
4
AVDD = 4.75 V
AVDD = 5 V
2
AVDD = 5.25 V
4.088
0
-55
-19
17
53
89
125
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2 2.4
Free-Air Temperature (°C)
D055
REFCAP Drift (ppm/ºC)
D056
AVDD = 5 V, number of devices = 30, ΔT = –55°C to 125°C
图 77. Variation of the Reference Buffer Output (REFCAP)
图 78. Reference Buffer Temperature Drift Histogram
vs Supply and Temperature
7.3.9 Auxiliary Channel
The device includes a single-ended auxiliary input channel (AUX_IN and AUX_GND). The AUX channel provides
direct interface to an internal, high-precision, 16-bit ADC through the multiplexer because this channel does not
include the front-end analog signal conditioning that the other analog input channels have. The AUX channel
supports a single unipolar input range of 0 V to VREF because there is no front-end PGA. The input signal on the
AUX_IN pin can vary from 0 V to VREF, whereas the AUX_GND pin must be tied to AGND.
When a conversion is initiated, the voltage between these pins is sampled directly on an internal sampling
capacitor (75 pF, typical). The input current required to charge the sampling capacitor is determined by several
factors, including the sampling rate, input frequency, and source impedance. For slow applications that use a
low-impedance source, the inputs of the AUX channel can be directly driven. When the throughput, input
frequency, or the source impedance increases, a driving amplifier must be used at the input to achieve good ac
performance from the AUX channel. Some key requirements of the driving amplifier are discussed in the Input
Driver for the AUX Channel section.
32
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The AUX channel in the ADS8688AT offers a true 16-bit performance with no missing codes. 图 79 and 图 80
show some typical performance characteristics of the AUX channel.
8000
6000
4000
2000
0
0
œ40
œ80
œ120
œ160
œ200
0
50000
100000
150000
200000
250000
C068
Input Frequency (Hz)
32763 32764 32765 32766 32767 32768 32769 32770 32771
Output Codes
fIN = 1 kHz, SNR = 88.2 dB, SINAD = 88.1 dB, THD = –102 dB,
SFDR = 102 dB, number of points = 64k
C066
Mean = 32767.15, sigma = 0.83
图 80. Typical FFT Plot
图 79. DC Histogram for Mid-Scale Input
(AUX Channel)
(AUX Channel)
7.3.9.1 Input Driver for the AUX Channel
For applications that use the AUX input channels at high throughput and high input frequency, a driving amplifier
with low output impedance is required to meet the ac performance of the internal 16-bit ADC. Some key
specifications of the input driving amplifier are discussed below:
•
Small-signal bandwidth. The small-signal bandwidth of the input driving amplifier must be much higher than
the bandwidth of the AUX input to ensure that there is no attenuation of the input signal resulting from the
bandwidth limitation of the amplifier. In a typical data acquisition system, a low cut-off frequency, antialiasing
filter is used at the inputs of a high-resolution ADC. The amplifier driving the antialiasing filter must have a low
closed-loop output impedance for stability, thus implying a higher gain bandwidth for the amplifier. Higher
small-signal bandwidth also minimizes the harmonic distortion at higher input frequencies. In general, 公式 1
can be uses as a basis to calculate the amplifier bandwidth requirements.
GBW í 4ìf-3 dB
where:
•
f–3dB is the 3-dB bandwidth of the RC filter
(1)
•
•
Distortion. In order to achieve the distortion performance of the AUX channel, the distortion of the input driver
(as shown in 公式 2) must be at least 10 dB lower than the specified distortion of the internal ADC.
THDAMP Ç THDADC -10 dB
(2)
Noise. Careful considerations must be made to select a low-noise, front-end amplifier in order to prevent any
degradation in SNR performance of the system. As a rule of thumb, to ensure that the noise performance of
the data acquisition system is not limited by the front-end circuit, keep the total noise contribution from the
front-end circuit below 20% of the input-referred noise of the ADC. As 公式 3 explains, noise from the input
driver circuit is band-limited by the low cut-off frequency of the input antialiasing filter.
2
SNR dB
(
)
V
≈
∆
’
÷
1
-
_ AMP_PP
p
2
1
5
V
NG ì
+ en2_RMS
ì
ìf-3dB
Ç
ì
FSR ì10
2 2
f
20
∆
«
÷
◊
6.6
where:
•
•
•
V1 / f_AMP_PP is the peak-to-peak flicker noise
en_RMS is the amplifier broadband noise density in nV/√Hz
NG is the noise gain of the front-end circuit, which is equal to 1 in a buffer configuration
(3)
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7.3.10 ADC Transfer Function
The ADS8688AT is a multichannel device that supports single-ended, bipolar, and unipolar input ranges on all
input channels. The output of the device is in straight binary format for both bipolar and unipolar input ranges.
The format for the output codes is the same across all analog channels.
图 81 shows the ideal transfer characteristic for each ADC channel for all input ranges. The full-scale range
(FSR) for each input signal is equal to the difference between the positive full-scale (PFS) input voltage and the
negative full-scale (NFS) input voltage. The LSB size is equal to FSR / 216 = FSR / 65536 because the resolution
of the ADC is 16 bits. For a reference voltage of VREF = 4.096 V, 表 4 lists the LSB values corresponding to the
different input ranges.
FFFFh
8000h
0001h
FSR œ 1LSB
Analog Input (AIN_nP t AIN_nGND)
1LSB
FSR/2
NFS
PFS
图 81. 16-Bit ADC Transfer Function (Straight-Binary Format)
表 4. ADC LSB Values for Different Input Ranges (VREF = 4.096 V)
POSITIVE FULL-SCALE NEGATIVE FULL-SCALE
FULL-SCALE RANGE (V)
INPUT RANGE (V)
LSB (µV)
(V)
10.24
5.12
2.56
1.28
0.64
10.24
5.12
2.56
1.28
(V)
–10.24
–5.12
–2.56
–1.28
–0.64
0
±2.5 × VREF
±1.25 × VREF
20.48
10.24
5.12
2.56
1.28
10.24
5.12
2.56
1.28
312.50
156.25
±0.625 × VREF
78.125
±0.3125 × VREF
±0.15625 × VREF
0 to 2.5 × VREF
0 to 1.25 × VREF
0 to 0.625 × VREF
0 to 0.3125 × VREF
39.0625
19.53125
156.25
0
78.125
0
39.0625
19.53125
0
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7.3.11 Alarm Feature
The device has an active-high ALARM output on pin 35. The ALARM signal is synchronous and changes its
state on the 16th falling edge of the SCLK signal. A high level on ALARM indicates that the alarm flag has
tripped on one or more channels of the device. This pin can be wired to interrupt the host input. When an
ALARM interrupt is received, the alarm flag registers are read to determine which channels have an alarm. The
device features independently programmable alarms for each channel. There are two alarms per channel (a low
and a high alarm) and each alarm threshold has a separate hysteresis setting.
The ADS8688AT sets a high alarm when the digital output for a particular channel exceeds the high alarm upper
limit [high alarm threshold (T) + hysteresis (H)]. The alarm resets when the digital output for the channel is less
than or equal to the high alarm lower limit (high alarm T – H – 2). 图 82 shows this function.
Similarly, the lower alarm is triggered when the digital output for a particular channel falls below the low alarm
lower limit (low alarm threshold T – H – 1). The alarm resets when the digital output for the channel is greater
than or equal to the low alarm higher limit (low alarm T + H + 1). 图 83 shows this function.
L_ALARM On
H_ALARM On
L_ALARM Off
H_ALARM Off
(T œ H œ 1)(T + H + 1)
ADC Output
(T + H)
ADC Output
(T œ H œ 2)
图 83. Low-ALARM Hysteresis
图 82. High-ALARM Hysteresis
图 84 depicts a functional block diagram for a single-channel alarm. There are two flags for each high and low
alarm: active alarm flag and tripped alarm flag; see the alarm flag registers for more details. The active alarm flag
is triggered when an alarm condition is encountered for a particular channel; the active alarm flag resets when
the alarm shuts off. A tripped alarm flag sets an alarm condition in the same manner as for an active alarm flag.
However, the tripped alarm flag remains latched and resets only when the appropriate alarm flag register is read.
Alarm Threshold
ALARM
Channel n
+/-
Hysteresis Channel n
Active Alarm Flag
Channel n
+
ADC Output
Channel n
16th
SCLK
Tripped Alarm Flag
S
R
Q
Q
Channel n
Alarm Flag Read
ADC
SDO
图 84. Alarm Functionality Schematic
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7.4 Device Functional Modes
7.4.1 Device Interface
7.4.1.1 Digital Pin Description
图 85 shows the digital data interface for the ADS8688AT.
CS
SCLK
CS
SCLK
SDO
SDI
SDO
SDI
RST / PD
DAISY
RST / PD
SDON (from previous device)
or DGND
图 85. Pin Configuration for the Digital Interface
The signals shown in 图 85 are summarized as follows:
7.4.1.1.1 CS (Input)
CS indicates an active-low, chip-select signal. CS is also used as a control signal to trigger a conversion on the
falling edge. Each data frame begins with the falling edge of the CS signal. The analog input channel to be
converted during a particular frame is selected in the previous frame. On the CS falling edge, the devices sample
the input signal from the selected channel and a conversion is initiated using the internal clock. The device
settings for the next data frame can be input during this conversion process. When the CS signal is high, the
ADC is considered to be in an idle state.
7.4.1.1.2 SCLK (Input)
This pin indicates the external clock input for the data interface. All synchronous accesses to the device are
timed with respect to the falling edges of the SCLK signal.
7.4.1.1.3 SDI (Input)
SDI is the serial data input line. SDI is used by the host processor to program the internal device registers for
device configuration. At the beginning of each data frame, the CS signal goes low and the data on the SDI line
are read by the device at every falling edge of the SCLK signal for the next 16 SCLK cycles. Any changes made
to the device configuration in a particular data frame are applied to the device on the subsequent falling edge of
the CS signal.
7.4.1.1.4 SDO (Output)
SDO is the serial data output line. SDO is used by the device to output conversion data. The size of the data
output frame varies depending on the register setting for the SDO format; see 表 14. A low level on CS releases
the SDO pin from the Hi-Z state. SDO is kept low for the first 15 SCLK falling edges. The MSB of the output data
stream is clocked out on SDO on the 16th SCLK falling edge, followed by the subsequent data bits on every
falling edge thereafter. The SDO line goes low after the entire data frame is output and goes to a Hi-Z state when
CS goes high.
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Device Functional Modes (接下页)
7.4.1.1.5 DAISY (Input)
DAISY is a serial input pin. When multiple devices are connected in daisy-chain mode, as illustrated in 图 88, the
DAISY pin of the first device in the chain is connected to GND. The DAISY pin of every subsequent device is
connected to the SDO output pin of the previous device, and the SDO output of the last device in the chain goes
to the SDI of the host processor. If an application uses a stand-alone device, the DAISY pin is connected to
GND.
7.4.1.1.6 RST/PD (Input)
RST/PD is a dual-function pin. 图 86 shows the timing of this pin and 表 5 explains the usage of this pin.
RST / PD
tPL_RST_PD
图 86. RST/PD Pin Timing
表 5. RST/PD Pin Functionality
CONDITION
DEVICE MODE
40 ns < tPL_RST_PD ≤ 100 ns
The device is in RST mode and does not enter PWR_DN mode.
The device is in RST mode and may or may not enter PWR_DN mode.
This setting is not recommended.
100 ns < tPL_RST_PD < 400 ns
The device enters PWR_DN mode and the program registers are reset to default
value.
tPL_RST_PD ≥ 400 ns
The device can be placed into power-down (PWR_DN) mode by pulling the RST/PD pin to a logic low state for at
least 400 ns. The RST/PD pin is asynchronous to the clock; thus, RST/PD can be triggered at any time
regardless of the status of other pins (including the analog input channels). When the device is in power-down
mode, any activity on the digital input pins (apart from the RST/PD pin) is ignored.
The program registers in the device can be reset to their default values (RST) by pulling the RST/PD pin to a
logic low state for no longer than 100 ns. This input is asynchronous to the clock. When RST/PD is pulled back
to a logic high state, the device is placed in normal mode. One valid write operation must be executed on the
program register in order to configure the device, followed by an appropriate command (AUTO_RST or MAN) to
initiate conversions.
When the RST/PD pin is pulled back to a logic high level, the device wakes-up in a default state in which the
program registers are reset to their default values.
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7.4.1.2 Data Acquisition Example
This section provides an example of how a host processor can use the device interface to configure the device
internal registers as well as convert and acquire data for sampling a particular input channel. The timing diagram
shown in 图 87 provides further details.
Sample
N
Sample
N + 1
CS
23
24
26
1
2
14
15
16
17
18
25
27
28
29
7
8
9
SCLK
30
31
32
Data from sample N
D14
D6
D5
D4
D3
D2
D1
D0
D15
D9
D8
D7
X
SDO
SDI
B14
B9
B8
B7
B2
B15
B1
B0
B3
X X X X X X X X
B10
1
2
3
4
图 87. Device Operation Using the Serial Interface Timing Diagram
There are four events shown in 图 87, which are described below:
•
Event 1: The host initiates a data conversion frame through a falling edge of the CS signal. The analog input
signal at the instant of the CS falling edge is sampled by the ADC and conversion is performed using an
internal oscillator clock. The analog input channel converted during this frame is selected in the previous data
frame. The internal register settings of the device for the next conversion can be input during this data frame
using the SDI and SCLK inputs. Initiate SCLK at this instant and latch data on the SDI line into the device on
every SCLK falling edge for the next 16 SCLK cycles. At this instant, SDO goes low because the device does
not output internal conversion data on the SDO line during the first 16 SCLK cycles.
•
•
•
Event 2: During the first 16 SCLK cycles, the device completes the internal conversion process and data are
now ready within the converter. However, the device does not output data bits on SDO until the 16th falling
edge appears on the SCLK input. Because the ADC conversion time is fixed (the maximum value is given in
the Electrical Characteristics table), the 16th SCLK falling edge must appear after the internal conversion is
over, otherwise data output from the device is incorrect. Therefore, the SCLK frequency cannot exceed a
maximum value, as provided in the Timing Requirements: Serial Interface table.
Event 3: At the 16th falling edge of the SCLK signal, the device reads the LSB of the input word on the SDI
line. The device does not read anything from the SDI line for the remaining data frame. On the same edge,
the MSB of the conversion data is output on the SDO line and can be read by the host processor on the
subsequent falling edge of the SCLK signal. For 16 bits of output data, the LSB can be read on the 32nd
SCLK falling edge. The SDO outputs 0 on subsequent SCLK falling edges until the next conversion is
initiated.
Event 4: When the internal data from the device is received, the host terminates the data frame by
deactivating the CS signal to high. The SDO output goes into a Hi-Z state until the next data frame is initiated,
as explained in Event 1.
7.4.1.3 Host-to-Device Connection Topologies
The digital interface of the ADS8688AT offers a lot of flexibility in the ways that a host controller can exchange
data or commands with the device. A typical connection between a host controller and a stand-alone device is
illustrated in 图 85. However, there are applications that require multiple ADCs but the host controller has limited
interfacing capability. This section describes two connection topologies that can be used to address the
requirements of such applications.
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7.4.1.3.1 Daisy-Chain Topology
图 88 shows a typical connection diagram with multiple devices in daisy-chain mode. The CS, SCLK, and SDI
inputs of all devices are connected together and controlled by a single CS, SCLK, and SDO pin of the host
controller, respectively. The DAISY1 input pin of the first ADC in the chain is connected to DGND, the SDO1
output pin is connected to the DAISY2 input of ADC2, and so forth. The SDON pin of the Nth ADC in the chain is
connected to the SDI pin of the host controller. The devices do not require any special hardware or software
configuration to enter daisy-chain mode.
Host Controller
SDI
SDO
CS
SCLK
CS
SCLK SDI
CS
SCLK SDI
CS
SCLK SDI
DAISY2
SDO2
DAISY1
SDO1
DAISYN
SDON
DGND
ADC1
ADC2
ADCN
图 88. Daisy-Chain Connection Schematic
图 89 shows a typical timing diagram for three devices connected in daisy-chain mode.
Sample
N
Sample
N + 1
tS
CS
1
2
15
16
17
18
33
34
49
50
31
32
47
48
63
64
SCLK
SDI
X
X
X
X
X
X
X
X
X
X
B14
B2
B1
B0
X
B15
X
SDO1,
DAISY2
{D15}1 {D14}1
{D15}2 {D14}2
{D15}3 {D14}3
{D1}1 {D0}1
SDO2,
DAISY3
{D1}2 {D0}2 {D15}1 {D14}1
{D1}1 {D0}1
{D15}2 {D14}2
{D1}3 {D0}3
{D1}2 {D0}2 {D15}1 {D14}1
{D1}1 {D0}1
SDO3
Data from Sample N
ADC3
Data from Sample N
ADC2
Data from Sample N
ADC1
图 89. Three Devices Connected in Daisy-Chain Mode Timing Diagram
At the falling edge of the CS signal, all devices sample the input signal at their respective selected channels and
enter into conversion phase. For the first 16 SCLK cycles, the internal register settings for the next conversion
can be entered using the SDI line that is common to all devices in the chain. During this time period, the SDO
outputs for all devices remain low. At the end of conversion, every ADC in the chain loads its own conversion
result into an internal 16-bit shift register. At the 16th SCLK falling edge, every ADC in the chain outputs the MSB
bit on its own SDO output pin. On every subsequent SCLK falling edge, the internal shift register of each ADC
latches the data available on its DAISY pin and shifts out the next bit of data on its SDO pin. Therefore, the
digital host receives the data of ADCN, followed by the data of ADCN–1, and so forth (in MSB-first fashion). In
total, a minimum of 16 × N SCLK falling edges are required to capture the outputs of all N devices in the chain.
This example uses three devices in a daisy-chain connection, so 3 × 16 = 48 SCLK cycles are required to
capture the outputs of all devices in the chain along with the 16 SCLK cycles to input the register settings for the
next conversion, resulting in a total of 64 SCLK cycles for the entire data frame. The overall throughput of the
system is proportionally reduced with the number of devices connected in a daisy-chain configuration.
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The following points must be noted about the daisy-chain configuration illustrated in 图 88:
•
The SDI pins for all devices are connected together so each device operates with the same internal
configuration. This limitation can be overcome by spending additional host controller resources to control the
CS or SDI input of devices with unique configurations.
•
If the number of devices connected in daisy-chain is more than four, loading increases on the shared output
lines from the host controller (CS, SDO, and SCLK). This increased loading can lead to digital timing errors.
This limitation can be overcome by using digital buffers on the shared outputs from the host controller before
feeding the shared digital lines into additional devices.
7.4.1.3.2 Star Topology
图 90 shows a typical connection diagram with multiple devices in the star topology. The SDI and SCLK inputs of
all devices are connected together and are controlled by a single SDO and SCLK pin of the host controller,
respectively. Similarly, the SDO outputs of all devices are tied together and connected to the SDI input pin of the
host controller. The CS input pin of each device is individually controlled by separate CS control lines from the
host controller.
CS1
CS2
CS
SCLK
CSN
SDO
SDI
ADC1
CS
SCLK
SDI
SDO
SDI
ADC2
CS
SCLK
SDI
SDO
SDO
SCLK
ADCN
图 90. Star Topology Connection Schematic
The timing diagram for a typical data frame in the star topology is the same as in a stand-alone device operation,
as illustrated in 图 87. The data frame for a particular device starts with the falling edge of the CS signal and
ends when the CS signal goes high. Because the host controller provides separate CS control signals for each
device in this topology, devices can be selected in any order and conversions can be initiated by bringing down
the CS signal for that particular device. As explained in 图 87, when CS goes high at the end of each data frame,
the SDO output of the device is placed into a Hi-Z state. Therefore, the shared SDO line in the star topology is
controlled only by the device with an active data frame (CS is low). In order to avoid any conflict related to
multiple devices driving the SDO line at the same time, ensure that the host controller pulls down the CS signal
for only one device at any particular time.
TI recommends connecting a maximum of four devices in the star topology. Beyond that, loading may increase
on the shared output lines from the host controller (SDO and SCLK). This loading can lead to digital timing
errors. This limitation can be overcome by using digital buffers on the shared outputs from the host controller
before being fed into additional devices.
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7.4.2 Device Modes
The ADS8688AT supports multiple modes of operation that are software programmable. After powering up, the
device is placed into idle mode and does not perform any function until a command is received from the user. 表
7 lists all commands to enter the different modes of the device. After power-up, the program registers wake up
with the default values and require appropriate configuration settings before performing any conversion. The
diagram in 图 91 explains how to switch the device from one mode of operation to another.
RESET
(RST)
Program Registers
are set to default
values
RST
NO_OP
IDLE
Device waits for a
valid command to
initiate conversion
MAN_Ch_n
NO_OP
NO_OP
MANUAL
Channel n
(MAN_Ch_n)
STANDBY
(STDBY)
MAN_Ch_n / AUTO_RST
STDBY / PWR_DN / PROG
AUTO
Ch. Scan
(AUTO)
POWER
DOWN
(PWR_DN)
PROGRAM
REGISTER
(PROG)
AUTO Seq.
RESET
(AUTO_RST)
PWR_DN
PROG
NO_OP
IDLE
AUTO_RST
图 91. State Transition Diagram
7.4.2.1 Continued Operation in the Selected Mode (NO_OP)
Holding the SDI line low continuously (equivalent to writing a 0 to all 16 bits) during device operation continues
device operation in the last selected mode (STDBY, PWR_DN, AUTO_RST, or MAN_Ch_n). In this mode, the
device follows the same settings that are already configured in the program registers.
If a NO_OP condition occurs when the device is performing any read or write operation in the program register
(PROG mode), then the device retains the current settings of the program registers. The device goes back to
IDLE mode and waits for a proper command to be entered before executing the program register read or write
configuration.
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7.4.2.2 Frame Abort Condition (FRAME_ABORT)
As explained in the Data Acquisition Example section, the device digital interface is designed such that each data
frame starts with a falling edge of the CS signal. During the first 16 SCLK cycles, the device reads the 16-bit
command word on the SDI line. The device waits to execute the command until the last bit of the command is
received, which is latched on the 16th SCLK falling edge. During this operation, the CS signal must stay low. If
the CS signal goes high for any reason before the data transmission is complete, the device goes into an
INVALID state and waits for a proper command to be written. This condition is called the FRAME_ABORT
condition. When the device is operating in this INVALID mode, any read operation on the device returns invalid
data on the SDO line. The output of the ALARM pin continues to reflect the status of input signal on the
previously selected channel.
7.4.2.3 STANDBY Mode (STDBY)
The device supports a low-power standby mode (STDBY) in which only part of the circuit is powered down. The
internal reference and buffer is not powered down, and therefore, the device can be quickly powered up in 20 µs
on exiting the STDBY mode. When the device comes out of STDBY mode, the program registers are not reset to
the default values.
To enter STDBY mode, execute a valid write operation as shown in 图 92 to the command register with a
STDBY command of 8200h. The command is executed and the device enters STDBY mode on the next CS
rising edge following this write operation. The device remains in STDBY mode if no valid conversion command
(AUTO_RST or MAN_Ch_n) is executed and SDI remains low (see the Continued Operation in the Selected
Mode (NO_OP) section) during the subsequent data frames. When the device operates in STDBY mode, the
program register settings can be updated (as explained in the Program Register Read/Write Operation section)
using 16 SCLK cycles. However, if 32 complete SCLK cycles are provided, then the device returns invalid data
on the SDO line because there is no ongoing conversion in STDBY mode. The program register read operation
can take place normally during this mode.
Sample N
Enters STDBY on
CS Rising Edge
CS can go high immediately after Standby
command or after reading frame data.
CS
16
17
16
1
2
14
15
18
30
31
32
1
2
14
15
SCLK
Stays in STDBY
if SDI is Low in a
Data Frame
X
STDBY Command œ 8200h
X
X
X
X
X
X
X
SDI
Data from Sample N
D14
D2
D1
D0
D15
D3
SDO
图 92. Enter and Remain in STDBY Mode Timing Diagram
42
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In order to exit STDBY mode, as shown in 图 93, a valid 16-bit write command must be executed to enter auto
(AUTO_RST) or manual (MAN_CH_n) scan mode. The device starts exiting STDBY mode on the next CS rising
edge. At the next CS falling edge, the device samples the analog input at the channel selected by the
MAN_CH_n command or the first channel of the AUTO_RST mode sequence. To ensure that the input signal is
sampled correctly, keep the minimum width of the CS signal at 20 µs after exiting STDBY mode so the device
internal circuitry can be fully powered up and biased properly before taking the sample. The data output for the
selected channel can be read during the same data frame, as explained in 图 87.
Device exits
STDBY Mode on
CS Rising Edge
CS
Min width of CS HIGH = 20µs
for valid sample
16
1
2
3
4
5
12
13
14
15
6
7
8
9
10
11
SCLK
AUTO_RST Command
MAN_CH_n Command
SDI
SDO
图 93. Exit STDBY Mode Timing Diagram
7.4.2.4 Power-Down Mode (PWR_DN)
The device supports a hardware and software power-down mode (PWR_DN) in which all internal circuitry is
powered down, including the internal reference and buffer. A minimum time of 15 ms is required for the device to
power up and convert the selected analog input channel after exiting PWR_DN mode, if the device is operating
in the internal reference mode (REFSEL = 0). The hardware power-down mode for the device is explained in the
RST/PD (Input) section. The primary difference between the hardware and software power-down modes is that
the program registers are reset to default values when the devices wake up from hardware power-down, but the
previous settings of the program registers are retained when the devices wake up from software power-down.
To enter PWR_DN mode using software, execute a valid write operation as depicted in 图 94 on the command
register with a software PWR_DN command of 8300h. The command is executed and the device enters
PWR_DN mode on the next CS rising edge following this write operation. The device remains in PWR_DN mode
if no valid conversion command (AUTO_RST or MAN_Ch_n) is executed and SDI remains low (see the
Continued Operation in the Selected Mode (NO_OP) section) during the subsequent data frames. When the
device operates in PWR_DN mode, the program register settings can be updated (as explained in the Program
Register Read/Write Operation section) using 16 SCLK cycles. However, if 32 complete SCLK cycles are
provided, then the device returns invalid data on the SDO line because there is no ongoing conversion in
PWR_DN mode. The program register read operation can take place normally during this mode.
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Sample N
Enters PWR_DN on
CS Rising Edge
CS can go high immediately after PWR_DN
command or after reading frame data.
CS
16
17
16
1
2
14
15
18
30
31
32
1
2
14
15
SCLK
Stays in PWR_DN
if SDI is Low in a
Data Frame
X
PWR_DN Command œ 8300h
X
X
X
X
X
X
X
SDI
Data from Sample N
D14
D2
D1
D0
D15
D3
SDO
图 94. Enter and Remain in PWR_DN Mode Timing Diagram
In order to exit from PWR_DN mode, as shown in 图 95, a valid 16-bit write command must be executed. The
device comes out of PWR_DN mode on the next CS rising edge. For operation in internal reference mode
(REFSEL = 0), 15 ms are required for the device to power-up the reference and other internal circuits and settle
to the required accuracy before valid conversion data are output for the selected input channel.
First 16-bit accurate data
frame after recovery from
PWR_DN mode
Device exits PWR_DN Mode, but
waits 15ms for 16-bit settling
CS
16
1
2
3
4
5
12
13
14
15
6
7
8
9
10
11
SCLK
AUTO_RST Command
MAN_CH_n Command
SDI
SDO
Invalid
Data
图 95. Exit PWR_DN Mode Timing Diagram
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7.4.2.5 Auto Channel Enable With Reset (AUTO_RST)
The device can be programmed as explained in 图 96 to scan the input signal on all analog channels
automatically by writing a valid auto channel sequence with a reset (AUTO_RST, A000h) command in the
command register. As shown in 图 96, the CS signal can be pulled high immediately after the AUTO_RST
command or after reading the output data of the frame. However, in order to accurately acquire and convert the
input signal on the first selected channel in the next data frame, the command frame must be a complete frame
of 32 SCLK cycles.
The sequence of channels for the automatic scan can be configured by the AUTO SCAN sequencing control
register (01h to 02h) in the program register; see the Program Register Map section. In this mode, the device
continuously cycles through the selected channels in ascending order, beginning with the lowest channel and
converting all channels selected in the program register. On completion of the sequence, the device returns to
the lowest count channel in the program register and repeats the sequence. The input voltage range for each
channel in the auto-scan sequence can be configured by setting the range select registers of the program
registers.
Samples 2nd Ch. of
Auto-Ch Sequence
Sample N
Enters AUTO_RST Mode on CS Rising Edge
Samples 1st Ch. of Auto-Ch Sequence
CS can go high immediately after AUTO_RST
command or after reading frame data.
CS
16
17
16
32
1
2
14
15
18
30
31
32
1
2
14
15
31
SCLK
Stays in AUTO_RST Mode if
SDI is Low in a Data Frame
X
AUTO_RST Command œ A000h
X
X
X
X
X
X
X
SDI
Data from Sample N
Data from 1st Ch of Seq.
D14
D2
D1
D0
D15
D3
SDO
图 96. Enter AUTO_RST Mode Timing Diagram
The device remains in AUTO_RST mode if no other valid command is executed and SDI is kept low (see the
Continued Operation in the Selected Mode (NO_OP) section) during subsequent data frames. If the AUTO_RST
command is executed again at any time during this mode of operation, then the sequence of the scanned
channels is reset. The device returns to the lowest count channel of the auto-scan sequence in the program
register and repeats the sequence. The timing diagram in 图 97 shows this behavior using an example in which
channels 0 to 2 are selected in the auto sequence. For switching between AUTO_RST mode and MAN_Ch_n
mode; see the Channel Sequencing Modes section.
Sample
N
Ch 0
Sample
Ch 1
Sample
Ch 2
Sample
Ch 0
Sample
CS
SCLK
SDI
AUTO_RST
xxxx
0000h
xxxx
0000h
xxxx
AUTO_RST
xxxx
0000h
xxxx
SDO
Sample N Data
Ch 0 Data
Ch 1 Data
Ch 2 Data
Ch 0 Data
Based on Previous
Mode Setting
AUTO_RST Mode
(Channel sequence restarted from
AUTO_RST Mode
(Channels 0-2 are selected in sequence.)
lowest count.)
图 97. Device Operation Example in AUTO_RST Mode
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7.4.2.6 Manual Channel n Select (MAN_Ch_n)
The device can be programmed to convert a particular analog input channel by operating in manual channel n
scan mode (MAN_Ch_n). This programming is done as shown in 图 98 by writing a valid manual channel n
select command (MAN_Ch_n) in the command register. As shown in 图 98, the CS signal can be pulled high
immediately after the MAN_Ch_n command or after reading the output data of the frame. However, in order to
accurately acquire and convert the input signal on the next channel, the command frame must be a complete
frame of 32 SCLK cycles. See 表 7 for a list of commands to select individual channels during MAN_Ch_n mode.
Sample N
2nd Sample of Manual Ch. n
Enters MAN_Ch_n Mode on CS Rising Edge
1st Sample of Manual Channel N
CS can go high immediately after MAN_Ch_n
command or after reading frame data.
CS
16
17
16
32
1
2
14
15
18
30
31
32
1
2
14
15
31
SCLK
Stays in MAN_Ch_n Mode if
SDI is Low in a Data Frame
X
MAN_Ch_n Command
X
X
X
X
X
X
X
SDI
Data from Sample N
Sample 1 of Channel n
D14
D2
D1
D0
D15
D3
SDO
图 98. Enter MAN_Ch_n Scan Mode Timing Diagram
The manual channel n select command (MAN_Ch_n) is executed and the device samples the analog input on
the selected channel on the CS falling edge of the next data frame following this write operation. The input
voltage range for each channel in the MAN_Ch_n mode can be configured by setting the range select registers
in the program registers. The device continues to sample the analog input on the same channel if no other valid
command is executed and SDI is kept low (see the Continued Operation in the Selected Mode (NO_OP) section)
during subsequent data frames. The timing diagram in 图 99 shows this behavior using an example in which
channel 1 is selected in the manual sequencing mode. For switching between MAN_Ch_n mode and
AUTO_RST mode; see the Channel Sequencing Modes section.
Sample
N
Ch 1
Sample
Ch 1
Sample
Ch 1
Sample
Ch 3
Sample
CS
SCLK
SDI
MAN_Ch_1
xxxx
0000h
xxxx
0000h
xxxx
MAN_Ch_3
xxxx
0000h
xxxx
SDO
Sample N Data
Ch 1 Data
Ch 1 Data
Ch 1 Data
Ch 3 Data
Based on Previous
Mode Setting
MAN_Ch_n Mode
(Ch 1 is selected and device continuously converts Ch 1 if NO_OP command is provided)
MAN_Ch_n Mode
(Transition from Ch1 to Ch 3)
图 99. Device Operation in MAN_Ch_n Mode
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7.4.2.7 Channel Sequencing Modes
The device offers two channel sequencing modes: AUTO_RST and MAN_Ch_n.
In AUTO_RST mode, the channel number automatically increments in every subsequent frame. As explained in
the auto-scan sequencing control registers, the analog inputs can be selected for an automatic scan with a
register setting. The device automatically scans only the selected analog inputs in ascending order. The
unselected analog input channels can also be powered down for optimizing power consumption in this mode of
operation. The auto-mode sequence can be reset at any time during an automatic scan (using the AUTO_RST
command). When the reset command is received, the ongoing auto-mode sequence is reset and restarts from
the lowest selected channel in the sequence.
In MAN_Ch_n mode, the same input channel is selected during every data conversion frame. The input
command words to select individual analog channels in MAN_Ch_n mode are listed in 表 7. If a particular input
channel is selected during a data frame, then the analog inputs on the same channel are sampled during the
next data frame. 图 100 shows the SDI command sequence for transitions from AUTO_RST to MAN_Ch_n
mode.
Ch 0
Ch 5
Ch 1
Ch 3
Sample
Sample
Sample
Sample
CS
SCLK
SDI
0000h
xxxx
MAN_Ch_1
xxxx
MAN_Ch_3
xxxx
MAN_Ch_n
xxxx
SDO
Ch 0 Data
Ch 5 Data
Ch 1 Data
Ch 3 Data
AUTO_RST Mode
MAN_Ch_n Mode
图 100. Transitioning From AUTO_RST to MAN_Ch_n Mode
(Channels 0 and 5 are Selected for Auto Sequence)
图 101 shows the SDI command sequence for transitions from MAN_Ch_n to AUTO_RST mode. Each SDI
command is executed on the next CS falling edge. A RST command can be issued at any instant during any
channel sequencing mode, after which the device is placed into a default power-up state in the next data frame.
Sample
N
Ch 2
Sample
Ch 0
Sample
Ch 5
Sample
CS
SCLK
SDI
MAN_Ch_2
xxxx
AUTO_RST
xxxx
0000h
xxxx
0000h
xxxx
SDO
Sample N Data
Ch 2 Data
Ch 0 Data
Ch 5 Data
Based on Previous
Mode Setting
MAN_Ch_n Mode
AUTO_RST Mode
图 101. Transitioning From MAN_Ch_n to AUTO_RST Mode
(Channels 0 and 5 are Selected for Auto Sequence)
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7.4.2.8 Reset Program Registers (RST)
The device supports a hardware and software reset (RST) mode in which all program registers are reset to their
default values. The device can be put into RST mode using a hardware pin, as explained in the RST/PD (Input)
section.
The device program registers can be reset to their default values, as shown in 图 102, during any data frame by
executing a valid write operation on the command register with a RST command of 8500h. The device remains in
RST mode if no valid conversion command (AUTO_RST or MAN_Ch_n) is executed and SDI remains low (see
the Continued Operation in the Selected Mode (NO_OP) section) during the subsequent data frames. When the
device operates in RST mode, the program register settings can be updated (as explained in the Program
Register Read/Write Operation section) using 16 SCLK cycles. However, if 32 complete SCLK cycles are
provided, then the device returns invalid data on the SDO line because there is no ongoing conversion in RST
mode. The values of the program register can be read normally during this mode. A valid AUTO_RST or
MAN_CH_n channel selection command must be executed for initiating a conversion on a particular analog
channel using the default program register settings.
All Program
Registers are Reset
Sample N
to Default Values on
CS Rising Edge
CS can go high immediately after RST
command or after reading frame data.
CS
16
17
1
2
13
14
15
18
30
31
32
3
4
5
SCLK
X
Reset Program Registers (RST) œ 8500h
X
X
X
X
X
X
X
SDI
Data from Sample N
D14
D2
D1
D0
D15
D3
SDO
图 102. Reset Program Registers (RST) Timing Diagram
7.5 Register Maps
The internal registers of the ADS8688AT are categorized into two categories: command registers and program
registers.
The command registers are used to select the channel sequencing mode (AUTO_RST or MAN_Ch_n), configure
the device in standby (STDBY) or power-down (PWR_DN) mode, and reset (RST) the program registers to their
default values.
The program registers are used to select the sequence of channels for AUTO_RST mode, select the SDO output
format, control input range settings for individual channels, control the ALARM feature, reading the alarm flags,
and programming the alarm thresholds for each channel.
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Register Maps (接下页)
表 6 lists the access codes used for the ADS8688AT registers.
表 6. ADS8688AT Access Type Codes
Access Type
Code
Description
Read Type
R
R
Read
R-W
R/W
Read or write
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
7.5.1 Command Register Description
The command register is a 16-bit, write-only register that is used to set the operating modes of the ADS8688AT.
The settings in this register are used to select the channel sequencing mode (AUTO_RST or MAN_Ch_n),
configure the device in standby (STDBY) or power-down (PWR_DN) mode, and reset (RST) the program
registers to their default values. 表 7 lists all command settings for this register. During power-up or reset, the
default content of the command register is all 0's and the device waits for a command to be written before being
placed into any mode of operation. See 图 1 for a typical timing diagram for writing a 16-bit command into the
device. The device executes the command at the end of this particular data frame when the CS signal goes high.
表 7. Command Register Map
MSB BYTE
LSB BYTE
B[7:0]
COMMAND
(Hex)
REGISTER
OPERATION IN NEXT FRAME
B15 B14 B13 B12 B11 B10 B9
B8
Continued Operation
(NO_OP)
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
0
1
0
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000h
8200h
8300h
8500h
A000h
C000h
C400h
C800h
CC00h
D000h
D400h
D800h
DC00h
E000h
Continue operation in previous mode
Device is placed into standby mode
Device is powered down
Standby
(STDBY)
0
1
1
0
0
0
0
0
0
0
0
0
0
Power Down
(PWR_DN)
Reset Program Registers
(RST)
Program register is reset to default
Auto mode enabled following a reset
Channel 0 input is selected
Channel 1 input is selected
Channel 2 input is selected
Channel 3 input is selected
Channel 4 input is selected
Channel 5 input is selected
Channel 6 input is selected
Channel 7 input is selected
AUX channel input is selected
Auto Ch. Sequence With Reset
(AUTO_RST)
Manual Ch 0 Selection
(MAN_Ch_0)
Manual Ch 1 Selection
(MAN_Ch_1)
Manual Ch 2 Selection
(MAN_Ch_2)
Manual Ch 3 Selection
(MAN_Ch_3)
Manual Ch 4 Selection
(MAN_Ch_4)
Manual Ch 5 Selection
(MAN_Ch_5)
Manual Ch 6 Selection
(MAN_Ch_6)
Manual Ch 7 Selection
(MAN_Ch_7)
Manual AUX Selection
(MAN_AUX)
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7.5.2 Program Register Description
The program register is a 16-bit register used to set the operating modes of the ADS8688AT. The settings in this
register are used to select the channel sequence for AUTO_RST mode, configure the device ID in daisy-chain
mode, select the SDO output format, control input range settings for individual channels, control the ALARM
feature, reading the alarm flags, and programming the alarm thresholds for each channel. All program settings
for this register are listed in 表 10. During power-up or reset, the different program registers in the device wake
up with their default values and the device waits for a command to be written before being placed into any mode
of operation.
7.5.2.1 Program Register Read/Write Operation
The program register is a 16-bit read or write register. There must be a minimum of 24 SCLKs after the CS
falling edge for any read or write operation to the program registers. When CS goes low, the SDO line goes low
as well. The device receives the command (see 表 8 and 表 9) through SDI where the first seven bits (bits 15-9)
represent the register address and the eighth bit (bit 8) is the write or read instruction.
For a write cycle, the next eight bits (bits 7-0) on SDI are the desired data for the addressed register. Over the
next eight SCLK cycles, the device outputs this 8-bit data that is written into the register. This data readback
allows verification to determine if the correct data are entered into the device. 图 103 shows a typical timing
diagram for a program register write cycle.
表 8. Write Cycle Command Word
REGISTER ADDRESS
(Bits 15-9)
WR/RD
(Bit 8)
DATA
(Bits 7-0)
PIN
SDI
ADDR[6:0]
1
DIN[7:0]
Sample
N
CS
24
16
23
15
17
18
1
2
6
7
8
9
10
SCLK
SDI
DIN [7:0]
X X X X
ADDR [6:0]
WR
Data written into register, DIN [7:0]
SDO
图 103. Program Register Write Cycle Timing Diagram
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For a read cycle, the next eight bits (bits 7-0) on SDI are don’t care bits and SDO stays low. From the 16th SCLK
falling edge and onwards, SDO outputs the 8-bit data from the addressed register during the next eight clocks, in
MSB-first fashion. 图 104 shows a typical timing diagram for a program register read cycle.
表 9. Read Cycle Command Word
REGISTER ADDRESS
(Bits 15-9)
WR/RD
(Bit 8)
DATA
(Bits 7-0)
PIN
SDI
ADDR[6:0]
0000 000
0
0
XXXXX
SDO
DOUT[7:0]
CS
24
16
23
15
17
18
1
2
6
7
8
9
10
SCLK
SDI
X X X X X X
ADDR [6:0]
RD
DOUT [7:0]
SDO
图 104. Program Register Read Cycle Timing Diagram
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7.5.2.2 Program Register Map
This section provides a bit-by-bit description of each program register.
表 10. Program Register Map
REGISTER
ADDRESS
BITS[15:9]
REGISTER BITS
DEFAULT
VALUE(1)
REGISTER
7
6
5
4
3
2
1
0
AUTO SCAN SEQUENCING CONTROL
AUTO_SEQ_EN
01h
02h
FFh
00h
CH7_EN
CH7_PD
CH6_EN
CH6_PD
CH5_EN
CH5_PD
CH4_EN
CH4_PD
CH3_EN
CH3_PD
CH2_EN
CH2_PD
CH1_EN
CH1_PD
CH0_EN
CH0_PD
Channel Power Down
DEVICE FEATURES SELECTION CONTROL
Feature Select
03h
00h
DEV[1:0]
0
ALARM_EN
0
SDO [2:0]
RANGE SELECT REGISTERS
Channel 0 Input Range
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
00h
00h
00h
00h
00h
00h
00h
00h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Range Select Channel 0[3:0]
Range Select Channel 1[3:0]
Range Select Channel 2[3:0]
Range Select Channel 3[3:0]
Range Select Channel 4[3:0]
Range Select Channel 5[3:0]
Range Select Channel 6[3:0]
Range Select Channel 7[3:0]
Channel 1 Input Range
Channel 2 Input Range
Channel 3 Input Range
Channel 4 Input Range
Channel 5 Input Range
Channel 6 Input Range
Channel 7 Input Range
ALARM FLAG REGISTERS (Read-Only)
Tripped Alarm
Flag Ch7
Tripped Alarm
Flag Ch6
Tripped Alarm
Flag Ch5
Tripped Alarm
Flag Ch4
Tripped Alarm
Flag Ch3
Tripped Alarm
Flag Ch2
Tripped Alarm
Flag Ch1
Tripped Alarm
Flag Ch0
ALARM Overview Tripped-Flag
ALARM Ch 0-3 Tripped-Flag
ALARM Ch 0-3 Active-Flag
ALARM Ch 4-7 Tripped-Flag
ALARM Ch 4-7 Active-Flag
10h
11h
12h
13h
14h
00h
00h
00h
00h
00h
Tripped Alarm
Flag Ch0 Low Flag Ch0 High Flag Ch1 Low
Tripped Alarm
Tripped Alarm
Tripped Alarm
Tripped Alarm
Tripped Alarm
Tripped Alarm
Tripped Alarm
Flag Ch1 High Flag Ch2 Low Flag Ch2 High Flag Ch3 Low Flag Ch3 High
Active Alarm Active Alarm Active Alarm
Active Alarm Active Alarm Active Alarm Active Alarm Active Alarm
Flag Ch0 Low Flag Ch0 High Flag Ch1 Low
Tripped Alarm Tripped Alarm Tripped Alarm
Flag Ch1 High Flag Ch2 Low Flag Ch2 High Flag Ch3 Low Flag Ch3 High
Tripped Alarm Tripped Alarm Tripped Alarm Tripped Alarm Tripped Alarm
Flag Ch4 Low Flag Ch4 High Flag Ch5 Low
Flag Ch5 High Flag Ch6 Low Flag Ch6 High Flag Ch7 Low Flag Ch7 High
Active Alarm Active Alarm Active Alarm
Flag Ch4 Low Flag Ch4 High Flag Ch5 Low
Active Alarm Active Alarm Active Alarm Active Alarm Active Alarm
Flag Ch5 High Flag Ch6 Low Flag Ch6 High Flag Ch7 Low Flag Ch7 High
(1) All registers are reset to the default values at power-on or at device reset using the register settings method.
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表 10. Program Register Map (接下页)
REGISTER
ADDRESS
BITS[15:9]
REGISTER BITS
DEFAULT
VALUE(1)
REGISTER
7
6
5
4
3
2
1
0
ALARM THRESHOLD REGISTERS
Ch 0 Hysteresis
15h
16h
17h
18h
19h
…
00h
FFh
FFh
00h
00h
…
CH0_HYST[7:0]
CH0_HT[15:8]
CH0_HT[7:0]
CH0_LT[15:8]
CH0_LT[7:0]
Ch 0 High Threshold MSB
Ch 0 High Threshold LSB
Ch 0 Low Threshold MSB
Ch 0 Low Threshold LSB
…
See the alarm threshold setting registers for details regarding the ALARM threshold settings registers.
Ch 7 Hysteresis
38h
39h
3Ah
3Bh
3Ch
00h
FFh
FFh
00h
00h
CH7_HYST[7:0]
CH7_HT[15:8]
CH7_HT[7:0]
CH7_LT[15:8]
CH7_LT[7:0]
Ch 7 High Threshold MSB
Ch 7 High Threshold LSB
Ch 7 Low Threshold MSB
Ch 7 Low Threshold LSB
COMMAND READ BACK (Read-Only)
Command Read Back
3Fh
00h
COMMAND_WORD[7:0]
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7.5.2.3 Program Register Descriptions
7.5.2.3.1 Auto-Scan Sequencing Control Registers
In AUTO_RST mode, the device automatically scans the preselected channels in ascending order with a new
channel selected for every conversion. Each individual channel can be selectively included in the auto channel
sequencing. For channels not selected for auto sequencing, the analog front-end circuitry can be individually
powered down.
7.5.2.3.1.1 Auto-Scan Sequence Enable Register (address = 01h)
This register selects individual channels for sequencing in AUTO_RST mode. The default value for this register is
FFh, which implies that in default condition all channels are included in the auto-scan sequence. If no channels
are included in the auto sequence (that is, the value for this register is 00h), then channel 0 is selected for
conversion by default.
图 105. AUTO_SEQ_EN Register
7
6
5
4
3
2
1
0
CH7_EN
R/W-1h
CH6_EN
R/W-1h
CH5_EN
R/W-1h
CH4_EN
R/W-1h
CH3_EN
R/W-1h
CH2_EN
R/W-1h
CH1_EN
R/W-1h
CH0_EN
R/W-1h
表 11. AUTO_SEQ_EN Field Descriptions
Bit
Field
Type
Reset
Description
7
CH7_EN
R/W
1h
Channel 7 enable.
0 = Channel 7 is not selected for sequencing in AUTO_RST mode
1 = Channel 7 is selected for sequencing in AUTO_RST mode
6
5
4
3
2
1
0
CH6_EN
CH5_EN
CH4_EN
CH3_EN
CH2_EN
CH1_EN
CH0_EN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1h
1h
1h
1h
1h
1h
1h
Channel 6 enable.
0 = Channel 6 is not selected for sequencing in AUTO_RST mode
1 = Channel 6 is selected for sequencing in AUTO_RST mode
Channel 5 enable.
0 = Channel 5 is not selected for sequencing in AUTO_RST mode
1 = Channel 5 is selected for sequencing in AUTO_RST mode
Channel 4 enable.
0 = Channel 4 is not selected for sequencing in AUTO_RST mode
1 = Channel 4 is selected for sequencing in AUTO_RST mode
Channel 3 enable.
0 = Channel 3 is not selected for sequencing in AUTO_RST mode
1 = Channel 3 is selected for sequencing in AUTO_RST mode
Channel 2 enable.
0 = Channel 2 is not selected for sequencing in AUTO_RST mode
1 = Channel 2 is selected for sequencing in AUTO_RST mode
Channel 1 enable.
0 = Channel 1 is not selected for sequencing in AUTO_RST mode
1 = Channel 1 is selected for sequencing in AUTO_RST mode
Channel 0 enable.
0 = Channel 0 is not selected for sequencing in AUTO_RST mode
1 = Channel 0 is selected for sequencing in AUTO_RST mode
54
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7.5.2.3.1.2 Channel Power Down Register (address = 02h)
This register powers down individual channels that are not included for sequencing in AUTO_RST mode. The
default value for this register is 00h, which implies that in default condition all channels are powered up. If all
channels are powered down (that is, the value for this register is FFh), then the analog front-end circuits for all
channels are powered down and the output of the ADC contains invalid data. If the device is in MAN-Ch_n mode
and the selected channel is powered down, then the device yields invalid output that can also trigger a false
alarm condition.
图 106. Channel Power Down Register
7
6
5
4
3
2
1
0
CH7_PD
R/W-0h
CH6_PD
R/W-0h
CH5_PD
R/W-0h
CH4_PD
R/W-0h
CH3_PD
R/W-0h
CH2_PD
R/W-0h
CH1_PD
R/W-0h
CH0_PD
R/W-0h
表 12. Channel Power Down Register Field Descriptions
Bit
Field
Type
Reset
Description
7
CH7_PD
R/W
0h
Channel 7 power-down.
0 = The analog front-end on channel 7 is powered up and channel 7 can be
included in the AUTO_RST sequence
1 = The analog front-end on channel 7 is powered down and channel 7
cannot be included in the AUTO_RST sequence
6
5
4
3
2
1
0
CH6_PD
CH5_PD
CH4_PD
CH3_PD
CH2_PD
CH1_PD
CH0_PD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
Channel 6 power-down.
0 = The analog front-end on channel 6 is powered up and channel 6 can be
included in the AUTO_RST sequence
1 = The analog front-end on channel 6 is powered down and channel 6
cannot be included in the AUTO_RST sequence
Channel 5 power-down.
0 = The analog front-end on channel 5 is powered up and channel 5 can be
included in the AUTO_RST sequence
1 = The analog front-end on channel 5 is powered down and channel 5
cannot be included in the AUTO_RST sequence
Channel 4 power-down.
0 = The analog front-end on channel 4 is powered up and channel 4 can be
included in the AUTO_RST sequence
1 = The analog front-end on channel 4 is powered down and channel 4
cannot be included in the AUTO_RST sequence
Channel 3 power-down.
0 = The analog front-end on channel 3 is powered up and channel 3 can be
included in the AUTO_RST sequence
1 = The analog front end on channel 3 is powered down and channel 3
cannot be included in the AUTO_RST sequence
Channel 2 power-down.
0 = The analog front end on channel 2 is powered up and channel 2 can be
included in the AUTO_RST sequence
1 = The analog front end on channel 2 is powered down and channel 2
cannot be included in the AUTO_RST sequence
Channel 1 power-down.
0 = The analog front end on channel 1 is powered up and channel 1 can be
included in the AUTO_RST sequence
1 = The analog front end on channel 1 is powered down and channel 1
cannot be included in the AUTO_RST sequence
Channel 0 power-down.
0 = The analog front end on channel 0 is powered up and channel 0 can be
included in the AUTO_RST sequence
1 = The analog front end on channel 0 is powered down and channel 0
cannot be included in the AUTO_RST sequence
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7.5.2.3.2 Device Features Selection Control Register (address = 03h)
The bits in this register can be used to configure the device ID for daisy-chain operation, enable the ALARM
feature, and configure the output bit format on SDO.
图 107. Feature Select Register
7
6
5
0
4
3
0
2
1
0
DEV[1:0]
R/W-0h
ALARM_EN
R/W-0h
SDO[2:0]
R/W-0h
R-0h
R-0h
表 13. Feature Select Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
DEV[1:0]
R/W
0h
Device ID bits.
00 = ID for device 0 in daisy-chain mode
01 = ID for device 1 in daisy-chain mode
10 = ID for device 2 in daisy-chain mode
11 = ID for device 3 in daisy-chain mode
5
4
0
0
R
0h
0h
Must always be set to 0
R/W
ALARM feature enable.
0 = ALARM feature is disabled
1 = ALARM feature is enabled
3
0
R
0h
0h
Must always be set to 0
2-0
SDO[2:0]
R/W
SDO data format bits (see 表 14).
表 14. Description of Program Register Bits for SDO Data Format
OUTPUT FORMAT
BITS 8-5
SDO FORMAT
SDO[2:0]
BEGINNING OF THE
OUTPUT BIT STREAM
BITS 24-9
BITS 4-3
BITS 2-0
16th SCLK falling edge,
no latency
Conversion result for selected
channel (MSB-first)
000
001
010
011
SDO pulled low
16th SCLK falling edge,
no latency
Conversion result for selected
channel (MSB-first)
Channel
SDO pulled low
address(1)
16th SCLK falling edge,
no latency
Conversion result for selected
channel (MSB-first)
Channel
Device
SDO pulled
low
address(1)
address(1)
16th SCLK falling edge,
no latency
Conversion result for selected
channel (MSB-first)
Channel
Device
Input
address(1)
address(1)
range(1)
(1) 表 15 lists the bit descriptions for these channel addresses, device addresses, and input range.
表 15. Bit Description for the SDO Data
BIT
BIT DESCRIPTION
24-9
8-5
16 bits of conversion result for the channel represented in MSB-first format.
Four bits of channel address.
0000 = Channel 0
0001 = Channel 1
0010 = Channel 2
0011 = Channel 3
0100 = Channel 4
0101 = Channel 5
0110 = Channel 6
0111 = Channel 7
4-3
2-0
Two bits of device address (mainly useful in daisy-chain mode).
Three LSB bits of input voltage range (see the range select registers).
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7.5.2.3.3 Range Select Registers (addresses 05h-0Ch)
Address 05h corresponds to channel 0, address 06h corresponds to channel 1, address 07h corresponds to
channel 2, address 08h corresponds to channel 3, address 09h corresponds to channel 4, address 0Ah
corresponds to channel 5, address 0Bh corresponds to channel 6, and address 0Ch corresponds to channel 7.
These registers allow the selection of input ranges for all individual channels. The default value for these
registers is 00h.
图 108. Channel n Input Range Registers
7
0
6
0
5
0
4
0
3
2
1
0
Range_CHn[3:0]
R/W-0h
R-0h
R-0h
R-0h
R-0h
表 16. Channel n Input Range Registers Field Descriptions
Bit
Field
Type
R
Reset
0h
Description
7-4
3-0
0
Must always be set to 0
Range_CHn[3:0]
R/W
0h
Input range selection bits for channel n (n = 0 to 7).
0000 = Input range is set to ±2.5 × VREF
0001 = Input range is set to ±1.25 × VREF
0010 = Input range is set to ±0.625 × VREF
0011 = Input range is set to ±0.3125 × VREF
1011 = Input range is set to ±0.15625 × VREF
0101 = Input range is set to 0 to 2.5 × VREF
0110 = Input range is set to 0 to 1.25 × VREF
0111 = Input range is set to 0 to 0.625 × VREF
1111 = Input range is set to 0 to 0.3125 × VREF
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7.5.2.3.4 Alarm Flag Registers (Read-Only)
The alarm conditions related to individual channels are stored in these registers. The flags can be read when an
alarm interrupt is received on the ALARM pin. There are two types of flag for every alarm: active and tripped.
The active flag is set to 1 under the alarm condition (when data cross the alarm limit) and remains so as long as
the alarm condition persists. The tripped flag turns on the alarm condition similar to the active flag, but remains
set until read. This feature relieves the device from having to track alarms.
7.5.2.3.4.1 ALARM Overview Tripped-Flag Register (address = 10h)
The ALARM overview tripped-flags register contains the logical OR of high or low tripped alarm flags for all eight
channels.
图 109. ALARM Overview Tripped-Flag Register
7
6
5
4
3
2
1
0
Tripped Alarm
Flag Ch7
Tripped Alarm
Flag Ch6
Tripped Alarm
Flag Ch5
Tripped Alarm
Flag Ch4
Tripped Alarm
Flag Ch3
Tripped Alarm
Flag Ch2
Tripped Alarm
Flag Ch1
Tripped Alarm
Flag Ch0
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
表 17. ALARM Overview Tripped-Flag Register Field Descriptions
Bit
7
Field
Type
R
Reset
0h
Description
Tripped Alarm Flag Ch7
Tripped Alarm Flag Ch6
Tripped Alarm Flag Ch5
Tripped Alarm Flag Ch4
Tripped Alarm Flag Ch3
Tripped Alarm Flag Ch2
Tripped Alarm Flag Ch1
Tripped Alarm Flag Ch0
Tripped alarm flag for all analog channels at a glance.
Each individual bit indicates a tripped alarm flag status for each
channel, as per the alarm flags register for channels 7 to 0,
respectively.
0 = No alarm detected
1 = Alarm detected
6
R
0h
5
R
0h
4
R
0h
3
R
0h
2
R
0h
1
R
0h
0
R
0h
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7.5.2.3.4.2 Alarm Flag Registers: Tripped and Active (address = 11h to 14h)
There are two alarm thresholds (high and low) per channel, with two flags for each threshold. An active alarm
flag is enabled when an alarm is triggered (when data cross the alarm threshold) and remains enabled as long
as the alarm condition persists. A tripped alarm flag is enabled in the same manner as an active alarm flag, but
remains latched until read. Registers 11h to 14h in the program registers store the active and tripped alarm flags
for all individual eight channels.
图 110. ALARM Ch0-3 Tripped-Flag Register (address = 11h)
7
6
5
4
3
2
1
0
Tripped Alarm
Flag Ch0 Low
Tripped Alarm
Flag Ch0 High
Tripped Alarm
Flag Ch1 Low
Tripped Alarm
Flag Ch1 High
Tripped Alarm
Flag Ch2 Low
Tripped Alarm
Flag Ch2 High
Tripped Alarm
Flag Ch3 Low
Tripped Alarm
Flag Ch3 High
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
表 18. ALARM Ch0-3 Tripped-Flag Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
Tripped Alarm Flag Ch n
Low or High (n = 0 to 3)
R
0h
Tripped alarm flag high, low for channel n (n = 0 to 3)
Each individual bit indicates an active high or low alarm flag status for
each channel, as per the alarm flags register for channels 0 to 7.
0 = No alarm detected
1 = Alarm detected
图 111. ALARM Ch0-3 Active-Flag Register (address = 12h)
7
6
5
4
3
2
1
0
Active Alarm
Active Alarm
Active Alarm
Active Alarm
Active Alarm
Active Alarm
Active Alarm
Active Alarm
Flag Ch0 Low
Flag Ch0 High
Flag Ch1 Low
Flag Ch1 High
Flag Ch2 Low
Flag Ch2 High
Flag Ch3 Low
Flag Ch3 High
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
表 19. ALARM Ch0-3 Active-Flag Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
Active Alarm Flag Ch n Low
or High (n = 0 to 3)
R
0h
Active alarm flag high, low for channel n (n = 0 to 3)
Each individual bit indicates an active high or low alarm flag status for
each channel, as per the alarm flags register for channels 0 to 7.
0 = No alarm detected
1 = Alarm detected
图 112. ALARM Ch4-7 Tripped-Flag Register (address = 13h)(1)
7
6
5
4
3
2
1
0
Tripped Alarm
Flag Ch4 Low
Tripped Alarm
Flag Ch4 High
Tripped Alarm
Flag Ch5 Low
Tripped Alarm
Flag Ch5 High
Tripped Alarm
Flag Ch6 Low
Tripped Alarm
Flag Ch6 High
Tripped Alarm
Flag Ch7 Low
Tripped Alarm
Flag Ch7 High
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
(1) This register is not included in the 4-channel version of the device. A write operation on this register has no effect on device behavior. A
read operation on this register outputs all 1's on the SDO line.
表 20. ALARM Ch4-7 Tripped-Flag Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
Tripped Alarm Flag Ch n
Low or High (n = 4 to 7)
R
0h
Tripped alarm flag high, low for channel n (n = 4 to 7).
Each individual bit indicates an active high or low alarm flag status for
each channel, as per the alarm flags register for channels 0 to 7.
0 = No alarm detected
1 = Alarm detected
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图 113. ALARM Ch4-7 Active-Flag Register (address = 14h)(1)
7
6
5
4
3
2
1
0
Active Alarm
Active Alarm
Active Alarm
Active Alarm
Active Alarm
Active Alarm
Active Alarm
Active Alarm
Flag Ch4 Low
Flag Ch4 High
Flag Ch5 Low
Flag Ch5 High
Flag Ch6 Low
Flag Ch6 High
Flag Ch7 Low
Flag Ch7 High
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
(1) This register is not included in the 4-channel version of the device. A write operation on this register has no effect on device behavior. A
read operation on this register outputs all 1's on the SDO line.
表 21. ALARM Ch4-7 Active-Flag Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
Active Alarm Flag Ch n Low
or High (n = 4 to 7)
R
0h
Active alarm flag high, low for channel n (n = 4 to 7).
Each individual bit indicates an active high or low alarm flag status for
each channel, as per the alarm flags register for channels 0 to 7.
0 = No alarm detected
1 = Alarm detected
60
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7.5.2.3.5 Alarm Threshold Setting Registers
The ADS8688AT features individual high and low alarm threshold settings for each channel. Each alarm
threshold is 16 bits wide with 8-bit hysteresis, which is the same for both high and low threshold settings. This
40-bit setting is accomplished through five 8-bit registers associated with every high and low alarm.
REGISTER BITS
ADDR
NAME
7
6
5
4
3
2
1
0
Ch 0 Hysteresis
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
CH0_HYST[7:0]
Ch 0 High Threshold MSB
Ch 0 High Threshold LSB
Ch 0 Low Threshold MSB
Ch 0 Low Threshold LSB
Ch 1 Hysteresis
CH0_HT[15:8]
CH0_HT[7:0]
CH0_LT[15:8]
CH0_LT[7:0]
CH1_HYST[7:0]
CH1_HT[15:8]
CH1_HT[7:0]
CH1_LT[15:8]
CH1_LT[7:0]
Ch 1 High Threshold MSB
Ch 1 High Threshold LSB
Ch 1 Low Threshold MSB
Ch 1 Low Threshold LSB
Ch 2 Hysteresis
CH2_HYST[7:0]
CH2_HT[15:8]
CH2_HT[7:0]
CH2_LT[15:8]
CH2_LT[7:0]
Ch 2 High Threshold MSB
Ch 2 High Threshold LSB
Ch 2 Low Threshold MSB
Ch 2 Low Threshold LSB
Ch 3 Hysteresis
CH3_HYST[7:0]
CH3_HT[15:8]
CH3_HT[7:0]
CH3_LT[15:8]
CH3_LT[7:0]
Ch 3 High Threshold MSB
Ch 3 High Threshold LSB
Ch 3 Low Threshold MSB
Ch 3 Low Threshold LSB
Ch 4 Hysteresis
CH4_HYST[7:0]
CH4_HT[15:8]
CH4_HT[7:0]
CH4_LT[15:8]
CH4_LT[7:0]
Ch 4 High Threshold MSB
Ch 4 High Threshold LSB
Ch 4 Low Threshold MSB
Ch 4 Low Threshold LSB
Ch 5 Hysteresis
CH5_HYST[7:0]
CH5_HT[15:8]
CH5_HT[7:0]
CH5_LT[15:8]
CH5_LT[7:0]
Ch 5 High Threshold MSB
Ch 5 High Threshold LSB
Ch 5 Low Threshold MSB
Ch 5 Low Threshold LSB
Ch 6 Hysteresis
CH6_HYST[7:0]
CH6_HT[15:8]
CH6_HT[7:0]
CH6_LT[15:8]
CH6_LT[7:0]
Ch 6 High Threshold MSB
Ch 6 High Threshold LSB
Ch 6 Low Threshold MSB
Ch 6 Low Threshold LSB
Ch 7 Hysteresis
CH7_HYST[7:0]
CH7_HT[15:8]
CH7_HT[7:0]
CH7_LT[15:8]
CH7_LT[7:0]
Ch 7 High Threshold MSB
Ch 7 High Threshold LSB
Ch 7 Low Threshold MSB
Ch 7 Low Threshold LSB
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图 114. Ch n Hysteresis Registers
7
6
5
4
3
2
1
0
CHn_HYST[7:0]
R/W-0h
表 22. Channel n Hysteresis Register Field Descriptions
(n = 0 to 7)
Bit
Field
Type
Reset
Description
7-0
Channel n Hysteresis[7-0]
R/W
0h
These bits set the channel high and low alarm hysteresis for
channel n (n = 0 to 7)
For example, bits 7-0 of the channel 0 register (address 15h) set
the channel 0 alarm hysteresis.
00000000 = No hysteresis
00000001 = ±1-LSB hysteresis
00000010 to 11111110 = ±2-LSB to ±254-LSB hysteresis
11111111 = ±255-LSB hysteresis
图 115. Ch n High Threshold MSB Registers
7
6
5
4
3
2
1
0
CHn_HT[15:8]
R/W-1h
表 23. Channel n High Threshold MSB Register Field Descriptions
(n = 0 to 7)
Bit
Field
Type
Reset
Description
7-0
CHn_HT[15:8]
R/W
1h
These bits set the MSB byte for the 16-bit channel n high alarm.
For example, bits 7-0 of the channel 0 register (address 16h) set
the MSB byte for the channel 0 high alarm threshold. The
channel 0 high alarm threshold is AAFFh when bits 7-0 of the
channel 0 high threshold MSB register (address 16h) are set to
AAh and bits 7-0 of the channel 0 high threshold LSB register
(address 17h) are set to FFh.
0000 0000 = MSB byte is 00h
0000 0001 = MSB byte is 01h
0000 0010 to 1110 1111 = MSB byte is 02h to FEh
1111 1111 = MSB byte is FFh
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图 116. Ch n High Threshold LSB Registers
7
6
5
4
3
2
1
0
CHn_HT[7:0]
R/W-1h
表 24. Channel n High Threshold LSB Register Field Descriptions
(n = 0 to 7)
Bit
Field
CHn_HT[7-0]
Type
Reset
Description
7-0
R/W
1h
These bits set the LSB for the 16-bit channel n high alarm.
For example, bits 7-0 of the channel 0 register (address 17h) set
the LSB for the channel 0 high alarm threshold. The channel 0
high alarm threshold is AAFFh when bits 7-0 of the channel 0
high threshold MSB register (address 16h) are set to AAh and
bits 7-0 of the channel 0 high threshold LSB register (address
17h) are set to FFh.
0000 0000 = LSB byte is 00h
0000 0001 = LSB byte is 01h
0000 0010 to 1111 1110 = LSB byte is 02h to FEh
1111 1111 = LSB byte is FFh
图 117. Ch n Low Threshold MSB Registers
7
6
5
4
3
2
1
0
CHn_LT[15:8]
R/W-0h
表 25. Channel n Low Threshold MSB Register Field Descriptions
(n = 0 to 7)
Bit
Field
CHn_LT[15:8]
Type
Reset
Description
7-0
R/W
0h
These bits set the MSB byte for the 16-bit channel n low alarm.
For example, bits 7-0 of the channel 0 register (address 18h) set
the MSB byte for the channel 0 low alarm threshold. The
channel 0 low alarm threshold is AAFFh when bits 7-0 of the
channel 0 low threshold MSB register (address 18h) are set to
AAh and bits 7-0 of the channel 0 low threshold LSB register
(address 19h) are set to FFh.
0000 0000 = MSB byte is 00h
0000 0001 = MSB byte is 01h
0000 0010 to 1110 1111 = MSB byte is 02h to FEh
1111 1111 = MSB byte is FFh
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图 118. Ch n Low Threshold LSB Registers
7
6
5
4
3
2
1
0
CHn_LT[7:0]
R/W-0h
表 26. Channel n Low Threshold MSB Register Field Descriptions
(n = 0 to 7)
Bit
Field
CHn_LT[7-0]
Type
Reset
Description
7-0
R/W
00h
These bits set the LSB for the 16-bit channel n low alarm.
For example, bits 7-0 of the channel 0 register (address 19h) set
the LSB for the channel 0 low alarm threshold. The channel 0
low alarm threshold is AAFFh when bits 7-0 of the channel 0 low
threshold MSB register (address 18h) are set to AAh and bits 7-
0 of the channel 0 low threshold LSB register (address 19h) are
set to FFh.
0000 0000 = LSB byte is 00h
0000 0001 = LSB byte is 01h
0000 0010 to 1110 1111 = LSB byte is 02h to FEh
1111 1111 = LSB byte is FFh
7.5.2.3.6 Command Read-Back Register (address = 3Fh)
This register allows the device mode of operation to be read. On execution of this command, the device outputs
the command word executed in the previous data frame. The output of the command register appears on SDO
from the 16th falling edge onwards in an MSB-first format. All information regarding the command register is
contained in the first eight bits and the last eight bits are 0 (see 表 7), thus the command read-back operation
can be stopped after the 24th SCLK cycle.
图 119. Command Read-Back Register
7
6
5
4
3
2
1
0
COMMAND_WORD[15:8]
R-0h
表 27. Command Read-Back Register Field Descriptions
Bit
Field
COMMAND_WORD[15:8]
Type
Reset
Description
7-0
R
0h
Command executed in previous data frame.
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The ADS8688AT is a fully integrated data acquisition system based on a 16-bit SAR ADC. The device includes
an integrated analog front-end for each input channel and an integrated precision reference with a buffer. As
such, this device does not require any additional external circuits for driving the reference or analog input pins of
the ADC.
8.2 Typical Applications
8.2.1 Phase-Compensated, 8-Channel, Multiplexed Data Acquisition System for Power Automation
Ch1 Input, V1
Reference
Input, VR
Ch n Input, Vn
(n = 1 to 7)
∆ꢀ = Measured Phase Difference
Between Channels
Angle (ꢀ)
∆ꢀr1
∆ꢀrn
(n = 1 to 7)
AVDD = 5 V
ADS8688AT
R0P
AIN_0P
1 MW
PGA
LPF
C0
1 MW
AIN_0GND
R0M
Simple Capture Card
16-Bit
ADC
R7P
AIN_7P
1 MW
1 MW
FPGA
SITARA
PGA
LPF
C7
AIN_7GND
DDR
R7M
4.096 V
AGND
Typical 50-Hz
Sine-Wave from CT/PT
Balanced RC Filter
on Each Input
图 120. 8-Channel, Multiplexed Data Acquisition System for Power Automation
8.2.1.1 Design Requirements
In modern power grids, accurately measuring the electrical parameters of the various areas of the power grid is
extremely critical. This measurement helps determine the operating status and running quality of the grid. Such
accurate measurements also help diagnose potential problems with the power network so that these problems
can be resolved quickly without having any significant service disruption. The key electrical parameters include
amplitude, frequency, and phase, which are important for calculating the power factor, power quality, and other
parameters of the power system.
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Typical Applications (接下页)
The phase angle of the electrical signal on the power network buses is a special interest to power system
engineers. The primary objective for this design is to accurately measure the phase and phase difference
between the analog input signals in a multichannel data acquisition system. When multiple input channels are
sampled in a sequential manner as in a multiplexed ADC, an additional phase delay is introduced between the
channels. Thus, the phase measurements are not accurate. However, this additional phase delay is constant and
can be compensated in application software.
The key design requirements are given below:
•
•
•
Single-ended sinusoidal input signal with a ±10-V amplitude and typical frequency (fIN = 50 Hz).
Design an 8-channel multiplexed data acquisition system using a 16-bit SAR ADC.
Design a software algorithm to compensate for the additional phase difference between the channels.
8.2.1.2 Detailed Design Procedure
The application circuit and system diagram for this design is illustrated in 图 120. This design includes a
complete hardware and software implementation of a multichannel data acquisition system for power automation
applications.
This system can be designed using the ADS8688AT, which is a 16-bit, 500-kSPS, 8-channel, multiplexed input,
SAR ADC with integrated precision reference and analog front-end circuitry for each channel. The ADC supports
bipolar input ranges up to ±10.24 V with a single 5-V supply and provides minimum latency in data output
resulting from the SAR architecture. The integration offered by this device makes the ADS8688AT an ideal
selection for such applications, because the integrated signal conditioning helps minimize system components
and avoids the need for generating high-voltage supply rails. The overall system-level dc precision (gain and
offset errors) and low temperature drift offered by this device helps system designers achieve the desired system
accuracy without calibration. In most applications, using passive RC filters or multi-stage filters in front of the
ADC is preferred to reduce the noise of the input signal.
The software algorithm implemented in this design uses the discrete fourier transform (DFT) method to calculate
and track the input signal frequency, obtain the exact phase angle of the individual signal, calculate the phase
difference, and implement phase compensation. The entire algorithm has four steps:
•
•
•
•
Calculate the theoretical phase difference introduced by the ADC resulting from multiplexing input channels
Estimate the frequency of the input signal using frequency tracking and DFT techniques
Calculate the phase angle of all signals in the system based on the estimated frequency
Compensate the phase difference for all channels using the theoretical value of an additional MUX phase
delay calculated in the first step
8.2.1.3 Application Curve
表 28 and 图 121 summarize the performance for this design. In this example, multiple sinusoidal input signals of
an amplitude at ±10 V are applied to the inputs of the ADC. The initial phase angle is the same for all signals, but
the input frequency is varied from 45 Hz to 55 Hz. The phase error in the last column of 表 28 reflects the
measurement accuracy of this design.
表 28. Theoretical and Measured Phase Difference
THEORETICAL PHASE
ERROR(1)
MEASURED PHASE
ERROR(2)
PHASE ERROR AFTER
COMPENSATION(3)
INPUT TEST CONDITION
Phase difference
(consecutive channels)
0.036°
0.252°
0.036145°
0.249964°
0.000145°
0.002036°
Phase difference
(farthest channels, channel 0 to channel 7)
(1) Theoretical phase difference introduced by multiplexing is calculated based on the formula: Δφ = (fIN / fADC) × N × 360°, where N =
integral gap between two channels in the multiplexer sequence; fIN = input signal frequency; and fADC = 500 kSPS, maximum throughput
of the ADC.
(2) Measured phase value (before compensation) includes phase difference between any two channels resulting from multiplexing ADC
inputs.
(3) The algorithm subtracts theoretical phase difference from the measured phase to compensate for the phase difference resulting from the
MUX inputs.
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0.04
0.038
0.036
0.034
0.032
0.03
Measured Phase Difference
Theoretical Phase Difference
53 54
45
46
47
48
49
50
51
52
55
Input Signal Frequency (Hz)
C066
图 121. Measured and Theoretical Phase Difference Between Consecutive Channels
For a step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, see Phase Compensated 8-Channel, Multiplexed Data Acquisition System for Power Automation
Reference Design.
8.2.2 16-Bit, 8-Channel, Integrated Analog Input Module for Programmable Logic Controllers (PLCs)
24 VDC_LIMIT
24 VDC
Hot Swap
Protection
LM5069
Isolated
Power Supply
6-V VISO
5-V VISO, 25 mA
LDO
LM5017
TPS71501
9.3 VDC
5-V VISO
3.3 VDC,
15 mA
5-V VISO
LDO
TPS71533
50-Pin Interface
Connector
Filter
4 SE Voltage Inputs:
±10 VDC
0 VDC to 10 VDC
0 VDC to 5 VDC
1 VDC to 5 VDC
(To Base Board)
AVDD
DVDD
ADS8688AT
Protection
Protection
SPI
16-Bit, 8-Ch, 500-kSPS
SAR ADC
4 Current Inputs:
0 mA to 20 mA
4 mA to 20 mA
3.3 VDC
Filter
Digital Isolator
ISO7141CC
I2C
EEPROM
图 122. 16-Bit, 8-Channel, Integrated Analog Input Module for PLCs
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8.2.2.1 Design Requirements
This reference design provides a complete solution for a single-supply industrial control analog input module.
The design is suitable for process control end equipment, such as programmable logic controllers (PLCs),
distributed control systems (DCSs), and data acquisition systems (DAS) modules that must digitize standard
industrial current inputs, and bipolar or unipolar input voltage ranges up to ±10 V. In an industrial environment,
the analog voltage and current ranges typically include ±2.5 V, ±5 V, ±10 V, 0 V to 5 V, 0 V to 10 V, 4 mA to
20 mA, and 0 mA to 20 mA. This reference design can measure all standard industrial voltage and current
inputs. Eight channels are provided on the module, and each channel can be configured as a current or voltage
input with software configuration.
The key design requirements are given below:
•
Up to eight channels of user-programmable inputs:
–
–
Voltage inputs (with a typical ZIN of 1 MΩ): ±10 V, ±5 V, ±2.5 V, 0 V to 10 V, and 0 V to 5 V
Current inputs (with a ZIN of 300 Ω): 0 mA to 20 mA, 4 mA to 20 mA, and ±20 mA
•
•
•
•
•
•
A 16-bit SAR ADC with SPI
Accuracy of ≤ 0.2% at 25°C over the entire input range of voltage and current inputs
Onboard isolated fly-buck™ power supply with inrush current protection
Slim-form factor 96 mm × 50.8 mm × 10 mm (L × W × H)
LabView-based GUI for signal-chain analysis and functional testing
Designed to comply with IEC61000-4 standards for ESD, EFT, and surge
8.2.2.2 Detailed Design Procedure
The application circuit and system diagram for this design is illustrated in 图 122.
The module has eight analog input channels, and each channel can be configured as a current or voltage input
with software configuration. This design can be implemented using the ADS8688AT, 16-bit, 8-channel, single-
supply SAR ADC with an on-chip PGA and reference. The on-chip PGA provides a high-input impedance
(typically 1 MΩ) and filters noise interference. The on-chip, 4.096-V, ultra-low drift voltage reference is used as
the reference for the ADC core.
Digital isolation is achieved using an ISO7141CC and ISO1541. The host microcontroller communicates with a
TCA6408A (an 8-bit, I2C, I/O expander over an I2C bus). The ISO1541D is a bidirectional, I2C isolator that
isolates the I2C lines for the TCA6408A. The TCA6408A controls the low RON opto-switch that is used to switch
between voltage-to-current input modes. The input channel configuration is done in microcontroller firmware.
A low-cost, constant, on-time, synchronous buck regulator in fly-buck configuration with an external transformer
(LM5017) generates the isolated power supply. The LM5017 has a wide input supply range, making this device
ideal for accepting a 24-V industrial supply. This transformer can accept up to 100 V, thereby making reliable
transient protection of the input supply more easily achievable. The fly-buck power supply isolates and steps the
input voltage down to 6 V. The supply then provides that voltage to the TPS70950 (the low dropout regulator) to
generate 5 V to power the ADS8688AT and other circuitry. The LM5017 also features a number of other safety
and reliability functions, such as undervoltage lockout (UVLO), thermal shutdown, and peak current limit
protection.
Input analog signals are protected against high-voltage, fast-transient events often expected in an industrial
environment. The protection circuitry makes use of the transient voltage suppressor (TVS) and ESD diodes. The
RC low-pass mode filters are used on each analog input before the input reaches the ADS8688AT, thus
eliminating any high-frequency noise pickups and minimizing aliasing.
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8.2.2.3 Application Curve
表 29 summarizes the performance for this design.
表 29. Measurement Results Summary for PLC Analog Input Module Design
ADS8688AT
SPECIFICATION
SERIAL NUMBER
PARAMETER
INPUT RANGE
MEASURED RESULT
±10 V
0 V 10 V
0 V to 5 V
±10 V
90 dB (min)
90.85 dB
89.52 dB
88.48 dB
14.80
14.58
14.41
1.77
1
SNR (dB)
88.5 dB (min)
87.5 dB (min)
14.66
14.41
14.24
2
2
3
4
ENOB (Bits)
0 V 10 V
0 V to 5 V
±10 V
Maximum INL (LSB)
Minimum INL (LSB)
0 V 10 V
0 V to 5 V
±10 V
2
1.64
2
1.35
–2
–1.47
–1.36
–1.37
0 V 10 V
0 V to 5 V
–2
–2
图 123 shows the accuracy performance for this design for the ±10.24-V input range.
0.08
Pre Calibration Error
Post Calibration Error
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
0
10000
20000
30000
40000
50000
60000
Digital Output Code
C067
图 123. System Accuracy Performance in ±2.5 × VREF Input Range
For a step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, see 16-Bit, 8-Channel, Integrated Analog Input Module for Programmable Logic Controllers (PLCs).
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9 Power Supply Recommendations
The device uses two separate power supplies: AVDD and DVDD. The internal circuits of the device operate on
AVDD; DVDD is used for the digital interface. AVDD and DVDD can be independently set to any value within the
permissible range.
The AVDD supply pins must be decoupled with AGND by using a minimum 10-µF and 1-µF capacitor on each
supply. Place the 1-µF capacitor as close to the supply pins as possible. Place a minimum 10-µF decoupling
capacitor very close to the DVDD supply to provide the high-frequency digital switching current. The effect of
using the decoupling capacitor is illustrated in the difference between the power-supply rejection ratio (PSRR)
performance of the device. 图 124 shows the PSRR of the device without using a decoupling capacitor. 图 125
shows that the PSRR improves when the decoupling capacitors are used.
150
130
110
90
140
120
100
80
---- ± 2.5*VREF, ---- ± 1.25*VREF, ---- ± 0.625*VREF,
------±0.3125*VREF, -------±0.156 VREF, ---- + 2.5*VREF
---- + 1.25*VREF, ---- + 0.625*VREF, ---- + 0.3125*VREF
---- ± 2.5*VREF, ---- ± 1.25*VREF, ---- ± 0.625*VREF,
------±0.3125*VREF, -------±0.156 VREF, ---- + 2.5*VREF
---- + 1.25*VREF, ---- + 0.625*VREF, ---- + 0.3125*VREF
70
60
50
30
40
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
Input Frequency (MHz)
Input Frequency (MHz)
C063
C062
Code output near 32,769
Code output near 32,768
图 124. PSRR Without a Decoupling Capacitor
图 125. PSRR With a Decoupling Capacitor
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10 Layout
10.1 Layout Guidelines
图 126 illustrates a PCB layout example for the ADS8688AT.
•
Partition the PCB into analog and digital sections. Care must be taken to ensure that the analog signals are
kept away from the digital lines. This layout helps keep the analog input and reference input signals away
from the digital noise. In this layout example, the analog input and reference signals are routed on the lower
side of the board and the digital connections are routed on the top side of the board.
•
•
Using a single dedicated ground plane is strongly encouraged.
Power sources to the ADS8688AT must be clean and well-bypassed. TI recommends using a
1-μF, X7R-grade, 0603-size ceramic capacitor with at least a 10-V rating in close proximity to the analog
(AVDD) supply pins. For decoupling the digital (DVDD) supply pin, a 10-μF, X7R-grade, 0805-size ceramic
capacitor with at least a 10-V rating is recommended. Placing vias between the AVDD, DVDD pins and the
bypass capacitors must be avoided. All ground pins must be connected to the ground plane using short, low
impedance paths.
•
There are two decoupling capacitors used for the REFCAP pin. The first is a small, 1-μF, X7R-grade, 0603-
size ceramic capacitor placed close to the device pins for decoupling the high-frequency signals and the
second is a 22-µF, X7R-grade, 1210-size ceramic capacitor to provide the charge required by the reference
circuit of the device. Both of these capacitors must be directly connected to the device pins without any vias
between the pins and capacitors.
•
•
The REFIO pin also must be decoupled with a 10-µF ceramic capacitor, if the internal reference of the device
is used. The capacitor must be placed close to the device pins.
For the auxiliary channel, the fly-wheel RC filter components must be placed close to the device. Among
ceramic surface-mount capacitors, COG (NPO) ceramic capacitors provide the best capacitance precision.
The type of dielectric used in COG (NPO) ceramic capacitors provides the most stable electrical properties
over voltage, frequency, and temperature changes.
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10.2 Layout Example
Digital Pins
1: SDI
38: CS
37: SCLK
2: RST/PD
3: DAISY
4: REFSEL
36: SDO
35: ALARM
34: DVDD
REFSEL
5: REFIO
10µF
10µF (When using internal VREF
)
6: REFGND
1µF
33: DGND
GND
22µF
7: REFCAP
32: AGND
8: AGND
1µF
31: AGND
9: AVDD
30: AVDD
1µF
10: AUX_IN
11: AUX_GND
12: AIN_6P
29: AGND
28: AGND
27: AIN_5P
26: AIN_5GND
25: AIN_4P
24: AIN_4GND
23: AIN_3P
22: AIN_3GND
21: AIN_2P
20: AIN_2GND
13: AIN_6GND
14: AIN_7P
Optional RC Filter for
Channel AIN_0 to AIN_7
15: AIN_7GND
16: AIN_0P
17: AIN_0GND
18: AIN_1P
19: AIN_1GND
Analog Pins
图 126. Board Layout for the ADS8688AT
72
版权 © 2018, Texas Instruments Incorporated
ADS8688AT
www.ti.com.cn
ZHCSID7 –JUNE 2018
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档:
•
•
•
•
•
•
•
•
•
•
ISO154x 低功耗双向 I2C 隔离器
ISO71xxCC 4242VPK 小封装低功耗三通道和四通道数字隔离器
LM5017 100V、600mA 恒定开通时间同步降压稳压器
具有关断功能的 20MHz、0.9pA、RRIO、CMOS OPA320 高精度、低噪声运算放大器
《REF50xx 低噪声、极低漂移、高精度电压基准》
具有中断输出、复位和配置寄存器的 TCA6408A 低电压 8 位 I2C 和 SMBus 低功耗 I/O 扩展器
具有使能功能的 150mA、30V、1μA IQ TPS709 稳压器
AN-2029 操作和处理相关建议应用报告
适用于可编程逻辑控制器 (PLC) 的 16 位 8 通道、软件可配置模拟输入模块
用于电力自动化的相位补偿 8 通道多路复用数据采集系统参考设计
11.2 接收文档更新通知
要接收文档更新通知,请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册,即可每周接收产
品信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范,
并且不一定反映 TI 的观点;请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中,您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
fly-buck, E2E are trademarks of Texas Instruments.
SPI is a trademark of Motorola.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本,请参阅左侧的导航栏。
版权 © 2018, Texas Instruments Incorporated
73
PACKAGE OPTION ADDENDUM
www.ti.com
26-May-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS8688ATDBT
ACTIVE
TSSOP
DBT
38
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
ADS8688AT
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
DBT0038A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SEATING
PLANE
6.55
6.25
TYP
C
A
0.1 C
PIN 1 INDEX AREA
38 X 0.5
38
1
2X
9
9.75
9.65
NOTE 3
19
B
20
0.23
38 X
0.17
4.45
1.2 MAX
0.1
C A B
4.35
NOTE 4
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
4220221/A 05/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
DBT0038A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
38 X (1.5)
SYMM
(R0.05) TYP
38
1
38 X (0.3)
38 X (0.5)
SYMM
19
20
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220221/A 05/2020
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBT0038A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
38 X (1.5)
SYMM
(R0.05) TYP
38
1
38 X (0.3)
38 X (0.5)
SYMM
19
20
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220221/A 05/2020
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI“按原样”提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的 TI 产品,(2) 设计、验
证并测试您的应用,(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
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