ADS8924BRGET [TI]
具有内部 VREF 缓冲器、内部 LDO 和增强型 SPI 的 16 位 250kSPS 单通道 SAR ADC | RGE | 24 | -40 to 125;
| 型号： | ADS8924BRGET |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有内部 VREF 缓冲器、内部 LDO 和增强型 SPI 的 16 位 250kSPS 单通道 SAR ADC | RGE | 24 | -40 to 125 转换器 |
| 文件： | 总78页 (文件大小：3280K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADS8920B
ADS8922B
ADS8924B
ZHCSFE1B –JUNE 2016–REVISED AUGUST 2017
具有集成式基准缓冲器和增强性能的 ADS892xB 16 位，高速 SAR ADC
特性
1 特性
3 说明
1
•
•
分辨率：16 位
无延迟输出的高采样率：
ADS8920B、ADS8922B 和 ADS8924B (ADS892xB)
属于引脚对引脚兼容的高速、单通道、高精度、基于
16 位逐次逼近型寄存器 (SAR) 的模数转换器 (ADC)
系列，且带有集成式基准缓冲器和集成式低压差稳压器
(LDO)。该器件系列包括 ADS890xB（20 位）和
ADS891xB（18 位）这两种分辨率型号。
–
–
–
ADS8920B：1MSPS
ADS8922B：500kSPS
ADS8924B：250kSPS
•
•
•
集成 LDO 支持单电源操作
无压降的低功耗基准缓冲器
出色的交流和直流性能：
借助 TI 的增强型 SPI 特性，ADS892xB 可提高模拟性
能，同时保持高分辨率数据传输。增强型 SPI 支持
ADS89xxB 以较低时钟速度实现高吞吐量，从而简化
板布局并降低系统成本。增强型 SPI 也简化了数据计
时，从而使器件成为 FPGA、DSP 等应用的 理想选
择。ADS89xxB 兼容标准 SPI 接口。
–
–
–
SNR：96.8dB，THD：–125dB
INL：±0.25LSB
DNL：±0.2LSB、16 位、无丢失码
•
宽输入范围：
–
–
单极差分输入范围：±VREF
VREF 输入范围：2.5V 至 5V
ADS892xB 具有内部数据奇偶校验功能，可以将其附
加到 ADC 数据输出。主机使用奇偶校验位进行的
ADC 数据验证提高了系统可靠性。
•
•
单电源低功耗运行
增强型 SPI 数字接口
–
–
接口 SCLK：1MSPS 时为 18MHz。
1MSPS 时的 SPI 接口时钟
器件分辨率
20 位
3 线 SPI
3 线增强型 SPI
可配置数据奇偶校验输出
70MHz
22MHz
•
•
扩展温度范围：-40°C 至 +125°C
18 位
16 位
58MHz
52MHz
20MHz
18MHz
小型封装：4mm × 4mm 超薄四方扁平无引线
(VQFN) 封装
(1) 有关 增强型 SPI 的 全部特性，请参阅 部分。
2 应用
•
•
•
测试和测量
医疗成像
高精度、高速数据采集
使用 ADS89xxB 集成功能轻松实现 系统设计
Multi-ADC System with Single Supply
and Reference
Lowest Clock Speeds at 1-MSPS using 3-Wire Enhanced-
SPI
ADS89xxB
VREF
MCU
AINP
AINM
CONV
IN
Data
CS
CS
IN
REFIN
REFBUFOUT
BUF
SDO
SDI
Parity
DD
DD
DVDD
18-MHz
SCK
SCLK
ISO
Quiet time
AINP
ADC
Data
Data
Read
AVDD
ADC Conversion
ADC Conversion
AINM
Parity
D
D
AVDD
SPI
Enhanced SPI (Data + Parity)
18-MHz
52-MHz
ADS89xxB
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBAS729
ADS8920B
ADS8922B
ADS8924B
ZHCSFE1B –JUNE 2016–REVISED AUGUST 2017
www.ti.com.cn
目录
7.5 Programming........................................................... 28
7.6 Register Maps......................................................... 52
Application and Implementation ........................ 58
8.1 Application Information............................................ 58
8.2 Typical Application .................................................. 60
Power-Supply Recommendations...................... 65
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 6
6.1 Absolute Maximum Ratings ..................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 7
6.6 Timing Requirements................................................ 9
6.7 Switching Characteristics........................................ 10
6.8 Typical Characteristics............................................ 14
Detailed Description ............................................ 19
7.1 Overview ................................................................. 19
7.2 Functional Block Diagram ....................................... 19
7.3 Feature Description................................................. 20
7.4 Device Functional Modes........................................ 26
8
9
10 Layout................................................................... 66
10.1 Layout Guidelines ................................................. 66
10.2 Layout Example .................................................... 67
11 器件和文档支持 ..................................................... 68
11.1 Documentation Support ........................................ 68
11.2 相关链接................................................................ 68
11.3 Receiving Notification of Documentation Updates 68
11.4 社区资源................................................................ 68
11.5 商标....................................................................... 69
11.6 静电放电警告......................................................... 69
11.7 Glossary................................................................ 69
12 机械、封装和可订购信息....................................... 69
7
4 Revision History
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (July 2016) to Revision B
Page
•
•
•
已更改 将器件信息表更改为 1MSPS 时的 SPI 接口时钟表 .................................................................................................... 1
已更改 首页图 ......................................................................................................................................................................... 1
Changed REFBUFOUT pin description from "Reference buffer output, ADC reference input" to "Internal reference
buffer output, external reference input" .................................................................................................................................. 4
•
•
Changed DVDD range in condition line of Electrical Characteristics from 2.35 V to 3.6 V to 1.65 V to 5.5 V........................ 7
Changed maximum value for DVDD range in Electrical Characteristics, Timing Requirements, and Switching
Characteristics from 3.6 V to 5.5 V......................................................................................................................................... 7
•
•
•
•
•
•
•
•
•
•
•
•
•
Added TA = 25°C to reference buffer offset voltage test condition in Electrical Characteristics table ................................... 7
Changed input offset thermal drift typ value from 10 to 1 ...................................................................................................... 7
Added fIN = 2 kHz test condition to SFDR in Electrical Characteristics table ........................................................................ 8
Added new conditions to serial clock frequency in the Timing Requirements table .............................................................. 9
Changed serial clock time period in Timing Characteristics table ......................................................................................... 9
Added serial clock frequency conditions in Timing Characteristics table .............................................................................. 9
Changed serial clock time period in Timing Characteristics table ......................................................................................... 9
Added strobe output time to Switching Characteristics table ............................................................................................... 10
Added descriptive text and one figure to the Reference Buffer Module section .................................................................. 20
Deleted text from first note element regarding data transfer activity in zone 2.................................................................... 35
Added new option bullet for multiSPI digital interface module in Data Transfer Protocols section ..................................... 35
Added new note (1) for SCLK in Table 9 ............................................................................................................................ 45
Deleted "For the ADS892xB, limit the value of RFLT to a maximum of 2.5-Ω in order to avoid any significant
degradation in linearity performance. " from the last paragraph of the Charge Kickback Filter section .............................. 59
•
•
•
•
Changed Data Acquisition (DAQ) Circuit for Lowest Distortion and Noise Performance... section for clarity ..................... 60
Added more design parameters to Design Parameters table .............................................................................................. 60
Changed Detailed Design Procedure section for clarity....................................................................................................... 61
Added two new application curves ....................................................................................................................................... 61
2
版权 © 2016–2017, Texas Instruments Incorporated
ADS8920B
ADS8922B
ADS8924B
www.ti.com.cn
ZHCSFE1B –JUNE 2016–REVISED AUGUST 2017
Revision History (接下页)
•
•
Added new typical application subsection ........................................................................................................................... 62
Added text to Power-Supply Recommendations section for clarity ..................................................................................... 65
Changes from Original (June 2016) to Revision A
Page
•
•
已更改 将“产品预览”更改为“生产数据” ................................................................................................................................... 1
Changed DVDD specified throughput value in the Recommended Operating Conditions from 3.6 V to 5.5 V....................... 6
版权 © 2016–2017, Texas Instruments Incorporated
3
ADS8920B
ADS8922B
ADS8924B
ZHCSFE1B –JUNE 2016–REVISED AUGUST 2017
www.ti.com.cn
5 Pin Configuration and Functions
RGE Package
24-Pin VQFN
Top View
CONVST
RST
1
2
3
4
5
6
18
17
16
15
14
13
SDO-2
SDO-3
DVDD
GND
REFIN
Thermal
Pad
REFM
REFBUFOUT
NC
DECAP
DECAP
Not to scale
Pin Functions
PIN
NAME
AINM
NO.
10
9
FUNCTION
Analog input
Analog input
DESCRIPTION
Negative analog input
AINP
Positive analog input
Chip-select input pin; active low
CS
24
Digital input
The device takes control of the data bus when CS is low.
The SDO-x pins go to Hi-Z when CS is high.
Conversion start input pin.
A CONVST rising edge brings the device from ACQ state to CNV state.
CONVST
1
Digital input
DECAP
DVDD
GND
13, 14
16
Power supply
Power supply
Power supply
No connection
Place decoupling capacitor here for internal power supply. Short pin 13 and 14 together.
Interface power supply pin
Ground
11, 15
6
NC
Float these pins; no external connection.
REFBUFOUT
REFIN
5, 7
3
Analog input/output Internal reference buffer output, external reference input. Short pin 5 and 7 together.
Analog input
Analog input
Reference voltage input
REFM
4, 8
Reference ground potential
Asynchronous reset input pin.
A low pulse on the RST pin resets the device. All register bits return to the default state.
RST
2
Digital input
RVDD
12
Power supply
Analog power supply pin.
Multifunction output pin.
RVS
21
Digital output
With CS held high, RVS reflects the status of the internal ADCST signal.
With CS low, the status of RVS depends on the output protocol selection.
Clock input pin for the serial interface.
All system-synchronous data transfer protocols are timed with respect to the SCLK signal.
SCLK
SDI
23
22
Digital input
Digital input
Serial data input pin.
This pin is used to feed data or commands into the device.
4
Copyright © 2016–2017, Texas Instruments Incorporated
ADS8920B
ADS8922B
ADS8924B
www.ti.com.cn
ZHCSFE1B –JUNE 2016–REVISED AUGUST 2017
Pin Functions (continued)
PIN
NAME
SDO-0
NO.
20
FUNCTION
Digital output
Digital output
Digital output
Digital output
Supply
DESCRIPTION
Serial communication pin: data output 0
Serial communication pin: data output 1
Serial communication pin: data output 2
Serial communication pin: data output 3
Exposed thermal pad; connect to GND.
SDO-1
19
SDO-2
18
SDO-3
17
Thermal pad
Copyright © 2016–2017, Texas Instruments Incorporated
5
ADS8920B
ADS8922B
ADS8924B
ZHCSFE1B –JUNE 2016–REVISED AUGUST 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.1
–0.3
–0.3
–0.3
–130
–40
MAX
7
UNIT
V
RVDD to GND
DVDD to GND
7
V
REFIN to REFM
RVDD + 0.3
0.1
V
REFM to GND
V
Analog Input (AINP, AINM) to GND
Digital input (RST, CONVST, CS, SCLK, SDI) to GND
Digital output (RVS, SDO-0, SDO-1, SDO-2, SDO-3) to GND
Analog Input (AINP, AINM) to RVDD and GND
Operating free-air temperature, TA
Storage temperature, Tstg
VREF + 0.3
DVDD + 0.3
DVDD + 0.3
130
V
V
V
mA
°C
°C
125
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
NOM
MAX
5.5
UNIT
RVDD
DVDD
Analog supply voltage (RVDD to AGND)
Digital supply voltage (DVDD to AGND)
5
3
3
V
Operating
1.65
2.35
2.5
10
5.5
V
Specified throughput
5.5
VREF
CREFBUF
RESR
TA
Reference input voltage on REFIN
External ceramic decoupling capacitor
External series resistor
RVDD – 0.3
V
µF
Ω
0
1.3
Specified free-air operating temperature
–40
25
125
°C
6.4 Thermal Information
ADS892xB
THERMAL METRIC(1)
RGE (VQFN)
24 PINS
31.9
UNITS
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
29.9
8.9
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJB
8.9
RθJC(bot)
2.0
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6
Copyright © 2016–2017, Texas Instruments Incorporated
ADS8920B
ADS8922B
ADS8924B
www.ti.com.cn
ZHCSFE1B –JUNE 2016–REVISED AUGUST 2017
6.5 Electrical Characteristics
At RVDD = 5.5 V, DVDD = 1.65 V to 5.5 V, VREF = 5 V, and maximum throughput (unless otherwise noted).
Minimum and maximum values at TA = –40°C to +125°C; typical values at TA = 25°C.
PARAMETER
ANALOG INPUT
TEST CONDITIONS
MIN
TYP
MAX UNIT
Full-scale input range
(AINP – AINM)
FSR
VIN
–VREF
0
VREF
VREF
V
V
V
Absolute input voltage
(AINP and AINM to REFM)
Common-mode voltage
(AINP + AINM) / 2
(VREF / 2) –
0.1
(VREF / 2) +
0.1
VCM
VREF / 2
Sample mode
60
4
pF
pF
CIN
Input capacitance
Hold mode
VOLTAGE REFERENCE INPUT (REFIN)
IREF
Reference input current
Internal capacitance
VREF = 5 V
0.1
10
1
µA
pF
CREF
REFERENCE BUFFER OUTPUT (REFBUFOUT)
Reference buffer offset voltage
V(RO)
With EN_MARG = 0b(1), TA = 25°C(2)
–250
250
1.3
µV
µF
(VREFBUFOUT – VREF
)
External ceramic decoupling
capacitor
CREFBUF
10
0
RESR
ISHRT
External series resistor
Short-circuit current
Margining range
Ω
30
±4.5
280
mA
mV
µV
With EN_MARG = 1b(1)
With EN_MARG = 1b(1)
Margining resolution
DC ACCURACY(3) (CREFBUF = 10 µF, RESR = 0 Ω)
Resolution
16
Bits
Bits
0.5 LSB(5)
0.5 LSB(5)
NMC
INL
No missing codes
16
-0.5
-0.5
-3
Integral nonlinearity(4)
Differential nonlinearity(4)
±0.3
±0.2
±0.5
±3
DNL
TA = 25°C(2)
TA = –40°C to +125°C(2)
3
E(IO)
Input offset error(4)
LSB(5)
5
-5
dVOS/dT
GE
Input offset thermal drift(2)
Gain error(4)
1
μV/°C
0.03 %FSR
ppm/°C
EN_MARG = 0b(1)(6)
EN_MARG = 0b(1)(6)
-0.03
–3
±0.005
3.6
dGE/dT
TNS
Gain error thermal drift
Transition noise
0.5
LSB(5)
First output code deviation for
burst-mode data acquisition
See Reference Buffer Module
3
TNS
dB
CMRR
Common-mode rejection ratio dc to 20 kHz
80
SAMPLING DYNAMICS
Aperture delay
4
2
ns
tj-rms
Aperture jitter
ps RMS
MHz
f3-DB(small) Small-signal bandwidth
23
(1) See the REF_MRG Register.
(2) For selected VREF, see the OFST_CAL Register.
(3) While operating with internal reference buffer and LDO.
(4) See Figure 8, Figure 9, Figure 14, and Figure 15 for statistical distribution data for DNL, INL, offset, and gain error parameters.
(5) LSB = least-significant bit. 1 LSB at 16-bit resolution is approximately 15 ppm.
(6) Includes internal reference buffer errors and drifts.
Copyright © 2016–2017, Texas Instruments Incorporated
7
ADS8920B
ADS8922B
ADS8924B
ZHCSFE1B –JUNE 2016–REVISED AUGUST 2017
www.ti.com.cn
Electrical Characteristics (continued)
At RVDD = 5.5 V, DVDD = 1.65 V to 5.5 V, VREF = 5 V, and maximum throughput (unless otherwise noted).
Minimum and maximum values at TA = –40°C to +125°C; typical values at TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
AC ACCURACY(3)(7) (CREFBUF = 10 µF, RESR = 0 Ω)
SINAD
Signal-to-noise + distortion
fIN = 2 kHz
95.7
96
95.9
96.8
95
dB
dB
fIN = 2 kHz
fIN = 100 kHz
fIN = 2 kHz
fIN = 100 kHz
fIN = 2 kHz
SNR
Signal-to-noise ratio
–125
–110
125
THD
Total harmonic distortion
dB
dB
SFDR
Spurious-free dynamic range
LDO OUTPUT (DECAP)
LDO output voltage
VLDO
2.85
V
(DECAP pins)
External ceramic capacitor on
DECAP pins
CLDO
1
µF
tPU_LDO
LDO power-up time
Short-circuit current
CLDO = 1 µF, RVDD > VLDO
1
ms
ISHRT-LDO
100
mA
DIGITAL INPUTS
1.65 V < DVDD < 2.3 V
2.3 V < DVDD < 5.5 V
1.65 V < DVDD < 2.3 V
2.3 V < DVDD < 5.5 V
0.8 DVDD
0.7 DVDD
–0.3
DVDD + 0.3
VIH
VIL
High-level input voltage
V
DVDD + 0.3
0.2 DVDD
0.3 DVDD
0.1
Low-level input voltage
Input current
V
–0.3
±0.01
μA
DIGITAL OUTPUTS
VOH
VOL
High-level output voltage
Low-level output voltage
IOH = 500-µA source
IOH = 500-µA sink
0.8 DVDD
0
DVDD
V
V
0.2 DVDD
POWER SUPPLY
ADS8920B at RVDD = 5 V, 1-MSPS
ADS8922B at RVDD = 5 V, 500-KSPS
ADS8924B at RVDD = 5 V, 250-KSPS
Static, no conversion
Static, PD_ADC = 1b(8)
Static, PD_REFBUF = 1b(8)
4.2
3.2
5.3
4
mA
mA
mA
μA
2.8
3.5
970
900
120
IRVDD
Analog supply current
μA
μA
Static, PD_ADC = 1b and
PD_REFBUF = 1b(8)
40
1
μA
μA
DVDD = 3 V, CLOAD = 10 pF, no
conversion
IDVDD
Digital supply current
Power dissipation
ADS8920B at RVDD = 5 V, 1-MSPS
ADS8922B at RVDD = 5 V, 500-KSPS
ADS8924B at RVDD = 5 V, 250-KSPS
21
16
14
26.5
20
PRVDD
mW
17.5
(7) For VIN = –0.1 dBFS.
(8) See the PD_CNTL Register.
8
Copyright © 2016–2017, Texas Instruments Incorporated
ADS8920B
ADS8922B
ADS8924B
www.ti.com.cn
ZHCSFE1B –JUNE 2016–REVISED AUGUST 2017
6.6 Timing Requirements
TIMING
DIAGRAM
MIN
TYP
MAX
UNIT
CONVERSION CYCLE
ADS8920B
ADS8922B
ADS8924B
ADS8920B
1000
500
fcycle
Sampling frequency
kHz
µs
250
1
2
tcycle
ADC cycle-time period ADS8922B
ADS8924B
Figure 1
4
twh_CONVST Pulse duration: CONVST high
twl_CONVST Pulse duration: CONVST low
30
30
300
30
ns
ns
ns
ns
tacq
Acquisition time
tqt_acq
Quiet acquisition time
Figure 46,
see Data
Transfer
td_cnvcap
Quiet aperture time
20
ns
Protocols
ASYNCHRONOUS RESET, AND LOW POWER MODES
twl_RST Pulse duration: RST low
SPI-COMPATIBLE SERIAL INTERFACE
2.35 V ≤ DVDD ≤ 5.5 V,
100
ns
Figure 2
TA = –40°C to +125°C,
VIH > 0.7 DVDD, VIL < 0.3 DVDD
70
20
57
68
1.65 V ≤ DVDD < 2.35 V,
TA = –40°C to +125°C,
VIH > 0.8 DVDD, VIL < 0.2 DVDD
fCLK
Serial clock frequency
MHz
Figure 3
1.65 V ≤ DVDD < 2.35 V,
TA = 0°C to +60°C,
VIH > 0.8 DVDD, VIL < 0.2 DVDD
1.65 V ≤ DVDD < 2.35 V,
TA = –40°C to +125°C,
VIH > 0.9 DVDD, VIL < 0.1 DVDD
tCLK
Serial clock time period
SCLK high time
1/fCLK
0.45
0.45
12
ns
tCLK
tCLK
ns
Figure 3
Figure 3
tph_CK
0.55
0.55
tpl_CK
SCLK low time
tsu_CSCK
tsu_CKDI
tht_CKDI
tht_CKCS
Setup time: CS falling to the first SCLK capture edge
Setup time: SDI data valid to the SCLK capture edge
Hold time: SCLK capture edge to (previous) data valid on SDI
Delay time: last SCLK falling to CS rising
1.5
1
ns
ns
7
ns
SOURCE-SYNCHRONOUS SERIAL INTERFACE (External Clock)(1)
SDR (DATA_RATE = 0b),
2.35 V ≤ DVDD ≤ 5.5 V
70
35
Figure 4,
see Data
Transfer
Protocols
fCLK
Serial clock frequency
Serial clock time period
MHz
ns
DDR (DATA_RATE = 1b),
2.35 V ≤ DVDD ≤ 5.5 V
tCLK
1/fCLK
(1) The external clock option is not recommended when operating with DVDD < 2.35 V. See Table 9.
Copyright © 2016–2017, Texas Instruments Incorporated
9
ADS8920B
ADS8922B
ADS8924B
ZHCSFE1B –JUNE 2016–REVISED AUGUST 2017
www.ti.com.cn
6.7 Switching Characteristics
At RVDD = 5.5 V, DVDD = 1.65 V to 5.5 V, VREF = 5 V, and maximum throughput (unless otherwise noted).
Minimum and maximum values at TA = –40°C to +125°C; typical values at TA = 25°C.
TIMING
DIAGRAM
PARAMETER
MIN
TYP
MAX
UNIT
CONVERSION CYCLE
ADS8920B
580
1100
2400
640
1200
2500
tconv
Conversion time
ADS8922B
ADS8924B
ns
Figure 1
Figure 2
ASYNCHRONOUS RESET, AND LOW POWER MODES
td_rst
Delay time: RST rising to RVS rising
Power-up time for converter module
3
ms
ms
ms
tPU_ADC
1
See
PD_CNTL
Register
tPU_REFBUF Power-up time for internal reference buffer, CREFBUF = 10 µF
Power-up time for
10
tPU_Device
CLDO = 1 µF, CREFBUF = 10 µF
10
ms
device
SPI-COMPATIBLE SERIAL INTERFACE
tden_CSDO
tdz_CSDO
td_CKDO
Delay time: CS falling to data enable
9
10
ns
ns
ns
ns
Delay time: CS rising to SDO going to Hi-Z
Delay time: SCLK launch edge to (next) data valid on SDO
Figure 3
13
td_CSRDY_f Delay time: CS falling to RVS falling
12
Figure 4
Figure 4
After NOP operation
30
Delay time:
td_CSRDY_r
ns
CS rising to RVS rising
After WR or RD operation
120
SOURCE-SYNCHRONOUS SERIAL INTERFACE (External Clock)(1)
td_CKSTR_r Delay time: SCLK launch edge to RVS rising
td_CKSTR_f Delay time: SCLK launch edge to RVS falling
toff_STRDO_f Time offset: RVS falling to (next) data valid on SDO
toff_STRDO_r Time offset: RVS rising to (next) data valid on SDO
13
13
ns
ns
-2
-2
2
ns
Figure 4
2
ns
tph_STR
tpl_STR
Strobe output high time, 2.35 V ≤ DVDD ≤ 5.5 V
Strobe output low time, 2.35 V ≤ DVDD ≤ 5.5 V
0.45
0.45
0.55
0.55
tSTR
tSTR
SOURCE-SYNCHRONOUS SERIAL INTERFACE (Internal Clock)
td_CSSTR Delay time: CS falling to RVS rising
INTCLK option
15
50
ns
ns
15
30
60
Strobe output time
period
tSTR
INTCLK / 2 option
INTCLK / 4 option
Figure 5
tph_STR
tpl_STR
Strobe output high time
Strobe output low time
0.45
0.45
0.55
0.55
tSTR
tSTR
(1) The external clock option is not recommended when operating with DVDD < 2.35 V. See Table 9.
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Sample
S
Sample
S + 1
twh_CONVST
twl_CONVST
CONVST
tcycle
tconv_max
tconv
tconv_min
tacq
ADCST (Internal)
CNV (C)
ACQ (C + 1)
CS
RVS
Figure 1. Conversion Cycle Timing
trst
twl_RST
RST
td_rst
CONVST
CS
SCLK
RVS
SDO-x
Figure 2. Asynchronous Reset Timing
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tCLK
tph_CK
tpl_CK
SCLK(1)
CS
tsu_CKDI
tht_CKDI
tsu_CSCK
tht_CKCS
SCLK(1)
SDI
tden_CSDO
tdz_CSDO
td_CKDO
SDO-x
SDO-x
(1) The SCLK polarity, launch edge, and capture edge depend on the SPI protocol selected.
Figure 3. SPI-Compatible Serial Interface Timing
tCLK
tph_CK
tpl_CK
CS
SCLK
td_CKSTR_f
tsu_CSCK
tht_CKCS
td_CKSTR_r
SCLK
SDO-x
RVS
RVS
tden_CSDO
tdz_CSDO
toff_STRDO_r
toff_STRDO_f
SDO-x
(DDR)
td_CSRDY_f
td_CSRDY_r
toff_STRDO_r
SDO-x
(SDR)
Figure 4. Source-Synchronous Serial Interface Timing (External Clock)
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tSTR
RVS
CS
tph_STR
tpl_STR
tden_CSDO
tdz_CSDO
toff_STRDO_r
toff_STRDO_f
SDO-x
(DDR)
SDO-x
td_CSRDY_f
td_CSRDY_r
toff_STRDO_r
SDO-x
(SDR)
RVS
td_CSSTR
Figure 5. Source-Synchronous Serial Interface Timing (Internal Clock)
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6.8 Typical Characteristics
at TA = 25°C, RVDD = 5.5 V, DVDD = 3 V, VREF = 5 V, and maximum-rated throughput (unless otherwise noted)
0.5
0.25
0
0.5
0.25
0
-0.25
-0.25
-0.5
-0.5
-32768
32767
-32768
32767
ADC Output Code
ADC Output Code
D001
D002
Typical DNL = ±0.2 LSB
Typical INL = ±0.3 LSB
Figure 6. Typical DNL
Figure 7. Typical INL
500
400
300
200
100
0
500
400
300
200
100
0
5
-0.
4
-0.
3
-0.
2
-0.
1
-0.
0
5
-0.
4
-0.
3
-0.
2
-0.
1
-0.
0
0.1
0.2
0.3
0.4
0.5
0.1
0.2
0.3
0.4
0.5
D007
D008
1000 devices
Figure 8. Typical DNL Distribution
1000 devices
Figure 9. Typical INL Distribution
0.5
0.5
Maximum
Minimum
Maximum
Minimum
0.25
0
0.25
0
-0.25
-0.25
-0.5
-0.5
-40
-7
26
59
92
125
-40
-7
26
59
92
125
Free-Air Temperature (èC)
Free-Air Temperature (èC)
D003
D004
Figure 10. DNL vs Temperature
Figure 11. INL vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, RVDD = 5.5 V, DVDD = 3 V, VREF = 5 V, and maximum-rated throughput (unless otherwise noted)
0.5
0.25
0
0.5
0.25
0
Maximum
Minimum
Maximum
Minimum
-0.25
-0.25
-0.5
-0.5
2.5
3
3.5
4
4.5
5
2.5
3
3.5
4
4.5
5
Reference Voltage (V)
Reference Voltage (V)
D005
D006
Figure 12. DNL vs Reference Voltage
Figure 13. INL vs Reference Voltage
2000
1600
1200
800
400
0
3000
2500
2000
1500
1000
500
0
3
5
-2.
2
5
-1.
1
-
5
-0.
0
1
2
3
3
00
2
00
1
00
0
-
-
01
0.0
02
0.0
03
0.0
0.5
1.5
2.5
-0.
-0.
-0.
D019
D022
4000 devices
Figure 14. Typical Offset Distribution
4000 devices
Figure 15. Typical Gain Error Distribution
5
3
10
6
2
1
-2
-6
-10
-1
-3
-5
-40
-7
26
59
92
125
2.5
3
3.5
4
4.5
5
Free-Air Temperature (èC)
Reference Voltage (V)
D020
D021
REF_SEL[2:0] = 000b
With appropriate REF_SEL[2:0], see OFST_CAL
Figure 16. Offset vs Temperature
Figure 17. Offset vs Reference Voltage
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Typical Characteristics (continued)
at TA = 25°C, RVDD = 5.5 V, DVDD = 3 V, VREF = 5 V, and maximum-rated throughput (unless otherwise noted)
2
0.02
0.01
0
Gain (%FS) ADC only
Gain (%FS) ADC + REFBUF
Gain (%FS) ADC only
Gain (%FS) ADC + REFBUF
1
0
-1
-0.01
-0.02
-2
-40
-7
26
59
92
125
2.5
3.5
4.5
5
Free-Air Temperature (èC)
Reference Voltage (V)
D023
D024
EN_MARG = 0b
EN_MARG = 0b
Figure 18. Gain Error vs Temperature
Figure 19. Gain Error vs Reference Voltage
1500
1250
1000
750
500
250
0
0
-50
-100
-150
-200
2
-1
0
1
2
0
100
200
300
400
500
fIN, Input Frequency (kHz)
D009
D011
Standard Deviation = 0.47 LSB
fIN = 2 kHz
SNR = 96.8 dB
THD = –125 dB
Figure 20. DC Input Histogram
Figure 21. Typical FFT - ADS8920B
0
-50
0
-50
-100
-150
-100
-150
-200
-200
0
0
50
100
150
200
250
25
50
75
100
125
fIN, Input Frequency (kHz)
fIN, Input Frequency (kHz)
D029
D030
fIN = 2 kHz
SNR = 96.8 dB
THD = –125 dB
fIN = 2 kHz
SNR = 96.8 dB
THD = –125 dB
Figure 22. Typical FFT - ADS8922B
Figure 23. Typical FFT - ADS8924B
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Typical Characteristics (continued)
at TA = 25°C, RVDD = 5.5 V, DVDD = 3 V, VREF = 5 V, and maximum-rated throughput (unless otherwise noted)
98
97.75
97.5
97.25
97
16.5
16.25
16
-116
-118
-120
-122
-124
132
128
124
120
116
SNR
SINAD
ENOB
THD
SFDR
15.75
15.5
15.25
15
96.75
96.5
96.25
96
14.75
14.5
-40
-7
26
59
92
125
-40
-7
26
59
92
125
Free-Air Temperature (èC)
Free-Air Temperature (èC)
D013
D014
fIN = 2 kHz
fIN = 2 kHz
Figure 24. Noise Performance vs Temperature
Figure 25. Distortion Performance vs Temperature
-116
-119
-122
-125
-128
132
100
98
96
94
92
90
16
THD
SFDR
SNR
SINAD
ENOB
15.8
15.6
15.4
15.2
15
128
124
120
116
2.5
3
3.5
4
4.5
5
2.5
3
3.5
4
4.5
5
Reference Voltage (V)
Reference Voltage (V)
D015
D016
fIN = 2 kHz
fIN = 2 kHz
Figure 26. Noise Performance vs Reference Voltage
Figure 27. Distortion Performance vs Reference Voltage
-92
124
120
116
112
108
104
100
96
100
98
96
94
92
90
88
17
SNR
THD
SFDR
SINAD
ENOB
-96
-100
-104
-108
-112
-116
-120
-124
16.5
16
15.5
15
14.5
14
92
0
100
200
300
400
500
0
100
200
300
400
500
fIN, Input Frequency (kHz)
fIN, Input Frequency (kHz)
D017
D018
Figure 28. Noise Performance vs Input Frequency
Figure 29. Distortion Performance vs Input Frequency
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Typical Characteristics (continued)
at TA = 25°C, RVDD = 5.5 V, DVDD = 3 V, VREF = 5 V, and maximum-rated throughput (unless otherwise noted)
4.5
4
5
4.5
4
ADS8920B
ADS8922B
ADS8924B
3.5
3
3.5
3
2.5
2
ADS8920B
ADS8922B
ADS8924B
2.5
1.5
2
3
3.5
4
4.5
5
5.5
-40
-7
26
59
92
125
RVDD
Free-Air Temperature (èC)
D026
D028
RVDD = 5 V
Figure 30. Analog Supply Current vs Supply Voltage
Figure 31. Analog Supply Current vs Temperature
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7 Detailed Description
7.1 Overview
The ADS892xB is a family of high-speed, successive approximation register (SAR), analog-to-digital converters
(ADC) based on a charge redistribution architecture. These compact devices integrate a reference buffer and
LDO, and feature high performance at a high throughput rate with low power consumption.
This device family supports unipolar, fully differential, analog input signals. The integrated reference buffer
supports the burst mode of data acquisition for external reference voltages in the range 2.5 V to 5 V, and offers a
wide selection of input ranges without additional input scaling.
When a conversion is initiated, the differential input between the AINP and AINM pins is sampled on the internal
capacitor array. The device uses an internal clock to perform conversions. During the conversion process, both
analog inputs are disconnected from the internal circuit. At the end of conversion process, the device reconnects
the sampling capacitors to the AINP and AINM pins and enters an acquisition phase.
The integrated LDO allows the device to operate on a single supply, RVDD. The device consumes only 21 mW,
16 mW, or 14 mW of power when operating at the rated maximum throughput of 1 MSPS, 500 kSPS, or 250
kSPS, respectively, with the internal reference buffer and LDO enabled.
The enhanced multiSPI™ digital interface is backward-compatible with traditional SPI protocol. Configurable
features simplify board layout, timing, and firmware, and support high throughput at lower clock speeds, thus
allowing an easy interface with a variety of microcontrollers, DSPs, and FPGAs.
The ADS892xB enables test and measurement, medical, and industrial applications to achieve fast, low-noise,
low-distortion, low-power data acquisition in small form factors.
7.2 Functional Block Diagram
REFIN
BUF
REFBUFOUT
REFM
RVDD
LDO
DVDD
DECAP
multiSPITM
Digital
AINP
AINM
To
Digital
Host
SAR ADC
Interface
GND
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7.3 Feature Description
From a functional perspective, the device comprises four modules: the low-dropout regulator (LDO), the
reference buffer (BUF), the converter (SAR ADC), and the interface (multiSPI digital interface), as shown in the
Functional Block Diagram section.
The LDO module is powered by the RVDD supply, and generates the bias voltage for internal circuit blocks of the
device. The reference buffer module buffers the external reference voltage source from the dynamic, capacitive
switching load present on the reference pins during the conversion process. The converter module samples and
converts the analog input into an equivalent digital output code. The interface module facilitates communication
and data transfer between the device and the host controller.
7.3.1 LDO Module
To enable single-supply operation, the device features an internal low-dropout regulator (LDO). The LDO is
powered by the RVDD supply, and the output is available on the two DECAP pins. This LDO output powers the
critical analog blocks within the device, and must not be used for any other external purposes.
Short the two DECAP pins together, and decouple with the GND pin by placing a 1-μF, X7R-grade, ceramic
capacitor with a 10-V rating, as shown in Figure 32. There is no upper limit on the value of the decoupling
capacitor; however, a larger decoupling capacitor results in a longer power-up time for the device. See the
Layout section for layout recommendations.
RVDD
DECAP
DECAP
LDO
CLDO
1 ꢀF
GND
Figure 32. Internal LDO Connections
7.3.2 Reference Buffer Module
On the CONVST rising edge, the device moves from ACQ state to CONV state, and the internal capacitors are
switched to the REFBUFOUT pins as per the successive approximation algorithm. Most of the switching charge
required during the conversion process is provided by external decoupling capacitor CREFBUF. If the charge lost
from the CREFBUF is not replenished before the next CONVST rising edge, the voltage on REFBUFOUT pins is
less than VREFBUFOUT. The subsequent conversion occurs with this different reference voltage, and causes a
proportional error in the output code. The internal reference buffer of the device maintains the voltage on
REFBUFOUT pins within 0.5-LSB of VREFBUFOUT. All the performance characteristics of the device are specified
with the internal reference buffer and specified values of CREFBUF and RESR
.
In burst-mode of operation, the device stays in ACQ state for a long duration of time and then performs a burst of
conversions. During the acquisition state (ACQ), the sampling capacitor (CS) is connected to the differential input
pins and no charge is drawn from the REFBUFOUT pins. However, during the very first conversion cycle, there
is a step change in the current drawn from the REFBUFOUT pins. This sudden change in load triggers a
transient settling response in the reference buffer. For a fixed input voltage, any transient settling error at the end
of the conversion cycle results in a change in output codes over the subsequent conversions, as shown in
Figure 33. The internal reference buffer of the ADS89xxB, when used with the recommended values of CREFBUF
and RESR, keeps the transient settling error at the end of each conversion cycle within 0.5-LSB. Therefore, the
device supports burst-mode of operation with every conversion result being as per the datasheet specifications.
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Feature Description (continued)
3
With External Series Reference Directly Driving SAR ADC
With External Reference Buffer Driving SAR ADC
With ADS892xB Internal Reference Buffer
0
-3
0
100
200
300
400
500
600
700
800
900
1000
Time (µs)
Figure 33. ADC Output Codes in Burst-Mode Operation With Various ADC Reference Buffers
Figure 34 shows the block diagram of the internal reference buffer.
ADS89xxB
RVDD
œ
BUF
REFBUFOUT
REFBUFOUT
REFIN
+
Margin
REFM
REFM
GND
Figure 34. Internal Reference Buffer Block Diagram
The input range for the device is set by the external voltage applied at the REFIN pin (VREF). The REFIN pin has
electrostatic discharge (ESD) protection diodes to the RVDD and GND pins. For minimum input offset error (see
E(IO) specified in the Electrical Characteristics), set the REF_SEL[2:0] bits to the value closest to VREF (see the
OFST_CAL register).
The internal reference buffer has a typical gain of 1 V/V with minimal offset error (see V(RO) specified in the
Electrical Characteristics), and the output of the buffer is available between the REFBUFOUT pins and the REFM
pins. Set the REF_OFST[4:0] bits to add or subtract an intentional offset voltage (see the REF_MRG register).
Figure 35 shows the external connections required for the internal reference buffer.
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Feature Description (continued)
+VA
RVDD
REFIN
ADS89xxB
-
REFBUFOUT
REFBUFOUT
IREF
VREF
BUF
External
Reference
Source
+
RREF_FLT
RESR
Margin
REFM
REFM
CREFBUF
CREF_FLT
GND
Figure 35. External Connections for the Internal Reference Buffer
Select RREF_FLT and CREF_FLT to limit the broadband noise contribution from the external reference source. The
device takes very little current, IREF, from the REFIN pin (typically, 0.1 µA). However, this current flows through
RREF_FLT and may result in additional gain error.
Short the two REFBUFOUT pins externally. Short the two REFM pins to GND externally. As shown in Figure 35,
place a combination of RESR and CREFBUF (see the Electrical Characteristics) between the REFBUFOUT pins and
the REFM pins as close to the device as possible. See the Layout section for layout recommendations.
7.3.3 Converter Module
As shown in Figure 36, the converter module samples the analog input signal (provided between the AINP and
AINM pins), compares this signal with the reference voltage (between the pair of REFBUFOUT and REFM pins),
and generates an equivalent digital output code.
The converter module receives RST and CONVST inputs from the interface module, and outputs the ADCST
signal and the conversion result back to the interface module.
REFP
DVDD
AVDD
RST
OSC
CONVST
CS
RST
SCLK
SDI
AINP
AINM
CONVST
ADCST
Sample-
and-Hold
Circuit
Interface
Module
SDO-0
SDO-1
SDO-2
SDO-3
RVS
ADC
Conversion
Result
AGND
Converter Module
DGND
REFM
GND
Figure 36. Converter Module
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Feature Description (continued)
7.3.3.1 Sample-and-Hold Circuit
These devices support unipolar, fully differential, analog input signals. Figure 37 shows a small-signal equivalent
circuit of the sample-and-hold circuit. Each sampling switch is represented by a resistance (RS1 and RS2, typically
50 Ω) in series with an ideal switch (SW1 and SW2). The sampling capacitors, CS1 and CS2, are typically 60 pF.
RS1
SW1
AINP
4 pF
4 pF
CS1
REFBUFOUT
CS2
GND
GND
RS2
SW2
AINM
Device in Hold Mode
Figure 37. Input Sampling Stage Equivalent Circuit
During the acquisition process (ACQ state), both positive and negative inputs are individually sampled on CS1
and CS2, respectively. During the conversion process (CNV state), the device converts for the voltage difference
between the two sampled values: VAINP – VAINM
.
Each analog input pin has electrostatic discharge (ESD) protection diodes to REFBUFOUT and GND. Keep the
analog inputs within the specified range to avoid turning the diodes on.
Equation 1 and Equation 2 show the full-scale input range (FSR) and common-mode voltage (VCM), respectively,
supported at the analog inputs for any external reference voltage provided on the REFIN pin (VREF).
FSR = êVREF
(1)
V
≈
’
REF
VCM
=
ê 0.1 V
∆
«
÷
◊
2
(2)
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Feature Description (continued)
7.3.3.2 Internal Oscillator
The device family features an internal oscillator (OSC) that provides the conversion clock; see Figure 36. The
conversion duration is bound by the minimum and maximum value of tconv, as specified in the Switching
Characteristics table.
The interface module uses this internal clock (OSC), an external clock (provided by the host controller on the
SCLK pin), or a combination of both the internal and external clocks, to execute the data transfer operations
between the device and host controller; see the Interface Module section for more details.
7.3.3.3 ADC Transfer Function
The device family supports unipolar, fully differential analog inputs. The device output is in two's compliment
format. Figure 38 and Table 1 show the ideal transfer characteristics for the device.
The least significant bit (LSB) for the ADC is given by Equation 3:
FSR
216
VREF
216
1 LSB =
= 2ì
(3)
7FFF
0000
FFFF
8001
8000
VIN
œVREF + 1 LSB
œ1 LSB
0
VREF œ 1 LSB
Differential Analog Input
(AINP - AINM)
Figure 38. Differential Transfer Characteristics
Table 1. Transfer Characteristics
DIFFERENTIAL ANALOG INPUT VOLTAGE
(AINP – AINM)
OUTPUT CODE
(HEX)
< –VREF
–VREF + 1 LSB
–1 LSB
8000
8001
FFFF
0000
0001
7FFF
0
1 LSB
> VREF – 1 LSB
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7.3.4 Interface Module
The interface module facilitates the communication and data transfer between the device and the host controller.
As shown in Figure 39, the module consists of shift registers (both input and output), configuration registers, and
a protocol unit.
Shift Registers
RST
Output Data Register (ODR)
CONVST
D21 D20
D1
D0
CS
22 Bits
22 Bits
SCLK
SDI
B21
B20
B1
B0
Converter Module
SDO-0
SDO-1
SDO-2
SDO-3
RVS
Input Data Register (IDR)
Command Processor
SCLK
Counter
Configuration Registers
Interface Module
Figure 39. Interface Module
The Pin Configuration and Functions section provides descriptions of the interface pins. The Data Transfer
Frame section details the functions of shift registers, the SCLK counter, and the command processor. The Data
Transfer Protocols section details supported protocols. The Register Maps section explains the configuration
registers and bit settings.
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7.4 Device Functional Modes
As shown in Figure 40, this device family supports three functional states: RST, ACQ, and CNV. The device
state is determined by the status of the CONVST and RST control signals provided by the host controller.
Power Up
ACQ
RST Rising Edge
CONVST Rising Edge
RST Falling Edge
End of Conversion
CNV
RST
RST Falling Edge
Figure 40. Device Functional States
7.4.1 RST State
The RST pin is an asynchronous digital input for the device. To enter RST state, the host controller pulls the RST
pin low and keeps it low for the twl_RST duration (as specified in the Timing Requirements table).
In RST state, all configuration registers (see the Register Maps section) are reset to their default values, the RVS
pin remains low, and the SDO-x pins are Hi-Z.
To exit RST state, the host controller pulls the RST pin high, with CONVST and SCLK held low and CS held
high, as shown in Figure 41. After a delay of td_rst, the device enters ACQ state and the RVS pin goes high.
trst
twl_RST
RST
td_rst
CONVST
CS
SCLK
RVS
SDO-x
Figure 41. Asynchronous Reset
To operate the device in either ACQ or CNV state, RST must be held high. With RST held high, transitions on
the CONVST pin determine the functional state of the device.
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Device Functional Modes (continued)
Figure 42 shows a typical conversion process. The internal ADCST signal goes low during conversion and goes
high at the end of conversion. With CS held high, RVS reflects the status of ADCST.
Sample
S
Sample
S + 1
twh_CONVST
twl_CONVST
CONVST
tcycle
tconv_max
tconv
tconv_min
tacq
ADCST (Internal)
CNV (C)
ACQ (C + 1)
CS
RVS
Figure 42. Typical Conversion Process
7.4.2 ACQ State
In ACQ state, the device acquires the analog input signal. The device enters ACQ state at power-up, when
coming out of power down (See the PD Control section), after any asynchronous reset, and at the end of every
conversion.
An RST falling edge takes the device from ACQ state to RST state. A CONVST rising edge takes the device
from ACQ state to CNV state.
7.4.3 CNV State
The device moves from ACQ state to CNV state on a rising edge of the CONVST pin. The conversion process
uses an internal clock. The device ignores any further transitions on the CONVST signal until the ongoing
conversion is complete (that is, during the time interval of tconv).
At the end of conversion, the device enters ACQ state. The cycle time for the device is given by Equation 4:
tcycle-min = tconv + tacq-min
(4)
NOTE
The conversion time, tconv, varies within the specified limits of tconv_min and tconv_max (as
specified in the Switching Characteristics table). After initiating a conversion, the host
controller must monitor for a low-to-high transition on the RVS pin or wait for the tconv_max
duration to elapse before initiating a new operation (data transfer or conversion). If RVS is
not monitored, substitute tconv in Equation 4 with tconv_max
.
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7.5 Programming
This device family features nine configuration registers (as described in the Register Maps section). To access
the internal configuration registers, these devices support the commands listed in Table 2.
Table 2. Supported Commands
COMMAND
ACRONYM
B[21:17]
B[16:8]
B[7:0]
COMMAND DESCRIPTION
00000
10000
10001
10010
10011
11111
000000000
<9-bit address>
<9-bit address>
<9-bit address>
<9-bit address>
111111111
00000000
<8-bit unmasked bits>
00000000
NOP
No operation
CLR_BITS Clear <8-bit unmasked bits> from <9-bit address>
RD_REG Read contents from the <9-bit address>
WR_REG Write <8-bit data> to the <9-bit address>
SET_BITS Set <8-bit unmasked bits> from <9-bit address>
<8-bit data>
<8-bit unmasked bits>
11111111
NOP
No operation
Remaining
combinations
These commands are reserved and treated by the
device as no operation
xxxxxxxxx
xxxxxxxx
Reserved
These devices support two types of data transfer operations: data write (the host controller configures the
device), and data read (the host controller reads data from the device).
Any data write to the device is always synchronous to the external clock provided on the SCLK pin. The
WR_REG command writes the 8-bit data into the 9-bit address specified in the command string. The CLR_BITS
command clears the specified bits (identified by 1) at the 9-bit address (without affecting the other bits), and the
SET_BITS command sets the specified bits (identified by 1) at the 9-bit address (without affecting the other bits).
The data read from the device can be synchronized to the same external clock or to an internal clock of the
device by programming the configuration registers (see the Data Transfer Protocols section for details).
7.5.1 Output Data Word
In any data transfer frame, the contents of an internal, 22-bit, output data word are shifted out on the SDO pins.
The D[21:6] bits of the 22-bit output data word for any frame F + 1, are determined by:
•
•
Value of the DATA_VAL bit applicable to frame F + 1 (see the DATA_CNTL register)
The command issued in frame F
If a valid RD_REG command is executed in frame F, then the D[21:14] bits in frame F + 1 reflect the contents of
the selected register, and the D[13:0] bits are zeros.
If the DATA_VAL bit for frame F + 1 is set to 1, then the D[21:6] bits in frame F + 1 are replaced by the
DATA_PATN[15:0] bits.
For all other combinations, the D[21:6] bits for frame F + 1 are the latest conversion result.
Figure 43 shows the output data word. Figure 44 shows further details of the parity computation unit illustrated in
Figure 43.
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Output Data
Word D[21:0]
A valid RG_READ command is received in
the previous frame?
D21
D20
Yes
Register Data
<8-bit REGDATA>_<8-bit 0's>
D[21:6]
0
16-bit Conversion Result
16-bit DATA_PATN[15:0]
No
1
D7
D6
D5
D4
DATA_VAL
Parity Computation Unit
0b
0b
0b
0b
D3
D2
D1
D0
Figure 43. Output Data Word (D[21:0])
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Output Data Word D[21:0]
Parity Computation Unit
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
XOR
XOR
XOR
XOR
XOR
XOR
XOR
D8
D7
D6
FLPAR
FTPAR
D5
D4
D3
D2
D1
D0
)
)
11
0
0
0
0
16 MSBs
10
01
00
MUX
12 MSBs
8 MSBs
4 MSBs
PAR_EN
FPAR_LOC[1:0]
Figure 44. Parity Bits Computation
With the PAR_EN bit set to 0, the D[5] and D[4] bits of the output data word are set to 0 (default configuration).
When the PAR_EN bit is set to 1, the device calculates the parity bits (FLPAR and FTPAR) and appends them
as bits D[5] and D[4].
•
•
FLPAR is the even parity calculated on bits D[21:6].
FTPAR is the even parity calculated on the bits defined by FPAR_LOC[1:0].
See the DATA_CNTL register for more details on the FPAR_LOC[1:0] bit settings. Bits D[3:0] are set to 0000b.
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7.5.2 Data Transfer Frame
A data transfer frame between the device and the host controller is bounded between a CS falling edge and the
subsequent CS rising edge. The host controller can initiate a data transfer frame (as shown in Figure 45) at any
time irrespective of the status of the CONVST signal; however, the data read during such a data transfer frame is
a function of relative timing between the CONVST and CS signals.
Frame F
CONVST
CS
RVS
As per output protocol selection.
td_CSRDY_r
SCLK
N SCLKs
SDI
Valid Command
SDO-x
ODR Data
SCLK Counter
0
SCLK Counter
N
Output Data Word
Input Data Register (IDR)
D21
D0
D0
B21
B0
D21
D21
D0
Output Data Register (ODR)
Command Processor
Figure 45. Data Transfer Frame
For this discussion, assume that the CONVST signal remains low.
A typical data transfer frame F follows this order:
1. The host controller pulls CS low to initiate a data transfer frame. On the CS falling edge:
–
–
–
RVS goes low, indicating the beginning of the data transfer frame.
The SCLK counter is reset to 0.
The device takes control of the data bus. As shown in Figure 45, the 22-bit contents of the output data
word (see Figure 43) are loaded in to the 22-bit output data register (ODR; see Figure 39).
–
The 22-bit input data register (IDR; see Figure 39) is reset to 000000h, corresponding to a NOP
command.
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2. During the frame, the host controller provides clocks on the SCLK pin. Inside the device:
–
–
–
For each SCLK capture edge, the SCLK counter is incremented and the data bit received on the SDI pin
is shifted in to the IDR.
For each launch edge of the output clock (SCLK in this case), ODR data are shifted out on the selected
SDO-x pins.
The status of the RVS pin depends on the output protocol selection (see the Protocols for Reading From
the Device section).
3. The host controller pulls CS high to end the data transfer frame. On the CS rising edge:
–
–
–
The SDO-x pins go to Hi-Z.
RVS goes high (after a delay of td_CSRDY_r).
As illustrated in Figure 45, the 22-bit contents of the IDR are transferred to the command processor (see
Figure 39) for decoding and further action.
After pulling CS high, the host controller monitors for a low-to-high transition on the RVS pin, or waits for the
td_CSRDY_r time (see the Switching Characteristics table) to elapse before initiating a new operation (data transfer
or conversion). The delay, td_CSRDY_r, for any data transfer frame F varies based on the data transfer operation
executed in frame F.
At the end of data transfer frame F:
•
•
•
If the SCLK counter is < 22, then the IDR captured less than 22 bits from the SDI. In this case, the device
treats frame F as a short command frame. At the end of a short command frame, the IDR is not updated and
the device treats the frame as a no operation (NOP) command.
If the SCLK counter = 22, then the IDR captured exactly 22 bits from SDI. In this case, the device treats the
frame F as a optimal command frame. At the end of an optimal command frame, the command processor
decodes the 22-bit contents of the IDR as a valid command word.
If the SCLK counter > 22, then the IDR captured more than 22 bits from the SDI; however, only the last 22
bits are retained. In this case, the device treats frame F as a long command frame. At the end of a long
command frame, the command processor treats the 22-bit contents of the IDR as a valid command word.
There is no restriction on the maximum number of clocks that can be provided within any data transfer frame
F. However, as explained above, make sure that the last 22 bits shifted into the device before the CS rising
edge constitute the desired command.
In a short command frame, the write operation to the device is invalidated; however, the output data bits
transferred during the short command frame are still valid output data. Therefore, the host controller can use
such shorter data transfer frames to read only the required number of MSB bits from the 22-bit output data word.
As shown in Figure 43, an optimal read frame for the ADS892xB devices must read only the 16 MSB bits of the
output data word. The length of an optimal read frame depends on the output protocol selection; see the
Protocols for Reading From the Device section for more details.
NOTE
The previous example shows data-read and data-write operations synchronous to the
external clock provided on the SCLK pin.
However, the device also supports data read operation synchronous to the internal clock;
see the Protocols for Reading From the Device section for more details. In this case, while
the ODR contents are shifted on the SDO (or SDOs) on the launch edge of the internal
clock, the device continues to capture the SDI data into the IDR (and increment the SCLK
counter) on SCLK capture edges.
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7.5.3 Interleaving Conversion Cycles and Data Transfer Frames
The host controller operates the device at the desired throughput by interleaving the conversion cycles and the
data transfer frames.
The cycle time of the device, tcycle, is the time difference between two consecutive CONVST rising edges
provided by the host controller. The response time of the device, tresp, is the time difference between the host
controller initiating conversion C, and the host controller receiving the complete result for conversion C.
Figure 46 shows three conversion cycles: C, C + 1, and C + 2. Conversion C is initiated by a CONVST rising
edge at time t = 0, and the conversion result becomes available for data transfer at tconv. However, this result is
loaded into the ODR only on the subsequent CS falling edge. This CS falling edge must be provided before the
completion of conversion C + 1 (that is, before tcycle + tconv).
To achieve the rated performance specifications, the host controller must make sure that no digital signals toggle
during the quiet acquisition time (tqt_acq) and quiet aperture time (td_cnvcap). Any noise during td_cnvcap may
negatively affect the result of the ongoing conversion, whereas any noise during tqt_acq may negatively affect the
result of the subsequent conversion.
Sample
Sample
Sample
S
S + 1
S + 2
tcycle
td_cnvcap
tqt_acq
tconv
tacq
CONVST
ADCST
(Internal)
Zone 1
Zone 2
Conversion
Conversion
C + 1
Conversion
C + 2
C
t = 0
Figure 46. Data Transfer Zones
This architecture allows for two distinct time zones (zone 1 and zone 2) to transfer data for each conversion.
Zone 1 and zone 2 for conversion C are defined in Table 3.
Table 3. Data Transfer Zones Timing
ZONE
STARTING TIME
ENDING TIME
tcycle - tqt_acq
tconv
Zone 1 for conversion C
tcycle + td_cnvcap
tcycle + tcycle - tqt_acq
Zone 2 for conversion C
The response time includes the conversion time and the data transfer time, and thus is a function of the selected
data transfer zone.
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Figure 47 and Figure 48 illustrate interleaving of three conversion cycles (C, C + 1, and C + 2) with three data
transfer frames (F, F + 1, and F + 2) in zone 1 and in zone 2, respectively.
Sample
Sample
Sample
S
S + 1
S + 2
tcycle
td_cnvcap
tqt_acq
tconv
tacq
CONVST
ADCST
(Internal)
Zone 1
C
Zone 1
C + 1
Zone 1
C + 2
Conversion
C
Conversion
C + 1
Conversion
C + 2
Frame
Frame
Frame
F
F + 1
F + 2
CS
SDO
tread-Z1
tresp-Z1
C
C + 1
C + 2
SCLK
t = 0
Figure 47. Zone 1 Data Transfer
Sample
S
Sample
S + 1
Sample
S + 2
tcycle
td_cnvcap
tqt_acq
tconv
tacq
CONVST
ADCST
(Internal)
Zone 2
C
Zone 2
C + 1
Zone 2
C + 2
Conversion
Conversion
C + 1
Conversion
C + 2
C
Frame
Frame
Frame
F
F + 1
F + 2
CS
SDO
tread-Z2
tresp-Z2
C œ 1
C
C + 1
SCLK
t = 0
Figure 48. Zone 2 Data Transfer
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To achieve cycle time tcycle, the read time in zone 1 is given by Equation 5:
tread-Z1 Ç tcycle - tconv - tqt_acq
(5)
For an optimal data transfer frame, Equation 5 results in an SCLK frequency given by Equation 6:
16
fSCLK
í
tread-Z1
(6)
(7)
Then, the zone 1 data transfer achieves a response time defined by Equation 7:
tresp-Z1-min = tconv + tread-Z1
At lower SCLK speeds, tread-Z1 increases, resulting in slower response times and higher cycle times.
To achieve the same cycle time, tcycle, the read time in zone 2 is given by Equation 8:
tread-Z2 Ç tcycle - td_cnvcap - tqt_acq
(8)
For an optimal data transfer frame, Equation 8 results in an SCLK frequency given by Equation 9:
16
fSCLK
í
tread_Z2
(9)
Then, the zone 2 data transfer achieves a response time defined by Equation 10:
tresp-Z2-min = tcycle + td_cnvcap + tread-Z2
(10)
Any increase in tread-Z2 increases response time and may increase cycle time.
For a given cycle time, the zone 1 data transfer clearly achieves faster response time, but also requires a higher
SCLK speed (as evident from Equation 5, Equation 6, and Equation 7); whereas, the zone 2 data transfer clearly
requires a lower SCLK speed but has a slower response time (as evident from Equation 8, Equation 9, and
Equation 10). For more information about benefits of zone 2 data transfer when using isolated digital interface or
MCU refer to TI TechNote - Simplify Isolation Designs Using an Enhanced-SPI ADC Interface.
NOTE
A data transfer frame can begin in zone 1, and then extend into zone 2; however, the host
controller must make sure that no digital transitions occur during the tqt_acq and td_cnvcap
time intervals.
NOTE
For data transfer operations in zone
2 using the ADC-Clock-Master protocol
(SDO_MODE[1:0] = 11b), the device supports only the external-clock-echo option
(SSYNC_CLK_SEL[1:0] = 00b); see Table 9.
7.5.4 Data Transfer Protocols
This device family features a multiSPI digital interface that allows the host controller to operate at slower SCLK
speeds and still achieve the required throughput and response time. The multiSPI digital interface module offers
three options to reduce the SCLK speed required for data transfer:
•
•
•
Increase the width of the output data bus.
Enable double data rate (DDR) transfer.
Extended data transfer window, as shown in Figure 48.
These three options can be combined to achieve further reduction in SCLK speed.
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There are various factors that limit the maximum SCLK frequency in a system.
Figure 49 shows the delays in the communication channel between the host controller and the device in a typical
serial communication.
Digital Isolator
(Optional)
TI Device
Host Controller
tpcb_CK
SCLK
SCLK
td_ckdo
tsu_h
td_ISO
SDI
SDO-x
td_ISO
tpcb_SDO
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Figure 49. Delays in Serial Communication
For example, if tpcb_CK and tpcb_SDO are the delays introduced by the printed circuit board (PCB) traces for the
serial clock and SDO signals, td_CKDO is the clock-to-data delay of the device, td_ISO is the propagation delay
introduced by the digital isolator, and tsu_h is the setup time specification of the host controller, then the total
delay in the path is given by Equation 11:
td_total_serial = tpcb_CK + td_iso + td_ckdo + td_iso + tpcb_SDO + tsu_h
(11)
In a standard SPI protocol, the host controller and the device launch and capture data bits on alternate SCLK
edges. Therefore, the td_total_serial delay must be kept to less than half of the SCLK duration. Equation 12 shows
the fastest clock allowed by the SPI protocol:
1
fclk-SPI
Ç
2ìtd_total-serial
(12)
Larger values of the td_total_serial delay restricts the maximum SCLK speed for the SPI protocol, resulting in higher
read and response times, and can possibly limit the throughput.
Figure 50 shows a delay (td_delcap) introduced in the capture path (inside the host controller).
Digital Isolator
(Optional)
Device
Host Controller
tpcb_CK
td_delcap
SCLK
tsu_h
SCLK
td_ckdo
td_ISO
SDI
SDO-x
td_ISO
tpcb_SDO
Figure 50. Delayed Capture
The total delay in the path modifies to Equation 13:
td_total_serial = tpcb_CK + td_iso + td_ckdo + td_iso + tpcb_SDO + tsu_h - td_ delcap
(13)
This reduction in total delay allows the SPI protocol to operate at higher clock speeds.
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The multiSPI digital interface module offers two additional options to remove the restriction on the SCLK speed:
•
Early data launch (EDL) mode of operation
In EDL mode, the device launches the output data on SDO-x pin (or pins) half a clock earlier compared to the
standard SPI protocol. Therefore, Equation 12 modifies to Equation 14:
1
fclk-SPI
Ç
td_total-serial
(14)
The reduction in total delay allows the serial interface to operate at higher clock speeds.
•
ADC-Clock-Master (source-synchronous) mode of operation
As illustrated in Figure 51, in ADC-Clock-Master mode, the device provides a synchronous output clock (on
the RVS pin) along with the output data (on the SDO-x pins).
Digital Isolator
(Optional)
TI Device
Host Controller
tpcb_CK
SCLK
SCLK
td_ckdo
td_ISO
SDO-x
td_ckstr
SDI
td_ISO
tsu_h
toff_strdo
tpcb_SDO
RVS
td_ISO
tpcb_RVS
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Figure 51. Delays in ADC-Clock-Master (Source-Synchronous) Mode
For negligible values of toff_STRDO, the total delay in the path for a source-synchronous data transfer, is given
by Equation 15:
td_total_srcsync = tpcb_RVS -tpcb_SDO + tsu_h
(15)
As shown by the difference between Equation 11 and Equation 15, using ADC-Clock-Master mode
completely eliminates the effect of isolator delays (td_ISO) and clock-to-data delays (td_CKDO); typically, the
largest contributors in the overall delay computation.
Furthermore, the actual values of tpcb_RVS and tpcb_SDO do not matter. In most cases, the td_total_srcsync delay
can be kept at a minimum by routing the RVS and SDO lines together on the PCB. Therefore, the ADC-
Clock-Master mode allows the data transfer between the host controller and the device to operate at much
higher SCLK speeds. For more information about using ADC-Clock-Master to mode to achieve fast SCLK
speeds, with an isolated interface or high routing delays, see Optimizing Data Transfer on High-Resolution,
High Throughput Data Converters. Zone 2 data transfer also enables longer quiet time for analog input
settling, and is discussed in Improving Input Settling for Precision Data Converters.
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7.5.4.1 Protocols for Configuring the Device
As shown in Table 4, the host controller can use any of the four legacy, SPI-compatible protocols (SPI-00-S, SPI-
01-S, SPI-10-S, or SPI-11-S) to write data to the device.
Table 4. SPI Protocols for Configuring the Device
NO. OF SCLK
(Optimal Command
Frame)
SCLK POLARITY
(At CS Falling Edge)
SCLK PHASE
(Capture Edge)
TIMING
DIAGRAM
PROTOCOL
SDI_CNTL
SDO_CNTL
SPI-00-S
SPI-01-S
SPI-10-S
SPI-11-S
Low
Low
High
High
Rising
Falling
Falling
Rising
00h
01h
02h
03h
00h
00h
00h
00h
22
22
22
22
Figure 52
Figure 53
Figure 54
Figure 55
At power-up or after coming out of any asynchronous reset, the device supports the SPI-00-S protocol for data-
read and data-write operations.
To select a different SPI-compatible protocol, program the SDI_MODE[1:0] bits in the SDI_CNTL register. This
first write operation must adhere to the SPI-00-S protocol. Any subsequent data transfer frames must adhere to
the newly selected protocol.
Figure 52 to Figure 55 detail the four protocols using an optimal command frame; see the Timing Requirements
and Switching Characteristics tables for associated timing parameters.
NOTE
As explained in the Data Transfer Frame section, a valid write operation to the device
requires a minimum of 22 SCLKs to be provided within a data transfer frame.
Any data write operation to the device must continue to follow the SPI-compatible protocol
selected in the SDI_CNTL register, irrespective of the protocol selected for the data-read
operation.
CS
SCLK
SDI
CS
SCLK
SDI
B21
B20
B1
B0
B21
B20
B19
B1
B0
RVS
RVS
Figure 52. SPI-00-S Protocol, Optimal Command
Frame
Figure 53. SPI-01-S Protocol, Optimal Command
Frame
CS
CS
SCLK
SCLK
SDI
B21
B20
B19
B1
B0
SDI
B21
B20
B2
B1
B0
RVS
RVS
Figure 54. SPI-10-S Protocol, Optimal Command
Frame
Figure 55. SPI-11-S Protocol, Optimal Command
Frame
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7.5.4.2 Protocols for Reading From the Device
The protocols for the data-read operation can be broadly classified into three categories:
1. Legacy, SPI-compatible (SPI-xy-S) protocol
2. SPI-compatible protocols with bus width options (SPI-xy-D and SPI-xy-Q)
3. Source-synchronous (SRC) protocols
7.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols
As shown in Table 5, the host controller can use any of the four legacy, SPI-compatible protocols (SPI-00-S, SPI-
01-S, SPI-10-S, or SPI-11-S) to read data from the device.
Table 5. SPI Protocols for Reading From the Device
SCLK
NO. OF SCLK
(Optimal Read
Frame)
POLARITY
(At CS Falling
Edge)
SCLK PHASE
(Capture Edge)
MSB BIT
LAUNCH EDGE
TIMING
DIAGRAM
PROTOCOL
SDI_CNTL
SDO_CNTL
SPI-00-S
SPI-01-S
SPI-10-S
SPI-11-S
Low
Low
High
High
Rising
Falling
Falling
Rising
CS falling
1st SCLK rising
CS falling
00h
01h
02h
03h
00h
00h
00h
00h
16
16
16
16
Figure 56
Figure 57
Figure 58
Figure 59
1st SCLK falling
At power-up or after coming out of any asynchronous reset, the device supports the SPI-00-S protocol for data-
read and data-write operations. To select a different SPI-compatible protocol for both the data transfer
operations:
1. Program the SDI_MODE[1:0] bits in the SDI_CNTL register. This first write operation must adhere to the SPI-
00-S protocol. Any subsequent data transfer frames must adhere to the newly selected protocol.
2. Set the SDO_MODE[1:0] bits = 00b in the SDO_CNTL register.
Figure 56 to Figure 59 explain the details of the four protocols using an optimal command frame to read all 22
bits of the output data word. Table 5 shows the number of SCLK required in an optimal read frame for the
different output protocol selections.
D21
CS
SCLK
SDO-0
RVS
CS
SCLK
SDO-0
RVS
D21
D20
D1
D0
D20
D20
D20
D19
D1
D1
D0
D0
D21
D21
D20
D20
D19
D0
D21
D21
D19
D1
D0
0
D1
D0
Figure 56. SPI-00-S Protocol, 22 SCLKs
Figure 57. SPI-01-S Protocol, 22 SCLKs
D21
CS
SCLK
SDO-0
RVS
CS
SCLK
SDO-0
RVS
D21
D20
D19
D1
D0
D21
D20
D20
D19
D19
D1
D1
D0
D0
D21
D21
D20
D20
D2
D1
D0
D0
D21
D20
D1
D0
0
D2
D1
Figure 58. SPI-10-S Protocol, 22 SCLKs
Figure 59. SPI-11-S Protocol, 22 SCLKs
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For SDI_MODE[1:0] = 00b or 10b, the device supports an Early Data Launch (EDL) option. Set SDO_MODE[1:0]
= 01b in the SDO_CNTL register to enable the feature (see Table 6). Setting SDO_MODE[1:0] = 01b has no
effect if SDI_MODE[1:0] = 01b or 11b.
Table 6. SPI Protocols with Early Data Launch
SCLK POLARITY
(At CS Falling
Edge)
NO. OF SCLK
(Optimal Read
Frame)
SCLK PHASE
(Capture Edge)
MSB BIT LAUNCH
EDGE
TIMING
DIAGRAM
PROTOCOL
SDI_CNTL
SDO_CNTL
SPI-00-S-EDL
SPI-10-S-EDL
Low
Rising
Falling
CS falling
CS falling
00h
02h
01h
01h
16
16
Figure 56
Figure 58
High
As shown in Figure 60, and Figure 61, the device launches the output data bit on the SDO-0 pin half clock earlier
compared to the standard SPI protocol.
D21
D21
CS
SCLK
SDO-0
RVS
CS
SCLK
SDO-0
RVS
D21
D20
D19
D1
D1
D0
D0
D20
D19
D18
D0
0
D21
D21
D20
D20
D19
D1
D1
D0
D20
D20
D19
D19
D18
D0
D19
D0
D21
Figure 60. SPI-00-S-EDL Protocol, 22 SCLKs
Figure 61. SPI-10-S-EDL Protocol, 22 SCLKs
When using these SPI-compatible protocols, the RVS output remains low throughout the data transfer frame; see
the Timing Requirements and Switching Characteristics tables for associated timing parameters.
With SDO_CNTL[7:0] = 00h or 01h, if the host controller uses a long data transfer frame, the device exhibits
daisy-chain operation (see the Multiple Devices: Daisy-Chain Topology section).
NOTE
Use SPI-compatible protocols to execute the RD_REG, WR_REG, CLR_BITS, and
SET_BITS commands specified in Table 2.
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7.5.4.2.2 SPI-Compatible Protocols with Bus Width Options
The device provides an option to increase the SDO bus width from one bit (default, single SDO) to two bits (dual
SDO) or four bits (quad SDO) when operating with any of the four legacy, SPI-compatible protocols.
Set the SDO_WIDTH[1:0] bits in the SDO_CNTL register to select the SDO bus width. The SCLK launch edge
depends on the SPI protocol selection (as shown in Table 7).
Table 7. SPI-Compatible Protocols with Bus Width Options
SCLK
#SCLK
(Optimal Read
Frame)
POLARITY
(At CS Falling
Edge)
SCLK PHASE
(Capture Edge)
MSB BIT
LAUNCH EDGE
TIMING
DIAGRAM
PROTOCOL
SDI_CNTL
SDO_CNTL
SPI-00-D
SPI-01-D
SPI-10-D
SPI-11-D
SPI-00-Q
SPI-01-Q
SPI-10-Q
SPI-11-Q
Low
Low
High
High
Low
Low
High
High
Rising
Falling
Falling
Rising
Rising
Falling
Falling
Rising
CS falling
First SCLK rising
CS falling
00h
01h
02h
03h
00h
01h
02h
03h
08h
08h
08h
08h
0Ch
0Ch
0Ch
0Ch
8
8
8
8
4
4
4
4
Figure 62
Figure 63
Figure 64
Figure 65
Figure 66
Figure 67
Figure 68
Figure 69
First SCLK falling
CS falling
First SCLK rising
CS falling
First SCLK falling
In dual-SDO mode (SDO_WIDTH[1:0] = 10b), two bits of data are launched on the two SDO pins (SDO-0 and
SDO-1) on every SCLK launch edge.
In quad-SDO mode (SDO_WIDTH[1:0] = 11b), four bits of data are launched on the four SDO pins (SDO-0,
SDO-1, SDO-2, and SDO-3) on every SCLK launch edge.
CS
CS
SCLK
SDO-1
SDO-0
RVS
SCLK
SDO-1
SDO-0
0
0
D21
D20
D19
D18
D3
D2
D1
D0
D21
D20
D19
D18
D3
D2
D1
D0
RVS
Figure 62. SPI-00-D Protocol
Figure 63. SPI-01-D Protocol
CS
SCLK
SDO-1
SDO-0
RVS
CS
SCLK
SDO-1
SDO-0
RVS
D21
D20
D19
D18
D3
D2
D1
D0
0
0
D21
D20
D19
D18
D5
D4
D3
D2
D1
D0
Figure 64. SPI-10-D Protocol
Figure 65. SPI-11-D Protocol
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CS
CS
SCLK
SCLK
SDO-3
SDO-2
SDO-1
SDO-0
RVS
D21
D20
D19
D18
D17
D16
D15
D14
D1
D0
0
SDO-3
SDO-2
SDO-1
SDO-0
RVS
0
0
0
0
D21
D20
D19
D18
D17
D16
D15
D14
D5
D4
D3
D2
D1
D0
0
0
0
Figure 66. SPI-00-Q Protocol
Figure 67. SPI-01-Q Protocol
CS
SCLK
SDO-3
SDO-2
SDO-1
SDO-0
RVS
CS
SCLK
SDO-3
SDO-2
SDO-1
SDO-0
RVS
0
0
0
0
D21
D20
D19
D18
D17
D16
D15
D14
D5
D4
D3
D2
D1
D21
D20
D19
D18
D17
D16
D15
D14
D1
D0
0
D0
0
0
0
Figure 68. SPI-10-Q Protocol
Figure 69. SPI-11-Q Protocol
For SDI_MODE[1:0] = 00b or 10b, the device supports an early data launch (EDL) option. Set SDO_MODE[1:0]
= 01b in the SDO_CNTL register to enable the feature (see Table 8). Setting SDO_MODE[1:0] = 01b has no
effect if SDI_MODE[1:0] = 01b or 11b.
Table 8. SPI Protocols with Early Data Launch
SCLK
NO. OF SCLK
(Optimal Read
Frame)
POLARITY
(At CS Falling
Edge)
SCLK PHASE
(Capture Edge)
MSB BIT
LAUNCH EDGE
TIMING
DIAGRAM
PROTOCOL
SDI_CNTL
SDO_CNTL
SPI-00-D-
EDL
Low
High
Low
High
Rising
Falling
Rising
Falling
CS falling
CS falling
CS falling
CS falling
00h
02h
00h
02h
09h
09h
0Dh
0Dh
8
8
4
4
Figure 62
Figure 64
Figure 66
Figure 68
SPI-10-D-
EDL
SPI-00-Q-
EDL
SPI-10-Q-
EDL
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As shown in Figure 60, and Figure 61, the device launches the output data bits on the SDO-x pins half clock
earlier compared to the standard SPI protocol.
CS
SCLK
SDO-1
SDO-0
RVS
CS
SCLK
D21
D20
D19
D18
D17
D16
D3
D2
D1
D0
SDO-1
SDO-0
RVS
D21
D20
D19
D18
D17
D16
D3
D2
D1
D0
Figure 70. SPI-00-D-EDL Protocol
Figure 71. SPI-10-D-EDL Protocol
CS
SCLK
SDO-3
SDO-2
SDO-1
SDO-0
RVS
CS
SCLK
SDO-3
SDO-2
SDO-1
SDO-0
RVS
D21
D20
D19
D18
D17
D16
D15
D14
D1
D0
D21
D20
D19
D18
D17
D16
D15
D14
D1
D0
0
0
0
0
Figure 72. SPI-00-Q-EDL Protocol
Figure 73. SPI-10-Q-EDL Protocol
When using any of the SPI-compatible protocols, the RVS output remains low throughout the data transfer frame;
see the Timing Requirements and Switching Characteristics tables for associated timing parameters.
Figure 62 to Figure 73 illustrate how the wider data bus allows the host controller to read all 22 bits of the output
data word using shorter data transfer frames. Table 7 and Table 8 show the number of SCLK required in an
optimal read frame for the different output protocol selections.
NOTE
With SDO_CNTL[7:0] ≠ 00h or 01h, a long data transfer frame does not result in daisy-
chain operation. On SDO pin (or pins), the 22 bits of output data word are followed by
zeros.
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7.5.4.2.3 Source-Synchronous (SRC) Protocols
As described in the Data Transfer Protocols section, the multiSPI digital interface supports an ADC-Clock-Master
or a source-synchronous mode of data transfer between the device and host controller. In this mode, the device
provides an output clock that is synchronous with the output data. Furthermore, the host controller can also
select the output clock source, data bus width, and data transfer rate.
7.5.4.2.3.1 Output Clock Source Options with SRC Protocols
In all SRC protocols, the RVS pin provides the output clock. The device allows this output clock to be
synchronous to either the external clock provided on the SCLK pin or to the internal clock of the device.
Furthermore, this internal clock can be divided by a factor of two or four to lower the data rates.
As shown in Figure 74, set the SSYNC_CLK_SEL[1:0] bits in the SDO_CNTL register to select the output clock
source.
SCLK
OSC
00
INTCLK
01
Output Clock
RVS
INTCLK / 2
INTCLK / 4
10
11
/ 2
/ 4
SSYNC_CLK_SEL [1:0]
Figure 74. Output Clock Source Options With SRC Protocols
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7.5.4.2.3.2 Bus Width Options With SRC Protocols
The device provides an option to increase the SDO bus width from one bit (default, single SDO) to two bits (dual
SDO) or to four bits (quad SDO) when operating with any of the SRC protocols. Set the SDO_WIDTH[1:0] bits in
the SDO_CNTL register to select the SDO bus width.
In dual-SDO mode (SDO_WIDTH[1:0] = 10b), two bits of data are launched on the two SDO pins (SDO-0 and
SDO-1) on every SCLK rising edge.
In quad-SDO mode (SDO_WIDTH[1:0] = 11b), four bits of data are launched on the four SDO pins (SDO-0,
SDO-1, SDO-2, and SDO-3) on every SCLK rising edge.
7.5.4.2.3.3 Output Data Rate Options With SRC Protocols
The device provides an option to transfer the data to the host controller at a single data rate (default, SDR) or at
a double data rate (DDR). Set the DATA_RATE bit in the SDO_CNTL register to select the data transfer rate.
In SDR mode (DATA_RATE = 0b), the RVS pin toggles from low to high, and the output data bits are launched
on the SDO pins on the output clock rising edge.
In DDR mode (DTA_RATE = 1b), the RVS pin toggles (from low-to-high or high-to-low), and the output data bits
are launched on the SDO pins on every output clock edge, starting with the first rising edge.
The device supports all 24 combinations of output clock source, bus width, and output data rate, as shown in
Table 9.
Table 9. SRC Protocol Combinations
#OUTPUT CLOCK
(Optimal Read
Frame)
OUTPUT CLOCK
SOURCE
OUTPUT DATA
RATE
TIMING
DIAGRAM
PROTOCOL
BUS WIDTH
SDI_CNTL
SDO_CNTL
SRC-EXT-SS
SRC-INT-SS
SRC-IB2-SS
SRC-IB4-SS
SRC-EXT-DS
SRC-INT-DS
SRC-IB2-DS
SRC-IB4-DS
SRC-EXT-QS
SRC-INT-QS
SRC-IB2-QS
SRC-IB4-QS
SRC-EXT-SD
SRC-INT-SD
SRC-IB2-SD
SRC-IB4-SD
SRC-EXT-DD
SRC-INT-DD
SRC-IB2-DD
SRC-IB4-DD
SRC-EXT-QD
SRC-INT-QD
SRC-IB2-QD
SRC-IB4-QD
SCLK(1)
INTCLK(3)
INTCLK / 2(3)
INTCLK / 4(3)
SCLK(1)
Single
Single
Single
Single
Dual
SDR
SDR
SDR
SDR
SDR
SDR
SDR
SDR
SDR
SDR
SDR
SDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
DDR
03h
43h
83h
C3h
0Bh
4Bh
8Bh
CBh
0Fh
4Fh
8Fh
CFh
13h
53h
93h
D3h
1Bh
5Bh
9Bh
DBh
1Fh
5Fh
9Fh
DFh
8
8
8
8
8
8
8
8
4
4
4
4
8
8
8
8
4
4
4
4
2
2
2
2
Figure 75
Figure 76
Figure 79
Figure 80
Figure 83
Figure 84
Figure 77
Figure 78
Figure 81
Figure 82
Figure 85
Figure 86
INTCLK(3)
Dual
INTCLK / 2(3)
INTCLK / 4(3)
SCLK(1)
Dual
Dual
Quad
Quad
Quad
Quad
Single
Single
Single
Single
Dual
INTCLK(3)
INTCLK / 2(3)
INTCLK / 4(3)
SCLK(1)
00h, 01h,
02h, or 03h(2)
INTCLK(3)
INTCLK / 2(3)
INTCLK / 4(3)
SCLK(1)
INTCLK(3)
Dual
INTCLK / 2(3)
INTCLK / 4(3)
SCLK(1)
INTCLK(3)
INTCLK / 2(3)
INTCLK / 4(3)
Dual
Dual
Quad
Quad
Quad
Quad
(1) The EXTCLK option is not recommended when operating with DVDD < 2.35 V.
(2) Any of the four values can be used; see the Protocols for Configuring the Device section for more information.
(3) The device supports INTCLK, INTCLK / 2, and INTCLK / 4 options only for data transfer operations in zone 1. The EXTCLK option is
supported in zone 1 and zone 2; see Figure 46.
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Figure 75 to Figure 86 show the details of various source synchronous protocols. Table 9 shows the number of
output clocks required in an optimal read frame for the different output protocol selections.
CS
SCLK
SDO-0
RVS
CS
SCLK
SDO-0
RVS
D21
D20
D21
D19
D20
D1
D2
D0
D1
D0
D21
D20
D2
D1
D0
Figure 75. SRC-EXT-SS: SRC, SCLK, Single SDO,
SDR
Figure 76. SRC-INT-SS: SRC, INTCLK, Single SDO,
SDR
CS
CS
D20
D2
D0
D1
SCLK
SCLK
SDO-0
RVS
D21
D19
D21 D20
D1
D2
SDO-0
RVS
D21 D20
D3
D2
D1
D0
D3
D0
Figure 77. SRC-EXT-SD: SRC, SCLK, Single SDO, Figure 78. SRC-INT-SD: SRC, INTCLK, Single SDO,
DDR
DDR
CS
SCLK
SDO-1
SDO-0
RVS
CS
SCLK
D21
D20
D19
D18
D5
D4
D3
D2
D1
D0
SDO-1
SDO-0
RVS
D21
D20
D19
D18
D5
D4
D3
D2
D1
D0
Figure 79. SRC-EXT-DS: SRC, SCLK, Dual SDO,
SDR
Figure 80. SRC-INT-DS: SRC, INTCLK, Dual SDO,
SDR
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CS
SCLK
SDO-1
SDO-0
RVS
SCLK
D21 D19
D20 D18
D7
D6
D5
D4
D3
D2
D1
D0
SDO-1
SDO-0
RVS
D21 D19
D20 D18
D7
D6
D5
D4
D3
D2
D1
D0
Figure 81. SRC-EXT-DD: SRC, SCLK, Dual SDO,
DDR
Figure 82. SRC-INT-DD: SRC, INTCLK, Dual SDO,
DDR
CS
CS
SCLK
SCLK
SDO-3
SDO-2
SDO-1
SDO-0
RVS
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
SDO-3
SDO-2
SDO-1
SDO-0
RVS
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
Figure 83. SRC-EXT-QS: SRC, SCLK, Quad SDO,
SDR
Figure 84. SRC-INT-QS: SRC, INTCLK, Quad SDO,
SDR
CS
CS
SCLK
SCLK
SDO-3
SDO-2
SDO-1
SDO-0
RVS
D21 D17 D13 D9
D20 D16 D12 D8
D19 D15 D11 D7
D18 D14 D10 D6
D5
D4
D3
D2
D1
D0
0
SDO-3
SDO-2
SDO-1
SDO-0
RVS
D21 D17 D13 D9
D20 D16 D12 D8
D19 D15 D11 D7
D18 D14 D10 D6
D5
D4
D3
D2
D1
D0
0
0
0
Figure 85. SRC-EXT-QD: SRC, SCLK, Quad SDO,
DDR
Figure 86. SRC-INT-QD: SRC, INTCLK, Quad SDO,
DDR
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7.5.5 Device Setup
The multiSPI digital interface and the device configuration registers offer multiple operation modes. This section
describes how to select the hardware connection topology to meet different system requirements.
7.5.5.1 Single Device: All multiSPI Options
Figure 87 shows the connections between a host controller and a single device in order to exercise all options
provided by the multiSPI digital interface.
DVDD
Isolation
(Optional)
RST
CONVST
CS
SCLK
SDI
Host
TI Device
SDO-0
SDO-1
SDO-2
SDO-3
RVS
Controller
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Figure 87. MultiSPI Digital Interface, All Pins
7.5.5.2 Single Device: Minimum Pins for a Standard SPI Interface
Figure 88 shows the minimum-pin interface for applications using a standard SPI protocol.
DVDD
Isolation
(Optional)
(Optional)
RST
(Optional)
CONVST
CS
SCLK
SDI
Host
Controller
TI Device
SDO-0
SDO-1
SDO-2
SDO-3
RVS
(Optional)
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Figure 88. SPI Interface, Minimum Pins
The CS, SCLK, SDI, and SDO-0 pins constitute a standard SPI port of the host controller. The CONVST pin is
tied to CS, and the RST pin is tied to DVDD. The SDO-1, SDO-2, and SDO-3 pins have no external connections.
The following features are also available:
•
•
•
Control the CONVST pin independently to get additional timing flexibility.
Control RST pin independently to add asynchronous reset functionality.
Monitor the RVS pin for additional timing benefits.
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7.5.5.3 Multiple Devices: Daisy-Chain Topology
A typical connection diagram showing multiple devices in a daisy-chain topology is shown in Figure 89.
Host Controller
Device 1
Device 2
Device N
Figure 89. Daisy-Chain Connections
The CONVST, CS, and SCLK inputs of all devices are connected together and controlled by a single CONVST,
CS, and SCLK pin of the host controller, respectively. The SDI input pin of the first device in the chain (Device 1)
is connected to the SDO pin of the host controller, the SDO-0 output pin of Device 1 is connected to the SDI
input pin of Device 2, and so on. The SDO-0 output pin of the last device in the chain (Device N) is connected to
the SDI pin of the host controller.
To operate multiple devices in a daisy-chain topology, the host controller sets the configuration registers in each
device with identical values and operates with any of the legacy, SPI-compatible protocols for data-read and
data-write operations (SDO_CNT[7:0] = 00h or 01h). With these configurations settings, the 22-bit ODR and 22-
bit IDR registers in each device collapse to form a single, 22-bit unified shift register (USR) per device, as shown
in Figure 90.
Host Controller
SDO
CONVST
SCLK
SDI
CS
22 Bits
22 Bits
22 Bits
SDI
SDO-0
SDI
SDO-0
SDI
SDO-0
DB DB
DB DB
20 21
DB DB
DB DB
20 21
DB DB
DB DB
20 21
0
1
0
1
0
1
Unified Shift Register (USR)
Device 1
Unified Shift Register (USR)
Device 2
Unified Shift Register (USR)
Device N
Figure 90. Unified Shift Register
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All devices in the daisy-chain topology sample the respective device analog input signals on the CONVST rising
edge. The data transfer frame starts with a CS falling edge. On each SCLK launch edge, every device in the
chain shifts out the MSB of the respective USR on to the respective SDO-0 pin. On every SCLK capture edge,
each device in the chain shifts in data received on the respective SDI pin as the LSB bit of the respective USR.
Therefore, in a daisy-chain configuration, the host controller receives the data of Device N, followed by the data
of Device N – 1, and so on (MSB-first). On the CS rising edge, each device decodes the contents in the
respective USR, and takes appropriate action.
A typical timing diagram for three devices connected in daisy-chain topology using the SPI-00-S protocol is
shown in Figure 91.
CS
SCLK
1
2
21
22
23
24
43
44
45
46
Configuration Data Device 1
B20 B1
Configuration Data Device 2
B42 B23
Configuration Data Device 3
B64 B45
Output Data œ Device 1
{D20}1 {D1}1
65
66
{SDO}HOST
{SDI}1
B65
B64
B45
B44
B43
B42
B23
B22
B21
B0
{SDO-0}1
{SDI}2
{D21}1
{D21}2
{D21}3
{D20}1
{D20}2
{D1}1
{D1}2
{D0}1
{D0}2
{D0}3
B65
B64
B45
B44
{D0}1
{D0}2
B43
B65
B22
B44
{SDO-0}2
{SDI}3
{D21}1
{D21}2
{D20}1
{D1}1
Output Data œ Device 3
{D20}3 {D1}3
Output Data œ Device 2
{D20}2 {D1}2
{SDO-0}3
{SDI}HOST
{D21}1
{D0}1
Figure 91. Three-Device, Daisy-Chain Timing
In daisy-chain topology, the overall throughput of the system is proportionally reduced as more devices are
connected in the daisy-chain.
NOTE
For N devices connected in daisy-chain topology, an optimal data transfer frame must
contain 22 × N SCLK capture edges. For a longer data transfer frame (number of SCLK in
the frame > 22 × N), the host controller must appropriately align the configuration data for
each device before bringing CS high. A shorter data transfer frame (number of SCLK in
the frame < 22 × N) might result in an erroneous device configuration, and must be
avoided.
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7.5.5.4 Multiple Devices: Star Topology
A typical connection diagram showing multiple devices in a star topology is shown in Figure 92. The CONVST,
SDI, and SCLK inputs of all devices are connected together, and are controlled by a single CONVST, SDO, and
SCLK pin of the host controller, respectively. Similarly, the SDO output pin of all devices are tied together and
connected to the a single SDI input pin of the host controller. The CS input pin of each device is individually
controlled by separate CS control lines from the host controller.
Host Controller
TI Device 1
TI Device 2
TI Device N
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Figure 92. Star-Topology Connection
The timing diagram for three devices connected in the star topology is shown in Figure 93. In order to avoid any
conflict related to multiple devices driving the SDO line at the same time, make sure that the host controller pulls
down the CS signal for only one device at any particular time.
SCLK
{CS}1
{CS}2
{CS}3
1
2
21
22
23
24
43
44
45
46
65
66
Configuration Data Device 1
{B20}1 {B1}1
Output Data œ Device 1
{D20}1 {D1}1
Configuration Data Device 2
{B20}2 {B1}2
Output Data œ Device 2
{D20}2 {D1}2
Configuration Data Device 3
{B20}3 {B1}3
Output Data œ Device 3
{D20}3 {D1}3
{SDO}HOST
{SDI}1,2,3
{B21}1
{B0}1
{B21}2
{B0}2
{B21}3
{B0}3
{SDO-0}1,2,3
{SDI}HOST
{D21}1
{D0}1
{D21}2
{D0}2
{D21}3
{D0}3
Figure 93. Three-Device, Star Connection Timing
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7.6 Register Maps
7.6.1 Device Configuration and Register Maps
The device features nine configuration registers, mapped as described in Table 10.
Table 10. Configuration Registers Mapping
ADDRESS
004h
REGISTER NAME
PD_CNTL
REGISTER DESCRIPTION
Low-power modes control
008h
SDI_CNTL
SDI input protocol selection
00Ch
010h
SDO_CNTL
DATA_CNTL
PATN_LSB
PATN_MID
PATN_MSB
OFST_CAL
REF_MRG
SDO output protocol selection
Output data word configuration
Eight least significant bits (LSB) of the output pattern
Eight middle bits of the output pattern
Four most significant bits (MSB) of the output pattern
Offset calibration
014h
015h
016h
020h
030h
Reference margin
7.6.1.1 PD_CNTL Register (address = 04h) [reset = 00h]
This register controls the low-power modes offered by the device.
Figure 94. PD_CNTL Register
7
0
6
0
5
0
4
0
3
0
2
1
0
0
PD_REFBUF
R/W-0b
PD_ADC
R/W-0b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. PD_CNTL Register Field Descriptions
Bit
7-3
2
Field
Type
R
Reset
00000b
0b
Description
0
Reserved bits. Reads return 00000b.
PD_REFBUF
R/W
This bit powers down the internal reference buffer.
0b = Internal reference buffer is powered up
1b = Internal reference buffer is powered down
1
PD_ADC
R/W
0b
This bit powers down the converter module.
0b = converter module is powered up
1b = converter module is powered down
0
0
R
0b
Reserved bits. Do not write. Reads return 0b.
To power-down the converter module, set the PD_ADC bit in the PD_CNTL register. The converter module
powers down on the rising edge of CS. To power-up the converter module, reset the PD_ADC bit in the
PD_CNTL register. The converter module starts to power-up on the rising edge of CS. Wait for tPU_ADC before
initiating any conversion or data transfer operation.
To power-down the internal reference buffer, set the PD_REFBUF bit in the PD_CNTL register. The internal
reference buffer powers down on the rising edge of CS. To power-up the internal reference buffer, reset the
PD_REFBUF bit in the PD_CNTL register. The internal reference buffer starts to power-up on the rising edge of
CS. Wait for tPU_REFBUF before initiating any conversion.
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7.6.1.2 SDI_CNTL Register (address = 008h) [reset = 00h]
This register selects the SPI protocol for writing data to the device.
Figure 95. SDI_CNTL Register
7
0
6
0
5
0
4
0
3
0
2
0
1
0
SDI_MODE[1:0]
R/W-00b
R-0b
R-0b
R-0b
R-0b
R-0b
R-0b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. SDI_CNTL Register Field Descriptions
Bit
7-2
1-0
Field
Type
R
Reset
Description
0
000000b Reserved bits. Do not write. Reads return 000000b.
SDI_MODE[1:0]
R/W
00b
These bits select the protocol for writing data into the device.
00b = Standard SPI with CPOL = 0 and CPHASE = 0
01b = Standard SPI with CPOL = 0 and CPHASE = 1
10b = Standard SPI with CPOL = 1 and CPHASE = 0
11b = Standard SPI with CPOL = 1 and CPHASE = 1
7.6.1.3 SDO_CNTL Register (address = 0Ch) [reset = 00h]
This register configures the protocol for reading data from the device.
Figure 96. SDO_CNTL Register
7
6
5
0
4
3
2
1
0
SDO_MODE[1:0]
R/W-00b
SSYNC_CLK_SEL[1:0]
R/W-00b
DATA_RATE
R/W-0b
SDO_WIDTH[1:0]
R/W-00b
R-0b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. SDO_CNTL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
SSYNC_CLK_SEL[1:0]
R/W
00b
These bits select the source and frequency of the clock for the ADC-
Clock-Master mode, and are valid only if SDO_MODE[1:0] = 11b.
00b = External SCLK echo
01b = Internal clock (INTCLK)
10b = Internal clock / 2 (INTCLK / 2)
11b = Internal clock / 4 (INTCLK / 4)
5
4
0
R
0b
0b
Reserved bit. Do not write. Reads return 0b.
DATA_RATE
R/W
This bit is ignored if SDO_MODE[1:0] = 00b. When SDO_MODE[1:0] =
11b:
0b = SDOs are updated at single data rate (SDR) with respect to the
output clock
1b = SDOs are updated at double data rate (DDR) with respect to the
output clock
3-2
1-0
SDO_WIDTH[1:0]
SDO_MODE[1:0]
R/W
R/W
00b
00b
These bits set the width of the output bus.
0xb = Data are output only on SDO-0
10b = Data are output only on SDO-0 and SDO-1
11b = Data are output on SDO-0, SDO-1, SDO-2, and SDO-3
These bits select the protocol for reading data from the device.
00b = SDO follows the SPI protocol selected in the SDI_CNTL register
01b = SDO follows the SPI protocol selected in the SDI_CNTL register
but with Early Data Launch feature enabled. See Table 6.
10b = Invalid configuration, not supported by the device
11b = SDO follows the source-synchronous protocol
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7.6.1.4 DATA_CNTL Register (address = 010h) [reset = 00h]
This register configures the contents of the 22-bit output data word (D[21:0]).
Figure 97. DATA_CNTL Register
7
0
6
0
5
0
4
0
3
2
1
0
FPAR_LOC[1:0]
R/W-00b
PAR_EN
R/W-0b
DATA_VAL
R/W-0b
R-0b
R-0b
R-0b
R-0b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. DATA_CNTL Register Field Descriptions
Bit
7-4
3-2
Field
Type
R
Reset
0000b
00b
Description
0
Reserved bits. Reads return 0000b.
FPAR_LOC[1:0]
R/W
These bits control the data span for calculating the FTPAR bit (bit D[4] in
the output data word).
00b = D[4] reflects even parity calculated for 4 MSB
01b = D[4] reflects even parity calculated for 8 MSB
10b = D[4] reflects even parity calculated for 12 MSB
11b = D[4] reflects even parity calculated for all 16 bits (that is, the same
as FLPAR)
1
0
PAR_EN
R/W
R/W
0b
0b
0b = Output data does not contain any parity information
D[5] = 0
D[4] = 0
1b = Parity information is appended to the LSB of the output data
D[5] = Even parity calculated on bits D[21:6]
D[4] = Even parity computed on selected number of MSB of D[21:6]
as per FPAR_LOC[1:0] setting
See Figure 44 for further details of parity computation.
DATA_VAL
These bits control bits D[21:6] of the output data word.
0b = 16-bit conversion output
1b = 16-bit contents of the fixed-pattern registers
See PATN CNTL for more details.
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7.6.1.5 PATN_LSB Register (address = 014h) [reset = 00h]
This register controls the eight LSB of the output pattern when DATA_VAL = 1b; see Figure 101.
Figure 98. PATN_LSB Register
7
6
5
4
3
2
1
0
PATN_LSB_BITS
R/W-00000000b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. PATN_LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PATN_LSB_BITS
R/W
00000000b
8 LSB of the output pattern
7.6.1.6 PATN_MID Register (address = 015h) [reset = 00h]
This register controls the middle eight bits of the output pattern when DATA_VAL = 1b; see Figure 101.
Figure 99. PATN_MID Register
7
6
5
4
3
2
1
0
PATN_MID_BITS
R/W-00000000b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. PATN_MID Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PATN_MID_BITS
R/W
00000000b
8 middle bits of the output pattern
7.6.1.7 PATN_MSB Register (address = 016h) [reset = 00h]
This register controls the four MSB of the output pattern when DATA_VAL = 1b; see Figure 101.
Figure 100. PATN_MSB Register
7
0
6
0
5
0
4
0
3
2
1
0
PATN_MSB_BITS
R/W-0000b
R-0b
R-0b
R-0b
R-0b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. PATN_MSB Register Field Descriptions
Bit
7-4
3-0
Field
Type
R
Reset
0000b
0000b
Description
0
Reserved bits. Reads return 0000b.
4 MSB of the output pattern
PATN_MSB_BITS
R/W
16-bit pattern
DATA_PATN[15:0]
P15
P12
P11
P4
P3
P0
PATN_MSB[3:0]
4-bits
PATN_MID[7:0]
8-bits
PATN_LSB[7:4]
4-bits
Figure 101. DATA_PATN[15:0]
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7.6.1.8 OFST_CAL Register (address = 020h) [reset = 00h]
This register selects the external reference range for optimal offset calibration.
Figure 102. OFST_CAL Register
7
0
6
0
5
0
4
0
3
0
2
1
0
REF_SEL[2:0]
R/W-000b
R-0b
R-0b
R-0b
R-0b
R-0b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. OFST_CAL Register Field Descriptions
Bit
7-3
2-0
Field
Type
R
Reset
00000b
000b
Description
0
Reserved bits. Reads return 00000b.
REF_SEL[2:0]
R/W
These bits select the external reference range for optimal offset.
000b = Optimum offset calibration for VREF = 5.0 V
001b = Optimum offset calibration for VREF = 4.5 V
010b = Optimum offset calibration for VREF = 4.096 V
011b = Optimum offset calibration for VREF = 3.3 V
100b = Optimum offset calibration for VREF = 3.0 V
101b = Optimum offset calibration for VREF = 2.5 V
110b = Optimum offset calibration for VREF = 5.0 V
111b = Optimum offset calibration for VREF = 5.0 V
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7.6.1.9 REF_MRG Register (address = 030h) [reset = 00h]
This register selects the margining to be added to or subtracted from the reference buffer output; see the
Reference Buffer Module section.
Figure 103. REF_MRG Register
7
0
6
0
5
4
3
2
1
0
EN_MARG
R/W-0b
REF_OFST[4:0]
R/W-00000b
R-0b
R-0b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19. REF_MRG Register Field Descriptions
Bit
7-6
5
Field
Type
R
Reset
00b
0b
Description
0
Reserved bits. Reads return 00b.
EN_MARG
R/W
This bit enables margining feature.
0b = Margining is disabled
1b = Margining is enabled
4-0
REF_OFST[4:0]
R/W
00000b
These bits select the reference offset value as per Table 20.
Table 20. REF_OFST[4:0] settings
REF_OFST[4:0]
ΔVREFBUFOUT (typical(1)
0 mV
)
00000b
00001b
00010b
00011b
00100b
00101b
00110b
00111b
01000b
01001b
01010b
01011b
01100b
01101b
01110b
01111b
10000b
10001b
10010b
10011b
10100b
10101b
10110b
10111b
11000b
11001b
11010b
11011b
11100b
11101b
11110b
11111b
280 µV
580 µV
840 µV
1.12 mV
1.4 mV
1.68 mV
1.96 mV
2.24 mV
2.52 mV
2.8 mV
3.08 mV
3.36 mV
3.64 mV
3.92 mV
4.2 mV
–4.5 mV
–4.22 mV
–3.94 mV
–3.66 mV
–3.38 mV
–3.1 mV
–2.82 mV
–2.54 mV
–2.26 mV
–1.98 mV
–1.7 mV
–1.42 mV
–1.14 mV
–860 µV
–580 µV
–280 µV
(1) The actual VREFBUFOUT value may vary by ±10% from Table 20
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The two primary circuits required to maximize the performance of a high-precision, successive approximation
register (SAR), analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This
section presents general principles for designing these circuits, followed by an application circuit designed using
the ADS892xB.
8.1.1 ADC Reference Driver
The external reference source must provide low-drift and very accurate voltage at the REFIN pin of the
ADS892xB. The output broadband noise of most references can be in the order of a few hundred μVRMS
.
Therefore, to prevent any degradation in the noise performance of the ADC, appropriately filter the output of the
voltage reference by using a low-pass filter with a cutoff frequency of a few hundred hertz.
The internal reference buffer of the ADS892xB provides the dynamic load posed on the REFBUFOUT pin during
the conversion process. Decouple the REFBUFOUT pin with the REFM pin using the recommended CREFBUF and
RESR. See the Layout section for layout recommendations.
8.1.2 ADC Input Driver
The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and a charge
kickback filter. The amplifier is used for signal conditioning of the input signal and the low output impedance of
the amplifier provides a buffer between the signal source and the switched capacitor inputs of the ADC. The
charge kickback filter helps attenuate the sampling charge injection from the switched-capacitor input stage of
the ADC, and band-limits the wideband noise contributed by the front-end circuit. Careful design of the front-end
circuit is critical to meet the linearity and noise performance of the ADS892xB.
8.1.2.1 Charge-Kickback Filter
The charge-kickback filter is an RC filter at the input pins of the ADC that filters the broadband noise from the
front-end drive circuitry, and attenuates the sampling charge injection from the switched-capacitor input stage of
the ADC. A filter capacitor, CFLT, is connected from each input pin of the ADC to the ground (as shown in
Figure 104). This capacitor helps reduce the sampling charge injection and provides a charge bucket to quickly
charge the internal sample-and-hold capacitors during the acquisition process. Generally, the value of this
capacitor must be at least 20 times the specified value of the ADC sampling capacitance. For the ADS892xB, the
input sampling capacitance is equal to 60 pF; therefore, for optimal performance, keep CFLT greater than 1.2 nF.
This capacitor must be a COG- or NPO-type. The type of dielectric used in COG or NPO ceramic capacitors
provides the most stable electrical properties over voltage, frequency, and temperature changes.
RFLT
2.2 ꢀ
CFLT
10 nF
ADS89xxB
RFLT
2.2 ꢀ
CFLT
10 nF
Figure 104. Charge Kickback Filter Configuration
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Application Information (continued)
Driving capacitive loads can degrade the phase margin of the input amplifier, thus making the amplifier
marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of
the amplifiers. A higher value of RFLT helps with amplifier stability, but adds distortion as a result of interactions
with the nonlinear input impedance of the ADC. Distortion increases with source impedance, input signal
frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability of the
driver amplifier and distortion performance of the design. Always verify the stability and settling behavior of the
driving amplifier and charge-kickback filter by TINA-TI™ SPICE simulation. Keep the tolerance of the selected
resistors less than 1% to keep the inputs balanced.
8.1.2.2 Input Amplifier Selection
Selection criteria for the input amplifiers is highly dependent on the input signal type, as well as the performance
goals, of the data acquisition system. Some key amplifier specifications to consider when selecting an
appropriate amplifier to drive the inputs of the ADC are:
•
Small-signal bandwidth. Select the small-signal bandwidth of the input amplifiers to be as high as possible
after meeting the power budget of the system. Higher bandwidth reduces the closed-loop output impedance
of the amplifier, thus allowing the amplifier to more easily drive the ADC sample-and-hold capacitor and the
RC filter (Charge-Kickback Filter) at the inputs of the ADC. Higher bandwidth amplifiers offer faster settling
times while driving the capacitive load of the charge-kickback filter, thus reducing harmonic distortion at
higher input frequencies. In order to maintain the overall stability of the input driver circuit, select the amplifier
with a unity gain bandwidth (UGB) as described in Equation 16:
≈
∆
«
’
÷
◊
1
UGB í 4 ì
2p
ì RFLT ì CFLT
(16)
•
•
Distortion. Both the ADC and the input driver introduce distortion in a data acquisition block. To make sure
that the distortion performance of the data acquisition system is not limited by the front-end circuit, the
distortion of the input driver must be at least 10 dB less than the distortion of the ADC, as shown in
Equation 17.
THDAMP Ç THDADC - 10
dB
(17)
Noise. Noise contribution of the front-end amplifiers must be as low as possible to prevent any degradation in
SNR performance of the system. Generally, to make sure that the noise performance of the data acquisition
system is not limited by the front-end circuit, the total noise contribution from the front-end circuit must be
kept below 20% of the input-referred noise of the ADC. Noise from the input driver circuit is band-limited by
designing a low cutoff frequency, charge-kickback filter, as explained in Equation 18.
2
SNR
(
dB
)
≈
∆
’
÷
V
≈
∆
’
÷
-
1
_ AMP_PP
p
2
1
5
VREF
2
20
+ en2_RMS
ì
ì f-3dB
Ç
ì
ì10
f
«
◊
NG ì 2 ì
∆
∆
÷
÷
6.6
«
◊
where:
•
•
•
•
V1 / f_AMP_PP is the peak-to-peak flicker noise in µV
en_RMS is the amplifier broadband noise density in nV/√Hz
f–3dB is the 3-dB bandwidth of the charge-kickback filter
NG is the noise gain of the front-end circuit that is equal to 1 in a buffer configuration
(18)
•
Settling Time. For dc signals with fast transients that are common in a multiplexed application, the input signal
must settle within an 16-bit accuracy at the device inputs during the acquisition time window. This condition is
critical to maintain the overall linearity performance of the ADC. Typically, amplifier data sheets specify the
output settling performance only up to 0.1% to 0.001%, which may not be sufficient for the desired 16-bit
accuracy. Therefore, always verify the settling behavior of the input driver by TINA-TI SPICE simulations
before selecting the amplifier.
Copyright © 2016–2017, Texas Instruments Incorporated
59
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ADS8922B
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8.2 Typical Application
8.2.1 Data Acquisition (DAQ) Circuit for Lowest Distortion and Noise Performance With Differential Input
ADS89xxB
5 V
1 kꢁ
REFBUFOUT
REFIN
VIN
VOUT
BUF
REF5045
0.1 ꢁ
10 ꢀF
1 ꢀF
10 ꢀF
0.1 ꢁ
22 ꢀF
GND
REFM
5 V
RVDD
1 nF
1 ꢀF
1 ꢀF
1 kꢁ
DECAP
LDO
5 V
1 kꢁ
2.2 ꢁ
10 nF
10 nF
VCM
1.12 V
OPA2625
ADC
2.2 ꢁ
GND
1 kꢁ
1 kꢁ
1 nF
Figure 105. Differential-Input DAQ Circuit for Lowest Distortion and Noise Using the ADS892xB
8.2.1.1 Design Requirements
For this example, the design parameters are listed in Table 21.
Table 21. Design Parameters
DESIGN PARAMETER
ADC sample rate
Input signal
EXAMPLE VALUE
Maximum-specified throughput
2-kHz input, 4.5-VPP fully differential
> 96-dB
Noise performance, SNR
Distortion, THD
Linearity, INL
< –120-dB
< ±0.5-LSB
Reference
4.5 V
Power supply
< 5.5-V analog, 3.3-V I/O
8.2.1.2 Detailed Design Procedure
The application circuit is illustrated in Figure 105. For simplicity, power-supply decoupling capacitors are not
shown in these circuit diagrams; see the Power-Supply Recommendations section for suggested guidelines.
The reference voltage of 4.5 V is generated by the high-precision, low-noise REF5045 circuit. The output
broadband noise of the reference is heavily filtered by a low-pass filter with a 3-dB cutoff frequency of 16 Hz.
60
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ADS8920B
ADS8922B
ADS8924B
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Generally, the distortion from the input driver must be at least 10 dB less than the ADC distortion. The low-power
OPA2625 (a high-bandwidth, low-distortion, high-precision amplifier in an inverting gain configuration) as an input
driver provides exceptional ac performance because of its extremely low-distortion and high-bandwidth
specifications. The distortion resulting from variation in the common-mode signal is eliminated by using the
OPA2625 in an inverting gain configuration. To exercise the complete dynamic range of the device, the common-
mode voltage at the ADS892xB inputs is established at a value of 2.25 V (4.5 V / 2) by using the noninverting
pins of the OPA2625 amplifiers. In addition, the components of the charge kickback filter keep the noise from the
front-end circuit low without adding distortion to the input signal.
For a complete schematic, see the ADS8920BEVM-PDK user's guide located in the ADS8920B SAR Analog to
Digital Converter Evaluation Module web folder at www.ti.com.
A similar circuit is used in reference design TIPD211, a step-by-step process to design a 20-Bit, 1-MSPS, 4-Ch
Small Form Factor Design for Test and Measurement Applications using four ADS8900B SAR ADCs, four
OPA2625 precision amplifiers and one REF5050 precision reference.
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to TI Precision Design TIPD211, 18-Bit, 1-MSPS, 4-Ch Small Form Factor Design for Test and
Measurement Applications (TIDUBW7).
8.2.1.3 Application Curves
0
-50
0.5
0.25
0
-100
-150
-200
-0.25
-0.5
-32768
32767
0
100
200
300
400
500
ADC Output Code
fIN, Input Frequency (kHz)
D002
D011
16-bit NMC DNL, ±0.2-LSB INL
96.2-dB SNR, –124-dB THD
Figure 106. Typical Linearity
Figure 107. Noise-Performance FFT Plot - ADS8920B
0
-50
0
-50
-100
-150
-200
-100
-150
-200
0
50
100
150
200
250
0
25
50
75
100
125
fIN, Input Frequency (kHz)
fIN, Input Frequency (kHz)
D029
D030
96.2-dB SNR, –124-dB THD
96.2-dB SNR, –124-dB THD
Figure 108. Noise-Performance FFT Plot - ADS8922B
Figure 109. Noise-Performance FFT Plot - ADS8924B
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8.2.2 DAQ Circuit With FDA Input Driver and Single-Ended or Differential Input
ADS89xxB
5 V
1 kꢁ
REFBUFOUT
REFIN
VIN
VOUT
BUF
REF5045
0.1 ꢁ
10 ꢀF
1 ꢀF
10 ꢀF
0.1 ꢁ
GND
22 ꢀF
REFM
5 V
RVDD
1 nF
1 ꢀF
1 ꢀF
DECAP
1 kꢁ
LDO
1 kꢁ
VOCM
2.2 ꢁ
10 ꢁ
5 V
THS4551
10 nF
ADC
1 kꢁ
2.2 ꢁ
GND
10 ꢁ
1 kꢁ
Copyright © 2017, Texas Instruments Incorporated
1 nF
Figure 110. DAQ Circuit With FDA Input Driver and Differential Input
ADS89xxB
5 V
1 kꢁ
REFBUFOUT
REFIN
VIN
REF5045
GND
VOUT
BUF
0.1 ꢁ
10 ꢀF
1 ꢀF
10 ꢀF
0.1 ꢁ
22 ꢀF
REFM
5 V
RVDD
1 ꢀF
1 ꢀF
1 nF
1 kꢁ
DECAP
LDO
1 kꢁ
VOCM
2.2 ꢁ
10 ꢁ
5 V
THS4551
10 nF
ADC
1 kꢁ
2.2 ꢁ
GND
10 ꢁ
1 kꢁ
Copyright © 2017, Texas Instruments Incorporated
1 nF
Figure 111. DAQ Circuit With FDA Input Driver and Single-Ended Input
8.2.3 Design Requirements
For this example, the design parameters are listed in Table 22.
62
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ADS8922B
ADS8924B
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ZHCSFE1B –JUNE 2016–REVISED AUGUST 2017
Table 22. Design Parameters
DESIGN PARAMETER
ADC sample rate
Input signal
EXAMPLE VALUE
Maximum-specified throughput
2-kHz input, ±4.5-VPP fully differential and ±4.5-VPP single-ended bipolar signal
Noise performance, SNR
Distortion, THD
Linearity, INL
> 96-dB
< –120-dB
< ±0.5-LSB
Reference
4.5 V
Power supply
< 5.4-V analog, 3.3-V I/O
8.2.4 Detailed Design Procedure
The application circuits are shown in Figure 110 and Figure 111. In both applications, the input signal is
processed through a high-bandwidth, low-distortion, fully-differential amplifier (FDA) designed in a gain of 1 V/V
and a low-pass RC filter before going to the ADC.
The reference voltage of 4.5 V generated by the high-precision, low-noise REF5045 circuit. The output
broadband noise of the reference is heavily filtered by a low-pass filter with a 3-dB cutoff frequency of 16 Hz.
Generally, the distortion from the input driver must be at least 10 dB less than the ADC distortion. The distortion
resulting from variation in the common-mode signal is eliminated by using the FDA in an inverting gain
configuration that establishes a fixed common-mode level for the circuit. This configuration also eliminates the
requirement of a rail-to-rail swing at the amplifier input. Therefore, these circuits use the low-power THS4551 as
an input driver that provides exceptional ac performance because of its extremely low-distortion and high
bandwidth specifications. In addition, the components of the charge kickback filter keep the noise from the front-
end circuit low without adding distortion to the input signal.
The circuit in Figure 110 shows a fully-differential data acquisition (DAQ) block optimized for low distortion and
noise using the THS4551 and ADS892xB. This front-end circuit configuration requires a differential signal at the
input of the FDA and provides a differential output to drive the ADC inputs. The common-mode voltage of the
input signal provided to the ADC is set by the VOCM pin of the THS4551 (not shown in Figure 110). To use the
complete dynamic range of the ADC, VOCM can be set to VREF / 2 by using a simple resistive divider.
The circuit in Figure 111 shows a single-ended to differential DAQ block optimized for low distortion and noise
using the THS4551 and the ADS892xB. This front-end circuit configuration requires a single-ended bipolar signal
at the input of the FDA and provides a fully-differential output to drive the ADC inputs. The common-mode
voltage of the input signal provided to the ADC is set by the VOCM pin of the THS4551 (not shown in Figure 111).
To use the complete dynamic range of the ADC, VOCM can be set to VREF / 2 by using a simple resistive divider.
8.2.5 Application Curves
0.5
0.25
0
0.5
0.25
0
-0.25
-0.25
-0.5
-0.5
-32768
32767
-32768
32767
ADC Output Code
ADC Output Code
D031
D032
±0.15-LSB INL
±0.15-LSB INL
Figure 112. Typical Linearity, Differential Input
Figure 113. Typical Linearity, Single-Ended Input
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0
0
-50
-50
-100
-150
-200
-100
-150
-200
0
100
200
300
400
500
0
100
200
300
400
500
fIN, Input Frequency (kHz)
fIN, Input Frequency (kHz)
D033
D034
SNR = 96.1 dB, THD = –131.7 dB
SNR = 95.9 dB, THD = –125.9 dB
Figure 114. Noise-Performance FFT Plot: ADS8920B,
Differential Input
Figure 115. Noise-Performance FFT Plot: ADS8920B,
Single-Ended Input
0
0
-50
-100
-150
-200
-50
-100
-150
-200
0
50
100
150
200
250
0
50
100
150
200
250
fIN, Input Frequency (kHz)
fIN, Input Frequency (kHz)
D035
D036
SNR = 96.2 dB, THD = –132 dB
SNR = 96 dB, THD = –126 dB
Figure 116. Noise-Performance FFT Plot: ADS8922B,
Differential Input
Figure 117. Noise-Performance FFT Plot: ADS8922B,
Single-Ended Input
0
0
-50
-100
-150
-200
-50
-100
-150
-200
0
25
50
75
100
125
0
25
50
75
100
125
fIN, Input Frequency (kHz)
fIN, Input Frequency (kHz)
D037
D038
SNR = 96.1 dB, THD = –131.5 dB
SNR = 95.9 dB, THD = –125.6 dB
Figure 118. Noise-Performance FFT Plot: ADS8924B,
Differential Input
Figure 119. Noise-Performance FFT Plot: ADS8924B,
Single-Ended Input
64
Copyright © 2016–2017, Texas Instruments Incorporated
ADS8920B
ADS8922B
ADS8924B
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ZHCSFE1B –JUNE 2016–REVISED AUGUST 2017
9 Power-Supply Recommendations
The devices have two separate power supplies: RVDD and DVDD. The internal reference buffer and the internal
LDO operate on RVDD. The ADC core operates on the LDO output (available on the DECAP pins). DVDD is used
for the interface circuits. RVDD and DVDD can be independently set to any value within their permissible ranges.
During normal operation, if RVDD supply drops below the RVDD minimum specification, ramp the RVDD supply
down to ≤ 0.7 V before power-up. During power-up, RVDD must rise monotonically to the recommended minimum
operating voltage.
The RVDD supply voltage value defines the permissible range for the external reference voltage VREF on REFIN
pin as:
2.5 V ≤ VREF ≤ (RVDD – 0.3) V
(19)
Place a 10-µF decoupling capacitor between the RVDD and GND pins, and between the DVDD and GND pins,
as shown in Figure 120. Use a minimum 1-µF decoupling capacitor between the DECAP pins and the GND pin.
ADS89xxB
RVDD
BUF
RVDD
DECAP
LDO
DVDD
10 ꢀF
1 ꢀF
ADC
DVDD
10 µF
GND
Figure 120. Power-Supply Decoupling
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ADS8922B
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ZHCSFE1B –JUNE 2016–REVISED AUGUST 2017
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
This section provides some layout guidelines for achieving optimum performance with the ADS892xB device
family.
10.1.1 Signal Path
As illustrated in Figure 121, the analog input signals are routed in opposite directions to the digital connections.
The reference decoupling components are kept away from the switching digital signals. This arrangement
prevents noise generated by digital switching activity from coupling to sensitive analog signals.
10.1.2 Grounding and PCB Stack-Up
Low inductance grounding is critical for achieving optimum performance. Grounding inductance is kept below 1
nH with 15-mil grounding vias and a printed circuit board (PCB) layout design that has at least four layers. Place
all critical components of the signal chain on the top layer with a solid analog ground from subsequent inner
layers to minimize via length to ground.
For lowest inductance grounding, connect the GND pins of the ADS892xB (pin 11 and pin 15) directly to the
device thermal pad and place at least four 8-mil grounding vias on the device thermal pad.
10.1.3 Decoupling of Power Supplies
Place the decoupling capacitors on RVDD, the LDO output, and DVDD within 20 mil from the respective pins, and
use a 15-mil via to ground from each capacitor. Avoid placing vias between any supply pin and the respective
decoupling capacitor.
10.1.4 Reference Decoupling
Dynamic currents are also present at the REFBUFOUT and REFM pins during the conversion phase, and
excellent decoupling is required to achieve optimum performance. Place a 10-μF, X7R-grade, ceramic capacitor
with at least 10-V rating and an ESR of 1-Ω between the REFBUFOUT and the REFM pins, as illustrated in
Figure 121. Select 0603- or 0805-size capacitors to keep equivalent series inductance (ESL) low. Connect the
REFM pins to the decoupling capacitor before a ground via.
10.1.5 Differential Input Decoupling
Dynamic currents are also present at the differential analog inputs of the ADS892xB. Use C0G- or NPO-type
capacitors to decouple these inputs because with these type of capacitors, capacitance stays almost constant
over the full input voltage range. Lower-quality capacitors (such as X5R and X7R) have large capacitance
changes over the full input-voltage range that may cause degradation in the performance of the device.
66
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ADS8922B
ADS8924B
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ZHCSFE1B –JUNE 2016–REVISED AUGUST 2017
10.2 Layout Example
REFM
GND
External
Reference
Input
CREFBUF
Reference
Decoupling
RESR
GND
REFIN
REFBUFOUT
RST
1
CONVST
CS
GND
7
GND
GND
SCLK
SDI
AINP
RVS
AINM
GND
SDO-0
SDO-1
19
SDO-2
SDO-3
+
Differential
Analog Input
Digital Inputs
and Outputs
-
GND
Analog Input
GND
GND
GND
Power Supply
Figure 121. Recommended Layout
版权 © 2016–2017, Texas Instruments Incorporated
67
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ADS8922B
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www.ti.com.cn
11 器件和文档支持
11.1 Documentation Support
11.1.1 相关文档
如需相关文档，请参阅：
•
•
•
•
•
•
•
•
•
•
•
•
《ADS8920BEVM-PDK 用户指南》（文献编号：SBAU270）
《通过 TI 的 multiSPI™ 数字接口为 SAR ADC 实现更快、更智能、更强大的系统解决方案》
《超声波 CW 多普勒求和及 20 位真正原始数据转换参考设计》
《适用于测试和测量应用的 20 位、1MSPS、4 通道 接收器 参考设计
《可实现最大 SNR 和采样率的 20 位、1MSPS 隔离器优化数据采集参考设计》
《优化抖动以实现最大 SNR 和采样率的 20 位、1MSPS 隔离式数据采集 (DAQ) 参考设计》
《使用增强型 SPI ADC 接口简化隔离设计》
《优化高分辨率和高吞吐量数据转换器上的数据传输》
《改善精密数据转换器的输入趋稳》
《OPAx625 高带宽、高精度、低 THD+N、16 位和 18 位模数转换器 (ADC) 驱动器数据表》
《REF5050 低噪声、极低漂移、精密电压基准数据表》
《THS4551 低噪声、高精度 150MHz 全差分放大器》
11.2 相关链接
下面的表格中列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即购买的快速链
接。
表 23. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
工具和软件
请单击此处
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
请单击此处
ADS8920B
ADS8922B
ADS8924B
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. 有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
68
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ADS8922B
ADS8924B
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ZHCSFE1B –JUNE 2016–REVISED AUGUST 2017
11.5 商标
multiSPI, TINA-TI, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修
订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
版权 © 2016–2017, Texas Instruments Incorporated
69
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS8920BRGER
ADS8920BRGET
ADS8922BRGER
ADS8922BRGET
ADS8924BRGER
ADS8924BRGET
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGE
RGE
RGE
RGE
RGE
RGE
24
24
24
24
24
24
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
8920B
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
8920B
8922B
8922B
8924B
8924B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS8920BRGER
ADS8920BRGET
ADS8922BRGER
ADS8922BRGET
ADS8924BRGER
ADS8924BRGET
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGE
RGE
RGE
RGE
RGE
RGE
24
24
24
24
24
24
3000
250
330.0
180.0
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
4.25
1.15
1.15
1.15
1.15
1.15
1.15
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS8920BRGER
ADS8920BRGET
ADS8922BRGER
ADS8922BRGET
ADS8924BRGER
ADS8924BRGET
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGE
RGE
RGE
RGE
RGE
RGE
24
24
24
24
24
24
3000
250
346.0
210.0
346.0
210.0
346.0
210.0
346.0
185.0
346.0
185.0
346.0
185.0
33.0
35.0
33.0
35.0
33.0
35.0
3000
250
3000
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGE 24
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
A
4.1
3.9
B
4.1
3.9
PIN 1 INDEX AREA
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
ꢀꢀꢀꢀꢁꢂꢃꢄꢂꢅ
(0.2) TYP
2X 2.5
12
7
20X 0.5
6
13
25
2X
SYMM
2.5
1
18
0.30
PIN 1 ID
(OPTIONAL)
24X
0.18
24
19
0.1
0.05
C A B
C
SYMM
0.48
0.28
24X
4219016 / A 08/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
2.7)
(
24
19
24X (0.58)
24X (0.24)
1
18
20X (0.5)
25
SYMM
(3.825)
2X
(1.1)
ꢆꢄꢂꢁꢇꢀ9,$
TYP
6
13
(R0.05)
7
12
2X(1.1)
SYMM
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219016 / A 08/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGE0024H
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)
4X ( 1.188)
24
19
24X (0.58)
24X (0.24)
1
18
20X (0.5)
SYMM
(3.825)
(0.694)
TYP
6
13
25
(R0.05) TYP
METAL
TYP
7
12
(0.694)
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
78% PRINTED COVERAGE BY AREA
SCALE: 20X
4219016 / A 08/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
www.ti.com
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