ADS9226IRHBT [TI]
具有增强型 SPI 的 16 位、2.048MSPS、双通道、同步采样 SAR ADC | RHB | 32 | -40 to 125;
| 型号： | ADS9226IRHBT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有增强型 SPI 的 16 位、2.048MSPS、双通道、同步采样 SAR ADC | RHB | 32 | -40 to 125 |
| 文件： | 总36页 (文件大小：2163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS9226
ZHCSLM5 –JULY 2020
ADS9226 16 位双通道、低延迟、同步采样SAR ADC
1 特性
3 说明
• 高分辨率、高吞吐量：
ADS9226 是一款 16 位双通道同步采样模数转换器
(ADC)，具有集成式基准缓冲器。该器件可由 5V 单电
源供电运行，支持单极和伪差分模拟输入信号，具有出
色的直流和交流规格。
– 16 位，2.048MSPS
• 低延迟快速响应时间：488ns
• 两个同步采样通道
• 单极伪差分输入
• 出色的直流和交流性能：
该器件支持 SPI 兼容串行（增强型 SPI）接口，因此
易于与多种微控制器、数字信号处理器 (DSP) 和现场
可编程门阵列(FPGA) 搭配使用。
– 16 位，无丢码
– ±2.75LSB 最大INL
该器件采用节省空间的 5mm × 5mm VQFN 封装。
ADS9226 的额定工作温度范围为–40°C 至+125°C。
– 90.8dB SNR，-100dB THD
• 宽模拟电源电压范围：4V 至5.5V
• 集成式基准缓冲器
• SPI 兼容串行接口
• 工作温度范围：–40°C 至+125°C
• 小尺寸：5mm × 5mm VQFN
器件信息(1)
封装尺寸（标称值）
器件型号
ADS9226
封装
VQFN (32)
5.00mm x 5.00mm
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
2 应用
• 伺服驱动器位置反馈
• 伺服驱动器功率级模块
• 电信光模块
• 电能质量分析仪
• 直流/交流电源，电子负载
Absolute/Incremental Encoder
SONAR
Reference
Position
I
ADC
sine
0°
ADC
Baseband
Signal
Host
Host
Encoder
Q
ADC
cosine
ADC
90°
Low Latency SAR
Low Latency SAR
Local Oscillator
典型应用图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBAS842
ADS9226
ZHCSLM5 –JULY 2020
www.ti.com.cn
Table of Contents
7.3 Feature Description...................................................16
7.4 Device Functional Modes..........................................20
8 Application and Implementation..................................22
8.1 Application Information............................................. 22
8.2 Typical Application.................................................... 24
9 Power Supply Recommendations................................26
10 Layout...........................................................................27
10.1 Layout Guidelines................................................... 27
10.2 Layout Example...................................................... 28
11 Device and Documentation Support..........................29
11.1 Related Documentation...........................................29
11.2 Receiving Notification of Documentation Updates..29
11.3 Support Resources................................................. 29
11.4 Trademarks............................................................. 29
11.5 Electrostatic Discharge Caution..............................29
11.6 Glossary..................................................................29
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................6
6.6 Timing Requirements..................................................8
6.7 Switching Characteristics............................................8
6.8 Timing Diagrams.........................................................9
6.9 Typical Characteristics.............................................. 11
7 Detailed Description......................................................15
7.1 Overview...................................................................15
7.2 Functional Block Diagram.........................................15
Information.................................................................... 29
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
July 2020
*
Initial release.
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5 Pin Configuration and Functions
1
24
23
22
21
20
19
18
17
AINP_A
SDO-0A
SDO-1A
2
AINM_A
3
NC
4
GND
Thermal Pad
5
SDO-0B
SDO-1B
REFIN
6
NC
7
AINM_B
8
AINP_B
图5-1. RHB Package, 5-mm × 5-mm, 32-Pin VQFN, Top View
Pin Functions
PIN
NAME
NO.
2
FUNCTION
Analog input
Analog input
Analog input
Analog input
DESCRIPTION
Negative analog input for channel A.
AINM_A
AINM_B
7
Negative analog input for channel B.
Positive analog input for channel A.
Positive analog input for channel B.
AINP_A
1
AINP_B
8
Analog power-supply pin. Short pins 12 and 29 together.
Place a 1-µF decoupling capacitor between pins 11 and 12.
Place a 1-µF decoupling capacitor between pins 29 and 30.
AVDD
CS
12, 29
13, 14
26, 28
Power supply
Digital input
Power supply
Chip-select input pin; active low.
The device takes control of the data bus when CS is low.
The SDO-xy pins go to Hi-Z when CS is high.
Connect these pins together externally with a short trace.
Interface power-supply pin.
Place a 1-µF decoupling capacitor between pins 27 and 26 and pins 27
and 28.
DVDD
4, 11, 15, 27,
30
GND
NC
Power supply
No connection
Device ground.
3, 6, 17, 18,
21, 22, 25
No external connection.
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PIN
NAME
NO.
FUNCTION
DESCRIPTION
Reference voltage for the ADC.
REFIN
5
Analog input
ADC_A negative reference input.
Externally connect to the device GND.
REFM_A
REFM_B
REFP_A
REFP_B
32
9
Analog input
Analog input
Analog output
Analog output
ADC_B negative reference input.
Externally connect to the device GND.
Positive output of reference buffer A. ADC_A positive reference input.
Place a 10-µF decoupling capacitor between pins 31 and 32.
31
10
Positive output of reference buffer B. ADC_B positive reference input.
Place a 10-µF decoupling capacitor between pins 9 and 10.
SCLK
16
24
20
23
19
Digital input
Digital output
Digital output
Digital output
Digital output
Clock input pin for the serial interface.
Data output 0 for channel A.
Data output 0 for channel B.
Data output 1 for channel A.
Data output 1 for channel B.
SDO-0A
SDO-0B
SDO-1A
SDO-1B
Exposed thermal pad. TI recommends connecting this pin to the printed
circuit board (PCB) ground.
Thermal pad
Supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
MAX
6
UNIT
V
AVDD to GND
DVDD to GND
6
V
–0.3
Digital input pins
DVDD + 0.3
DVDD + 0.3
AVDD + 0.3
GND + 0.1
AVDD + 0.3
AVDD + 0.3
10
V
GND –0.3
GND –0.3
–0.3
Digital output pins
V
AINP_A, AINP_B to GND, AINM_A, AINM_B to GND
REFM_A, REFM_B
V
V
GND –0.1
GND –0.3
–0.3
REFP_A, REFP_B to GND
V
Reference input voltage
REFIN to GND
V
Input or output current to any pin except power-supply pin
Junction temperature, TJ
mA
°C
°C
–10
150
Storage temperature, Tstg
150
–65
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER SUPPLY
AVDD
4
1.65
2.35
5
3
3
5.5
5.5
5.5
V
V
Operating
SCLK > 20 MHz
DVDD
EXTERNAL REFERENCE INPUT
External reference
VREFIN
1.4
AVDD/2
V
AVDD/1.75 –0.2
input voltage
ANALOG INPUTS
FSR
Full-scale input range
VREFIN
V
V
–VREFIN
–0.1
Absolute input voltage
AINP_x(1)
VINP_x
AVDD + 0.1
Absolute input voltage
AINM_x(2)
VINM_x
VREFIN
VREFIN + 0.1
V
V
REFIN –0.1
TEMPERATURE RANGE
TA Ambient temperature
25
125
°C
–40
(1) AINP_x refers to AINP_A and AINP_B positive input pins for ADC_A and ADC_B respectively.
(2) AINM_x refers to AINM_A and AINM_B positive input pins for ADC_A and ADC_B respectively.
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UNIT
6.4 Thermal Information
ADS9226
THERMAL METRIC(1)
RHB (VQFN)
32 PINS
29
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
17.1
9.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ΨJT
9.4
ΨJB
RθJC(bot)
0.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
at AVDD = 4 V to 5.5 V, DVDD = 3.3 V, VREFIN = AVDD / 2 and maximum throughput (unless otherwise noted); minimum and
maximum values at TA = –40°C to +125°C; typical values at TA = 25°C and AVDD = 5 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ANALOG INPUT
IIN
Analog input leakage current
±1
16
1
µA
pF
Sample mode
Ci
Input capacitance
Hold mode
52
4.2
–3-dB input signal
–0.1-dB input signal
BW
Analog input bandwidth
MHz
DC ACCURACY
Resolution
No missing codes
16
–0.55
–2.75
–9
bit
DNL
INL
EO
Differential nonlinearity
Integral nonlinearity
Offset error
±0.25
±1
0.55
2.75
9
LSB
LSB
LSB
LSB
±2
Offset error matching
±0.5
ΔEO/
ΔT
Offset error temperature drift
1
ppm/℃
GE
Gain error
±0.01
0.2
0.027 %FSR
%FSR
–0.027
Gain error matching
ΔGE/
ΔT
Gain drift
5
ppm/°C
LSB
Mid code, PFS –1000, NFS +
1000
Transition noise
0.675
AC ACCURACY
fIN = 2 kHz
88
87
90.8
90
SNR
Signal-to-noise ratio
dB
dB
dB
fIN = 100 kHz
fIN = 2 kHz
90.5
89.6
–100
–95
105
SINAD
THD
Signal-to-noise plus distortion
Total harmonic distortion
fIN = 100 kHz
fIN = 2 kHz
fIN = 100 kHz
fIN = 2 kHz
SFDR
Spurious-free dynamic range
Channel to channel isolation
dB
dB
fIN = 100 kHz
100
fIN_ADCA = 15 kHz at 10% FSR
fIN_ADCB = 25 kHz at 100% FSR
ISOXT
–115
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at AVDD = 4 V to 5.5 V, DVDD = 3.3 V, VREFIN = AVDD / 2 and maximum throughput (unless otherwise noted); minimum and
maximum values at TA = –40°C to +125°C; typical values at TA = 25°C and AVDD = 5 V
PARAMETER
INTERNAL REFERENCE BUFFER
GREFBUF Reference buffer gain
TEST CONDITIONS
MIN
TYP
MAX UNIT
1.75
0
V/V
Reference buffer output offset
1
mV
µV/C
µV
–1
(1)
(VREFP_x - VREFIN
)
Reference buffer output offset
temperature drift
10
±50
10
Reference buffer output mismatch
500
27
–500
(VREFP_A - VREFP_B
)
For specified performance, between
each pair of REFP_x and REFM_x
CREFP_x Reference buffer output capacitor
7
µF
DIGITAL INPUTS
VIH
VIL
VIH
VIL
High-level input voltage
Low-level intput voltage
High-level input voltage
Low-level intput voltage
0.7 × DVDD
–0.3
DVDD +0.3
0.3 × DVDD
DVDD +0.3
0.2 × DVDD
V
V
V
V
DVDD > 2.3 V
0.8 × DVDD
–0.3
DVDD ≤2.3 V
DIGITAL OUTPUTS
VOH
VOL
High-level output voltage
Low-level output voltage
IOH = 500-µA source
IOH = 500-µA sink
0.8 × DVDD
0
DVDD
V
V
0.2 × DVDD
POWER SUPPLY
AVDD = 5 V, fDATA = 2.048 MSPS
AVDD = 5 V, no conversion
16.5
9
20
IAVDD
Analog supply current
mA
dB
100-mVp-p ripple on AVDD,
frequency < 100 kHz
PSRR
Power supply rejection ratio
70
(1) REFP_x refers to the REFP_A and REFP_B reference pins for the ADC_A and ADC_B respectively.
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6.6 Timing Requirements
at AVDD = 4 V to 5.5 V, DVDD = 2.35 V to 5.5 V and maximum throughput (unless otherwise noted); minimum and maximum
values at TA = –40°C to +125°C; typical values at TA = 25°C, AVDD = 5 V and DVDD = 3.3 V
MIN
NOM
MAX
UNIT
CONVERSION CONTROL
tCycle
Cycle time
488
ns
kSPS
ns
fSample
tACQ
Sampling rate
2048
Acquisition time
Pulse duration: CS high
Pulse duration: CS low
tCYCLE - 160
tWH_CS
tWL_CS
SPI MODES
fCLK
15
15
ns
ns
Serial clock frequency
32.768
MHz
tCLK
Serial clock time period
1/ fCLK
0.45
0.45
14
tPH_CLK
tPL_CLK
tSU_CSCK
tHT_CKCS
SCLK high time
0.55
0.55
tCLK
tCLK
ns
SCLK low time
Setup time: CS faling to first SCLK capture edge
Delay time: last SCLK launch edge to CS rising
8
ns
6.7 Switching Characteristics
at AVDD = 4 V to 5.5 V, DVDD = 2.35 V to 5.5 V and maximum throughput (unless otherwise noted); minimum and maximum
values at TA = –40°C to +125°C; typical values at TA = 25°C, AVDD = 5 V and DVDD = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CONVERSION
tCONV
Conversion time
422
ns
SPI MODES
tDEN_CSDO
tDZ_CSDO
Delay time: CS falling to data valid on SDO-x
Delay time: CS rising edge to SDO-x tristate
14
13
ns
ns
Delay time: SCLK launch edge to next data valid on
SDO-x
tD_CKDO
16
ns
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6.8 Timing Diagrams
Sample
”N‘
Sample
”N+1‘
tcycle
> tCONV
CAVDD
CS
SCLK
Output Data ADCx
Sample ”N‘
SDO-0x
SDO-1x
CDVDD
Output Data ADCx
Sample ”N‘
图6-1. Conversion Control Latency-0 Data Capture
Sample
”N‘
Sample
”N+1‘
Sample
”N+2‘
tcycle
tWH_CS
tWL_CS
CAVDD
CS
tCLK
SCLK
Output Data ADCx
Sample ”N-1‘
Output Data ADCx
Sample ”N‘
SDO-0x
SDO-1x
CDVDD
Output Data ADCx
Sample ”N-1‘
Output Data ADCx
Sample ”N‘
图6-2. Conversion Control Latency-1 Data Capture
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tCLK
tPL_CK
tPH_CK
CS
SCLK
tD_CKDO
tSU_CSCK
tHT_CKCS
SDO-xy
SCLK
tDEN_CSDO
tDZ_CSDO
SDO-xy
图6-3. SPI-Compatible Serial Interface Timing
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6.9 Typical Characteristics
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREFIN = 2.5 V, and fSample = 2.048 MSPS (unless otherwise noted)
0
-40
0
-40
-80
-80
-120
-160
-200
-120
-160
-200
0
250
500
Frequency (kHz)
750
1000
0
250
500
Frequency (kHz)
750
1000
D001
D002
fIN = 100 kHz, SNR = 90.1 dB, THD = –99.3 dB
图6-4. Typical FFT at fIN = 100 kHz
fIN = 500 kHz, SNR = 90 dB, THD = –90.9 dB
图6-5. Typical FFT at fIN = 500 kHz
95
93
91
89
87
85
95
93
91
89
87
85
-50
0
50
Free-Air Temperature (°C)
100
150
-50
0
50
Free-Air Temperature (°C)
100
150
D004
D005
fIN = 2 kHz
fIN = 2 kHz
图6-6. SNR vs Free-Air Temperature
图6-7. SINAD vs Free-Air Temperature
-98
-100
-102
-104
-106
-108
94
92
90
88
86
84
-50
0
50
Free-Air Temperature (°C)
100
150
0
250
500
Frequency (KHz)
750
1000
D006
D007
fIN = 2 kHz
图6-8. THD vs Free-Air Temperature
图6-9. SNR vs Input Frequency
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6.9 Typical Characteristics (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREFIN = 2.5 V, and fSample = 2.048 MSPS (unless otherwise noted)
93
91
89
87
85
83
-85
-89
-93
-97
-101
-105
0
250
500
Frequency (KHz)
750
1000
0
250
500
Frequency (KHz)
750
1000
D008
D009
图6-10. SINAD vs Input Frequency
图6-11. THD vs Input Frequency
45000
40000
35000
30000
25000
20000
15000
10000
5000
2
1.2
0.4
-0.4
-1.2
-2
0
-40
-7
26 59
Free-Air Temperature (°C)
92
125
D031
-4
-3
-2
-1
0
1
2
3
ADC Code
D010
Standard deviation = 0.65 LSB
图6-13. Offset Error vs Free-Air Temperature
图6-12. DC Input Histogram
0.01
0.005
0
1
0.6
0.2
-0.2
-0.6
-1
-0.005
-0.01
-0.015
-0.02
-40
-7
26 59
Free-Air Temperature (°C)
92
125
D032
-32768
-16384
0
ADC A Code
16384
32768
D022
图6-14. Gain Error vs Free-Air Temperature
图6-15. Typical DNL ADC A
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6.9 Typical Characteristics (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREFIN = 2.5 V, and fSample = 2.048 MSPS (unless otherwise noted)
1
0.6
0.2
-0.2
-0.6
-1
2
1.2
0.4
-0.4
-1.2
-2
-32768
-16384
0
ADC B Code
16384
32768
-32768
-16384
0
ADC A Code
16384
32768
D023
D024
图6-16. Typical DNL ADC B
图6-17. Typical INL ADC A
2
1.2
0.4
-0.4
-1.2
-2
1
0.6
0.2
-0.2
-0.6
-1
DNL Max
DNL Min
-32768
-16384
0
ADC B Code
16384
32768
-50
0
50
Free-Air Temperature (°C)
100
150
D025
D026
图6-18. Typical INL ADC B
图6-19. DNL vs Free-Air Temperature
2
1.2
0.4
-0.4
-1.2
-2
20
16
12
8
INL Max
INL Min
4
0
-50
0
50
Free-Air Temperature (°C)
100
150
0
512
1024
fsample (kSPS)
1536
2048
D027
D028
图6-20. INL vs Free-Air Temperature
图6-21. Dynamic AVDD Current vs Sampling Rate
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6.9 Typical Characteristics (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, VREFIN = 2.5 V, and fSample = 2.048 MSPS (unless otherwise noted)
20
19
18
17
16
15
10
9
8
7
6
5
-50
0
50
Free-Air Temperature (°C)
100
150
-50
0
50
Free-Air Temperature (°C)
100
150
D029
D030
图6-22. Dynamic AVDD Current vs Free-Air Temperature
图6-23. Static AVDD Current vs Free-Air Temperature
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7 Detailed Description
7.1 Overview
The ADS9226 is a 16-bit, dual-channel, high-speed, simultaneous-sampling, analog-to-digital converter (ADC).
The device supports pseudo-differential input signals and a full-scale range equal to 2 × VREFIN
.
When a conversion is initiated, the difference between the AINP_x and AINM_x pins is sampled on the internal
capacitor array. The device uses an internal clock to perform conversions. During the conversion process, both
analog inputs are disconnected from the internal circuit. At the end of the conversion process, the device
reconnects the sampling capacitors to the AINP_x and AINM_x pins and enters an acquisition phase. The device
includes reference buffers to provide the charge required by the ADCs during conversion.
The device includes a traditional serial programming interface (SPI)-compatible serial interface to interface with a
variety of microcontrollers, digital signal processors (DSPs), and field-programmable gate arrays (FPGAs).
7.2 Functional Block Diagram
REFM_A
REFP_A
REFIN
DVDD
AVDD
REFBUF_A
AINP_A
AINM_A
CS
ADC_A
SCLK
AVDD
Serial
Interface
SDO-0A
AINP_B
AINM_B
ADC_B
SDO-1B
AVDD
REFIN
REFBUF_B
REFM_B
REFP_B
GND
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7.3 Feature Description
From a functional perspective, the device is comprised of five modules: two converters (ADC_A, ADC_B), two
reference buffers (REFBUF_A, REFBUF_B), and the serial interface, as illustrated in 节7.2.
The converter module samples and converts the analog input into an equivalent digital output code. The
reference buffers provide the charge required by the converters for the conversion process. The serial interface
module facilitates communication and data transfer between the device and the host controller.
7.3.1 Converter Modules
As shown in 图 7-1, both converter modules sample the analog input signal (provided between the AINP_x and
AINM_x pins), compare this signal with the reference voltage (between the pair of REFP_x and REFM_x pins),
and generate an equivalent digital output code. The converter modules receive the CS input from the interface
module, and output the ADCST signal and the conversion result back to the interface module.
REFP_x
DVDD
AVDD
OSC
CS
SCLK
AINP_x
AINM_x
CONVST
ADCST
Sample-
and-Hold
Circuit
SDO-0A
Interface
Module
Conversion
Result
SDO-1B
AGND
ADC_A
ADC_B
GND
REFM_x
图7-1. Converter Modules
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7.3.1.1 Analog Input With Sample-and-Hold
This device supports unipolar, pseudo-differential analog input signals. 图 7-2 shows a small-signal equivalent
circuit of the sample-and-hold circuit. Each sampling switch is represented by a resistance (RS1 and RS2,
typically 120 Ω) in series with an ideal switch (SW1 and SW2). The sampling capacitors, CS1 and CS2, are
typically 16 pF.
RS1
SW1
AINP_x
1 pF
1 pF
CS1
AVDD
CS2
GND
GND
RS2
SW2
AINM_x
Device in Hold Mode
图7-2. Analog Input Structure for Converter Module
During the acquisition process, both inputs are individually sampled on CS1 and CS2, respectively. During the
conversion process, both converters convert for the respective voltage difference between the sampled values:
V
AINP_x –VINM_x.
Equation 1 and Equation 2 provide the full-scale input range (FSR) and bias voltage (VBIAS) at the negative
input), supported at the analog inputs for the reference voltage (VREFIN) on the REFIN pin.
FSR = ±VREFIN = 2 × VREFIN
VBIAS = VREFIN ± 0.1 V
(1)
(2)
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7.3.1.2 ADC Transfer Function
This device supports unipolar, pseudo-differential input signals. The device output is in two's complement format.
图 7-3 and 表 7-1 show the ideal transfer characteristics for the device. Equation 3 gives the least significant bit
(LSB) for the ADC.
1 LSB = FSR / 2n
(3)
where
• FSR is defined in 方程式1
• n = Resolution of the device
PFSC
MC
NFSC
A
B
C
VIN
Analog Input
(AINP_x œ AINM_x)
图7-3. Ideal Transfer Characteristics
表7-1. Transfer Characteristics
INPUT VOLTAGE
(AINP_x-AINM_x)
IDEAL OUTPUT CODE
(R = 16)
STEP
CODE
DESCRIPTION
A
B
C
NFSC
MC
Negative full-scale code
Mid code
8000
0000
7FFF
≤–(VREF –0.5 LSB)
–0.5 LSB to 0.5 LSB
≥(VREF –1.5 LSB)
PFSC
Positive full-scale code
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7.3.2 External Reference Voltage
The device requires an external reference voltage of the value VREFIN, as specified in 节 6. 图 7-4 shows the
connections for using the device with an external reference. A reference without an integrated buffer can be
used because of the high input impedance of the REFIN pin.
AVDD
œ
REFP_x
REFBUF_x
External
+
Reference
Voltage
REFIN
CFLT
CREFBUF
REFM_x
GND
图7-4. Connection Diagram for Reference and Reference Buffers
7.3.3 Reference Buffers
On the CS rising edge, both converters start converting the sampled value on the analog input, and the internal
capacitors are switched to the REFP_x pins. Most of the switching charge required during the conversion
process is provided by the external decoupling capacitor CREFP_x. If the charge lost from CREFP_x is not
replenished before the next CS rising edge, the subsequent conversion occurs with this different reference
voltage and causes a proportional error in the output code. To eliminate these errors, the internal reference
buffers of the device maintains the voltage on the REFP_x pins.
All performance characteristics of the device are specified with the internal reference buffer and a specified value
of CREFP_x. As shown in 图 7-4, place a decoupling capacitor CREFP_x between the REFP_x pins and the
REFM_x pin as close to the device as possible.
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7.4 Device Functional Modes
This device supports two functional states: acquisition phase (ACQ) and conversion phase (CNV).
7.4.1 ACQ State
In ACQ state, the device acquires the analog input signal. The device enters ACQ state at power-up, when
coming out of power down and by the ADCST signal (internal). A CS rising edge takes the device from ACQ
state to CNV state.
7.4.2 CNV State
The device moves from ACQ state to CNV state and starts conversion on a rising edge of the CS pin. The
conversion process uses an internal clock. The host must provide a minimum time of tCYCLE between two
subsequent start of conversions.
7.4.3 Output Data Word
The output data word consists of a conversion result of N bits where N = 16 for the ADS9226. The output data
word D[N-1:0], as shown in 图7-5, is left-justified and split into two data lines (SDO-xy) for each ADC.
SCLK
1
2
8
9
0
SDO-1x
D15
D13
D1
SDO-0x
D14
D12
D0
0
For ADC_A, x = A. For ADC_B, x = B.
图7-5. Output Data Word
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7.4.4 Conversion Control and Data Transfer Frame
A data transfer frame starts with a falling edge of the CS signal. In any frame, the clocks provided on the SCLK
pin are used to transfer the output data for the completed conversion. The device has two SDOs (SDO-0x and
SDO-1x) for each ADC. For ADC_A, the device provides data on SDO-0A and SDO-1A, whereas for ADC_B,
the device provides data on SDO-0B and SDO-1B. The most significant bit (Dn-1x) of the output data is launched
on the SDO-1x pins and the MSB-1 (Dn-2x) bit is launched on the SDO-0x pins on the falling edge of CS, any
subsequent output bits are launched on the rising edges provided on SCLK. When all output bits of the
conversion result are shifted out, the device launches 0's on the subsequent SCLK rising edges. The data
transfer frame ends with a rising edge of the CS signal. For detailed timing specifications, see 节6 and 图7-6.
The CS pulse high time determines if the data being read back is with a 0 sample latency or a 1 sample latency.
See 图 6-1 and 图 6-2 for the respective timing diagrams. The maximum-rated sampling rate of 2.048 MSPS is
achieved with a latency-1 data capture.
CS
SCLK
SDO-1x
DN-1 x
D1 x
SDO-0x
DN-2 x
D0 x
For ADC_A, x = A. For ADC_B, x = B.
图7-6. Data Transfer Frame for Reading Data
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8 Application and Implementation
Note
以下应用部分的信息不属于TI 组件规范，TI 不担保其准确性和完整性。客户应负责确定 TI 组件是否适
用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The two primary circuits required to maximize the performance of a high-precision, successive approximation
register (SAR) analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This
section presents general principles for designing these circuits, followed by an application circuit designed using
the ADS9226.
8.1.1 ADC Input Driver
The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and a charge-
kickback filter. The amplifier is used for signal conditioning of the input signal and the low output impedance of
the amplifier provides a buffer between the signal source and the switched-capacitor inputs of the ADC. The
charge-kickback filter helps attenuate the sampling charge injection from the switched-capacitor input stage of
the ADC, and band-limits the wideband noise contributed by the front-end circuit. Careful design of the front-end
circuit is critical to meet the linearity and noise performance of the ADS9226.
8.1.1.1 Charge-Kickback Filter
The charge-kickback filter is an RC filter at the input pins of the ADC that filters the broadband noise from the
front-end drive circuitry and attenuates the sampling charge injection from the switched-capacitor input stage of
the ADC. A filter capacitor, CFLT (as shown in 图 8-1), is connected from each input pin of the ADC to ground.
This capacitor helps reduce the sampling charge injection and provides a charge bucket to quickly charge the
internal sample-and-hold capacitors during the acquisition process. Generally, the value of this capacitor must be
at least 20 times the specified value of the ADC sampling capacitance. For the ADS9226, the input sampling
capacitance is equal to 16 pF; therefore, for optimal performance, keep CFLT greater than 320 pF. This capacitor
must be a COG- or NPO-type. The type of dielectric used in COG or NPO ceramic capacitors provides the most
stable electrical properties over voltage, frequency, and temperature changes.
RFLT
CFLT
Device
RFLT
CFLT
图8-1. Charge-Kickback Filter
Driving capacitive loads can degrade the phase margin of the input amplifier, thus making the amplifier
marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of
the amplifiers. A higher value of RFLT helps with amplifier stability, but adds distortion as a result of interactions
with the nonlinear input impedance of the ADC. Distortion increases with source impedance, input signal
frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability of the
driver amplifier and distortion performance of the design. Always verify the stability and settling behavior of the
driving amplifier and charge-kickback filter by TINA-TI™ SPICE simulation. Keep the tolerance of the selected
resistors less than 1% to keep the inputs balanced.
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8.1.2 Input Amplifier Selection
Selection criteria for the input amplifiers is highly dependent on the input signal type, as well as the performance
goals, of the data acquisition system. Some key amplifier specifications to consider when selecting an
appropriate amplifier to drive the inputs of the ADC are:
• Small-signal bandwidth. Select the small-signal bandwidth of the input amplifiers to be as high as possible
after meeting the power budget of the system. Higher bandwidth reduces the closed-loop output impedance
of the amplifier, thus allowing the amplifier to more easily drive the ADC sample-and-hold capacitor and the
RC filter (the charge-kickback filter) at the inputs of the ADC. Higher bandwidth amplifiers offer faster settling
times when driving the capacitive load of the charge-kickback filter, thus reducing harmonic distortion at
higher input frequencies. Equation 4 describes the unity-gain bandwidth (UGB) of the amplifier to be selected
in order to maintain the overall stability of the input driver circuit:
≈
∆
«
’
÷
◊
1
UGB í 4 ì
2p
ì RFLT ì CFLT
(4)
• Distortion. Both the ADC and the input driver introduce distortion in a data acquisition block. Equation 5
shows that to make sure that the distortion performance of the data acquisition system is not limited by the
front-end circuit, the distortion of the input driver must be at least 10 dB less than the distortion of the ADC:
THDAMP Ç THDADC - 10
dB
(5)
• Noise. Noise contribution of the front-end amplifiers must be as low as possible to prevent any degradation in
SNR performance of the system. Generally, to make sure that the noise performance of the data acquisition
system is not limited by the front-end circuit, the total noise contribution from the front-end circuit must be
kept below 20% of the input-referred noise of the ADC. Equation 6 explains that noise from the input driver
circuit is band-limited by designing a low cutoff frequency, charge-kickback filter:
2
SNR dB
(
20
)
≈
∆
’
÷
V
≈
∆
’
÷
-
1
f
_ AMP_PP
p
2
1
5
VREF
2
NG ì 2 ì
+ en2_RMS
ì
ì f-3dB
Ç
ì
ì10
«
◊
∆
∆
÷
÷
6.6
«
◊
(6)
where
– V1 / f_AMP_PP is the peak-to-peak flicker noise in μV
– en_RMS is the amplifier broadband noise density in nV/√Hz
– f–3dB is the 3-dB bandwidth of the charge-kickback filter
– NG is the noise gain of the front-end circuit that is equal to 1 in a buffer configuration
• Settling Time. For DC signals with fast transients that are common in a multiplexed application, the input
signal must settle within an 16-bit accuracy at the device inputs during the acquisition time window. This
condition is critical to maintain the overall linearity performance of the ADC. Settling accuracy for DC
transients directly translates to the linear performance for AC input signals, especially those that may use the
ADC full-scale range. Typically, amplifier data sheets specify the output settling performance only up to 0.1%
to 0.001%, which may not be sufficient for the desired 16-bit accuracy. Therefore, always verify the settling
behavior of the input driver by TINA-TI SPICE simulations before selecting the amplifier.
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8.2 Typical Application
AVDD
AVDD
REFIN / 2
OPA836
+
15.8 Ω
œ
AINP_x
AINM_x
330 pF
330 pF
1 kΩ
ADS9226
ADC_x
VIN
1 kΩ
15.8 Ω
REFIN
Input Driver
图8-2. Typical Connection Diagram of the ADS9226 Application Circuit
8.2.1 Design Requirements
The design parameters are listed in 表8-1 for this example.
表8-1. Design Parameters
DESIGN PARAMETER
ADC sample rate
Analog input signal
SNR
EXAMPLE VALUE
2 MSPS
2 kHz, ±2.5 V, pseudo-differential
> 87 dB
THD
< –100 dB
Power supply
5-V analog, 3.3-V digital
8.2.2 Detailed Design Procedure
图 8-2 shows an application circuit for this example. The device incorporates two independently matched
reference buffers for each ADC. Decouple the reference buffer outputs (the REFP_A and REFP_B pins) with the
REFM_A and REFM_B pins, respectively, with 10-µF decoupling capacitors. The circuit in 图 8-2 shows a
pseudo-differential data acquisition (DAQ) block optimized for low distortion and noise using the OPA836 and the
ADS9226. The single-ended inputs are level-shifted and driven using a high-bandwidth, low-distortion,
operational amplifier configured with a gain of –1 V/V and an optimal RC charge-kickback filter before going to
the ADC. Generally, the distortion from the input driver must be at least 10 dB less than the ADC distortion.
Therefore, these circuits use the OPA836 as an input driver that provides exceptional AC performance because
of its extremely low-distortion and high bandwidth specifications. In addition, the components of the charge-
kickback filter are selected to keep the noise from the front-end circuit low without adding distortion.
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8.2.3 Application Curve
图8-3 provides the typical FFT for the circuit shown in 图8-2.
0
-50
-100
-150
-200
1
2
3 4 567 10
20 30 50 70100 200
Frequency (kHz)
500 1000
D031
SNR = 89.9 dB, THD = –102.9 dB
图8-3. Typical FFT With a 2-kHz Signal
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9 Power Supply Recommendations
The device has two separate power supplies: AVDD and DVDD. The reference buffers and converter modules
(ADC_A and ADC_B) operate on AVDD. The serial interface operates on DVDD. AVDD and DVDD can be
independently set to any value within their permissible ranges.
As shown in 图 9-1, connect pins 12 and 29 together and place 1-µF decoupling capacitors between pin 12
(AVDD) and pin 11 (GND), and between pin 29 (AVDD) and pin 30 (GND). To decouple the DVDD supply, place
a 1-µF decoupling capacitor between pin 28 (DVDD) and pin 27 (GND), and between pin 26 (DVDD) and pin 27
(GND).
1 µF
1 µF
12
AVDD
29
30
GND
AVDD
11
GND
REFIN
AVDD
DVDD
28
REFBUF_A
AVDD
DVDD
1 µF
1 µF
AINP_A
27
26
GND
ADC_A
DVDD
AINM_A
AINP_B
Serial
Interface
ADC_B
AINM_B
AVDD
REFBUF_B
AVDD
REFIN
图9-1. Power-Supply Decoupling
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10 Layout
10.1 Layout Guidelines
This section provides some layout guidelines for achieving optimum performance with the ADS9226.
10.1.1 Signal Path
Route the analog input signals in opposite directions to the digital connections. The reference decoupling
components are kept away from the switching digital signals. This arrangement prevents noise generated by
digital switching activity from coupling to sensitive analog signals.
10.1.2 Grounding and PCB Stack-Up
Low inductance grounding is critical for achieving optimum performance. Grounding inductance is kept below 1
nH with 15-mil grounding vias and a printed circuit board (PCB) layout design that has at least four layers. Place
all critical components of the signal chain on the top layer with a solid analog ground from subsequent inner
layers to minimize via length to ground.
10.1.3 Decoupling of Power Supplies
Place the decoupling capacitors on AVDD and DVDD within 20 mil from the respective pins, and use a 15-mil via
to ground from each capacitor. Avoid placing vias between any supply pin and the respective decoupling
capacitor.
10.1.4 Reference Decoupling
Dynamic currents are present at the REFP_x and REFM_x pins during the conversion phase, and excellent
decoupling is required to achieve optimum performance. Place a 10-µF, X7R-grade, ceramic capacitor with at
least a 10-V rating. Select 0603- or 0805-size capacitors to keep equivalent series inductance (ESL) low.
Connect the REFM_x pins to the decoupling capacitor before a ground via. Also place decoupling capacitors on
the REFby2 pin.
10.1.5 Analog Input Decoupling
Dynamic currents are also present at the pseudo-differential analog inputs of the ADS9226. Use C0G- or NPO-
type capacitors to decouple these inputs because with these types of capacitors, capacitance stays almost
constant over the full input voltage range. Lower-quality capacitors (such as X5R and X7R) have large
capacitance changes over the full input-voltage range that may cause degradation in the performance of the
device.
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10.2 Layout Example
CFILT
CREFP_A
RFILT
RFILT
32
25
CFILT
1
24
ADS9226
CREFIN
8
17
9
16
CFILT
CREFP_B
RFILT
RFILT
CFILT
图10-1. Example Layout for the ADS9226
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11 Device and Documentation Support
11.1 Related Documentation
For related documentation see the following:
• Texas Instruments, REF50xx Low-Noise, Very Low Drift, Precision Voltage Reference data sheet
• Texas Instruments, OPAx836 Very Low Power, Rail-ro-Rail Out Operational Amplifiers data sheet
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TINA-TI™ and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS9226IRHBR
ADS9226IRHBT
ACTIVE
ACTIVE
VQFN
VQFN
RHB
RHB
32
32
3000 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
ADS9226
ADS9226
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
RHB 32
5 x 5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
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PACKAGE OUTLINE
RHB0032E
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
(0.1)
5.1
4.9
SIDE WALL DETAIL
20.000
OPTIONAL METAL THICKNESS
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
SEE SIDE WALL
DETAIL
2X
SYMM
33
3.5
0.3
0.2
32X
24
0.1
C A B
C
1
0.05
32
25
PIN 1 ID
(OPTIONAL)
SYMM
0.5
0.3
32X
4223442/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
(
0.2) TYP
VIA
8
17
(R0.05)
TYP
9
16
(1.475)
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223442/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223442/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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