AFE1104EG4 [TI]

DATACOM, DIGITAL SLIC, PDSO48, GREEN, PLASTIC, SSOP-48;


型号：	AFE1104EG4
厂家：	TEXAS INSTRUMENTS
描述：	DATACOM, DIGITAL SLIC, PDSO48, GREEN, PLASTIC, SSOP-48 电信光电二极管电信集成电路
文件：	总14页 (文件大小：467K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Not Recommended for New Designs

AFE1104

AFE1104E

HDSL/MDSL ANALOG FRONT END

FEATURES

DESCRIPTION

● COMPLETE ANALOG INTERFACE

● T1, E1, AND MDSL OPERATION

● CLOCK SCALEABLE SPEED

● SINGLE CHIP SOLUTION

Burr-Brown’s Analog Front End greatly reduces the

size and cost of an HDSL or MDSL system by provid-

ing all of the active analog circuitry needed to connect

PairGain Technologies SPAROW HDSL digital sig-

nal processor to an external compromise hybrid and a

1:2 HDSL line transformer. All internal filter re-

sponses as well as the pulse former output scale with

clock frequency—allowing the AFE1104 to operate

over a range of bit rates from 196kbps to 1.168Mbps.

● +5V ONLY (5V OR 3.3V DIGITAL)

● 250mW POWER DISSIPATION

● 48-PIN SSOP

● –40°C TO +85°C OPERATION

Functionally, this unit is separated into a transmit and

a receive section. The transmit section generates, fil-

ters, and buffers outgoing 2B1Q data. The receive

section filters and digitizes the symbol data received

on the telephone line and passes it to the SPAROW.

The HDSL Analog Interface is a monolithic device

fabricated on 0.6µCMOS. It operates on a single +5V

supply. It is housed in a 48-pin SSOP package.

txLINE_P

Pulse

Line

Former

Driver

txLINE_N

REF_P

PLL_OUT

Voltage

Reference

V_CM

PLL_IN

txDAT

txCLK

Transmit

Control

REF_N

rxSYNC

rxCLK

Receive

Control

rxLINE_P

rxLOOP

rxGAIN

rxLINE_N

Delta-Sigma

Modulator

rxHYB_P

Decimation

Filter

rxD13 - rxD0

rxHYB_N

Patents Pending

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111

Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

PDS-1331A

Printed in U.S.A. August, 1996

AFE1104

SBWS002

Not Recommended for New Designs

SPECIFICATIONS

Typical at 25°C, AV_DD= +5V, DV_DD= +3.3V, f_tx= 584kHz (E1 rate), unless otherwise specified.

AFE1104E

TYP

PARAMETER

COMMENTS

MIN

MAX

UNITS

RECEIVE CHANNEL

Number of Inputs

Input Voltage Range

Common-Mode Voltage

Input Impedance

Differential

Balanced Differential⁽¹⁾

1.5V CMV Recommended

All Inputs

±3.0

+1.5

See Typical Performance Curves

Input Capacitance

Input Gain Matching

Resolution

±2

Bits

Line Input vs Hybrid Input

Programmable Gain

Settling Time for Gain Change

Four Gains: 0dB, 3.25dB, 6dB, and 9dB

Symbol

Periods

%FSR⁽²⁾

Gain + Offset Error

Tested at Each Gain Range

Output Data Coding

Two’s Complement

Output Data Rate, rxSYNC⁽³⁾

584

kHz

TRANSMIT CHANNEL

Transmit Symbol Rate, f_tx

T1 Transmit –3dB Point

T1 Rate Power Spectral Density⁽⁴⁾

E1 Transmit –3dB Point

E1 Rate Power Spectral Density⁽⁴⁾

Transmit Power^{(4, 5)}

kHz

Bellcore TA-NWT-3017 Compliant

ETSI RTR/TM-03036 Compliant

196

See Typical Performance Curves

292

See Typical Performance Curves

kHz

dBm

Pulse Output

See Typical Performance Curves

Common-Mode Voltage, V_CM

Output Resistance⁽⁶⁾

AV_DD/2

Ω

DC to 1MHz

TRANSCEIVER PERFORMANCE

Uncanceled Echo⁽⁷⁾

rxGAIN = 0dB, Loopback Enabled

rxGAIN = 0dB, Loopback Disabled

rxGAIN = 3.25dB, Loopback Disabled

rxGAIN = 6dB, Loopback Disabled

rxGAIN = 9dB, Loopback Disabled

–67

–69

–71

–73

DIGITAL INTERFACE⁽⁶⁾

Logic Levels

V_IH

V_IL

V_OH

V_OL

|I_IH| < 10µA

|I_IL| < 10µA

I_OH= –20µA

I_OL= 20µA

DV_DD–1

–0.3

DV_DD–0.5

DV_DD+0.3

+0.8

+0.4

Receive Channel Interface

t_rx1

rxCLK Period

rxCLK Duty Cycle

rxSYNC to rxCLK Setup Time

rxCLK to rxSYNC Hold Time

rxCLK to rxD13 - rxD0 Delay

215

t_rx2

t_rx3

t_rx4

Transmit Channel Interface

t_tx1

t_tx2

t_tx3

txCLK Period

txCLK Pulse Width

Basic txDAT Pulse Unit

1.7

10.2

µs

t_tx1/96

POWER

Analog Power Supply Voltage

Digital Power Supply Voltage

Power Dissipation^{(4, 5, 8)}

PSRR

Specification

Operating Range

Specification

Operating Range

DV_DD= 3.3V

4.75

3.15

5.25

3.3

250

300

DV_DD= 5V

TEMPERATURE RANGE

Operating⁽⁶⁾

–40

+85

°C

NOTES: (1) With a balanced differential signal, the positive input is 180° out of phase with the negative input, therefore the actual voltage swing about the common

mode voltage on each pin is ±1.5V to achieve a differential input range of ±3.0V or 6Vp-p. (2) FSR is Full-Scale Range. (3) The output data is available at twice the

symbol rate with interpolated values. (4) With a pseudo-random equiprobable sequence of HDSL pulses; 13.5dBm applied to the transformer (27dBm output from

txLINE_Pand txLINE_N). (5) See the Discussion of Specifications section of this data sheet for more information. (6) Guaranteed by design and characterization. (7)

Uncanceled Echo is a measure of the total analog errors in the transmitter and receiver sections including the effect of non-linearity and noise. See the Discussion

of Specifications section of this data sheet for more information. (8) Power dissipation includes only the power dissipated within the component and does not include

power dissipated in the external loads. See the Discussion of Specifications section for more information.

AFE1104

Not Recommended for New Designs

PIN DESCRIPTIONS

PIN #

TYPE

NAME

DESCRIPTION

Ground

Power

Input

Ground

Input

PGND

PV_DD

txCLK

DGND

txDAT

rxD0

rxD1

rxD2

rxD3

rxD4

Analog Ground for PLL

Analog Supply (+5V) for PLL

Transmit Symbol Clock (392kHz for T1, 584kHz for E1)

Digital Ground

DAC+ Line from SPAROW

ADC Output Bit-0

ADC Output Bit-1

ADC Output Bit-2

ADC Output Bit-3

ADC Output Bit-4

ADC Output Bit-5

Digital Ground

Digital Supply (+3.3V to +5V)

ADC Output Bit-6

ADC Output Bit-7

ADC Output Bit-8

ADC Output Bit-9

ADC Output Bit-10

ADC Output Bit-11

Output

Ground

Power

Output

Input

Power

Input

Ground

Output

Power

Ground

Output

Power

Output

Ground

Output

Input

rxD5

DGND

DV_DD

rxD6

rxD7

rxD8

rxD9

rxD10

rxD11

rxD12

rxD13

rxCLK

rxSYNC

rxGAIN0

rxGAIN1

rxLOOP

AV_DD

rxHYB_N

rxHYB_P

rxLINE_N

rxLINE_P

AGND

REF_P

V_CM

REF_N

AV_DD

AGND

txLINE_N

AV_DD

txLINE_P

AGND

ADC Output Bit-12

ADC Output Bit-13

A/D Clock (18.816MHz for T1, 28.03MHz for E1)

ADC Sync Signal (392kHz for T1, 584kHz for E1)

Receive Gain Control Bit-0

Receive Gain Control Bit-1

Loopback Control Signal (loopback is enabled by positive signal)

Analog Supply (+5V)

Negative Input from Hybrid Network

Positive Input from Hybrid Network

Negative Line Input

Positive Line Input

Analog Ground

Positive Reference Output, Nominally 3.5V

Common-Mode Voltage (buffered), Nominally 2.5V

Negative Reference Output, Nominally 1.5V

Analog Supply (+5V)

Analog Ground

Transmit Line Output Negative

Analog Supply (+5V)

Transmit Line Output Positive

Analog Ground

Connection to Ground Recommended

PLL Filter Output

PLL_OUT

PLL_IN

PLL Filter Input

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN

assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject

to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not

authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

AFE1104

Not Recommended for New Designs

PIN CONFIGURATION

ABSOLUTE MAXIMUM RATINGS

Analog Inputs: Current .............................................. ±100mA, Momentary

±10mA, Continuous

Top View

SSOP

Voltage .................................. AGND –0.3V to AV_DD+0.3V

Analog Outputs Short Circuit to Ground (+25°C) ..................... Continuous

AV_DDto AGND ........................................................................ –0.3V to 6V

PV_DDto PGND ........................................................................ –0.3V to 6V

DV_DDto DGND ........................................................................ –0.3V to 6V

PLL_INor PLL_OUTto PGND ......................................... –0.3V to PV_DD+0.3V

Digital Input Voltage to DGND ..................................–0.3V to DV_DD+0.3V

Digital Output Voltage to DGND ...............................–0.3V to DV_DD+0.3V

AGND, DGND, PGND Differential Voltage ......................................... 0.3V

Junction Temperature (T_J) ............................................................ +150°C

Storage Temperature Range .......................................... –40°C to +125°C

Lead Temperature (soldering, 3s) ................................................. +260°C

Power Dissipation ......................................................................... 700mW

PGND

PV_DD

txCLK

DGND

txDAT

rxD0

48 PLL_IN

47 PLL_OUT

46 NC

45 NC

44 NC

43 NC

rxD1

42 AGND

41 txLINE_P

40 AV_DD

39 txLINE_N

38 AGND

37 AV_DD

36 REF_N

35 V_CM

rxD2

PACKAGE/ORDERING INFORMATION

rxD3

PACKAGE

DRAWING TEMPERATURE

rxD4 10

rxD5 11

PRODUCT

PACKAGE

NUMBER⁽¹⁾

RANGE

AFE1104E

48-Pin Plastic SSOP

333

–40°C to +85°C

DGND 12

DV_DD13

rxD6 14

NOTE: (1) For detailed drawing and dimension table, please see end of data

sheet, or Appendix C of Burr-Brown IC Data Book.

AFE1104E

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown

recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

rxD7 15

34 REF_P

33 AGND

32 AGND

31 rxLINE_P

30 rxLINE_N

29 rxHYB_P

28 rxHYB_N

27 AV_DD

26 rxLOOP

25 rxGAIN1

rxD8 16

rxD9 17

rxD10 18

rxD11 19

rxD12 20

rxD13 21

rxCLK 22

rxSYNC 23

rxGAIN0 24

ESD damage can range from subtle performance degradation

to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

AFE1104

Not Recommended for New Designs

TYPICAL PERFORMANCE CURVES

At Output of Pulse Transformer

Typical at 25°C, AV_DD= +5V, DV_DD= +3.3V, unless otherwise specified.

POWER SPECTRAL DENSITY LIMIT

–20

–40

–38dBm/Hz for T1

–80dB/decade

–40dBm/Hz for E1

–60

–118dBm/Hz

–80

196kHz

292kHz

–120dBm/Hz

for E1

–100

–120

10K

100K

10M

Frequency (Hz)

CURVE 1. Upper Bound of Power Spectral Density Measured at the Transformer Output.

0.4T 0.4T

B = 1.07

C = 1.00

D = 0.93

QUATERNARY SYMBOLS

NORMALIZED

LEVEL

–1

–3

0.01

1.07

1.00

0.93

0.03

–0.01

–0.16

–0.05

0.0264

2.8248

2.6400

2.4552

0.0792

–0.0264

–0.4224

–0.1320

0.0088

0.9416

0.8800

0.8184

0.0264

–0.0088

–0.1408

–0.0440

–0.0088

–0.9416

–0.8800

–0.8184

–0.0264

0.0088

–0.0264

–2.8248

–2.6400

–2.4552

–0.0792

0.0264

0.1408

0.0440

0.4224

0.1320

1.25T

A = 0.01

E = 0.03

A = 0.01

F = –0.01

–1.2T

H = –0.05

14T

F = –0.01

50T

G = –0.16

–0.6T 0.5T

CURVE 2. Transmitted Pulse Template and Actual Performance as Measured at the Transformer Output.

INPUT IMPEDANCE vs BIT RATE

200

T1 = 78kbps, 45kΩ

E1 = 1168kbps, 30kΩ

150

100

300

500

700

900

1100

1300

Bit Rate (kbps)

CURVE 3. Input Impedance of rxLINE and rxHYB.

AFE1104

Not Recommended for New Designs

AFE. The rxHYB_Pand rxHYB_Ninputs remain connected.

Loopback is enabled by applying a positive signal (Logic 1)

to rxLOOP.

THEORY OF OPERATION

The transmit channel consists of a switched-capacitor pulse

forming network followed by a differential line driver. The

pulse forming network receives symbol data from

SPAROW’S DAC+ line and generates a 2B1Q output wave-

form. The output meets the pulse mask and power spectral

density requirements defined in European Telecommunica-

tions Standards Institute document RTR/TM-03036 for E1

mode and in sections 6.2.1 and 6.2.2.1 of Bellcore technical

advisory TA-NWT-001210 for T1 mode. The differential

line driver uses a composite output stage combining class B

operation (for high efficiency driving large signals) with

class AB operation (to minimize crossover distortion).

ECHO CANCELLATION IN THE AFE

The rxHYB input is designed to be subtracted from the

rxLINE input for first order echo cancellation. To accom-

plish this, note that the rxLINE input is connected to the

same polarity signal at the transformer (positive to positive

and negative to negative) while the rxHYB input is con-

nected to opposite polarity through the compromise hybrid

(negative to positive and positive to negative) as shown in

Figure 2.

The receive channel is designed around a fourth-order delta

sigma A/D converter. It includes a difference amplifier that

can be used with an external compromise hybrid for first

order analog crosstalk reduction. A programmable gain

amplifier with gains of 0dB to +9dB is also included. The

delta sigma modulator operating at a 24X oversampling ratio

produces 14 bits of resolution at output rates up to 584kHz.

The basic functionality of the AFE1104 is illustrated in

Figure 1 shown below.

RECEIVE DATA CODING

The data from the receive channel A/D converter is in two’s

complement code.

ANALOG INPUT

OUTPUT CODE (rxD13 - rxD0)

Positive Full Scale

Mid Scale

Negative Full Scale

01111111111111

00000000000000

10000000000000

The receive channel operates by summing the two differen-

tial inputs, one from the line (rxLINE) and the other from the

compromise hybrid (rxHYB). The connection of these two

inputs so that the hybrid signal is subtracted from the line

signal is described in the paragraph titled “Echo Cancella-

tion in the AFE”. The equivalent gain for each input in the

difference amp is 1. The resulting signal then passes to a

programmable gain amplifier which can be set for gains of

0dB through 9dB. The ADC converts the signal to a

14-bit digital word, rxD13 - rxD0.

RECEIVE CHANNEL PROGRAMMABLE

GAIN AMPLIFIER

The gain of the amplifier at the input of the Receive Channel

is set by two gain control pins, rxGAIN1 and rxGAIN0. The

resulting gain between 0dB and +9dB is shown below.

rxGAIN1

rxGAIN0

GAIN

0dB

3.25dB

6dB

rxLOOP INPUT

9dB

rxLOOP is the loopback control signal. When enabled, the

rxLINE_Pand rxLINE_Ninputs are disconnected from the

txLINE_P

txLINE_N

Pulse Former

txDAT

Differential

Line Driver

rxHYB_P

rxHYB_N

ADC

rxD13 - rxD0

rxLINE_P

rxLINE_N

Programmable

Gain Amp

Difference

Amplifier

FIGURE 1. Functional Block Diagram of AFE1104.

AFE1104

Not Recommended for New Designs

0.1µF

PLL_OUT

PLL_IN

REF_P

V_CM

REF_N

1kΩ

1:2 Transformer

Tip

13Ω

txLINE_P

txLINE_N

0.01µF

200Ω

13Ω

Ring

0.1µF

Neg

Pos

SPAROW

DAC+

0.01µF

Compromise

Hybrid

txDAT

Neg

TX_SYM_CLK

HOLD_

txCLK

rxSYNC

rxCLK

750Ω

0.1µF

MCLK19_2

rxHYB_P

rxHYB_N

2kΩ

rxLOOP

rxGAIN1

rxGAIN0

rxD13 - rxD0

AFE1104

100pF

750Ω

REF_N

2kΩ

0.1µF

AD13 - AD0

Input antialias

filter f_C1MHz

0.1µF

AGND

PGND

DGND

AGND

rxLINE_N

rxLINE_P

2kΩ

750Ω

REF_N

2kΩ

100pF

750Ω

DV_DD

PV_DD

AV_DDAV_DDAV_DD

5V to 3.3V Digital

0.1µF

5V Analog

1 - 10µF

0.1µF 0.1µF 0.1µF

10µF

0.1µF

5 - 10Ω resistor for isolation

FIGURE 2. Basic Connection Diagram.

rxHYB AND rxLINE INPUT ANTI-ALIASING FILTERS

rxHYB AND rxLINE INPUT BIAS VOLTAGE

The –3dB frequency of the input anti-aliasing filter for the

rxLINE and rxHYB differential inputs should be about

1MHz. Suggested values for the filter are 750Ω for each of

the two input resistors and 100pF for the capacitor. Together

the two 750Ω resistors and the 100pF capacitor result in a

–3dB frequency of just over 1MHz. The 750Ω input resis-

tors will result in a minimal voltage divider loss with the

input impedance of the AFE1104.

The transmitter output on the txLINE pins is centered at

midscale, 2.5V. But, the rxLINE input signal is centered at

1.5V in the circuit shown in Figure 2 above.

Inside the AFE1104, the rxHYB and rxLINE signals are

subtracted as described in the paragraph on echo cancella-

tion above. This means that the rxHYB inputs need to be

centered at 1.5V just as the rxLINE signal is centered at

1.5V. REF_N(Pin 36) is a 1.5V voltage source. The external

compromise hybrid must be designed so that the signal into

the rxHYB inputs is centered at 1.5V.

This circuit applies at both T1 and E1 rates. For slower rates,

the antialiasing filters will give best performance with their

–3dB frequency approximately equal to the bit rate. For

example, a –3dB frequency of 500kHz should be used for a

single pair bit rate of 500kbps.

AFE1104

Not Recommended for New Designs

TIMING DIAGRAMS

t_tx2

txCLK

txCLK48 (Internal)

txDAT (+3 Symbol)

txDAT (+1 Symbol)

txDAT (–1 Symbol)

txDAT (–3 Symbol)

txDAT (0 Symbol)

t_tx3

3t_tx3

5t_tx3

7t_tx3

9t_tx3

NOTES: (1) t_tx1is the txCLK period which is 1/(Symbol Rate). (2) txCLK48 is an internal 48X oversample clock generated by an on-chip

phase-locked loop from the txCLK signal. (3) txDAT is sampled on the first four rising edges of txCLK48 during each symbol period. (4)

All transitions are specified relative to the falling edge of txCLK. (5) Maximum allowable error for any edge is ± t_tx1/96(±17.8ns at E1 rate;

±26.6ns at T1 rate).

FIGURE 3. Transmit Channel Timing.

t_rx1

rxCLK

rxSYNC

t_rx2

t_rx3

t_rx4

Data 1a

rxD13 - rxD0

Data 1

Data 2

t_tx1/2

NOTES: (1) rxCLK is an externally supplied clock with a frequency of 48 times the symbol rate. It is divided by 2 in the AFE1104 and used as the

24X oversampling clock of the delta-sigma A/D converter. (2) rxSYNC controls the availability of the 14-bit output of the A/D converter.

FIGURE 4. Receive Channel Timing.

AFE1104

Not Recommended for New Designs

RECEIVE TIMING

both to the AFE and to the input of an adaptive filter. The

output of the adaptive filter is subtracted from the AFE

output to form the uncanceled echo signal. Once the filter

taps have converged, the RMS value of the uncancelled echo

is calculated. Since there is no far-end signal source or

additive line noise, the uncanceled echo contains only noise

and linearity errors generated in the transmitter and receiver.

The rxSYNC signal controls portions of the A/D converter’s

decimation filter and the data output timing of the A/D

converter. It is generated at the symbol rate by the user and

must be synchronized with rxCLK. The bandwidth of the

A/D converter decimation filter is equal to one half of the

symbol rate. The A/D converter data output rate is 2X the

symbol rate. The specifications of the AFE1104 assume that

one A/D converter output is used per symbol period and the

other interpolated output is ignored. The Receive Timing

Diagram suggests using the rxSYNC pulse to read the first

data output in a symbol period. Either data output may be

used. Both data outputs may be used for more flexible post-

processing.

The data sheet value for uncancelled echo is the ratio of

the RMS uncanceled echo (referred to the receiver input

through the receiver gain) to the nominal transmitted signal

(13.5dBm into 135Ω, or 1.74Vrms). This echo value is

measured under a variety of conditions: with loopback

enabled (line input disconnected); with loopback disabled

under all receiver gain ranges; and with the line shorted (S₁

closed in Figure 5).

DISCUSSION OF

SPECIFICATIONS

UNCANCELED ECHO

POWER DISSIPATION

Approximately 75% of the power dissipation in the AFE1104

is in the analog circuitry, and this component does not

change with clock frequency. However, the power dissipa-

tion in the digital circuitry does decrease with lower clock

frequency. In addition, the power dissipation in the digital

section is decreased when operating from a smaller supply

voltage, such as 3.3V. (The analog supply, AV_DD, must

remain in the range 4.75V to 5.25V).

The key measure of transceiver performance is uncanceled

echo. This measurement is made as shown in the diagram of

Figure 5 and the measurement is made as follows. The AFE

is connected to an output circuit including a typical 1:2 line

transformer. The line is simulated by a 135Ω resistor.

Symbol sequences are generated by the tester and applied

13Ω

1:2

5.6Ω

Transmit

Data

txDAT_P

txLINE_P

txLINE_N

135Ω

S₁

0.047µF

576Ω

rxHYB_P

1.54kΩ

2kΩ

100pF

AFE1104

0.01µF

150Ω

2kΩ

rxHYB_N

576Ω

0.047µF

0.1µF

750Ω

rxLINE_P

2kΩ

100pF

2kΩ

rxLINE_N

REF_N

750Ω

0.1µF

Uncancelled

Echo

rxD13 - rxD0

FIGURE 5. Uncanceled Echo Test Diagram.

AFE1104

Not Recommended for New Designs

The power dissipation listed in the specifications section

pins of the AFE11104 (pins 3 through 26). However, DV_DD

may be supplied by a wide printed circuit board (PCB) trace.

A digital ground plane underneath all digital pins is strongly

recommended.

applies under these normal operating conditions: 5V Analog

Power Supply; 3.3V Digital Power Supply; standard 13.5dBm

delivered to the line; and a pseudo-random equiprobable

sequence of HDSL output pulses. The power dissipation

specifications includes all power dissipated in the AFE1104,

it does not include power dissipated in the external load.

The external power is 16.5dBm, 13.5dBm to the line and

13.5dBm to the impedance matching resistors. The external

load power of 16.5dBm is 45mW. The typical power dissi-

pation in the AFE1104 under various conditions is shown in

Table I.

The phase-locked loop is powered from PV_DD(pin 2) and its

ground is referenced to PGND (pin 1). Note that PV_DDmust

be in the 4.75V to 5.25V range. This portion of the AFE1104

should be decoupled with both a 10µF Tantalum capacitor

and a 0.1µF ceramic capacitor. The ceramic capacitor should

be placed as close to the AFE1104 as possible. The place-

ment of the Tantalum capacitor is not as critical, but should

be close. In each case, the capacitor should be connected

between PV_DDand PGND.

TYPICAL POWER

In most systems, it will be natural to derive PV_DDfrom the

AV_DDsupply. A 5Ω to 10Ω resistor should be used to

connect PV_DDto the analog supply. This resistor in combi-

nation with the 10µF capacitor form a lowpass filter—

keeping glitches on AV_DDfrom affecting PV_DD. Ideally,

PV_DDwould originate from the analog supply (via the

resistor) near the power connector for the printed circuit

board. Likewise, PGND should connect to a large PCB trace

or small ground plane which returns to the power supply

connector underneath the PV_DDsupply path. The PGND

“ground plane” should also extend underneath PLL_INand

PLL_OUT(pins 47 and 48).

BIT RATE

DISSIPATION

IN THE AFE1104

(mW)

PER AFE1104

(Symbols/sec)

DVDD

(V)

584 (E1)

392 (T1)

3.3

250

300

240

270

230

245

146 (E1/4)

3.3

TABLE I. Typical Power Dissipation.

LAYOUT

The remaining portion of the AFE1104 should be considered

analog. All AGND pins should be connected directly to a

common analog ground plane and all AV_DDpins should be

connected to an analog 5V power plane. Both of these planes

should have a low impedance path to the power supply.

The analog front end of an HDSL system has a number of

conflicting requirements. It must accept and deliver digital

outputs at fairly high rates of speed, phase-lock to a high-

speed digital clock, and convert the line input to a high-

precision (14-bit) digital output. Thus, there are really three

sections of the AFE1104: the digital section, the phase-

locked loop, and the analog section.

Ideally, all ground planes and traces and all power planes

and traces should return to the power supply connector

before being connected together (if necessary). Each ground

and power pair should be routed over each other, should not

overlap any portion of another pair, and the pairs should be

separated by a distance of at least 0.25 inch (6mm). One

exception is that the digital and analog ground planes should

be connected together underneath the AFE1104 by a small

trace.

The power supply for the digital section of the AFE1104 can

range from 3.3V to 5V. This supply should be decoupled to

digital ground with a ceramic 0.1µF capacitor placed as

close to DGND (pin 12) and DV_DD(pin 13) as possible.

Ideally, both a digital power supply plane and a digital

ground plane should run up to and underneath the digital

AFE1104

PACKAGE OPTION ADDENDUM

www.ti.com

1-Aug-2011

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

AFE1104E

NRND

SSOP

TBD

Call TI

AFE1104E/1K

1000

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

AFE1104E/1KG4

AFE1104EG4

NRND

SSOP

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

TBD

Call TI

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0 (mm)

B0 (mm)

K0 (mm)

Pin1

Diameter Width

(mm) W1 (mm)

(mm) (mm) Quadrant

AFE1104E/1K

SSOP

1000

330.0

32.4

11.35

16.2

3.1

16.0

32.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2008

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SSOP DL 48

SPQ

Length (mm) Width (mm) Height (mm)

346.0 346.0 49.0

AFE1104E/1K

1000

Pack Materials-Page 2

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AFE1104EG4 [TI]

相关型号：

AFE1105

AFE1105E

AFE1105E/1K

AFE1105EA

AFE1115

AFE1115E

AFE1115E-1/1K

AFE1115E-1/1KG4

AFE1115E/1K

AFE1115E/1K

AFE1124

AFE1124E