AFE3010AIRGTR [TI]
具有自检和中性点接地故障检测功能的接地故障断路器 (GFCI) | RGT | 16 | -40 to 105;
| 型号： | AFE3010AIRGTR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有自检和中性点接地故障检测功能的接地故障断路器 (GFCI) | RGT | 16 | -40 to 105 断路器 |
| 文件： | 总34页 (文件大小：1439K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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AFE3010
SBFS042 –JUNE 2020
AFE3010 Ground Fault Circuit Interrupter (GFCI) With Self-Test and Neutral-Ground Fault
Detection
1 Features
3 Description
The AFE3010 is a precision, low-power, Ground Fault
Circuit Interrupter (GFCI) controller used for detecting
ground fault leakage paths in electrical circuits. This
device is a single IC solution that continuously
monitors an electrical circuit for multiple fault
conditions to verify that the system is operating
correctly.
1
•
Single-chip GFCI controller to aid in the design of
UL-943 compliant systems
–
–
–
Built-in self-test to detect end-of-life, blink the
LED, and/ or trip the load switch
Detect ground fault leakage path, and trip the
load switch
Detect neutral-ground leakage path, and trip
the load switch
In addition to a ground fault leakage detection, the
AFE3010 can detect a grounded neutral condition
which can also lead to a harmful shock from a
•
•
•
•
Protection against single-component failure
Dual VDD and GND pins for redundancy
Integrated noise filter to prevent false trips
connected appliance. The device implements
a
unique closed-loop grounded neutral detection
scheme that eliminates the need for component
resonance tuning, resulting in optimized system
development time. Periodic self-test is performed
once in every 180 cycles of the AC power line to
ensure all the components related to ground fault
control system are working properly. In case of any
component failure the device enables an LED light,
and/ or trips a solenoid to open the load switch. In
applications where an LED light indicator is not
needed, the ALARM pin can be configured as a
secondary SCR driver to drive an additional solenoid
for redundancy purpose.
Simultaneously protects against HOT to GND and
neutral to GND faults
•
•
Adjustable fault current thresholds through
external feedback resistors
Fast response time
–
–
–
–
150 ms for ±5mA ground fault current
85 ms for ±10-mA ground fault current
40 ms for ±30-mA ground fault current
10 ms for ±50-mA ground fault current
•
Onboard shunt regulator powers the system
through passives
The AFE3010 integrates shunt and LDO regulators to
directly power from an AC line through a diode bridge
and passive components.
•
•
Supports 120-V/ 60-Hz or 220-V/ 50-Hz systems
Operating temperature range: –40 ºC to 105 ºC
The AFE3010 offers flexible configurable options to
implement robust application specific protection
schemes in different end-equipments such as
electrical receptacles, circuit breakers, and so forth.
2 Applications
•
•
•
•
•
GFCI Outlet Receptacles
GFCI Circuit Breakers
Power Cord (In-Line GFCI)
Hair Dryer
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
AFE3010
VQFN (16)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Dish Washer
GFCI Application
HOT
200:1
1000:1
NEUTRAL
LOAD
SWITCH
Solenoid
C3
C2
R5
R8
R6
D2
R7
C4
Q1
R1
R2
C5
C6
NG_OUT
VDD1
OUT FB
REF
R3
R4
FT
PTT
AFE3010
VDD2
C7
C1
SEL
PH
SW_OPEN
C9
GND
SCR
SCR_TST
ALARM
R9
SCR
C8
C10
R10
LOAD
R11
R12
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AFE3010
SBFS042 –JUNE 2020
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Table of Contents
7.4 Device Functional Modes........................................ 12
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application .................................................. 18
8.3 What to Do and What Not to Do ............................ 22
Power Supply Recommendations...................... 23
1
2
3
4
5
6
Features.................................................................. 1
8
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
7.3 Feature Description................................................... 8
9
10 Layout................................................................... 24
10.1 Layout Guidelines ................................................. 24
10.2 Layout Example .................................................... 24
11 Device and Documentation Support ................. 25
11.1 Receiving Notification of Documentation Updates 25
11.2 Support Resources ............................................... 25
11.3 Trademarks........................................................... 25
11.4 Electrostatic Discharge Caution............................ 25
11.5 Glossary................................................................ 25
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
June 2020
*
Initial release.
2
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SBFS042 –JUNE 2020
5 Pin Configuration and Functions
RGT Package
16-Pin VQFN
Top View
SW_OPEN
VDD1
1
2
3
4
12
11
10
9
PTT
SEL
Thermal
Pad
VDD2
PH
GND
SCR_TST
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
1
SW_OPEN
Input
Controls ALARM pin while asserted low. Refer to Table 3 for more details.
Power supply to the part from rectifying diode through series resistor. There is also a
decoupling cap at this pin.
2
VDD1
Power
3
4
VDD2
GND
Power
Redundant power supply pin.
Ground pin for the device.
Ground
Generates a pulse to start the Ground to Neutral fault detection scheme. Drives the
secondary winding of the 200:1 transformer through an AC-coupled capacitor. Leave this pin
floating if Neutral-GND fault detection is not needed.
5
6
7
NG_OUT
SCR
Output
Output
Output
Current output pin that drives the SCR after a fault is detected.
Alarm/ LED driver output. Drives a 3-KHz signal that can be used to drive an LED or buzzer
to indicate that the self-test failed. Can be configured as secondary SCR driver when a 500-
KΩ resistor is connected between SEL pin and ground. Refer to Table 2 for more details.
ALARM
8
9
FT
Output
I/O
Drives the base of a bipolar transistor to emulate fault event during self-test.
Monitors the phase of the sine wave of HOT power line after the solenoid. Drives a weak
HIGH output during SCR self-test. Clamped to VDD through an internal diode.
SCR_TST
Monitors the phase of the sine wave of HOT power line. Clamped to VDD through an internal
diode.
10
PH
Input
11
12
13
14
15
16
SEL
PTT
OUT
FB
Input
Input
Control pin to configure the device. Refer to Table 2 for more details.
Active-low push-to-test pin. Starts self-test and fires SCR if self-test passes.
Amplifier output node.
Output
Input
Amplifier inverting input.
REF
GND
I/O
Amplifier non-inverting input. Typically 2.5 V derived from an internal 5-V regulator.
Ground pin for the device.
Ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
0
MAX
26
UNIT
V
Supply Voltage
Input Voltage
VDD1, VDD2
PH, SCR_TST
–0.3
26
V
REF, FB,
SW_OPEN,
PTT, SEL
–0.3
6
V
NG_OUT
–0.3
–0.3
26
6
V
V
Output Voltage
FT, OUT, SCR,
ALARM
Junction temperature, TJ
Storage temperature, Tstg
150
150
°C
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per
±2000
ANSI/ESDA/JEDEC JS-001, allpins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specificationJESD22-C101, all pins(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
5.5
UNIT
V
VREF, VFB
VSW_OPEN
VPTT, VSEL
,
,
Input voltage
TA
Ambient temperature
–40
105
°C
6.4 Thermal Information
AFE3010
THERMAL METRIC(1)
RGT (QFN)
16 PINS
49.2
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
56.5
24
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.8
ΨJB
24
RθJC(bot)
9.4
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE AND REFERENCE
19.5
20
30
20.5
60
V
ppm/°C
mA
VVDD
IREF
Power Supply Shunt Regulator Voltage
TA = –0 °C to 105 °C
VREF = 0 V
Clamping Current at VREF
Reference Voltage
1
1.7
2.5
80
2.5
2.42
2.58
100
V
VREF
TA = –40 °C to 105 °C
ppm/°C
Force VDD to 19 V through 50-Ω, Measured
VDD to GND
900
1250
1500
µA
µA
IQ
Quiescent Current
Offset Voltage, RTI
Force 19 V to VDD through 50-Ω, Measured
VDD to GND, TA = –40 °C to 105 °C
AMPLIFIER
–150
150
0.5
µV
µV/°C
nV/√Hz
pA/√Hz
Gohms
kHz
VOS
TA = –40 °C to 105 °C
Vn_inp
Iin_inp
Input Voltage Noise
10
2
Input Current Noise
ZOL
Open-loop Transimpedance
Application Bandwidth(1)
VOUT Swing to VDD
VOUT Swing to GND
7
BW
6.5
Vosw_vdd
Vosw_gnd
No Load
No Load
4.8
V
0.1
V
DIGITAL CONTROL
Leakage Current = ±5 mA
Leakage Current = ±10 mA
Leakage Current = ±30 mA
Leakage Current > ±50 mA
0.15
0.085
0.04
s
s
s
s
tgf_resp
Ground Fault Response Time
0.01
Debounce Time from 'PTT High to Low
Transition' to Self-test Start
td1
td2
td3
80
130
140
ms
ms
ms
Debounce Time from 'SW_OPEN High to Low
Transition' to SCR Fire (Long Pulse)
Debounce Time from 'SW_OPEN Low to High
Transition' to ALARM Off
SW_OPEN Low Time to Execute Fault
Counter RESET without SCR Fire (Short
Pulse)
td4
55
ms
SCR DRIVER
IOH
High-Level Output Current
Output Impedance
VO = 1.0 V
2
3
mA
ROUT
550
Ω
ALARM DRIVER
VOH
High-Level Output Voltage
IOH =-1 mA
IOL =1 mA
3
3.2
0.25
3
V
V
VOL
Low-Level Output Voltage
LED/ Alarm Frequency
0.35
3
fLED_AL
FT DRIVER
IOH
KHz
High-Level Output Current
Output Impedance
VO = 1.0 V
2
mA
ROUT
550
Ω
NG_OUT DRIVER
VOL
VOH
Low-Level Output Voltage
High-Level Output Voltage
IOL = 4 mA
0.2
0.4
V
V
IOH = –0.1 mA
VVDD–0.8
VVDD–0.2
(1) The typical bandwidth of the current feedback amplifier is measured based off the recommended component values in the Application
and Implementation section. This number will vary if the component values change in a particular application.
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6.6 Typical Characteristics
at TA = 25 °C typical (unless otherwise noted)
45
50
45
40
35
30
25
20
15
10
5
38.9%
40
41.7%
35
30
30.6%
25.0%
25
22.2%
22.2%
20
15
8.3%
10
5
2.8%
-80
2.8%
-30
2.8%
-80
2.8%
-40
0.0%
-30
0
-90
0
-90
-70
-60
Offset Voltage (mV)
Conditions: Temp = 25èC
-50
-40
-20
-70
-60
Offset Voltage (mV)
Conditions: Temp = 105èC
Figure 2. Amplifier Offset Voltage Distribution
-50
-20
Figure 1. Amplifier Offset Voltage Distribution
40000
35000
30000
25000
20000
15000
10000
5000
40
36
32
28
24
20
16
12
8
36.1%
30.6%
19.4%
8.3%
5.6%
4
0.0%
0
0
-90
-80
-70
-60
Offset Voltage (mV)
Conditions: Temp = -40èC
Figure 3. Amplifier Offset Voltage Distribution
-50
-40
-30
-20
100 200
500 1000 2000 5000 10000
Frequency (Hz)
100000
Conditions:R7=36KW, R6=75W
Figure 4. Amplifier Transimpedance vs Frequency
1E-5
8E-6
6E-6
4E-6
2E-6
0
20
19.98
19.96
19.94
19.92
19.9
AVG
+3STD
-3STD
-2E-6
-4E-6
-6E-6
-8E-6
-1E-5
19.88
19.86
19.84
19.82
19.8
10 2030 50 100 200 5001000
Frequency (Hz)
10000
100000
-40
-10
20
50
80
110
Temperature (èC)
Conditions:R7 = 36KW, R6 = 75W
Figure 6. VDD Drift Across Temperature
Figure 5. Amplifier Output Noise
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7 Detailed Description
7.1 Overview
The AFE3010 is a Ground Fault Circuit Interrupter (GFCI) controller to detect the presence of leakage paths that
could lead to potential injuries from electric shock. This device is designed to develop UL-943 compliant system
like a GFCI receptacle or circuit-breaker. The self-test functionality ensures that the circuit is operating correctly
prior to an actual fault event. A GFCI device relies on the imbalance of differential current through the
transformer to detect a ground fault. The presence of a neutral-ground leakage path can potentially mask some
of this imbalance through the transformer during an actual ground fault event, resulting in safety hazard for the
downstream equipments connected to the GFCI unit. The AFE3010 employs an unique closed-loop neutral-
ground leakage detection scheme to alleviate this safety hazard. The precision, low-noise amplifier along with the
threshold detection filters in the AFE3010 ensure accurate detection of fault events while minimizing unintended
false alerts.
7.2 Functional Block Diagram
AFE3010
OUT
SCR Control
SCR
VS
-
FB
REF
+
NG_OUT
PTT
VDD
PH
VREF
Over-Limit Timers
Self-Test Digital
FT
VTH:1-4
ALARM
Bias, Reference &
Thresholds
SCR_TST
GND
SW_OPEN
SEL
Threshold
Detection
GFCI SELF-TEST
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7.3 Feature Description
7.3.1 Powering The AFE3010
Figure 7 shows the recommended components and configurations to develop a GFCI system using the
AFE3010. The AFE3010 features an internal 20-V shunt regulator that connects to an external rectifier output
through limiting resistors R1 and R2. The two separate VDD and GND pins offer redundancy during single
component failure events in GFCI systems. An internal 5-V rail powers the majority of the internal circuitry, and
drives all the signal pins except the NG_OUT, PH, and SCR_TST pins. The NG_OUT pin is referenced to the 20-
V VDD through an internal reverse blocking diode inside the device.
HOT
200:1
1000:1
LOAD
NEUTRAL
D4
R8
Solenoid
C3
C2
R5
R6
D2
R7
C4
Q1
R1
R2
C5
C6
OUT FB
REF
NG_OUT
VDD1
R3
R4
FT
PTT
D1
AFE3010
VDD2
C7
C1
SEL
PH
SW_OPEN
C9
GND
SCR
SCR_TST
ALARM
R9
C8
SCR
C10
C11
D3
R10
R11
R12
Figure 7. AFE3010 Application Diagram
7.3.2 Sensing Amplifier
The AFE3010 employs a current-feedback chopper amplifier topology to sense a wide range of fault currents
with high precision. The current-feedback topology allows the device to maintain consistent gain across the wide
fault current limits. Hence no degradation of accuracy is experienced at large fault current measurements. The
device REF, FB, and OUT pins are the noninverting, inverting, and output terminals of the amplifier, respectively.
The user access of all three pins helps system designers develop their own current sensing thresholds and
bandwidths by optimizing the corresponding passive component values.
7.3.3 Noise Filter
As shown in Figure 8, the AFE3010 uses a unique 2-stage filter architecture to provide robust protection against
false trips. A series of internal comparators register the fault current thresholds at the output of the sensing
amplifier. Once a valid fault threshold is detected, the filter searches for a pre-determined pattern of fault
occurrences in the consecutive cycles. If the specific pattern is detected, the filter will enable the SCR driver to
open the power line switch. As shown in Table 1, the AFE3010 response time is faster than the UL943 mandated
requirements.
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Feature Description (continued)
Fault Event at LOAD
IF
IL+IF
1000:1
LOAD
HOT
NEUTRAL
IL
AFE3010
VO ß IF
Integration &
Noise Filter
SCR
Drive
Sensing
Amp
Figure 8. AFE3010 Filter Scheme During Fault Conditions
Table 1. AFE3010 Response Time
FAULT CURRENT
FAULT RESPONSE TIME
AFE3010 TYPICAL RESPONSE
mA
UL943 TIMING REQUIREMENTS (S)
TIME (S)
> ±5
> ±10
> ±30
> ±50
< 6.335
<1.000
< 0.371
< 0.100
0.150
0.085
0.040
0.010
7.3.4 ALARM (LED) Driver
The AFE3010 ALARM pin can be used to drive an LED or a buzzer. Under normal system operation the ALARM
output remains low. During active operation, the ALARM signal generates a 3-KHz signal for the duration of
positive half of the power cycle and remains low for the duration of the negative half power cycle. Figure 9 shows
the ALARM signal scheme over a 60-Hz power line.
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8.33ms
8.33ms
ALARM/ LED Pulsing at 3KHz
ALARM/ LED Low
Figure 9. AFE3010 ALARM Signal Active Mode Definition (Time Calculation Shown for a 60-Hz Power
Line)
7.3.5 Phase Detection
The AFE3010 monitors power line signal phase at any given time through the PH and SCR_TST pins. Both pins
are clamped to VDD through internal clamping diodes. The PH pin is connected directly to the HOT power line.
This enables the device to monitor the power signal instantaneously. Phase measurement is critical for faster
and accurate response to system fault conditions. The SCR_TST pin measures the phase after the rectifying
diode.
7.3.6 SCR Control
The AFE3010 triggers an external SCR through the device SCR pin during a load fault event or self-test fail
event. This SCR trigger event activates a solenoid to trip the load switch disconnecting the load.
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7.3.7 Self-Test Function
The AFE3010 performs two different types of self-tests: periodic self-test and continuous self-test.
7.3.7.1 Periodic Self-Test
At system power up, the self-test starts after 60 cycles of power line signal, and retests within 60 cycles if the first
self-test fails. Five consecutive self-test fails drive the SCR and assert the ALARM signal blinking at 1-second
intervals (for 60-Hz systems). After the first self-test pass, the device fires ALARM for 250-ms period to indicate
the successful pass of the first self-test. During normal operating conditions, the self-test repeats every 180
cycles. Figure 10 shows the periodic self-test sequences and decision blocks. The device requires one cycle
from the AC power line to complete the periodic self-tests listed below:
1. Ground Fault Test: the AFE3010 generates a fault current through the FT pin. The device reads a test pass if
the AFE3010 detects the fault current through the transformer. If the fault current is not detected, the device
reads a test fail. This fail event triggers another self-test within next 60 cycles. After five consecutive fails, the
AFE3010 fires the SCR and sets the ALARM blinking at 1-s intervals (for 60-Hz systems). The ground fault
test covers the integrity check of the transformer, fault current generator components, feedback resistors,
and the AFE3010 fault detection circuits.
2. SCR Integrity Test: The AFE3010 performs SCR integrity test after completing the ground fault test. The
device induces a SCR anode signal transition with the help of SCR_TST pin. If the SCR anode signal low
transition is not detected, the AFE3010 reads a test fail. This fail event triggers another self-test within next
60 cycles. After five consecutive fails it fires the SCR and sets ALARM blinking at 1-s intervals (for 60-Hz
systems).
7.3.7.2 Continuous Self-Test
The AFE3010 performs the following continuous mode self-tests. If any of these tests fail, the device does not
wait to perform another self-test. Rather, the AFE3010 immediately fires the SCR and sets the ALARM blinking
as 1-s intervals (for 60-Hz systems).
1. Open Solenoid Test: The AFE3010 checks for transition of AC line signal at the PH and SCR_TST pins. If
the device does not detect a transition of the line signal at PH or SCR_TST pins for approximately 100 ms,
then the device reads a self-test fail.
2. Diode Bridge Test: if a diode is shorted in the diode bridge rectifier, the device is able to detect the variation
in supply current from the diode bridge. This detection is considered a self-test fail, and the AFE3010 fires
the SCR and sets the ALARM blinking at 1-s intervals (for 60-Hz systems).
3. Amplifier Short/ Open: The device monitors for sustained fault current conditions, even after the fault current
has been detected and SCR has fired. The primary purpose of this self-test is to detect a single-point failure
with the amplifier signal pins and associated components. If a failure is detected, the device fires SCR one
more time and LED starts blinking. In the event the load switch doesn't open after SCR is fired, this self-test
recognizes a failure and starts the LED blinking.
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Self-test Begins
60 Cycles after
Power Up
Initiate a Ground-
Fault Leakage Event
through FT Pin
Monitor Filter Counter
to Detect the Induced
Fault
Yes
Was the
Induced Fault
Detected?
Repeat Self-test
in 180 Cycles
Start SCR Self-test
No
Was the SCR
Operation
Verified?
No
Self-test Passes
Repeat Self-test
in 60 Cycles
Is this the 5th
Consecutive Fail?
Yes
Yes
No
No
Is this the 5th
Consecutive Fail?
Yes
Initiate ALARM
Blinking, and Drive
SCR to Open the
Load Switch
Figure 10. AFE3010 Self-test Sequence
7.4 Device Functional Modes
7.4.1 Pin Configuration
The AFE3010 offers multiple operating modes and pin functions. These modes can be set by the SEL pin per
Table 2.
Table 2. Pin Configuration
SEL
SCR SELF-TEST
ALARM
5 V (Leave floating)
No
Works as ALARM/ LED driver.
2.5 V (Connect 500-KΩ resistor to
Works as secondary SCR driver in applications
where ALARM (LED) function is not needed.
Yes
Yes
GND)
0 V (Connect to GND)
Works as ALARM/ LED driver.
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7.4.2 ALARM Modes to Drive LED
The AFE3010 supports three different modes when the ALARM pin is used as an LED driver:
1. Successful power-up indication: The LED turns on for 250-ms when the first periodic self-test is completed
after power up. On a 60-Hz system, this event occurs approximately one second after power up.
2. LED blinking due to self-test fail: In case of a self-test fail, the ALARM pin sets the LED in blinking mode a
frequency of 0.5-Hz. In this state, the LED is on for one second and off for one second. When the ALARM
pin goes into blinking mode, a system power recycle or a successful self-test pass through the PTT press will
deactivate the ALARM signal.
3. LED on through the SW_OPEN pin: If the SW_OPEN pin is low, the LED will turn on without 0.5-Hz blinking.
During a self-test fail event, the device overrides the SW_OPEN state and puts the LED blinking mode at 0.5
Hz.
Table 3. ALARM (LED) Operating Modes
AFE3010 STATUS
SW_OPEN PIN
ALARM (LED) FUNCTION
COMMENTS
Floating
Self-test fail dominates ALARM (LED)
behavior and ignores the SW_OPEN
signal
Self-test fails
ALARM (LED) blinks
Low
Floating
Low
ALARM (LED) remains off
Load switch open due
to H-G or N-G fault
ALARM (LED) remains on without blinking
ALARM (LED) on for 0.25 s after first self-
test pass
Indicates the event of first self-test
pass after power up
Floating
Low
At power up, during the
first self-test only
ALARM (LED) on without blinking
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Manual Self-Test Using PTT Pin
The AFE3010 supports manual self-test using the PTT pin.
8.1.1.1 Successful Self-Test
Figure 11 shows a successful manual self-test timing with the PTT pin.
1
6
PTT
Debounce Time, td1
2
Self-test
SCR
4
Fault Counter RESET
5
ALARM
Figure 11. Successful Manual Self-Test Using PTT Pin
1. The test sequence starts when PTT transitions from high to low.
2. After a debounce time to ensure there is no false transition, the device starts the self-test.
3. If the self-test passes, the SCR fires.
4. The internal fault counter resets.
5. The ALARM signal remains low to indicate the self-test passed.
6. The PTT signal transitions low to high to complete the self-test event.
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Application Information (continued)
8.1.1.2 Unsuccessful Self-Test
Figure 12 shows an unsuccessful manual self-test timing with the PTT pin.
1
6
PTT
2
Self-test
SCR
4
Fault Counter RESET
5
ALARM
Figure 12. Unsuccessful Manual Self-Test Using PTT Pin
1. The test sequence starts when PTT transitions from high to low.
2. After a debounce time to ensure there is no false transition, the device starts the self-test.
3. If the self-test does not pass, the SCR does not fire.
4. The internal fault counter doesn't reset.
5. The ALARM signal starts to blink at 0.5Hz (for 60-Hz systems) to indicate the self-test fail.
6. The PTT signal transitions low to high to complete the self-test event.
8.1.2 ALARM and RESET Function With SW_OPEN
The SW_OPEN pin can be used as a reset signal to the device through a mechanical assembly or a micro
controller. When the SW_OPEN remains low longer than the debounce time td2, the device fires the SCR. For
applications that require a reset without the SCR fire, keep the SW_OPEN low state for shorter duration (in
between 55 ms to 75 ms) before transition to high state. The ALARM (LED) function is also modified using the
SW_OPEN function. Connect a noise-blocking capacitor to the SW_OPEN pin if this function is not needed.
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Application Information (continued)
8.1.2.1 No Self-Test Fail Event
If there is no self-test failure event, the ALARM is turned on without blinking when the SW_OPEN signal goes
from high to low. Figure 13 describes the sequence of events.
5
1
SW_OPEN
Debounce Time, td2
Debounce Time, td3
2
SCR
Fault Counter Reset
ALARM
3
4
6
Figure 13. ALARM With SW_OPEN Transition to Low. No Self-Test Failure.
1. The SW_OPEN signal transitions from high to low.
2. After a debounce time to ensure there is no false transition, the device fires the SCR.
3. The internal fault counter resets.
4. The ALARM turns on.
5. The SW_OPEN signal transitions low to high.
6. After a debounce time to ensure there is no false transition, the ALARM turns off.
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Application Information (continued)
8.1.2.2 Self-Test Fail Event
If there is a prior self-test failure event, the ALARM will continue to blink at 0.5 Hz (for 60-Hz systems) when the
SW_OPEN signal goes from high to low. Figure 14 describes the sequence of events.
1
5
SW_OPEN
Debounce Time, td2
Debounce Time, td3
2
SCR
Fault Counter Reset
ALARM
3
4
6
Figure 14. ALARM With SW_OPEN Transition to Low and Prior Self-Test Failure
1. SW_OPEN signal transitions from high to low.
2. After a debounce time to ensure there is no false transition, the device fires the SCR.
3. The internal fault counter resets.
4. The ALARM continues to blink at 0.5 Hz (for 60-Hz systems) because the self-test fail overrides SW_OPEN
function.
5. The SW_OPEN signal transitions low to high.
6. After a debounce time to ensure there is no false transition, the ALARM turns off.
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8.2 Typical Application
HOT
200:1
1000:1
LOAD
NEUTRAL
D4
R8
Solenoid
C3
C2
R5
R6
D2
R7
C4
Q1
R1
R2
C5
C6
OUT FB
REF
NG_OUT
VDD1
R3
R4
FT
PTT
D1
AFE3010
VDD2
C7
C1
SEL
PH
SW_OPEN
C9
GND
SCR
SCR_TST
ALARM
R9
C8
SCR
C10
C11
D3
R10
R11
R12
Figure 15. Typical GFCI Application Schematic With AFE3010
8.2.1 Design Requirements
Figure 15 is the typical application for the AFE3010 when the SEL pin is grounded. The system requirements
shown in Table 4 are based upon the UL-943 standard. The required component power and voltage ratings
should be chosen based upon the line voltage. See Table 5 for more information on power ratings.
Table 4. Design Requirements
DESIGN PARAMETER
Line or source voltage
VALUE
120 VAC (±15%)
50-60 Hz
Line frequency
Line polarity (connection to GFCI unit)
Operational temperature
Rated load
Normal and reverse polarity
–40 °C to +105 °C
20 A RMS
Ground fault threshold (trip point)
5 mA RMS
Ground fault threshold variation over all
parameters
±0.5 mA RMS
Per UL-943
Neutral-to-ground fault detection
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8.2.2 Detailed Design Procedure
The following procedure details how to design a GFCI system with the AFE3010. The procedure is not intended
to represent all of the validation required for a GFCI system to comply with the necessary regulations. The main
goals are to tune the ground fault trip level and neutral-to-ground (N-G) detection of the system.
Table 5 presents the key parameters needed for the components in Figure 15. Table 5 also provides brief
explanations of components and parameters. Component voltage ratings are dependent upon either the 20-V
internal shunt regulator, the internal 5-V rail, or by the line voltage itself. Note that while Table 5 shows tested
and working values, some components could be optimized further to reduce necessary power and voltage
ratings depending upon the system requirements.
Table 5. Summary of Components in AFE3010 Typical Application
COMPONENT
DESIGNATOR
COMPONENT
VALUE
COMPONENT
RATINGS
DESCRIPTION
Primary decoupling capacitance for AFE3010. Voltage rating dependent
upon the 20-V shunt regulator.
C1
C2
C3
C4
3.3 µF
0.1 µF
0.47 µF
1 nF
50 V, ±10%, X7R
50 V, ±10%, NP0
> 5 V, ±10%, X7R
> 5 V, ±10%, NP0
Capacitive load for NG_OUT driver to generate a current pulse. Voltage
rating dependent upon the 20-V shunt regulator.
Tunes and stabilizes the amplifier response so VOUT is inverted with Line
at normal polarity.
Improves the noise immunity of the amplifier and comparators. TI does
not recommend to increase this value further.
Improves the noise immunity of the amplifier. It can be increased up to
150 nF given R6 and R7 do not change. Always check for amplifier
stability over-temperature when increasing this value.
C5
C6
1 nF
> 5 V, ±10%, NP0
> 5 V, ±10%, NP0
It helps keep the reference voltage buffer stable from high-frequency
noise transients. TI does not recommend to increase this value further.
180 pF
C7, C8, C9
C10
1 nF
> 5 V, ±10%, NP0
> 5 V, ±10%, X7R
These capacitors filter noise coupled to their respective digital pins.
These capacitors help prevent noise coupling into the gate of the SCR.
0.47 µF
250 VAC, ±10%,
X7R
Helps keep the SCR anode stable. Voltage rating dependent upon line
voltage.
C11
D1
2 .2 nF
N/A
Provides line voltage rectification for AFE3010 VDD. Voltage rating
dependent upon line voltage.
600 V, 1 A
1000 V, 1 A
Red LED
Provides current rectification for SCR and solenoid. Voltage rating
dependent upon line voltage.
D2
N/A
LED driven by ALARM to indicate initial passing of self-test on power up
and self-test failure.
D3
Red
Prevents any current flowing from emitter to collector in Q1, which
D4
Q1
N/A
600 V, 1 A
400 V, 1 A
protects the AFE3010 from current injection during abnormal states of
Q1.
400 V
NPN transistor controlled by FT driver to perform periodic self-tests.
Limit current for AFE3010 shunt regulator at VDD. Resistors are placed in
two parallel pairs to ensure normal operation even if a resistor fails. One
pair is placed above the bridge (D1) to limit current in event of a D1
failure. Power rating determined by line voltage and supply current.
R1, R2, R3, R4
18.0 kΩ
100 Ω
5%, 0.5 W
Limits current into NG_OUT pin during inductive kickback from driving
200-turn coil. Limiting the current will keep the internal ESD cells from
turning on and potentially damaging the device. Thus, take caution when
decreasing this value to improve N-G detection. To reduce R5 and protect
AFE3010, a Schottky diode can be used at NG_OUT to clamp pin voltage
during inductive kickback.
R5
1%, 0.1 W
Input resistor for the internal amplifier. R6 can be adjusted to improve N-
G detection.
R6
R7
75 Ω
1%, 0.1 W
1%, 0.1 W
Feedback resistor for the internal amplifier. Sets the gain for ground fault
signals. Thus, R7 can be adjusted to change the device trip point.
36 kΩ
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Table 5. Summary of Components in AFE3010 Typical Application (continued)
COMPONENT
DESIGNATOR
COMPONENT
VALUE
COMPONENT
RATINGS
DESCRIPTION
Sets the level of fault current used in the periodic self-test when Q1 is
turned on. The fault current should be greater than the trip point for
successful detection and operation. The self-test will be hardest to pass
when line connects to GFCI with reverse polarity and there is a small
leakage current that is below the trip current. The worst-case power
condition will be when a device cannot detect the self-test fault current
and thus Q1 is on for a half-cycle of line.
R8
10.5 kΩ
1%, 0.5 W
Limits the output current of the ALARM driver. Using a higher R9 value
will reduce supply current when ALARM is driving D3.
R9
1.5 kΩ
560 Ω
5%, 0.1 W
5%, 0.1 W
R10
Limits the output current of the SCR driver.
Limits the current into the SCR_TST pin when regulating to 20 V and sets
internal biasing. The value of the resistor should not change from the
recommendation when SEL = LOW. The lowest acceptable value is a 1%
49.9 kΩ. Given a 170-V peak line voltage, the average power rating
required is calculated with [((170 V – 20 V)2) /R11] / [2 × SQRT(2)].
R11
R12
51 kΩ
1 MΩ
5%, 1/3 W
5%, 0.1 W
Limits the current into PH pin.
WARNING
When evaluating this device, implement high-voltage safety precaution and
procedures.
1. The first step in the design of a system with AFE3010 is to determine the correct transformer orientation and
coil connections. The AFE3010 internal detection scheme requires the fault waveforms to have a specific
polarity to the Hot-to-Neutral line voltage. The two rules the design must follow are:
a. The amplifier output voltage (VOUT) must be approximately 180° out of phase with the Hot-Neutral line
voltage when line voltage connects to a GFCI unit with normal polarity. Thus, when line is connected to
system with reverse polarity, the VOUT signal must be in-phase with line voltage. The amplifier's polarity
is determined by the value of C3, the connection of amplifier inputs (REF and FB) to the 1000-turn coil,
and by the direction of the line wires through the transformer core. Refer to Figure 17 for the correct
waveform. Note that normal line polarity means that the Hot and neutral nodes of the source are
connected correctly to the Hot and Neutral input connectors of the system, respectively, which means the
PH pin and D4 are also connected to Hot as shown in Figure 15.
b. The N-G pulse on VOUT when there is a N-G fault must look like Figure 18. The N-G pulse measured on
VOUT should first increase above 2.5 V and then decrease below 2.5 V. The second, downward pulse
should be greater in amplitude and energy than the initial positive pulse. This rule should be true
regardless of line polarity. N-G pulse polarity is determined by the connection of NG_OUT and GND pins
to the 200-turn coil and by the polarity of the line wires through the transformer core.
2. Populate the board with the recommended values shown in Table 5.
3. Tune the amplifier's ground fault threshold (trip point).
a. Set up the system with an adjustable Hot-to-ground (H-G) fault load and an ammeter in-series to
measure the fault (or leakage) current.
b. Adjust the fault load so that the ammeter reads < 3 mA RMS of fault current.
c. Power off and then power on the system to reset any possible trips by the system.
d. Slowly increase the fault current until the AFE3010 SCR driver is pulsed and trips the solenoid. Note the
ammeter reading once the system trips.
e. If the system trips too early (< 4.5 mA RMS), then disconnect the system from power and decrease R7.
f. If the system trips too late (> 5.5 mA RMS), then disconnect the system from power and increase R7.
4. Tune the system's Neutral-to-ground (N-G) detection.
a. Set up the system according to Figure 16. Note that this initial design process does not require testing N-
G detection with H-G fault or load currents.
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S1
+
HOT
+
GFCI
system
RN = 0.4 ꢀ
NEUTRAL
-
-
RG= 1.6 ꢀ
S3
Figure 16. Neutral-to-Ground Detection Test Setup for AFE3010 Design Procedure
b. Choose the RN and RG pair that creates the largest total resistance, as this is the worst-case for the
AFE3010's N-G detection. In this procedure, the total N-G resistance to test is 2 Ω.
c. Using the relays S1 and S3, switch in the N-G fault and check if the system trips. Note that either relay
may be closed first.
d. If the system successfully trips, then re-test the detection over temperature.
e. If the system successfully detects N-G fault overtemperature, then the first-pass component optimization
is complete.
f. If the system fails to detect the N-G, then consider the following component modifications:
i. Adjust R6. Decreasing R6 has shown to increase the N-G pulse sensed by amplifier with minimal
effect on amplifier gain.
ii. Increase R7. The trip point must be checked again because the amplifier gain will increase.
iii. Reduce the NG_OUT resistor R5. Note that there is a lower bound to the value of R5, depending on
the impedance of the 200-turn coil. R5 helps limit current from any activated internal ESD cells
during the inductive kickback on the NG_OUT pin. If R5 must be decreased, consider adding a
Schottky diode at the NG_OUT pin to clamp the NG_OUT voltage above the Absolute Maximum
Rating of –0.3 V.
iv. Add a small capacitor from the REF pin to GND. Values between 100 pF and 300 pF are acceptable.
5. Successful operation of the AFE3010 can be seen with the successful passing of the internal self-tests. A
successful self-test can be observed with the ALARM LED (D3) blinking once one second after device power
up.
6. Perform the rest of the testing specified in the UL-943 standard.
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8.2.3 Application Curves
2.7
200
175
150
125
100
75
3.5
3.2
3.0
2.8
2.5
2.2
2.0
1.8
1.5
1.2
24
21
18
15
12
9
OUT
Line
2.6
2.6
2.5
2.4
2.4
2.4
2.3
2.2
2.2
2.2
2.1
2.1
2.0
2.0
50
25
0
-25
-50
-75
-100
-125
-150
-175
6
3
OUT
NGOUT
VDD
0
Successful periodic self-test
-5 10 15
1.9
-30
-3
-25
-20
-15
-10
0
5
20
25
-200 -100
0
100
200
300
400
500
600
700
800
Time (ms)
Time (µs)
D100
D200
Figure 17. Amplifier Output During a 3.7-mA Ground Fault
With Normal Line Polarity
Figure 18. Neutral-Ground Pulse on VOUT With 2-Ω N-G
Fault. No Load or Fault Currents.
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
1200
3.5
3
1400
OUT
SCR
OUT
SCR
1200
1000
800
600
400
200
0
Line
LINE
1000
2.5
2
800
600
400
200
0
1.5
1
0.5
0
-200
-0.5
-200
-240 -210 -180 -150 -120
-90
-60
-30
0
30
60
-225 -200 -175 -150 -125 -100
-75
-50
-25
0
25
Time (ms)
Time (ms)
D201
D202
Figure 19. Device Trip to 5-mA RMS Ground Fault on
Device Power Up
Figure 20. Device Trip to 2-Ω N-G Fault. No Load Or Fault
Currents.
8.3 What to Do and What Not to Do
Do:
•
Check that the system can pass its own periodic self-test before performing system testing and
characterization.
•
Make R8 small enough so the AFE3010 can pass a self-test even when there is some small leakage current
and the line is connected with reverse polarity.
•
•
Make R5 large enough so that the NG_OUT driver current does not burn or break the 200-turn coil.
Make R5 large enough so that the NG_OUT pin voltage does not drop below –0.3 V or does not sink more 5
mA of current during inductive kickback.
•
•
Always re-test the trip point and N-G detection whenever making changes to the system component values.
Place filter capacitors as close a possible to the device pins, especially for the amplifier, VDD, PH, PTT, and
SW_OPEN pins.
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9 Power Supply Recommendations
It is important to choose proper resistors and capacitors for the VDD pins. Sufficient decoupling capacitance is
required to keep the internal 20-V shunt regulator stable during events in which the AFE3010 is driving loads with
the ALARM, SCR, or NG_OUT pins. The values recommended in the typical application schematic and Table 5
have shown to maintain a stable VDD even during events when diodes in D1 rectifier were shorted. Additionally,
the VDD regulator maintained sufficient voltage even when one of the current limiting resistors (R1 through R4)
was disconnected. As a general rule, do not let the VDD regulator drop below 8 V during board failure events, or
else the device could reset. If the capacitance at VDD is too large, then the device takes longer to power up,
which adds to trip times when device is powered up with a fault current. The recommended values shown in
Table 5 have shown to yield power-up trip times compliant with the UL 943 standard.
The current-limiting resistors for VDD (R1 through R4) should have enough resistance to reduce power
dissipation, but should not be large enough to affect power-on trip times. To determine the maximum total power
rating needed by these resistors, calculate the maximum instantaneous supply current (IVDD) needed by summing
the maximum quiescent current and the maximum ALARM and SCR driver currents. The NG_OUT driver current
has shown minimal effect on VDD regulation.
Place the decoupling capacitors as close as possible to the VDD pins to generate a short, low-impedance return
current path to ground.
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10 Layout
10.1 Layout Guidelines
The layout of the AFE3010 and its surrounding circuit is critical to maintaining performance and minimizing
unwanted noise coupling. Follow these layout guidelines:
•
•
•
Place all capacitors as close as possible to their respective pins or nodes.
Route the signal traces from the 1000-turn coil to the amplifier as a differential pair.
Provide low-impedance ground connections throughout the board, especially between the ground pin of the
rectifier (D1) and the ground pin of the AFE3010.
•
Connect the bottom AFE3010 thermal pad to board ground to help with noise immunity.
10.2 Layout Example
To the 100-turn coil
To the 200-turn coil
R6
C6
To HOT
R7
C2
Bottom or
mid-layer
trace
C5
C4
R12
R5
VIA to Analog
Ground Plane
Bottom or
mid-layer
trace
R4
To
button
PTT
SEL
SW_OPEN
C1
VIAs to tie thermal
pad to ground
plane
VDD1
VDD2
GND
To rectifier
supply
PH
SCR_TST
C8
R3
To
R10
To
R9
To
Q1
VIA to Analog
Ground Plane
To rectifier ground
To R11
Figure 21. AFE3010 Layout Example
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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23-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
AFE3010AIRGTR
AFE3010AIRGTT
ACTIVE
ACTIVE
VQFN
VQFN
RGT
RGT
16
16
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 105
-40 to 105
A3010
A3010
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Aug-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jul-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
AFE3010AIRGTR
AFE3010AIRGTT
VQFN
VQFN
RGT
RGT
16
16
3000
250
330.0
180.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jul-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
AFE3010AIRGTR
AFE3010AIRGTT
VQFN
VQFN
RGT
RGT
16
16
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RGT0016C
VQFN - 1 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
SIDE WALL
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
1.0
0.8
C
SEATING PLANE
0.08
0.05
0.00
1.68 0.07
(DIM A) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
1.5
1
12
0.30
16X
0.18
13
16
0.1
C A B
PIN 1 ID
(OPTIONAL)
SYMM
0.05
0.5
0.3
16X
4222419/D 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.68)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
(2.8)
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
(0.58) TYP
8
(R0.05)
ALL PAD CORNERS
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222419/D 04/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.55)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4222419/D 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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