AFE4300PNR [TI]
Low-Cost, Integrated Analog Front-End for Weight-Scale and Body Composition Measurement; 低成本，集成模拟前端的重量，规模和体成分测量
| 型号： | AFE4300PNR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Low-Cost, Integrated Analog Front-End for Weight-Scale and Body Composition Measurement |
| 文件： | 总30页 (文件大小：309K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AFE4300
www.ti.com
SBAS586B –JUNE 2012–REVISED JUNE 2013
Low-Cost, Integrated Analog Front-End
for Weight-Scale and Body Composition Measurement
Check for Samples: AFE4300
1
FEATURES
DESCRIPTION
The AFE4300 is
a
low-cost analog front-end
2
•
Weight-Scale Front-End:
incorporating two separate signal chains: one chain
for weight-scale (WS) measurement and the other for
body composition measurement (BCM) analysis. A
16-bit, 860-SPS analog-to-digital converter (ADC) is
multiplexed between both chains. The weight
measurement chain includes an instrumentation
amplifier (INA) with the gain set by an external
resistor, followed by a 6-bit digital-to-analog converter
(DAC) for offset correction, and a circuit to drive the
external bridge/load cell with a fixed 1.7 V for
ratiometric measurements.
–
–
Supports up to Four Load Cell Inputs
On-Chip Load Cell 1.7-V Excitation Voltage
for Ratiometric Measurement
–
68-nVrms Input-Referred Noise (0.1 Hz to 2
Hz)
–
–
Best-Fit Linearity: 0.01% of Full-Scale
Weight-Scale Measurement : 540 µA
•
Body Composition Front-End:
–
Supports Up To Three Tetra-Polar Complex
Impedance Measurements
The AFE4300 can also measure body composition by
applying a sinusoidal current into the body. The
sinusoidal current is generated with an internal
pattern generator and a 6-bit, 1-MSPS DAC. A
voltage-to-current converter applies this sinusoidal
current into the body, between two terminals. The
voltage created across these two terminals as a
result of the impedance of the body is measured back
with a differential amplifier, rectified, and its amplitude
is extracted and measured by the 16-bit ADC.
–
6-Bit, 1-MSPS Sine-Wave Generation
Digital-to-Analog Converter (DAC)
–
–
–
–
375-µArms, ±20% Excitation Source
Dynamic Range : 0 Ω to 2.8 kΩ
0.1-Ω Measurement RMS Noise in 2-Hz BW
Body Composition measurement : 970 µA
•
Analog-to_Digital Converter (ADC):
–
–
16 Bits, 860 SPS
The AFE4300 operates from 2 V to 3.6 V, is specified
from 0°C to +70°C, and is available in a TQFP-80
package.
Supply current: 110 µA
APPLICATIONS
•
Weight Scales with Body Composition
Measurements
FUNCTIONAL BLOCK DIAGRAM
RG
CLK
OUTx_FILT
AVDD
VLDO
MUX
INPx
INMx
ó 4
A1
A2
+
offset
STE
VSENSEPx
VSENSEMx
SDIN
SDOUT
SCLK
RDY
Patient
&
ESD
ADC
(16bit, 860SPS)
MUX
Full Wave
Rectifier
A3
SPI
MUX
Protection
IOUTPx
I/Q
Demodulator
Patient
&
Zs
ESD
Protection
MUX
IOUTMx
0.9V
VDAC_FILT_IN
1.5k +/- 20%
CLK
DAC
(6bit)
DDS
(10bits)
Reference
LDO
VDACOUT
AVSS
AUXx
VREF VLDO
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
SPI is a trademark of Motorola Inc..
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
AFE4300
SBAS586B –JUNE 2012–REVISED JUNE 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE INFORMATION(1)
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or visit
the device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range (unless otherwise noted).
AFE4300
–0.3 to +4.1
–0.3 to AVDD + 0.3
±2
UNIT
V
AVDD to AVSS
Any pin
Voltage range
V
Diode current at any device pin
mA
°C
°C
Rh
V
Maximum operating junction temperature, TJ max
Storage temperature range, Tstg
Storage humidity
+105
–25 to +85
10% to 90%
2000
Humand body model (HBM)
Charged device model (CDM)
Electrostatic discharge
ratings
1000
V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-
maximum rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
V
AVDD
AVSS
fCLK
Supply voltage
2
3.6
Supply voltage
0
1
V
External clock input frequency
Ambient temperature range
MHz
°C
TA
0
+70
THERMAL INFORMATION
AFE4300
THERMAL METRIC(1)
PN (TQFP)
80 PINS
50.5
UNITS
θJA
Junction-to-ambient thermal resistance
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
14.2
25.3
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.5
ψJB
24.9
θJCbot
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
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SBAS586B –JUNE 2012–REVISED JUNE 2013
ELECTRICAL CHARACTERISTICS: Front-End Amplification (Weight-Scale Signal Chain)
Over operating free-air temperature range, AVDD – AVSS = 3 V, G1 = 183, and G2 = 1, unless otherwise noted.
AFE4300
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BRIDGE SUPPLY
V(VLDO)
Output voltage (bridge supply voltage)
Output current
1.7
V
Current capability
20
mA
mA
ms
IO
Short-circuit protection
100
1
tSTBY
Enable/disable time
With 470 nF cap on VLDO pin
AMPLIFICATION CHAIN
Offset error
With offset correction DAC disabled
With offset correction DAC diasbled
80
0.25
µV
µV/°C
fA
Offset drift vs temperature
Input bias current
±70
Input offset current
±140
68
fA
Vn
Noise voltage, equivalent input
Noise current, equivalent input
Differential input impedance
Common-mode input impedance
Input common-mode rejection ratio
G1 = 183, 0.01 Hz < f < 2 Hz
f = 10 Hz
nVrms
fA/√Hz
GΩ || pF
GΩ || pF
dB
In
100
zid
100 || 4
100 || 8
95
zic
CMRR
G1 = 183
From input to digital output (including
ADC)
INLWS
Gain nonlinearity
0.01
% of FS(1)
First-stage gain equation
Power-up time
(1 + 2 × 100k / RG)
1
V/V
ms
kΩ
tup
From power up to valid reading
R1
Internal feedback resistors
Second-stage gain settings
Total gain error
95
100
1, 2, 3, 4
±5%
105
Gain2
Offset DAC number of bits
Full-scale offset DAC output current
6
Bits
µA
IDAC
±6.5
(1) FS = full-scale.
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SBAS586B –JUNE 2012–REVISED JUNE 2013
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ELECTRICAL CHARACTERISTICS: Body Composition Measurement Front-End
Over operating free-air temperature range, AVDD – AVSSS = 3 V, unless otherwise noted.
AFE4300
PARAMETER
WAVEFORM GENERATOR
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DAC resolution
6
1
1
Bits
V(PP)
DAC full-scale voltage
DAC sample rate
Common mode voltage = 0.9 V
MSPS
–3 dB bandwidth of the 2nd-order low-pass
filter
BWLPF
R1
150 ±30
kHz
Internal current-setting resistor
1.5 ±20%
kΩ
DEMODULATION CHAIN
Input Impedance
50
kΩ
From impedance to dc output of
demodulator, IQ Mode & FWR mode
Gain
0.72
V/kΩ
Gain error (without calibration)
Offset error (without calibration)
Common-mode rejection ratio
FWR mode and I/Q mode
FWR mode and I/Q mode
2.5
±5
% of FS
mV
CMRR
75
dB
0Ω to 1.25 kΩ range
0Ω to 2.50 kΩ range
0.15
3
% of FS
% of FS
Nonlinearity
Internal resistor = 5 kΩ,
external capacitor = 4.7 µF
BWDEMOD
Rectifier bandwidth
3.5 ±20%
15
Hz
20-kHz waveform, noise integrated from
0.01 Hz to 2 Hz
Output noise at rectifier output
µVrms
4
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SBAS586B –JUNE 2012–REVISED JUNE 2013
ELECTRICAL CHARACTERISTICS: Analog-to-Digital Converter
Over operating free-air temperature range, AVDD – AVSS = 3 V, unless otherwise noted.
AFE4300
PARAMETER
ANALOG-TO-DIGITAL CONVERTER
ADC input voltage range
TEST CONDITIONS
MIN
TYP
MAX
UNIT
At the input of the ADC (after PGA)
At the input of the PGA
2 × VREF
VADC / Gain
1.7
V
VIN
Full-scale input voltage
Reference voltage
V
VREF
V
RON(mux)
Input multiplexer on-resistance
AAUX input impedance
Output data rate
0 V ≤ VAAUX ≤ AVDD
6
kΩ
4
MΩ
SPS
Bits
LSB
LSB
LSB
fDR
8
860
Resolution
16
EI
Integral linearity error
Best fit, DR = 8 SPS
Differential inputs
1
±1
EO
Offset error
Single-ended inputs
±3
EG
Gain error
0.05%
AVDD / 3
1.5
VBAT_MON
IBAT_MON
IBAT_MON_ACC
Battery monitor output
Battery monitor current consumption
Battery monitor accuracy
V
µA
±2%
POWER CONSUMPTION
Power-down current
0.25
100
540
970
110
µA
µA
µA
µA
µA
Sleep-mode current
Supply Current
Weight-scale chain measurements
Body-composition measurements
Auxillary-channel measurements
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, AVDD – AVSS = 3V (unless otherwise noted)
PARAMETER
DIGITAL INPUT/OUTPUT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIH
VIL
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Input current
0.75AVDD
AVSS
AVDD
V
V
0.25AVDD
VOH
VOL
IIN
IOL = 1 mA
0.8AVDD
GND
V
IOL = 1 mA
0.2AVDD
V
±30
µA
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SPI TIMING CHARACTERISTICS
tCSH
STE
tSCLK
tCSSC
tSPWH
tSCCS
SCLK
tDIHD
tSPWL
tSCSC
tDIST
SDIN
tDOHD
tCSDOD
tCSDOZ
Hi-Z
tDOPD
Hi-Z
SDOUT
Figure 1. Serial Interface Timing
TIMING REQUIREMENTS: SERIAL INTERFACE TIMING
At TA = 0°C to +70°C and VDD = 2 V to 3.6 V, unless otherwise noted.
SYMBOL
tCSSC
tSCLK
DESCRIPTION
MIN
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STE low to first SCLK setup time(1)
SCLK period
100
250
100
100
50
tSPWH
tSPWL
tDIST
SCLK pulse width high
SCLK pulse width low
Valid SDIN to SCLK falling edge setup time
Valid SDIN to SCLK falling edge hold time
SCLK rising edge to valid new SDOUT propagation delay(2)
SCLK rising edge to DOUT invalid hold time
STE low to SDOUT driven propagation delay
STE high to SDOUT Hi-Z propagation delay
STE high pulse
tDIHD
50
tDOPD
tDOHD
tCSDOD
tCSDOZ
tCSH
50
0
100
100
200
100
tSCCS
Final SCLK falling edge to STE high
(1) STE can be tied low.
(2) DOUT load = 20 pF || 100 kΩ to DGND.
6
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SBAS586B –JUNE 2012–REVISED JUNE 2013
PIN CONFIGURATION
PN PACKAGE
TQFP-80
(TOP VIEW)
1
2
60
59
58
57
56
AVSS
INP1
AVSS
RDY
INM1
INP2
3
SCLK
SDIN
4
SDOUT
INM2
AVSS
INP_R
INM_R
AVSS
INP3
5
6
55 NC
7
54 STE
8
53
RESET
9
52 NC
10
11
12
13
14
15
16
17
18
19
20
51 AUX2
50
49
48
47
46
45
44
43
42
41
OUTP_Q_FILT
OUTM_Q_FILT
OUTP_FILT
OUTM_FILT
AVDD
INM3
INP4
INM4
AVSS
AUX1
AVSS
VLDO
NC
VREF
NC
AVDD
VSENSEM_R0
VSENSEM_R1
DAC_OUT
DAC_FILT_IN
PIN ASSIGNMENTS
PIN
INPUT/
NAME
AAUX1
AAUX2
AVDD
NUMBER
15
OUTPUT
DESCRIPTION
I
I
Auxiliary input to the ADC
Auxiliary input to the ADC
Supply (3.3 V)
51
18, 46, 80
1, 6, 9, 14, 21, 32,
45, 60, 77
AVSS
CLK
—
Ground
79
20
19
I
I
1-MHz clock
DAC_FILT_IN
DACOUT
Current generator input. Connect ac blocking capacitor between this pin and pin 19.
DAC output. Connect ac blocking capacitor between this pin and pin 20.
O
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PIN ASSIGNMENTS (continued)
PIN
INPUT/
NAME
INM1 to INM4
INP1 to INP4
INM_R
NUMBER
OUTPUT
DESCRIPTION
3, 5, 11, 13
I
Instrumentation amplifier differential inputs for each of the four weight-scale channels
2, 4, 10, 12
I
8
7
—
—
Connection of gain setting resistor for the instrumentation amplifier
Current source output to electrodes
INP_R
22, 23, 24, 25, 26,
27
IOUT5 to IOUT0
NC
O
43, 44, 52, 55, 61,
62, 63, 64, 65, 66,
67, 68, 69, 70, 71,
72, 73, 74, 75, 76,
78
—
Do not connect
OUTM_I_FILT
OUTP_I_FILT
OUTM_Q_FILT
OUTP_Q_FILT
RDY
47
48
—
—
—
—
O
O
O
I
I channel demodulator low pass filter, connect 10 µF between both pins
49
Q channel demodulator low pass filter, connect 10 µF between both pins
Data ready
50
59
RN1, RN0
RP1, RP0
RST
30, 31
28, 29
53
Current source output to calibration resistors
Reset. 0: reset, 1: normal operation.
SPI enable. 0: shift data in, 1: disable.
Clock to latch input data (negative edge latch)
Serial data input
STE
54
I
SCLK
58
I
SDIN
57
I
SDOUT
56
O
O
O
Serial data output
VLDO
16
LDO output to supply the bridges (~1.7 V), Connect 470 nF to AVSS
Reference voltage (connect 470 nF to AVSS)
VREF
17
VSENSEN_R1,
VSENSEN_R0
41, 42
39, 40
I
I
I
Input to differential amplifier from calibration resistors
Input to differential amplifier from electrode
VSENSEP_R1,
VSENSEP_R0
VSENSE5 to
VSENSE0
33, 34, 35, 36, 37,
38
8
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SBAS586B –JUNE 2012–REVISED JUNE 2013
TYPICAL CHARACTERISTICS
All measurements at room temperature with AVDD = 3 V, unless otherwise specified.
80
70
60
50
40
30
20
10
0.05
Input−Referred with Gain = 183
WS Gain = 183
0.04
0.03
0.02
0.01
0
−0.01
−0.02
−0.03
−0.04
−0.05
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
−10
−5
0
5
10
Frequency (Hz)
Differential Input Voltage (mV)
G001
G004
Figure 2. Weight-Scale Chain Noise vs Frequency
Figure 3. Weight-Scale Chain Nonlinearity
1.75
20
FWR Mode
IQ Mode
Data Based on 300 Devices Including R1 Variation
18
16
14
12
10
8
1.5
1.25
1
0.75
0.5
0.25
0
6
4
2
0
0
500
1000
1500
2000
2500
G006
Resistance (Ω)
DAC Output Current (µArms)
G005
Figure 4. BCM DAC Output Current Distribution
Figure 5. Body Impedance to Output Voltage Transfer Curve
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OVERVIEW
The AFE4300 is a low-cost, integrated front-end designed for weight scales incorporating body-composition
measurements. The AFE4300 integrates all the components typically used in a weight scale. It has two signal
chains: one for weight scale measurements and the other for body composition measurements. Both signal
chains share a 16-bit, delta-sigma converter that operates at a data rate of up to 860 SPS. This device also
integrates a reference and a low-dropout regulator (LDO) that generates a 1.7-V supply that can be used as the
excitation source for the load cells, thus simplifying ratiometric measurements. Both the signal chains use a
single DAC. The DAC is used to generate the dc signal for load-cell offset cancellation in the weight-scale chain.
The same DAC is also used to generate the sine-wave modulation signal for the body-composition signal chain.
Therefore, only one of the two signal chains can be activated at a time (using the apprpriate register bits).
Two unique features of the AFE4300 are that it provides an option for connecting up to four separate load cells,
and supports tetrapolar measurements with I/Q measurements.
AUX2
AUX1
VLDO
AVDD VREF
AVDD
11001
VLDO
1
0
10001
01001
REF
LDO
BAT_MON_EN
15[0], 15[7]
WS_PDB
9[0]
WEIGHT SCALE
BRIDGE_SEL
15[2:1]
80k, 160k, 240k, 320k
A+
80k
1
0
ADC_REF_SEL
16[6:5]
INP_R
INM_R
+/-
6.5uA
Current
DAC 6bit
100K
00000
RG
100k
ADC_PD
1[7]
OFFSET_DAC_VALUE
13[5:0]
A1
A2
000
1
BRIDGE_SEL
15[2:1]
ADC
REF
80k, 160k, 240k, 320k
ADC
16b 860sps
A-
001
010
AVSS
80k
WS_PGA_GAIN
13[14:13]
16
1
ADC_CONV_MODE
1[15]
OPAMP1
1.5k +/- 20%
R1
`
2nd order
150KHz
LPF
3
DAC 6bit
1MSPS
Clock
DDS
optional
IOUT5
IOUT4
IOUT3
IOUT2
IOUT1
IOUT0
RP1
ADC_MEAS_MODE
1[13:11]
Divider
0.9V
1
(ó4)
1
DAC_PD
9[3]
00011
00101
BCM_DAC_FREQ
14[9:0]
ADC_DATA_RATE
1[6:4]
RP0
ISW_MUX
10[15:0]
Decimation
Filter
External clock
Clock
Divider
DcoemnarFilt
3
IQ_DEMOD_CLK_DIV_FAC
15[13:11]
I/Q_DEMOD_CLK
RN1
RN0
1
0
ADC_DATA_RESULT
0[15:0]
VSENSE5
VSENSE4
5
VSENSE3
2R
VSENSE2
R
VSENSE1
1
VSENSE0
PERIPHERAL_SEL
16[4:0]
SPI
IQ_MODE_ENABLE
12[11]
VSENSERP1
VSENSERP0
5K
5K
VSW_MUX
11[15:0]
I
I/Q DEMODULATOR
OR
External clock
5K
5K
FULL-WAVE RECTIFIER
R
2R
VSENSERN1
VSENSERN0
Q
PDB
9[2]
BCM_PDB
9[1]
BODY COMPOSITION METER
10uF
10uF
Figure 6. Block Diagram
10
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SBAS586B –JUNE 2012–REVISED JUNE 2013
THEORY OF OPERATION
This section describes the details of the AFE4300 internal functional elements. The analog blocks are reviewed
first, followed by the digital interface. The theory behind the body-composition measurement using the full-wave
rectification method and the I/Q demodulation method are also described. The analog front-end is divided in two
signal chains: a weight-measurement chain and a body-composition measurement front-end chain; both use the
same 16-bit ADC and 6-bit DAC.
Throughout this document:
•
•
•
•
•
fCLK denotes the frequency of the signal at the CLK pin.
tCLK denotes the period of the signal at the CLK pin.
fDR denotes the output data rate of the ADC.
tDR denotes the time period of the output data.
fMOD denotes the frequency at which the modulator samples the input.
WEIGHT-SCALE ANALOG FRONT-END
Figure 7 shows a top-level view of the front-end section devoted to weight-scale measurement. The weight-scale
front-end has two stages of gain, with an offset correction DAC in the second gain stage. The first-stage gain is
set by the external resistor and the second-stage gain is set by progamming the internal registers. For access
and programming information, see the REGISTERS section.
AFE4300
VLDO
WEIGHT SCALE
WS_PDB
9[0]
BRIDGE_SEL
15[2:1]
80k, 160k, 240k, 320k
RFB2
A+
80k
RFB1
Current
DAC 6bit
100K
+/-6.5µ A
To Digitizer
100k
RFB1
OFFSET_DAC_VALUE
13[5:0]
RFB2
BRIDGE_SEL
15[2:1]
A-
80k
80k, 160k, 240k, 320k
WS_PGA_GAIN
13[14:13]
Figure 7. Weight-Scale Front-End
Though not shown in the diagram, an antialiasing network is required in front of the INA to filter out
electromagnetic interference (EMI) signals or any other anticipated interference signals. A simple RC network
should be sufficient, combined with of the attenuation provided by the on-chip decimation filter.
An internal reference source provides a constant voltage of 1.7 V at the VLDO output to drive the external bridge.
The output of the bridge is connected to an INA (first stage). The first-stage gain (A1) is set by the external
resistor (RG) and the 100-kΩ (±5%) internal feedback resistors (RFB1) as shown in Equation 1:
A1 = (1 + 2 ´ 100k / RG)
(1)
The second-stage gain (A2) is controlled by feedback resistors RFB2, which have four possible values: 80 kΩ, 160
kΩ, 240 kΩ, and 320 kΩ. Because the gain is RF / 80 kΩ, the gain setting can be 1, 2, 3, or 4. See the
REGISTERS section for details on setting the appropriate register bits.
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Input Common mode Range
The usable input common mode range of the weight-scale front-end depends on various parameters, including
the maximum differential input signal, supply voltage, and gain. The output of the first-stage amplifier must be
within 250 mV of the power supply rails for linear operation. The allowed common-mode range is determined by
Equation 2:
GAIN´ VMAX _DIFF
GAIN´ VMAX _DIFF
AVDD - 0.25 -
> CM > AVSS + 0.25 +
2
2
Where:
•
•
VMAX_DIFF = maximum differential input signal at the input of the first gain stage,
CM = Common-mode range.
(2)
For example, If AVDD = 2 V, the first stage gain = 183, and VMAX_DFF = 7.5 mV (dc + signal), then:
1.06 V > CM > 0.936 V
Input Differential Dynamic Range
The max differential (INP – INN) signal depends on the analog supply, reference used in the system. This range
is shown in Equation 3:
VREF
GAIN
VREF
GAIN
MAX(INP - INN) <
; Full-Scale Range = 2 ´
(3)
The gain in Equation 3 is the product of the gains of the INA and the second-stage gain. The full-scale input from
the bridge signal typically consists of a differential dc offset from the load cell plus the actual weight signal.
Having a high gain in the first stage helps minimize the effect of the noise addition from the subsequent stages.
However, make sure to choose a gain that does not saturate the first stage with the full-scale signal. Also, the
common-mode of the signal must fall within the range, as per Equation 2.
Offset Correction DAC
One way to increase the dynamic range of the signal chain is by calibrating the inherent offset of the load cell
during the initial calibration cycle. The offset correction is implemented in the second stage with a 6-bit differential
DAC, where each output is a mirror of the other and can source or sink up to 6.5 µA. The effect at the output of
the second stage is an addition of up to ±6.5 µA × 2 × RFB2. This is equivalent to a voltage at the input of the
second stage (A+ / A–) of up to ±6.5 µA × 2 × 80 kΩ = ±1 V, when RFB2 = 80 kΩ. Notice that this has no effect in
avoiding the first-stage saturation. Because the offset correction DAC is a 6-bit DAC, the offset compensation
step is 2 V/26 = 31.2 mV when referred to the input of the second stage.
Offset Correction Example
As an example, use a bridge powered from 1.7 V with 1.5 mV/V sensitivity and a potential offset between –4 mV
and 4 mV. Worst case, the maximum signal is 4 mV of offset plus 1.7 × 1.5 mV/V = 2.55 mV of signal, for a total
of 6.55 mV. The bridge common-mode voltage is ~0.85 V. The maximum excursion is 0.85 V – 0.25 V = 0.6 V
(bottom rail) single-ended, on each output (A+ or A–). Therefore, ±1.2 V differentially at the output of the first
stage prevents saturation. This result means that the first stage can have up to a gain of 1.2 V / 6.55 mV = 183.
Using this same example, the swing at the output of the first stage corresponding only to the potential offset
range is 183 × ±4 mV = ±0.732 V. This swing can be completely removed at the output of the second stage by
the offset correction (because it has a ±1-V range) except for a maximum error of 31.2 mV.
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BODY COMPOSITION MEASUREMENT ANALOG FRONT-END
Body composition is traditionally obtained by measuring the impedance across several points on the body and
matching the result in a table linking both the impedance measured and the body composition. This table is
created by each manufacturer and is usually based on age group, sex, weight, and other parameters.
The body impedance that we want to measure, Z(f), is a function of the excitation frequency, and can be
represented by polar or cartesian notations:
q f
( ) = R f + jX f
j
Z f
( )
=
Z f .e
( )
( ) ( )
where:
•
•
|Z| = sqrt(R2 + X2)
θ = arctg(X/R)
(4)
The AFE4300 provides two options for body impedance measurement: ac rectification and I/Q demodulation.
Both options work by injecting a sinusoidal current into the body and measuring the voltage across the body. The
portion of the circuit injecting the current into the body is the same for each of those options. The difference,
however, lies in how the measured voltage across the impedance is processed to obtain the final result.
AC Rectification
Figure 8 shows the portion of the AFE4300 devoted to body composition measurement in the RMS detector
mode.
AFE4300
2nd order
DAC 6bit
1MSPS
R1
DDS
150KHz
LPF
OPAMP1
IOUT5
IOUT4
IOUT3
IOUT2
IOUT1
IOUT0
1
1
DAC_PD
9[3]
DAC_FREQ
14[9:0]
RP1
RP0
To Digitaizer
ISW_MATRIX
10[15:0]
RN1
RN0
VSENSE5
VSENSE4
VSENSE3
VSENSE2
VSENSE1
2R
R
R
VSENSE0
VSENSERP1
VSENSERP0
5K
5K
R
R
VSW_MATRIX
11[15:0]
Demodulator
R
R
2R
VSENSERN1
VSENSERN0
BCM_PDB
9[1]
BODY COMPOSITION METER
Figure 8. BCM in AC Rectifier Mode
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The top portion of Figure 8 represents the current-injection circuit. A direct digital synthesizer (DDS) generates a
sinusoidal digital pattern with a frequency obtained by dividing a 1-MHz clock with a 10-bit counter. The digital
pattern drives a 6-bit, 1-MSPS DAC. The output of the DAC is filtered by a 150-kHz, second-order filter to
remove the images, followed by a series external capacitor to block the dc current and avoid any dc current
injection into the body. The output of the filter (after the dc blocking capacitor) drives a resistor setting the
amplitude of the current to be injected in the body, as shown in Equation 5:
I t = VDAC / R1= A sin w t
( )
( )
0
(5)
The tolerance of the resistor is ±20%; therefore, the resistor and the DAC amplitude are set so that the current
injected is 375 µArms when all the elements are nominal. With a +20% error, the source is 450 µArms, and still
below the 500 µArms limit.
Current flows into the body through an output analog multiplexer (mux) that allows the selection of up to six
different contact points on the body. The same mux allows the connection of four external impedances for
calibration. The current crosses the body impedance and a second mux selects the return path (contact) on the
body, closing the loop to the output of the amplifier.
At the same time that the current is injected, a second set of multiplexers connects a differential amplifier across
the same body impedance in order to measure the voltage drop created by the injected current, shown by
Equation 6:
v(t) = A Z sin(w0t + q)
where Z and θ are the module and phase of the impedance at ω0, respectively.
(6)
The output of the amplifier is routed to a pair of switches that implement the demodulation at the same frequency
as the excitation current source in order to drive the control of those switches. This circuit performs a full-wave
rectification of the differential amplifier output and a low-pass filter at its output, recovers the dc level, and finally
routes it to the same 16-bit digitizer used in the weight-scale chain.
2A Z
2
T
DC =
A | Z | sin w t + q dt =
( 0 )
p
T/2
(7)
Ultimately, the dc output is proportional to the module of the impedance. The proportionality factor can be
obtained through calibration with the four external impedances. Although, with one single frequency or
measurement, only the module of the impedance can be obtained; two different frequencies could be used to
obtain both the real and the imaginary parts.
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I/Q Demodulation
The AFE4300 includes a second circuit that with a single frequency measurement, obtains both the real and the
imaginary portions, as shown in Figure 9. As explained previously, the portion of the circuit injecting the current
into the body is the same for both configurations. Therefore, the circuit is the same in Figure 8 and Figure 9. The
difference between them is that an I/Q demodulator is used in this second approach, as shown in Figure 9.
AFE4300
2nd order
DAC 6bit
1MSPS
R1
DDS
150KHz
LPF
OPAMP1
IOUT5
IOUT4
IOUT3
IOUT2
IOUT1
IOUT0
RP1
1
1
DAC_PD
9[3]
DAC_FREQ
14[9:0]
To Digitaizer
RP0
ISW_MATRIX
10[15:0]
External clock
Clock
Divider
IQ_DEMOD_CLK_DIV_FAC
15[13:11]
RN1
RN0
To Digitaizer
VSENSE5
VSENSE4
VSENSE3
R
2R
R
VSENSE2
VSENSE1
VSENSE0
VSENSERP1
VSENSERP0
R
5K
VSW_MATRIX
11[15:0]
I/Q
R
5K
Demodulator
R
R
R
2R
VSENSERN1
VSENSERN0
5K
5K
R
R
R
BCM_PDB
9[1]
BODY COMPOSITION METER
Figure 9. BCM in I/Q Demodulator Mode
As with the case of the RMS detector, a differential amplifier measures the voltage drop across the impedance,
as shown in Equation 8:
v(t) = A Z sin(w0t + q)
where:
•
•
Z = the module of the impedance at ω0
θ = phase of the impedance at ω0
(8)
The I/Q demodulator takes the v(t) signal and outputs two dc values. These two values are used to extract the
impedance module and phase with a single frequency measurement. Figure 9 shows the block diagrm of the
implementation. Using the I/Q demodulator helps reduce power consumption while yielding excellent
performance. The local oscillator (LO) signals for the mixers are generated from the same clock driving the
DDS/DAC and are of the same phase and frequency as the sinusoidal i(t) (see Equation 5). The LO signals
directly control the switches on the in-phase (I) path, and after a delay of 90° degrees, control the switches on
the quadrature (Q) path. This switching results in multiplying the v(t) signal by a square signal swinging from –1
to 1. Breaking down the LO signal into Fourier terms, we have Equation 9:
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4
1
1
LOI(t) = (sin(w0t) + sin(3w0t) + sin(5w0t) +...)
5
p
3
(9)
Therefore, the output voltage of the mixer is as shown in Equation 10:
4
1
1
I(t) = A Z (sin(w t + q)sin(w t) + sin(w t + q)sin(3w t) + sin(w t + q)sin(5w t) +...)
5
0
0
0
0
0
0
p
3
Where I(t) = in-phase output (not to be confused with i(t), the current injected in the impedance).
Applying fundamental trigonometry gives Equation 11:
(10)
(11)
1
1
sin a sin b = - cos(a + b) + cos(a - b)
Each product of sinusoids can be broken up in an addition of two sinusoids. Equation 12 shows the first term:
1
1
1
1
sin(w0t + q)sin(w0t) = cos(w0t + q - w0t) - cos(w0t + w0t + q) = cos(q) - cos(2w0t + q)
(12)
Equation 13 shows the 2nd product:
1
1
1
1
sin(w0t + q)sin(3w0t) = cos(w0t + q - 3w0t) - cos(3w0t + w0t + q) = cos(-2w0t + q) - cos(4w0t + q)
(13)
And so on. Performing the same analysis on the Q side, the output voltage of the mixer is shown in Equation 14:
4
1
1
Q(t) = A Z (sin(w0t + q)cos(w0t) + sin(w0t + q)cos(3w0t) + sin(w0t + q)cos(5w0t) +...)
5
p
3
(14)
(15)
(16)
Agiain, applying fundamental trigonometry gives Equation 15:
1
1
sin a cos b = sin(a + b) + sin(a - b)
Each of the products can be broken up into sums. Starting with the first product, as shown in Equation 16:
1
1
sin(w0t + q)cos(w0t) = sin(2w0t + q) + sin(q)
And so on. Note that on I(t) as well as on Q(t), all the terms beyond the cutoff frequency of the low-pass filter at
the output of the mixers (setup by the two 1-kΩ resistors and an external capacitor) are removed, leaving only
the dc terms, giving Equation 17 for IDC and Equation 18 for QDC
:
2A Z
IDC
=
cos(q) = K Z cos(q)
p
(17)
(18)
2A Z
QDC
=
sin(q) = K Z sin(q)
p
In reality, the LO amplitude is not known (likely, not ±1) and affects the value of K in Equation 17 and
Equation 18. Solving these two equations gives Equation 19:
QDC
q = arctan
IDC
1
2
IDC + QDC
2
Z =
K
(19)
In order to account for all the nonidealities in the system, the AFE4300 also offers four extra terminals on the
driving side (two to drive, and two for the currents to return) and four extra terminals on the receive/differential-
amplifier side. As with RMS mode, these spare terminals allow for connection of up to four external calibration
impedances, and they also compute K.
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DIGITIZER
The digitizer block includes an analog mux and a 16-bit sigma-delta ADC.
Multiplexer
There are two levels of analog mux. The first level selects from among the outputs of the weight scale, the body
composition function, two auxiliary inputs, and the battery monitor. A second mux is used to obtain the
measurement of the outputs coming from the first mux, either differentially or with respect to ground (single-
ended). Note that when measuring single-ended inputs, the negative range of the output codes are not used. For
battery or AVDD monitoring, an internal 1/3 resistor divider is included that enables the measurement using only
one reference setting for any battery voltage, thus simplifying the monitoring routine.
Analog-to-Digital Converter
The 16-bit, delta-sigma, ADC operates at a modulator frequency of 250 kHz with an fCLK of 1 MHz. The full-scale
voltage of the ADC is set by the voltage at its reference (VREF). The reference can be either the LDO output (1.7
V) for the weight-scale front-end or the internally-generated reference signal (1.7 V) for the BCM front-end.
The decimation filter at the output of the modulator is a single-order sinc filter. The decimation rate can be
programmed to provide data rates from 8 SPS to 860 SPS with an fCLK of 1 MHz. Refer to the
ADC_CONTROL_REGISTER1 register in the REGISTERS section for details on programming the data rates.
Figure 10 shows the frequency response of the digital filter for a data rate of 8 SPS. Note that the modulator has
pass band around integer multiples of the modulator sampling frequency of 250 kSPS. Set the corner frequency
of the antialiasing network before the INA so that there is adequate attenuation at the first multiple of the
modulator frequency.
0
Data Rate = 8 SPS
-10
-20
-30
-40
-50
-60
-70
-80
1
10
100
1k
10k
Input Frequency (Hz)
Figure 10. Frequency Response
The output format of the ADC is twos complement binary. Table 1 describes the output code versus the input
signal, where full-scale (FS) is equal to the VREF value.
Table 1. Input Signal Versus Ideal Output Code
INPUT SIGNAL, VIN
(AINP – AINN)
≥ FS (215 – 1)/215
+FS/215
IDEAL OUTPUT CODE
7FFFh
0001h
0
0
–FS/215
FFFFh
8000h
≤ –FS
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Operating Modes
The digitizer of the AFE4300 operates in one of two modes: continuous-conversion or single-shot. In Continuous-
Conversion mode, the AFE4300 continuously performs conversions. Once a conversion has been completed, the
AFE4300 places the result in the Conversion register and immediately begins another conversion. In Single-Shot
mode, the AFE4300 waits until the ADC_PD bit of ADC_CONTROL_REGISTER1 is set high. Once asserted, the
bit is set to '0', indicating that a conversion is currently in progress. Once conversion data are ready, the
ADC_PD bit reasserts, and the device powers down. Writing a '1' to the ADC_PD bit during a conversion has no
effect.
RESET AND POWER-UP
After power up, the device needs to be reset to get all the internal registers to their default state. Resetting the
device is done by applying a zero pulse in the RST line for more than 20 ns after the power is stable for 5 ms.
After 30 ns, the first access can be initiated (first falling edge of STE). As part of the reset process, the AFE4300
sets all of the register bits to the respective default settings. Some of the register bits must be written after reset
and power up for proper operation. Refer to the REGISTERS section for more details. By default, the AFE4300
enters into a power-down state at start-up. The device interface and digital are active, but no conversion occurs
until the ADC_PD bit is written to. The initial power-down state of the AFE4300 is intended to relieve systems
with tight power-supply requirements from encountering a surge during power-up.
DUTY CYCLING FOR LOW POWER
For many applications, improved performance at low data rates may not be required. For these applications, the
AFE4300 supports duty cycling that can yield significant power savings by periodically requesting high data-rate
readings at an effectively lower data rate. For example, an AFE4300 in power-down mode with a data rate set to
860 SPS could be operated by a microcontroller that instructs a single-shot conversion every 125 ms (8 SPS).
Because a conversion at 860 SPS only requires approximately 1.2 ms, the AFE4300 automatically enters power-
down mode for the remaining 123.8 ms. In this configuration, the digitizer consumes about 1/100th the power of
the digitizer when operated in Continuous-Conversion mode. The rate of duty cycling is completely arbitrary and
is defined by the master controller.
SERIAL INTERFACE
The SPI™-compatible serial interface consists of either four signals (STE, SCLK, SDIN, and SDOUT) or three
signals (in which case, STE can be tied low). The interface is used to read conversion data, read from and write
to registers, and control AFE4300 operation. The data packet (between falling and rising edge of STE) is 24 bits
long and is serially shifted into SDIN with the MSB first. The first eight bits (MSB) represent the address of the
register being accessed and last 16 bits (LSB) represent the data to be stored or read from that address. For the
eight bits address, the lower five bits [20:16] are the real address bits. Bit 21 is the read and write bit.
•
'0' in bit 21 defines a write operation of the 16 data bits [15:0] into the register defined by the address bits
[20:16].
•
'1' in bit 21 triggers a read operation of the register defined by the address bits [20:16]. The data are output
into SDOUT with every rising edge of SCLK, starting at the ninth rising edge. At the same time, data in SDIN
are shifted inside the 16 data bits of that given register. Note that everytime a register is read, it must be
rewritten except while reading the data output register.
SPI Enable (STE)
The STE pin selects the AFE4300 for SPI communication. This feature is useful when multiple devices share the
serial bus. STE must remain low for the duration of the serial communication. When STE is taken high, the serial
interface is reset, and SCLK is ignored.
Serial Clock (SCLK)
The SCLK pin features a Schmitt-triggered input and is used to clock data on the DIN and RDY pins into and out
of the AFE4300. Even though the input has hysteresis, it is recommended to keep SCLK as clean as possible to
prevent glitches from accidentally shifting the data. When the serial interface is idle, hold SCLK low.
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Data Input (SDIN)
The data input pin (SDIN) is used along with SCLK to send data to the AFE4300 (opcode commands and
register data). The device latches data on SDIN on the falling edge of SCLK. The AFE4300 never drives the
SDIN pin. Note that everytime a register is read, it must be rewritten, except while reading the data output
register.
Data Output (SDOUT)
The data output and data ready pin (RDY) are used with SCLK to read conversion and register data from the
AFE4300. In Read Data Continuous mode, RDY goes low when conversion data are ready, and goes high 8 μs
before the data ready signal. Data on RDY are shifted out on the rising edge of SCLK. If the AFE4300 does not
share the serial bus with another device, STE may be tied low. Note that every time a register is read, it must be
rewritten, except while reading the data output register.
Data Ready (RDY)
RDY acts as a conversion ready pin in both Continous-Conversion mode and Single-Shot mode. When in
Continuous-Conversion mode, the AFE4300 provides a brief (~8 μs) pulse on the RDY pin at the end of each
conversion. In Single-Shot mode, the RDY pin asserts low at the end of a conversion. Figure 11 and Figure 12
show the timing diagram for these two modes.
STE
SCLK
SDIN
Activate single
shot mode (1)
Read ADC
Data
RDY
(2)
tconv
SDOUT
ADC
Data
Note 1 : Write ADC_CONTROL_REGISTER[7] = 1, ADC_CONTROL_REGISTER1[15] = 1,
Note 2 : tCONV = Time to internally set ADC_CONTROL_REGISTER[15] to logic ”0‘, ADC power up, single conversion, ADC power down,
ADC_CONTROL_REGISTER1[15] internally set to logic ”1‘
Figure 11. Timing for Single-Shot Mode
STE
SCLK
SDIN
Read ADC
Data
Activate continuous
shot mode (1)
Read ADC
Data
8us
RDY
tDR
tDR
tDR
SDOUT
ADC
ADC
Data2
Data1
Note 1 : Write ADC_CONTROL_REGISTER[7] = 0
Figure 12. Timing for Continuous Mode
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REGISTERS
Register Map
Table 2 describes the registers of the AFE4300.
Table 2. Register Map
REGISTER NAME
CONTROL
ADDRESS
DESCRIPTION
DEFAULT
DEVICE CONTROLS
(See Description)
DAC_PD
0x09[14:13]
0x09[3]
Write '11' after power up and/or reset
Enable DAC for WS, BC measurements
Chip power down
00b
0b
PDB
0x09[2]
0b
DEVICE_CONTROL1
Body composition measurement front-end
power down
BCM_PDB
0x09[1]
0b
WS_PDB
0x09[0]
0x0F[7]
0x0F[0]
Weight-scale front-end power down
0b
0b
0b
BAT_MON_EN1
BAT_MON_EN2
Enables battery monitoring along with bit[0]
Enables battery monitoring along with bit[7]
DEVICE_CONTROL2
ADC CONTROLS
ADC_DATA_RESULT
(See Description)
ADC_CONV_MODE
ADC_MEAS_MODE
ADC_PD
0x00[15:0]
0x01[15]
ADC data result, read only register
Continuous-Conversion or Single-Shot mode
Single-Ended or Differential mode
ADC power down
0b
000b
1b
0x01[13:11]
0x01[7]
ADC_CONTROL_REGISTER1
ADC_CONTROL_REGISTER2
ADC_DATA_RATE
ADC_REF_SEL
0x01[6:4]
0x10[6:5]
0x10[4:0]
ADC data-rate control bits
100b
00b
Reference selection bits
PERIPHERAL_SEL
Peripheral selection bits
00000b
WEIGHT-SCALE MODES
DEVICE_CONTROL2
BRIDGE_SEL
WS_PGA_GAIN
0x0F[2:1]
0x0D[14:13]
0x0D[5:0]
Selects one of the four bridge inputs
PGA gain of weight-scale front-end
00b
00b
WEIGHT_SCALE_CONTROL
BCM CONTROLS
ISW_MUX
OFFSET_DAC_VALUE
Offset DAC setting for weight-scale front-end
000000b
ISW_MUXP
ISW_MUXM
0x0A[15:8]
0x0A[7:0]
Control for switches IOUTP and RP
Control for switches IOUTN and RN
0x00
0x00
Control for switches VSENSEP and
VSENSEP_R
VSENSE_MUXP
VSENSE_MUXM
0x0B[15:8]
0x0B[7:0]
0x00
0x00
VSENSE_MUX
Control for switches VSENSEN and
VSENSN_R
Sets the frequency of BCM excitation current
source
BCM_DAC_FREQ
IQ_MODE_ENABLE
DEVICE_CONTROL2
DAC_FREQ
0x0E[9:0]
0x0C[11]
0x00
0b
IQ_MODE_ENABLE
Enable IQ demodulator
IQ_DEMOD_CLK_DIV_
FAC
0x0F[13:11]
IQ Demodulator clock frequency
000b
MISCELLANEOUS REGISTERS
MISC_REGISTER1
(See Description)
(See Description)
(See Description)
0x02[15:0]
0x03[15:0]
0x1A[15:0]
Write 0x0000 after power up and/or reset
Write 0xFFFF after power up and/or reset
Write 0x0030 after power up and/or reset
0x8000
0x7FFF
0x0000
MISC_REGISTER2
MISC_REGISTER3
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ADC_DATA_RESULT (Address 0x00, Default 0x0000)
This register stores the most recent conversion data in twos complement format with the MSB in bit 15 and the
LSB in bit 0.
ADC_CONTROL_REGISTER1 (Address 0x01, Default 0x01C3)
This register is used in conjunction with ADC_PD (bit 7). Refer to the description of the ADC_PD bit for more
details.
15
14
1
13
12
11
10
0
9
0
8
1
7
6
5
4
3
0
2
0
1
0
0
0
ADC_CONV_
MODE
ADC_
PD
ADC_MEAS_MODE
ADC_DATA _RATE
Bit 15
ADC_CONV_MODE: ADC conversion mode/ADC single-shot conversion start.
This bit determines the operational status of the device. This bit can only be written when in the ADC power-down
mode. When read, this bit gives the status report of the conversion.
For a write status:
0 : No effect (default)
1 : Single-shot conversion mode
For a read status:
0 : Device currently performing a conversion
1 : Device not currently performing a conversion
Bit 14
Always write ‘1’.
Bits[13:11]
ADC_MEAS_MODE: ADC measurement mode selection.
These bits set the ADC measurements to be either single-ended or differential.
ADC_MEAS_MODE
ADC AINP, AINM
000 (default)
001
A1, A2 = differential (default)
A1, AVSS = single-ended
A2, AVSS = single-ended
010
Bits[10:8]
Bit 7
Always write '001'
ADC_PD: ADC Powerdown
This bit powers down the ADC_PGA and the ADC. By default, the ADC is powered down (ADC_PDN = '1').
For continuous convesion mode, this bit must to set to '0'.
For single-shot mode, this bit must be set to ‘1’ along with bit 15. During single-shot conversion mode, the device
automatically powers up the ADC, triggers one ADC conversion, and then powers down the ADC.
ADC_CONV_MODE (Bit 15)
ADC_PDN (Bit 7)
MODE
X
0
1
0
Continuous conversion
ADC PD
1 (default)
1 (default)
Single-shot
Bits[6:4]
ADC_DATA_RATE: Conversion rate select bits.
These bits select one of eight different ADC conversion rates. The data rates shown assume a master clock of 1 MHz.
000: 8 SPS
001: 16 SPS
010: 32 SPS
011: 64 SPS
100: 128 SPS (default)
101: 250 SPS
110: 475 SPS
111: 860 SPS
Bits[3:0]
Always write '0000'. At power up, these bits are set as '0011'.
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MISC_REGISTER1 (Address 0x02, Default 0x8000)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Bit 15
Always write ‘0’. At power up, this bit is set as '1'.
Not used, always write ‘0’. At power up, these bits are set as '0'.
Bits[14:0]
MISC_REGISTER2 (Address 0x03, Default 0x7FFF)
15
1
14
1
13
1
12
1
11
1
10
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
Bit 15
Always write ‘1’. At power up, this bit is set as '0'.
Always write ‘1’. At power up, these bits are set as '1'.
Bits[14:0]
DEVICE_CONTROL1 (Address 0x09, Default 0x0000)
15
0
14
1
13
1
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
3
2
1
0
0
DAC_PD PDB BCM_PDB WS_PDB
Bits[15]
Not used. Always write '0'.
Not used. Always write '1'.
Not used. Always write '0'.
Bits[14:13]
Bits[12:4]
Bit 3
DAC_PDB: Power down DAC.
This bit powers down the weight-scale front-end offset correction DAC and the BCM front-end current source DAC.
0: Power up DAC (default)
1: Power down DAC
Bit 2
PDB: Power down device.
This bit in conjunction with the other power-down bits determines the power state of the device.
0: Power down (default)
1: Power up of front-end
Bit 1
Bit 0
BCM_PDB: Body composition measurement front-end power-down bit.
0: Power down body compositionmeasurement front-end (default)
1: Power up body composition measurement front-end. Power down the weight scale when powering up the BCM.
WS_PDB: Weight-scale front-end power-down bit.
0: Power down weight-scale front-end (default)
1: Power up weight-scale front-end. Power down BCM when powering up the weight scale.
Table 3 shows the available power-down modes.
Table 3. Power-Down Modes
DAC_PDB
(Bit3)
PDB
(Bit 2)
BCM_PDB
(Bit 1)
WS_PDB
(Bit 0)
ADC_PD
(Bit 7, ADC Control Register)
MODE
Full device power down
Sleep mode
X
1
0
1
0
0
0
0
1
1
Weight-scale power down, body
composition measurement
0
1
1
0
0
Body composition measurement
power down, weight-scale
measurement
0
1
0
1
0
Weight-scale and body composition
measurement power down
0
1
0
0
0
(aux/battery measurement)
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ISW_MUX (Address 0x0A, Default 0x0000)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RP1
RP0
RN1
RN0
Bits[15:10]
Bits[9:8]
Bits[7:2]
Bits[1:0]
IOUTP[5:0]
These bits close the switches routing IOUTPx to the negative input of OPAMP1.
0: Switch is open (default)
1: Switch is closed
RP[1:0]
These bits close the switches routing the calibration signal to the negative input of OPAMP1.
0: Switch is open (default)
1: Switch is closed
IOUTN[5:0]
These bits close the switches routing IOUTNx to the output of OPAMP1.
0: Switch is open (default)
1: Switch is closed
RN[1:0]
These bits close the switches routing the calibration signal to the output of OPAMP1.
0: Switch is open (default)
1: Switch is closed
VSENSE_MUX (Address 0x0B, Default 0x0000)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bits[15:10]
Bits[9:8]
Bits[7:2]
Bits[1:0]
VSENSEPx[5:0]
These bits close the switches routing VSENSEPx to the positive input of the receive amplifier.
0: Switch is open (default)
1: Switch is closed
VSENSEP_Rx[1:0]
These bits close the switches routing the calibration signal to the positive input of the receive amplifier.
0: Switch is open (default)
1: Switch is closed
VSENSENx[5:0]
These bits close the switches routing VSENSENx to the negative input of the receive amplifier.
0: Switch is open (default)
1: Switch is closed
VSENSEM_Rx[1:0]
These bits close the switches routing the calibration signal to the negative input of the receive amplifier.
0: Switch is open (default)
1: Switch is closed
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IQ_MODE_ENABLE (Address 0x0C, Default 0x0000)
15
0
14
0
13
0
12
0
11
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
IQ_
MODE_
ENABLE
Bits[15:12]
Bit 11
Not used. Always write '0'.
IQ_MODE_ENABLE: Enable the I/Q demodulator.
This bit sets the impedece measurement mode to either full-wave rectifier mode or I/Q demodulator mode. For I/Q
Demodulator mode, the DAC_FREQ bits of the BCM_DAC_FREQ register and the IQ_DEMOD_CLK_DIV_FAC bits of
the DEVICE_CONTROL2 register must be set appropriately. Refer to the respective register section for more details.
0: Full-Wave Rectifier mode (default)
1: I/Q Demodulator mode
Bits[10:0]
Not used. Always write '0'.
WEIGHT_SCALE_CONTROL (Address 0x0D, Default 0x0000)
15
0
14
13
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
4
3
2
1
0
WS_PGA_GAIN
OFFSET_DAC_VALUE
Bit 15
Not used. Always write '0'.
Bits[14:13]
WS_PGA_GAIN: Sets the second-stage gain of the weight-scale front-end.
00: Gain = 1 (default)
01: Gain = 2
10: Gain = 3
11: Gain = 4
Bits[12:6]
Not used. Always write '0'.
Bit[5:0]
OFFSET_DAC_VALUE: Offset correction DAC setting.
These bits set the value for the DAC used to correct the input offset of the weight-scale front-end. The correction is
made at the second stage. The offset correction at the output of the first stage is given by OFFSET_DAC_VALUE ×
31.2 mV. Note that OFFSET_DAC_VALUE is a number from –32 to 31, in twos complement; default is '000000'.
BCM_DAC_FREQ (Address 0x0E, Default 0x0000)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
7
6
5
4
3
2
1
0
DAC8 DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 DAC0
Bits[15:9]
Bits[8:0]
Not used. Always write '0'.
DAC[8:0]: Sets the frequency of the BCM excitation current source.
The DAC output frequency is given by DAC[9:0] × fCLK / 1024, where fCLK is the frequency of the device input clock
(pin 79). All combinations of the DAC frequency can be used for the full-wave rectifier mode. However, only certain
combinations of the DAC frequency can be used for the IQ demodulator mode. Refer to the description of the
DEVICE_CONTROL2 register for more details.
For example, with fCLK = 1 MHz:
DAC = 0x00FF → 255 kHz
DAC = 0x0001 → 1 kHz
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DEVICE_CONTROL2 (Address 0x0F, Default 0x0000)
15
0
14
0
13
12
11
10
0
9
0
8
0
7
6
0
5
0
4
0
3
0
2
1
0
BAT_
MON_
EN1
BAT_
IQ_DEMOD_CLK_DIV_FAC
BRIDGE_SEL MON_
EN0
Bits[15:14]
Bits[13:11]
Not used. Always write '0'.
IQ_DEMOD_CLK_DIV_FAC: I/Q demodulator clock frequency.
The clock for the IQ demodulator (IQ_DEMOD_CLK signal) is internally generated from the device input clock (fCLK
)
by a divider controlled by this register. Note that the IQ_DEMOD_CLK should be four times the BCM_DAC_FREQ so
that it can generate the phases for the mixers (that is, IQ_DEMOD_CLK = fCLK / (IQ_DEMOD_CLK_DIV_FAC) =
BCM_DAC_FREQ × 4)
000: Divide by 1 (default)
001: Divide by 2
010: Divide by 4
011: Divide by 8
100: Divide by 16
Others: Divide by 32
Bit 7
BAT_MON_EN1: This bit (along with BAT_MON_EN0, bit 0) enables battery monitoring.
When disabled, the battery monitoring block is powered down to save power. See the description of BAT_MON_EN0,
bit 0.
Bits[6:3]
Bits[2:1]
Not used. Always write '0'.
BRIDGE_SEL: Selects one of the four input pairs to be routed to the weight-scale front-end.
00: Bridge 1 (INP1, INM1) connected to the weight-scale front-end (default)
01: Bridge 2 (INP2, INM2) connected to the weight-scale front-end
10: Bridge 3 (INP3, INM3) connected to the weight-scale front-end
11: Bridge 4 (INP4, INM4) connected to the weight-scale front-end.
Bit 0
BAT_MON_EN0: This bit along with BAT_MON_EN1 (Bit[7]) enables battery monitoring.
00: Monitor disabled (default)
11: Monitor enabled (AVDD / 3)
NOTE: The PERIPHERAL_SEL bits of the ADC_CONTROL_REGISTER2 must be set to '10001' in order to route the
battey monitor output to the ADC.
ADC_CONTROL_REGISTER2 (Address 0x10, Default 0x0000)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
5
4
3
2
1
0
ADC_REF_SEL
PERIPHERAL_SEL
Bits[15:7]
Bits[6:5]
Not used. Always write '0'.
ADC_REF_SEL[1:0]: Selects the reference for the ADC.
00: ADCREF connected to VLDO. Used for ratiometric weight-scale measurement (default).
01, 10: Do not use
11: ADCREF connected to VREF (internal voltage reference generator). Used for impedance measurement.
Bits[4:0]
PERIPHERAL_SEL[4:0]: Selects the signals that are connected to the ADC.
00000: Output of the weight-scale front-end (default)
00011: Output of the body composition measurement front-end (OUTP_FILT/OUTM_FILT)
00101: Output of the body composition measurement front-end (OUTP_Q_FILT/OUTM_Q_FILT)
01001: AUX1 signal for single-ended measurement. Also set bit[13:11] of the ADC_CONTROL_REGISTER1 to '001'.
10001: AUX2 signal for single-ended measurement. Also set bit[13:11] of the ADC_CONTROL_REGISTER1 to '010'.
11001: AUX2 and AUX1 signal for differential measurement (AUX2-AUX1). Also set bit[13:11] of the
ADC_CONTROL_REGISTER1 to 000.
NOTE: All other bit combinations are invalid.
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MISC_REGISTER3 (Address 0x1A, Default 0x0000)
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
1
4
1
3
0
2
0
1
0
0
0
Bits[15:6]
Bits[5:4]
Bits[3:0]
Not used. Always write '0'.
Always write '1'.
Not used. Always write '0'.
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SBAS586B –JUNE 2012–REVISED JUNE 2013
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from the page numbers in the current version.
Changes from Revision A (June 2012) to Revision B
Page
•
•
•
•
•
•
•
•
•
Changed title condition for Electrical Charancteristics ......................................................................................................... 3
Changed test condition for rectifier bandwidth parameter .................................................................................................... 4
Changed y-axis unit in Figure 5 ............................................................................................................................................ 9
Changed R1 percentage in Figure 6 .................................................................................................................................. 10
Changed feedback resistor percentage in second paragraph after Figure 7 ..................................................................... 11
Changed description for last row of Table 2 ....................................................................................................................... 20
Changed bit descriptions of ISW_MUX register ................................................................................................................. 23
Changed bit 9 for BCM_DAC_FREQ (Address 0x0E) ........................................................................................................ 24
Changed bit numbers for MISC_REGISTER3 (Address 0x1A) .......................................................................................... 26
Changes from Original (June 2012) to Revision A
Page
•
Changed data sheet from product preview to production data ............................................................................................. 1
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PACKAGE OPTION ADDENDUM
www.ti.com
1-May-2013
PACKAGING INFORMATION
Orderable Device
AFE4300PN
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
LQFP
LQFP
PN
80
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-3-260C-168 HR
AFE4300
AFE4300
AFE4300PNR
ACTIVE
PN
1000
Green (RoHS
& no Sb/Br)
Level-3-260C-168 HR
0 to 70
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
60
M
0,08
41
61
40
0,13 NOM
80
21
1
20
Gage Plane
9,50 TYP
0,25
12,20
SQ
11,80
0,05 MIN
0°–7°
14,20
SQ
13,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
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