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AFE4403

SBAS650B –MAY 2014–REVISED JULY 2014

AFE4403 Ultra-Small, Integrated Analog Front-End for Heart Rate Monitors and

Low-Cost Pulse Oximeters

1 Features

2 Applications

1

•

Fully-Integrated AFE for Pulse Oximeter and

Heart Rate Monitoring Applications:

•

Medical Pulse Oximeter Applications

Optical HRM

•

Transmit:

Industrial Photometry Applications

–

Integrated Dual LED Driver

3 Description

(H-Bridge or Common Anode)

The AFE4403 is a fully-integrated analog front-end

(AFE) ideally suited for pulse oximeter applications.

The device consists of a low-noise receiver channel

with an integrated analog-to-digital converter (ADC),

an LED transmit section, and diagnostics for sensor

and LED fault detection. The device is a very

configurable timing controller. This flexibility enables

the user to have complete control of the device timing

characteristics. To ease clocking requirements and

provide a low-jitter clock to the AFE4403, an oscillator

is also integrated that functions from an external

crystal. The device communicates to an external

microcontroller or host processor using an SPI™

interface.

–

Option for a Third LED Support for Optimized

SPO2, HRM, or Multi-Wavelength HRM

–

Up to 110-dB Dynamic Range

LED Current:

–

Programmable to 100 mA with 8-Bit

Current Resolution

–

30 µA + Average LED Current

Programmable LED On-Time

Independent LED2 and LED1 Current

Reference

•

Receive Channel with High Dynamic Range:

–

22-Bit Output in Twos Complement Format

Up to 105-dB Dynamic Range

Low Power: < 650 µA

The device is a complete AFE solution packaged in a

single, compact DSBGA-36 (3.07 mm × 3.07 mm ×

0.5 mm) and is specified over the operating

temperature range of –20°C to 70°C.

Dynamic Power-Down Mode to Reduce

Current to 300 µA

Device Information⁽¹⁾

–

Adaptable to a Very Wide Range of Signal

Amplitudes:

PART NUMBER

PACKAGE

BODY SIZE (NOM)

AFE4403

DSBGA (36)

3.07 mm × 3.07 mm

–

Total Programmable Gain: 10 kΩ to 4 MΩ

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

Integrated Digital Ambient Estimation and

Subtraction

•

Flexible Clocking by External Clock or Crystal:

–

Pulse Frequency: 62.5 SPS to 2000 SPS

Flexible Pulse sequencing and Timing Control

Input Clock Range: 4 MHz (Min) to 60 MHz

(Max)

•

Integrated Fault Diagnostics:

–

Photodiode and LED Open and

Short Detection

Supplies:

–

Rx = 2.0 V to 3.6 V

Tx = 3.0 V to 5.25 V

•

Package: Compact DSBGA-36

(3.07 mm × 3.07 mm × 0.5 mm)

Specified Temperature Range: –20°C to 70°C

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

AFE4403

SBAS650B –MAY 2014–REVISED JULY 2014

www.ti.com

Table of Contents

8.2 Functional Block Diagram ....................................... 20

8.3 Feature Description................................................. 21

8.4 Device Functional Modes........................................ 45

8.5 Programming........................................................... 53

8.6 Register Maps......................................................... 58

Application and Implementation ........................ 83

9.1 Application Information............................................ 83

9.2 Typical Application .................................................. 83

1

2

3

4

5

6

7

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Device Family Options .......................................... 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 Handling Ratings....................................................... 5

7.3 Recommended Operating Conditions....................... 6

7.4 Thermal Information.................................................. 6

7.5 Electrical Characteristics........................................... 7

7.6 Timing Requirements.............................................. 11

9

10 Power Supply Recommendations ..................... 87

10.1 Power Consumption Considerations..................... 88

11 Layout................................................................... 90

11.1 Layout Guidelines ................................................. 90

11.2 Layout Example .................................................... 90

12 Device and Documentation Support ................. 91

12.1 Trademarks........................................................... 91

12.2 Electrostatic Discharge Caution............................ 91

12.3 Glossary................................................................ 91

7.7 Timing Requirements: Supply Ramp and Power-

Down........................................................................ 12

7.8 Typical Characteristics............................................ 14

Detailed Description ............................................ 20

8.1 Overview ................................................................. 20

8

13 Mechanical, Packaging, and Orderable

Information ........................................................... 91

4 Revision History

Changes from Revision A (June 2014) to Revision B

Page

•

Changed Pin Configuration diagram: changed Top View to Bottom View ............................................................................ 3

Added footnote to Figure 41 ................................................................................................................................................ 27

Changes from Original (May 2014) to Revision A

Page

•

Changed document status to Production Data ...................................................................................................................... 1

Changed first and third sub-bullets of Flexible Clocking Features bullet .............................................................................. 1

Changed MIN to NOM in Body Size column of Device Information table ............................................................................. 1

Added Device Family Options table and Pin Configuration and Functions section ............................................................... 3

Added Specifications section ................................................................................................................................................. 5

Added Detailed Description section ..................................................................................................................................... 20

Added Application and Implementation section.................................................................................................................... 83

Added Power Supply Recommendations section ............................................................................................................... 87

Added Layout section .......................................................................................................................................................... 90

2

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SBAS650B –MAY 2014–REVISED JULY 2014

5 Device Family Options

LED DRIVE

CURRENT

(mA, max)

OPERATING

TEMPERATURE

RANGE

LED DRIVE

CONFIGURATION

Tx POWER SUPPLY

(V)

PRODUCT

PACKAGE-LEAD

AFE4400

VQFN-40

Bridge, push-pull

50

3 to 5.25

0°C to 70°C

–40°C to 85°C

–20°C to 70°C

50, 75, 100,

150, and 200

AFE4490

AFE4403

VQFN-40

DSBGA-36

25, 50, 75, and 100

6 Pin Configuration and Functions

YZP Package

DSBGA-36

(Bottom View)

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Pin Functions

NAME

NO.

FUNCTION

DESCRIPTION

Output signal that indicates ADC conversion completion.

Can be connected to the interrupt input pin of an external microcontroller.

ADC_RDY

D5

Digital

AFE-only power-down input; active low.

Can be connected to the port pin of an external microcontroller.

AFE_PDN

BG

C3

C2

Digital

Decoupling capacitor for internal band-gap voltage to ground.

Connect a decoupling capacitor to ground.

To achieve the lowest transmitter noise, use a capacitor value of 2.2 µF.

Reference

To reduce the recovery time from power-down (from 1 s to 0.1 s), use a capacitor value of

0.1 µF instead—but with slightly degraded transmitter noise.

Buffered 4-MHz output clock output.

Can be connected to the clock input pin of an external microcontroller.

CLKOUT

DIAG_END

DNC⁽¹⁾

E6

B4

Digital

—

Output signal that indicates completion of diagnostics.

Can be connected to the port pin of an external microcontroller.

C1, A1, E3, D3,

F5, B5, B6

Do not connect these pins. Leave as open circuit.

INN

INP

F1

E1

A3

Analog

Supply

Receiver input pin. Connect to photodiode anode.

Receiver input pin. Connect to photodiode cathode.

LED driver ground pin, H-bridge. Connect to common board ground.

LED_DRV_GND

LED driver supply pin, H-bridge. Connect to an external power supply capable of supplying the

large LED current, which is drawn by this supply pin.

LED_DRV_SUP

RESET

A6

D4

Supply

Digital

AFE-only reset input, active low.

Can be connected to the port pin of an external microcontroller

RX_ANA_GND

RX_ANA_SUP

RX_DIG_GND

RX_DIG_SUP

SCLK

E2

F2, E4

B2, F6

E5

Supply

SPI

Rx analog ground pin. Connect to common board ground.

Rx analog supply pin; 0.1-µF decoupling capacitor to ground

Rx digital ground pin. Connect to common board ground.

Rx digital supply pin; 0.1-µF decoupling capacitor to ground

SPI clock pin

C6

SPISIMO

C4

SPI

SPI serial in master out

SPISOMI

C5

SPI

SPI serial out master in

SPISTE

D6

SPI

SPI serial interface enable

TX_CTRL_SUP

A2

Supply

Transmit control supply pin (0.1-µF decoupling capacitor to ground)

Transmitter reference voltage, 0.25 V default after reset.

Connect a decoupling capacitor to ground.

TX_REF

B1

Reference

To achieve the lowest transmitter noise, use a capacitor value of 2.2 µF.

To reduce the recovery time from power-down (from 1 s to 0.1 s), use a capacitor value of

0.1 µF instead—but with slightly degraded transmitter noise.

TXN

TXP

A4

A5

Analog

LED driver out. Connect to LED in common anode or H-bridge configuration.

LED driver out for third LED. Connect to optional third LED supported in common anode

configuration.

TX3

B3

Analog

Input common-mode voltage output.

This signal can be used to shield (guard) the INP, INN traces.

If used as a shield, then connect a series resistor (1 kΩ) and a decoupling capacitor (10 nF) to

ground.

VCM

D1

Reference

If VCM is not used externally, then these external components are not required.

VSS

D2

F4

Supply

Digital

Substrate ground. Connect to common board ground.

Crystal oscillator pins.

Connect an external crystal between these pins with the correct load capacitor

(as specified by vendor) to ground.

XOUT

Crystal oscillator pins.

XIN

F3

Digital

Connect an external crystal between these pins with the correct load capacitor

(as specified by vendor) to ground.

(1) Leave pins as open circuit. Do not connect.

4

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SBAS650B –MAY 2014–REVISED JULY 2014

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

UNIT

V

RX_ANA_SUP, RX_DIG_SUP to RX_ANA_GND, RX_DIG_GND

TX_CTRL_SUP, LED_DRV_SUP to LED_DRV_GND

RX_ANA_GND, RX_DIG_GND to LED_DRV_GND

4

6

V

0.3

V

Analog inputs

RX_ANA_GND – 0.3

RX_DIG_GND – 0.3

RX_ANA_SUP + 0.3

V

Digital inputs

RX_DIG_SUP + 0.3

V

Input current to any pin except supply pins⁽²⁾

±7

±50

±7

mA

°C

Momentary

Input current

Continuous

Operating temperature range

0–20

70

Maximum junction temperature, T_J

125

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing beyond the supply rails must be current-limited

to 10 mA or less.

7.2 Handling Ratings

MIN

MAX

UNIT

T_stg

Storage temperature range

–60

150

°C

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all

pins⁽¹⁾

–1000

–250

1000

250

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC specification

JESD22-C101, all pins⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

PARAMETER

SUPPLIES

MIN

MAX

UNIT

RX_ANA_SUP

RX_DIG_SUP

TX_CTRL_SUP

AFE analog supply

2.0

3.0

3.6

V

AFE digital supply

Transmit controller supply

5.25

(1)(2)

[3.0 or (0.75 + V_LED+ V_CABLE

)

,

H-bridge

5.25

0.3

V

whichever is greater]

LED_DRV_SUP

Transmit LED driver supply

(1)(2)

Common anode

configuration

[3.0 or (0.5 + V_LED+ V_CABLE

)

,

whichever is greater]

Difference between LED_DRV_SUP and

TX_CTRL_SUP

–0.3

TEMPERATURE

Specified temperature range

Storage temperature range

–20

–60

70

°C

150

(1) V_LEDrefers to the maximum voltage drop across the external LED (at maximum LED current) connected between the TXP and TXN pins

(in H-bridge mode) and from the TXP and TXN pins to LED_DRV_SUP (in the common anode configuration).

(2) V_CABLErefers to voltage drop across any cable, connector, or any other component in series with the LED.

7.4 Thermal Information

AFE4403

THERMAL METRIC⁽¹⁾

YZP (WCSP)

UNIT

36 BALLS

49.8

0.2

R_θJA

Junction-to-ambient thermal resistance

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

8.5

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.8

ψ_JB

8.5

R_θJC(bot)

n/a

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6

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SBAS650B –MAY 2014–REVISED JULY 2014

7.5 Electrical Characteristics

Minimum and maximum specifications are at T_A= –20°C to 70°C, typical specifications are at 25°C. Crystal mode enabled,

detector capacitor = 50 pF differential, ADC averaging set to maximum allowed for each PRF, TX_REF voltage set to 0.5 V,

and CLKOUT tri-stated, at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, stage 2

amplifier disabled, and f_CLK= 8 MHz, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PERFORMANCE (Full-Signal Chain)

R_F= 10 kΩ

R_F= 25 kΩ

R_F= 50 kΩ

R_F= 100 kΩ

R_F= 250 kΩ

R_F= 500 kΩ

R_F= 1 MΩ

50

20

10

5

µA

I_{IN_FS}

Full-scale input current

µA

2

µA

1

µA

0.5

µA

PRF

Pulse repetition frequency

PRF duty cycle

62.5

2000

25%

SPS

DC_PRF

f_CM= 50 Hz and 60 Hz, LED1 and LED2 with

R_SERIES= 500 kΩ, R_F= 500 kΩ

75

95

dB

CMRR

Common-mode rejection ratio

f_CM= 50 Hz and 60 Hz, LED1-AMB and LED2-AMB with

R_SERIES= 500 kΩ, R_F= 500 kΩ

PSRR_LEDPSRR, transmit LED driver

PSRR_TxPSRR, transmit control

PSRR_RxPSRR, receiver

Total integrated noise current, input-

With respect to ripple on LED_DRV_SUP

75

60

25

dB

With respect to ripple on TX_CTRL_SUP

With respect to ripple on RX_ANA_SUP and RX_DIG_SUP

R_F= 100 kΩ, PRF = 600 Hz, duty cycle = 5%

dB

pA_RMS

referred (receiver with transmitter loop

back, 0.1-Hz to 20-Hz bandwidth)

R_F= 500 kΩ, PRF = 600 Hz, duty cycle = 5%

6

pA_RMS

RECEIVER FUNCTIONAL BLOCK LEVEL SPECIFICATION

R_F= 500 kΩ, ambient cancellation enabled,

stage 2 gain = 4, PRF = 1200 Hz, LED duty cycle = 25%

3.2

5.3

pA_RMS

Total integrated noise current, input

referred (receiver alone) over 0.1-Hz to

20-Hz bandwidth

R_F= 500 kΩ, ambient cancellation enabled,

stage 2 gain = 4, PRF = 1200 Hz, LED duty cycle = 5%

I-V TRANSIMPEDANCE AMPLIFIER

See the Receiver Channel

G

Gain

R_F= 10 kΩ to 1 MΩ

V/µA

section for details

Gain accuracy

Feedback resistance

±7%

10k, 25k, 50k, 100k, 250k,

500k, and 1M

R_F

Ω

Feedback resistor tolerance

Feedback capacitance

R_F

C_F

±20%

5, 10, 25, 50, 100, and 250

pF

Feedback capacitor tolerance

Full-scale differential output voltage

Common-mode voltage on input pins

±20%

1

V

Set internally

0.9

Includes equivalent capacitance of photodiode, cables,

EMI filter, and so forth

External differential input capacitance

Shield output voltage, V_CM

10

1000

pF

V

With a 1-kΩ series resistor and a 10-nF decoupling

capacitor to ground

0.8

0.9

1

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Electrical Characteristics (continued)

Minimum and maximum specifications are at T_A= –20°C to 70°C, typical specifications are at 25°C. Crystal mode enabled,

detector capacitor = 50 pF differential, ADC averaging set to maximum allowed for each PRF, TX_REF voltage set to 0.5 V,

and CLKOUT tri-stated, at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, stage 2

amplifier disabled, and f_CLK= 8 MHz, unless otherwise noted.

PARAMETER

AMBIENT CANCELLATION STAGE

Gain

TEST CONDITIONS

MIN

TYP

MAX

UNIT

0, 3.5, 6, 9.5, and 12

dB

µA

Current DAC range

0

10

Current DAC step size

LOW-PASS FILTER

1

Low-pass corner frequency

3-dB attenuation

Duty cycle = 25%

Duty cycle = 10%

500

0.004

0.041

28

Hz

dB

ms

Pass-band attenuation, 2 Hz to 10 Hz

Filter settling time

ANALOG-TO-DIGITAL CONVERTER

Resolution

After diagnostics mode

22

Bits

SPS

V

Sample rate

See the ADC Operation and Averaging Module section

4 × PRF

±1.2

ADC full-scale voltage

ADC conversion time

ADC reset time⁽¹⁾

PRF / 4

µs

2

t_CLK

TRANSMITTER

Selectable, 0 to 100

(see the LEDCNTRL: LED

Control Register for details)

Output current range

mA

LED current DAC error

Output current resolution

±10%

8

Bits

dB

Transmitter noise dynamic range,

over 0.1-Hz to 20-Hz bandwidth,

TX_REF set to 0.5 V

At 25-mA output current

At 50-mA output current

110

50

dB

µs

Minimum sample time of LED1 and

LED2 pulses

LED_ON = 0

1

50

0.50

7

µA

%

LED current DAC leakage current

LED current DAC linearity

LED_ON = 1

Percent of full-scale current

From zero current to 50 mA

From 50 mA to zero current

µs

Output current settling time

(with resistive load)

7

DIAGNOSTICS

Start of diagnostics after the DIAG_EN register bit is set.

End of diagnostic is indicated by DIAG_END going high.

Duration of diagnostics state machine

16

ms

Open fault resistance

Short fault resistance

> 100

< 10

kΩ

INTERNAL OSCILLATOR

f_CLKOUT

CLKOUT frequency

With an 8-MHz crystal connected to the XIN, XOUT pins

4

50%

200

MHz

CLKOUT duty cycle

Crystal oscillator start-up time

µs

(1) A low ADC reset time can result in a small component of the LED signal leaking into the ambient phase. With an ADC reset of two clock

cycles, a –60-dB leakage is expected. In many cases, this leakage does not affect system performance. However, if this crosstalk must

be completely eliminated, a longer ADC reset time of approximately six clock cycles is recommended for t₂₂, t₂₄, t₂₆, and t₂₈in

Figure 48.

8

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Electrical Characteristics (continued)

Minimum and maximum specifications are at T_A= –20°C to 70°C, typical specifications are at 25°C. Crystal mode enabled,

detector capacitor = 50 pF differential, ADC averaging set to maximum allowed for each PRF, TX_REF voltage set to 0.5 V,

and CLKOUT tri-stated, at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, stage 2

amplifier disabled, and f_CLK= 8 MHz, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

EXTERNAL CLOCK

For SPO2 applications

50

ps

Maximum allowable external clock jitter

For optical heart rate only

±2%

1000

60

(2)

External clock input frequency

4

8

MHz

0.75 ×

RX_DIG_SUP

Voltage input high (V_IH

)

V

External clock input voltage

0.25 ×

RX_DIG_SUP

Voltage input low (V_IL)

TIMING

Wake-up time from complete

power-down

1000

ms

Wake-up time from Rx power-down

Wake-up time from Tx power-down

Active low RESET pulse duration

100

1000

1

µs

ms

t_RESET

DIAG_END pulse duration at the

completion of diagnostics

CLKOUT

cycles

t_DIAGEND

4

1

CLKOUT

cycle

t_ADCRDY

ADC_RDY pulse duration

DIGITAL SIGNAL CHARACTERISTICS

0.8

DVDD

DVDD +

0.1

V_IH

Logic high input voltage

AFE_PDN, SCLK, SPISIMO, SPISTE, RESET

> 1.3

V

0.2

DVDD

V_IL

I_IN

Logic low input voltage

Logic input current

AFE_PDN, SCLK, SPISIMO, SPISTE, RESET

0 V < V_DigitalInput< DVDD

–0.1

–10

< 0.4

V

µA

V

10

0.9

DVDD

> (RX_DIG_SUP –

0.2 V)

V_OH

Logic high output voltage

DIAG_END, SPISOMI, ADC_RDY, CLKOUT

0.1

< 0.4

V_OL

Logic low output voltage

DIAG_END, SPISOMI, ADC_RDY, CLKOUT

V

DVDD

SUPPLY CURRENT

RX_ANA_SUP = 3.0 V, with 8-MHz clock running,

Rx stage 2 disabled

0.6

0.7

mA

RX_ANA_SUP = 3.0 V, with 8-MHz clock running,

Rx stage 2 enabled

Receiver analog supply current

RX_ANA_SUP = 3.0 V, with 8-MHz clock running,

Rx stage 2 disabled, external clock mode

0.49

Receiver digital supply current

LED driver supply current

RX_DIG_SUP = 3.0 V

0.15

30

15

3

mA

µA

With zero LED current setting

Transmitter control supply current

Receiver current only (RX_ANA_SUP)

Receiver current only (RX_DIG_SUP)

Transmitter current only (LED_DRV_SUP)

Transmitter current only (TX_CTRL_SUP)

Receiver current only (RX_ANA_SUP)

Receiver current only (RX_DIG_SUP)

Transmitter current only (LED_DRV_SUP)

Transmitter current only (TX_CTRL_SUP)

3

Complete power-down

(using the AFE_PDN pin)

1

200

150

2

Power-down Rx alone

Power-down Tx alone

2

(2) Refer to the CLKDIV[2:0] register bits for a detailed list of input clock frequencies that are supported.

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Electrical Characteristics (continued)

Minimum and maximum specifications are at T_A= –20°C to 70°C, typical specifications are at 25°C. Crystal mode enabled,

detector capacitor = 50 pF differential, ADC averaging set to maximum allowed for each PRF, TX_REF voltage set to 0.5 V,

and CLKOUT tri-stated, at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, stage 2

amplifier disabled, and f_CLK= 8 MHz, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER DISSIPATION

LED_DRV_SUP Does not include LED current.

1

µA

TX_CTRL_SUP

Power-down with

the AFE_PDN pin

RX_ANA_SUP

5

RX_DIG_SUP

0.1

1

LED_DRV_SUP Does not include LED current.

TX_CTRL_SUP

Power-down with

the PDNAFE

register bit

1

RX_ANA_SUP

15

20

30

15

200

150

2

RX_DIG_SUP

LED_DRV_SUP Does not include LED current.

TX_CTRL_SUP

Power-down Rx

Power-down Tx

RX_ANA_SUP

RX_DIG_SUP

LED_DRV_SUP Does not include LED current.

TX_CTRL_SUP

2

RX_ANA_SUP

600

150

30

15

600

150

30

15

700

150

RX_DIG_SUP

LED_DRV_SUP Does not include LED current.

TX_CTRL_SUP

After reset, with 8-

MHz clock running

RX_ANA_SUP

RX_DIG_SUP

LED_DRV_SUP Does not include LED current.

TX_CTRL_SUP

With stage 2 mode

enabled and 8-MHz

clock running

RX_ANA_SUP

RX_DIG_SUP

Does not include LED

LED_DRV_SUP

current.

7

µA

Dynamic power-

down mode enabled

PRF = 100 Hz,

PDN_CYCLE duration = 8 ms

TX_CTRL_SUP

RX_ANA_SUP

RX_DIG_SUP

5

205

150

µA

10

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7.6 Timing Requirements

PARAMETER

MIN

TYP

MAX

UNIT

MHz

ns

t_CLK

Clock frequency on the XIN pin

8

t_SCLK

Serial shift clock period

62.5

10

t_STECLK

t_CLKSTEH,L

t_SIMOSU

t_SIMOHD

t_SOMIPD

t_SOMIHD

STE low to SCLK rising edge, setup time

SCLK transition to SPI STE high or low

SIMO data to SCLK rising edge, setup time

Valid SIMO data after SCLK rising edge, hold time

SCLK falling edge to valid SOMI, setup time

SCLK rising edge to invalid data, hold time

ns

10

ns

10

ns

10

ns

17

ns

0.5

t_SCLK

t_CLK

XIN

t_STECLK

SPISTE

t_SPICLK

t_CLKSTEH

31

23

7

0

SCLK

t_CLKSTEL

t_SIMOHD

t_SIMOSU

A7

A6

A1

A0

SPISIMO

SPISOMI

t_SOMIHD

t_SOMIPD

D22

D17 D16

D23

D7

D6

D1

D0

ꢀ}v[ꢁꢀꢁꢂ, can be high or low.

(1) The SPI_READ register bit must be enabled before attempting a register read.

(2) Specify the register address whose contents must be read back on A[7:0].

(3) The AFE outputs the contents of the specified register on the SPISOMI pin.

Figure 1. Serial Interface Timing Diagram, Read Operation^(1)(2)(3)

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t_STECLK

SPISTE

31

23

0

SCLK

t_SIMOHD

t_SIMOSU

A7

A6

A1

A0

D23

D22

D1

D0

SPISIMO

Figure 2. Serial Interface Timing Diagram, Write Operation

7.7 Timing Requirements: Supply Ramp and Power-Down

PARAMETER

VALUE

t₁

t₂

t₃

t₄

Time between Rx and Tx supplies ramping up

Time between both supplies stabilizing and high-going RESET edge

RESET pulse duration

Keep as small as possible (for example, ±10 ms)

> 100 ms

> 0.5 ms

> 1 µs

Time between RESET and SPI commands

Time between SPI commands and the ADC_RESET which corresponds > 3 ms of cumulative sampling time in each

to valid data

t₅

phase^(1)(2)(3)

> 1 s⁽³⁾

Time between RESET pulse and high-accuracy data coming out of the

signal chain

t₆

t₇

t₈

Time from AFE_PDN high-going edge and RESET pulse⁽⁴⁾

> 100 ms

> 1 s⁽³⁾

Time from AFE_PDN high-going edge (or PDN_AFE bit reset) to high-

accuracy data coming out of the signal chain

(1) This time is required for each of the four switched RC filters to fully settle to the new settings. The same time is applicable whenever

there is a change to any of the signal chain controls (for example, LED current setting, TIA gain, and so forth).

(2) If the SPI commands involve a change in the TX_REF value from its default, then there is additional wait time of approximately 1 s (for a

2.2-µF decoupling capacitor on the TX_REF pin).

(3) Dependent on the value of the capacitors on the BG and TX_REF pins. The 1-s wait time is necessary when the capacitors are 2.2 µF

and scale down proportionate to the capacitor value. A very low capacitor (for example, 0.1 µF) on these pins causes the transmitter

dynamic range to reduce to approximately 100 dB.

(4) After an active power-down from AFE_PDN, the device should be reset using a low-going RESET pulse.

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RX Supplies

(RX_ANA_SUP, RX_DIG_SUP)

t₁

TX Supplies

(TX_CTRL_SUP, LED_DRV_SUP)

t₂

t₆

RESET

t₃

t₄

t₅

SPI Interface

t₇

t₃

ADC_RDY

AFE_PDN

t₆

t₈

Figure 3. Supply Ramp and Hardware Power-Down Timing

RX Supplies

(RX_ANA_SUP, RX_DIG_SUP)

t₁

TX Supplies

(TX_CTRL_SUP, LED_DRV_SUP)

t₂

PDN_AFE

Bit Set

PDN_AFE Bit

Reset

RESET

t₈

t₃

t₄

t₅

SPI Interface

ADC_RDY

AFE_PDN

t₆

Figure 4. Supply Ramp and Software Power-Down Timing

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7.8 Typical Characteristics

At PRF = 100 Hz, 25% duty cycle, R_F= 500 kΩ, C_Fis adjusted to keep TIA time constant at 1/10th of sampling duration, All

supplies at 3.3 V, 8-MHz external clock, CLKOUT tri-state, 1-µF capacitor on TX_REF and BG pins, detector C_IN= 50 pF,

TX_REF = 0.5 V, ADC averaging = max allowed, and SNR in dBFS is noise referred to full-scale range of 2 V, unless

otherwise noted.

600

500

400

300

200

100

50

40

30

20

10

0

I(LED_DRV_SUP)

I(TX_CTRL_SUP)

I(RX_DIG_SUP)

I(RX_ANA_SUP)

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

2.6

3

3.4

3.8

4.2

4.6

5

Receiver Supply Voltage (V)

Transmitter Supply Voltage (V)

C001

C002

LED current = 0 mA

Figure 5. Receiver Currents vs Receiver Supply Voltage

Figure 6. Transmitter Currents vs

Transmitter Supply Voltage

1200

1000

800

700

600

500

400

300

200

Clock Division Ratio = 1

Clock Division Ratio = 2

Clock Division Ratio = 4

Clock Division Ratio = 6

Clock Division Ratio = 8

Clock Division Ratio = 12

600

400

200

0

10

20

30

40

50

60

50

250

450

650

850

1050

1250

External Clock Frequency (MHz)

PRF (Hz)

C003

C004

PRF = 150 Hz

Active window = 500 µs

LED pulse = 100 µs

All four DYNAMIC bits set to 1

Figure 7. Receiver Currents (Analog and Digital) vs

Clock Divider Ratio

Figure 8. Receiver Current vs

PRF in Dynamic Power-Down Mode

700

600

500

400

300

200

5

±5

±15

±25

±35

±45

5% Duty cycle

25% Duty cycle

0

1

2

3

4

5

6

7

8

9

1

10

100

1000

PDN_CYCLE Width (ms)

Frequency (Hz) in Log Scale

C005

C030

PRF = 100 Hz

LED pulse = 100 µs

All four DYNAMIC bits set to 1

Figure 9. Receiver Current (Analog and Digital) vs

Dynamic Power-Down Duty Cycle

Figure 10. Filter Response vs Duty cycle

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Typical Characteristics (continued)

At PRF = 100 Hz, 25% duty cycle, R_F= 500 kΩ, C_Fis adjusted to keep TIA time constant at 1/10th of sampling duration, All

supplies at 3.3 V, 8-MHz external clock, CLKOUT tri-state, 1-µF capacitor on TX_REF and BG pins, detector C_IN= 50 pF,

TX_REF = 0.5 V, ADC averaging = max allowed, and SNR in dBFS is noise referred to full-scale range of 2 V, unless

otherwise noted.

106

104

102

100

98

50

45

40

35

30

25

20

15

10

Output voltage = 0 %FS

Output voltage = 10 %FS

Output voltage = 25 %FS

Output voltage = 50 %FS

Output voltage = 75 %FS

Output voltage = 0 %FS

Output voltage = 10 %FS

Output voltage = 25 %FS

Output voltage = 50 %FS

Output voltage = 75 %FS

96

0

5

10

15

20

25

0

5

10

15

20

25

Duty Cycle (%)

C007

C006

500-Hz PRF

Figure 11. SNR over Nyquist Bandwidth vs Duty Cycle

(Input Current with Tx-Rx Loopback)

Figure 12. Input-Referred Noise Current over Nyquist

Bandwidth vs Duty Cycle

(Input Current with Tx-Rx Loopback)

100000

108

RF = 10 kꢀ

RF = 25 kꢀ

RF = 50 kꢀ

RF = 25 kꢀ

10000

1000

100

10

RF = 100 kꢀ

RF = 250 kꢀ

RF = 500 kꢀ

RF = 1000 kꢀ

106

RF = 50 kꢀ

RF = 100 kꢀ

RF = 250 kꢀ

RF = 500 kꢀ

RF = 1000 kꢀ

104

102

100

98

1

0

5

10

15

20

25

0

5

10

15

20

25

Duty Cycle (%)

C011

C008

Figure 14. Receiver Input-Referred Noise Current over

Nyquist Bandwidth vs Duty Cycle (Different Gain Settings)

Figure 13. Receiver SNR over Nyquist Bandwidth vs

Duty Cycle (Different Gain Settings)

112

100000

RF = 10 kꢀ

RF = 25 kꢀ

RF = 50 kꢀ

RF = 100 kꢀ

RF = 250 kꢀ

RF = 500 kꢀ

RF = 1000 kꢀ

RF = 10 kꢀ

RF = 25 kꢀ

RF = 50 kꢀ

110

108

106

104

102

10000

RF = 100 kꢀ

RF = 250 kꢀ

RF = 500 kꢀ

RF = 1000 kꢀ

1000

100

10

1

0

5

10

15

20

25

0

5

10

15

20

25

Duty Cycle (%)

C009

C010

Figure 15. Receiver SNR in 20-Hz BW vs Duty Cycle

(Different Gain Settings)

Figure 16. Receiver Input-Referred Noise Current in

20-Hz BW vs Duty Cycle (Different Gain Settings)

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Typical Characteristics (continued)

At PRF = 100 Hz, 25% duty cycle, R_F= 500 kΩ, C_Fis adjusted to keep TIA time constant at 1/10th of sampling duration, All

supplies at 3.3 V, 8-MHz external clock, CLKOUT tri-state, 1-µF capacitor on TX_REF and BG pins, detector C_IN= 50 pF,

TX_REF = 0.5 V, ADC averaging = max allowed, and SNR in dBFS is noise referred to full-scale range of 2 V, unless

otherwise noted.

102

40

30

20

10

0

98

94

ADC Averaging = 1

ADC Averaging = 2

ADC Averaging = 4

ADC Averaging = 8

ADC Averaging = 16

ADC Averaging = 1

ADC Averaging = 2

ADC Averaging = 4

ADC Averaging = 8

ADC Averaging = 16

90

86

0

5

10

15

20

25

0

5

10

15

20

25

Duty Cycle (%)

C013

C012

Figure 17. Receiver SNR over Nyquist Bandwidth vs

Duty Cycle (Different ADC Averaging)

Figure 18. Receiver Input-Referred Noise Current over

Nyquist Bandwidth vs Duty Cycle (Different ADC Averaging)

116

112

108

104

30

PRF = 62.5 Hz

PRF = 100 Hz

PRF = 500 Hz

PRF = 1000 Hz

25

20

PRF = 2000 Hz

15

10

5

PRF = 62.5 Hz

PRF = 100 Hz

PRF = 500 Hz

100

96

PRF = 1000 Hz

PRF = 2000 Hz

92

0

5

10

15

20

25

0

5

10

15

20

25

Duty Cycle (%)

C015

C014

Figure 19. Receiver SNR in 20-Hz BW vs Duty Cycle

(Different PRFs)

Figure 20. Receiver Input Referred Noise in 20-Hz BW vs

Duty Cycle (Different PRFs)

112

108

104

100

96

25

20

15

10

5

0

250

500

750

1000

1250

0

250

500

750

1000

1250

PRF (Hz)

C017

C016

Active window = 500 µs

LED pulse = 100 µs

All four DYNAMIC bits set to 1

Active window = 500 µs

LED pulse = 100 µs

All four DYNAMIC bits set to 1

Figure 21. Receiver SNR in 20-Hz BW in Dynamic

Power-Down Mode vs PRF

Figure 22. Receiver Input-Referred Noise in 20-Hz BW in

Dynamic Power-Down Mode vs PRF

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Typical Characteristics (continued)

At PRF = 100 Hz, 25% duty cycle, R_F= 500 kΩ, C_Fis adjusted to keep TIA time constant at 1/10th of sampling duration, All

supplies at 3.3 V, 8-MHz external clock, CLKOUT tri-state, 1-µF capacitor on TX_REF and BG pins, detector C_IN= 50 pF,

TX_REF = 0.5 V, ADC averaging = max allowed, and SNR in dBFS is noise referred to full-scale range of 2 V, unless

otherwise noted.

106

104

102

100

98

30

26

22

18

14

10

96

0

2

4

6

8

10

0

2

4

6

8

10

Dynamic Powerdown Cycle Width (ms)

Dynamic Powerdown Cycle width (ms)

C019

C018

PRF = 100 Hz

LED pulse = 100 µs

PRF = 100 Hz

LED pulse = 100 µs

All four DYNAMIC bits set to 1

Figure 23. Receiver SNR over Nyquist Bandwidth vs

Dynamic Power-Down Duty Cycle

Figure 24. Receiver Input-Referred Noise over Nyquist

Bandwidth vs Dynamic Power-Down Duty Cycle

106

104

102

100

30

26

22

RF = 250 kꢀ

18

14

10

RF = 500 kꢀ

RF = 250 kꢀ

98

RF = 500 kꢀ

96

0

10

20

30

40

50

60

70

0

10

20

30

40

50

60

70

±20 ±10

Temperature (deg C)

C021

C020

LED pulse = 100 µs Pleth current = 1 µA

Figure 25. SNR in 20-Hz Bandwidth vs Temperature

(Tx-Rx Loopback)

Figure 26. Input-Referred Noise Current in 20-Hz BW vs

Temperature (TX-Rx Loopback)

106

105

104

103

102

101

20

Stg2Gain = 1

Stg2Gain = 1.5

Stg2Gain = 2

Stg2Gain = 3

Stg2Gain = 4

16

12

8

100

Stg2Gain = 1

99

98

97

96

Stg2Gain = 1.5

Stg2Gain = 2

Stg2Gain = 3

Stg2Gain = 4

4

0

5

10

15

20

25

0

5

10

15

20

25

Duty Cycle (%)

C023

C022

Stage 2 enabled

Figure 27. Receiver SNR over Nyquist Bandwidth vs

Duty Cycle (Different Stage 2 Gain Settings)

Figure 28. Receiver Input-Referred Noise Current over

Nyquist Bandwidth vs Duty Cycle

(Different Stage 2 Gain Settings)

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Typical Characteristics (continued)

At PRF = 100 Hz, 25% duty cycle, R_F= 500 kΩ, C_Fis adjusted to keep TIA time constant at 1/10th of sampling duration, All

supplies at 3.3 V, 8-MHz external clock, CLKOUT tri-state, 1-µF capacitor on TX_REF and BG pins, detector C_IN= 50 pF,

TX_REF = 0.5 V, ADC averaging = max allowed, and SNR in dBFS is noise referred to full-scale range of 2 V, unless

otherwise noted.

60

56

52

48

44

40

36

32

28

24

20

100

80

60

40

20

0

±20

3

4

5

6

7

0

50

100

150

200

250

300

Internal Clock Frequency (MHz)

DAC Current Setting Code

C029

C025

R_F= 250 kΩ

PRF = 100 Hz

ADC averaging = 1

TX_REF = 0.25 V

Figure 30. Transmitter DAC Current Step Error

Figure 29. Receiver Input-Referred Noise Current vs

Internal Clock Frequency

116

112

108

25

TX_REF = 0.25 V

TX_REF = 0.5 V

TX_REF = 0.75 V

TX_REF = 1 V

20

15

10

5

TX_REF = 0.25 V

TX_REF = 0.5 V

TX_REF = 0.75 V

TX_REF = 1 V

104

100

96

0

5

10

15

20

25

0

5

10

15

20

25

Duty Cycle (%)

C027

C028

PRF = 500 Hz

DAC current is set such that ADC output is 50 %FS

Figure 31. SNR in 20-Hz BW vs Duty Cycle

(TX_REF Voltage with Tx-Rx Loopback)

Figure 32. Input Referred Noise Current in 20-Hz BW vs

Duty Cycle (TX_REF Voltage with Tx-Rx Loopback)

60

50

40

30

25

20

15

10

5

20

Actual current

Expected current - 2 %

10

Expected current + 2 %

0

50

100

150

200

250

300

44

45

46

47

48

49

50

51

52

DAC Current Setting Code

LED Current (mA)

C024

C031

TX_REF = 0.25 V

LED current = 48 mA

100 devices on tester

Figure 33. Transmitter Current linearity

Figure 34. Transmitter Current Across Devices

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Typical Characteristics (continued)

At PRF = 100 Hz, 25% duty cycle, R_F= 500 kΩ, C_Fis adjusted to keep TIA time constant at 1/10th of sampling duration, All

supplies at 3.3 V, 8-MHz external clock, CLKOUT tri-state, 1-µF capacitor on TX_REF and BG pins, detector C_IN= 50 pF,

TX_REF = 0.5 V, ADC averaging = max allowed, and SNR in dBFS is noise referred to full-scale range of 2 V, unless

otherwise noted.

100

DAC setting = 50 codes

80

60

40

20

0

DAC setting = 75 codes

DAC setting = 100 codes

0.25

0.5

0.75

1

TX_REF (V)

C026

Figure 35. Transmitter Current vs TX_REF Voltage

(Multiple DAC Settings)

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8 Detailed Description

8.1 Overview

The AFE4403 is a complete analog front-end (AFE) solution targeted for pulse oximeter applications. The device

consists of a low-noise receiver channel, an LED transmit section, and diagnostics for sensor and LED fault

detection. To ease clocking requirements and provide the low-jitter clock to the AFE, an oscillator is also

integrated that functions from an external crystal. The device communicates to an external microcontroller or host

processor using an SPI interface. The Functional Block Diagram section provides a detailed block diagram for

the AFE4403. The blocks are described in more detail in the following sections.

8.2 Functional Block Diagram

Device

Reference

C_F

+ 1.2V

-

R_F

Filter

+

Gain

+

Buffer

SPISTE

Digital

Filter

INP

INN

Stage 2

TIA

4G ADC

SPISIMO

C_PO

SPI

SPISOMI

SCLK

R_F

Control

C_F

Photodiode

VCM

Timing

Connector

LED_DRV_SUP

c

TX3

TXN

LED Driver

AFE_PDN

ADC_RDY

RESET

LED Current

Control DAC

TXP

%

DNC⁽¹⁾

Diagonostic

Signals

DIAG_END

OSC

Diagnostics

c

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8.3 Feature Description

8.3.1 Receiver Channel

This section describes the functionality of the receiver channel.

8.3.1.1 Receiver Front-End

The receiver consists of a differential current-to-voltage (I-V) transimpedance amplifier (TIA) that converts the

input photodiode current into an appropriate voltage, as shown in Figure 36. The feedback resistor of the

amplifier (R_F) is programmable to support a wide range of photodiode currents. Available R_Fvalues include:

1 MΩ, 500 kΩ, 250 kΩ, 100 kΩ, 50 kΩ, 25 kΩ, and 10 kΩ.

The device is ideally suited as a front-end for a PPG (photoplethysmography) application. In such an application,

the light from the LED is reflected (or transmitted) from (or through) the various components inside the body

(such as blood, tissue, and so forth) and are received by the photodiode. The signal received by the photodiode

has three distinct components:

1. A pulsatile or ac component that arises as a result of the changes in blood volume through the arteries.

2. A constant dc signal that is reflected or transmitted from the time invariant components in the path of light.

This constant dc component is referred to as the pleth signal.

3. Ambient light entering the photodiode.

The ac component is usually a small fraction of the pleth component, with the ratio referred to as the perfusion

index (PI). Thus, the allowed signal chain gain is usually determined by the amplitude of the dc component.

Rx

S_LED2

CONV_LED2

LED2

C_F

R_F

R_G

ADC

ADC Output Rate

PRF Sa/sec

Amb

LED1

+

Stage 2

Gain

S_{LED2_amb}

S_LED1

+

CONV_{LED2_amb}

CONV_LED1

TIA

C_PD

Buffer

ûꢀꢀADC

R_G

R_F

C_F

ADC Convert

ADC Clock

Amb

Ambient

DAC

CONV_{LED1_amb}

S_{LED1_amb}

I-V Amplifier

Filter

Buffer

ADC

Amb cancellation DAC

Ambient-cancellation current can be set digitally using SPI interface.

Figure 36. Receiver Front-End

The R_Famplifier and the feedback capacitor (C_F) form a low-pass filter for the input signal current. Always ensure

that the low-pass filter RC time constant has sufficiently high bandwidth (as shown by Equation 1) because the

input current consists of pulses. For this reason, the feedback capacitor is also programmable. Available C_F

values include: 5 pF, 10 pF, 25 pF, 50 pF, 100 pF, and 250 pF. Any combination of these capacitors can also be

used.

Rx Sample Time

R_F´ C_F£

10

(1)

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Feature Description (continued)

The output voltage of the I-V amplifier includes the pleth component (the desired signal) and a component

resulting from the ambient light leakage. The I-V amplifier is followed by the second stage, which consists of a

current digital-to-analog converter (DAC) that sources the cancellation current and an amplifier that gains up the

pleth component alone. The amplifier has five programmable gain settings: 0 dB, 3.5 dB, 6 dB, 9.5 dB, and

12 dB. The gained-up pleth signal is then low-pass filtered (500-Hz bandwidth) and buffered before driving a 22-

bit ADC. The current DAC has a cancellation current range of 10 µA with 10 steps (1 µA each). The DAC value

can be digitally specified with the SPI interface. Using ambient compensation with the ambient DAC allows the

dc-biased signal to be centered to near mid-point of the amplifier (±0.9 V). Using the gain of the second stage

allows for more of the available ADC dynamic range to be used.

The output of the ambient cancellation amplifier is separated into LED2 and LED1 channels. When LED2 is on,

the amplifier output is filtered and sampled on capacitor C_LED2. Similarly, the LED1 signal is sampled on the

C_LED1capacitor when LED1 is on. In between the LED2 and LED1 pulses, the idle amplifier output is sampled to

estimate the ambient signal on capacitors C_{LED2_amb}and C_{LED1_amb}

.

The sampling duration is termed the Rx sample time and is programmable for each signal, independently. The

sampling can start after the I-V amplifier output is stable (to account for LED and cable settling times). The Rx

sample time is used for all dynamic range calculations; the minimum time recommended is 50 µs. While the

AFE4403 can support pulse widths lower than 50 us, having too low a pulse width could result in a degraded

signal and noise from the photodiode.

A single, 22-bit ADC converts the sampled LED2, LED1, and ambient signals sequentially. Each conversion

provides a single digital code at the ADC output. As discussed in the Receiver Timing section, the conversions

are meant to be staggered so that the LED2 conversion starts after the end of the LED2 sample phase, and so

on.

Note that four data streams are available at the ADC output (LED2, LED1, ambient LED2, and ambient LED1) at

the same rate as the pulse repetition frequency. The ADC is followed by a digital ambient subtraction block that

additionally outputs the (LED2 – ambient LED2) and (LED1 – ambient LED1) data values.

The model of the photodiode and the connection to the TIA is shown in Figure 37.

C_F

R_F

Sensor Model

V_TIA

-

+

-

ADC

C_IN

I_in

V_TIA

+

C_F

R_F

Figure 37. TIA Block Diagram

I_inis the signal current generated by the photodiode in response to the incident light. C_inis the zero-bias

capacitance of the photodiode. The current-to-voltage gain in the TIA is given by Equation 2:

V_TIA(diff) = V_TIA⁺– V_TIA^–= 2 × I_in× R_F

(2)

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Feature Description (continued)

For example, for a photodiode current of I_in= 1 µA and a TIA gain setting of R_F= 100 kΩ, the differential output

of the TIA is equal to 200 mV. The TIA has an operating range of ±1 V, and the ADC has an input full-scale

range of ±1.2 V (the extra margin is to prevent the ADC from saturating while operating the TIA at the fullest

output range). Furthermore, because the PPG signal is one-sided, only one half of the full-scale is used. TI

recommends operating the device at a dc level that is not more than 50% to 60% of the ADC full-scale. The

margin allows for sudden changes in the signal level that might saturate the signal chain if operating too close to

full-scale. Signal levels are shown in Figure 38:

+1.2 V

ADC max

(Differential)

+1 V

TIA max

(Differential)

+0.6 V

Ideal Operating

Point

0 V

-1 V

TIA min

(Differential)

-1.2 V

ADC min

(Differential)

Figure 38. Signal Levels in TIA and ADC

On startup, a gain calibration algorithm running on the microcontroller unit (MCU) can be used to monitor the dc

level and adjusts the LED current and TIA gain to get close to the target dc level. In addition to a target dc level,

a high and low threshold (for example 80% and 20% of full-scale) can be determined that can cause the

algorithm to switch to a different TIA gain or LED current setting when the signal amplitude changes beyond

these thresholds.

In heart rate monitoring (HRM) applications demanding small-form factors, the sensor size can be so small (and

the signal currents so low) that they do not occupy even 50% of full-scale even with the highest TIA gain setting

of 1 MΩ, which is the case for signal currents that are less than 300 nA. As such, experimentation with various

use cases is essential in order to determine the optimal target value, as well as high and low thresholds. Also, by

enabling the stage 2 and introducing additional gain (up to 12 dB), a few extra decibels of SNR can be achieved.

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Feature Description (continued)

8.3.1.2 Ambient Cancellation Scheme and Second Stage Gain Block

The receiver provides digital samples corresponding to ambient duration. The host processor (external to the

AFE) can use these ambient values to estimate the amount of ambient light leakage. The processor must then

set the value of the ambient cancellation DAC using the SPI, as shown in Figure 39.

Device

Host Processor

LED2 Data

ADC Output Rate

PRF Samples per Second

Ambient (LED2)

Data

Front End

(LED2 ± Ambient)

Data

Ambient Estimation Block

SPI

Interface

Ambient information is available in the host

processor.

ADC

Rx

SPI

Digital

Block

The processor can:

* Read ambient data

LED1 Data

Ambient (LED1)

Data

* Estimate ambient value to

be cancelled

* Set the value to be used by the ambient

cancellation DAC using the SPI of AFE

(LED1 ± Ambient)

Data

Digital Control for Ambient-Cancellation DAC

Figure 39. Ambient Cancellation Loop (Closed by the Host Processor)

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Feature Description (continued)

Using the set value, the ambient cancellation stage subtracts the ambient component and gains up only the pleth

component of the received signal; see Figure 40. The amplifier gain is programmable to 0 dB, 3.5 dB, 6 dB,

9.5 dB, and 12 dB.

I_CANCEL

Cf

Rg

Rf

I_PLETH+ I_AMB

Ri

Rx

V_DIFF

Ri

Rf

Rg

I_CANCEL

Cf

Value of I_CANCELset using

the SPI interface.

Figure 40. Front-End (I-V Amplifier and Cancellation Stage)

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Feature Description (continued)

The differential output of the second stage is V_DIFF, as given by Equation 3:

R_F

V_DIFF= 2 ´ I_PLETH

´

+ I_AMB

´

- I_CANCEL´ R_G

R_I

where:

•

R_I= 100 kΩ,

I_PLETH= photodiode current pleth component,

I_AMB= photodiode current ambient component, and

I_CANCEL= the cancellation current DAC value (as estimated by the host processor).

(3)

R_Gvalues with various gain settings are listed in Table 1.

Table 1. R_GValues

GAIN

0 (x1)

R_G(kΩ)

100

3.5 (x1.5)

6 (x2)

150

200

9.5 (x3)

12 (x4)

300

400

8.3.1.3 Receiver Control Signals

LED2 sample phase (S_LED2or S_R): When this signal is high, the amplifier output corresponds to the LED2 on-

time. The amplifier output is filtered and sampled into capacitor C_LED2. To avoid settling effects resulting from the

LED or cable, program S_LED2to start after the LED turns on. This settling delay is programmable.

Ambient sample phase (S_{LED2_amb}or S_{R_amb}): When this signal is high, the amplifier output corresponds to the

LED2 off-time and can be used to estimate the ambient signal (for the LED2 phase). The amplifier output is

filtered and sampled into capacitor C_{LED2_amb}

.

LED1 sample phase (S_LED1or S_IR): When this signal is high, the amplifier output corresponds to the LED1 on-

time. The amplifier output is filtered and sampled into capacitor C_LED1. To avoid settling effects resulting from the

LED or cable, program S_LED1to start after the LED turns on. This settling delay is programmable.

Ambient sample phase (S_{LED1_amb}or S_{IR_amb}): When this signal is high, the amplifier output corresponds to the

LED1 off-time and can be used to estimate the ambient signal (for the LED1 phase). The amplifier output is

filtered and sampled into capacitor C_{LED1_amb}

.

LED2 convert phase (CONV_LED2or CONV_R): When this signal is high, the voltage sampled on C_LED2is buffered

and applied to the ADC for conversion. At the end of the conversion, the ADC provides a single digital code

corresponding to the LED2 sample.

Ambient convert phases (CONV_{LED2_amb}or CONV_{R_amb}, CONV_{LED1_amb}or CONV_{IR_amb}): When this signal is

high, the voltage sampled on C_{LED2_amb}(or C_{LED1_amb}) is buffered and applied to the ADC for conversion. At the

end of the conversion, the ADC provides a single digital code corresponding to the ambient sample.

LED1 convert phase (CONV_LED1or CONV_IR): When this signal is high, the voltage sampled on C_LED1is

buffered and applied to the ADC for conversion. At the end of the conversion, the ADC provides a single digital

code corresponding to the LED1 sample.

8.3.1.4 Receiver Timing

See Figure 41 for a timing diagram detailing the control signals related to the LED on-time, Rx sample time, and

the ADC conversion times for each channel. Figure 41 shows the timing for a case where each phase occupies

25% of the pulse repetition period. However, this percentage is not a requirement. In cases where the device is

operated with low pulse repetition frequency (PRF) or low LED pulse durations, the active portion of the pulse

repetition period can be reduced. Using the dynamic power-down feature, the overall power consumption can be

significantly reduced.

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Red LED

ON signal

T_LEDLED ON time

<= 0.25T

IR LED

ON signal

N+1

Plethysmograph signal

N+2

N

Photo-diode current

Or

N

N+1

I-V output pulses

Ambient level

(dark level)

Rx sample time

= T_LED± settle time

S_R,

Sample Red

S_{R_amb}

,

Sample Ambient

(red phase)

S_IR,

Sample IR

S_{IR_amb}

,

Sample Ambient

(IR phase)

CONV_{IR_amb}

,

Convert ambient sample

(IR phase)

CONV_R,

Convert red sample

CONV_{R_amb}

,

Convert ambient sample

(red phase)

CONV_IR,

Convert IR sample

ADC Conversion

Pulse repetition period T = 1/PRF

T_CONV

Sample phase ± input current is converted to an analog voltage.

Sample phase width is variable from 0 to 25% duty cycle

Convert phase ± sampled analog voltage is converted to a digital code

NOTE: Relationship to the AFE4403 EVM is: LED1 = IR and LED2 = RED.

Figure 41. Rx Timing Diagram

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8.3.2 Clocking and Timing Signal Generation

The crystal oscillator generates a master clock signal using an external crystal. In the default mode, a divide-by-2

block converts the 8-MHz clock to 4 MHz, which is used by the AFE to operate the timer modules, ADC, and

diagnostics. The 4-MHz clock is buffered and output from the AFE in order to clock an external microcontroller.

The clocking functionality is shown in Figure 42.

Timer

Module

Divide-

by-2

ADC

Diagnostics

Module

Oscillator

XIN

XOUT

CLKOUT

4 MHz

8-MHz Crystal

Figure 42. AFE Clocking

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To enable flexible clocking, the AFE4403 has a clock divider with programmable division ratios. While the default

division ratio is divide-by-2, the clock divider can be programmed to select between ratios of 1, 2, 4, 6, 8, or 12.

The division ratio should be selected based on the external clock input frequency such that the divided clock has

a frequency close to 4 MHz. For this reason, CLKOUT is referred as a 4-MHz clock in this document. When

operating with an external clock input, the divider is reset based on the RESET rising edge. Figure 43 shows the

case where the divider ratio is set to divide-by-2.

Tres_setup

CLK input (on XIN)

RESET

CLKOUT

Figure 43. Clock Divider Reset

The device supports both external clock mode as well as an internal clock mode with external crystal.

In the external clock mode, an external clock is input on the XIN pin and the device internally generates the

internal clock (used by the timing engine and the ADC) by a programmable division ratio. After division, the

internal clock should be within a range of 4 MHz to 6 MHz. The exact frequency of this divided clock is one of the

pieces of information required to establish the heart rate being measured from the pulse data.

In internal clock mode, an external crystal (connected between XIN and XOUT) is used to generate the clock. To

generate sustained oscillations, the oscillator within the AFE provides negative resistance to cancel out the ESR

of the crystal. A good rule of thumb is to limit the ESR of the crystal to less than a third of the negative resistance

achievable by the oscillator. Figure 44 shows the connection of Crystal to AFE4403.

OSCILLATOR

XIN

C1

XOUT

C2

8 MHz crystal

(Csh, ESR)

Figure 44. Connection of Crystal to AFE4403

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In Figure 44 the crystal is characterized by a capacitance, C_sh(shunt capacitance of the crystal) and an

equivalent series resistance (ESR). C1 and C2 are external capacitors added at the XIN and XOUT pins.

The negative resistance achievable from the internal oscillator is given by Equation 4:

R = –1 / (2 × ω × C_sh× [1 + C_sh/ C_L])

where

•

C_L= (C1 × C2) / (C1 + C2),

ω is the frequency of oscillation in rads,

C_shis the shunt capacitor of the crystal, and

C1, C2 are the capacitors to ground from the XIN, XOUT pins. A value of approximately 15 pF is recommended for

C1, C2.

(4)

For example, with C_sh= 8 pF, C1 = C2 = 15 pF, and a frequency of 8 MHz, the result is Equation 5:

R = –600 Ω

(5)

Thus, the crystal ESR is limited to less than approximately 200 Ω.

TI highly recommends that a single clock source be used to generate the clock required by the AFE as well as

the clock needed by the microcontroller (MCU). If an independent clock source is used by the MCU, then any

energy coupling into the AFE supply or ground or input pins can cause aliased spurious tones close to the heart

rate being measured. To enable operation with the single clock source between the AFE and the MCU, two

options are possible:

1. AFE clock as master: The AFE uses a crystal to generate its clock. CLKOUT from the AFE is used as the

input clock for the MCU.

2. MCU clock as master: The AFE operates with an external clock provided by the MCU.

Note that the switching of CLKOUT consumes power. Thus, if CLKOUT is not used, it can be shut off using the

CLKOUT_TRI bit.

8.3.3 Timer Module

See Figure 45 for a timing diagram detailing the various timing edges that are programmable using the timer

module. The rising and falling edge positions of 11 signals can be controlled. The module uses a single 16-bit

counter (running off of the 4-MHz clock) to set the time-base.

All timing signals are set with reference to the pulse repetition period (PRP). Therefore, a dedicated compare

register compares the 16-bit counter value with the reference value specified in the PRF register. Every time that

the 16-bit counter value is equal to the reference value in the PRF register, the counter is reset to 0.

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LED2(Red LED)

ON signal

t_LEDLED On-Time

d 0.25 T

LED1(IR LED)

ON signal

Rx Sample Time = t_LED± Settling Time

S_{LED2_amb}

,

Sample Ambient

(LED2(Red) phase)

S_LED1

,

Sample LED1(IR)

S_{LED1_amb}

,

Sample Ambient

(LED1(IR) phase)

S_LED2

,

Sample LED2(Red)

CONV_LED2

,

Convert LED2(Red) sample

CONV_{LED2_amb}

,

Convert ambient sample

(LED2(Red) phase)

CONV_LED1

,

Convert LED1(IR) sample

CONV_{LED1_amb}

,

Convert ambient sample

(LED1(IR) phase)

ADC Conversion

ADC Reset

ADC_RDY Pin

Pulse Repetition Period (PRP)

T = 1 / PRF

NOTE: Programmable edges are shown in blue and red.

Figure 45. AFE Control Signals

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For the timing signals in Figure 41, the start and stop edge positions are programmable with respect to the PRF

period. Each signal uses a separate timer compare module that compares the counter value with

preprogrammed reference values for the start and stop edges. All reference values can be set using the SPI

interface.

After the counter value has exceeded the stop reference value, the output signal is set. When the counter value

equals the stop reference value, the output signal is reset. Figure 46 shows a diagram of the timer compare

register. With a 4-MHz clock, the edge placement resolution is 0.25 µs.

Set

START

STOP

Start Reference Register

Output

Signal

Counter

Input

Reset

Stop Reference Register

Timer Compare Register

Enable

Figure 46. Compare Register

The ADC conversion signal requires four pulses in each PRF clock period. Timer compare register 11 uses four

sets of start and stop registers to control the ADC conversion signal, as shown in Figure 47.

Reset

CLKIN

16-Bit Counter

Reset

Enable

Counter

S

R

Start

Stop

PRF

Pulse

Timer Compare

16-Bit Register 1

Timer Compare

16-Bit PRF Register

RED LED

IR LED

En

S

R

Start

Stop

S

R

Start

Stop

CONV_R,

Convert RED Sample

Timer Compare

16-Bit Register 2

Timer Compare

16-Bit Register 7

S

R

Start

Stop

S

R

S_R

Start

Stop

CONV_IR

,

Timer Compare

16-Bit Register 3

Timer Compare

16-Bit Register 8

Sample RED

Convert IR Sample

En

CONV_{IR_amb}

,

S

R

Start

Stop

S

R

S_IR

Sample IR

Start

Stop

Timer Compare

16-Bit Register 4

Timer Compare

16-Bit Register 9

Convert Ambient Sample

(IR Phase)

En

CONV_{R_amb}

,

S

R

S

R

Start

Stop

Start

Stop

Timer Compare

16-Bit Register 5

Timer Compare

16-Bit Register 10

Convert Ambient Sample

(RED Phase)

S_{R_amb}

,

Sample Ambient

(red phase)

START-A

STOP-A

S

R

Start

Stop

S_{IR_amb}

Sample Ambient

(IR phase)

,

Timer Compare

16-Bit Register 6

En

START-B

STOP-B

ADC

Timer Compare

Conversion

16-Bit Register 11

START-C

STOP-D

START-D

STOP-D

En

Timer Module

Figure 47. Timer Module

8.3.3.1 Using the Timer Module

The timer module registers can be used to program the start and end instants in units of 4-MHz clock cycles.

These timing instants and the corresponding registers are listed in Table 2.

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Note that the device does not restrict the values in these registers; thus, the start and end edges can be

positioned anywhere within the pulse repetition period. Care must be taken by the user to program suitable

values in these registers to avoid overlapping the signals and to make sure none of the edges exceed the value

programmed in the PRP register. Writing the same value in the start and end registers results in a pulse duration

of one clock cycle. The following steps describe the timer sequencing configuration:

1. With respect to the start of the PRP period (indicated by timing instant t₀in Figure 48), the following

sequence of conversions must be followed in order: convert LED2 → LED2 ambient → LED1 → LED1

ambient.

2. Also, starting from t₀, the sequence of sampling instants must be staggered with respect to the respective

conversions as follows: sample LED2 ambient → LED1 → LED1 ambient → LED2.

3. Finally, align the edges for the two LED pulses with the respective sampling instants.

Table 2. Clock Edge Mapping to SPI Registers

TIME INSTANT

(See Figure 48 and

EXAMPLE⁽²⁾

(Decimal)

Figure 49)⁽¹⁾

DESCRIPTION

Start of pulse repetition period

Start of sample LED2 pulse

End of sample LED2 pulse

Start of LED2 pulse

CORRESPONDING REGISTER ADDRESS AND REGISTER BITS

No register control

t₀

t₁

—

LED2STC[15:0], register 01h

6050

7998

6000

7999

50

t₂

LED2ENDC[15:0], register 02h

LED2LEDSTC[15:0], register 03h

LED2LEDENDC[15:0], register 04h

ALED2STC[15:0], register 05h

t₃

t₄

End of LED2 pulse

t₅

Start of sample LED2 ambient pulse

End of sample LED2 ambient pulse

Start of sample LED1 pulse

End of sample LED1 pulse

Start of LED1 pulse

t₆

ALED2ENDC[15:0], register 06h

LED1STC[15:0], register 07h

1998

2050

3998

2000

3999

4050

5998

t₇

t₈

LED1ENDC[15:0], register 08h

LED1LEDSTC[15:0], register 09h

LED1LEDENDC[15:0], register 0Ah

ALED1STC[15:0], register 0Bh

ALED1ENDC[15:0], register 0Ch

t₉

t₁₀

t₁₁

t₁₂

End of LED1 pulse

Start of sample LED1 ambient pulse

End of sample LED1 ambient pulse

LED2CONVST[15:0], register 0Dh

Must start one AFE clock cycle after the ADC reset pulse ends.

t₁₃

t₁₄

t₁₅

t₁₆

t₁₇

t₁₈

t₁₉

Start of convert LED2 pulse

4

End of convert LED2 pulse

LED2CONVEND[15:0], register 0Eh

1999

2004

3999

4004

5999

6004

ALED2CONVST[15:0], register 0Fh

Must start one AFE clock cycle after the ADC reset pulse ends.

Start of convert LED2 ambient pulse

End of convert LED2 ambient pulse

Start of convert LED1 pulse

ALED2CONVEND[15:0], register 10h

LED1CONVST[15:0], register 11h

Must start one AFE clock cycle after the ADC reset pulse ends.

End of convert LED1 pulse

LED1CONVEND[15:0], register 12h

ALED1CONVST[15:0], register 13h

Must start one AFE clock cycle after the ADC reset pulse ends.

Start of convert LED1 ambient pulse

t₂₀

t₂₁

t₂₂

t₂₃

End of convert LED1 ambient pulse

ALED1CONVEND[15:0], register 14h

ADCRSTSTCT0[15:0], register 15h

ADCRSTENDCT0[15:0], register 16h

7999

0

Start of first ADC conversion reset pulse

End of first ADC conversion reset pulse⁽³⁾

3

Start of second ADC conversion reset pulse ADCRSTSTCT1[15:0], register 17h

2000

End of second ADC conversion reset

ADCRSTENDCT1[15:0], register 18h

pulse⁽³⁾

t₂₄

2003

t₂₅

t₂₆

t₂₇

t₂₈

t₂₉

Start of third ADC conversion reset pulse

End of third ADC conversion reset pulse⁽³⁾

Start of fourth ADC conversion reset pulse

ADCRSTSTCT2[15:0], register 19h

ADCRSTENDCT2[15:0], register 1Ah

ADCRSTSTCT3[15:0], register 1Bh

4000

4003

6000

6003

7999

End of fourth ADC conversion reset pulse⁽³⁾ADCRSTENDCT3[15:0], register 1Ch

End of pulse repetition period PRPCOUNT[15:0], register 1Dh

(1) Any pulse can be set to zero width by making its start value higher than the end value.

(2) Values are based off of a pulse repetition frequency (PRF) = 500 Hz and duty cycle = 25%.

(3) See Figure 49, note 2 for the effect of the ADC reset time crosstalk.

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LED2 (RED LED)

On Signal

t₃

t₄

LED1 (IR LED)

On Signal

t₉

t₁₀

S_{LED2_amb}

Sample Ambient

LED2 (RED) Phase

,

t₆

t₅

S_LED1

,

Sample LED1 (IR)

t₇

t₈

S_{LED1_amb}

,

Sample Ambient

LED1 (IR) Phase

t₁₁

t₁₂

S_LED2

,

Sample LED2 (RED)

t₁

t₂

CONV_LED2

,

t₁₄

t₁₃

Convert LED2 (RED) Sample

CONV_{LED2_amb}

,

Convert Ambient Sample

LED2 (RED) Phase

t₁₅

t₁₆

CONV_LED1

,

t₁₇

Convert LED1 (IR) Sample

t₁₈

CONV_{LED1_amb}

,

Convert Ambient Sample

LED1 (IR) Phase

t₁₉

t₂₀

ADC Conversion

ADC Reset

t₂₃

t₂₅

t₂₇

t₂₁

t₂₂

t₂₄

t₂₆

t₂₈

Pulse Repetition Period (PRP),

One Cycle

t₀

t₂₉

(1) RED = LED2, IR = LED1.

(2) A low ADC reset time can result in a small component of the LED signal leaking into the ambient phase. With an ADC reset of two clock

cycles, a –60-dB leakage is expected. In many cases, this leakage does not affect system performance. However, if this crosstalk must be

completely eliminated, a longer ADC reset time of approximately six clock cycles is recommended for t₂₂, t₂₄, t₂₆, and t₂₈

.

Figure 48. Programmable Clock Edges⁽¹⁾⁽²⁾

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t₁₄

CONV_LED2

Convert LED2 (RED) Sample

,

t₁₃

CONV_{LED2_amb}

Convert Ambient Sample

LED2 (RED) Phase

,

t₁₆

t₁₅

t₁₈

CONV_LED1

Convert LED1 (IR) Sample

,

t₁₇

CONV_{LED1_amb}

Convert Ambient Sample

LED1 (IR) Phase

,

t₂₀

t₁₉

ADC Conversion

Two 4-MHz Clock Cycles

t₂₁

t₂₃

t₂₅

t₂₇

t₂₂

ADC Reset

t₂₄

t₂₈

t₂₆

Pulse Repetition Period (PRP),

One Cycle

t₀

t₂₉

(1) RED = LED2, IR = LED1.

(2) A low ADC reset time can result in a small component of the LED signal leaking into the ambient phase. With an ADC reset of two clock

cycles, a –60-dB leakage is expected. In many cases, this leakage does not affect system performance. However, if this crosstalk must be

completely eliminated, a longer ADC reset time of approximately six clock cycles is recommended for t₂₂, t₂₄, t₂₆, and t₂₈

.

Figure 49. Relationship Between the ADC Reset and ADC Conversion Signals⁽¹⁾⁽²⁾

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8.3.4 Receiver Subsystem Power Path

The block diagram in Figure 50 shows the AFE4403 Rx subsystem power routing. Internal LDOs running off

RX_ANA_SUP and RX_DIG_SUP generate the 1.8-V supplies required to drive the internal blocks. The two

receive supplies could be shorted to a single supply on the board.

1.8 V

RX_ANA_SUP to

RX_ANA_SUP

1.8-V Regulator

Rx Analog Modules

RX_DIG_SUP to

1.8 V

RX_DIG_SUP

1.8-V Regulator

Rx I/O

Block

I/O

Pins

Rx Digital

Device

Figure 50. Receive Subsystem Power Routing

8.3.5 Transmit Section

The transmit section integrates the LED driver and the LED current control section with 8-bit resolution.

The RED and IR LED reference currents can be independently set. The current source (I_LED) locally regulates

and ensures that the actual LED current tracks the specified reference. The transmitter section uses an internal

0.25-V reference voltage for operation. This reference voltage is available on the TX_REF pin and must be

decoupled to ground with a 2.2-μF capacitor. The TX_REF voltage is derived from the TX_CTRL_SUP. The

TX_REF voltage can be programmed from 0.25 V to 1 V. A lower TX_REF voltage allows a lower voltage to be

supported on LED_DRV_SUP. However, the transmitter dynamic range falls in proportion to the voltage on

TX_REF. Thus, a TX_REF setting of 0.5 V gives a 6-dB lower transmitter dynamic range as compared to a 1-V

setting on TX_REF, and a 6-dB higher transmitter dynamic range as compared to a 0.25-V setting on TX_REF.

Note that reducing the value of the band-gap reference capacitor on the BG pin reduces the time required for the

device to wake-up and settle. However, this reduction in time is a trade-off between wake-up time and noise

performance.For example, reducing the value of the capacitors on the BG and TX_REF pins from 2.2 uF to 0.1

uF reduces the wake-up time (from complete power-down) from 1000 ms to 100 ms, but results in a few decibels

of degradation in the transmitter dynamic range.

The minimum LED_DRV_SUP voltage required for operation depends on:

•

Voltage drop across the LED (V_LED),

Voltage drop across the external cable, connector, and any other component in series with the LED (V_CABLE),

and

•

Transmitter reference voltage.

See the Recommended Operating Conditions table for further details.

Two LED driver schemes are supported:

•

An H-bridge drive for a two-terminal back-to-back LED package; see Figure 51.

A push-pull drive for a three-terminal LED package; see Figure 52.

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LED_DRV_SUP

TX_CTRL_SUP

External

Supply

Tx

C_BULK

H-Bridge

LED2_ON

LED1_ON

H-Bridge

Driver

LED2_ON

or

LED1_ON

LED2 Current

Reference

LED

Current

Control

I_LED

8-Bit Resolution

LED1 Current

Reference

Register

LED2 Current Reference

LED1 Current Reference

Figure 51. Transmit: H-Bridge Drive

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TX_CTRL_SUP

LED_DRV_SUP

External

Supply

C_BULK

Tx

LED2_ON

LED1_ON

H-Bridge

Driver

LED2_ON

or

LED1_ON

LED2 Current

Reference

LED

Current

Control

I_LED

8-Bit Resolution

LED1 Current

Reference

Register

RED Current Reference

IR Current Reference

Figure 52. Transmit: Push-Pull LED Drive for Common Anode LED Configuration

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8.3.5.1 Third LED Support

A third LED can be optionally connected on the TX3 pin, as shown in Figure 53. An example application involving

a third LED is where the Red and IR LEDs are connected on the TXP, TXN pins for pulse oximeter applications

and a third LED (for example a Green LED) is connected on the TX3 pin for a heart rate monitoring application.

The third LED can be connected only in common anode configuration. By programming the TX3_MODE register

bit, the timing engine controls on TXP can be transferred to the TX3 pin. In this mode, the register bits that

indicate the diagnostic results on the TXP pin now indicate the diagnostic results on the TX3 pin. The selection

between using TX3 versus using TXP, TXN is intended as a static mode selection as opposed to a dynamic

switching selection. A typical time delay of approximately 20 ms is required for the receive channel to settle after

a change to the TX3_MODE setting. During this transition time, the receive signal chain should be active so that

the filters are able to settle to the new signal level from the third LED.

Figure 53. Multiplexing Third LED

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8.3.5.2 Transmitter Power Path

The block diagram in Figure 54 shows the AFE4403 Tx subsystem power routing.

TX_CTRL_SUP

Tx Reference

and

Control

LED_DRV_SUP

LED

Current

Control

DAC

Tx LED

Bridge

Device

Figure 54. Transmit Subsystem Power Routing

8.3.5.3 LED Power Reduction During Periods of Inactivity

The diagram in Figure 55 shows how LED bias current passes 50 µA whenever LED_ON occurs. In order to

minimize power consumption in periods of inactivity, the LED_ON control must be turned off. Furthermore, the

TIMEREN bit in the CONTROL1 register should be disabled by setting the value to 0.

Note that depending on the LEDs used, the LED may sometimes appear dimly lit even when the LED current is

set to 0 mA. This appearance is because of the switching leakage currents (as shown in Figure 55) inherent to

the timer function. The dimmed appearance does not effect the ambient light level measurement because during

the ambient cycle, LED_ON is turned off for the duration of the ambient measurement.

0 mA to 50 mA

(See the LEDRANGE bits

in the LEDCNTRL register.)

1 PA

50 PA

LED_ON

Figure 55. LED Bias Current

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8.3.5.4 LED Configurations

Multiple LED configurations are possible with the AFE4403.

Case 1: Red, IR LEDs in the common anode configuration for SPO2 and a Green LED for the HRM. Figure 56

shows the common anode configuration for this case. Figure 57 shows the configuration for HRM mode.

LED_DRV_SUP

Max

100mA

Max

100mA

OFF

RED

IR

TX3

TXM

TXP

LED1

Controls

LED2

Controls

LED_DRV_GND

Figure 56. SPO2 Application, Common Anode Configuration

HRM mode: Set TX3_MODE = 1.

LED_DRV_SUP

Max 50mA

RED

IR

OFF

TX3

TXM

TXP

To disable the IR

LED, set LED1

FRQWUROVꢀWRꢀµ0¶.

LED2

Controls

LED1

Controls

LED_DRV_GND

Figure 57. HRM Application Using the Third LED (Optional use of the IR LED)

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Case 2: Red, IR LEDs in an H-bridge configuration for SPO2 and a Green LED for the HRM. The H-bridge

configuration for this case is shown in Figure 58. Figure 59 shows the configuration for HRM mode.

SPO2 mode: Set TX3_MODE = 0.

LED_DRV_SUP

LED2

LED1

Controls

LED_DRV_SUP

IR

Max 100mA

OFF

TXM

TXP

TX3

RED

LED2

LED1

Controls

LED_DRV_GND

Figure 58. SPO2 Application, H-Bridge Configuration

HRM mode: Set TX3_MODE = 1.

LED_DRV_SUP

LED1

Controls

IR

Max 50mA

TXM

TXP

TX3

OFF

RED

LED2

Controls

To disable the IR

LED, set LED1

FRQWUROVꢀWRꢀµ0¶.

LED1

Controls

LED_DRV_GND

Figure 59. HRM Application Using the Third LED

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Case 3: Driving two LEDs simultaneously for HRM.

Some sensor modules have two LEDs on either side of the photodiode to make the illumination more uniform.

The two LEDs can be connected in parallel, as shown in Figure 60.

The connection shown in Figure 60 results in an equal split of the current between the two LEDs if their forward

voltages are exactly matched. High mismatch in the forward voltages of the two LEDs can cause one of them to

consume the majority of the current.

LED_DRV_SUP

TXP

TXM

TX3

Max

100mA

LED2

Controls

LED1

Controls

LED_DRV_GND

Figure 60. Using Two Parallel LEDs for an HRM Application

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Case 4: Driving two LEDs separated in time for HRM.

The two LEDs can also be driven as shown in Figure 61.

While this mode of driving the two LEDs does not drive them simultaneously, there are two advantages in this

case. First, the full current is available for driving each LED. Secondly, the mismatch in the forward voltages

between the two LEDs does not play a role.

LED_DRV_SUP

TX3

TXM

TXP

Max

100mA

TX3

LED2

Controls

LED1

Controls

LED_DRV_GND

Figure 61. Using Two Parallel LEDs for an HRM Application with Separation in Timing

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8.4 Device Functional Modes

8.4.1 ADC Operation and Averaging Module

After the falling edge of the ADC reset signal, the ADC conversion phase starts (refer to Figure 49). Each ADC

conversion takes 50 µs.

The ADC operates with averaging. The averaging module averages multiple ADC samples and reduces noise to

improve dynamic range. Figure 62 shows a diagram of the averaging module. The ADC output is a 22-bit code

that is obtained by discarding the two MSBs of the 24-bit registers (for example the register with address 2Ah),

as shown in Figure 63.

Rx Digital

ADC Reset

22-Bits

ADC Output Rate

PRF Samples per Second

Register

42

LED2 Data

ADC

Register

43

Ambient

(LED2) Data

LED2_Ambient Data

ADC

Averager

Register

44

LED1 Data

ADC Reset

Ambient

(LED1) Data

Register

45

LED1_Ambient Data

ADC Convert

ADC Clock

Figure 62. Averaging Module

Figure 63. 22-Bit Word

23

11

22

21

9

20

8

19

18

17

16

15

14

2

13

1

12

0

Ignore

22-Bit ADC Code, MSB to LSB

10

7

6

5

4

3

22-Bit ADC Code, MSB to LSB

Table 3 shows the mapping of the input voltage to the ADC to its output code.

Table 3. ADC Input Voltage Mapping

DIFFERENTIAL INPUT VOLTAGE AT ADC INPUT

22-BIT ADC OUTPUT CODE

1000000000000000000000

1111111111111111111111

0000000000000000000000

0000000000000000000001

0111111111111111111111

–1.2 V

(–1.2 / 2²¹) V

0

(1.2 / 2²¹) V

1.2 V

The data format is binary twos complement format, MSB-first. Because the TIA has a full-scale range of ±1 V, TI

recommends that the input to the ADC does not exceed ±1 V, which is approximately 80% of its full-scale.

In cases where having the processor read the data as a 24-bit word instead of a 22-bit word is more convenient,

the entire register can be mapped to the input level as shown in Figure 64.

Figure 64. 24-Bit Word

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

24-Bit ADC Code, MSB to LSB

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Table 4 shows the mapping of the input voltage to the ADC to its output code when the entire 24-bit word is

considered.

Table 4. Input Voltage Mapping

DIFFERENTIAL INPUT VOLTAGE AT ADC INPUT

24-BIT ADC OUTPUT CODE

111000000000000000000000

111111111111111111111111

000000000000000000000000

000000000000000000000001

000111111111111111111111

–1.2 V

(–1.2 / 2²¹) V

0

(1.2 / 2²¹) V

1.2 V

Now the data can be considered as a 24-bit data in binary twos complement format, MSB-first. The advantage of

using the entire 24-bit word is that the ADC output is correct, even when the input is over the normal operating

range.

8.4.1.1 Operation Without Averaging

In this mode, the ADC outputs a digital sample one time for every 50 µs. Consider a case where the ADC_RDY

signals are positioned at 25%, 50%, 75%, and 100% points in the pulse repetition period. At the next rising edge

of the ADC reset signal, the first 22-bit conversion value is written into the result registers sequentially as follows

(see Figure 65):

•

At the 25% reset signal, the first 22-bit ADC sample is written to register 2Ah.

At the 50% reset signal, the first 22-bit ADC sample is written to register 2Bh.

At the 75% reset signal, the first 22-bit ADC sample is written to register 2Ch.

At the next 0% reset signal, the first 22-bit ADC sample is written to register 2Dh. The contents of registers

2Ah and 2Bh are written to register 2Eh and the contents of registers 2Ch and 2Dh are written to register

2Fh.

At the rising edge of the ADC_RDY signal, the contents of all six result registers can be read out.

8.4.1.2 Operation With Averaging

In this mode, all ADC digital samples are accumulated and averaged after every 50 µs. At the next rising edge of

the ADC reset signal, the average value (22-bit) is written into the output registers sequentially, as follows (see

Figure 66):

•

At the 25% reset signal, the averaged 22-bit word is written to register 2Ah.

At the 50% reset signal, the averaged 22-bit word is written to register 2Bh.

At the 75% reset signal, the averaged 22-bit word is written to register 2Ch.

At the next 0% reset signal, the averaged 22-bit word is written to register 2Dh. The contents of registers 2Ah

and 2Bh are written to register 2Eh and the contents of registers 2Ch and 2Dh are written to register 2Fh.

At the rising edge of the ADC_RDY signal, the contents of all six result registers can be read out.

The number of samples to be used per conversion phase is specified in the CONTROL1 register (NUMAV[7:0]).

The user must specify the correct value for the number of averages, as described in Equation 6:

0.25 ´ Pulse Repetition Period

NUMAV[7:0] + 1 =

- 1

50 ms

(6)

Note that the 50-µs factor corresponds to a case where the internal clock of the AFE (after division) is exactly

equal to 4 MHz. The factor scales linearly with the clock period being used.

When the number of averages is 0, the averaging is disabled and only one ADC sample is written to the result

registers.

Note that the number of average conversions is limited by 25% of the PRF. For example, eight samples can be

averaged with PRF = 625 Hz, and four samples can be averaged with PRF = 1250 Hz.

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ADC Conversion

ADC Data

1

2

3

4

5

6

7

8

9

10 11 12

13 14 15 16

17 18 19 20

ADC Reset

0%

75%

50%

25%

0%

ADC Data 1 are

written into

register 42.

ADC Data 9 are

written into

register 44.

ADC Data 5 are

written into

register 43.

ADC Data 13 are written into

register 45.

Register 42 ꢀ register 43

are written into register 46.

Register 44 ꢀꢁregister 45

are written into register 47.

ADC_RDY Pin

Pulse Repetition Period (PRP)

T = 1 / PRF

1.0 T

0 T

Figure 65. ADC Data Without Averaging (When Number of Averages = 0)

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ADC Conversion

ADC Data

1

2

3

4

5

6

7

8

9

10 11 12

13 14 15 16

17 18 19 20

ADC Reset

0%

75%

50%

25%

Average of

ADC data 1 to 3 are

written into

0%

Average of

ADC data 5 to 7

are written into

register 43.

Average of

ADC data 9 to 11 are

written into

Average of

ADC data 13 to 15 are written

into register 45.

register 42.

register 44.

Register 42 ꢀ register 43

are written into register 46.

Register 44 ꢀꢁregister 45

are written into register 47.

ADC_RDY Pin

Pulse Repetition Period

T = 1 / PRF

1.0 T

0 T

NOTE: Example is with three averages. The value of the NUMAVG[7:0] register bits = 2.

Figure 66. ADC Data with Averaging Enabled

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8.4.1.3 Dynamic Power-Down Mode

When operated at low PRF, a dynamic power-down mode can be optionally enabled to shut off blocks during a

portion of each period. This operation is illustrated in Figure 67. The dynamic power-down signal (called

PDN_CYCLE) can be internally generated using the timing controller. PDN_CYCLE can be used to shut off

power to internal blocks during the unused section within each pulse repetition period.

Pulse repetition period

Sample LED2

Sample Ambient 2

Sample LED1

Sample Ambient 1

Convert LED2

Convert Ambient 2

Convert LED1

Convert Ambient 1

PDN_CYCLE

t₁

t₂

Figure 67. Dynamic Power-Down Mode Timing

t₁and t₂denote the timing margin between the active portion of the period and the dynamic power-down signal.

TI recommends setting t₁> 50 µs and t₂> 200 µs in order to ensure sufficient time for the shutdown blocks to

recover from power-down. By choosing the blocks that are shut down during dynamic power-down, a power

savings of anywhere between 35% to 70% power can be achieved when the PDN_CYCLE phase is active.

The sequence of the convert phases within a pulse repetition period should be as follows: LED2 (Red) →

Ambient 2 → LED1 (IR) → Ambient 1. The sample phases must precede the corresponding convert phase. Also

note that the ADC_RDY signal comes at the beginning of the pulse repetition period. Thus, the contents of the

registers must be read before the completion of the first conversion phase in the pulse repetition period. These

contents correspond to the samples of the four phases from the previous pulse repetition period.

The DYNAMIC1, DYNAMIC2, DYNAMIC3, and DYNAMIC4 bits determine which blocks are powered down

during the dynamic power-down state (when PDN_CYCLE is high). For maximum power saving, all four bits can

be set to 1. TI recommends setting t₁to greater than 100 µs and t₂to greater than 200 µs to ensure that the

blocks recover from power-down in time for the next cycle.

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The bit corresponding to the TIA power-down (DYNAMIC3) needs a bit more consideration. When the TIA is

powered down, the TIA no longer maintains the bias across the photodiode output. This loss of bias can cause

the photodiode output voltage to drift from the normal value. The recovery time constant associated with the

photodiode returning to a proper bias condition (when the TIA is powered back on) is approximately equal to 2 ×

C_PD× R_F, where C_PDis the effective differential capacitance of the photodiode and R_Fis the TIA gain setting.

This consideration might result in a different choice for the value of t₂.

8.4.2 Diagnostics

The device includes diagnostics to detect open or short conditions of the LED and photosensor, LED current

profile feedback, and cable on or off detection.

8.4.2.1 Photodiode-Side Fault Detection

Figure 68 shows the diagnostic for the photodiode-side fault detection.

Internal

TX_CTRL_SUP

10 kꢀ

1 kꢀ

Cable

Rx On/Off

INN

INP

To Rx Front-End

Rx On/Off

GND Wires

PD Wires

LED Wires

Legend for Cable

Figure 68. Photodiode Diagnostic

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8.4.2.2 Transmitter-Side Fault Detection

Figure 69 shows the diagnostic for the transmitter-side fault detection.

Internal

TX_CTRL_SUP

10 kꢀ

Cable

TXP

D

C

TXN

GND Wires

PD Wires

LED DAC

LED Wires

Legend for Cable

Figure 69. Transmitter Diagnostic

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Figure 70 shows the timing for the diagnostic function.

DIAG_EN Register Bit = 1

Diagnostic State

Machine

Diagnostic State Machine

Diagnostic Starts

Diagnostic Ends

DIAG_END Pin

t_WIDTH= Four 4-MHz

Clock Cycles

t_DIAG

Figure 70. Diagnostic Timing Diagram

By default, the diagnostic function takes t_DIAG= 16 ms to complete. After the diagnostics function completes, the

AFE4403 filter must be allowed time to settle. See the Electrical Characteristics for the filter settling time.

8.5 Programming

8.5.1 Serial Programming Interface

The SPI-compatible serial interface consists of four signals: SCLK (serial clock), SPISOMI (serial interface data

output), SPISIMO (serial interface data input), and SPISTE (serial interface enable).

The serial clock (SCLK) is the serial peripheral interface (SPI) serial clock. SCLK shifts in commands and shifts

out data from the device. SCLK features a Schmitt-triggered input and clocks data out on the SPISOMI. Data are

clocked in on the SPISIMO pin. Even though the input has hysteresis, TI recommends keeping SCLK as clean

as possible to prevent glitches from accidentally shifting the data. When the serial interface is idle, hold SCLK

low.

The SPI serial out master in (SPISOMI) pin is used with SCLK to clock out the AFE4403 data. The SPI serial in

master out (SPISIMO) pin is used with SCLK to clock in data to the AFE4403. The SPI serial interface enable

(SPISTE) pin enables the serial interface to clock data on the SPISIMO pin in to the device.

8.5.2 Reading and Writing Data

The device has a set of internal registers that can be accessed by the serial programming interface formed by

the SPISTE, SCLK, SPISIMO, and SPISOMI pins.

8.5.2.1 Writing Data

The SPI_READ register bit must be first set to 0 before writing to a register. When SPISTE is low:

•

Serially shifting bits into the device is enabled.

Serial data (on the SPISIMO pin) are latched at every SCLK rising edge.

The serial data are loaded into the register at every 32nd SCLK rising edge.

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Programming (continued)

In case the word length exceeds a multiple of 32 bits, the excess bits are ignored. Data can be loaded in

multiples of 32-bit words within a single active SPISTE pulse. The first eight bits form the register address and

the remaining 24 bits form the register data. Figure 71 shows an SPI timing diagram for a single write operation.

For multiple read and write cycles, refer to the Multiple Data Reads and Writes section.

SPISTE

SPISIMO

SCLK

A7

A6

A1

A0

D23 D22

D17 D16

D15 D14

D9

D8

D7

D6

D1

D0

'RQ¶WꢀFDUH, can be high or low.

Figure 71. AFE SPI Write Timing Diagram

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Programming (continued)

8.5.2.2 Reading Data

The SPI_READ register bit must be first set to 1 before reading from a register. The AFE4403 includes a mode

where the contents of the internal registers can be read back on the SPISOMI pin. This mode may be useful as a

diagnostic check to verify the serial interface communication between the external controller and the AFE. To

enable this mode, first set the SPI_READ register bit using the SPI write command, as described in the Writing

Data section. In the next command, specify the SPI register address with the desired content to be read. Within

the same SPI command sequence, the AFE outputs the contents of the specified register on the SPISOMI pin.

Figure 72 shows an SPI timing diagram for a single read operation. For multiple read and write cycles, refer to

the Multiple Data Reads and Writes section.

SPISTE

SPISIMO

SPISOMI

A7

A6

A1

A0

D23 D22

D17 D16

D15 D14

D9

D8

D7

D6

D1

D0

SCLK

'RQ¶WꢀFDUH, can be high or low.

(1) The SPI_READ register bit must be enabled before attempting a serial readout from the AFE.

(2) Specify the register address of the content that must be readback on bits A[7:0].

(3) The AFE outputs the contents of the specified register on the SPISOMI pin.

Figure 72. AFE SPI Read Timing Diagram

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8.5.2.4 Register Initialization

After power-up, the internal registers must be initialized to the default values. This initialization can be done in

one of two ways:

•

Through a hardware reset by applying a low-going pulse on the RESET pin, or

By applying a software reset. Using the serial interface, set SW_RESET (bit D3 in register 00h) high. This

setting initializes the internal registers to the default values and then self-resets to 0. In this case, the RESET

pin is kept high (inactive).

8.5.2.5 AFE SPI Interface Design Considerations

Note that when the AFE4403 is deselected, the SPISOMI, CLKOUT, ADC_RDY, and DIAG_END digital output

pins do not enter a 3-state mode. This condition, therefore, must be taken into account when connecting multiple

devices to the SPI port and for power-management considerations. In order to avoid loading the SPI bus when

multiple devices are connected, the SOMI_TRI register bit must be to 1 whenever the AFE SPI is inactive. The

DIGOUT_TRISTATE register bit must be set to 1 to tri-state the ADC_RDY and DIAG_END pins. The

CLKOUT_TRI register bit must be set to 1 to put the CLKOUT buffer in tri-state mode.

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8.6.2 AFE Register Description

Figure 74. CONTROL0: Control Register 0 (Address = 00h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

0

14

0

13

0

12

0

11

10

9

8

7

6

5

4

3

2

1

0

TIM_

SPI_

READ

0

SW_RST DIAG_EN COUNT_

RST

This register is write-only. CONTROL0 is used for AFE software and count timer reset, diagnostics enable, and

SPI read functions.

Bits 23:4

Bit 3

Must be 0

SW_RST: Software reset

0 = No action (default after reset)

1 = Software reset applied; resets all internal registers to the default values and self-clears

to 0

Bit 2

DIAG_EN: Diagnostic enable

0 = No action (default after reset)

1 = Diagnostic mode is enabled and the diagnostics sequence starts when this bit is set.

At the end of the sequence, all fault status are stored in the DIAG: Diagnostics Flag

Register. Afterwards, the DIAG_EN register bit self-clears to 0.

Note that the diagnostics enable bit is automatically reset after the diagnostics completes

(16 ms). During the diagnostics mode, ADC data are invalid because of the toggling

diagnostics switches.

Bit 1

Bit 0

TIM_CNT_RST: Timer counter reset

0 = Disables timer counter reset, required for normal timer operation (default after reset)

1 = Timer counters are in reset state

SPI READ: SPI read

0 = SPI read is disabled (default after reset)

1 = SPI read is enabled

Figure 75. LED2STC: Sample LED2 Start Count Register (Address = 01h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

0

LED2STC[15:0]

11

10

9

8

7

6

5

4

3

2

1

LED2STC[15:0]

This register sets the start timing value for the LED2 signal sample.

Bits 23:16

Bits 15:0

Must be 0

LED2STC[15:0]: Sample LED2 start count

The contents of this register can be used to position the start of the sample LED2 signal with

respect to the pulse repetition period (PRP), as specified in the PRPCOUNT register. The

count is specified as the number of

4-MHz clock cycles. Refer to the Using the Timer Module section for details.

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Figure 76. LED2ENDC: Sample LED2 End Count Register (Address = 02h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

LED2ENDC[15:0]

11

10

9

8

7

6

5

4

3

2

1

0

LED2ENDC[15:0]

This register sets the end timing value for the LED2 signal sample.

Bits 23:16

Bits 15:0

Must be 0

LED2ENDC[15:0]: Sample LED2 end count

The contents of this register can be used to position the end of the sample LED2 signal with

respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the

number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.

Figure 77. LED2LEDSTC: LED2 LED Start Count Register (Address = 03h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

LED2LEDSTC[15:0]

11

10

9

8

7

6

5

4

3

2

1

0

LED2LEDSTC[15:0]

This register sets the start timing value for when the LED2 signal turns on.

Bits 23:16

Bits 15:0

Must be 0

LED2LEDSTC[15:0]: LED2 start count

The contents of this register can be used to position the start of the LED2 with respect to the

PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-

MHz clock cycles. Refer to the Using the Timer Module section for details.

Figure 78. LED2LEDENDC: LED2 LED End Count Register (Address = 04h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

LED2LEDENDC[15:0]

11

10

9

8

7

6

5

4

3

2

1

0

LED2LEDENDC[15:0]

This register sets the end timing value for when the LED2 signal turns off.

Bits 23:16

Bits 15:0

Must be 0

LED2LEDENDC[15:0]: LED2 end count

The contents of this register can be used to position the end of the LED2 signal with respect

to the PRP, as specified in the PRPCOUNT register. The count is specified as the number

of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.

62

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Figure 79. ALED2STC: Sample Ambient LED2 Start Count Register (Address = 05h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

ALED2STC[15:0]

11

10

9

8

7

6

5

4

3

2

1

0

ALED2STC[15:0]

This register sets the start timing value for the ambient LED2 signal sample.

Bits 23:16

Bits 15:0

Must be 0

ALED2STC[15:0]: Sample ambient LED2 start count

The contents of this register can be used to position the start of the sample ambient LED2

signal with respect to the PRP, as specified in the PRPCOUNT register. The count is

specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section

for details.

Figure 80. ALED2ENDC: Sample Ambient LED2 End Count Register

(Address = 06h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

0

ALED2ENDC[15:0]

11

10

9

8

7

6

5

4

3

2

1

ALED2ENDC[15:0]

This register sets the end timing value for the ambient LED2 signal sample.

Bits 23:16

Bits 15:0

Must be 0

ALED2ENDC[15:0]: Sample ambient LED2 end count

The contents of this register can be used to position the end of the sample ambient LED2

signal with respect to the PRP, as specified in the PRPCOUNT register. The count is

specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section

for details.

Figure 81. LED1STC: Sample LED1 Start Count Register (Address = 07h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

0

LED1STC[15:0]

11

10

9

8

7

6

5

4

3

2

1

LED1STC[15:0]

This register sets the start timing value for the LED1 signal sample.

Bits 23:17

Bits 16:0

Must be 0

LED1STC[15:0]: Sample LED1 start count

The contents of this register can be used to position the start of the sample LED1 signal with

respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the

number of

4-MHz clock cycles. Refer to the Using the Timer Module section for details.

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Figure 82. LED1ENDC: Sample LED1 End Count (Address = 08h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

0

LED1ENDC[15:0]

11

10

9

8

7

6

5

4

3

2

1

LED1ENDC[15:0]

This register sets the end timing value for the LED1 signal sample.

Bits 23:17

Bits 16:0

Must be 0

LED1ENDC[15:0]: Sample LED1 end count

The contents of this register can be used to position the end of the sample LED1 signal with

respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the

number of

4-MHz clock cycles. Refer to the Using the Timer Module section for details.

Figure 83. LED1LEDSTC: LED1 LED Start Count Register (Address = 09h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

LED1LEDSTC[15:0]

11

10

9

8

7

6

5

4

3

2

1

0

LED1LEDSTC[15:0]

This register sets the start timing value for when the LED1 signal turns on.

Bits 23:16

Bits 15:0

Must be 0

LED1LEDSTC[15:0]: LED1 start count

The contents of this register can be used to position the start of the LED1 signal with respect

to the PRP, as specified in the PRPCOUNT register. The count is specified as the number

of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.

Figure 84. LED1LEDENDC: LED1 LED End Count Register (Address = 0Ah, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

LED1LEDENDC[15:0]

11

10

9

8

7

6

5

4

3

2

1

0

LED1LEDENDC[15:0]

This register sets the end timing value for when the LED1 signal turns off.

Bits 23:16

Bits 15:0

Must be 0

LED1LEDENDC[15:0]: LED1 end count

The contents of this register can be used to position the end of the LED1 signal with respect

to the PRP, as specified in the PRPCOUNT register. The count is specified as the number

of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.

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Figure 85. ALED1STC: Sample Ambient LED1 Start Count Register (Address = 0Bh, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

ALED1STC[15:0]

11

10

9

8

7

6

5

4

3

2

1

0

ALED1STC[15:0]

This register sets the start timing value for the ambient LED1 signal sample.

Bits 23:16

Bits 15:0

Must be 0

ALED1STC[15:0]: Sample ambient LED1 start count

The contents of this register can be used to position the start of the sample ambient LED1

signal with respect to the PRP, as specified in the PRPCOUNT register. The count is

specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section

for details.

Figure 86. ALED1ENDC: Sample Ambient LED1 End Count Register

(Address = 0Ch, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

0

ALED1ENDC[15:0]

11

10

9

8

7

6

5

4

3

2

1

ALED1ENDC[15:0]

This register sets the end timing value for the ambient LED1 signal sample.

Bits 23:16

Bits 15:0

Must be 0

ALED1ENDC[15:0]: Sample ambient LED1 end count

The contents of this register can be used to position the end of the sample ambient LED1

signal with respect to the PRP, as specified in the PRPCOUNT register. The count is

specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section

for details.

Figure 87. LED2CONVST: LED2 Convert Start Count Register (Address = 0Dh, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

LED2CONVST[15:0]

11

10

9

8

7

6

5

4

3

2

1

0

LED2CONVST[15:0]

This register sets the start timing value for the LED2 conversion.

Bits 23:16

Bits 15:0

Must be 0

LED2CONVST[15:0]: LED2 convert start count

The contents of this register can be used to position the start of the LED2 conversion signal

with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as

the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.

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Figure 88. LED2CONVEND: LED2 Convert End Count Register (Address = 0Eh, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

LED2CONVEND[15:0]

11

10

9

8

7

6

5

4

3

2

1

0

LED2CONVEND[15:0]

This register sets the end timing value for the LED2 conversion.

Bits 23:16

Bits 15:0

Must be 0

LED2CONVEND[15:0]: LED2 convert end count

The contents of this register can be used to position the end of the LED2 conversion signal

with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as

the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.

Figure 89. ALED2CONVST: LED2 Ambient Convert Start Count Register

(Address = 0Fh, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

0

ALED2CONVST[15:0]

11

10

9

8

7

6

5

4

3

2

1

ALED2CONVST[15:0]

This register sets the start timing value for the ambient LED2 conversion.

Bits 23:16

Bits 15:0

Must be 0

ALED2CONVST[15:0]: LED2 ambient convert start count

The contents of this register can be used to position the start of the LED2 ambient

conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The

count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer

Module section for details.

Figure 90. ALED2CONVEND: LED2 Ambient Convert End Count Register

(Address = 10h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

0

ALED2CONVEND[15:0]

11

10

9

8

7

6

5

4

3

2

1

ALED2CONVEND[15:0]

This register sets the end timing value for the ambient LED2 conversion.

Bits 23:16

Bits 15:0

Must be 0

ALED2CONVEND[15:0]: LED2 ambient convert end count

The contents of this register can be used to position the end of the LED2 ambient

conversion signal with respect to the PRP. The count is specified as the number of 4-MHz

clock cycles. Refer to the Using the Timer Module section for details.

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Figure 91. LED1CONVST: LED1 Convert Start Count Register (Address = 11h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

LED1CONVST[15:0]

11

10

9

8

7

6

5

4

3

2

1

0

LED1CONVST[15:0]

This register sets the start timing value for the LED1 conversion.

Bits 23:16

Bits 15:0

Must be 0

LED1CONVST[15:0]: LED1 convert start count

The contents of this register can be used to position the start of the LED1 conversion signal

with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as

the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.

Figure 92. LED1CONVEND: LED1 Convert End Count Register (Address = 12h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

LED1CONVEND[15:0]

11

10

9

8

7

6

5

4

3

2

1

0

LED1CONVEND[15:0]

This register sets the end timing value for the LED1 conversion.

Bits 23:16

Bits 15:0

Must be 0

LED1CONVEND[15:0]: LED1 convert end count

The contents of this register can be used to position the end of the LED1 conversion signal

with respect to the PRP. The count is specified as the number of 4-MHz clock cycles. Refer

to the Using the Timer Module section for details.

Figure 93. ALED1CONVST: LED1 Ambient Convert Start Count Register

(Address = 13h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

0

ALED1CONVST[15:0]

11

10

9

8

7

6

5

4

3

2

1

ALED1CONVST[15:0]

This register sets the start timing value for the ambient LED1 conversion.

Bits 23:16

Bits 15:0

Must be 0

ALED1CONVST[15:0]: LED1 ambient convert start count

The contents of this register can be used to position the start of the LED1 ambient

conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The

count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer

Module section for details.

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Figure 94. ALED1CONVEND: LED1 Ambient Convert End Count Register

(Address = 14h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

0

ALED1CONVEND[15:0]

11

10

9

8

7

6

5

4

3

2

1

ALED1CONVEND[15:0]

This register sets the end timing value for the ambient LED1 conversion.

Bits 23:16

Bits 15:0

Must be 0

ALED1CONVEND[15:0]: LED1 ambient convert end count

The contents of this register can be used to position the end of the LED1 ambient

conversion signal with respect to the PRP. The count is specified as the number of 4-MHz

clock cycles. Refer to the Using the Timer Module section for details.

Figure 95. ADCRSTSTCT0: ADC Reset 0 Start Count Register (Address = 15h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

ADCRSTSTCT0[15:0]

11

10

9

8

7

6

5

4

3

2

1

0

ADCRSTSTCT0[15:0]

This register sets the start position of the ADC0 reset conversion signal.

Bits 23:16

Bits 15:0

Must be 0

ADCRSTSTCT0[15:0]: ADC RESET 0 start count

The contents of this register can be used to position the start of the ADC reset conversion

signal (default value after reset is 0000h). Refer to the Using the Timer Module section for

details.

Figure 96. ADCRSTENDCT0: ADC Reset 0 End Count Register (Address = 16h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

ADCRSTENDCT0[15:0]

11

10

9

8

7

6

5

4

3

2

1

0

ADCRSTENDCT0[15:0]

This register sets the end position of the ADC0 reset conversion signal.

Bits 23:16

Bits 15:0

Must be 0

ADCRSTENDCT0[15:0]: ADC RESET 0 end count

The contents of this register can be used to position the end of the ADC reset conversion

signal (default value after reset is 0000h). Refer to the Using the Timer Module section for

details.

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Figure 97. ADCRSTSTCT1: ADC Reset 1 Start Count Register (Address = 17h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

ADCRSTSTCT1[15:0]

11

10

9

8

7

6

5

4

3

2

1

0

ADCRSTSTCT1[15:0]

This register sets the start position of the ADC1 reset conversion signal.

Bits 23:16

Bits 15:0

Must be 0

ADCRSTSTCT1[15:0]: ADC RESET 1 start count

The contents of this register can be used to position the start of the ADC reset conversion.

Refer to the Using the Timer Module section for details.

Figure 98. ADCRSTENDCT1: ADC Reset 1 End Count Register (Address = 18h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

ADCRSTENDCT1[15:0]

11

10

9

8

7

6

5

4

3

2

1

0

ADCRSTENDCT1[15:0]

This register sets the end position of the ADC1 reset conversion signal.

Bits 23:16

Bits 15:0

Must be 0

ADCRSTENDCT1[15:0]: ADC RESET 1 end count

The contents of this register can be used to position the end of the ADC reset conversion.

Refer to the Using the Timer Module section for details.

Figure 99. ADCRSTSTCT2: ADC Reset 2 Start Count Register (Address = 19h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

ADCRSTSTCT2[15:0]

11

10

9

8

7

6

5

4

3

2

1

0

ADCRSTSTCT2[15:0]

This register sets the start position of the ADC2 reset conversion signal.

Bits 23:16

Bits 15:0

Must be 0

ADCRSTSTCT2[15:0]: ADC RESET 2 start count

The contents of this register can be used to position the start of the ADC reset conversion.

Refer to the Using the Timer Module section for details.

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Figure 100. ADCRSTENDCT2: ADC Reset 2 End Count Register (Address = 1Ah, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

ADCRSTENDCT2[15:0]

11

10

9

8

7

6

5

4

3

2

1

0

ADCRSTENDCT2[15:0]

This register sets the end position of the ADC2 reset conversion signal.

Bits 23:16

Bits 15:0

Must be 0

ADCRSTENDCT2[15:0]: ADC RESET 2 end count

The contents of this register can be used to position the end of the ADC reset conversion.

Refer to the Using the Timer Module section for details.

Figure 101. ADCRSTSTCT3: ADC Reset 3 Start Count Register (Address = 1Bh, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

ADCRSTSTCT3[15:0]

11

10

9

8

7

6

5

4

3

2

1

0

ADCRSTSTCT3[15:0]

This register sets the start position of the ADC3 reset conversion signal.

Bits 23:16

Bits 15:0

Must be 0

ADCRSTSTCT3[15:0]: ADC RESET 3 start count

The contents of this register can be used to position the start of the ADC reset conversion.

Refer to the Using the Timer Module section for details.

Figure 102. ADCRSTENDCT3: ADC Reset 3 End Count Register (Address = 1Ch, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

ADCRSTENDCT3[15:0]

11

10

9

8

7

6

5

4

3

2

1

0

ADCRSTENDCT3[15:0]

This register sets the end position of the ADC3 reset conversion signal.

Bits 23:16

Bits 15:0

Must be 0

ADCRSTENDCT3[15:0]: ADC RESET 3 end count

The contents of this register can be used to position the end of the ADC reset conversion

signal (default value after reset is 0000h). Refer to the Using the Timer Module section for

details.

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Figure 103. PRPCOUNT: Pulse Repetition Period Count Register (Address = 1Dh, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

PRPCOUNT[15:0]

11

10

9

8

7

6

5

4

3

2

1

0

PRPCOUNT[15:0]

This register sets the device pulse repetition period count.

Bits 23:16

Bits 15:0

Must be 0

PRPCOUNT[15:0]: Pulse repetition period count

The contents of this register can be used to set the pulse repetition period (in number of

clock cycles of the 4-MHz clock). The PRPCOUNT value must be set in the range of 800 to

64000. Values below 800 do not allow sufficient sample time for the four samples; see the

Electrical Characteristics table.

Figure 104. CONTROL1: Control Register 1 (Address = 1Eh, Reset Value = 0000h)

23

0

22

0

21

0

20

19

0

18

0

17

0

16

0

15

0

14

0

13

0

12

0

8

11

0

10

0

9

7

6

5

4

3

2

1

0

TIMEREN

NUMAV[7:0]

This register configures the clock alarm pin and timer.

Bits 23:9

Bit 8

Must be 0

TIMEREN: Timer enable

0 = Timer module is disabled and all internal clocks are off (default after reset)

1 = Timer module is enabled

Bits 7:0

NUMAV[7:0]: Number of averages

Specify an 8-bit value corresponding to the number of ADC samples to be averaged – 1.

For example, to average four ADC samples, set NUMAV[7:0] equal to 3.

The maximum number of averages is 16. Any setting of NUMAV[7:0] greater than or equal

to a decimal value of 15 results in the number of averages getting set to 16.

Figure 105. SPARE1: SPARE1 Register For Future Use (Address = 1Fh, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

0

14

0

13

0

12

0

11

0

10

0

9

8

7

6

5

4

3

2

1

0

This register is a spare register and is reserved for future use.

Bits 23:0 Must be 0

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Figure 106. TIAGAIN: Transimpedance Amplifier Gain Setting Register

(Address = 20h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

0

12

0

ENSEP

GAIN

STAGE2

EN1

11

0

10

9

8

7

6

5

4

3

2

1

0

STG2GAIN1[2:0]

CF_LED1[4:0]

RF_LED1[2:0]

This register sets the device transimpedance amplifier gain mode and feedback resistor and capacitor values.

Bits 23:16

Bit 15

Must be 0

ENSEPGAIN: Enable separate gain mode

0 = The R_F, C_Fvalues and stage 2 gain settings are the same for both the LED2 and LED1

signals; the values are specified by the bits (RF_LED2, CF_LED2, STAGE2EN2,

STG2GAIN2) in the TIA_AMB_GAIN register (default after reset)

1 = The R_F, C_Fvalues and stage 2 gain settings can be independently set for the LED2 and

LED1 signals. The values for LED1 are specified using the bits (RF_LED1, CF_LED1,

STAGE2EN1, STG2GAIN1) in the TIAGAIN register, whereas the values for LED2 are

specified using the corresponding bits in the TIA_AMB_GAIN register.

Bit 14

STAGE2EN1: Enable stage 2 for LED 1

0 = Stage 2 is bypassed (default after reset)

1 = Stage 2 is enabled with the gain value specified by the STG2GAIN1[2:0] bits

Bits 13:11

Bits 10:8

Must be 0

STG2GAIN1[2:0]: Program stage 2 gain for LED1

000 = 0 dB, or linear gain of 1 (default after

reset)

100 = 12 dB, or linear gain of 4

101 = Do not use

001 = 3.5 dB, or linear gain of 1.5

010 = 6 dB, or linear gain of 2

011 = 9.5 dB, or linear gain of 3

110 = Do not use

111 = Do not use

Bits 7:3

Bits 2:0

CF_LED1[4:0]: Program C_Ffor LED1

00000 = 5 pF (default after reset)

00001 = 5 pF + 5 pF

00010 = 15 pF + 5 pF

00100 = 25 pF + 5 pF

01000 = 50 pF + 5 pF

10000 = 150 pF + 5 pF

Note that any combination of these C_Fsettings is also supported by setting multiple bits to 1.

For example, to obtain C_F= 100 pF, set bits 7:3 = 01111.

RF_LED1[2:0]: Program R_Ffor LED1

000 = 500 kΩ (default after reset)

001 = 250 kΩ

010 = 100 kΩ

100 = 25 kΩ

101 = 10 kΩ

110 = 1 MΩ

111 = None

011 = 50 kΩ

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Figure 107. TIA_AMB_GAIN: Transimpedance Amplifier and Ambient Cancellation Stage Gain Register

(Address = 21h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

18

17

16

15

14

13

0

12

0

FLTR

CNRSEL

STAGE2

EN2

AMBDAC[3:0]

11

0

10

9

8

7

6

5

4

3

2

1

0

STG2GAIN[2:0]

CF_LED2[4:0]

RF_LED2[2:0]

This register configures the ambient light cancellation amplifier gain, cancellation current, and filter corner

frequency.

Bits 23:20

Bits 19:16

Must be 0

AMBDAC[3:0]: Ambient DAC value

These bits set the value of the cancellation current.

0000 = 0 µA (default after reset)

0001 = 1 µA

1000 = 8 µA

1001 = 9 µA

0010 = 2 µA

1010 = 10 µA

0011 = 3 µA

0100 = 4 µA

0101 = 5 µA

0110 = 6 µA

1011 = Do not use

1100 = Do not use

1101 = Do not use

1110 = Do not use

1111 = Do not use

0111 = 7 µA

Bit 15

Bit 14

Must be 0

STAGE2EN2: Stage 2 enable for LED 2

0 = Stage 2 is bypassed (default after reset)

1 = Stage 2 is enabled with the gain value specified by the STG2GAIN2[2:0] bits

Bits 13:11

Bits 10:8

Must be 0

STG2GAIN2[2:0]: Stage 2 gain setting for LED 2

000 = 0 dB, or linear gain of 1 (default after reset)

001 = 3.5 dB, or linear gain of 1.5

010 = 6 dB, or linear gain of 2

011 = 9.5 dB, or linear gain of 3

100 = 12 dB, or linear gain of 4

101 = Do not use

110 = Do not use

111 = Do not use

Bits 7:3

Bits 2:0

CF_LED[4:0]: Program C_Ffor LEDs

00000 = 5 pF (default after reset)

00001 = 5 pF + 5 pF

00010 = 15 pF + 5 pF

00100 = 25 pF + 5 pF

01000 = 50 pF + 5 pF

10000 = 150 pF + 5 pF

Note that any combination of these C_Fsettings is also supported by setting multiple bits to 1.

For example, to obtain C_F= 100 pF, set D[7:3] = 01111.

RF_LED[2:0]: Program R_Ffor LEDs

000 = 500 kΩ

001 = 250 kΩ

010 = 100 kΩ

011 = 50 kΩ

100 = 25 kΩ

101 = 10 kΩ

110 = 1 MΩ

111 = None

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Figure 108. LEDCNTRL: LED Control Register (Address = 22h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

16

15

14

13

12

0

LED_RANGE[1:0]

LED1[7:0]

11

10

9

8

7

6

5

4

3

2

1

LED1[7:0]

LED2[7:0]

This register sets the LED current range and the LED1 and LED2 drive current.

Bits 23:18

Bits 17:16

Must be 0

LED_RANGE[1:0]: LED range

These bits program the full-scale LED current range for Tx. Table 7 details the settings.

Bits 15:8

LED1[7:0]: Program LED current for LED1 signal

Use these register bits to specify the LED current setting for LED1 (default after reset is

00h).

The nominal value of the LED current is given by Equation 7, where the full-scale LED

current is either 0 mA or 50 mA (as specified by the LED_RANGE[1:0] register bits).

Bits 7:0

LED2[7:0]: Program LED current for LED2 signal

Use these register bits to specify the LED current setting for LED2 (default after reset is

00h).

The nominal value of LED current is given by Equation 8, where the full-scale LED current is

either 0 mA or 50 mA (as specified by the LED_RANGE[1:0] register bits).

Table 7. Full-Scale LED Current across Tx Reference Voltage Settings⁽¹⁾

TX_REF = 0.25 V

TX_REF = 0.5 V

TX_REF = 0.75 V

TX_REF = 1.0 V

LED_RANGE[1:

0]

(2)

I_MAX

V_HR

I_MAX

V_HR

I_MAX

V_HR

I_MAX

V_HR

00 (default after

reset)

50 mA

0.75 V

100 mA

1.1 V

Do not use

—

Do not use

—

01

10

11

25 mA

50 mA

0.7 V

0.75 V

—

50 mA

100 mA

Tx is off

1.0 V

1.1 V

—

75 mA

Do not use

Tx is off

1.3 V

—

100 mA

Do not use

Tx is off

1.6 V

—

Tx is off

—

(1) For a 3-V to 3.6-V supply, use TX_REF = 0.25 or 0.5 V. For a 4.75-V to 5.25-V supply, use TX_REF = 0.75 V or 1.0 V.

(2) V_HRrefers to the headroom voltage (over and above the LED forward voltage and cable voltage drop) needed on the LED_DRV_SUP.

The V_HRvalues specified are for the H-bridge configuration. In the common anode configuration, V_HRcan be lower by 0.25 V.

LED1[7:0]

´ Full-Scale Current

256

(7)

LED2[7:0]

´ Full-Scale Current

256

(8)

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Figure 109. CONTROL2: Control Register 2 (Address = 23h, Reset Value = 0000h)

23

0

22

0

21

0

20

19

0

18

17

16

0

15

0

14

13

0

12

0

DYNAMI

C1

DYNAMI

C2

TX_REF1 TX_REF0

11

10

9

8

7

6

0

5

0

4

3

2

1

0

DIGOUT_

TRI

STATE

EN_

SLOW_

DIAG

TXBRG

MOD

XTAL

DIS

DYNAMI DYNAMI

C3 C4

0

PDNTX

PDNRX PDNAFE

This register controls the LED transmitter, crystal, and the AFE, transmitter, and receiver power modes.

Bits 23:21

Bit 20

Must be 0

DYNAMIC1

0 = Transmitter is not powered down during dynamic power-down phase

1 = Transmitter is powered down during dynamic power-down phase

Bit 19

Must be 0

Bits 18:17

TX_REF[1:0]: Tx reference voltage

These bits set the transmitter reference voltage. This Tx reference voltage is available on

the device TX_REF pin.

00 = 0.25-V Tx reference voltage (default value after reset)

01 = 0.5-V Tx reference voltage

10 = 1.0-V Tx reference voltage

11 = 0.75-V Tx reference voltage, D3

Bits 16:15

Bit 14

Must be 0

DYNAMIC2

0 = Part of the ADC is not powered down during dynamic power-down phase

1 = Part of the ADC is powered down during dynamic power-down phase

Bit 11

Bit 10

Bit 9

TXBRGMOD: Tx bridge mode

0 = LED driver is configured as an H-bridge (default after reset)

1 = LED driver is configured as a push-pull

DIGOUT_TRISTATE: Tri-state bit for the ADC_RDY and DIAG_END pins

0 = ADC_RDY and DIAG_END are not tri-stated

1 = ADC_RDY and DIAG_END are tri-stated

XTALDIS: Crystal disable mode

0 = The crystal module is enabled; the 8-MHz crystal must be connected to the XIN and

XOUT pins

1 = The crystal module is disabled; an external 8-MHz clock must be applied to the XIN pin

Bit 8

EN_SLOW_DIAG: Fast diagnostics mode enable

0 = Fast diagnostics mode, 8 ms (default value after reset)

1 = Slow diagnostics mode, 16 ms

Bits 7:5

Bit 4

Must be 0

DYNAMIC3

0 = TIA is not powered down during dynamic power-down phase

1 = TIA is powered down during dynamic power-down phase

Bit 3

DYNAMIC4

0 = The rest of the ADC is not powered down during dynamic power-down phase

1 = The rest of the ADC is powered down during dynamic power-down phase

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Bit 2

Bit 1

Bit 0

PDN_TX: Tx power-down

0 = The Tx is powered up (default after reset)

1 = Only the Tx module is powered down

PDN_RX: Rx power-down

0 = The Rx is powered up (default after reset)

1 = Only the Rx module is powered down

PDN_AFE: AFE power-down

0 = The AFE is powered up (default after reset)

1 = The entire AFE is powered down (including the Tx, Rx, and diagnostics blocks)

Figure 110. SPARE2: SPARE2 Register For Future Use (Address = 24h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

0

14

0

13

0

12

0

11

0

10

0

9

8

7

6

5

4

3

2

1

0

This register is a spare register and is reserved for future use.

Bits 23:0 Must be 0

Figure 111. SPARE3: SPARE3 Register For Future Use (Address = 25h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

0

14

0

13

0

12

0

11

0

10

0

9

8

7

6

5

4

3

2

1

0

This register is a spare register and is reserved for future use.

Bits 23:0 Must be 0

Figure 112. SPARE4: SPARE4 Register For Future Use (Address = 26h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

0

14

0

13

0

12

0

11

0

10

0

9

8

7

6

5

4

3

2

1

0

This register is a spare register and is reserved for future use.

Bits 23:0

Must be 0

Figure 113. RESERVED1: RESERVED1 Register For Factory Use Only

(Address = 27h, Reset Value = XXXXh)

23

X⁽¹⁾

11

X

22

X

21

X

20

X

19

X

18

X

17

X

16

X

15

X

14

X

13

X

12

X

10

X

9

8

7

6

5

4

3

2

1

0

X

(1) X = don't care.

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This register is reserved for factory use. Readback values vary between devices.

Figure 114. RESERVED2: RESERVED2 Register For Factory Use Only

(Address = 28h, Reset Value = XXXXh)

23

X⁽¹⁾

11

X

22

X

21

X

20

X

19

X

18

X

17

X

16

X

15

X

14

X

13

X

12

X

10

X

9

8

7

6

5

4

3

2

1

0

X

(1) X = don't care.

This register is reserved for factory use. Readback values vary between devices.

Figure 115. ALARM: Alarm Register (Address = 29h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

0

14

0

13

0

12

0

11

0

10

0

9

8

7

6

5

4

3

2

1

0

This register controls the alarm pin functionality.

Bits 23:0 Must be 0

Figure 116. LED2VAL: LED2 Digital Sample Value Register (Address = 2Ah, Reset Value = 0000h)

23

22

21

20

19

18

17

16

15

14

13

12

LED2VAL[23:0]

11

10

9

8

7

6

5

4

3

2

1

0

LED2VAL[23:0]

Bits 23:0

LED2VAL[23:0]: LED2 digital value

This register contains the digital value of the latest LED2 sample converted by the ADC. The

ADC_RDY signal goes high each time that the contents of this register are updated. The

host processor must readout this register before the next sample is converted by the AFE.

Figure 117. ALED2VAL: Ambient LED2 Digital Sample Value Register

(Address = 2Bh, Reset Value = 0000h)

23

11

22

10

21

20

19

18

17

16

15

14

13

1

12

0

ALED2VAL[23:0]

9

8

7

6

5

4

3

2

ALED2VAL[23:0]

Bits 23:0

ALED2VAL[23:0]: LED2 ambient digital value

This register contains the digital value of the latest LED2 ambient sample converted by the

ADC. The ADC_RDY signal goes high each time that the contents of this register are

updated. The host processor must readout this register before the next sample is converted

by the AFE.

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Figure 118. LED1VAL: LED1 Digital Sample Value Register (Address = 2Ch, Reset Value = 0000h)

23

22

21

20

19

18

17

16

15

14

13

12

LED1VAL[23:0]

11

10

9

8

7

6

5

4

3

2

1

0

LED1VAL[23:0]

Bits 23:0

LED1VAL[23:0]: LED1 digital value

This register contains the digital value of the latest LED1 sample converted by the ADC. The

ADC_RDY signal goes high each time that the contents of this register are updated. The

host processor must readout this register before the next sample is converted by the AFE.

Figure 119. ALED1VAL: Ambient LED1 Digital Sample Value Register

(Address = 2Dh, Reset Value = 0000h)

23

11

22

10

21

20

19

18

17

16

15

14

13

1

12

0

ALED1VAL[23:0]

9

8

7

6

5

4

3

2

ALED1VAL[23:0]

Bits 23:0

ALED1VAL[23:0]: LED1 ambient digital value

This register contains the digital value of the latest LED1 ambient sample converted by the

ADC. The ADC_RDY signal goes high each time that the contents of this register are

updated. The host processor must readout this register before the next sample is converted

by the AFE.

Figure 120. LED2-ALED2VAL: LED2-Ambient LED2 Digital Sample Value Register

(Address = 2Eh, Reset Value = 0000h)

23

11

22

21

20

19

18

17

16

15

14

13

12

0

LED2-ALED2VAL[23:0]

10

9

8

7

6

5

4

3

2

1

LED2-ALED2VAL[23:0]

Bits 23:0

LED2-ALED2VAL[23:0]: (LED2 – LED2 ambient) digital value

This register contains the digital value of the LED2 sample after the LED2 ambient is

subtracted. The host processor must readout this register before the next sample is

converted by the AFE.

Note that this value is inverted when compared to waveforms shown in many publications.

Figure 121. LED1-ALED1VAL: LED1-Ambient LED1 Digital Sample Value Register

(Address = 2Fh, Reset Value = 0000h)

23

11

22

21

20

19

18

17

16

15

14

13

12

0

LED1-ALED1VAL[23:0]

10

9

8

7

6

5

4

3

2

1

LED1-ALED1VAL[23:0]

Bits 23:0

LED1-ALED1VAL[23:0]: (LED1 – LED1 ambient) digital value

This register contains the digital value of the LED1 sample after the LED1 ambient is

subtracted from it. The host processor must readout this register before the next sample is

converted by the AFE.

Note that this value is inverted when compared to waveforms shown in many publications.

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Figure 122. DIAG: Diagnostics Flag Register (Address = 30h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

0

14

0

13

0

12

PD_ALM

0

11

10

9

8

7

6

5

4

3

2

1

LED_

ALM

LED2

OPEN

LED1

OPEN

OUTNSH OUTPSH

GND GND

INNSC

GND

INPSC

GND

INNSC

LED

INPSC

LED

LEDSC

PDOC

PDSC

This register is read only. This register contains the status of all diagnostic flags at the end of the diagnostics

sequence. The end of the diagnostics sequence is indicated by the signal going high on DIAG_END pin.

Bits 23:13

Bit 12

Read only

PD_ALM: Power-down alarm status diagnostic flag

This bit indicates the status of PD_ALM .

0 = No fault (default after reset)

1 = Fault present

Bit 11

Bit 10

Bit 9

LED_ALM: LED alarm status diagnostic flag

This bit indicates the status of LED_ALM .

0 = No fault (default after reset)

1 = Fault present

LED2OPEN: LED2 open diagnostic flag

This bit indicates that LED2 is open.

0 = No fault (default after reset)

1 = Fault present

LED1OPEN: LED1 open diagnostic flag

This bit indicates that LED1 is open.

0 = No fault (default after reset)

1 = Fault present

This bit indicates that LED2 is open.

0 = No fault (default after reset)

1 = Fault present

Bit 8

Bit 7

Bit 6

Bit 5

LEDSC: LED short diagnostic flag

This bit indicates an LED short.

0 = No fault (default after reset)

1 = Fault present

OUTNSHGND: OUTN to GND diagnostic flag

This bit indicates that OUTN is shorted to the GND cable.

0 = No fault (default after reset)

1 = Fault present

OUTPSHGND: OUTP to GND diagnostic flag

This bit indicates that OUTP is shorted to the GND cable.

0 = No fault (default after reset)

1 = Fault present

PDOC: PD open diagnostic flag

This bit indicates that PD is open.

0 = No fault (default after reset)

1 = Fault present

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Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PDSC: PD short diagnostic flag

This bit indicates a PD short.

0 = No fault (default after reset)

1 = Fault present

INNSCGND: INN to GND diagnostic flag

This bit indicates a short from the INN pin to the GND cable.

0 = No fault (default after reset)

1 = Fault present

INPSCGND: INP to GND diagnostic flag

This bit indicates a short from the INP pin to the GND cable.

0 = No fault (default after reset)

1 = Fault present

INNSCLED: INN to LED diagnostic flag

This bit indicates a short from the INN pin to the LED cable.

0 = No fault (default after reset)

1 = Fault present

INPSCLED: INP to LED diagnostic flag

This bit indicates a short from the INP pin to the LED cable.

0 = No fault (default after reset)

1 = Fault present

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Figure 123. CONTROL3: Control Register (Address = 31h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

0

13

12

0

TX3_MO

DE

0

11

0

10

0

9

8

7

6

5

4

3

2

1

0

SOMI_

TRI

CLKOUT

_TRI

0

CLKDIV[2:0]

This register controls the clock divider ratio.

Bits 23:16

Bit 15

Must be 0

TX3_MODE: Selection of third LED

This bit transitions the control from the default two LEDs (on TXP, TXN) to the third LED on

TX3.

0 = LEDs on TXP, TXN are active

1 = LED on TX3 is active. Timing engine controls on TXP are transferred to TX3. Maximum

current setting supported for the third LED is 50 mA.

Bits 14:5

Bit 4

Must be 0

SOMI_TRI: Serial data output 3-state mode

This bit determines the state of the SPISOMI output pin. In order to avoid loading the SPI

bus when multiple devices are connected, this bit must be set to 1 (3-state mode) whenever

the device SPI is inactive.

0 = SPISOMI output buffer is active (normal operation, default)

1 = SPISOMI output buffer is in 3-state mode

Bit 3

CLKOUT_TRI: CLKOUT output 3-state mode

This bit determines the state of the CLKOUT output pin.

0 = CLKOUT buffer is active (normal operation, default)

1 = CLKOUT buffer is in 3-state mode

Bits 2:0

CLKDIV[2:0]: Clock divider ratio

These bits set the ratio of the clock divider and determine the frequency of CLKOUT relative

to the input clock frequency.

Table 8 shows the clock divider ratio settings.

Table 8. Clock Divider Ratio Settings

CLKDIV[2:0]

000

DIVIDER RATIO

Divide-by-2

Do not use

INPUT CLOCK FREQUENCY RANGE

8 MHz to 12 MHz⁽¹⁾

Do not use

001

010

Divide-by-4

Divide-by-6

Divide-by-8

Divide-by-12

Do not use

16 MHz to 24 MHz⁽¹⁾

24 MHz to 36 MHz

32 MHz to 48 MHz

48 MHz to 60 MHz

Do not use

011

100

101

110

111

Divide by 1⁽²⁾

4 MHz to 6 MHz

(1) These frequency ranges can be used when generating the clock using the crystal.

(2) When using divide-by-1, the external clock should have a duty cycle between 48% to 52%.

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Figure 124. PDNCYCLESTC: PDNCYCLESTC Register (Address = 32h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

0

PDNCYCLESTC[15:0]

11

10

9

8

7

6

5

4

3

2

1

PDNCYCLESTC[15:0]

Bits 23:16

Bits 15:0

Must be 0

PDNCYCLESTC[15:0]: Dynamic (cycle-to-cycle) power-down start count

The contents of this register can be used to position the start of the PDN_CYCLE signal with

respect to the pulse repetition period (PRP). The count is specified as the number of cycles

of CLKOUT. If the dynamic power-down feature is not required, then do not program this

register.

Figure 125. PDNCYCLEENDC: PDNCYCLEENDC Register (Address = 33h, Reset Value = 0000h)

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

14

13

12

PDNCYCLEENDC[15:0]

11

10

9

8

7

6

5

4

3

2

1

0

PDNCYCLEENDC[15:0]

Bits 23:16

Bits 15:0

Must be 0

PDNCYCLEENDC[15:0]: Dynamic (cycle-to-cycle) power-down end count

The contents of this register can be used to position the end of the PDN_CYCLE signal with

respect to the pulse repetition period (PRP). The count is specified as the number of cycles

of CLKOUT. If the dynamic power-down feature is not required, then do not program this

register.

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9 Application and Implementation

9.1 Application Information

The AFE4403 is ideally suited as an analog front-end for processing PPG (photoplethysmography) signals. The

information contained in PPG signals can be used for measuring SPO2 as well as for monitoring heart rate. The

high dynamic range of the device enables measuring SPO2 with a high degree of accuracy, even under

conditions of low perfusion (ac:dc ratio). An SPO2 measurement system involves two different wavelength LEDs:

usually Red and IR. By computing the ratio of the ac:dc at the two different wavelengths, SPO2 can be

calculated. Heart rate monitoring systems can also benefit from the high dynamic range of the AFE4403, which

enables a high-fidelity pulsating signal to be captured, even in cases where the signal strength is low.

9.2 Typical Application

Device connections in a typical application is shown in Figure 126. The schematic shows a cabled application in

which the LEDs and photodiode are connected to the device through a cable. However, in an application without

cables, the LEDs and photodiode can be directly connected to the TXP, TXN, TX3, INP, and INN pins directly.

Figure 126. Schematic

9.2.1 Design Requirements

An SPO2 application usually involves a Red LED and IR LED. In addition, a heart rate monitoring application can

use a different wavelength LED, such as a Green LED. The LEDs can be connected either in the common anode

configuration or H-bridge configuration to the TXP, TXN pins. The LED connected to the TX3 pin can only be

connected in the common anode configuration.

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Typical Application (continued)

9.2.2 Detailed Design Procedure

Refer to LED Configurations for different ways to connect the LEDs to the TXP, TXN, and TX3 pins. The

photodiode (shown in Figure 127) receives light from both the Red and IR phases and usually has good

sensitivities at both these wavelengths.

Figure 127. Photodiode

The photodiode connected as shown in Figure 127 operates in zero bias because of the negative feedback from

the transimpedance amplifier. The signal current generated by the photodiode is converted into a voltage by the

transimpedance amplifier, which has a programmable transimpedance gain. The rest of the signal chain then

presents a voltage to the ADC. The full-scale output of the transimpedance amplifier is ±1 V and the full-scale

input to the ADC is ±1.2 V. An automatic gain control (AGC) loop can be used to set the target dc voltage at the

ADC input to approximately 50% of its full-scale. Such an AGC loop can control a combination of the LED current

and TIA gain to achieve this target value.

9.2.3 Application Curves

This section outlines the trends seen in the Typical Characteristics curves from an application perspective.

Figure 5 illustrates the receiver currents in external clock mode with CLKOUT tri-stated. The curve in Figure 5

are taken without the dynamic power-down feature enabled, so much lower currents can be achieved using the

dynamic power-down feature. Enabling the crystal mode or removing the CLKOUT tri-state increases the

receiver currents from the values depicted in the curve.

Figure 6 illustrates the transmitter currents with a zero LED current setting. The average LED current can be

computed based on the value of the PRF and LED pulse durations, and can be added to the LED_DRV_SUP

current described in Figure 6.

Figure 7 illustrates the total receiver current (analog plus digital supply) for different clock divider ratios. For each

clock divider ratio, the external clock frequency is swept in frequency such that the divided clock changes

between 3 MHz to 7 MHz. Note however that the supported range for the divided clock is 4 MHz to 6 MHz at

each division ratio. Also, the external clock should be limited to be between 4 MHz to 60 MHz.

Figure 8 illustrates the power savings arising out of the dynamic power-down mode. This mode can be set by

defining the start and end points for the signal PDN_CYCLE within the pulse repetition period. In Figure 8, the

LED pulse durations are chosen to be 100 µs and the conversions are also chosen to be 100 µs wide. Thus, the

entire active period fits in 500 µs. With the timing margins for t₁and t₂indicated in Figure 67, the PDN_CYCLE

pulse spans the rest of the pulse repetition period. As PRF reduces, the duty cycle of the PDN_CYCLE pulse (as

a fraction of the pulse repetition period) increases, which is the reason for the power reduction at lower PRFs as

seen in Figure 8.

Figure 9 illustrates the power savings as a function of the PDN_CYCLE duration at a fixed PRF of 100 Hz. A

100-Hz PRF corresponds to a period of 10 ms. Figure 9 indicates the PDN_CYCLE duration swept from 0 ms to

9 ms. With higher durations of PDN_CYCLE, the receiver power reduces.

Figure 10 illustrates the baseband response of the switched RC filter for a 5% and 25% duty cycle. When the

duty cycle reduces, the effective bandwidth of the filter reduces.

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Typical Application (continued)

Figure 128 shows the SNR of the signal chain as a function of the output voltage level. The data are taken by

looping back the transmitter outputs to the receiver inputs using an external op amp that converts the transmitter

voltage to a receiver input current. The loopback op amp and external resistors are an extra source of noise in

this measurement, so the actual noise levels are higher than the total noise of the transmitter plus the receiver.

The SNR in this curve (and other curves) is expressed in terms of dBFS, where the full-scale of the channel is

used as the reference level. Because the valid operating range of the signal chain is ±1 V, a full-scale of 2 V is

used for converting the output noise to a dBFS number. %FS refers to the percentage of the output level as a

function of the positive full-scale. For example, a 50 %FS curve corresponds to the case where the output level is

0.5 V. Also, the total noise in this curve is the total integrated noise in the digital output. All noise is contained in

the Nyquist band, which extends from –PRF / 2 to PRF / 2.

106

Output voltage = 0 %FS

Output voltage = 10 %FS

104

Output voltage = 25 %FS

Output voltage = 50 %FS

102

100

98

Output voltage = 75 %FS

96

0

5

10

15

20

25

Duty Cycle (%)

C007

Figure 128. SNR over Nyquist Bandwidth vs Duty Cycle (Input Current with Tx-Rx Loopback)

Figure 129 is a representation of the same data as Figure 10. However, the noise is represented in terms of the

input-referred noise current in pArms. By multiplying this number with the TIA gain setting (500 k in this case),

the output noise voltage can be computed.

50

Output voltage = 0 %FS

45

Output voltage = 10 %FS

Output voltage = 25 %FS

Output voltage = 50 %FS

Output voltage = 75 %FS

40

35

30

25

20

15

10

0

5

10

15

20

25

Duty Cycle (%)

C006

Figure 129. Input-Referred Noise Current over Nyquist Bandwidth vs Duty Cycle

(Input Current with Tx-Rx Loopback)

Figure 13 illustrates the SNR from the receiver as a function of the sampling duty cycle (which is the sampling

pulse duration referred to the pulse repetition period) for different settings of TIA gain. This curve is taken at 100-

Hz PRF. The maximum duty cycle is limited to 25%. A lower sampling duty cycle also means a lower LED pulse

duration duty cycle, which results in power saving.

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Typical Application (continued)

Figure 14 illustrates the input-referred noise corresponding to Figure 13. Figure 15 and Figure 16 illustrate the

SNR and input-referred noise current in a 0.1-Hz to 20-Hz band for the LED-ambient data. By performing a

digital ambient subtraction, the low-frequency noise in the signal chain can be significantly attenuated. The noise

levels in the bandwidth of interest are lower than the noise over the full Nyquist bandwidth. For a PPG signal, the

signal band of interest is usually less than 10 Hz. By performing some digital low-pass filtering in the processor,

this noise reduction can be achieved. Figure 17 and Figure 18 illustrate the noise reduction from ADC averaging.

TI therefore recommends setting the number of ADC averages to the maximum allowed at a given PRF.

Figure 19 and Figure 20 illustrate the noise at different PRFs over a 20-Hz bandwidth. At a higher PRF, the 20-

Hz noise band is a smaller fraction of the Nyquist band. Thus, noise is lower at higher PRFs in these figures.

Figure 21 and Figure 22 illustrate the noise at different PRFs over a 20-Hz bandwidth with dynamic power-down

mode enabled. The active window remains as 500 µs and all samples and conversions are performed at this

time. For the rest of the period, the device is in dynamic power-down with the t₁and t₂values as described in

Figure 67. Again, the noise reduces with higher PRF. Figure 23 and Figure 24 illustrate the noise as a function of

the PDN_CYCLE duration varied from 0 ms to 9 ms, with the active duration (available for conversion) occupying

the rest of the period. With higher PDN_CYCLE durations, the number of allowed ADC averages reduces, ehich

explains the slight increase in noise at higher PDN_CYCLE durations. Figure 25 and Figure 26 illustrate the

noise as a function of temperature over a 20-Hz bandwidth. The measurements are performed with a transmit-

receive loopback as explained earlier. The input current is maintained at 1 µA. Thus, for 250-k gain setting, the

output voltage is 0.5 V and for a 500-k gain setting, the output voltage is 1 V. Figure 27 and Figure 28 illustrate

the noise reduction using additional gain in stage 2. Figure 29 shows the noise as a function of the internal

(divided) clock frequency. The external clock is varied from 7 MHz to 14 MHz with a clock division ratio of 2. This

range of external clock results in the internal clock varying from 3.5 MHz to 7 MHz. Out of this range, 4 MHz to 6

MHz is the allowed range for the internal (divided) clock at all clock division ratios. Figure 30 illustrates the

deviation in the measured LED current with respect to the calculated current when the LED current code is swept

from 0 to 255 in steps of 1.

Figure 31 and Figure 32 illustrate the transmitter+receiver noise (in external loopback mode) as a function of the

TX_REF voltage setting. At lower TX_REF voltages, there is a slight increase in the transmitter noise. This

increase is not very apparent from the curves because the transmitter noise is at a level much lower than the

total noise. Figure 33 illustrates the transmitter current as a function of the current setting code. Figure 34

illustrates the spread of the transmitter current taken across a large number of devices for the same current

setting. Figure 35 illustrates how the LED current changes linearly with the TX_REF voltage for a fixed code.

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10 Power Supply Recommendations

The AFE4403 has two sets of supplies: the receiver supplies (RX_ANA_SUP, RX_DIG_SUP) and the transmitter

supplies (TX_CTRL_SUP, LED_DRV_SUP). The receiver supplies can be between 2.0 V to 3.6 V, whereas the

transmitter supplies can be between 3.0 V to 5.25 V. Another consideration that determines the minimum allowed

value of the transmitter supplies is the forward voltage of the LEDs being driven. The current source and

switches inside the AFE require voltage headroom that mandates the transmitter supply to be a few hundred

millivolts higher than the LED forward voltage. TX_REF is the voltage that governs the generation of the LED

current from the internal reference voltage. Choosing the lowest allowed TX_REF setting reduces the additional

headroom required but results in higher transmitter noise. Other than for the highest-end clinical SPO2

applications, this extra noise resulting from a lower TX_REF setting can be acceptable.

Consider a design where the LEDs are meant to be used in common anode configuration with a current setting

of 50 mA. Assume that the LED manufacturer mentions the highest forward voltage of the LEDs is 2.5 V at this

current setting. Further, assume that the TX_REF voltage is set to 0.5 V. The voltage headroom required in this

case is 1 V. Thus, the LED_DRV_SUP must be driven with a voltage level greater than or equal to 3.5 V (2.5 V

plus 1 V).

LED_DRV_SUP and TX_CTRL_SUP are recommended to be tied together to the same supply (between 3.0 V to

5.25 V). The external supply (connected to the common anode of the two LEDs) must be high enough to account

for the forward drop of the LEDs as well as the voltage headroom required by the current source and switches

inside the AFE. In most cases, this voltage is expected to fall below 5.25 V; thus the external supply can be the

same as LED_DRV_SUP. However, there may be cases (for instance when two LEDs are connected in series)

where the voltage required on the external supply is higher than 5.25 V. Such a case must be handled with care

to ensure that the voltage on the TXP and TXN pins remains less than 5.25 V and never exceeds the supply

voltage of LED_DRV_SUP, TX_CTRL_SUP by more than 0.3 V.

Many scenarios of power management are possible.

Case 1: The LED forward voltage is such that a voltage of 3.3 V is acceptable on LED_DRV_SUP. In this case,

a single 3.3-V supply can be used to drive all four pins (RX_ANA_SUP, RX_DIG_SUP, TX_CTRL_SUP,

LED_DRV_SUP). Care should be taken to provide some isolation between the transmit and receive supplies

because LED_DRV_SUP carries the high-switching current from the LEDs.

Case 2: A low-voltage supply of 2.2 V is available in the system. In this case, a boost converter can be used to

derive the voltage for LED_DRV_SUP, as shown in Figure 130.

2.2-V supply

(Connect to RX_ANA, RX_DIG)

3.6 V

(Connect to LED_DRV_SUP, TX_CTRL_SUP)

Boost

Converter

Figure 130. Boost Converter

The boost converter requires a clock (usually in the megahertz range) and there is usually a ripple at the boost

converter output at this switching frequency. While this frequency is much higher than the signal frequency of

interest (which is at maximum a few tens of hertz around dc), a small fraction of this switching noise can possibly

alias to the low-frequency band. Therefore, TI strongly recommends that the switching frequency of the boost

converter be offset from every multiple of the PRF by at least 20 Hz. This offset can be ensured by choosing the

appropriate PRF.

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Case 3: In cases where a high-voltage supply is available in the system, a buck converter or an LDO can be

used to derive the voltage levels required to drive RX_ANA and RX_DIG, as shown in Figure 131.

3.9V

(Connect to LED_DRV_SUP, TX_CTRL_SUP)

2.2V supply

(Connect to RX_ANA/RX_DIG)

LDO

Figure 131. Buck Converter or an LDO

10.1 Power Consumption Considerations

The lowest power consumption mode of the AFE4403 corresponds to the following settings:

•

PRF = 62.5 Hz,

External clock mode (XTALDIS = 1), and

CLKOUT tri-stated (CLKOUT_TRI = 1).

With the above settings, the currents taken from the supplies are as shown in Table 9. The LED driver current is

with zero LED current setting.

Table 9. Current Consumption in Normal Mode

SUPPLY

RX_ANA

VOLTAGE (V)

CURRENT (µA)

2

3

490

155

15

RX_DIG

TX_CTRL_SUP

LED_DRV_SUP

55

Enabling the crystal (XTALDIS = 0) leads to an additional power consumption that can be estimated to be

approximately equal to (2 × C_sh+ 0.5 × C1 + 0.5 × C2) × 0.4 × f_XTAL, where C_shis the effective shunt capacitance

of the crystal, C1 and C2 are the capacitances from the XIN and XOUT pins to ground, and f_XTALis the frequency

of the crystal.

Removing the CLKOUT tri-state leads to an additional power consumption of approximately C_LOAD× V_SUP× f,

where V_SUPis the supply voltage of RX_DIG in volts, f = 4 MHz, C_LOAD= the capacitive load on the CLKOUT pin

+ 2 pF.

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The power consumption can be reduced significantly by using the dynamic power-down mode. An illustration of

this mode is shown in Table 10, where:

•

PRF = 62.5 Hz,

Dynamic power-down is active for 14.7 ms every pulse repetition period,

All four bits (DYNAMIC[4:1]) are set to 1,

External clock mode (XTALDIS = 1), and

CLKOUT is tri-stated (CLKOUT_TRI = 1).

Table 10. Current Consumption in Dynamic Power-Down Mode

SUPPLY

RX_ANA

VOLTAGE (V)

CURRENT (µA)

2

3

150

155

5

RX_DIG

TX_CTRL_SUP

LED_DRV_SUP

5

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11 Layout

11.1 Layout Guidelines

Some key layout guidelines are mentioned below:

1. TXP, TXN, and TX3 are fast-switching lines and should be routed away from sensitive reference lines as well

as from the INP, INN inputs.

2. If the INP, INN lines are required to be routed over a long trace, TI recommends that VCM be used as a

shield for the INP, INN lines.

3. The device can draw high-switching currents from the LED_DRV_SUP pin. Therefore, TI recommends

having a decoupling capacitor electrically close to the pin.

11.2 Layout Example

Figure 132. Example Layout

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12 Device and Documentation Support

12.1 Trademarks

SPI is a trademark of Motorola.

All other trademarks are the property of their respective owners.

12.2 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.3 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

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17-Jun-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

AFE4403YZPR

AFE4403YZPT

DSBGA

YZP

36

3000

250

180.0

8.4

3.16

0.71

4.0

8.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Jun-2015

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

AFE4403YZPR

AFE4403YZPT

DSBGA

YZP

36

3000

250

182.0

20.0

Pack Materials-Page 2

D: Max = 3.07 mm, Min = 3.01 mm

E: Max = 3.07 mm, Min = 3.01 mm

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型号：	AFE4403YZPR
厂家：	TEXAS INSTRUMENTS
描述：	AFE4403 Ultra-Small, Integrated Analog Front-End for Heart Rate Monitors and Low-Cost Pulse Oximeters
文件：	总97页 (文件大小：1840K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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