AFE539A4 [TI]
具有 PID/TEC 控制功能的四通道 10 位智能模拟前端 (AFE)，具有内置 ADC 和 DAC;
| 型号： | AFE539A4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 PID/TEC 控制功能的四通道 10 位智能模拟前端 (AFE)，具有内置 ADC 和 DAC |
| 文件： | 总65页 (文件大小：2898K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AFE539A4
ZHCSNR0 –AUGUST 2021
AFE539A4 智能模拟前端(AFE)，具有四通道10 位DAC 和适用于配备I2C 和SPI
接口的比例积分(PI) 控制器的ADC
1 特性
2 应用
• 集成式比例积分(PI) 控制
• 激光
• 化学和气体分析仪
• 机器人感应模块
• 移动机器人感应模块
• 导引头前端
– 10 位ADC 输入和DAC 输出
– 从非易失性存储器(NVM) 中独立运行
– 可编程的比例和积分增益
– 适合输出钳位的比较器输入
– 适合输出的可编程最小值、最大值和共模值
– 可编程的环路-相位反转
• 聚合酶链反应(PCR) 测试
3 说明
• 电压输出（10 位）
AFE539A4 是一款 10 位四通道智能模拟前端 (AFE)。
每个模拟通道可配置为数模转换器 (DAC)、模数转换
器 (ADC) 或比较器。DAC 输出可以是电压和电流输
出。AFE539A4 支持高阻态断电模式，并在断电情况
下支持高阻态输出。DAC 输出提供一个强制检测选
项，可用作可编程比较器和电流阱。该器件具有一个集
成的状态机， 预编程为比例积分 (PI) 控制器。
AFE539A4 非常适用于热电制冷 (TEC) 控制、温度控
制和动态余量控制应用。AFE539A4 是智能 AFE 器
件，因为它具有高级集成功能。多功能 GPIO、函数生
成和 NVM 使这款智能 AFE 适用于无处理器的 应用和
设计重复使用。
– 1 LSB INL 和DNL
– 1x、1.5x、2x、3x 和4x 增益
• 电流输出（8 位）
– 1 LSB INL 和DNL
– ±25 μA、±50 μA、±125 μA、±250 μA 输出
范围选项
• 适合所有通道的可编程比较器模式
• 所有通道均可配置为ADC 或DAC
• 当VDD 关闭时提供高阻抗输出
• 自动检测I2C 或SPI 接口
– 1.62V VIH (VDD = 5.5V)
• 通用输入输出(GPIO)
器件信息
封装(1)
• MODE 引脚可在编程和独立模式之间进行选择
• 用户可编程NVM
器件型号
封装尺寸（标称值）
AFE539A4
WQFN (16)
3.00mm x 3.00mm
• 基准：内部、外部或VDD
• 宽工作范围
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 电源：1.8V 至5.5V
– 温度范围：-40˚C 至+125˚C
• 微型封装：16 引脚WQFN (3mm × 3mm)
使用AFE539A4 的热电制冷(TEC) 控制
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBASAC1
AFE539A4
ZHCSNR0 –AUGUST 2021
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Table of Contents
7 Detailed Description......................................................14
7.1 Overview...................................................................14
7.2 Functional Block Diagram.........................................14
7.3 Feature Description...................................................15
7.4 Device Functional Modes..........................................17
7.5 Programming............................................................ 29
7.6 Register Maps...........................................................36
8 Application and Implementation..................................54
8.1 Application Information............................................. 54
8.2 Typical Application.................................................... 55
9 Power Supply Recommendations................................57
10 Layout...........................................................................57
10.1 Layout Guidelines................................................... 57
10.2 Layout Example...................................................... 57
11 Device and Documentation Support..........................58
11.1 Documentation Support.......................................... 58
11.2 接收文档更新通知................................................... 58
11.3 支持资源..................................................................58
11.4 Trademarks............................................................. 58
11.5 Electrostatic Discharge Caution..............................58
11.6 术语表..................................................................... 58
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics: Voltage Output ..................6
6.6 Electrical Characteristics: Current Output ..................8
6.7 Electrical Characteristics: Comparator Mode .............9
6.8 Electrical Characteristics: ADC Input .........................9
6.9 Electrical Characteristics: General ...........................10
6.10 Timing Requirements: I2C Standard Mode ............ 11
6.11 Timing Requirements: I2C Fast Mode .................... 11
6.12 Timing Requirements: I2C Fast Mode Plus ............ 11
6.13 Timing Requirements: SPI Write Operation ...........12
6.14 Timing Requirements: SPI Read and Daisy
Chain Operation ......................................................... 12
6.15 Timing Requirements: GPIO ..................................12
6.16 Timing Diagrams.....................................................13
Information.................................................................... 58
4 Revision History
DATE
REVISION
NOTES
August 2021
*
Initial release
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5 Pin Configuration and Functions
FB3
OUT3/AIN3
OUT2
1
2
3
4
12
11
10
9
FB0/AIN0
OUT0
Thermal Pad
OUT1
FB2/AIN2
FB1/AIN1
Not to scale
图5-1. RTE Package, 16-pin WQFN, Top View
表5-1. Pin Functions
DESCRIPTION
PIN
TYPE
NO.
NAME
Voltage feedback input for DAC channel 3.
In PI control or ADC mode, connect this pin to VDD with a pullup resistor. Do not connect to OUT3.
In voltage-output mode, connect to OUT3 for closed-loop amplifier output.
1
FB3
Input
In current-output mode, leave this pin unconnected to minimize leakage current.
2
3
OUT3/AIN3 Input/Output Analog output for DAC channel 3 or analog input for ADC channel 3.
OUT2
Output
Analog output for DAC channel 2.
Voltage feedback input for DAC channel 2.
In PI control or ADC mode, this pin is analog input for ADC2. Do not connect to OUT2.
In voltage-output mode, connect to OUT2 for closed-loop amplifier output.
In current-output mode, leave this pin unconnected to minimize leakage current.
4
FB2/AIN2 Input/Output
General-purpose input/output. This pin is configurable as LDAC, PD, RESET, STATUS, SDO, or
5
6
GPIO/SDO Input/Output PROTECT. When using the STATUS or SDO functions, connect this pin to the IO voltage with an
external pullup resistor.
I2C serial interface clock or SPI chip select input. Connect this pin to the IO voltage using an
SCL/SYNC
Output
external pullup resistor.
Address configuration input for I2C or serial data input for SPI.
7
8
A0/SDI
Input
In A0 function, connect this pin to VDD, AGND, SDA, or SCL for address configuration.
In SDI function, this pin does not need to be pulled up or pulled down.
Bidirectional I2C serial data bus or SPI clock input. Connect this pin to the IO voltage using an
external pullup resistor.
SDA/SCLK Input/Output
FB1/AIN1 Input/Output
Voltage feedback input for DAC channel 1.
In PI control or ADC mode, this pin is analog input for ADC1. Do not connect to OUT1.
In voltage-output mode, connect to OUT1 for closed-loop amplifier output.
In current-output mode, leave this pin unconnected to minimize leakage current.
9
10
11
OUT1
OUT0
Output
Output
Analog output for DAC channel 1.
Analog output for DAC channel 0.
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表5-1. Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NO.
NAME
Voltage feedback input for DAC channel 0.
In PI control or ADC mode, this pin is analog input for ADC0. Do not connect to OUT0.
In voltage-output mode, connect to OUT0 for closed-loop amplifier output.
In current-output mode, leave this pin unconnected to minimize leakage current.
12
FB0/AIN0 Input/Output
External bypass capacitor for the internal LDO. Connect a capacitor (approximately 1.5 μF)
between CAP and AGND.
13
CAP
Power
14
15
AGND
VDD
Ground
Power
Ground reference point for all circuitry on the device.
Supply voltage: 1.8 V to 5.5 V
External reference or interface mode select input. Connect a capacitor (approximately 0.1 μF)
between VREF and AGND. Use a pullup resistor to VDD when the external reference is not used. In
case an external reference is used or when in interface select mode, make sure the reference
ramps up after VDD.
VREF/
MODE
16
Input
In interface select mode:
Pull this pin low to enable I2C/SPI communication.
Pull this pin high to enable standalone mode.
Thermal
Pad
Thermal
Pad
Ground
Connect the thermal pad to AGND.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–10
–40
–65
MAX
6
UNIT
V
VDD
Supply voltage, VDD to AGND
Digital inputs to AGND
CAP to AGND
VDD + 0.3
1.65
V
V
VFBX to AGND
VDD + 0.3
VDD + 0.3
10
V
VOUTX to AGND
V
Current into any pin except the OUTx pins
Junction temperature
Storage temperature
mA
°C
°C
TJ
150
Tstg
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Electrostatic
discharge
V(ESD)
Charged device model (CDM), per JEDEC specification JESD22-C101, pins TBD(2)
Charged device model (CDM), per JEDEC specification JESD22-C101, pins TBD(2)
V
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.71
1.62
NOM
MAX UNIT
VDD
VIH
VIL
TA
Positive supply voltage to ground (AGND
)
5.5
V
V
V
Digital input high voltage, 1.7 V < VDD ≤5.5 V
Digital input low voltage
0.4
Ambient temperature
125 °C
–40
6.4 Thermal Information
AFE539A4
THERMAL METRIC(1)
RTE (WQFN)
UNIT
16 PINS
49
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
50
24.1
1.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJT
24.1
8.7
ΨJB
RθJC(bot)
(1) For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
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6.5 Electrical Characteristics: Voltage Output
all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.8 V ≤VDD ≤5.5 V,
DAC reference tied to VDD, gain = 1x, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩto AGND) and capacitive
load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER
STATIC PERFORMANCE
Resolution
TEST CONDITIONS
MIN
TYP
MAX
UNIT
10
–1
–1
Bits
LSB
LSB
INL Integral nonlinearity(1)
DNL Differential nonlinearity(1)
1
1
Code 0d into DAC, external reference, VDD = 5.5 V
6
6
12
Zero-code error(4)
mV
Code 0d into DAC, internal VREF, gain = 4x,
VDD = 5.5 V
15
Zero-code error temperature
coefficient(4)
±10
µV/°C
%FSR
0.3
0.75
0.5
1.8 V ≤VDD ≺ 2.7 V, VFB pin shorted to VOUT
2.7 V ≤VDD ≤5.5 V, VFB pin shorted to VOUT
–0.75
–0.5
Offset error(4)
0.25
Offset-error temperature
coefficient(4)
±0.0003
0.25
%FSR/°C
%FSR
Gain error(4)
0.5
–0.5
Gain-error temperature
coefficient(4)
±0.0008
%FSR/°C
1
1.8 V ≤VDD < 2.7 V, program full code into DAC
2.7 V ≤VDD ≤5.5 V, program full code into DAC
–1
Full-scale error(4)
%FSR
0.5
–0.5
Full-scale-error temperature
coefficient(4)
±0.0008
%FSR/°C
OUTPUT
Output voltage
Reference tied to VDD
0
VDD
200
V
RL = infinite, phase margin = 30°
RL = 5 kΩ, phase margin = 30°
CL
Capacitive load(2)
pF
1000
VDD = 1.8 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD
15
50
60
VDD = 2.7 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD
Short-circuit current
mA
VDD = 5.5 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD
To VDD (DAC output unloaded, internal reference =
1.21 V), VDD ≥1.21 V ☓ gain + 0.2 V
0.2
0.8
V
To VDD
Output-voltage headroom(2)
VFB dc output impedance(3)
(DAC output unloaded, reference tied to VDD
)
%FSR
To VDD (ILOAD = 10 mA at VDD = 5.5 V, ILOAD = 3 mA at
VDD = 2.7 V, ILOAD = 1 mA at VDD = 1.8 V), DAC code
= full scale
10
DAC output enabled, DAC reference tied to VDD (gain
= 1x) or internal reference (gain = 1.5x or 2x)
400
325
500
400
600
485
ZO
kΩ
DAC output enabled, internal VREF, gain = 3x or 4x
Power supply rejection ratio
(dc)
Internal VREF, gain = 2x, DAC at midscale;
VDD = 5 V ±10%
0.25
mV/V
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6.5 Electrical Characteristics: Voltage Output (continued)
all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.8 V ≤VDD ≤5.5 V,
DAC reference tied to VDD, gain = 1x, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩto AGND) and capacitive
load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC PERFORMANCE
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to
10%FSR, VDD = 5.5 V
20
tsett Output voltage settling time
µs
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to
10%FSR, VDD = 5.5 V, internal VREF, gain = 4x
25
0.3
75
Slew rate
VDD = 5.5 V
V/µs
mV
At startup (DAC output disabled), RL = 5 kΩ,
CL = 200 pF
Power on glitch magnitude
200
250
50
At startup (DAC output disabled), RL = 100 kΩ
DAC output disabled to enabled (DAC registers at zero
scale, RL = 100 kΩ
Output enable glitch
magnitude
mV
0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V
Output noise voltage (peak to
peak)
Vn
µVPP
Internal VREF, gain = 4x, 0.1 Hz to 10 Hz, DAC at
midscale, VDD = 5.5 V
90
f = 1 kHz, DAC at midscale, VDD = 5.5 V
0.35
0.9
Output noise density
µV/√Hz
Internal VREF, gain = 4x, f = 1 kHz, DAC at midscale,
VDD = 5.5 V
Internal VREF, gain = 4x, 200-mV 50-Hz or 60-Hz sine
wave superimposed on power supply voltage, DAC at
midscale
Power supply rejection ratio
(ac)(3)
-68
dB
±1 LSB change around mid code (including
feedthrough)
Code change glitch impulse
10
15
nV-s
mV
Code change glitch impulse
magnitude
±1 LSB change around mid code (including
feedthrough)
POWER
IDD
Current flowing into VDD(4)
Normal operation, DACs at full scale, digital pins static
150
µA/ch
(1) Measured with DAC output unloaded. For external reference and internal reference VDD ≥1.21 x gain + 0.2 V, between end-point
codes: 2d to 254d for 8-bit resolution.
(2) Specified by design and characterization, not production tested.
(3) Specified with 200-mV headroom with respect to reference value when internal reference is used.
(4) Measured with DAC output unloaded.
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6.6 Electrical Characteristics: Current Output
all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.8 V ≤VDD ≤5.5 V,
±250µA output range, and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER
STATIC PERFORMANCE
Resolution
TEST CONDITIONS
MIN
TYP
MAX
UNIT
8
–1
–1
Bits
LSB
LSB
INL Integral nonlinearity(1)
DNL Differential nonlinearity(1)
1
1
DAC output ranges: ±25 µA, ±50 µA, ±125 µA, and
±250 µA, DAC at midscale
Offset error
Gain error(4)
±1
%FSR
%FSR
DAC output ranges: ±25 µA, ±50 µA, ±125 µA, and
±250 µA
±1.3
OUTPUT
Output compliance voltage(1)
DAC output range: 0 µA to 25 µA, To VDD
200
400
100
mV
mV
DAC output ranges: ±25 µA, ±50 µA, ±125 µA, and
±250 µA, To VDD and to AGND
Output compliance voltage(1)
ZO
IOUT dc output impedance(2)
DAC code = midscale, DAC output kept at VDD/2
MΩ
Power supply rejection ratio
(dc)
DAC at midscale, gain setting: 0 µA to 25 µA, VDD
changed from 4.5 V to 5.5 V
0.28
100
LSB/V
DYNAMIC PERFORMANCE
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 1 LSB
at 8-bit resolution, VDD = 5.5 V, common-mode voltage
at OUTx pin is VDD/2
tsett Output current settling time
µs
Output noise current (peak to 0.1 Hz to 10 Hz, DAC at midscale,
Vn
150
1
nAPP
peak)
VDD = 5.5 V, ±250-µA output range
f = 1 kHz, DAC at midscale,
VDD = 5.5 V, ±250-µA output range
Output noise density
nA/√Hz
±250 µA output range, 200-mV 50-Hz or 60-Hz sine
wave superimposed on power supply voltage, DAC at
midscale
Power supply rejection ratio
(ac)(3)
TBD
LSB/V
µF
POWER
Load capacitor - CAP pin(2)
0.5
15
50
Normal operation, DACs at full scale, ±25-µA output
range, digital pins static
42
56
Normal operation, DACs at full scale, ±50-µA output
range, digital pins static
70
120
200
IDD
Current flowing into VDD(3)
µA/ch
Normal operation, DACs at full scale, ±125-µA output
range, digital pins static
98
Normal operation, DACs at full scale, ±250-µA output
range, digital pins static
167
(1) Measured between end-point codes 0d to 255d.
(2) Specified by design and characterization, not production tested.
(3) The current flowing into VDD does not account for the load current sourced or sinked on the OUTx pins. The VREF pin is connected to
VDD.
(4) Measured between DAC codes 10d and 255d.
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6.7 Electrical Characteristics: Comparator Mode
all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.8 V ≤VDD ≤5.5 V,
DAC reference tied to VDD, gain = 1x in voltage output mode, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩto
AGND) and capacitive load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER
STATIC PERFORMANCE
Offset error(1)
TEST CONDITIONS
MIN
TYP
TBD
4
MAX
UNIT
5
mV
1.8 V ≤VDD ≤5.5 V
–5
VDD = 5.5 V, external reference, TA = 125°C, FB in Hi-
Z mode, DAC at full-scale and VFB at 0 V or DAC at
zero-scale and VFB at 1.84 V, drift specified for 10
years of continuous operation
Offset error time drift
mV
OUTPUT
VREF connected to VDD, VFB resistor network
connected to ground
0
0
VDD
Input voltage
V
V
VREF connected to VDD, VFB resistor network
disconnected from ground
VDD (1/3
- 1/100)
VOL Logic low output voltage
0.1
15
ILOAD = 100 μA
DYNAMIC PERFORMANCE
DAC at midscale, FB input at Hi-Z, and transition step
at FB node is (VDAC –2 LSB) to (VDAC + 2 LSB),
transition time measured between 10% and 90% of
output, output current of 100 µA, comparator output
configured in push-pull mode, load capacitor at DAC
output is 25 pF
tresp-
Output response time
µs
comp
(1) Measured at DAC at mid-scale, comparator input at Hi-Z, and DAC operating with external reference.
6.8 Electrical Characteristics: ADC Input
all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.8 V ≤VDD ≤5.5 V,
DAC reference tied to VDD, gain = 1x in voltage output mode or ±250µA output range in current output mode, DAC output
pin (OUT) loaded with resistive load (RL = 5 kΩto AGND) and capacitive load (CL = 200 pF to AGND), and digital inputs at
VDD or AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
10
Bits
INL Integral nonlinearity(1) (2)
1
1
LSB
LSB
–1
–1
-5
DNL Differential nonlinearity(1) (2)
0
0
+5
+5
1
1.8 V ≤VDD ≺ 2.7 V
Offset error(3)
mV
-5
2.7 V ≤VDD ≤5.5 V
Gain error(3)
%FSR
V
–1
Input voltage range
Data rate
External VREF = VDD, VFB attenuation is 1
TBD
0
VDD
TBD
TBD
TBD
10
SPS
f = 1 kHz, VFB = VDD/2
ADC noise density
Sampling capacitor
µV/√Hz
Internal VREF, gain = 4x, f = 1 kHz, VFB = VDD/2
pF
(1) Measured with DAC output unloaded. For external reference and internal reference VDD ≥1.21 x gain + 0.2 V, between end-point
codes: 8d to 1008d for 10-bit resolution, 2d to 252d for 8-bit resolution.
(2) Specified by design and characterization, not production tested.
(3) Measured at DAC at mid-scale, comparator input at Hi-Z, and DAC operating with external reference.
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6.9 Electrical Characteristics: General
all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.8 V ≤VDD ≤5.5 V,
DAC reference tied to VDD, gain = 1x in voltage output mode or ±250µA output range in current output mode, DAC output
pin (OUT) loaded with resistive load (RL = 5 kΩto AGND) in voltage-output mode and capacitive load (CL = 200 pF to
AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER
INTERNAL REFERENCE
Initial accuracy
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA = 25°C
1.212
V
Reference output temperature
50 ppm/°C
coefficient(1)
EXTERNAL REFERENCE
External reference input range
EEPROM
1.7
VDD
V
20000
1000
50
–40°C ≤TA ≤85°C
TA = 125°C
Endurance
Cycles
Data retention(1)
TA = 25°C
Years
ms
EEPROM programming write
cycle time(1)
200
DIGITAL INPUTS
Voltage output mode, DAC output static at midscale,
fast+ mode, SCL toggling
Digital feedthrough
20
10
nV-s
pF
Pin capacitance
Per pin
POWER-DOWN MODE
IDD
Current flowing into VDD
DAC in sleep mode, internal reference powered down
17
µA
HIGH-IMPEDANCE OUTPUT
10
nA
nA
DAC in Hi-Z output mode, 1.7 V ≤VDD ≤5.5 V
VDD = 0 V, VOUT ≤1.5 V, decoupling capacitor
between VDD and AGND: 0.1 μF
200
Current flowing into VOUTX and
VFBX
ILEAK
VDD = 0 V, 1.5 V < VOUT ≤5.5 V, decoupling capacitor
between VDD and AGND: 0.1 μF
500
2
nA
µA
100 kΩbetween VDD and AGND, VOUT ≤1.25 V,
series resistance of 10 kΩat OUT pin
(1) Specified by design and characterization, not production tested.
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6.10 Timing Requirements: I2C Standard Mode
all input signals are timed from VIL to 70% of VDD, 1.8 V ≤VDD ≤5.5 V, –40°C ≤TA ≤+125°C, and 1.8 V ≤Vpull-up
≤VDD
V
MIN
NOM
MAX
UNIT
kHz
µs
fSCLK
tBUF
SCL frequency
100
Bus free time between stop and start conditions
Hold time after repeated start
Repeated start setup time
Stop condition setup time
Data hold time
4.7
4
tHDSTA
tSUSTA
tSUSTO
tHDDAT
tSUDAT
tLOW
tHIGH
tF
µs
4.7
4
µs
µs
0
ns
Data setup time
250
4700
4000
ns
SCL clock low period
ns
SCL clock high period
Clock and data fall time
Clock and data rise time
ns
300
ns
tR
1000
ns
6.11 Timing Requirements: I2C Fast Mode
all input signals are timed from VIL to 70% of VDD, 1.8 V ≤VDD ≤5.5 V, –40°C ≤TA ≤+125°C, and 1.8 V ≤Vpull-up
≤VDD
V
MIN
NOM
MAX
UNIT
kHz
µs
fSCLK
tBUF
SCL frequency
400
Bus free time between stop and start conditions
Hold time after repeated start
Repeated start setup time
Stop condition setup time
Data hold time
1.3
0.6
tHDSTA
tSUSTA
tSUSTO
tHDDAT
tSUDAT
tLOW
tHIGH
tF
µs
0.6
µs
0.6
µs
0
ns
Data setup time
100
1300
600
ns
SCL clock low period
ns
SCL clock high period
Clock and data fall time
Clock and data rise time
ns
300
300
ns
tR
ns
6.12 Timing Requirements: I2C Fast Mode Plus
all input signals are timed from VIL to 70% of VDD, 1.8 V ≤VDD ≤5.5 V, –40°C ≤TA ≤+125°C, and 1.8 V ≤Vpull-up
≤VDD
V
MIN
NOM
MAX
UNIT
MHz
µs
fSCLK
tBUF
SCL frequency
1
Bus free time between stop and start conditions
Hold time after repeated start
Repeated start setup time
Stop condition setup time
Data hold time
0.5
0.26
0.26
0.26
0
tHDSTA
tSUSTA
tSUSTO
tHDDAT
tSUDAT
tLOW
µs
µs
µs
ns
Data setup time
50
ns
SCL clock low period
0.5
µs
tHIGH
tF
SCL clock high period
Clock and data fall time
0.26
µs
120
ns
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6.12 Timing Requirements: I2C Fast Mode Plus (continued)
all input signals are timed from VIL to 70% of VDD, 1.8 V ≤VDD ≤5.5 V, –40°C ≤TA ≤+125°C, and 1.8 V ≤Vpull-up
≤VDD
V
MIN
NOM
MAX
UNIT
tR
Clock and data rise time
120
ns
6.13 Timing Requirements: SPI Write Operation
all input signals are timed from VIL to 70% of VDD, VDD = 1.8 V to 5.5 V, and –40°C ≤TA ≤+125°C
MIN
NOM
MAX
UNIT
MHz
ns
f(SCLK)
25
Serial clock frequency, 1.7 V ≤VDD ≤5.5 V
SCLK high time, 1.7 V ≤VDD ≤5.5 V
tSCLKHIGH
tSCLKLOW
tSDIS
18
18
8
ns
SCLK low time, 1.7 V ≤VDD ≤5.5 V
ns
SDI setup time, 1.7 V ≤VDD ≤5.5 V
tSDIH
8
ns
SDI hold time, 1.7 V ≤VDD ≤5.5 V
tCSS
18
10
50
2
ns
CS to SCLK falling edge setup time, 1.7 V ≤VDD ≤5.5 V
SCLK falling edge to CS rising edge, 1.7 V ≤VDD ≤5.5 V
CS hight time, 1.7 V ≤VDD ≤5.5 V
tCSH
ns
tCSHIGH
tDACWAIT
tBCASTWAIT
ns
µs
Sequential DAC update wait time for same channel, 1.7 V ≤VDD ≤5.5 V
Broadcast DAC update wait time, 1.7 V ≤VDD ≤5.5 V
2
µs
6.14 Timing Requirements: SPI Read and Daisy Chain Operation
all input signals are timed from VIL to 70% of VDD, VDD = 1.8 V to 5.5 V, and –40°C ≤TA ≤+125°C
MIN
NOM
MAX
UNIT
MHz
ns
f(SCLK)
tSCLKHIGH
tSCLKLOW
tSDIS
1
Serial clock frequency, 1.7 V ≤VDD ≤5.5 V
SCLK high time, 1.7 V ≤VDD ≤5.5 V
400
400
8
ns
SCLK low time, 1.7 V ≤VDD ≤5.5 V
ns
SDI setup time, 1.7 V ≤VDD ≤5.5 V
tSDIH
8
ns
SDI hold time, 1.7 V ≤VDD ≤5.5 V
tCSS
400
10
1
ns
CS to SCLK falling edge setup time, 1.7 V ≤VDD ≤5.5 V
SCLK falling edge to CS rising edge, 1.7 V ≤VDD ≤5.5 V
CS hight time, 1.7 V ≤VDD ≤5.5 V
tCSH
ns
tCSHIGH
µs
6.15 Timing Requirements: GPIO
all input signals are timed from VIL to 70% of VDD, VDD = 1.8 V to 5.5 V, and –40°C ≤TA ≤+125°C
MIN
NOM
MAX
UNIT
µs
GPI high time, 1.7 V ≤VDD ≤5.5 V(1)
tGPIHIGH
tGPILOW
tGPAWGD
tCS2LDAC
tSTP2LDAC
tLDACW
2
GPI low time, 1.7 V ≤VDD ≤5.5 V(1)
2
µs
LDAC falling edge to DAC update delay, 1.7 V ≤VDD ≤5.5 V(2)
CS rising edge to LDAC falling edge, 1.7 V ≤VDD ≤5.5 V
I2C stop bit rising edge to LDAC falling edge, 1.7 V ≤VDD ≤5.5 V
LDAC low time, 1.7 V ≤VDD ≤5.5 V
2
µs
1
1
2
µs
µs
µs
(1) The SCL, SDA, A0, and A1 pins can be configured as GPIOs that perform different channel-specific or independent operations.
(2) The GPIOs can be configured as channel-specific or global LDAC function. In a channel-specific LDAC mode, the LDAC pins can be
used to trigger DAC code patterns stored in the NVM.
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6.16 Timing Diagrams
Low byte ACK cycle
tR
tLOW
tF
SCL
tSUSTA
tSUDAT
tHDSTA
tHIGH
tSUSTO
tHDDAT
tHDSTA
SDA
tBUF
S
P
S
P
图6-1. I2C Timing Diagram
图6-2. SPI Write Timing Diagram
图6-3. SPI Read Timing Diagram
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7 Detailed Description
7.1 Overview
The AFE539A4 is a 10-bit, smart analog front end (AFE) that is configurable as a quad-channel, buffered
voltage-output or current-output DAC, or as a quad-channel ADC. Each analog channel can be independently
configured as a DAC, a comparator, or an ADC, with the exception that ADC channel 3 must be configured as
comparator before using other channels as ADCs.
The AFE539A4 provides a preprogrammed state machine that functions as a proportional-integral (PI) controller.
This device contains nonvolatile memory (NVM), an internal reference, automatically detects I2C and SPI
interfaces, a force-sense output, and a general-purpose input. The device supports Hi-Z power-down modes by
default, which can be configured to 10 kΩ-GND or 100 kΩ-GND using the NVM. The AFE539A4 has a power-
on-reset (POR) circuit that makes sure all the registers start with default or user-programmed settings using
NVM. The AFE539A4 operates with either an internal reference, external reference, or with power supply as the
reference, and provide a full-scale output of 1.8 V to 5.5 V.
The AFE539A4 supports I2C standard mode (100 kbps), fast mode (400 kbps), and fast mode plus (1 Mbps).
The I2C interface can be configured with four device addresses using the A0 pin. The SPI mode supports a
three-wire interface by default, with up to 25-MHz SCLK input. The GPIO input can be configured as SDO in the
NVM for SPI read capability. The GPIO input can alternatively be configurable as LDAC, PD, STATUS, FAULT-
DUMP, RESET, and PROTECT functions. The AFE539A4 is designed for closed-loop control applications, such
as TEC control, car seat heating control, medical in-vitro diagnostics devices, blood gas analyzers, and thermal
cyclers.
The AFE539A4 also includes digital slew rate control, and supports standard waveform generation such as sine
and cosine, triangular, and sawtooth waveforms. This device can generate pulse-width modulation (PWM) output
with the combination of the triangular or sawtooth waveform and the FB pin. The force-sense outputs of the DAC
channels can be used as programmable comparators. The comparator mode allows programmable hysteresis,
latching comparator, window comparator, and fault-dump to the NVM. These features enable the AFE539A4 to
go beyond the limitations of a conventional AFE that depends on a processor to function. As a result of the
processor-less operation and the smart feature set, the AFE539A4 is called a smart AFE.
7.2 Functional Block Diagram
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7.3 Feature Description
7.3.1 Smart Analog Front End (AFE) Architecture
The AFE539A4 consists of quad-channel, 10-bit digital-to-analog converters with string architecture, followed by
a voltage-output amplifier with an external FB pin and a voltage-to-current converter for each channel. 节 7.2
shows the DAC architecture within the block diagram, which operates from a 1.8-V to 5.5-V power supply. The
DAC has an internal voltage reference of 1.21 V. There is an option to select an external reference on the VREF
pin or use the power supply as a reference. The voltage output mode uses one of these three reference options.
The current output mode uses an internal band-gap reference to generate the current outputs. Both the voltage-
output and current-output modes support multiple programmable output ranges.
The AFE539A4 supports Hi-Z output when VDD is off, maintaining very low leakage current at the output pins
with up to 1.25 V of forced voltage.
The AFE539A4 supports an independent comparator mode for each channel. The respective FBx pins act as the
inputs for the comparator. The DAC architecture supports inversion of the comparator output using register
settings. The comparator outputs can be push-pull or open-drain. The comparator mode supports programmable
hysteresis using margin-high and margin-low register fields, a latching comparator, and a window comparator.
The comparator outputs are accessible internally by the device.
The AFE539A4 features an ADC on channel 3, with inputs that are multiplexed to all other channels: FB0/AIN0
for channel 0, FB1/AIN1 for channel 1, and FB2/AIN2 for channel 2. For channel 3, the ADC input pin is OUT3/
AIN3, not FB3. Connect FB3 to VDD using a pullup resistor whenever the ADC mode selected. Any channel that
is used as an ADC must be selected as a comparator. To use any other channel as an ADC, ADC3 must be
enabled as an ADC or comparator, even if not used.
The AFE539A4 features a programmable state machine supporting arithmetic, logic, and timing operations, as
shown in 图 7-1. This state machine has been preprogrammed as a proportional-integral (PI) controller allowing
the user to program the coefficients and input-output parameters. The details of the PI controller are discussed in
节 7.4.5.2. The state machine can be disabled by writing to the APPLICATION-CONFIG1 register. The user
configurations are stored in the NVM and the state machine can be operated in standalone mode without
interfacing to a processor (processor-less operation)
图7-1. Smart AFE Architecture
The AFE539A4 also supports internal function generation, such as sawtooth, triangular, and sine.
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7.3.2 Digital Input/Output
The AFE539A4 have four digital IO pins that include I2C, SPI, and GPIO interfaces. These devices automatically
detect I2C and SPI protocols at the first successful communication after power on, and then connect to the
detected interface. After an interface protocol is connected, any change in the protocol is ignored. The I2C
interface uses the A0 pin to select from among four address options. The SPI is a three-wire interface by default.
No readback capability is available in the three-wire SPI mode. The GPIO pin can be configured as the SDO
function in the register map and then programmed into the NVM. With the GPIO pin acting as SDO, the SPI
works as a four-wire interface. The SPI readback mode is slower than the write mode. The programming
interface pins are:
• For I2C: SCL, SDA, A0
• For SPI: SCLK, SDI, SYNC, SDO/GPIO
The GPIO can be configured as multiple functions other than SDO. These functions are LDAC, PD, STATUS,
PROTECT, FAULT-DUMP, and RESET. All the digital pins are open-drain when used as outputs. Therefore, all
the output pins must be pulled up to the desired IO voltage using external registers.
7.3.3 Nonvolatile Memory (NVM)
The AFE539A4 contain nonvolatile memory (NVM) bits. These memory bits are user programmable and
erasable, and retain the set values in the absence of a power supply. All the register bits, shown in the
highlighted gray cells in 表 7-15 and 表 7-16, can be stored in the NVM by setting NVM-PROG = 1 in the
COMMON-TRIGGER register; this bit automatically resets. The NVM-BUSY bit in the GENERAL-STATUS
register is set to 1 by the device when an NVM write or reload operation is ongoing. During this time, the device
blocks all read and write operations to the device. The NVM-BUSY bit is set to 0 after the write or reload
operation is complete; at this point, all read and write operations to the device are allowed. The default value for
all the registers in the AFE539A4 is loaded from NVM as soon as a POR event is issued.
The AFE539A4 also reloads the registers with the current values stored in the NVM using the NVM-RELOAD bit
in the COMMON-TRIGGER register. Set this bit to 1 for the device to start an NVM reload operation. After
completion, the device automatically resets this bit to 0. During the NVM-RELOAD operation, the NVM-BUSY bit
is set to 1.
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7.4 Device Functional Modes
7.4.1 Voltage-Output Mode
The voltage-output mode for each DAC channel can be entered by selecting the power-up option in the VOUT-
PDN-X fields in the COMMON-CONFIG register and simultaneously powering down the current output option for
the respective channels using the IOUT-PDN-X bits in the same register. Short the OUTx and FBx pins of
respective channels externally for closed-loop amplifier output. An open FBx pin saturates the amplifier output.
To achieve the desired voltage output, select the correct reference option, select the amplifier gain for the
required output range, and program the DAC code in the DAC-X-DATA register of the respective channels.
7.4.1.1 Voltage Reference and DAC Transfer Function
There are three voltage reference options possible with the AFE539A4: internal reference, external reference,
and the power supply as reference, as shown in 图 7-2. The DAC transfer function in the voltage-output and
comparator modes changes based on the voltage reference selection.
图7-2. Voltage Reference Selection and Power-Down Logic
7.4.1.2 Internal Reference
The AFE539A4 contain an internal reference that is disabled by default. To enable the internal reference, write 1
to bit EN-INT-REF in the COMMON-CONFIG register. The internal reference generates a fixed 1.21-V voltage
(typical). Use the VOUT-GAIN-X field in the DAC-X-VOUT-CMP-CONFIG register to achieve gains of 1.5x, 2x,
3x, or 4x for the DAC output voltage (VOUT). 方程式1 shows DAC transfer function using the internal reference.
DAC_DATA
V
=
× V
× GAIN
REF
(1)
OUT
N
2
where:
• N is the resolution in bits, 10 bits for AFE539A4
• DAC_DATA is the decimal equivalent of the binary code that is loaded to the DAC-X-DATA field in the DAC-
X-DATA register.
• DAC_DATA ranges from 0 to 2N –1.
• VREF is the internal reference voltage = 1.21 V.
• GAIN = 1.5x, 2x, 3x, or 4x, based on VOUT-X-GAIN bits.
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7.4.1.3 External Reference
The AFE539A4 provide an external reference input. Select the external reference option by configuring the
VOUT-GAIN-X field in the DAC-X-VOUT-CMP-CONFIG register appropriately. Write 1 to the DIS-MODE-IN bit in
the DEVICE-MODE-CONFIG register to minimize quiescent current. The external reference can be between
1.8 V and VDD. 方程式2 shows DAC transfer function when the external reference is used.
Note
The external reference must be less than VDD in both transient and steady-state conditions.
Therefore, the external reference must ramp up after VDD and ramp down before VDD.
DAC_DATA
V
=
× V
(2)
OUT
REF
N
2
where:
• N is the resolution in bits, 10 bits for AFE539A4.
• DAC_DATA is the decimal equivalent of the binary code that is loaded to the DAC-X-DATA field in the DAC-
X-DATA register.
• DAC_DATA ranges from 0 to 2N –1.
• VREF is the external reference voltage.
7.4.1.4 Power-Supply as Reference
By default, the AFE539A4 operate with the power-supply pin (VDD) as a reference. 方程式 3 shows DAC
transfer function when the power-supply pin is used as reference. The gain at the output stage is always 1x.
DAC_DATA
V
=
× V
(3)
OUT
DD
N
2
where:
• N is the resolution in bits, 10 bits for AFE539A4.
• DAC_DATA is the decimal equivalent of the binary code that is loaded to the DAC-X-DATA field in the DAC-
X-DATA register.
• DAC_DATA ranges from 0 to 2N –1.
• VDD is used as the DAC reference voltage.
7.4.2 Current-Output Mode
The current-output mode for each DAC channel is entered by disabling the respective IOUT-PDN-X bits in the
COMMON-CONFIG register and putting the respective VOUT-PDN-X fields in the same register in Hi-Z power-
down. Select the desired current-output range by writing to the IOUT-RANGE-X field in the DAC-X-IOUT-MISC-
CONFIG register. To minimize leakage in current-output mode, disconnect the FBx pin. The internal trimming
settings for voltage-output and current-output modes are different; therefore, there may be a momentary dc
offset when switching between voltage-output to current-output modes. Program the mode selection into the
NVM to avoid this offset. The transfer function of the current-output is shown in 方程式4.
DAC_DATA × I
− I
MIN
MAX
I
=
+ I
(4)
OUT
MIN
8
2
where:
• DAC_DATA is the DAC-X-DATA code.
• IMAX is the signed maximum current in the IOUT-RANGE-X setting.
• IMIN is the signed minimum current in the IOUT-RANGE-X setting.
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7.4.3 Comparator Mode
All the DAC channels can be configured as programmable comparators. To enter the comparator mode for a
channel, write 1 to the CMP-X-EN and the CMP-X-OUT-EN bits in the respective DAC-X-VOUT-CMP-CONFIG
register. The comparator output can be configured as push-pull or open-drain using the CMP-X-OD-EN bit. To
invert the comparator output, write 1 to the CMP-X-INV-EN bit. The FBx pin has a finite impedance. To enable
high-impedance on the FBx pin, write 1 to the CMP-X-HIZ-IN-DIS bit.
Note
In the Hi-Z input mode, the comparator input range is limited to:
• For GAIN = 1x, 1.5x, or 2x: VFB ≤(VREF × GAIN) / 3
• For GAIN = 3x, or 4x: VFB ≤(VREF × GAIN) / 6
Any higher input voltage is clipped.
Individual comparator channels can be configured in no-hysteresis, with-hysteresis, and window-comparator
modes using the CMP-X-MODE field in the respective DAC-X-CMP-MODE-CONFIG register.
7.4.4 Analog-to-Digital Converter (ADC) Mode
The quad DAC channels of the AFE539A4 can be converted to independent ADC inputs, as shown in 图 7-3.
The main ADC channel is ADC3, whereas the other inputs are multiplexed to ADC3. The ADCs can either be
controlled by the communication register using the register map or by the state machine. By default, the ADCs
are controlled by the state-machine in this device. To change the controller to the register map, stop the state
machine and then change the ADC controller in the ADC-CONFIG register. The ADC inputs for different
channels are listed in 表 7-1. Whenever any channel is selected as ADC, ADC3 must be configured as a
comparator and the FB3/AIN3 pin must be connected to VDD using a pullup resistor. The transfer function of the
ADC is given in 方程式5.
V
× K
IN
V
N − 1
ADC_DATA = INTEGER
× 2
(5)
FS
where:
• ADC_DATA is the ADC-DATA value in the ADC-DATA register.
• VIN is the input voltage at the respective ADC input pin.
• K is the attenuation factor at the ADC input; 1 for finite impedance and 3 for Hi-Z.
• VFS is the full-scale voltage set as per the voltage reference selection and gain setting. For example, if the
1.21-V internal reference is selected and the gain setting is 2x, then VFS is 2.42 V.
• N is the number of ADC bits. For AFE539A4, N = 10.
• (INTEGER) denotes integer division.
Follow these steps to configure and read data from ADC channel x:
1. Configure the full-scale voltage using VOUT-GAIN-X for the corresponding channel in the DAC-X-VOUT-
CMP-CONFIG register.
2. Configure DAC channel 3 as comparator by writing 1 to the CMP-X-EN bit in the DAC-3-VOUT-CMP-
CONFIG register. Only Hi-Z input is allowed in channel 3.
3. Configure DAC channel-x as comparator by writing 1 to the CMP-X-EN bit in the DAC-X-VOUT-CMP-
CONFIG register.
4. Select the ADC controller, number of averages, and ADC channel and then trigger the ADC conversion
using the ADC-CONFIG-TRIG register.
5. Read the ADC data using the ADC-DATA register. the data are valid when the ADC-DRDY bit is 1.
6. Repeat steps 4 and 5 for every ADC readback.
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图7-3. ADC Interface
表7-1. ADC Input Pins
ADC CHANNEL
PIN
INPUT RANGE
Hi-Z: 0 V to VFS/3
ADC0
FB0/AIN0
FB1/AIN1
Finite Impedance: 0 V to VFS
Hi-Z: 0 V to VFS/3
Finite Impedance: 0 V to VFS
ADC1
Hi-Z: 0 V to VFS/3
Finite Impedance: 0 V to VFS
ADC2
ADC3
FB2/AIN2
OUT3/AIN3
Hi-Z: 0 V to VFS/3
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7.4.5 Application-Specific Modes
This section provides the details of application-specific functional modes available in the AFE539A4.
7.4.5.1 Function Generation
The AFE539A4 implements a continuous waveform generation feature. These devices can generate a triangular
wave, sawtooth wave, and sine wave independently for every channel.
7.4.5.1.1 Programmable Slew-Rate Control
When the DAC data registers are written, the voltage on DAC output (VOUT) immediately transitions to the new
code following the slew rate and settling time specified in the Electrical Characteristics. The slew rate control
feature allows the user to control the rate at which the output voltage (VOUT) changes. When this feature is
enabled (using SLEW-RATE-X[3:0] bits), the DAC output changes from the current code to the code in DAC-X-
MARGIN-HIGH or DAC-X-MARGIN-LOW registers (when margin high or low commands are issued to the DAC)
using the step and rate set in CODE-STEP-X and SLEW-RATE-X bits in the DAC-X-FUNC-CONFIG register.
With the default slew rate control setting of no-slew, the output changes smoothly at a rate limited by the output
drive circuitry and the attached load. Using the slew-rate control feature, the output steps digitally at a rate
defined by bits CODE-STEP-X and SLEW-RATE-X. SLEW-RATE-X defines the rate at which the digital slew
updates; CODE-STEP-X defines the amount by which the output value changes at each update, for the
corresponding channels. 表 7-2 and 表 7-3 show different settings available for CODE-STEP-X and SLEW-
RATE-X.
When the slew rate control feature is used, the output changes happen at the programmed slew rate. This
configuration results in a staircase formation at the output as shown in 图 7-4. Do not write to CODE-STEP-X,
SLEW-RATE-X, or DAC-X-DATA during the output slew operation.
图7-4. Programmable Slew-Rate Control
表7-2. Code Step
REGISTER
CODE-STEP-X[2]
CODE-STEP-X[1]
CODE-STEP-X[0]
CODE STEP SIZE
1 LSB (default)
2 LSB
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3 LSB
4 LSB
DAC-X-FUNC-CONFIG
6 LSB
8 LSB
16 LSB
32 LSB
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表7-3. Slew Rate
TIME PERIOD
REGISTER
SLEW-RATE-X[3] SLEW-RATE-X[2] SLEW-RATE-X[1] SLEW-RATE-X[0]
(PER STEP)
No slew (default)
4 µs
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
8 µs
12 µs
18 µs
27 µs
40.5 µs
60.75 µs
91.13 µs
136.69 µs
239.2 µs
418.61 µs
732.56 µs
1281.98 µs
1281.98 µs
5127.92 µs
DAC-X-FUNC-CONFIG
7.4.5.1.2 Triangular Waveform Generation
The triangular waveform uses the DAC-X-MARGIN-LOW and DAC-X-MARGIN-HIGH registers for minimum and
maximum levels, respectively. The frequency of the waveform depends on the minimum and maximum levels,
CODE-STEP and SLEW-RATE settings as shown in 方程式 6. An external RC load with a time-constant larger
than the slew-rate settings can be dominant over the internal frequency calculation. The CODE-STEP-X and
SLEW-RATE-X settings are available in the DAC-X-FUNC-CONFIG register. Writing 0b000 to the FUNC-
CONFIG-X bit field in the DAC-X-FUNC-CONFIG register selects triangular waveform.
1
f
=
(6)
TRIANGLE_WAVE
MARGIN_HIGH − MARGIN_LOW + 1
2 × SLEW_RATE ×
CODE_STEP
where:
• SLEW_RATE is the SLEW-RATE-X setting as specified in 表7-3.
• CODE_STEP is the CODE-STEP-X setting as specified in 表7-2.
• MARGIN_HIGH is the DAC-X-MAGIN-HIGH as specified in 节7.6.2.
• MARGIN_LOW is the DAC-X-MAGIN-LOW as specified in 节7.6.3.
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7.4.5.1.3 Sawtooth Waveform Generation
The sawtooth and the inverse sawtooth waveforms use the DAC-X-MARGIN-LOW and DAC-X-MARGIN-HIGH
registers for minimum and maximum levels, respectively. The frequency of the waveform depends on the min
and max levels, CODE-STEP and SLEW-RATE settings as shown in 方程式 7. An external RC load with a time
constant larger than the slew-rate settings can be dominant over the internal frequency calculation. The CODE-
STEP-X and SLEW-RATE-X settings are available in the DAC-X-FUNC-CONFIG register. Write 0b001 to the
FUNC-CONFIG-X bit field in the DAC-X-FUNC-CONFIG register to select sawtooth waveform, and write 0b010
to select inverse sawtooth waveform.
1
f
=
(7)
SAWTOOTH_WAVE
MARGIN_HIGH − MARGIN_LOW + 1
SLEW_RATE ×
CODE_STEP
where:
• SLEW_RATE is the SLEW-RATE-X setting as specified in 表7-3.
• CODE_STEP is the CODE-STEP-X setting as specified in 表7-2.
• MARGIN_HIGH is the DAC-X-MAGIN-HIGH as specified in 节7.6.2.
• MARGIN_LOW is the DAC-X-MAGIN-LOW as specified in 节7.6.3.
7.4.5.1.4 Sine Waveform Generation
The sine wave function uses 24 preprogrammed points per cycle. The frequency of the sine wave depends on
the SLEW-RATE settings as shown in 方程式 8. An external RC load with a time constant larger than the slew-
rate settings can be dominant over the internal frequency calculation. The SLEW-RATE-X setting is available in
the DAC-X-FUNC-CONFIG register. Writing 0b100 to the FUNC-CONFIG-X bit field in the DAC-X-FUNC-
CONFIG register selects sine wave. The minimum level for the sine wave is always zero-code and the maximum
level is always full-code. Use the gain settings at the output amplifier for changing the full-scale output using the
internal reference option. The gain settings are accessible through the VOUT-GAIN-X bits in the DAC-X-VOUT-
CMP-CONFIG register. There are four phase settings available for the sine wave that are selected using the
PHASE-SEL-X bit in the DAC-X-FUNC-CONFIG register.
1
f
=
(8)
SINE_WAVE
24 × SLEW_RATE
where:
• SLEW_RATE is the SLEW-RATE-X setting as specified in 表7-3.
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7.4.5.2 Proportional-Integral (PI) Controller
The AFE539A4 provides a preprogrammed PI controller state machine, as shown in 图 7-5. ADC channel 0 is
used as the input and DAC channel 1 is used as the output. DAC channel 2 is used as a comparator that is used
to set the output of DAC channel 1 to a value specified by the SAFE-OUTPUT field. 表 7-4 lists all the input/
output pin names and functions.
图7-5. PI Controller Architecture
表7-4. PI Controller Pin Definition
PIN
FUNCTION
RANGE
Hi-Z: 0 V to VFS/3
FB0/AIN0
ADC0 input
Finite impedance: 0 V to VFS
OUT0
Not applicable
Not connected—leave floating.
FB1/AIN1
OUT1
Not applicable
Voltage-feedback input for DAC1—connect this pin to OUT1
DAC1 voltage output
0 V to VFS
FB2/AIN2
Hi-Z: 0 V to VFS/3
DAC2 comparator input—connect to AGND if unused for safe
Finite impedance: 0 V to VFS
output clamping
OUT2
Not applicable
Not applicable
Not applicable
Not connected—leave floating
FB3/AIN3
OUT3
Not used for PI contr0l—connect to VDD using a pullup resistor
Not connected—leave floating
The PI controller provides many configuration parameters. The following list describes the function of each
configuration parameter:
• SETPOINT: The 10-bit set point to which the ADC input is compared by the PI controller. The unit of this
value is the same as the value at the ADC0 input. The PI controller minimizes the error between the set point
and the sensed ADC data. The SETPOINT value is statically programmed using SRAM address 0x22. To
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change the SETPOINT value when the PI controller is running, use register address 0x06, as shown in 图
7-5.
• KP: This 16-bit parameter is used as the proportional gain. KP is multiplied with the instantaneous error. A
higher KP enables the loop to correct the error faster. However, if the external process has a fast response
time, a higher KP may cause system instability.
• KI: This 16-bit parameter is used as inverse integral gain. KI is inverted and multiplied to the accumulated
error. This parameter is important to help minimize the steady-state error under different ambient conditions
of the process. A higher KI means a weaker response to the steady-state error. A smaller KI can effectively
correct the steady-state error, but can also lead to bigger oscillations. The integral function is disabled when
KI = 0.
• MAX-OUTPUT: This 10-bit value limits the maximum value of the PI controller output.
• MIN-OUTPUT: This 10-bit value limits the minimum value of the PI controller output.
• COMMON-MODE: This 10-bit value is present at the PI output when the proportional and integral outputs are
zero. This parameter is very important to help achieve a uniform response for all set points with fixed KP and
KI settings. COMMON-MODE represents the nominal output to achieve a given set point. Therefore, for best
results, use empirically measured COMMON-MODE values for every set point. The COMMON-MODE value
is statically programmed using the SRAM address 0x25. To change the set-point value when the PI control is
running, use register address 0x0C, as shown in 图7-5.
• LOOP-POLARITY: This 1-bit parameter provides the option to invert the phase of the PI-controller loop. This
function is useful when the loop external to the device has an additional phase inversion. The sensed data
after the phase setting can be read at the dynamic address 0x18.
• SAFE-OUTPUT: This 10-bit parameter is used to take the output to this predefined value based on the output
of comparator channel 2. This function is useful in failure scenarios.
• ADC0-MODE: This 1-bit parameter is used to select between Hi-Z or finite-impedance mode for ADC0.
ADC0-MODE = 0 corresponds to Hi-Z input; ADC0-MODE = 1 corresponds to finite-impedance input.
• CMP2-THRESHOLD: This 10-bit parameter is used to set the threshold for comparator channel 2.
Note
An SRAM location is accessed using the SRAM-ADDR and SRAM-DATA registers. Do not access the
SRAM registers when the state machine is running. The state machine can be stopped by writing to
the STATE-MACHINE-CONFIG0 register. The critical parameters that must be updated in run-time
can be accessed using the dynamic locations as listed in 表7-5. The static (SRAM) locations in 表7-5
are mapped to NVM. The dynamic locations are not mapped to the NVM. Set all the unassigned bits
in the static SRAM locations to 0.
表7-5. PI Controller Parameters
REGISTER FIELD
NAME
STATIC ADDRESS
LOCATION
DEFAULT VALUE
(16-BIT ALIGNED)
DYNAMIC ADDRESS
LOCATION
STATIC ADDRESS
DYNAMIC ADDRESS
SETPOINT
0x22[9:0]
0x23[15:0]
0x26[15:0]
0x20[15:6]
0x21[15:6]
0x25[11:2]
0x27[0]
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
0x0200
0x0064
0x0001
0x7FC0
0x0000
0x7FC0
0x0000
0x0000
0x0000
0x7FC0
0x06[9:0]
N/A
Register
N/A
KP
KI
N/A
N/A
MAX-OUTPUT
MIN-OUTPUT
COMMON-MODE
LOOP-POLARITY
SAFE-OUTPUT
ADC0-MODE
CMP2-THRESHOLD
N/A
N/A
N/A
N/A
0x0C[11:2]
N/A
Register
N/A
0x27[15:6]
0x27[1]
N/A
N/A
N/A
N/A
0x24[15:6]
N/A
N/A
Follow these steps to configure and operate the PI controller:
1. Stop the state machine by writing 0 to the SM-ABORT and SM-EN bits in the STATE-MACHINE-CONFIG0
register.
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2. Connect the ADC input, comparator input, and DAC output as shown in 图7-5.
3. Write to the COMMON-CONFIG register to enable all the DAC channels.
4. Write to the DAC-X-VOUT-CMP-CONFIG register for respective channels to select the voltage reference
and output range for each channel. Configure channels 0, 2, and 3 as comparators.
5. Calculate the voltage output range for DAC1 and configure MIN-OUTPUT and MAX-OUTPUT accordingly.
6. Program the configuration parameters LOOP-POLARITY, ADC0-MODE, CMP2-THRESHOLD, and SAFE-
OUTPUT as appropriate for the system.
7. Program the initial values of KP and KI.
8. Maintain a table to SETPOINT versus COMMON-MODE in the host processor and program these values as
required by the system.
9. Configure the STATE-MACHINE-CONFIG0 register to start the state machine.
10. Tune the KP and KI iteratively to achieve the best transient and steady-state response.
11. Store the values in the NVM by writing to the NVM-PROG bit in the COMMON-TRIGGER register.
12. Start the state machine by writing 1 to the SM-EN and SM-START bits in the STATE-MACHINE-CONFIG0
register>
7.4.6 Device Reset and Fault Management
This section provides the details of power-on-reset (POR), software reset, and other diagnostics and fault-
management features of AFE539A4.
7.4.6.1 Power-On Reset (POR)
The AFE539A4 family of devices includes a power-on reset (POR) function that controls the output voltage at
power up. After the VDD supply has been established, a POR event is issued. The POR causes all registers to
initialize to default values, and communication with the device is valid only after a POR (boot-up) delay. The
default value for all the registers in the AFE539A4 is loaded from NVM as soon as the POR event is issued.
When the device powers up, a POR circuit sets the device to the default mode. The POR circuit requires specific
VDD levels, as indicated in 图 7-6, to make sure that the internal capacitors discharge and reset the device at
power up. To make sure that a POR occurs, VDD must be less than 0.7 V for at least 1 ms. When VDD drops to
less than 1.65 V, but remains greater than 0.7 V (shown as the undefined region), the device may or may not
reset under all specified temperature and power-supply conditions. In this case, initiate a POR. When VDD
remains greater than 1.65 V, a POR does not occur.
VDD (V)
5.5 V
Specified supply
voltage range
No power-on reset
1.71 V
1.65 V
Undefined
0.7 V
Power-on reset
0 V
图7-6. Threshold Levels for VDD POR Circuit
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7.4.6.2 External Reset
An external reset to the device can be triggered through the GPIO pin or through the register map. To initiate a
device software reset event, write the reserved code 1010 to the RESET field in the COMMON-TRIGGER
register. A software reset initiates a POR event. The GPIO pin can be configured as a RESET pin as shown in 表
7-13. This configuration must be programmed into the NVM so that the setting is not cleared after the device
reset. The RESET input must be a low pulse. The device comes out of reset on the rising edge of the RESET
input.
7.4.6.3 Register-Map Lock
The AFE539A4 implement a register-map lock feature that prevents an accidental or unintended write to the
DAC registers. The device locks all the registers when the DEV-LOCK bit in the COMMON-CONFIG register is
set to 1. To bypass the DEV-LOCK setting, write 0101 to the DEV-UNLOCK bits in the COMMON-TRIGGER
register.
7.4.6.4 NVM Cyclic Redundancy Check (CRC)
The AFE539A4 implement a cyclic redundancy check (CRC) feature for the NVM to make sure that the data
stored in the NVM is uncorrupted. There are two types of CRC alarm bits implemented in AFE539A4:
• NVM-CRC-FAIL-USER
• NVM-CRC-FAIL-INT
The NVM-CRC-FAIL-USER bit indicates the status of user-programmable NVM bits, and the NVM-CRC-FAIL-
INT bit indicates the status of internal NVM bits The CRC feature is implemented by storing a 16-Bit CRC
(CRC-16-CCITT) along with the NVM data each time NVM program operation (write or reload) is performed and
during the device start up. The device reads the NVM data and validates the data with the stored CRC. The CRC
alarm bits (NVM-CRC-FAIL-USER and NVM-CRC-FAIL-INT in the GENERAL-STATUS register) report any
errors after the data are read from the device NVM. The alarm bits are set only at boot-up.
7.4.6.4.1 NVM-CRC-FAIL-USER Bit
A logic 1 on NVM-CRC-FAIL-USER bit indicates that the user-programmable NVM data are corrupt. During this
condition, all registers in the DAC are initialized with factory reset values, and any DAC registers can be written
to or read from. To reset the alarm bits to 0, issue a software reset (see 节 7.4.6.2) command, or cycle power to
the DAC. A software reset or power-cycle also reloads the user-programmable NVM bits. In case the failure
persists, reprogram the NVM.
7.4.6.4.2 NVM-CRC-FAIL-INT Bit
A logic 1 on NVM-CRC-FAIL-INT bit indicates that the internal NVM data are corrupt. During this condition, all
registers in the DAC are initialized with factory reset values, and any DAC registers can be written to or read
from. In case of a temporary failure, to reset the alarm bits to 0, issue a software reset (see 节7.4.6.2) command
or cycle power to the DAC. A permanent failure in the NVM makes the device unusable.
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7.4.7 Power-Down Mode
The AFE539A4 output amplifier and internal reference can be independently powered down through the EN-INT-
REF, VOUT-PDN-X, and IOUT-PDN-X bits in the COMMON-CONFIG register, as shown in 图 7-2. At power up,
the DAC output and the internal reference are disabled by default. In power-down mode, the DAC outputs (OUTx
pins) are in a high-impedance state. To change this state to 10 kΩ-AGND or 100 kΩ-AGND in the voltage-output
mode (at power up), use the VOUT-PDN-X bits. The power-down state for current-output mode is always high-
impedance.
The DAC power-up state can be programmed to any state (power-down or normal mode) using the NVM. 表 7-6
shows the DAC power-down bits. The individual channel power-down bits or the global device power-down
function can be mapped to the GPIO pin using the GPIO-CONFIG register.
表7-6. DAC Power-Down Bits
REGISTER
VOUT-PDN-X[1]
VOUT-PDN-X[0]
IOUT-PDN-X
DESCRIPTION
Power up VOUT-X
0
0
1
Power down VOUT-X with 10 kΩ to AGND.
0
1
1
1
1
0
1
1
1
1
1
0
Power down IOUT-X to Hi-Z
Power down VOUT-X with 100 kΩ to AGND.
Power down IOUT-X to Hi-Z
COMMON-CONFIG
Power down VOUT-X to Hi-Z.
Power down IOUT-X to Hi-Z (default)
Power down VOUT-X to Hi-Z.
Power up IOUT-X
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7.5 Programming
7.5.1 SPI Programming Mode
An SPI access cycle for AFE539A4 is initiated by asserting the SYNC pin low. The serial clock, SCLK, can be a
continuous or gated clock. SDI data are clocked on SCLK falling edges. The SPI frame for AFE539A4 is 24 bits
long. Therefore, the SYNC pin must stay low for at least 24 SCLK falling edges. The access cycle ends when the
SYNC pin is deasserted high. If the access cycle contains less than the minimum clock edges, the
communication is ignored. By default, the SDO pin is not enabled (3-wire SPI). In the 3-wire SPI mode, if the
access cycle contains more than the minimum clock edges, only the first 24 bits are used by the device. When
SYNC is high, the SCLK and SDI signals are blocked, and SDO extends the last bit transmitted.
Note
The SDO pin does not become Hi-Z when SYNC is high. Therefore, when sharing a single SPI bus
across multiple receivers, disable the SDO pin of the DAC before reading from other receivers.
表 7-7 describes the format for the 24-bit SPI access cycle. The first byte input to SDI is the instruction cycle.
The instruction cycle identifies the request as a read or write command and the 7-bit address that is to be
accessed. The last 16 bits in the cycle form the data cycle.
表7-7. SPI Read/Write Access Cycle
BIT
FIELD
DESCRIPTION
23
R/W
Identifies the communication as a read or write command to the address register:
R/W = 0 sets a write operation. R/W = 1 sets a read operation
22 - 16
15 - 0
A[6:0]
DI[15:0]
Register address: specifies the register to be accessed during the read or write
operation
Data cycle bits: If a write command, the data cycle bits are the values to be written
to the register with address A[6:0]. If a read command, the data cycle bits are don't
care values.
Read operations require that the SDO pin is first enabled by setting the SDO-EN bit in the INTERFACE-CONFIG
register. This is called 4-wire SPI. A read operation is initiated by issuing a read command access cycle. After
the read command, a second access cycle must be issued to get the requested data. The output data format is
shown in 表 7-8. Data are clocked out on the SDO pin either on the falling edge or rising edge of SCLK
according to the FSDO bit.
The daisy-chain operation is also enabled with the SDO pin. In the daisy-chain mode, multiple devices are
connected in a chain with the SDO pin of one device is connected to SDI pin of the following device. The SPI
host drives the SDI pin of the first device in the chain. The SDO pin of the last device in the chain is connected to
the MISO pin of the SPI host. In the 4-wire SPI mode, if the access cycle contains multiples of 24 clock edges,
only the last 24 bits are used by the device first device in the chain. If the access cycle contains clock edges that
are not in multiples of 24, the SPI packet is ignored by the device.
表7-8. SDO Output Access Cycle
BIT
23
FIELD
R/W
DESCRIPTION
Echo R/W from previous access cycle
22 - 16
15 - 0
A[6:0]
DI[15:0]
Echo register address from previous access cycle
Readback data requested on previous access cycle
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7.5.2 I2C Programming Mode
The AFE539A4 devices have a 2-wire serial interface (SCL and SDA), and one address pin (A0), as shown in
the pin diagram, 图 5-1. The I2C bus consists of a data line (SDA) and a clock line (SCL) with pullup structures.
When the bus is idle, both SDA and SCL lines are pulled high. All the I2C-compatible devices connect to the I2C
bus through the open drain I/O pins, SDA and SCL.
The I2C specification states that the device that controls communication is called a master, and the devices that
are controlled by the master are called slaves. The master device generates the SCL signal. The master device
also generates special timing conditions (start condition, repeated start condition, and stop condition) on the bus
to indicate the start or stop of a data transfer. Device addressing is completed by the master. The master device
on an I2C bus is typically a microcontroller or digital signal processor (DSP). The AFE539A4 family operates as a
slave device on the I2C bus. A slave device acknowledges master commands, and upon master control,
receives or transmits data.
Typically, the AFE539A4 family operates as a slave receiver. A master device writes to the AFE539A4, a slave
receiver. However, if a master device requires the AFE539A4 internal register data, the AFE539A4 operate as a
slave transmitter. In this case, the master device reads from the AFE539A4. According to I2C terminology, read
and write refer to the master device.
The AFE539A4 family is a slave and supports the following data transfer modes:
• Standard mode (100 kbps)
• Fast mode (400 kbps)
• Fast mode plus (1.0 Mbps)
The data transfer protocol for standard and fast modes is exactly the same; therefore, both modes are referred
to as F/S-mode in this document. The fast mode plus protocol is supported in terms of data transfer speed, but
not output current. The low-level output current would be 3 mA; similar to the case of standard and fast modes.
The AFE539A4 family supports 7-bit addressing. The 10-bit addressing mode is not supported. The device
supports the general call reset function. Sending the following sequence initiates a software reset within the
device: start or repeated start, 0x00, 0x06, stop. The reset is asserted within the device on the rising edge of the
ACK bit, following the second byte.
Other than specific timing signals, the I2C interface works with serial bytes. At the end of each byte, a ninth clock
cycle generates and detects an acknowledge signal. An acknowledge is when the SDA line is pulled low during
the high period of the ninth clock cycle. A not-acknowledge is when the SDA line is left high during the high
period of the ninth clock cycle, as shown in 图7-7.
Data output
by transmitter
Not acknowledge
Data output
by receiver
Acknowledge
2
9
1
8
SCL from
master
S
Clock pulse for
acknowledgement
Start
condition
图7-7. Acknowledge and Not Acknowledge on the I2C Bus
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7.5.2.1 F/S Mode Protocol
The following steps explain a complete transaction in F/S mode.
1. The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in 图7-8. All I2C-compatible devices
recognize a start condition.
2. The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit
(R/W) on the SDA line. During all transmissions, the master makes sure that data are valid. A valid data
condition requires the SDA line to be stable during the entire high period of the clock pulse, as shown in 图
7-9. All devices recognize the address sent by the master and compare the address to the respective
internal fixed address. Only the slave device with a matching address generates an acknowledge by pulling
the SDA line low during the entire high period of the 9th SCL cycle, as shown in 图7-7. When the master
detects this acknowledge, the communication link with a slave has been established.
3. The master generates further SCL cycles to transmit (R/W bit 0) or receive (R/W bit 1) data to the slave. In
either case, the receiver must acknowledge the data sent by the transmitter. The acknowledge signal can be
generated by the master or by the slave, depending on which is the receiver. The 9-bit valid data sequences
consists of 8-data bits and 1 acknowledge-bit, and can continue as long as necessary.
4. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from
low-to-high while the SCL line is high, as shown in 图7-8. This action releases the bus and stops the
communication link with the addressed slave. All I2C-compatible devices recognize the stop condition. Upon
receipt of a stop condition, the bus is released, and all slave devices then wait for a start condition followed
by a matching address.
SDA
SDA
SCL
SCL
S
P
Start
condition
Stop
condition
Change of data
allowed
Data line stable
Data valid
图7-8. Start and Stop Conditions
图7-9. Bit Transfer on the I2C Bus
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7.5.2.2 I2C Update Sequence
For a single update, the AFE539A4 require a start condition, a valid I2C address byte, a command byte, and two
data bytes, as listed in 表7-9.
表7-9. Update Sequence
MSB
....
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
ACK
Address (A) byte
节7.5.2.2.1
Command byte
节7.5.2.2.2
Data byte - MSDB
DB [15:8]
Data byte - LSDB
DB [7:0]
DB [31:24]
DB [23:16]
After each byte is received, the AFE539A4 family acknowledges the byte by pulling the SDA line low during the
high period of a single clock pulse, as shown in 图 7-10. These four bytes and acknowledge cycles make up the
36 clock cycles required for a single update to occur. A valid I2C address byte selects the AFE539A4 device.
Recognize
START or
REPEATED
Recognize
STOP or
REPEATED
Generate ACKNOWLEDGE
START
START
signal
condition
condition
P
SDA
Sr
MSB
Acknowledgement
signal from Slave
Address
R/W
1
SCL
1
7
8
9
2 - 8
9
Sr
or
P
S
or
Sr
ACK
ACK
START or
REPEATED
START or
STOP
REPEATED
START
condition
Clock line held low while
interrupts are serviced
condition
图7-10. I2C Bus Protocol
The command byte sets the operating mode of the selected AFE539A4 device. For a data update to occur when
the operating mode is selected by this byte, the AFE539A4 device must receive two data bytes: the most
significant data byte (MSDB) and least significant data byte (LSDB). The AFE539A4 device performs an update
on the falling edge of the acknowledge signal that follows the LSDB.
When using fast mode (clock = 400 kHz), the maximum DAC update rate is limited to 10 kSPS. Using fast mode
plus (clock = 1 MHz), the maximum DAC update rate is limited to 25 kSPS. When a stop condition is received,
the AFE539A4 device releases the I2C bus and awaits a new start condition.
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7.5.2.2.1 Address Byte
The address byte, as shown in 表 7-10, is the first byte received from the master device following the start
condition. The first four bits (MSBs) of the address are factory preset to 1001. The next three bits of the address
are controlled by the A0 pin. The A0 pin input can be connected to VDD, AGND, SCL, or SDA. The A0 pin is
sampled during the first byte of each data frame to determine the address. The device latches the value of the
address pin, and consequently responds to that particular address according to 表7-11.
表7-10. Address Byte
COMMENT
MSB
LSB
AD6
1
AD5
0
AD4
0
AD3
AD2
AD1
AD0
R/ W
—
See 表7-11
General address
1
0
0 or 1
0
(slave address column)
Broadcast address
1
0
0
1
1 1
The AFE539A4 supports broadcast addressing, which is used for synchronously updating or powering down
multiple AFE539A4 devices. When the broadcast address is used, the AFE539A4 responds regardless of the
address pin state. Broadcast is supported only in write mode.
表7-11. Address Format
SLAVE ADDRESS
A0 PIN
AGND
VDD
000
001
010
011
SDA
SCL
7.5.2.2.2 Command Byte
表7-17 lists the command byte in the ADDRESS column.
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7.5.2.3 I2C Read Sequence
To read any register the following command sequence must be used:
1. Send a start or repeated start command with a slave address and the R/W bit set to 0 for writing. The device
acknowledges this event.
2. Send a command byte for the register to be read. The device acknowledges this event again.
3. Send a repeated start with the slave address and the R/W bit set to 1 for reading. The device acknowledges
this event.
4. The device writes the MSDB byte of the addressed register. The master must acknowledge this byte.
5. Finally, the device writes out the LSDB of the register.
An alternative reading method allows for reading back the value of the last register written. The sequence is a
start or repeated start with the slave address and the R/W bit set to 1, and the two bytes of the last register read
out.
The broadcast address cannot be used for reading.
表7-12. Read Sequence
R/W
(0)
R/W
(1)
S
MSB
ACK MSB
LSB ACK Sr MSB
ACK MSB
LSB
ACK
MSB
LSB
ACK
…
…
…
…
…
ADDRESS
BYTE
节7.5.2.2.1
COMMAND
BYTE
节7.5.2.2.2
ADDRESS
BYTE
节7.5.2.2.1
Sr
MSDB
From Slave
LSDB
From Master
Slave
From Master
Slave
From Master
Slave
Master
From Slave
Master
7.5.3 General-Purpose Input/Output (GPIO) Modes
Together with I2C and SPI, the AFE539A4 also supports a GPIO that can be configured in the NVM for multiple
functions. This pin allows for updating the DAC output channels and reading status bits without using the
programming interface, thus enabling processor-less operation. In the GPIO-CONFIG register, write 1 to the
GPI1-EN bit to set the GPIO pin as an input, or write 1 to the GPO1-EN bit to set the pin as output. There are
global and channel-specific functions mapped to the GPIO pin. For channel-specific functions, select the
channels using the GPI1-CH-SEL field in the GPIO-CONFIG register. 表 7-13 lists the functional options
available for the GPIO as input and 表 7-14 lists the options for the GPIO as output. Some of the GP input
operations are edge-triggered after the device boots up. After the power supply ramps up, the device registers
the GPI level and executes the associated command. This feature allows the user to configure the initial output
state at power-on. By default, the GPIO pin is not mapped to any operation. Pull the GPIO pin to high or low
when not used. When the GPIO pin is mapped to a specific input function, the corresponding software bit
functionality is disabled to avoid a race condition. When used as a RESET input, the GPIO pin must transmit an
active-low pulse for triggering a device reset. All other constraints of the functions are applied to the GPIO-based
trigger.
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REGISTER
表7-13. General-Purpose Input Function Map
GPIO EDGE /
BIT FIELD
VALUE
CHANNELS
FUNCTION
LEVEL
Falling-edge
Rising-edge
Low
Trigger FAULT-DUMP
0010
All
No effect
IOUT power-down
IOUT power-up
0011
0100
As per GPI1-CH-SEL
As per GPI1-CH-SEL
High
VOUT power-down. Pulldown
resistor as per the VOUT-PDN-X
setting
Low
High
VOUT power-up
Trigger PROTECT function
No effect
Falling-edge
Rising-edge
Falling-edge
Rising-edge
Falling-edge
0101
0111
All
All
Trigger CLR function
No effect
As per GPI1-CH-SEL. Both
the SYNC-CONFIG-X and the
GPI1-CH-SEL must be
Trigger LDAC function
1000
Rising-edge
No effect
configured for every channel.
GPIO-CONFIG
GPI1-CONFIG
Falling-edge
Rising-edge
Falling-edge
Rising-edge
Stop function generation
Start function generation
Trigger margin-low
1001
1010
As per GPI1-CH-SEL
As per GPI1-CH-SEL
Trigger margin-high
Trigger device RESET. The RESET
configuration must be programmed
into the NVM
Low pulse
1011
1100
All
All
Rising-edge
Low
Brings the device out of reset
NVM programming allowed
NVM programming blocked
Write to the register map allowed
High
Low
Write to the register map blocked
except a write to the DEV-UNLOCK
field
1101
All
High
NA
Others
NA
NA
表7-14. General-Purpose Output (STATUS) Function Map
REGISTER
BIT FIELD
VALUE
0001
0100
0101
0110
FUNCTION
NVM-BUSY
DAC-0-BUSY
DAC-1-BUSY
DAC-2-BUSY
DAC-3-BUSY
WIN-CMP-0
WIN-CMP-1
WIN-CMP-2
WIN-CMP-3
NA
0111
GPIO-CONFIG
GPO1-CONFIG
1000
1001
1010
1011
Others
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7.6 Register Maps
表7-15. Register Map (NVM-SAVE-CONFIG = 0b00)
MOST SIGNIFICANT DATA BYTE (MSDB)
LEAST SIGNIFICANT DATA BYTE (LSDB)
REGISTER
BIT15
BIT14
BIT13
BIT12
BIT11
BIT10
BIT9
BIT8
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
NOP
NOP
DAC-X-MARGIN-
HIGH
DAC-X-MARGIN-HIGH
DAC-X-MARGIN-LOW
X
X
DAC-X-MARGIN-
LOW
DAC-X-VOUT-
CMP-CONFIG
CMP-X-OD-
EN
CMP-X-
OUT-EN
CMP-X-HIZ- CMP-X-INV-
X
X
VOUT-X-GAIN
X
CMP-X-EN
IN-DIS
EN
DAC-X-IOUT-
MISC-CONFIG
IOUT-X-RANGE
X
DAC-X-CMP-
MODE-CONFIG
X
CMP-X-MODE
X
DAC-X-FUNC-
CLR-SEL-X
CONFIG
SYNC-
CONFIG-X
BRD-
CONFIG-X
FUNC-GEN-CONFIG-BLOCK-X
DAC-X-DATA
DAC-X-DATA
MUX-SEL
X
ADC-CONFIG-
ADC-
CONTROLLER
X
ADC-EN
ADC-AVG
RESERVED
IOUT-
X
ADC-TRIG
ADC-DRDY
TRIG
ADC-DATA
ADC-DATA
MUX-READBACK
VOUT-PDN-0
COMMON-
CONFIG
WIN-
LATCH-EN
EE-READ-
ADDR
IOUT-
PDN-3
IOUT-
PDN-1
IOUT-
PDN-0
DEV-LOCK
EN-INT-REF
VOUT-PDN-3
VOUT-PDN-2
VOUT-PDN-1
BIT-FAULT-
PDN-2
COMMON-
TRIGGER
READ-ONE-
TRIG
NVM-
RELOAD
DEV-UNLOCK
RESET
LDAC
CLR
X
PROTECT
NVM-PROG
DUMP
COMMON-DAC-
TRIG
RST-CMP-
FLAG-0
TRIG-MAR-
LO-0
TRIG-MAR-
HI-0
START-
FUNC-0
RST-CMP- TRIG-MAR- TRIG-MAR-
START-
FUNC-1
RST-CMP- TRIG-MAR- TRIG-MAR-
FLAG-2 LO-2 HI-2
START-
FUNC-2
RST-CMP- TRIG-MAR- TRIG-MAR-
START-
FUNC-3
FLAG-1
LO-1
HI-1
FLAG-3
LO-3
HI-3
GENERAL-
STATUS
NVM-CRC-
FAIL-INT
NVM-CRC-
FAIL-USER
DAC-
BUSY-3
DAC-
BUSY-2
DAC-
BUSY-1
DAC-
BUSY-0
ADC-DRDY
NVM-BUSY
DEVICE-ID
PROTECT-
FLAG
CMP-
FLAG-3
CMP-
FLAG-2
CMP-
FLAG-1
CMP-
FLAG-0
CMP-STATUS
GPIO-CONFIG
X
WIN-CMP-3 WIN-CMP-2 WIN-CMP-1 WIN-CMP-0
GPI-CH-SEL
GF-EN
X
GPO1-EN
GPO1-CONFIG
GPI1-CONFIG
GPI1-EN
DEVICE-MODE-
CONFIG
DIS-MODE- PWM-OUT-
FULL-GPI-
EN
APP-IO-
CTL-EN
NVM-SAVE-CONFIG
FB-IN-EN
PROTECT-CONFIG
X
X
IN
EN
INTERFACE-
CONFIG
TIMEOUT-
EN
FAST-SDO-
EN
X
X
RESERVED
X
X
SDO-EN
SM-EN
STATE-MACHINE-
CONFIG0
RESERVED
SM-ABORT SM-START
SRAM-CONFIG
SRAM-DATA
X
SRAM-ADDR
SRAM-DATA
BRDCAST-DATA
BRDCAST-DATA
X
Note: Shaded cells indicate the register bits or fields that are stored in NVM.
Note: X = Don't care.
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表7-16. Register Map (NVM-SAVE-CONFIG = 0b10)
MOST SIGNIFICANT DATA BYTE (MSDB)
LEAST SIGNIFICANT DATA BYTE (LSDB)
REGISTER
BIT15
BIT14
BIT13
BIT12
BIT11
BIT10
BIT9
BIT8
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
NOP
NOP
DAC-X-MARGIN-
HIGH
DAC-X-MARGIN-HIGH
DAC-X-MARGIN-LOW
X
X
DAC-X-MARGIN-
LOW
DAC-X-VOUT-
CMP-CONFIG
CMP-X-OD-
EN
CMP-X-
OUT-EN
CMP-X-HIZ- CMP-X-INV-
IN-DIS EN
X
X
VOUT-X-GAIN
X
CMP-X-EN
DAC-X-IOUT-
MISC-CONFIG
IOUT-X-RANGE
X
DAC-X-CMP-
MODE-CONFIG
X
CMP-X-MODE
X
DAC-X-FUNC-
CONFIG
SYNC-
CONFIG-X
BRD-
CONFIG-X
CLR-SEL-X
X
FUNC-GEN-CONFIG-BLOCK-X
RESERVED
DAC-X-DATA
DAC-X-DATA
MUX-SEL
X
ADC-CONFIG-
TRIG
ADC-
CONTROLLER
ADC-EN
ADC-AVG
X
ADC-TRIG
ADC-DRDY
ADC-DATA
ADC-DATA
RESET
MUX-READBACK
VOUT-PDN-0
COMMON-
CONFIG
WIN-
LATCH-EN
DEV-LOCK
EE-READ- EN-INT-REF
ADDR
VOUT-PDN-3
IOUT-
VOUT-PDN-2
IOUT-
VOUT-PDN-1
IOUT-
IOUT-
PDN-3
PDN-2
PDN-1
PDN-0
COMMON-
TRIGGER
DEV-UNLOCK
LDAC
CLR
X
BIT-FAULT- PROTECT READ-ONE- NVM-PROG
NVM-
DUMP
TRIG
RELOAD
COMMON-DAC-
TRIG
RST-CMP-
FLAG-0
TRIG-MAR-
LO-0
TRIG-MAR-
HI-0
START-
FUNC-0
RST-CMP- TRIG-MAR- TRIG-MAR-
START-
FUNC-1
RST-CMP- TRIG-MAR- TRIG-MAR-
FLAG-2 LO-2 HI-2
START-
FUNC-2
RST-CMP- TRIG-MAR- TRIG-MAR-
START-
FUNC-3
FLAG-1
LO-1
HI-1
FLAG-3
LO-3
HI-3
GENERAL-
STATUS
NVM-CRC-
FAIL-INT
NVM-CRC-
FAIL-USER
ADC-DRDY
DAC-
BUSY-3
DAC-
BUSY-2
DAC-
BUSY-1
DAC-
BUSY-0
NVM-BUSY
DEVICE-ID
CMP-STATUS
X
PROTECT- WIN-CMP-3 WIN-CMP-2 WIN-CMP-1 WIN-CMP-0
FLAG
CMP-
FLAG-3
CMP-
FLAG-2
CMP-
FLAG-1
CMP-
FLAG-0
GPIO-CONFIG
GF-EN
X
GPO1-EN
GPO1-CONFIG
GPI-CH-SEL
GPI1-CONFIG
GPI1-EN
DEVICE-MODE-
CONFIG
NVM-SAVE-CONFIG
DIS-MODE- PWM-OUT-
FB-IN-EN
FULL-GPI-
EN
PROTECT-CONFIG
X
APP-IO-
CTL-EN
X
IN
EN
INTERFACE-
CONFIG
X
TIMEOUT-
EN
X
RESERVED
X
FAST-SDO-
EN
X
SDO-EN
SM-EN
STATE-MACHINE-
CONFIG1
RESERVED
SM-ABORT SM-START
SRAM-CONFIG
SRAM-DATA
X
SRAM-ADDR
X
SRAM-DATA
DAC-X-DATA-8BIT
BRDCAST-DATA
DAC-X-DATA-8BIT
BRDCAST-DATA
X
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表7-17. Register Names
I2C OR SPI
ADDRESS
(COMMAND
BYTE)
REGISTER NAME
SECTION
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
NOP
节7.6.1
节7.6.2
节7.6.3
节7.6.4
节7.6.5
节7.6.6
节7.6.7
节7.6.2
节7.6.3
节7.6.4
节7.6.5
节7.6.6
节7.6.7
节7.6.2
节7.6.3
节7.6.4
节7.6.5
节7.6.6
节7.6.7
节7.6.2
节7.6.3
节7.6.4
节7.6.5
节7.6.6
节7.6.7
节7.6.8
节7.6.8
节7.6.8
节7.6.8
DAC-0-MARGIN-HIGH
DAC-0-MARGIN_LOW
DAC-0-VOUT-CMP-CONFIG
DAC-0-IOUT-MISC-CONFIG
DAC-0-CMP-MODE
DAC-0-FUNC-CONFIG
DAC-1-MARGIN-HIGH
DAC-1-MARGIN_LOW
DAC-1-VOUT-CMP-CONFIG
DAC-1-IOUT-MISC-CONFIG
DAC-1-CMP-MODE
DAC-1-FUNC-CONFIG
DAC-2-MARGIN-HIGH
DAC-2-MARGIN_LOW
DAC-2-VOUT-CMP-CONFIG
DAC-2-IOUT-MISC-CONFIG
DAC-2-CMP-MODE
DAC-2-FUNC-CONFIG
DAC-3-MARGIN-HIGH
DAC-3-MARGIN_LOW
DAC-3-VOUT-CMP-CONFIG
DAC-3-IOUT-MISC-CONFIG
DAC-3-CMP-MODE
DAC-3-FUNC-CONFIG
DAC-0-DATA
DAC-1-DATA
DAC-2-DATA
DAC-3-DATA
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表7-17. Register Names (continued)
I2C OR SPI
ADDRESS
(COMMAND
BYTE)
REGISTER NAME
SECTION
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
2Bh
2Ch
50h
ADC-CONFIG-TRIG
ADC-DATA
节7.6.9
节7.6.10
节7.6.11
节7.6.12
节7.6.13
节7.6.14
节7.6.15
节7.6.16
节7.6.17
节7.6.18
节7.6.19
节7.6.20
节7.6.21
节7.6.22
COMMON-CONFIG
COMMON-TRIGGER
COMMON-DAC-TRIG
GENERAL-STATUS
CMP-STATUS
GPIO-CONFIG
DEVICE-MODE-CONFIG
INTERFACE-CONFIG
STATE-MACHINE-CONFIG0
SRAM-CONFIG
SRAM-DATA
BRDCAST-DATA
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7.6.1 NOP Register (address = 00h) [reset = 0000h]
图7-11. NOP Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOP
R/W-0h
表7-18. NOP Register Field Descriptions
Bit
15 - 0
Field
NOP
Type
Reset
Description
R/W
0000h
No operation
7.6.2 DAC-X-MARGIN-HIGH Register (address = 01h, 07h, 0Dh, 13h) [reset = 0000h]
图7-12. DAC-X-MARGIN-HIGH Register (X = 0, 1, 2, 3)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DAC-X-MARGIN-HIGH[9:0]
R/W-0h
X
X-0h
表7-19. DAC-X-MARGIN-HIGH Register Field Descriptions
Bit
15 - 4
Field
Type
Reset
Description
DAC-X-MARGIN-HIGH[9:0]
R/W
000h
Margin-high code for DAC output
Data are in straight-binary format. MSB left-aligned.
Use the following bit-alignment:
AFE539A4: {DAC-X-MARGIN-HIGH[9:0], X, X}
X = Don't care bits.
3 - 0
X
X
0
Don't care
7.6.3 DAC-X-MARGIN-LOW Register (address = 02h, 08h, 0Eh, 14h) [reset = 0000h]
图7-13. DAC-X-MARGIN-LOW Register (X = 0, 1, 2, 3)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DAC-X-MARGIN-LOW[9:0]
R/W-0h
X
X-0h
表7-20. DAC-X-MARGIN-LOW Register Field Descriptions
Bit
15 - 4
Field
Type
Reset
Description
DAC-X-MARGIN-LOW[9:0]
R/W
000h
Margin-low code for DAC output
Data are in straight-binary format. MSB left-aligned.
Use the following bit-alignment:
AFE539A4: {DAC-X-MARGIN-LOW[9:0], X, X}
X = Don't care bits.
3 - 0
X
X
0
Don't care
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7.6.4 DAC-X-VOUT-CMP-CONFIG Register (address = 03h, 09h, 0Fh, 15h) [reset = 0000h]
图7-14. DAC-X-VOUT-CMP-CONFIG Register (X = 0, 1, 2, 3)
15
14
X
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VOUT-GAIN-X
X
CMP-X- CMP-X- CMP-X- CMP-X- CMP-X-
OD-EN OUT-EN HIZ-IN- INV-EN
DIS
EN
X-0h
R/W-0h
X-0h
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
表7-21. DAC-X-VOUT-CMP-CONFIG Register Field Descriptions
Bit
15 - 13
12 - 10 VOUT-GAIN-X
Field
Type
Reset
Description
X
X
0h
Don't care
R/W
0h
000: Gain = 1x, external reference on VREF pin.
001: Gain = 1x, VDD as reference.
010: Gain = 1.5x, internal reference.
011: Gain = 2x, internal reference.
100: Gain = 3x, internal reference.
101: Gain = 4x, internal reference.
Others: NA.
9 - 5
4
X
X
0h
0
Don't care
CMP-X-OD-EN
R/W
1: Set OUTx pin as open-drain in comparator mode (CMP-X-EN =
1 and CMP-X-OUT-EN = 1).
0: Set OUTx pin as push-pull.
3
2
CMP-X-OUT-EN
R/W
R/W
0
0
1: Bring comparator output to the respective OUTx pin.
0: Generate comparator output but consume internally.
CMP-X-HIZ-IN-DIS
1: FBx input has high-impedance. Input voltage range is limited.
0: FBx input is connected to resistor divider and has finite
impedance. Input voltage range is same as full-scale.
1
0
CMP-X-INV-EN
CMP-X-EN
R/W
R/W
0
0
1: Invert the comparator output.
0: Don't invert the comparator output.
1: Enable comparator mode. Current-output must be in power-
down.
0: Disable comparator mode.
7.6.5 DAC-X-IOUT-MISC-CONFIG Register (address = 04h, 0Ah, 10h, 16h) [reset = 0000h]
图7-15. DAC-X-IOUT-MISC-CONFIG Register (X = 0, 1, 2, 3)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
IOUT-RANGE-X
R/W-0h
X
X-0h
X-0h
表7-22. DAC-X-IOUT-MISC-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15 - 13
12 - 9
X
X
0h
Don't care.
IOUT-RANGE-X
R/W
0000
1000: -25 μA to +25 μA
1001: -50 μA to +50 μA
1010: -125 μA to +125 μA
1011: -250 μA to +250 μA
Others: NA.
8 - 0
X
X
000h
Don't care.
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7.6.6 DAC-X-CMP-MODE-CONFIG Register (address = 05h, 0Bh, 11h, 17h) [reset = 0000h]
图7-16. DAC-X-CMP-MODE-CONFIG Register (X = 0, 1, 2, 3)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
CMP-X-MODE
R/W-0h
X
X-0h
X-0h
表7-23. DAC-X-CMP-MODE-CONFIG Register Field Descriptions
Bit
15 - 12
11 - 10 CMP-X-MODE
Field
Type
Reset
00h
00
Description
X
X
Don't care.
R/W
00: No hysteresis or window function.
01: Hysteresis provided using DAC-X-MARGIN-HIGH and DAC-
X-MARGIN-LOW registers.
10: Window comparator mode with DAC-X-MARGIN-HIGH and
DAC-X-MARGIN-LOW registers setting window bounds.
11: Invalid setting.
9 - 0
X
X
000h
Don't care.
7.6.7 DAC-X-FUNC-CONFIG Register (address = 06h, 0Ch, 12h, 18h) [reset = 0000h]
图7-17. DAC-X-FUNC-CONFIG Register (X = 0, 1, 2, 3) for Linear Slew-Rate Setting
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CLR-SEL-X
SYNC-
BRD-
FUNC-GEN-CONFIG-BLOCK
CONFIG-X CONFIG-X
R/W-0h
R/W-0h R/W-0h
R/W-0h
表7-24. DAC-X-FUNC-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
CLR-SEL-X
R/W
0
0: Clear DAC-X to zero-scale.
1: Clear DAC-X to mid-scale.
14
13
SYNC-CONFIG-X
R/W
R/W
0
0
0: DAC-X output updates immediately after a write command.
1: DAC-X output updates with LDAC pin falling-edge or when the
LDAC bit in the COMMON-TRIGGER register is set to 1.
BRD-CONFIG-X
0: Don't update DAC-X with broadcast command.
1: Update DAC-X with broadcast command.
表7-25. Linear-Slew Mode: FUNC-GEN-CONFIG-BLOCK Field Descriptions
Bit
Field
Type
Reset
Description
12 - 11 PHASE-SEL-X
R/W
0
00: 0 degree.
01: 120 degree.
10: 240 degree.
11: 90 degree.
10 - 8
FUNC-CONFIG-X
R/W
0
000: Triangular wave.
001: Sawtooth wave.
010: Inverse sawtooth wave.
100: Sine wave.
111: Disable function generation.
Others: Invalid.
7
LOG-SLEW-EN-X
CODE-STEP-X
R/W
R/W
0
0
0: Enable linear slew.
6 - 4
CODE-STEP for linear-slew mode:
000: 1-LSB.
001: 2-LSB.
010: 3-LSB.
011: 4-LSB.
100: 6-LSB.
101: 8-LSB.
110: 16-LSB.
111: 32-LSB.
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表7-25. Linear-Slew Mode: FUNC-GEN-CONFIG-BLOCK Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3 - 0
SLEW-RATE-X
R/W
0
SLEW-RATE for logarithmic-slew mode:
0000: No slew for margin-high and margin-low. Invalid for
waveform generation.
0001: 4 µs/step.
0010: 8 µs/step.
0011: 12 µs/step.
0100: 18 µs/step.
0101: 27.04 µs/step.
0110: 40.48 µs/step.
0111: 60.72 µs/step.
1000: 91.12 µs/step.
1001: 136.72 µs/step.
1010: 239.2 µs/step.
1011: 418.64 µs/step.
1100: 732.56 µs/step.
1101: 1282 µs/step.
1110: 2563.92 µs/step.
1111: 5127.92 µs/step.
表7-26. Logarithmic-Slew Mode: FUNC-GEN-CONFIG-BLOCK Field Descriptions
Bit
Field
Type
Reset
Description
12 - 11
PHASE-SEL-X
R/W
0
00: 0 degree.
01: 120 degree.
10: 240 degree.
11: 90 degree.
10 - 8
FUNC-CONFIG-X
R/W
0
000: Triangular wave.
001: Sawtooth wave.
010: Inverse sawtooth wave.
100: Sine wave.
111: Disable function generation.
Others: Invalid.
7
LOG-SLEW-EN-X
RISE-SLEW-X
R/W
R/W
0
0
1: Enable logarithmic slew.
6 - 4
SLEW-RATE for log-slew mode:
000: 4 µs/step.
001: 12 µs/step.
010: 27.04 µs/step.
011: 60.72 µs/step.
100: 136.72 µs/step.
101: 418.64 µs/step.
110: 1282 µs/step.
111: 5127.92 µs/step.
3 - 1
FALL-SLEW-X
R/W
0
SLEW-RATE for log-slew mode:
000: 4 µs/step.
001: 12 µs/step.
010: 27.04 µs/step.
011: 60.72 µs/step.
100: 136.72 µs/step.
101: 418.64 µs/step.
110: 1282 µs/step.
111: 5127.92 µs/step.
0
X
X
0
Don't care.
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表7-27. State Machine Mode: Channel-0 FUNC-GEN-CONFIG-BLOCK Field Descriptions
Bit
Field
Type
Reset
Description
12 - 10
9 - 0
RESERVED
SETPOINT
X
0
Always write 0.
R/W
0x200
Run-time set-point location for PI controller.
表7-28. State Machine Mode: Channel-1 FUNC-GEN-CONFIG-BLOCK Field Descriptions
Bit
12
Field
Type
Reset
Description
RESERVED
COMMON-MODE
RESERVED
X
0
Always write 0.
11 - 2
1 - 0
R/W
X
0x1FF
0
Run-time common-mode location for PI controller.
Always write 0.
表7-29. State Machine Mode: Channel-3 FUNC-GEN-CONFIG-BLOCK Field Descriptions
Bit
12
Field
Type
Reset
Description
RESERVED
PI-OUTPUT
RESERVED
X
0
Always write 0.
11 - 2
1 - 0
R
0x000
0
Run-time PI controller output location.
Always write 0.
X
表7-30. State Machine Mode: Channel-3 FUNC-GEN-CONFIG-BLOCK Field Descriptions
Bit
Field
Type
Reset
Description
12 - 10
9 - 0
RESERVED
SENSED-DATA
X
0
Always write 0.
R/W
0x000
Run-time sensed data location for PI controller.
7.6.8 DAC-X-DATA Register (address = 19h, 1Ah, 1Bh, 1Ch) [reset = 0000h]
图7-18. DAC-X-DATA Register (X = 0, 1, 2, 3)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DAC-X-DATA[9:0]
R/W-0h
X
X-0h
表7-31. DAC-X-DATA Register Field Descriptions
Bit
15 - 4
Field
DAC-X-DATA[9:0]
Type
Reset
Description
R/W
000h
Data for DAC output
Data are in straight-binary format. MSB left-aligned. Use the
following bit-alignment:
AFE539A4: {DAC-X-DATA[9:0], X, X}
X = Don't care bits.
3 - 0
X
X
0h
Don't care.
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7.6.9 ADC-CONFIG-TRIG Register (address = 1Dh) [reset = 0000h]
图7-19. ADC-CONFIG-TRIG Register
15
X
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADC-
CONTROLL
ER
ADC-EN
ADC-AVG
MUX-SEL
RESERVED
X
ADC-
TRIG
X-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
X-0h
W-0h
表7-32. ADC-CONFIG-TRIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
14
X
X
0
0
Don't care.
ADC-CONTROLLER
R/W
0: ADC is controlled by the communication interface
1: ADC is controlled by the state-machine.
13
ADC-EN
R/W
R/W
0
0: ADC disabled.
1: ADC enabled.
12 - 11 ADC-AVG
00
Number of ADC samples to be averaged:
00: 4
01: 8
10: 16
11: 32
10 - 8
MUX-SEL
R/W
000
000: ADC0 in Hi-Z input mode.
001: ADC1 in Hi-Z input mode.
010: ADC2 in Hi-Z input mode.
011: ADC3 in Hi-Z input mode.
100: ADC0 in finite-impedance input mode.
101: ADC1 in finite-impedance input mode.
110: ADC2 in finite-impedance input mode.
111: Invalid.
7 - 5
4 - 1
0
RESERVED
X
R/W
R/W
W
0h
0h
0
Always write 110b.
Don't care.
ADC-TRIG
0: Don't care.
1: Trigger ADC. This bit is auto-resetting.
Note
Before setting the ADC-TRIG bit:
•
•
•
Set ADC-EN to 1.
Configure the reference and gain for channel-3.
Configure channel-3 as a comparator.
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7.6.10 ADC-DATA Register (address = 1Eh) [reset = 0000h]
图7-20. ADC-DATA Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADC-DATA[9:0]
MUX-READBACK
ADC-
DRDY
R-0h
R-0h
R-0h
表7-33. ADC-DATA Register Field Descriptions
Bit
15 - 4
Field
Type
Reset
Description
ADC-DATA[9:0]
R
000h
Data readback from ADC
Data are in straight-binary format. MSB left-aligned. Use the
following bit-alignment:
AFE539A4: {ADC-DATA[9:0], X, X}
X = Don't care bits.
3 - 1
MUX-READBACK
R
0h
000: ADC0 in Hi-Z input mode.
001: ADC1 in Hi-Z input mode.
010: ADC2 in Hi-Z input mode.
011: ADC3 in Hi-Z input mode.
100: ADC0 in finite-impedance input mode.
101: ADC1 in finite-impedance input mode.
110: ADC2 in finite-impedance input mode.
111: Invalid.
0
ADC-DRDY
R
0
0: ADC conversion in progress. ADC-DATA is invalid.
1: ADC conversion complete. ADC-DATA is valid.
7.6.11 COMMON-CONFIG Register (address = 1Fh) [reset = 1249h]
图7-21. COMMON-CONFIG Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WINDO
W-
DEV-
LOCK
EE-READ- EN-INT-
VOUT-PDN-3
IOUT-
PDN-3
VOUT-PDN-2
IOUT-
PDN-2
VOUT-PDN-1
IOUT-
PDN-1
VOUT-PDN-0
IOUT-
PDN-0
ADDR
REF
LATCH-
EN
R/W-0h R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
表7-34. COMMON-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
WINDOW-LATCH-EN
DEV-LOCK
R/W
0
0: Non-latching window-comparator output.
1: Latching window-comparator output
14
R/W
0
0 : Device not locked
1: Device locked, the device locks all the registers. To set this bit
back to 0 (unlock device), write to the unlock code to the DEV-
UNLOCK field in the COMMON-TRIGGER register first, followed
by a write to the DEV-LOCK bit as 0.
13
12
EE-READ-ADDR
EN-INT-REF
R/W
R/W
0
0: Fault-dump read enable at address 0x00.
1: Fault-dump read enable at address 0x01.
000
0: Disable internal reference
1: Enable internal reference. This bit must be set before using
internal reference gain settings.
11 - 10, 8 - VOUT-PDN-X
7, 5 - 4, 2 -
1
R/W
R/W
11
1
00: Power-up VOUT-X.
01: Power-down VOUT-X with 10 KΩto AGND.
10: Power-down VOUT-X with 100 KΩto AGND.
11: Power-down VOUT-X with Hi-Z to AGND.
9, 6, 3, 0 IOUT-PDN-X
0: Power-up IOUT-X.
1: Power-down IOUT-X
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7.6.12 COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
图7-22. COMMON-TRIGGER Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DEV-UNLOCK
RESET
LDAC
CLR
X
FAULT- PROTECT
DUMP
READ-
ONE-
TRIG
NVM-
PROG RELOAD
NVM-
R/W-0h
R/W-0h
R/W-0h
R/W-0h
X-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h R/W-0h
表7-35. COMMON-TRIGGER Register Field Descriptions
Bit
Field
Type
Reset
Description
15 - 12 DEV-UNLOCK
R/W
0000
0101: Device unlocking password.
Others: Don't care.
11 - 8
7
RESET
LDAC
W
0000
0
1010 : POR reset triggered. This field is self-resetting.
Others: Don't care.
R/W
0: LDAC operation not triggered.
1: LDAC operation triggered if the respective SYNC-CONFIG-X
bit in the DAC-X-FUNC-CONFIG register is 1. This bit is self-
resetting.
6
CLR
R/W
0
0: DAC registers and outputs unaffected.
1: DAC registers and outputs set to zero-code or mid-code based
on the respective CLR-SEL-X bit in the DAC-X-FUNC-CONFIG
register. This bit is self-resetting.
5
4
X
X
0
0
Don't care.
FAULT-DUMP
R/W
0: Fault-dump is not triggered.
1: Triggers fault-dump sequence. This bit is self-resetting.
3
2
1
0
PROTECT
R/W
R/W
R/W
R/W
0
0
0
0
0: PROTECT function not triggered.
1: Trigger PROTECT function. This bit is self-resetting.
READ-ONE-TRIG
NVM-PROG
0: Fault-dump read not triggered.
1: Read one row of NVM for fault-dump. This bit is self-resetting.
0: NVM write not triggered.
1: NVM write triggered. This bit is self-resetting.
NVM-RELOAD
0: NVM reload not triggered.
1: Reload data from NVM to register map. This bit is self-
resetting.
7.6.13 COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
图7-23. COMMON-DAC-TRIG Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET- TRIG- TRIG-MAR-
START- RESET TRIG- TRIG- START- RESET TRIG- TRIG- START- RESET
TRIG-
TRIG- START-
CMP-
FLAG-0
MAR-
LO-0
HI-0
FUNC-0 -CMP- MAR- MAR- FUNC- -CMP- MAR-
MAR- FUNC- -CMP- MAR-LO-3 MAR- FUNC-
FLAG-
1
LO-1
HI-1
1
FLAG-
2
LO-2
HI-2
2
FLAG-
2
HI-3
3
W-0h
W-0h
W-0h
R/W-0h
W-0h
W-0h
W-0h R/W-0h W-0h
W-0h
W-0h R/W-0h W-0h
W-0h
W-0h R/W-0h
表7-36. COMMON-DAC-TRIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15 , 11, 7, RESET-CMP-FLAG-X
3
W
0
0: Latching-comparator output unaffected.
1: Reset latching-comparator output. This bit is self-resetting.
14, 10, 6, TRIG-MAR-LO-X
2
W
0
0
0
0: Don't care.
1: Trigger margin-low command. This bit is self-resetting.
13, 9, 5, 1 TRIG-MAR-HI-X
W
0: Don't care.
1: Trigger margin-high command. This bit is self-resetting.
12, 8, 4, 0 START-FUNC-X
R/W
0: Stop function generation.
1: Start function generation as per FUNC-GEN-CONFIG-X in the
DAC-X-FUNC-CONFIG register.
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7.6.14 GENERAL-STATUS Register (address = 22h) [reset = TBD]
图7-24. GENERAL-STATUS Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NVM-
CRC-
FAIL-
INT
NVM-
CRC-
FAIL-
USER
ADC-DRDY
DAC-3- DAC-2- DAC-1- DAC-0-
X
DEVICE-ID
BUSY
R-0h
BUSY BUSY BUSY
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
X-0h
R-0h
表7-37. GENERAL-STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
15
NVM-CRC-FAIL-INT
R
0
0: No CRC error in OTP.
1: Indicates a failure in OTP loading. A software reset or power-
cycle can bring the device out of this condition in case of
temporary failure.
14
NVM-CRC-FAIL-USER
R
0
0: No CRC error in NVM loading.
1: Indicates a failure in NVM loading. The register settings are
corrupted. The device allows all operations during this error
condition. Reprogram the NVM to get original state. A software
reset brings the device out of this error condition.
13
12
11
10
9
ADC-DRDY
DAC-3-BUSY
DAC-2-BUSY
DAC-1-BUSY
DAC-0-BUSY
NVM-BUSY
DEVICE-ID
R
R
R
R
R
R
R
0
0: ADC conversion is not in progress.
1: ADC conversion in progress. ADC data is invalid.
0
0: DAC-3 channel can accept commands.
1: DAC-3 channel doesn't accept commands.
0
0: DAC-2 channel can accept commands.
1: DAC-2 channel doesn't accept commands.
0
0: DAC-1 channel can accept commands.
1: DAC-1 channel doesn't accept commands.
0
0: DAC-0 channel can accept commands.
1: DAC-0 channel doesn't accept commands.
8
0
0: NVM is available for read and write.
1: NVM is not available for read or write.
7 - 0
TBD
Device identifier:
AFE539A4: 1Ch
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7.6.15 CMP-STATUS Register (address = 23h) [reset = 0000h]
图7-25. CMP-STATUS Register
15
14
13
12
X
11
10
9
8
7
6
5
4
3
2
1
0
PROTECT- WIN- WIN- WIN- WIN- CMP- CMP- CMP- CMP-
FLAG
CMP-3 CMP-2 CMP-1 CMP-0 FLAG- FLAG- FLAG- FLAG-
3
2
1
0
X-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
表7-38. CMP-STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
15 - 9
8
X
X
0
0
Don't care.
PROTECT-FLAG
R
0 : PROTECT operation not triggred or in progress.
1: PROTECT function is completed. This bit resets to 0 when
read.
7, 6, 5, 4 WIN-CMP-X
3, 2, 1, 0 CMP-FLAG-X
R
R
0
0
Window comparator output from respective channels. The output
is latched or unlatched based on the WINDOW-LATCH-EN
setting in the COMMON-CONFIG register.
Synchronized comparator output from respective channels.
7.6.16 GPIO-CONFIG Register (address = 24h) [reset = 0000h]
图7-26. GPIO-CONFIG Register
15
14
X
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GF-EN
GPO1-
EN
GPO1-CONFIG
R/W-0h
GPI1-CH-SEL
R/W-0h
GPI1-CONFIG
GPI1-EN
R/W-0h
X-0h
R/W-0h
R/W-0h
R/W-0h
表7-39. GPIO-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
GF-EN
R/W
0
0: Glitch filter disabled for GP input. This setting provides faster
response.
1: Glitch filter enabled for GPI. This setting introduces additional
propagation delay but provides robustness.
14
13
X
X
0
0
Don't care.
GPO1-EN
R/W
0: Disable output mode for GPIO pin.
1: Enable output mode for GPIO pin.
12 - 9
GPO1-CONFIG
R/W
0000
STATUS function setting. The GPIO pin is mapped to the
following register bits as output:0000: ADC-DRDY
0001: NVM-BUSY
0100: DAC-0-BUSY
0101: DAC-1-BUSY
0110: DAC-2-BUSY
0111: DAC-3-BUSY
1000: WIN-CMP-0
1001: WIN-CMP-1
1010: WIN-CMP-2
1011:WIN-CMP-3
Others: NA
8 - 5
GPI1-CH-SEL
R/W
0000
Each bit corresponds to a DAC channel. 0b is disabled and 1b is
enabled.
GPI1-CH-SEL[0]: Channel 0
GPI1-CH-SEL[1]: Channel 1
GPI1-CH-SEL[2]: Channel 2
GPI1-CH-SEL[3]: Channel 3
Example: when GPI1-CH-SEL is 0101, both channel-0 and
channel-2 are enabled and both channel-1 and channel-3 are
disabled.
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表7-39. GPIO-CONFIG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
4 - 1
GPI1-CONFIG
R/W
0000
GPIO pin input configuration. Global settings act on the entire
device. Channel-specific settings are dependent on the channel
selection by the GPI1-CH-SEL bits:
0010: FAULT-DUMP (global). GPIO falling-edge triggers fault-
dump, GPIO = 1 has no effect.
0011: IOUT power-up, down (channel-specific). GPIO = 0 is
power-down, GPIO = 1 is power-up.
0100: VOUT power-up/down (channel-specific). The output load
is as per the VOUT-PDN-X setting. GPIO = 0 is power-down,
GPIO = 1 is power-up.
0101: PROTECT input (global). GPIO falling-edge asserts
PROTECT function, GPIO = 1 has no effect.
0111: CLR input (global). GPIO = 0 asserts CLR function, GPIO =
1has no effect.
1000: LDAC input (channel-specific). GPIO falling-edge asserts
LDAC function, GPIO = 1 has no effect. Both the SYNC-CONFIG-
X and the GPI1-CH-SEL must be configured for every channel.
1001: Start, stop function generation (channel-specific). GPIO
falling-edge stops function generation. GPIO rising-edge starts
function generation.
1010: Trigger margin-high, low (channel-specific). GPIO falling-
edge triggers margin-low. GPIO rising-edge triggers margin-high.
1011:RESET input (global). The falling-edge of the GPIO pin
asserts the RESET function. The RESET input must be a pulse.
The GPIO rising-edge brings the device out of reset. The RESET
configuration must be programmed into the NVM. Otherwise the
setting will be cleared after the device reset.
1100: NVM write-protection (global). GPIO falling-edge allows
NVM programming. GPIO = 1 blocks NVM programming.
1101: Register-map lock (global). GPIO = 0 allows update to the
register map. GPIO = 1 blocks any register map update except a
write to the DEV-UNLOCK field.
Others: NA
0
GPI1-EN
R/W
0
0: Disable input mode for GPIO pin.
1: Enable input mode for GPIO pin.
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7.6.17 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 0000h]
图7-27. DEVICE-MODE-CONFIG Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
DIS-
MODE-IN
RESERVED
PROTECT-
CONFIG
RESERVED
X
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
X-0h
表7-40. DEVICE-MODE-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15 - 14 RESERVED
R/W
00
00: Register map saved in the NVM as per 表7-15.
01: Register map saved in the NVM as per 表7-16.
Others: Invalid.
13
DIS-MODE-IN
R/W
0
0: MODE function enabled.
1: MODE function disabled.
12 - 10 RESERVED
R/W
R/W
0
Always write 0b000.
9 - 8
PROTECT-CONFIG
00
00: Switch to power-down (no slew).
01: Switch to DAC code stored in NVM (no slew) and then switch
to power-down.
10: Slew to margin-low code and then switch to power-down.
11: Slew to margin-high code and then switch to power-down.
7 - 5
4 - 0
RESERVED
X
R/W
R/W
0
Always write 0b000.
Don't care.
00h
7.6.18 INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
图7-28. INTERFACE-CONFIG Register
15
14
X
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TIMEOUT-
EN
X
FSDO-
EN
X
SDO-EN
X-0h
R/W-0h
X-0h
R/W-0h X-0h
R/W-0h
表7-41. INTERFACE-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15 - 13
12
X
X
0h
Don't care.
TIMEOUT-EN
R/W
0
0: I2C timeout disabled.
1: I2C timeout enabled.
11 - 3
2
X
X
0h
0
Don't care.
FSDO-EN
R/W
0: Fast SDO disabled.
1: Fast SDO enabled.
1
0
X
X
0
0
Don't care.
SDO-EN
R/W
0: SDO disabled.
1: SDO enabled on GPIO pin.
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7.6.19 STATE-MACHINE-CONFIG0 Register (address = 27h) [reset = 0000h]
图7-29. STATE-MACHINE-CONFIG0 Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
R/W-0h
SM-
SM-
SM-EN
ABORT START
R/W-0h R/W-0h R/W-0h
表7-42. STATE-MACHINE-CONFIG0 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
0000h
0
Description
15 - 3
2
RESERVED
SM-ABORT
Always write 0.
0: State machine not aborted.
1: State machine aborted.
1
0
SM-START
SM-EN
R/W
R/W
0
0
0: State machine stopped.
1: State machine started. The state machine must be enabled
using the SM-EN bit.
0: State machine disabled.
1: State machine enabled.
7.6.20 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
图7-30. SRAM-CONFIG Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
SRAM-ADDR
R/ W-0h
X-0h
表7-43. SRAM-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15 - 8
7 - 0
X
X
0h
Don't care.
SRAM-ADDR
R/W
0h
8-bit SRAM address. Writing to this register field configures the
SRAM address to be accessed next. This address automatically
increments after a read or write from the SRAM.
7.6.21 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
图7-31. SRAM-DATA Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRAM-DATA
R/ W-0h
表7-44. SRAM-DATA Register Field Descriptions
Bit
15 - 0
Field
SRAM-ADDR
Type
Reset
Description
R/W
0h
16-bit SRAM data. This data is written to or read from the address
configured in the SRAM-CONFIG register.
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7.6.22 BRDCAST-DATA Register (address = 50h) [reset = 0000h]
图7-32. BRDCAST-DATA Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BRDCAST-DATA[9:0]
R/W-0h
X
X-0h
表7-45. BRDCAST-DATA Register Field Descriptions
Bit
15 - 4
Field
BRDCAST-DATA[9:0]
Type
Reset
Description
R/W
000h
Broadcast code for all DAC channels
Data are in straight-binary format. MSB left-aligned. Use the
following bit-alignment:
AFE539A4: {BRDCAST-DATA[9:0], X, X}
X = Don't care bits.
The BRD-CONFIG-X bit in the DAC-X-FUNC-CONFIG register
must be enabled for the respective channels.
3 - 0
X
X
0h
Don't care.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
Follow these guidelines for best performance of the AFE539A4:
• In voltage-output mode, short the OUTx and FBx pins for each channel.
• In current-output mode, leave the FBx pins unconnected.
• The FBx pins function as inputs in comparator mode. Connect FB3 to VDD using a pullup resistor in the ADC
mode.
• Configure as a comparator each channel that is intended to be used as an ADC.
• Configure ADC3 as a comparator even when other channels are used as ADCs.
• The external reference must not exceed VDD, either during transient or steady-state conditions.
• For the best Hi-Z output performance, use a pullup resistor on the VREF pin to VDD. In case the VDD
remains floating during the off condition, place a 100-kΩresistor to AGND for proper detection of the VDD off
condition.
• All the digital outputs are open drain; use external pullup resistors on these pins.
• The interface protocol is detected at power on, and the device locks to the protocol as long as VDD is on.
• When allocating the I2C addresses in the system in I2C mode, consider the broadcast address as well.
• I2C timeout can be enabled for robustness.
• SPI mode is three-wire by default.
• Configure the GPIO pin as SDO in the NVM for SPI readback capability.
• The SPI clock speed in readback mode is slower than that in write mode.
• Power-down mode sets the DAC outputs in Hi-Z by default. Change the configuration appropriately for
different power-down settings.
• The DAC channels can also power-up with a programmed DAC code in the NVM.
• This device enables the state-machine by default. Stop the state-machine when the device is intended to be
used as an independent DAC or ADC.
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8.2 Typical Application
A thermoelectric cooling (TEC) circuit is used in many applications, such as laser diode cooling, medical blood
analysis and thermal-cycling, central-processing unit (CPU) cooling, portable refrigeration, automotive seat
heating, and more. A TEC element is controlled by controlling the voltage across the TEC element using a PI
controller. This application example extends the circuit explained in the Low-Power TEC Driver application
report. The complete circuit diagram is as shown in 图8-1.
图8-1. TEC Control
8.2.1 Design Requirements
表8-1. Design Parameters
PARAMETER
Measured temperature range
AFE output-voltage range
Temperature set point
Steady-state error
VALUE
–55ºC to +150ºC
0 V to 1.8 V
30ºC
< ±0.5ºC
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8.2.2 Detailed Design Procedure
This design example uses the TPS63020, a buck-boost converter, and connects the TEC element between the
VIN and VOUT nodes to create bidirectional voltage control of the TEC element. The control voltage to the
TPS63020 must be between 0 V and 1.8 V to achieve the full range of TEC current. As shown in 图 8-1, the
temperature is measured using the LMT70, a high-precision, analog temperature sensor. The LMT70 provides a
voltage output between 1.38 V and 300 mV for the temperature range of –55ºC to +125ºC. Therefore, configure
the PI controller output (DAC1) with the internal reference and a gain of 1.5x. Similarly, configure ADC0 to be in
Hi-Z input mode (ADC0-MODE = 0), with the internal reference, and 4x gain. This configuration sets ADC0 at a
full-scale input (VFS) range of (1.21 V * 4x) / 3 = 1.613 V. With 10-bit resolution, 1 LSB of ADC0 code
corresponds to (1.613 V / 1024) = 1.58 mV. The response slope of the LMT70 at 30ºC is 5.194 mV/ºC.
Therefore, 1 LSB of the ADC0 corresponds to (1.58 / 5.194) = 0.3ºC.
The voltage output of the LMT70 corresponding to the temperature set point of 30ºC is 943.227 mV. Using 方程
式 5, calculate the SETPOINT input as 598d (0x256). For negative feedback, use an odd number of phase
inversions in the feedback loop. The DAC1 output to the TPS63020 output has one phase inversion; the
TPS63020 decreases when the DAC1 output increases. The TPS63020 output and the TEC cold-side
temperature have the second phase inversion; the TEC cold-side temperature decreases when the TPS63020
output increases. The TEC cold-side and the LMT70 have the third phase inversion; when the TEC cold-side
temperature decreases, the LMT70 output voltage increases. The external loop of the AFE539A4 has an odd
number of phase inversions; therefore, make sure that the internal PI control loop has no phase inversion. To
prevent the phase inversion, configure LOOP-POLARITY = 1. Choose the values of RF and CF in 图 8-1 based
on the noise level present in the sensing circuit.
When the output of the comparator is low, the PI controller output enters safe mode. Therefore, the current
sense amplifier and the comparator setting must be configured to trigger safe mode at the desired TEC current
limit.
Follow the procedure described in 节7.4.5.2 to configure the parameters listed in 表8-2.
表8-2. PI Controller Parameters
REGISTER FIELD
NNAME
STATIC ADDRESS
LOCATION
CONFIGURED
VALUE (16-BIT)
DYNAMIC ADDRESS
LOCATION
STATIC ADDRESS
DYNAMIC ADDRESS
SETPOINT
0x22[9:0]
0x23[15:0]
0x26[15:0]
0x20[15:6]
0x21[15:6]
0x25[11:2]
0x27[0]
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
0x0256
0x0FA0
0x0001
0xFFC0
0x0000
0x7FC0
0x0001
0x0000
0x0002
0x7FC0
0x06[9:0]
N/A
Register
N/A
KP
KI
N/A
N/A
MAX-OUTPUT
MIN-OUTPUT
COMMON-MODE
LOOP-POLARITY
SAFE-OUTPUT
ADC0-MODE
CMP2-THRESHOLD
N/A
N/A
N/A
N/A
0x0C[11:2]
N/A
Register
N/A
0x27[15:6]
0x27[1]
N/A
N/A
N/A
N/A
0x24[15:6]
N/A
N/A
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9 Power Supply Recommendations
The AFE539A4 does not require specific power-supply sequencing. These devices require a single power
supply, VDD. However, make sure the external voltage reference is applied after VDD. Use a 0.1-µF decoupling
capacitor for the VDD pin. Use a bypass capacitor with a value approximately 1.5 µF for the CAP pin.
10 Layout
10.1 Layout Guidelines
The AFE539A4 pin configuration separates the analog, digital, and power pins for an optimized layout. For
signal integrity, separate the digital and analog traces, and place decoupling capacitors close to the device pins.
10.2 Layout Example
图10-1. Layout Example
Note: The ground and power planes have been omitted for clarity. Connect the thermal pad to ground.
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11 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
11.1 Documentation Support
11.1.1 Related Documentation
The following documentation is available: AFE539A4 Evaluation Module user's guide
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PAFE539A4RTET
ACTIVE
WQFN
RTE
16
250
TBD
Call TI
Call TI
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
GENERIC PACKAGE VIEW
RTE 16
3 x 3, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225944/A
www.ti.com
PACKAGE OUTLINE
RTE0016C
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
SIDE WALL
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
C
0.8 MAX
SEATING PLANE
0.08
0.05
0.00
1.68 0.07
(DIM A) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
17
1.5
1
12
0.30
16X
0.18
PIN 1 ID
(OPTIONAL)
13
16
0.1
C A B
SYMM
0.05
0.5
0.3
16X
4219117/B 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RTE0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.68)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
(2.8)
17
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
8
(R0.05)
ALL PAD CORNERS
(0.58) TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219117/B 04/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTE0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.55)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4219117/B 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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